VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp@ 84678

Last change on this file since 84678 was 84678, checked in by vboxsync, 5 years ago

AMD IOMMU: bugref:9654 Build fix.
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1/* $Id: PDMR0DevHlp.cpp 84678 2020-06-04 13:26:18Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device Helper parts.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/vmcc.h>
32#include <VBox/vmm/gvmm.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/ctype.h>
40#include <iprt/string.h>
41
42#include "dtrace/VBoxVMM.h"
43#include "PDMInline.h"
44
45
46/*********************************************************************************************************************************
47* Global Variables *
48*********************************************************************************************************************************/
49RT_C_DECLS_BEGIN
50extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
51extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
52extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp;
53extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
54extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp;
55extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
56extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
57RT_C_DECLS_END
58
59
60/*********************************************************************************************************************************
61* Internal Functions *
62*********************************************************************************************************************************/
63
64
65/** @name Ring-0 Device Helpers
66 * @{
67 */
68
69/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
70static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
71 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
72 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
73 void *pvUser)
74{
75 PDMDEV_ASSERT_DEVINS(pDevIns);
76 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
77 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
78 PGVM pGVM = pDevIns->Internal.s.pGVM;
79 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
80 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
81
82 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
83
84 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
85 return rc;
86}
87
88
89/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
90static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
91 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
92{
93 PDMDEV_ASSERT_DEVINS(pDevIns);
94 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
95 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
96 PGVM pGVM = pDevIns->Internal.s.pGVM;
97 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
98 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
99
100 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
101
102 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
103 return rc;
104}
105
106
107/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
108static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
109 size_t offSub, size_t cbSub, void **ppvMapping)
110{
111 PDMDEV_ASSERT_DEVINS(pDevIns);
112 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
113 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
114 *ppvMapping = NULL;
115
116 PGVM pGVM = pDevIns->Internal.s.pGVM;
117 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
118 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
119
120 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
121
122 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
123 return rc;
124}
125
126
127/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
128static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
129 void *pvBuf, size_t cbRead, uint32_t fFlags)
130{
131 PDMDEV_ASSERT_DEVINS(pDevIns);
132 if (!pPciDev) /* NULL is an alias for the default PCI device. */
133 pPciDev = pDevIns->apPciDevs[0];
134 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
135 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
136
137#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
138 /*
139 * Just check the busmaster setting here and forward the request to the generic read helper.
140 */
141 if (PCIDevIsBusmaster(pPciDev))
142 { /* likely */ }
143 else
144 {
145 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
146 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
147 memset(pvBuf, 0xff, cbRead);
148 return VERR_PDM_NOT_PCI_BUS_MASTER;
149 }
150#endif
151
152#ifdef VBOX_WITH_IOMMU_AMD
153 /** @todo IOMMU: Optimize/re-organize things here later. */
154 PGVM pGVM = pDevIns->Internal.s.pGVM;
155 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
156 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
157 if ( pDevInsIommu
158 && pDevInsIommu != pDevIns)
159 {
160 RTGCPHYS GCPhysOut;
161 uint16_t const uDeviceId = VBOX_PCI_BUSDEVFN_MAKE(pPciDev->Int.s.idxPdmBus, pPciDev->uDevFn);
162 int rc = pIommu->pfnMemRead(pDevInsIommu, uDeviceId, GCPhys, cbRead, &GCPhysOut);
163 if (RT_FAILURE(rc))
164 {
165 Log(("pdmR0DevHlp_PCIPhysRead: IOMMU translation failed. uDeviceId=%#x GCPhys=%#RGp cb=%u rc=%Rrc\n", uDeviceId,
166 GCPhys, cbRead, rc));
167 return rc;
168 }
169 }
170#endif
171
172 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
173}
174
175
176/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
177static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
178 const void *pvBuf, size_t cbWrite, uint32_t fFlags)
179{
180 PDMDEV_ASSERT_DEVINS(pDevIns);
181 if (!pPciDev) /* NULL is an alias for the default PCI device. */
182 pPciDev = pDevIns->apPciDevs[0];
183 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
184 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
185
186#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
187 /*
188 * Just check the busmaster setting here and forward the request to the generic read helper.
189 */
190 if (PCIDevIsBusmaster(pPciDev))
191 { /* likely */ }
192 else
193 {
194 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
195 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
196 return VERR_PDM_NOT_PCI_BUS_MASTER;
197 }
198#endif
199
200#ifdef VBOX_WITH_IOMMU_AMD
201 /** @todo IOMMU: Optimize/re-organize things here later. */
202 PGVM pGVM = pDevIns->Internal.s.pGVM;
203 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
204 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
205 if ( pDevInsIommu
206 && pDevInsIommu != pDevIns)
207 {
208 RTGCPHYS GCPhysOut;
209 uint16_t const uDeviceId = VBOX_PCI_BUSDEVFN_MAKE(pPciDev->Int.s.idxPdmBus, pPciDev->uDevFn);
210 int rc = pIommu->pfnMemWrite(pDevInsIommu, uDeviceId, GCPhys, cbWrite, &GCPhysOut);
211 if (RT_FAILURE(rc))
212 {
213 Log(("pdmR0DevHlp_PCIPhysWrite: IOMMU translation failed. uDeviceId=%#x GCPhys=%#RGp cb=%u rc=%Rrc\n", uDeviceId,
214 GCPhys, cbWrite, rc));
215 return rc;
216 }
217 }
218#endif
219
220 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
221}
222
223
224/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
225static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
226{
227 PDMDEV_ASSERT_DEVINS(pDevIns);
228 if (!pPciDev) /* NULL is an alias for the default PCI device. */
229 pPciDev = pDevIns->apPciDevs[0];
230 AssertReturnVoid(pPciDev);
231 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
232 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
233 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
234
235 PGVM pGVM = pDevIns->Internal.s.pGVM;
236 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
237 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
238 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
239
240 pdmLock(pGVM);
241
242 uint32_t uTagSrc;
243 if (iLevel & PDM_IRQ_LEVEL_HIGH)
244 {
245 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
246 if (iLevel == PDM_IRQ_LEVEL_HIGH)
247 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
248 else
249 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
250 }
251 else
252 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
253
254 if (pPciBusR0->pDevInsR0)
255 {
256 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
257
258 pdmUnlock(pGVM);
259
260 if (iLevel == PDM_IRQ_LEVEL_LOW)
261 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
262 }
263 else
264 {
265 pdmUnlock(pGVM);
266
267 /* queue for ring-3 execution. */
268 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
269 AssertReturnVoid(pTask);
270
271 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
272 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
273 pTask->u.PciSetIRQ.iIrq = iIrq;
274 pTask->u.PciSetIRQ.iLevel = iLevel;
275 pTask->u.PciSetIRQ.uTagSrc = uTagSrc;
276 pTask->u.PciSetIRQ.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
277
278 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
279 }
280
281 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
282}
283
284
285/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
286static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
287{
288 PDMDEV_ASSERT_DEVINS(pDevIns);
289 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
290 PGVM pGVM = pDevIns->Internal.s.pGVM;
291
292 pdmLock(pGVM);
293 uint32_t uTagSrc;
294 if (iLevel & PDM_IRQ_LEVEL_HIGH)
295 {
296 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
297 if (iLevel == PDM_IRQ_LEVEL_HIGH)
298 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
299 else
300 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
301 }
302 else
303 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
304
305 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
306
307 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
308 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
309 pdmUnlock(pGVM);
310 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
311}
312
313
314/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSendMsi} */
315static DECLCALLBACK(void) pdmR0DevHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
316{
317 PDMDEV_ASSERT_DEVINS(pDevIns);
318 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: GCPhys=%RGp uValue=%#x\n", pDevIns, pDevIns->iInstance, GCPhys, uValue));
319 PGVM pGVM = pDevIns->Internal.s.pGVM;
320
321 uint32_t uTagSrc;
322 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
323 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
324
325 if (pGVM->pdm.s.IoApic.pDevInsR0)
326 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
327 else
328 AssertFatalMsgFailed(("Lazy bastards!"));
329
330 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
331}
332
333
334/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
335static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
336{
337 RT_NOREF(fFlags);
338
339 PDMDEV_ASSERT_DEVINS(pDevIns);
340 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
341 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
342
343 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
344 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
345
346 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
347 return VBOXSTRICTRC_VAL(rcStrict);
348}
349
350
351/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
352static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
353{
354 RT_NOREF(fFlags);
355
356 PDMDEV_ASSERT_DEVINS(pDevIns);
357 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
358 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
359
360 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
361 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
362
363 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
364 return VBOXSTRICTRC_VAL(rcStrict);
365}
366
367
368/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
369static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
370{
371 PDMDEV_ASSERT_DEVINS(pDevIns);
372 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
373
374 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
375
376 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
377 return fEnabled;
378}
379
380
381/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
382static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
383{
384 PDMDEV_ASSERT_DEVINS(pDevIns);
385
386 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
387
388 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
389 return enmVMState;
390}
391
392
393/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
394static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
395{
396 PDMDEV_ASSERT_DEVINS(pDevIns);
397 va_list args;
398 va_start(args, pszFormat);
399 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
400 va_end(args);
401 return rc;
402}
403
404
405/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
406static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
407{
408 PDMDEV_ASSERT_DEVINS(pDevIns);
409 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
410 return rc;
411}
412
413
414/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
415static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
416{
417 PDMDEV_ASSERT_DEVINS(pDevIns);
418 va_list va;
419 va_start(va, pszFormat);
420 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
421 va_end(va);
422 return rc;
423}
424
425
426/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
427static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
428{
429 PDMDEV_ASSERT_DEVINS(pDevIns);
430 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
431 return rc;
432}
433
434
435
436/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
437static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
438{
439 PDMDEV_ASSERT_DEVINS(pDevIns);
440 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
441 return pDevIns->Internal.s.pGVM;
442}
443
444
445/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
446static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
447{
448 PDMDEV_ASSERT_DEVINS(pDevIns);
449 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
450 return VMMGetCpu(pDevIns->Internal.s.pGVM);
451}
452
453
454/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
455static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
456{
457 PDMDEV_ASSERT_DEVINS(pDevIns);
458 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
459 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
460 return idCpu;
461}
462
463
464/** @interface_method_impl{PDMDEVHLPR0,pfnTimerToPtr} */
465static DECLCALLBACK(PTMTIMERR0) pdmR0DevHlp_TimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
466{
467 PDMDEV_ASSERT_DEVINS(pDevIns);
468 RT_NOREF(pDevIns);
469 return (PTMTIMERR0)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hTimer);
470}
471
472
473/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
474static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
475{
476 return TMTimerFromMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicroSecs);
477}
478
479
480/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
481static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
482{
483 return TMTimerFromMilli(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliSecs);
484}
485
486
487/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
488static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
489{
490 return TMTimerFromNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanoSecs);
491}
492
493/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
494static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
495{
496 return TMTimerGet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
497}
498
499
500/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
501static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
502{
503 return TMTimerGetFreq(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
504}
505
506
507/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
508static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
509{
510 return TMTimerGetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
511}
512
513
514/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
515static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
516{
517 return TMTimerIsActive(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
518}
519
520
521/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
522static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
523{
524 return TMTimerIsLockOwner(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
525}
526
527
528/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock} */
529static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
530{
531 return TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
532}
533
534
535/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock2} */
536static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
537 PPDMCRITSECT pCritSect, int rcBusy)
538{
539 VBOXSTRICTRC rc = TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
540 if (rc == VINF_SUCCESS)
541 {
542 rc = PDMCritSectEnter(pCritSect, rcBusy);
543 if (rc == VINF_SUCCESS)
544 return rc;
545 AssertRC(VBOXSTRICTRC_VAL(rc));
546 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
547 }
548 else
549 AssertRC(VBOXSTRICTRC_VAL(rc));
550 return rc;
551}
552
553
554/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
555static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
556{
557 return TMTimerSet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uExpire);
558}
559
560
561/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
562static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
563{
564 return TMTimerSetFrequencyHint(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uHz);
565}
566
567
568/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
569static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
570{
571 return TMTimerSetMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicrosToNext);
572}
573
574
575/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
576static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
577{
578 return TMTimerSetMillies(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliesToNext);
579}
580
581
582/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
583static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
584{
585 return TMTimerSetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanosToNext);
586}
587
588
589/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
590static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
591{
592 return TMTimerSetRelative(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cTicksToNext, pu64Now);
593}
594
595
596/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
597static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
598{
599 return TMTimerStop(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
600}
601
602
603/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock} */
604static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
605{
606 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
607}
608
609
610/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock2} */
611static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
612{
613 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
614 int rc = PDMCritSectLeave(pCritSect);
615 AssertRC(rc);
616}
617
618
619/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
620static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
621{
622 PDMDEV_ASSERT_DEVINS(pDevIns);
623 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
624 return TMVirtualGet(pDevIns->Internal.s.pGVM);
625}
626
627
628/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
629static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
630{
631 PDMDEV_ASSERT_DEVINS(pDevIns);
632 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
633 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
634}
635
636
637/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
638static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
639{
640 PDMDEV_ASSERT_DEVINS(pDevIns);
641 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
642 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
643}
644
645
646/** @interface_method_impl{PDMDEVHLPR0,pfnQueueToPtr} */
647static DECLCALLBACK(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
648{
649 PDMDEV_ASSERT_DEVINS(pDevIns);
650 RT_NOREF(pDevIns);
651 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
652}
653
654
655/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
656static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
657{
658 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
659}
660
661
662/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
663static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
664{
665 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
666}
667
668
669/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsertEx} */
670static DECLCALLBACK(void) pdmR0DevHlp_QueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem,
671 uint64_t cNanoMaxDelay)
672{
673 return PDMQueueInsertEx(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem, cNanoMaxDelay);
674}
675
676
677/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
678static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
679{
680 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
681}
682
683
684/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
685static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
686{
687 PDMDEV_ASSERT_DEVINS(pDevIns);
688 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
689
690 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
691
692 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
693 return rc;
694}
695
696
697/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
698static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
699{
700 PDMDEV_ASSERT_DEVINS(pDevIns);
701 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
702
703 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
704
705 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
706 return rc;
707}
708
709
710/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
711static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
712{
713 PDMDEV_ASSERT_DEVINS(pDevIns);
714 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
715 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
716
717 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
718
719 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
720 return rc;
721}
722
723
724/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
725static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
726{
727 PDMDEV_ASSERT_DEVINS(pDevIns);
728 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
729 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
730
731 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
732
733 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
734 return rc;
735}
736
737
738/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
739static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
740{
741 PDMDEV_ASSERT_DEVINS(pDevIns);
742 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
743 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
744
745 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
746
747 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
748 return rc;
749}
750
751
752/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
753static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
754{
755 PDMDEV_ASSERT_DEVINS(pDevIns);
756 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
757
758 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
759
760 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
761 return cNsResolution;
762}
763
764
765/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
766static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
767{
768 PDMDEV_ASSERT_DEVINS(pDevIns);
769 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
770
771 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
772
773 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
774 return rc;
775}
776
777
778/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
779static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
780{
781 PDMDEV_ASSERT_DEVINS(pDevIns);
782 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
783
784 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
785
786 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
787 return rc;
788}
789
790
791/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
792static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
793 uint32_t cMillies)
794{
795 PDMDEV_ASSERT_DEVINS(pDevIns);
796 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
797 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
798
799 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
800
801 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
802 return rc;
803}
804
805
806/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
807static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
808 uint64_t uNsTimeout)
809{
810 PDMDEV_ASSERT_DEVINS(pDevIns);
811 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
812 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
813
814 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
815
816 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
817 return rc;
818}
819
820
821/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
822static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
823 uint64_t cNsTimeout)
824{
825 PDMDEV_ASSERT_DEVINS(pDevIns);
826 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
827 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
828
829 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
830
831 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
832 return rc;
833}
834
835
836/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
837static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
838{
839 PDMDEV_ASSERT_DEVINS(pDevIns);
840 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
841
842 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
843
844 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
845 return cNsResolution;
846}
847
848
849/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
850static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
851{
852 PDMDEV_ASSERT_DEVINS(pDevIns);
853 PGVM pGVM = pDevIns->Internal.s.pGVM;
854
855 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
856 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
857 return pCritSect;
858}
859
860
861/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
862static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
863{
864 /*
865 * Validate input.
866 *
867 * Note! We only allow the automatically created default critical section
868 * to be replaced by this API.
869 */
870 PDMDEV_ASSERT_DEVINS(pDevIns);
871 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
872 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
873 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
874 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
875 PGVM pGVM = pDevIns->Internal.s.pGVM;
876 AssertReturn(pCritSect->s.pVMR0 == pGVM, VERR_INVALID_PARAMETER);
877
878 VM_ASSERT_EMT(pGVM);
879 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
880
881 /*
882 * Check that ring-3 has already done this, then effect the change.
883 */
884 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
885 pDevIns->pCritSectRoR0 = pCritSect;
886
887 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
888 return VINF_SUCCESS;
889}
890
891
892/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
893static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
894{
895 PDMDEV_ASSERT_DEVINS(pDevIns);
896 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
897 return PDMCritSectEnter(pCritSect, rcBusy);
898}
899
900
901/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
902static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
903{
904 PDMDEV_ASSERT_DEVINS(pDevIns);
905 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
906 return PDMCritSectEnterDebug(pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
907}
908
909
910/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
911static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
912{
913 PDMDEV_ASSERT_DEVINS(pDevIns);
914 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
915 return PDMCritSectTryEnter(pCritSect);
916}
917
918
919/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
920static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
921{
922 PDMDEV_ASSERT_DEVINS(pDevIns);
923 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
924 return PDMCritSectTryEnterDebug(pCritSect, uId, RT_SRC_POS_ARGS);
925}
926
927
928/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
929static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
930{
931 PDMDEV_ASSERT_DEVINS(pDevIns);
932 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
933 return PDMCritSectLeave(pCritSect);
934}
935
936
937/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
938static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
939{
940 PDMDEV_ASSERT_DEVINS(pDevIns);
941 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
942 return PDMCritSectIsOwner(pCritSect);
943}
944
945
946/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
947static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
948{
949 PDMDEV_ASSERT_DEVINS(pDevIns);
950 RT_NOREF(pDevIns);
951 return PDMCritSectIsInitialized(pCritSect);
952}
953
954
955/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
956static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
957{
958 PDMDEV_ASSERT_DEVINS(pDevIns);
959 RT_NOREF(pDevIns);
960 return PDMCritSectHasWaiters(pCritSect);
961}
962
963
964/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
965static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
966{
967 PDMDEV_ASSERT_DEVINS(pDevIns);
968 RT_NOREF(pDevIns);
969 return PDMCritSectGetRecursion(pCritSect);
970}
971
972
973/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
974static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
975 SUPSEMEVENT hEventToSignal)
976{
977 PDMDEV_ASSERT_DEVINS(pDevIns);
978 RT_NOREF(pDevIns);
979 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
980}
981
982
983/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
984static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
985{
986 PDMDEV_ASSERT_DEVINS(pDevIns);
987 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
988 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
989 return hTraceBuf;
990}
991
992
993/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
994static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
995{
996 PDMDEV_ASSERT_DEVINS(pDevIns);
997 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
998 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
999 pPciBusReg->u32EndVersion, ppPciHlp));
1000 PGVM pGVM = pDevIns->Internal.s.pGVM;
1001
1002 /*
1003 * Validate input.
1004 */
1005 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
1006 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
1007 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1008 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
1009 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
1010 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1011
1012 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
1013
1014 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1015 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1016
1017 /* Check the shared bus data (registered earlier from ring-3): */
1018 uint32_t iBus = pPciBusReg->iBus;
1019 ASMCompilerBarrier();
1020 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
1021 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
1022 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
1023 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
1024 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
1025
1026 /* Check that the bus isn't already registered in ring-0: */
1027 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
1028 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
1029 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
1030 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1031 VERR_ALREADY_EXISTS);
1032
1033 /*
1034 * Do the registering.
1035 */
1036 pPciBusR0->iBus = iBus;
1037 pPciBusR0->uPadding0 = 0xbeefbeef;
1038 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1039 pPciBusR0->pDevInsR0 = pDevIns;
1040
1041 *ppPciHlp = &g_pdmR0PciHlp;
1042
1043 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1044 return VINF_SUCCESS;
1045}
1046
1047
1048/** @interface_method_impl{PDMDEVHLPR0,pfnIommuSetUpContext} */
1049static DECLCALLBACK(int) pdmR0DevHlp_IommuSetUpContext(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp)
1050{
1051 PDMDEV_ASSERT_DEVINS(pDevIns);
1052 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: pIommuReg=%p{.u32Version=%#x, u32TheEnd=%#x} ppIommuHlp=%p\n",
1053 pDevIns, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
1054 PGVM pGVM = pDevIns->Internal.s.pGVM;
1055
1056 /*
1057 * Validate input.
1058 */
1059 AssertPtrReturn(pIommuReg, VERR_INVALID_POINTER);
1060 AssertLogRelMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGCC_VERSION,
1061 ("%#x vs %#x\n", pIommuReg->u32Version, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1062 AssertLogRelMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGCC_VERSION,
1063 ("%#x vs %#x\n", pIommuReg->u32TheEnd, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1064
1065 AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
1066
1067 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1068 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1069
1070 /* Check the IOMMU shared data (registered earlier from ring-3). */
1071 uint32_t const idxIommu = pIommuReg->idxIommu;
1072 ASMCompilerBarrier();
1073 AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pGVM->pdm.s.aIommus), ("idxIommu=%#x\n", idxIommu), VERR_OUT_OF_RANGE);
1074 PPDMIOMMU pIommuShared = &pGVM->pdm.s.aIommus[idxIommu];
1075 AssertLogRelMsgReturn(pIommuShared->idxIommu == idxIommu, ("%u vs %u\n", pIommuShared->idxIommu, idxIommu), VERR_INVALID_PARAMETER);
1076 AssertLogRelMsgReturn(pIommuShared->pDevInsR3 == pDevIns->pDevInsForR3,
1077 ("%p vs %p (idxIommu=%u)\n", pIommuShared->pDevInsR3, pDevIns->pDevInsForR3, idxIommu), VERR_NOT_OWNER);
1078
1079 /* Check that the IOMMU isn't already registered in ring-0. */
1080 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aIommus) == RT_ELEMENTS(pGVM->pdmr0.s.aIommus));
1081 PPDMIOMMUR0 pIommuR0 = &pGVM->pdmr0.s.aIommus[idxIommu];
1082 AssertLogRelMsgReturn(pIommuR0->pDevInsR0 == NULL,
1083 ("%p (caller pDevIns=%p, idxIommu=%u)\n", pIommuR0->pDevInsR0, pDevIns, idxIommu),
1084 VERR_ALREADY_EXISTS);
1085
1086 /*
1087 * Register.
1088 */
1089 pIommuR0->idxIommu = idxIommu;
1090 pIommuR0->uPadding0 = 0xdeaddead;
1091 pIommuR0->pDevInsR0 = pDevIns;
1092
1093 *ppIommuHlp = &g_pdmR0IommuHlp;
1094
1095 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1096 return VINF_SUCCESS;
1097}
1098
1099
1100/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1101static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1102{
1103 PDMDEV_ASSERT_DEVINS(pDevIns);
1104 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1105 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1106 PGVM pGVM = pDevIns->Internal.s.pGVM;
1107
1108 /*
1109 * Validate input.
1110 */
1111 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1112 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1113 VERR_VERSION_MISMATCH);
1114 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1115 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1116 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1117 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1118 VERR_VERSION_MISMATCH);
1119 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1120
1121 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1122 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1123
1124 /* Check that it's the same device as made the ring-3 registrations: */
1125 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1126 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1127
1128 /* Check that it isn't already registered in ring-0: */
1129 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1130 VERR_ALREADY_EXISTS);
1131
1132 /*
1133 * Take down the callbacks and instance.
1134 */
1135 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1136 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1137 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1138 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1139
1140 /* set the helper pointer and return. */
1141 *ppPicHlp = &g_pdmR0PicHlp;
1142 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1143 return VINF_SUCCESS;
1144}
1145
1146
1147/** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
1148static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
1149{
1150 PDMDEV_ASSERT_DEVINS(pDevIns);
1151 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1152 PGVM pGVM = pDevIns->Internal.s.pGVM;
1153
1154 /*
1155 * Validate input.
1156 */
1157 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1158 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1159
1160 /* Check that it's the same device as made the ring-3 registrations: */
1161 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR3 == pDevIns->pDevInsForR3,
1162 ("%p vs %p\n", pGVM->pdm.s.Apic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1163
1164 /* Check that it isn't already registered in ring-0: */
1165 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Apic.pDevInsR0, pDevIns),
1166 VERR_ALREADY_EXISTS);
1167
1168 /*
1169 * Take down the instance.
1170 */
1171 pGVM->pdm.s.Apic.pDevInsR0 = pDevIns;
1172 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1173
1174 /* set the helper pointer and return. */
1175 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1176 return VINF_SUCCESS;
1177}
1178
1179
1180/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSetUpContext} */
1181static DECLCALLBACK(int) pdmR0DevHlp_IoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
1182{
1183 PDMDEV_ASSERT_DEVINS(pDevIns);
1184 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
1185 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
1186 PGVM pGVM = pDevIns->Internal.s.pGVM;
1187
1188 /*
1189 * Validate input.
1190 */
1191 AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
1192 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
1193 VERR_VERSION_MISMATCH);
1194 AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
1195 AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
1196 AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
1197 AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
1198 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
1199 VERR_VERSION_MISMATCH);
1200 AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
1201
1202 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1203 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1204
1205 /* Check that it's the same device as made the ring-3 registrations: */
1206 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR3 == pDevIns->pDevInsForR3,
1207 ("%p vs %p\n", pGVM->pdm.s.IoApic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1208
1209 /* Check that it isn't already registered in ring-0: */
1210 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.IoApic.pDevInsR0, pDevIns),
1211 VERR_ALREADY_EXISTS);
1212
1213 /*
1214 * Take down the callbacks and instance.
1215 */
1216 pGVM->pdm.s.IoApic.pDevInsR0 = pDevIns;
1217 pGVM->pdm.s.IoApic.pfnSetIrqR0 = pIoApicReg->pfnSetIrq;
1218 pGVM->pdm.s.IoApic.pfnSendMsiR0 = pIoApicReg->pfnSendMsi;
1219 pGVM->pdm.s.IoApic.pfnSetEoiR0 = pIoApicReg->pfnSetEoi;
1220 Log(("PDM: Registered IOAPIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1221
1222 /* set the helper pointer and return. */
1223 *ppIoApicHlp = &g_pdmR0IoApicHlp;
1224 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1225 return VINF_SUCCESS;
1226}
1227
1228
1229/** @interface_method_impl{PDMDEVHLPR0,pfnHpetSetUpContext} */
1230static DECLCALLBACK(int) pdmR0DevHlp_HpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp)
1231{
1232 PDMDEV_ASSERT_DEVINS(pDevIns);
1233 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: pHpetReg=%p:{.u32Version=%#x, } ppHpetHlp=%p\n",
1234 pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg, pHpetReg->u32Version, ppHpetHlp));
1235 PGVM pGVM = pDevIns->Internal.s.pGVM;
1236
1237 /*
1238 * Validate input.
1239 */
1240 AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
1241 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
1242 VERR_VERSION_MISMATCH);
1243 AssertPtrReturn(ppHpetHlp, VERR_INVALID_POINTER);
1244
1245 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1246 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1247
1248 /* Check that it's the same device as made the ring-3 registrations: */
1249 AssertLogRelMsgReturn(pGVM->pdm.s.pHpet == pDevIns->pDevInsForR3, ("%p vs %p\n", pGVM->pdm.s.pHpet, pDevIns->pDevInsForR3),
1250 VERR_NOT_OWNER);
1251
1252 ///* Check that it isn't already registered in ring-0: */
1253 //AssertLogRelMsgReturn(pGVM->pdm.s.Hpet.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Hpet.pDevInsR0, pDevIns),
1254 // VERR_ALREADY_EXISTS);
1255
1256 /*
1257 * Nothing to take down here at present.
1258 */
1259 Log(("PDM: Registered HPET device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1260
1261 /* set the helper pointer and return. */
1262 *ppHpetHlp = &g_pdmR0HpetHlp;
1263 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1264 return VINF_SUCCESS;
1265}
1266
1267
1268/**
1269 * The Ring-0 Device Helper Callbacks.
1270 */
1271extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1272{
1273 PDM_DEVHLPR0_VERSION,
1274 pdmR0DevHlp_IoPortSetUpContextEx,
1275 pdmR0DevHlp_MmioSetUpContextEx,
1276 pdmR0DevHlp_Mmio2SetUpContext,
1277 pdmR0DevHlp_PCIPhysRead,
1278 pdmR0DevHlp_PCIPhysWrite,
1279 pdmR0DevHlp_PCISetIrq,
1280 pdmR0DevHlp_ISASetIrq,
1281 pdmR0DevHlp_IoApicSendMsi,
1282 pdmR0DevHlp_PhysRead,
1283 pdmR0DevHlp_PhysWrite,
1284 pdmR0DevHlp_A20IsEnabled,
1285 pdmR0DevHlp_VMState,
1286 pdmR0DevHlp_VMSetError,
1287 pdmR0DevHlp_VMSetErrorV,
1288 pdmR0DevHlp_VMSetRuntimeError,
1289 pdmR0DevHlp_VMSetRuntimeErrorV,
1290 pdmR0DevHlp_GetVM,
1291 pdmR0DevHlp_GetVMCPU,
1292 pdmR0DevHlp_GetCurrentCpuId,
1293 pdmR0DevHlp_TimerToPtr,
1294 pdmR0DevHlp_TimerFromMicro,
1295 pdmR0DevHlp_TimerFromMilli,
1296 pdmR0DevHlp_TimerFromNano,
1297 pdmR0DevHlp_TimerGet,
1298 pdmR0DevHlp_TimerGetFreq,
1299 pdmR0DevHlp_TimerGetNano,
1300 pdmR0DevHlp_TimerIsActive,
1301 pdmR0DevHlp_TimerIsLockOwner,
1302 pdmR0DevHlp_TimerLockClock,
1303 pdmR0DevHlp_TimerLockClock2,
1304 pdmR0DevHlp_TimerSet,
1305 pdmR0DevHlp_TimerSetFrequencyHint,
1306 pdmR0DevHlp_TimerSetMicro,
1307 pdmR0DevHlp_TimerSetMillies,
1308 pdmR0DevHlp_TimerSetNano,
1309 pdmR0DevHlp_TimerSetRelative,
1310 pdmR0DevHlp_TimerStop,
1311 pdmR0DevHlp_TimerUnlockClock,
1312 pdmR0DevHlp_TimerUnlockClock2,
1313 pdmR0DevHlp_TMTimeVirtGet,
1314 pdmR0DevHlp_TMTimeVirtGetFreq,
1315 pdmR0DevHlp_TMTimeVirtGetNano,
1316 pdmR0DevHlp_QueueToPtr,
1317 pdmR0DevHlp_QueueAlloc,
1318 pdmR0DevHlp_QueueInsert,
1319 pdmR0DevHlp_QueueInsertEx,
1320 pdmR0DevHlp_QueueFlushIfNecessary,
1321 pdmR0DevHlp_TaskTrigger,
1322 pdmR0DevHlp_SUPSemEventSignal,
1323 pdmR0DevHlp_SUPSemEventWaitNoResume,
1324 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1325 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1326 pdmR0DevHlp_SUPSemEventGetResolution,
1327 pdmR0DevHlp_SUPSemEventMultiSignal,
1328 pdmR0DevHlp_SUPSemEventMultiReset,
1329 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1330 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1331 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1332 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1333 pdmR0DevHlp_CritSectGetNop,
1334 pdmR0DevHlp_SetDeviceCritSect,
1335 pdmR0DevHlp_CritSectEnter,
1336 pdmR0DevHlp_CritSectEnterDebug,
1337 pdmR0DevHlp_CritSectTryEnter,
1338 pdmR0DevHlp_CritSectTryEnterDebug,
1339 pdmR0DevHlp_CritSectLeave,
1340 pdmR0DevHlp_CritSectIsOwner,
1341 pdmR0DevHlp_CritSectIsInitialized,
1342 pdmR0DevHlp_CritSectHasWaiters,
1343 pdmR0DevHlp_CritSectGetRecursion,
1344 pdmR0DevHlp_CritSectScheduleExitEvent,
1345 pdmR0DevHlp_DBGFTraceBuf,
1346 pdmR0DevHlp_PCIBusSetUpContext,
1347 pdmR0DevHlp_IommuSetUpContext,
1348 pdmR0DevHlp_PICSetUpContext,
1349 pdmR0DevHlp_ApicSetUpContext,
1350 pdmR0DevHlp_IoApicSetUpContext,
1351 pdmR0DevHlp_HpetSetUpContext,
1352 NULL /*pfnReserved1*/,
1353 NULL /*pfnReserved2*/,
1354 NULL /*pfnReserved3*/,
1355 NULL /*pfnReserved4*/,
1356 NULL /*pfnReserved5*/,
1357 NULL /*pfnReserved6*/,
1358 NULL /*pfnReserved7*/,
1359 NULL /*pfnReserved8*/,
1360 NULL /*pfnReserved9*/,
1361 NULL /*pfnReserved10*/,
1362 PDM_DEVHLPR0_VERSION
1363};
1364
1365
1366#ifdef VBOX_WITH_DBGF_TRACING
1367/**
1368 * The Ring-0 Device Helper Callbacks - tracing variant.
1369 */
1370extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing =
1371{
1372 PDM_DEVHLPR0_VERSION,
1373 pdmR0DevHlpTracing_IoPortSetUpContextEx,
1374 pdmR0DevHlpTracing_MmioSetUpContextEx,
1375 pdmR0DevHlp_Mmio2SetUpContext,
1376 pdmR0DevHlpTracing_PCIPhysRead,
1377 pdmR0DevHlpTracing_PCIPhysWrite,
1378 pdmR0DevHlpTracing_PCISetIrq,
1379 pdmR0DevHlpTracing_ISASetIrq,
1380 pdmR0DevHlpTracing_IoApicSendMsi,
1381 pdmR0DevHlp_PhysRead,
1382 pdmR0DevHlp_PhysWrite,
1383 pdmR0DevHlp_A20IsEnabled,
1384 pdmR0DevHlp_VMState,
1385 pdmR0DevHlp_VMSetError,
1386 pdmR0DevHlp_VMSetErrorV,
1387 pdmR0DevHlp_VMSetRuntimeError,
1388 pdmR0DevHlp_VMSetRuntimeErrorV,
1389 pdmR0DevHlp_GetVM,
1390 pdmR0DevHlp_GetVMCPU,
1391 pdmR0DevHlp_GetCurrentCpuId,
1392 pdmR0DevHlp_TimerToPtr,
1393 pdmR0DevHlp_TimerFromMicro,
1394 pdmR0DevHlp_TimerFromMilli,
1395 pdmR0DevHlp_TimerFromNano,
1396 pdmR0DevHlp_TimerGet,
1397 pdmR0DevHlp_TimerGetFreq,
1398 pdmR0DevHlp_TimerGetNano,
1399 pdmR0DevHlp_TimerIsActive,
1400 pdmR0DevHlp_TimerIsLockOwner,
1401 pdmR0DevHlp_TimerLockClock,
1402 pdmR0DevHlp_TimerLockClock2,
1403 pdmR0DevHlp_TimerSet,
1404 pdmR0DevHlp_TimerSetFrequencyHint,
1405 pdmR0DevHlp_TimerSetMicro,
1406 pdmR0DevHlp_TimerSetMillies,
1407 pdmR0DevHlp_TimerSetNano,
1408 pdmR0DevHlp_TimerSetRelative,
1409 pdmR0DevHlp_TimerStop,
1410 pdmR0DevHlp_TimerUnlockClock,
1411 pdmR0DevHlp_TimerUnlockClock2,
1412 pdmR0DevHlp_TMTimeVirtGet,
1413 pdmR0DevHlp_TMTimeVirtGetFreq,
1414 pdmR0DevHlp_TMTimeVirtGetNano,
1415 pdmR0DevHlp_QueueToPtr,
1416 pdmR0DevHlp_QueueAlloc,
1417 pdmR0DevHlp_QueueInsert,
1418 pdmR0DevHlp_QueueInsertEx,
1419 pdmR0DevHlp_QueueFlushIfNecessary,
1420 pdmR0DevHlp_TaskTrigger,
1421 pdmR0DevHlp_SUPSemEventSignal,
1422 pdmR0DevHlp_SUPSemEventWaitNoResume,
1423 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1424 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1425 pdmR0DevHlp_SUPSemEventGetResolution,
1426 pdmR0DevHlp_SUPSemEventMultiSignal,
1427 pdmR0DevHlp_SUPSemEventMultiReset,
1428 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1429 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1430 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1431 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1432 pdmR0DevHlp_CritSectGetNop,
1433 pdmR0DevHlp_SetDeviceCritSect,
1434 pdmR0DevHlp_CritSectEnter,
1435 pdmR0DevHlp_CritSectEnterDebug,
1436 pdmR0DevHlp_CritSectTryEnter,
1437 pdmR0DevHlp_CritSectTryEnterDebug,
1438 pdmR0DevHlp_CritSectLeave,
1439 pdmR0DevHlp_CritSectIsOwner,
1440 pdmR0DevHlp_CritSectIsInitialized,
1441 pdmR0DevHlp_CritSectHasWaiters,
1442 pdmR0DevHlp_CritSectGetRecursion,
1443 pdmR0DevHlp_CritSectScheduleExitEvent,
1444 pdmR0DevHlp_DBGFTraceBuf,
1445 pdmR0DevHlp_PCIBusSetUpContext,
1446 pdmR0DevHlp_IommuSetUpContext,
1447 pdmR0DevHlp_PICSetUpContext,
1448 pdmR0DevHlp_ApicSetUpContext,
1449 pdmR0DevHlp_IoApicSetUpContext,
1450 pdmR0DevHlp_HpetSetUpContext,
1451 NULL /*pfnReserved1*/,
1452 NULL /*pfnReserved2*/,
1453 NULL /*pfnReserved3*/,
1454 NULL /*pfnReserved4*/,
1455 NULL /*pfnReserved5*/,
1456 NULL /*pfnReserved6*/,
1457 NULL /*pfnReserved7*/,
1458 NULL /*pfnReserved8*/,
1459 NULL /*pfnReserved9*/,
1460 NULL /*pfnReserved10*/,
1461 PDM_DEVHLPR0_VERSION
1462};
1463#endif
1464
1465
1466/** @} */
1467
1468
1469/** @name PIC Ring-0 Helpers
1470 * @{
1471 */
1472
1473/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1474static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1475{
1476 PDMDEV_ASSERT_DEVINS(pDevIns);
1477 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1478 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1479 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1480 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1481}
1482
1483
1484/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1485static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1486{
1487 PDMDEV_ASSERT_DEVINS(pDevIns);
1488 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1489 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1490 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1491 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1492}
1493
1494
1495/** @interface_method_impl{PDMPICHLP,pfnLock} */
1496static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1497{
1498 PDMDEV_ASSERT_DEVINS(pDevIns);
1499 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1500}
1501
1502
1503/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1504static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1505{
1506 PDMDEV_ASSERT_DEVINS(pDevIns);
1507 pdmUnlock(pDevIns->Internal.s.pGVM);
1508}
1509
1510
1511/**
1512 * The Ring-0 PIC Helper Callbacks.
1513 */
1514extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1515{
1516 PDM_PICHLP_VERSION,
1517 pdmR0PicHlp_SetInterruptFF,
1518 pdmR0PicHlp_ClearInterruptFF,
1519 pdmR0PicHlp_Lock,
1520 pdmR0PicHlp_Unlock,
1521 PDM_PICHLP_VERSION
1522};
1523
1524/** @} */
1525
1526
1527/** @name I/O APIC Ring-0 Helpers
1528 * @{
1529 */
1530
1531/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
1532static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1533 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1534 uint8_t u8TriggerMode, uint32_t uTagSrc)
1535{
1536 PDMDEV_ASSERT_DEVINS(pDevIns);
1537 PGVM pGVM = pDevIns->Internal.s.pGVM;
1538 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1539 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1540 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1541}
1542
1543
1544/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
1545static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1546{
1547 PDMDEV_ASSERT_DEVINS(pDevIns);
1548 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1549}
1550
1551
1552/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
1553static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1554{
1555 PDMDEV_ASSERT_DEVINS(pDevIns);
1556 pdmUnlock(pDevIns->Internal.s.pGVM);
1557}
1558
1559
1560/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
1561static DECLCALLBACK(int) pdmR0IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t uDevId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1562{
1563 PDMDEV_ASSERT_DEVINS(pDevIns);
1564 LogFlow(("pdmR0IoApicHlp_IommuMsiRemap: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
1565 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
1566
1567#ifdef VBOX_WITH_IOMMU_AMD
1568 /** @todo IOMMU: Optimize/re-organize things here later. */
1569 PGVM pGVM = pDevIns->Internal.s.pGVM;
1570 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
1571 PPDMDEVINS pDevInsIommu = pIommu->CTX_SUFF(pDevIns);
1572 if ( pDevInsIommu
1573 && pDevInsIommu != pDevIns)
1574 {
1575 int rc = pIommu->pfnMsiRemap(pDevInsIommu, uDevId, pMsiIn, pMsiOut);
1576 if (RT_FAILURE(rc))
1577 {
1578 Log(("pdmR0IoApicHlp_IommuMsiRemap: IOMMU MSI remap failed. uDevId=%#x pMsiIn=(%#RX64, %#RU32) rc=%Rrc\n",
1579 uDevId, pMsiIn->Addr.u64, pMsiIn->Data.u32, rc));
1580 return rc;
1581 }
1582 }
1583#else
1584 RT_NOREF(pDevIns, uDevId);
1585 *pMsiOut = *pMsiIn;
1586#endif
1587 return VINF_SUCCESS;
1588}
1589
1590
1591/**
1592 * The Ring-0 I/O APIC Helper Callbacks.
1593 */
1594extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp =
1595{
1596 PDM_IOAPICHLP_VERSION,
1597 pdmR0IoApicHlp_ApicBusDeliver,
1598 pdmR0IoApicHlp_Lock,
1599 pdmR0IoApicHlp_Unlock,
1600 pdmR0IoApicHlp_IommuMsiRemap,
1601 PDM_IOAPICHLP_VERSION
1602};
1603
1604/** @} */
1605
1606
1607
1608
1609/** @name PCI Bus Ring-0 Helpers
1610 * @{
1611 */
1612
1613/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1614static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1615{
1616 PDMDEV_ASSERT_DEVINS(pDevIns);
1617 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1618 PGVM pGVM = pDevIns->Internal.s.pGVM;
1619
1620 pdmLock(pGVM);
1621 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1622 pdmUnlock(pGVM);
1623}
1624
1625
1626/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1627static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1628{
1629 PDMDEV_ASSERT_DEVINS(pDevIns);
1630 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1631 PGVM pGVM = pDevIns->Internal.s.pGVM;
1632
1633 if (pGVM->pdm.s.IoApic.pDevInsR0)
1634 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
1635 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1636 {
1637 /* queue for ring-3 execution. */
1638 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1639 if (pTask)
1640 {
1641 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1642 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1643 pTask->u.IoApicSetIRQ.iIrq = iIrq;
1644 pTask->u.IoApicSetIRQ.iLevel = iLevel;
1645 pTask->u.IoApicSetIRQ.uTagSrc = uTagSrc;
1646
1647 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1648 }
1649 else
1650 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1651 }
1652}
1653
1654
1655/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1656static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
1657{
1658 PDMDEV_ASSERT_DEVINS(pDevIns);
1659 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
1660 PGVM pGVM = pDevIns->Internal.s.pGVM;
1661 if (pGVM->pdm.s.IoApic.pDevInsR0)
1662 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
1663 else
1664 AssertFatalMsgFailed(("Lazy bastards!"));
1665}
1666
1667
1668/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1669static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1670{
1671 PDMDEV_ASSERT_DEVINS(pDevIns);
1672 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1673}
1674
1675
1676/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1677static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1678{
1679 PDMDEV_ASSERT_DEVINS(pDevIns);
1680 pdmUnlock(pDevIns->Internal.s.pGVM);
1681}
1682
1683
1684/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1685static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1686{
1687 PDMDEV_ASSERT_DEVINS(pDevIns);
1688 PGVM pGVM = pDevIns->Internal.s.pGVM;
1689 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1690 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1691 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1692 return pRetDevIns;
1693}
1694
1695
1696/**
1697 * The Ring-0 PCI Bus Helper Callbacks.
1698 */
1699extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1700{
1701 PDM_PCIHLPR0_VERSION,
1702 pdmR0PciHlp_IsaSetIrq,
1703 pdmR0PciHlp_IoApicSetIrq,
1704 pdmR0PciHlp_IoApicSendMsi,
1705 pdmR0PciHlp_Lock,
1706 pdmR0PciHlp_Unlock,
1707 pdmR0PciHlp_GetBusByNo,
1708 PDM_PCIHLPR0_VERSION, /* the end */
1709};
1710
1711/** @} */
1712
1713
1714/** @name IOMMU Ring-0 Helpers
1715 * @{
1716 */
1717
1718/**
1719 * The Ring-0 IOMMU Helper Callbacks.
1720 */
1721extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp =
1722{
1723 PDM_IOMMUHLPR0_VERSION,
1724 PDM_IOMMUHLPR0_VERSION, /* the end */
1725};
1726
1727/** @} */
1728
1729
1730/** @name HPET Ring-0 Helpers
1731 * @{
1732 */
1733/* none */
1734
1735/**
1736 * The Ring-0 HPET Helper Callbacks.
1737 */
1738extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1739{
1740 PDM_HPETHLPR0_VERSION,
1741 PDM_HPETHLPR0_VERSION, /* the end */
1742};
1743
1744/** @} */
1745
1746
1747/** @name Raw PCI Ring-0 Helpers
1748 * @{
1749 */
1750/* none */
1751
1752/**
1753 * The Ring-0 PCI raw Helper Callbacks.
1754 */
1755extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1756{
1757 PDM_PCIRAWHLPR0_VERSION,
1758 PDM_PCIRAWHLPR0_VERSION, /* the end */
1759};
1760
1761/** @} */
1762
1763
1764
1765
1766/**
1767 * Sets an irq on the PIC and I/O APIC.
1768 *
1769 * @returns true if delivered, false if postponed.
1770 * @param pGVM The global (ring-0) VM structure.
1771 * @param iIrq The irq.
1772 * @param iLevel The new level.
1773 * @param uTagSrc The IRQ tag and source.
1774 *
1775 * @remarks The caller holds the PDM lock.
1776 */
1777DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1778{
1779 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1780 || !pGVM->pdm.s.IoApic.pDevInsR3)
1781 && ( pGVM->pdm.s.Pic.pDevInsR0
1782 || !pGVM->pdm.s.Pic.pDevInsR3)))
1783 {
1784 if (pGVM->pdm.s.Pic.pDevInsR0)
1785 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1786 if (pGVM->pdm.s.IoApic.pDevInsR0)
1787 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
1788 return true;
1789 }
1790
1791 /* queue for ring-3 execution. */
1792 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1793 AssertReturn(pTask, false);
1794
1795 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1796 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1797 pTask->u.IsaSetIRQ.iIrq = iIrq;
1798 pTask->u.IsaSetIRQ.iLevel = iLevel;
1799 pTask->u.IsaSetIRQ.uTagSrc = uTagSrc;
1800
1801 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1802 return false;
1803}
1804
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