VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp@ 90348

Last change on this file since 90348 was 90348, checked in by vboxsync, 3 years ago

VMM: Removed the VM pointers from the internal critsect structures. bugref:9218 bugref:10074
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1/* $Id: PDMR0DevHlp.cpp 90348 2021-07-26 21:01:38Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device Helper parts.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/vmcc.h>
32#include <VBox/vmm/gvmm.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/ctype.h>
40#include <iprt/string.h>
41
42#include "dtrace/VBoxVMM.h"
43#include "PDMInline.h"
44
45
46/*********************************************************************************************************************************
47* Global Variables *
48*********************************************************************************************************************************/
49RT_C_DECLS_BEGIN
50extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
51extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing;
52extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
53extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp;
54extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
55extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp;
56extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
57extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
58RT_C_DECLS_END
59
60
61/*********************************************************************************************************************************
62* Internal Functions *
63*********************************************************************************************************************************/
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
71static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
72 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
73 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
74 void *pvUser)
75{
76 PDMDEV_ASSERT_DEVINS(pDevIns);
77 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
78 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
79 PGVM pGVM = pDevIns->Internal.s.pGVM;
80 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
81 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
82
83 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
84
85 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
86 return rc;
87}
88
89
90/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
91static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
92 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
93{
94 PDMDEV_ASSERT_DEVINS(pDevIns);
95 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
96 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
97 PGVM pGVM = pDevIns->Internal.s.pGVM;
98 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
99 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
100
101 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
102
103 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
104 return rc;
105}
106
107
108/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
109static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
110 size_t offSub, size_t cbSub, void **ppvMapping)
111{
112 PDMDEV_ASSERT_DEVINS(pDevIns);
113 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
114 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
115 *ppvMapping = NULL;
116
117 PGVM pGVM = pDevIns->Internal.s.pGVM;
118 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
119 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
120
121 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
122
123 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
124 return rc;
125}
126
127
128/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
129static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
130 void *pvBuf, size_t cbRead, uint32_t fFlags)
131{
132 PDMDEV_ASSERT_DEVINS(pDevIns);
133 if (!pPciDev) /* NULL is an alias for the default PCI device. */
134 pPciDev = pDevIns->apPciDevs[0];
135 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
136 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
137
138#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
139 /*
140 * Just check the busmaster setting here and forward the request to the generic read helper.
141 */
142 if (PCIDevIsBusmaster(pPciDev))
143 { /* likely */ }
144 else
145 {
146 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n", pDevIns, pDevIns->iInstance,
147 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
148 memset(pvBuf, 0xff, cbRead);
149 return VERR_PDM_NOT_PCI_BUS_MASTER;
150 }
151#endif
152
153#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
154 int rc = pdmIommuMemAccessRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, fFlags);
155 if ( rc == VERR_IOMMU_NOT_PRESENT
156 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
157 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
158 else
159 return rc;
160#endif
161
162 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
163}
164
165
166/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
167static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
168 const void *pvBuf, size_t cbWrite, uint32_t fFlags)
169{
170 PDMDEV_ASSERT_DEVINS(pDevIns);
171 if (!pPciDev) /* NULL is an alias for the default PCI device. */
172 pPciDev = pDevIns->apPciDevs[0];
173 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
174 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
175
176#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
177 /*
178 * Just check the busmaster setting here and forward the request to the generic read helper.
179 */
180 if (PCIDevIsBusmaster(pPciDev))
181 { /* likely */ }
182 else
183 {
184 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n", pDevIns, pDevIns->iInstance,
185 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
186 return VERR_PDM_NOT_PCI_BUS_MASTER;
187 }
188#endif
189
190#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
191 int rc = pdmIommuMemAccessWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, fFlags);
192 if ( rc == VERR_IOMMU_NOT_PRESENT
193 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
194 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
195 else
196 return rc;
197#endif
198
199 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
200}
201
202
203/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
204static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
205{
206 PDMDEV_ASSERT_DEVINS(pDevIns);
207 if (!pPciDev) /* NULL is an alias for the default PCI device. */
208 pPciDev = pDevIns->apPciDevs[0];
209 AssertReturnVoid(pPciDev);
210 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
211 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
212 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
213
214 PGVM pGVM = pDevIns->Internal.s.pGVM;
215 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
216 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
217 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
218
219 pdmLock(pGVM);
220
221 uint32_t uTagSrc;
222 if (iLevel & PDM_IRQ_LEVEL_HIGH)
223 {
224 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
225 if (iLevel == PDM_IRQ_LEVEL_HIGH)
226 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
227 else
228 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
229 }
230 else
231 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
232
233 if (pPciBusR0->pDevInsR0)
234 {
235 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
236
237 pdmUnlock(pGVM);
238
239 if (iLevel == PDM_IRQ_LEVEL_LOW)
240 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
241 }
242 else
243 {
244 pdmUnlock(pGVM);
245
246 /* queue for ring-3 execution. */
247 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
248 AssertReturnVoid(pTask);
249
250 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
251 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
252 pTask->u.PciSetIrq.iIrq = iIrq;
253 pTask->u.PciSetIrq.iLevel = iLevel;
254 pTask->u.PciSetIrq.uTagSrc = uTagSrc;
255 pTask->u.PciSetIrq.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
256
257 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
258 }
259
260 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
261}
262
263
264/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
265static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
266{
267 PDMDEV_ASSERT_DEVINS(pDevIns);
268 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
269 PGVM pGVM = pDevIns->Internal.s.pGVM;
270
271 pdmLock(pGVM);
272 uint32_t uTagSrc;
273 if (iLevel & PDM_IRQ_LEVEL_HIGH)
274 {
275 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
276 if (iLevel == PDM_IRQ_LEVEL_HIGH)
277 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
278 else
279 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
280 }
281 else
282 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
283
284 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
285
286 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
287 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
288 pdmUnlock(pGVM);
289 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
290}
291
292
293/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
294static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
295{
296 RT_NOREF(fFlags);
297
298 PDMDEV_ASSERT_DEVINS(pDevIns);
299 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
300 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
301
302 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
303 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
304
305 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
306 return VBOXSTRICTRC_VAL(rcStrict);
307}
308
309
310/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
311static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
312{
313 RT_NOREF(fFlags);
314
315 PDMDEV_ASSERT_DEVINS(pDevIns);
316 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
317 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
318
319 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
320 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
321
322 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
323 return VBOXSTRICTRC_VAL(rcStrict);
324}
325
326
327/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
328static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
329{
330 PDMDEV_ASSERT_DEVINS(pDevIns);
331 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
332
333 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
334
335 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
336 return fEnabled;
337}
338
339
340/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
341static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
342{
343 PDMDEV_ASSERT_DEVINS(pDevIns);
344
345 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
346
347 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
348 return enmVMState;
349}
350
351
352/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
353static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
354{
355 PDMDEV_ASSERT_DEVINS(pDevIns);
356 va_list args;
357 va_start(args, pszFormat);
358 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
359 va_end(args);
360 return rc;
361}
362
363
364/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
365static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
366{
367 PDMDEV_ASSERT_DEVINS(pDevIns);
368 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
369 return rc;
370}
371
372
373/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
374static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
375{
376 PDMDEV_ASSERT_DEVINS(pDevIns);
377 va_list va;
378 va_start(va, pszFormat);
379 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
380 va_end(va);
381 return rc;
382}
383
384
385/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
386static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
387{
388 PDMDEV_ASSERT_DEVINS(pDevIns);
389 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
390 return rc;
391}
392
393
394
395/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
396static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
397{
398 PDMDEV_ASSERT_DEVINS(pDevIns);
399 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
400 return pDevIns->Internal.s.pGVM;
401}
402
403
404/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
405static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
406{
407 PDMDEV_ASSERT_DEVINS(pDevIns);
408 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
409 return VMMGetCpu(pDevIns->Internal.s.pGVM);
410}
411
412
413/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
414static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
415{
416 PDMDEV_ASSERT_DEVINS(pDevIns);
417 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
418 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
419 return idCpu;
420}
421
422
423/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
424static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
425{
426 PDMDEV_ASSERT_DEVINS(pDevIns);
427 return TMTimerFromMicro(pDevIns->Internal.s.pGVM, hTimer, cMicroSecs);
428}
429
430
431/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
432static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
433{
434 PDMDEV_ASSERT_DEVINS(pDevIns);
435 return TMTimerFromMilli(pDevIns->Internal.s.pGVM, hTimer, cMilliSecs);
436}
437
438
439/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
440static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
441{
442 PDMDEV_ASSERT_DEVINS(pDevIns);
443 return TMTimerFromNano(pDevIns->Internal.s.pGVM, hTimer, cNanoSecs);
444}
445
446/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
447static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
448{
449 PDMDEV_ASSERT_DEVINS(pDevIns);
450 return TMTimerGet(pDevIns->Internal.s.pGVM, hTimer);
451}
452
453
454/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
455static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
456{
457 PDMDEV_ASSERT_DEVINS(pDevIns);
458 return TMTimerGetFreq(pDevIns->Internal.s.pGVM, hTimer);
459}
460
461
462/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
463static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
464{
465 PDMDEV_ASSERT_DEVINS(pDevIns);
466 return TMTimerGetNano(pDevIns->Internal.s.pGVM, hTimer);
467}
468
469
470/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
471static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
472{
473 PDMDEV_ASSERT_DEVINS(pDevIns);
474 return TMTimerIsActive(pDevIns->Internal.s.pGVM, hTimer);
475}
476
477
478/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
479static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
480{
481 PDMDEV_ASSERT_DEVINS(pDevIns);
482 return TMTimerIsLockOwner(pDevIns->Internal.s.pGVM, hTimer);
483}
484
485
486/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock} */
487static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
488{
489 PDMDEV_ASSERT_DEVINS(pDevIns);
490 return TMTimerLock(pDevIns->Internal.s.pGVM, hTimer, rcBusy);
491}
492
493
494/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock2} */
495static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
496 PPDMCRITSECT pCritSect, int rcBusy)
497{
498 PDMDEV_ASSERT_DEVINS(pDevIns);
499 PGVM const pGVM = pDevIns->Internal.s.pGVM;
500 VBOXSTRICTRC rc = TMTimerLock(pGVM, hTimer, rcBusy);
501 if (rc == VINF_SUCCESS)
502 {
503 rc = PDMCritSectEnter(pGVM, pCritSect, rcBusy);
504 if (rc == VINF_SUCCESS)
505 return rc;
506 AssertRC(VBOXSTRICTRC_VAL(rc));
507 TMTimerUnlock(pGVM, hTimer);
508 }
509 else
510 AssertRC(VBOXSTRICTRC_VAL(rc));
511 return rc;
512}
513
514
515/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
516static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
517{
518 PDMDEV_ASSERT_DEVINS(pDevIns);
519 return TMTimerSet(pDevIns->Internal.s.pGVM, hTimer, uExpire);
520}
521
522
523/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
524static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
525{
526 PDMDEV_ASSERT_DEVINS(pDevIns);
527 return TMTimerSetFrequencyHint(pDevIns->Internal.s.pGVM, hTimer, uHz);
528}
529
530
531/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
532static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
533{
534 PDMDEV_ASSERT_DEVINS(pDevIns);
535 return TMTimerSetMicro(pDevIns->Internal.s.pGVM, hTimer, cMicrosToNext);
536}
537
538
539/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
540static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
541{
542 PDMDEV_ASSERT_DEVINS(pDevIns);
543 return TMTimerSetMillies(pDevIns->Internal.s.pGVM, hTimer, cMilliesToNext);
544}
545
546
547/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
548static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
549{
550 PDMDEV_ASSERT_DEVINS(pDevIns);
551 return TMTimerSetNano(pDevIns->Internal.s.pGVM, hTimer, cNanosToNext);
552}
553
554
555/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
556static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
557{
558 PDMDEV_ASSERT_DEVINS(pDevIns);
559 return TMTimerSetRelative(pDevIns->Internal.s.pGVM, hTimer, cTicksToNext, pu64Now);
560}
561
562
563/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
564static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
565{
566 PDMDEV_ASSERT_DEVINS(pDevIns);
567 return TMTimerStop(pDevIns->Internal.s.pGVM, hTimer);
568}
569
570
571/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock} */
572static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
573{
574 PDMDEV_ASSERT_DEVINS(pDevIns);
575 TMTimerUnlock(pDevIns->Internal.s.pGVM, hTimer);
576}
577
578
579/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock2} */
580static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
581{
582 PDMDEV_ASSERT_DEVINS(pDevIns);
583 PGVM const pGVM = pDevIns->Internal.s.pGVM;
584 TMTimerUnlock(pGVM, hTimer);
585 int rc = PDMCritSectLeave(pGVM, pCritSect);
586 AssertRC(rc);
587}
588
589
590/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
591static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
592{
593 PDMDEV_ASSERT_DEVINS(pDevIns);
594 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
595 return TMVirtualGet(pDevIns->Internal.s.pGVM);
596}
597
598
599/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
600static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
601{
602 PDMDEV_ASSERT_DEVINS(pDevIns);
603 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
604 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
605}
606
607
608/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
609static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
610{
611 PDMDEV_ASSERT_DEVINS(pDevIns);
612 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
613 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
614}
615
616
617/** @interface_method_impl{PDMDEVHLPR0,pfnQueueToPtr} */
618static DECLCALLBACK(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
619{
620 PDMDEV_ASSERT_DEVINS(pDevIns);
621 RT_NOREF(pDevIns);
622 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
623}
624
625
626/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
627static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
628{
629 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
630}
631
632
633/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
634static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
635{
636 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
637}
638
639
640/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsertEx} */
641static DECLCALLBACK(void) pdmR0DevHlp_QueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem,
642 uint64_t cNanoMaxDelay)
643{
644 return PDMQueueInsertEx(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem, cNanoMaxDelay);
645}
646
647
648/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
649static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
650{
651 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
652}
653
654
655/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
656static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
657{
658 PDMDEV_ASSERT_DEVINS(pDevIns);
659 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
660
661 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
662
663 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
664 return rc;
665}
666
667
668/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
669static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
670{
671 PDMDEV_ASSERT_DEVINS(pDevIns);
672 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
673
674 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
675
676 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
677 return rc;
678}
679
680
681/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
682static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
683{
684 PDMDEV_ASSERT_DEVINS(pDevIns);
685 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
686 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
687
688 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
689
690 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
691 return rc;
692}
693
694
695/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
696static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
697{
698 PDMDEV_ASSERT_DEVINS(pDevIns);
699 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
700 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
701
702 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
703
704 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
705 return rc;
706}
707
708
709/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
710static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
711{
712 PDMDEV_ASSERT_DEVINS(pDevIns);
713 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
714 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
715
716 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
717
718 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
719 return rc;
720}
721
722
723/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
724static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
725{
726 PDMDEV_ASSERT_DEVINS(pDevIns);
727 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
728
729 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
730
731 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
732 return cNsResolution;
733}
734
735
736/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
737static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
738{
739 PDMDEV_ASSERT_DEVINS(pDevIns);
740 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
741
742 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
743
744 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
745 return rc;
746}
747
748
749/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
750static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
751{
752 PDMDEV_ASSERT_DEVINS(pDevIns);
753 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
754
755 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
756
757 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
758 return rc;
759}
760
761
762/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
763static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
764 uint32_t cMillies)
765{
766 PDMDEV_ASSERT_DEVINS(pDevIns);
767 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
768 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
769
770 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
771
772 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
773 return rc;
774}
775
776
777/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
778static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
779 uint64_t uNsTimeout)
780{
781 PDMDEV_ASSERT_DEVINS(pDevIns);
782 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
783 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
784
785 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
786
787 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
788 return rc;
789}
790
791
792/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
793static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
794 uint64_t cNsTimeout)
795{
796 PDMDEV_ASSERT_DEVINS(pDevIns);
797 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
798 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
799
800 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
801
802 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
803 return rc;
804}
805
806
807/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
808static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
809{
810 PDMDEV_ASSERT_DEVINS(pDevIns);
811 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
812
813 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
814
815 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
816 return cNsResolution;
817}
818
819
820/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
821static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
822{
823 PDMDEV_ASSERT_DEVINS(pDevIns);
824 PGVM pGVM = pDevIns->Internal.s.pGVM;
825
826 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
827 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
828 return pCritSect;
829}
830
831
832/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
833static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
834{
835 /*
836 * Validate input.
837 *
838 * Note! We only allow the automatically created default critical section
839 * to be replaced by this API.
840 */
841 PDMDEV_ASSERT_DEVINS(pDevIns);
842 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
843 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
844 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
845 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
846 PGVM pGVM = pDevIns->Internal.s.pGVM;
847
848 VM_ASSERT_EMT(pGVM);
849 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
850
851 /*
852 * Check that ring-3 has already done this, then effect the change.
853 */
854 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
855 pDevIns->pCritSectRoR0 = pCritSect;
856
857 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
858 return VINF_SUCCESS;
859}
860
861
862/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
863static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
864{
865 PDMDEV_ASSERT_DEVINS(pDevIns);
866 return PDMCritSectEnter(pDevIns->Internal.s.pGVM, pCritSect, rcBusy);
867}
868
869
870/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
871static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
872{
873 PDMDEV_ASSERT_DEVINS(pDevIns);
874 return PDMCritSectEnterDebug(pDevIns->Internal.s.pGVM, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
875}
876
877
878/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
879static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
880{
881 PDMDEV_ASSERT_DEVINS(pDevIns);
882 return PDMCritSectTryEnter(pDevIns->Internal.s.pGVM, pCritSect);
883}
884
885
886/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
887static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
888{
889 PDMDEV_ASSERT_DEVINS(pDevIns);
890 return PDMCritSectTryEnterDebug(pDevIns->Internal.s.pGVM, pCritSect, uId, RT_SRC_POS_ARGS);
891}
892
893
894/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
895static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
896{
897 PDMDEV_ASSERT_DEVINS(pDevIns);
898 return PDMCritSectLeave(pDevIns->Internal.s.pGVM, pCritSect);
899}
900
901
902/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
903static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
904{
905 PDMDEV_ASSERT_DEVINS(pDevIns);
906 return PDMCritSectIsOwner(pDevIns->Internal.s.pGVM, pCritSect);
907}
908
909
910/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
911static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
912{
913 PDMDEV_ASSERT_DEVINS(pDevIns);
914 RT_NOREF(pDevIns);
915 return PDMCritSectIsInitialized(pCritSect);
916}
917
918
919/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
920static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
921{
922 PDMDEV_ASSERT_DEVINS(pDevIns);
923 return PDMCritSectHasWaiters(pDevIns->Internal.s.pGVM, pCritSect);
924}
925
926
927/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
928static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
929{
930 PDMDEV_ASSERT_DEVINS(pDevIns);
931 RT_NOREF(pDevIns);
932 return PDMCritSectGetRecursion(pCritSect);
933}
934
935
936/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
937static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
938 SUPSEMEVENT hEventToSignal)
939{
940 PDMDEV_ASSERT_DEVINS(pDevIns);
941 RT_NOREF(pDevIns);
942 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
943}
944
945
946/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
947static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
948{
949 PDMDEV_ASSERT_DEVINS(pDevIns);
950 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
951 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
952 return hTraceBuf;
953}
954
955
956/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
957static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
958{
959 PDMDEV_ASSERT_DEVINS(pDevIns);
960 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
961 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
962 pPciBusReg->u32EndVersion, ppPciHlp));
963 PGVM pGVM = pDevIns->Internal.s.pGVM;
964
965 /*
966 * Validate input.
967 */
968 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
969 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
970 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
971 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
972 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
973 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
974
975 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
976
977 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
978 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
979
980 /* Check the shared bus data (registered earlier from ring-3): */
981 uint32_t iBus = pPciBusReg->iBus;
982 ASMCompilerBarrier();
983 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
984 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
985 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
986 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
987 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
988
989 /* Check that the bus isn't already registered in ring-0: */
990 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
991 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
992 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
993 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
994 VERR_ALREADY_EXISTS);
995
996 /*
997 * Do the registering.
998 */
999 pPciBusR0->iBus = iBus;
1000 pPciBusR0->uPadding0 = 0xbeefbeef;
1001 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1002 pPciBusR0->pDevInsR0 = pDevIns;
1003
1004 *ppPciHlp = &g_pdmR0PciHlp;
1005
1006 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1007 return VINF_SUCCESS;
1008}
1009
1010
1011/** @interface_method_impl{PDMDEVHLPR0,pfnIommuSetUpContext} */
1012static DECLCALLBACK(int) pdmR0DevHlp_IommuSetUpContext(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp)
1013{
1014 PDMDEV_ASSERT_DEVINS(pDevIns);
1015 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: pIommuReg=%p{.u32Version=%#x, u32TheEnd=%#x} ppIommuHlp=%p\n",
1016 pDevIns, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
1017 PGVM pGVM = pDevIns->Internal.s.pGVM;
1018
1019 /*
1020 * Validate input.
1021 */
1022 AssertPtrReturn(pIommuReg, VERR_INVALID_POINTER);
1023 AssertLogRelMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGCC_VERSION,
1024 ("%#x vs %#x\n", pIommuReg->u32Version, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1025 AssertPtrReturn(pIommuReg->pfnMemAccess, VERR_INVALID_POINTER);
1026 AssertPtrReturn(pIommuReg->pfnMemBulkAccess, VERR_INVALID_POINTER);
1027 AssertPtrReturn(pIommuReg->pfnMsiRemap, VERR_INVALID_POINTER);
1028 AssertLogRelMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGCC_VERSION,
1029 ("%#x vs %#x\n", pIommuReg->u32TheEnd, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1030
1031 AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
1032
1033 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1034 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1035
1036 /* Check the IOMMU shared data (registered earlier from ring-3). */
1037 uint32_t const idxIommu = pIommuReg->idxIommu;
1038 ASMCompilerBarrier();
1039 AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pGVM->pdm.s.aIommus), ("idxIommu=%#x\n", idxIommu), VERR_OUT_OF_RANGE);
1040 PPDMIOMMUR3 pIommuShared = &pGVM->pdm.s.aIommus[idxIommu];
1041 AssertLogRelMsgReturn(pIommuShared->idxIommu == idxIommu, ("%u vs %u\n", pIommuShared->idxIommu, idxIommu), VERR_INVALID_PARAMETER);
1042 AssertLogRelMsgReturn(pIommuShared->pDevInsR3 == pDevIns->pDevInsForR3,
1043 ("%p vs %p (idxIommu=%u)\n", pIommuShared->pDevInsR3, pDevIns->pDevInsForR3, idxIommu), VERR_NOT_OWNER);
1044
1045 /* Check that the IOMMU isn't already registered in ring-0. */
1046 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aIommus) == RT_ELEMENTS(pGVM->pdmr0.s.aIommus));
1047 PPDMIOMMUR0 pIommuR0 = &pGVM->pdmr0.s.aIommus[idxIommu];
1048 AssertLogRelMsgReturn(pIommuR0->pDevInsR0 == NULL,
1049 ("%p (caller pDevIns=%p, idxIommu=%u)\n", pIommuR0->pDevInsR0, pDevIns, idxIommu),
1050 VERR_ALREADY_EXISTS);
1051
1052 /*
1053 * Register.
1054 */
1055 pIommuR0->idxIommu = idxIommu;
1056 pIommuR0->uPadding0 = 0xdeaddead;
1057 pIommuR0->pDevInsR0 = pDevIns;
1058 pIommuR0->pfnMemAccess = pIommuReg->pfnMemAccess;
1059 pIommuR0->pfnMemBulkAccess = pIommuReg->pfnMemBulkAccess;
1060 pIommuR0->pfnMsiRemap = pIommuReg->pfnMsiRemap;
1061
1062 *ppIommuHlp = &g_pdmR0IommuHlp;
1063
1064 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1065 return VINF_SUCCESS;
1066}
1067
1068
1069/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1070static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1071{
1072 PDMDEV_ASSERT_DEVINS(pDevIns);
1073 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1074 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1075 PGVM pGVM = pDevIns->Internal.s.pGVM;
1076
1077 /*
1078 * Validate input.
1079 */
1080 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1081 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1082 VERR_VERSION_MISMATCH);
1083 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1084 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1085 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1086 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1087 VERR_VERSION_MISMATCH);
1088 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1089
1090 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1091 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1092
1093 /* Check that it's the same device as made the ring-3 registrations: */
1094 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1095 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1096
1097 /* Check that it isn't already registered in ring-0: */
1098 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1099 VERR_ALREADY_EXISTS);
1100
1101 /*
1102 * Take down the callbacks and instance.
1103 */
1104 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1105 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1106 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1107 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1108
1109 /* set the helper pointer and return. */
1110 *ppPicHlp = &g_pdmR0PicHlp;
1111 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1112 return VINF_SUCCESS;
1113}
1114
1115
1116/** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
1117static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
1118{
1119 PDMDEV_ASSERT_DEVINS(pDevIns);
1120 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1121 PGVM pGVM = pDevIns->Internal.s.pGVM;
1122
1123 /*
1124 * Validate input.
1125 */
1126 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1127 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1128
1129 /* Check that it's the same device as made the ring-3 registrations: */
1130 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR3 == pDevIns->pDevInsForR3,
1131 ("%p vs %p\n", pGVM->pdm.s.Apic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1132
1133 /* Check that it isn't already registered in ring-0: */
1134 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Apic.pDevInsR0, pDevIns),
1135 VERR_ALREADY_EXISTS);
1136
1137 /*
1138 * Take down the instance.
1139 */
1140 pGVM->pdm.s.Apic.pDevInsR0 = pDevIns;
1141 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1142
1143 /* set the helper pointer and return. */
1144 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1145 return VINF_SUCCESS;
1146}
1147
1148
1149/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSetUpContext} */
1150static DECLCALLBACK(int) pdmR0DevHlp_IoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
1151{
1152 PDMDEV_ASSERT_DEVINS(pDevIns);
1153 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
1154 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
1155 PGVM pGVM = pDevIns->Internal.s.pGVM;
1156
1157 /*
1158 * Validate input.
1159 */
1160 AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
1161 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
1162 VERR_VERSION_MISMATCH);
1163 AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
1164 AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
1165 AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
1166 AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
1167 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
1168 VERR_VERSION_MISMATCH);
1169 AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
1170
1171 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1172 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1173
1174 /* Check that it's the same device as made the ring-3 registrations: */
1175 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR3 == pDevIns->pDevInsForR3,
1176 ("%p vs %p\n", pGVM->pdm.s.IoApic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1177
1178 /* Check that it isn't already registered in ring-0: */
1179 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.IoApic.pDevInsR0, pDevIns),
1180 VERR_ALREADY_EXISTS);
1181
1182 /*
1183 * Take down the callbacks and instance.
1184 */
1185 pGVM->pdm.s.IoApic.pDevInsR0 = pDevIns;
1186 pGVM->pdm.s.IoApic.pfnSetIrqR0 = pIoApicReg->pfnSetIrq;
1187 pGVM->pdm.s.IoApic.pfnSendMsiR0 = pIoApicReg->pfnSendMsi;
1188 pGVM->pdm.s.IoApic.pfnSetEoiR0 = pIoApicReg->pfnSetEoi;
1189 Log(("PDM: Registered IOAPIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1190
1191 /* set the helper pointer and return. */
1192 *ppIoApicHlp = &g_pdmR0IoApicHlp;
1193 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1194 return VINF_SUCCESS;
1195}
1196
1197
1198/** @interface_method_impl{PDMDEVHLPR0,pfnHpetSetUpContext} */
1199static DECLCALLBACK(int) pdmR0DevHlp_HpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp)
1200{
1201 PDMDEV_ASSERT_DEVINS(pDevIns);
1202 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: pHpetReg=%p:{.u32Version=%#x, } ppHpetHlp=%p\n",
1203 pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg, pHpetReg->u32Version, ppHpetHlp));
1204 PGVM pGVM = pDevIns->Internal.s.pGVM;
1205
1206 /*
1207 * Validate input.
1208 */
1209 AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
1210 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
1211 VERR_VERSION_MISMATCH);
1212 AssertPtrReturn(ppHpetHlp, VERR_INVALID_POINTER);
1213
1214 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1215 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1216
1217 /* Check that it's the same device as made the ring-3 registrations: */
1218 AssertLogRelMsgReturn(pGVM->pdm.s.pHpet == pDevIns->pDevInsForR3, ("%p vs %p\n", pGVM->pdm.s.pHpet, pDevIns->pDevInsForR3),
1219 VERR_NOT_OWNER);
1220
1221 ///* Check that it isn't already registered in ring-0: */
1222 //AssertLogRelMsgReturn(pGVM->pdm.s.Hpet.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Hpet.pDevInsR0, pDevIns),
1223 // VERR_ALREADY_EXISTS);
1224
1225 /*
1226 * Nothing to take down here at present.
1227 */
1228 Log(("PDM: Registered HPET device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1229
1230 /* set the helper pointer and return. */
1231 *ppHpetHlp = &g_pdmR0HpetHlp;
1232 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1233 return VINF_SUCCESS;
1234}
1235
1236
1237/**
1238 * The Ring-0 Device Helper Callbacks.
1239 */
1240extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1241{
1242 PDM_DEVHLPR0_VERSION,
1243 pdmR0DevHlp_IoPortSetUpContextEx,
1244 pdmR0DevHlp_MmioSetUpContextEx,
1245 pdmR0DevHlp_Mmio2SetUpContext,
1246 pdmR0DevHlp_PCIPhysRead,
1247 pdmR0DevHlp_PCIPhysWrite,
1248 pdmR0DevHlp_PCISetIrq,
1249 pdmR0DevHlp_ISASetIrq,
1250 pdmR0DevHlp_PhysRead,
1251 pdmR0DevHlp_PhysWrite,
1252 pdmR0DevHlp_A20IsEnabled,
1253 pdmR0DevHlp_VMState,
1254 pdmR0DevHlp_VMSetError,
1255 pdmR0DevHlp_VMSetErrorV,
1256 pdmR0DevHlp_VMSetRuntimeError,
1257 pdmR0DevHlp_VMSetRuntimeErrorV,
1258 pdmR0DevHlp_GetVM,
1259 pdmR0DevHlp_GetVMCPU,
1260 pdmR0DevHlp_GetCurrentCpuId,
1261 pdmR0DevHlp_TimerFromMicro,
1262 pdmR0DevHlp_TimerFromMilli,
1263 pdmR0DevHlp_TimerFromNano,
1264 pdmR0DevHlp_TimerGet,
1265 pdmR0DevHlp_TimerGetFreq,
1266 pdmR0DevHlp_TimerGetNano,
1267 pdmR0DevHlp_TimerIsActive,
1268 pdmR0DevHlp_TimerIsLockOwner,
1269 pdmR0DevHlp_TimerLockClock,
1270 pdmR0DevHlp_TimerLockClock2,
1271 pdmR0DevHlp_TimerSet,
1272 pdmR0DevHlp_TimerSetFrequencyHint,
1273 pdmR0DevHlp_TimerSetMicro,
1274 pdmR0DevHlp_TimerSetMillies,
1275 pdmR0DevHlp_TimerSetNano,
1276 pdmR0DevHlp_TimerSetRelative,
1277 pdmR0DevHlp_TimerStop,
1278 pdmR0DevHlp_TimerUnlockClock,
1279 pdmR0DevHlp_TimerUnlockClock2,
1280 pdmR0DevHlp_TMTimeVirtGet,
1281 pdmR0DevHlp_TMTimeVirtGetFreq,
1282 pdmR0DevHlp_TMTimeVirtGetNano,
1283 pdmR0DevHlp_QueueToPtr,
1284 pdmR0DevHlp_QueueAlloc,
1285 pdmR0DevHlp_QueueInsert,
1286 pdmR0DevHlp_QueueInsertEx,
1287 pdmR0DevHlp_QueueFlushIfNecessary,
1288 pdmR0DevHlp_TaskTrigger,
1289 pdmR0DevHlp_SUPSemEventSignal,
1290 pdmR0DevHlp_SUPSemEventWaitNoResume,
1291 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1292 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1293 pdmR0DevHlp_SUPSemEventGetResolution,
1294 pdmR0DevHlp_SUPSemEventMultiSignal,
1295 pdmR0DevHlp_SUPSemEventMultiReset,
1296 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1297 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1298 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1299 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1300 pdmR0DevHlp_CritSectGetNop,
1301 pdmR0DevHlp_SetDeviceCritSect,
1302 pdmR0DevHlp_CritSectEnter,
1303 pdmR0DevHlp_CritSectEnterDebug,
1304 pdmR0DevHlp_CritSectTryEnter,
1305 pdmR0DevHlp_CritSectTryEnterDebug,
1306 pdmR0DevHlp_CritSectLeave,
1307 pdmR0DevHlp_CritSectIsOwner,
1308 pdmR0DevHlp_CritSectIsInitialized,
1309 pdmR0DevHlp_CritSectHasWaiters,
1310 pdmR0DevHlp_CritSectGetRecursion,
1311 pdmR0DevHlp_CritSectScheduleExitEvent,
1312 pdmR0DevHlp_DBGFTraceBuf,
1313 pdmR0DevHlp_PCIBusSetUpContext,
1314 pdmR0DevHlp_IommuSetUpContext,
1315 pdmR0DevHlp_PICSetUpContext,
1316 pdmR0DevHlp_ApicSetUpContext,
1317 pdmR0DevHlp_IoApicSetUpContext,
1318 pdmR0DevHlp_HpetSetUpContext,
1319 NULL /*pfnReserved1*/,
1320 NULL /*pfnReserved2*/,
1321 NULL /*pfnReserved3*/,
1322 NULL /*pfnReserved4*/,
1323 NULL /*pfnReserved5*/,
1324 NULL /*pfnReserved6*/,
1325 NULL /*pfnReserved7*/,
1326 NULL /*pfnReserved8*/,
1327 NULL /*pfnReserved9*/,
1328 NULL /*pfnReserved10*/,
1329 PDM_DEVHLPR0_VERSION
1330};
1331
1332
1333#ifdef VBOX_WITH_DBGF_TRACING
1334/**
1335 * The Ring-0 Device Helper Callbacks - tracing variant.
1336 */
1337extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing =
1338{
1339 PDM_DEVHLPR0_VERSION,
1340 pdmR0DevHlpTracing_IoPortSetUpContextEx,
1341 pdmR0DevHlpTracing_MmioSetUpContextEx,
1342 pdmR0DevHlp_Mmio2SetUpContext,
1343 pdmR0DevHlpTracing_PCIPhysRead,
1344 pdmR0DevHlpTracing_PCIPhysWrite,
1345 pdmR0DevHlpTracing_PCISetIrq,
1346 pdmR0DevHlpTracing_ISASetIrq,
1347 pdmR0DevHlp_PhysRead,
1348 pdmR0DevHlp_PhysWrite,
1349 pdmR0DevHlp_A20IsEnabled,
1350 pdmR0DevHlp_VMState,
1351 pdmR0DevHlp_VMSetError,
1352 pdmR0DevHlp_VMSetErrorV,
1353 pdmR0DevHlp_VMSetRuntimeError,
1354 pdmR0DevHlp_VMSetRuntimeErrorV,
1355 pdmR0DevHlp_GetVM,
1356 pdmR0DevHlp_GetVMCPU,
1357 pdmR0DevHlp_GetCurrentCpuId,
1358 pdmR0DevHlp_TimerFromMicro,
1359 pdmR0DevHlp_TimerFromMilli,
1360 pdmR0DevHlp_TimerFromNano,
1361 pdmR0DevHlp_TimerGet,
1362 pdmR0DevHlp_TimerGetFreq,
1363 pdmR0DevHlp_TimerGetNano,
1364 pdmR0DevHlp_TimerIsActive,
1365 pdmR0DevHlp_TimerIsLockOwner,
1366 pdmR0DevHlp_TimerLockClock,
1367 pdmR0DevHlp_TimerLockClock2,
1368 pdmR0DevHlp_TimerSet,
1369 pdmR0DevHlp_TimerSetFrequencyHint,
1370 pdmR0DevHlp_TimerSetMicro,
1371 pdmR0DevHlp_TimerSetMillies,
1372 pdmR0DevHlp_TimerSetNano,
1373 pdmR0DevHlp_TimerSetRelative,
1374 pdmR0DevHlp_TimerStop,
1375 pdmR0DevHlp_TimerUnlockClock,
1376 pdmR0DevHlp_TimerUnlockClock2,
1377 pdmR0DevHlp_TMTimeVirtGet,
1378 pdmR0DevHlp_TMTimeVirtGetFreq,
1379 pdmR0DevHlp_TMTimeVirtGetNano,
1380 pdmR0DevHlp_QueueToPtr,
1381 pdmR0DevHlp_QueueAlloc,
1382 pdmR0DevHlp_QueueInsert,
1383 pdmR0DevHlp_QueueInsertEx,
1384 pdmR0DevHlp_QueueFlushIfNecessary,
1385 pdmR0DevHlp_TaskTrigger,
1386 pdmR0DevHlp_SUPSemEventSignal,
1387 pdmR0DevHlp_SUPSemEventWaitNoResume,
1388 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1389 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1390 pdmR0DevHlp_SUPSemEventGetResolution,
1391 pdmR0DevHlp_SUPSemEventMultiSignal,
1392 pdmR0DevHlp_SUPSemEventMultiReset,
1393 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1394 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1395 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1396 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1397 pdmR0DevHlp_CritSectGetNop,
1398 pdmR0DevHlp_SetDeviceCritSect,
1399 pdmR0DevHlp_CritSectEnter,
1400 pdmR0DevHlp_CritSectEnterDebug,
1401 pdmR0DevHlp_CritSectTryEnter,
1402 pdmR0DevHlp_CritSectTryEnterDebug,
1403 pdmR0DevHlp_CritSectLeave,
1404 pdmR0DevHlp_CritSectIsOwner,
1405 pdmR0DevHlp_CritSectIsInitialized,
1406 pdmR0DevHlp_CritSectHasWaiters,
1407 pdmR0DevHlp_CritSectGetRecursion,
1408 pdmR0DevHlp_CritSectScheduleExitEvent,
1409 pdmR0DevHlp_DBGFTraceBuf,
1410 pdmR0DevHlp_PCIBusSetUpContext,
1411 pdmR0DevHlp_IommuSetUpContext,
1412 pdmR0DevHlp_PICSetUpContext,
1413 pdmR0DevHlp_ApicSetUpContext,
1414 pdmR0DevHlp_IoApicSetUpContext,
1415 pdmR0DevHlp_HpetSetUpContext,
1416 NULL /*pfnReserved1*/,
1417 NULL /*pfnReserved2*/,
1418 NULL /*pfnReserved3*/,
1419 NULL /*pfnReserved4*/,
1420 NULL /*pfnReserved5*/,
1421 NULL /*pfnReserved6*/,
1422 NULL /*pfnReserved7*/,
1423 NULL /*pfnReserved8*/,
1424 NULL /*pfnReserved9*/,
1425 NULL /*pfnReserved10*/,
1426 PDM_DEVHLPR0_VERSION
1427};
1428#endif
1429
1430
1431/** @} */
1432
1433
1434/** @name PIC Ring-0 Helpers
1435 * @{
1436 */
1437
1438/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1439static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1440{
1441 PDMDEV_ASSERT_DEVINS(pDevIns);
1442 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1443 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1444 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1445 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1446}
1447
1448
1449/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1450static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1451{
1452 PDMDEV_ASSERT_DEVINS(pDevIns);
1453 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1454 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1455 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1456 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1457}
1458
1459
1460/** @interface_method_impl{PDMPICHLP,pfnLock} */
1461static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1462{
1463 PDMDEV_ASSERT_DEVINS(pDevIns);
1464 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1465}
1466
1467
1468/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1469static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1470{
1471 PDMDEV_ASSERT_DEVINS(pDevIns);
1472 pdmUnlock(pDevIns->Internal.s.pGVM);
1473}
1474
1475
1476/**
1477 * The Ring-0 PIC Helper Callbacks.
1478 */
1479extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1480{
1481 PDM_PICHLP_VERSION,
1482 pdmR0PicHlp_SetInterruptFF,
1483 pdmR0PicHlp_ClearInterruptFF,
1484 pdmR0PicHlp_Lock,
1485 pdmR0PicHlp_Unlock,
1486 PDM_PICHLP_VERSION
1487};
1488
1489/** @} */
1490
1491
1492/** @name I/O APIC Ring-0 Helpers
1493 * @{
1494 */
1495
1496/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
1497static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1498 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1499 uint8_t u8TriggerMode, uint32_t uTagSrc)
1500{
1501 PDMDEV_ASSERT_DEVINS(pDevIns);
1502 PGVM pGVM = pDevIns->Internal.s.pGVM;
1503 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1504 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1505 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1506}
1507
1508
1509/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
1510static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1511{
1512 PDMDEV_ASSERT_DEVINS(pDevIns);
1513 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1514}
1515
1516
1517/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
1518static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1519{
1520 PDMDEV_ASSERT_DEVINS(pDevIns);
1521 pdmUnlock(pDevIns->Internal.s.pGVM);
1522}
1523
1524
1525/** @interface_method_impl{PDMIOAPICHLP,pfnLockIsOwner} */
1526static DECLCALLBACK(bool) pdmR0IoApicHlp_LockIsOwner(PPDMDEVINS pDevIns)
1527{
1528 PDMDEV_ASSERT_DEVINS(pDevIns);
1529 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1530}
1531
1532
1533/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
1534static DECLCALLBACK(int) pdmR0IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1535{
1536 PDMDEV_ASSERT_DEVINS(pDevIns);
1537 LogFlow(("pdmR0IoApicHlp_IommuMsiRemap: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
1538 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
1539
1540#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1541 if (pdmIommuIsPresent(pDevIns))
1542 {
1543 PGVM pGVM = pDevIns->Internal.s.pGVM;
1544 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
1545 if (pIommu->pDevInsR0)
1546 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
1547 AssertMsgFailedReturn(("Implement queueing PDM task for remapping MSI via IOMMU in ring-3"), VERR_IOMMU_IPE_0);
1548 }
1549#else
1550 RT_NOREF(pDevIns, idDevice);
1551#endif
1552 return VERR_IOMMU_NOT_PRESENT;
1553}
1554
1555
1556/**
1557 * The Ring-0 I/O APIC Helper Callbacks.
1558 */
1559extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp =
1560{
1561 PDM_IOAPICHLP_VERSION,
1562 pdmR0IoApicHlp_ApicBusDeliver,
1563 pdmR0IoApicHlp_Lock,
1564 pdmR0IoApicHlp_Unlock,
1565 pdmR0IoApicHlp_LockIsOwner,
1566 pdmR0IoApicHlp_IommuMsiRemap,
1567 PDM_IOAPICHLP_VERSION
1568};
1569
1570/** @} */
1571
1572
1573
1574
1575/** @name PCI Bus Ring-0 Helpers
1576 * @{
1577 */
1578
1579/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1580static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1581{
1582 PDMDEV_ASSERT_DEVINS(pDevIns);
1583 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1584 PGVM pGVM = pDevIns->Internal.s.pGVM;
1585
1586 pdmLock(pGVM);
1587 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1588 pdmUnlock(pGVM);
1589}
1590
1591
1592/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1593static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
1594{
1595 PDMDEV_ASSERT_DEVINS(pDevIns);
1596 Log4(("pdmR0PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
1597 PGVM pGVM = pDevIns->Internal.s.pGVM;
1598
1599 if (pGVM->pdm.s.IoApic.pDevInsR0)
1600 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, iIrq, iLevel, uTagSrc);
1601 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1602 {
1603 /* queue for ring-3 execution. */
1604 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1605 if (pTask)
1606 {
1607 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1608 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1609 pTask->u.IoApicSetIrq.uBusDevFn = uBusDevFn;
1610 pTask->u.IoApicSetIrq.iIrq = iIrq;
1611 pTask->u.IoApicSetIrq.iLevel = iLevel;
1612 pTask->u.IoApicSetIrq.uTagSrc = uTagSrc;
1613
1614 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1615 }
1616 else
1617 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1618 }
1619}
1620
1621
1622/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1623static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
1624{
1625 PDMDEV_ASSERT_DEVINS(pDevIns);
1626 Assert(PCIBDF_IS_VALID(uBusDevFn));
1627 Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64,
1628 pMsi->Data.u32, uTagSrc));
1629 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, uBusDevFn, pMsi, uTagSrc);
1630}
1631
1632
1633/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1634static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1635{
1636 PDMDEV_ASSERT_DEVINS(pDevIns);
1637 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1638}
1639
1640
1641/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1642static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1643{
1644 PDMDEV_ASSERT_DEVINS(pDevIns);
1645 pdmUnlock(pDevIns->Internal.s.pGVM);
1646}
1647
1648
1649/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1650static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1651{
1652 PDMDEV_ASSERT_DEVINS(pDevIns);
1653 PGVM pGVM = pDevIns->Internal.s.pGVM;
1654 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1655 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1656 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1657 return pRetDevIns;
1658}
1659
1660
1661/**
1662 * The Ring-0 PCI Bus Helper Callbacks.
1663 */
1664extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1665{
1666 PDM_PCIHLPR0_VERSION,
1667 pdmR0PciHlp_IsaSetIrq,
1668 pdmR0PciHlp_IoApicSetIrq,
1669 pdmR0PciHlp_IoApicSendMsi,
1670 pdmR0PciHlp_Lock,
1671 pdmR0PciHlp_Unlock,
1672 pdmR0PciHlp_GetBusByNo,
1673 PDM_PCIHLPR0_VERSION, /* the end */
1674};
1675
1676/** @} */
1677
1678
1679/** @name IOMMU Ring-0 Helpers
1680 * @{
1681 */
1682
1683/** @interface_method_impl{PDMIOMMUHLPR0,pfnLock} */
1684static DECLCALLBACK(int) pdmR0IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
1685{
1686 PDMDEV_ASSERT_DEVINS(pDevIns);
1687 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1688}
1689
1690
1691/** @interface_method_impl{PDMIOMMUHLPR0,pfnUnlock} */
1692static DECLCALLBACK(void) pdmR0IommuHlp_Unlock(PPDMDEVINS pDevIns)
1693{
1694 PDMDEV_ASSERT_DEVINS(pDevIns);
1695 pdmUnlock(pDevIns->Internal.s.pGVM);
1696}
1697
1698
1699/** @interface_method_impl{PDMIOMMUHLPR0,pfnLockIsOwner} */
1700static DECLCALLBACK(bool) pdmR0IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
1701{
1702 PDMDEV_ASSERT_DEVINS(pDevIns);
1703 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1704}
1705
1706
1707/** @interface_method_impl{PDMIOMMUHLPR0,pfnSendMsi} */
1708static DECLCALLBACK(void) pdmR0IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
1709{
1710 PDMDEV_ASSERT_DEVINS(pDevIns);
1711 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, NIL_PCIBDF, pMsi, uTagSrc);
1712}
1713
1714
1715/**
1716 * The Ring-0 IOMMU Helper Callbacks.
1717 */
1718extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp =
1719{
1720 PDM_IOMMUHLPR0_VERSION,
1721 pdmR0IommuHlp_Lock,
1722 pdmR0IommuHlp_Unlock,
1723 pdmR0IommuHlp_LockIsOwner,
1724 pdmR0IommuHlp_SendMsi,
1725 PDM_IOMMUHLPR0_VERSION, /* the end */
1726};
1727
1728/** @} */
1729
1730
1731/** @name HPET Ring-0 Helpers
1732 * @{
1733 */
1734/* none */
1735
1736/**
1737 * The Ring-0 HPET Helper Callbacks.
1738 */
1739extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1740{
1741 PDM_HPETHLPR0_VERSION,
1742 PDM_HPETHLPR0_VERSION, /* the end */
1743};
1744
1745/** @} */
1746
1747
1748/** @name Raw PCI Ring-0 Helpers
1749 * @{
1750 */
1751/* none */
1752
1753/**
1754 * The Ring-0 PCI raw Helper Callbacks.
1755 */
1756extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1757{
1758 PDM_PCIRAWHLPR0_VERSION,
1759 PDM_PCIRAWHLPR0_VERSION, /* the end */
1760};
1761
1762/** @} */
1763
1764
1765
1766
1767/**
1768 * Sets an irq on the PIC and I/O APIC.
1769 *
1770 * @returns true if delivered, false if postponed.
1771 * @param pGVM The global (ring-0) VM structure.
1772 * @param iIrq The irq.
1773 * @param iLevel The new level.
1774 * @param uTagSrc The IRQ tag and source.
1775 *
1776 * @remarks The caller holds the PDM lock.
1777 */
1778DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1779{
1780 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1781 || !pGVM->pdm.s.IoApic.pDevInsR3)
1782 && ( pGVM->pdm.s.Pic.pDevInsR0
1783 || !pGVM->pdm.s.Pic.pDevInsR3)))
1784 {
1785 if (pGVM->pdm.s.Pic.pDevInsR0)
1786 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1787 if (pGVM->pdm.s.IoApic.pDevInsR0)
1788 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, NIL_PCIBDF, iIrq, iLevel, uTagSrc);
1789 return true;
1790 }
1791
1792 /* queue for ring-3 execution. */
1793 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1794 AssertReturn(pTask, false);
1795
1796 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1797 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1798 pTask->u.IsaSetIrq.uBusDevFn = NIL_PCIBDF;
1799 pTask->u.IsaSetIrq.iIrq = iIrq;
1800 pTask->u.IsaSetIrq.iLevel = iLevel;
1801 pTask->u.IsaSetIrq.uTagSrc = uTagSrc;
1802
1803 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1804 return false;
1805}
1806
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