VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp@ 91930

Last change on this file since 91930 was 91930, checked in by vboxsync, 3 years ago

VMM,Devices: Eliminate direct calls to IOMMmioResetRegion and IOMMmioMapMmio2Page APIs and introduce callbacks in the device helper callback table, bugref:10074
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File size: 75.2 KB
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1/* $Id: PDMR0DevHlp.cpp 91930 2021-10-21 10:12:30Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device Helper parts.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/vmcc.h>
32#include <VBox/vmm/gvmm.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/ctype.h>
40#include <iprt/string.h>
41
42#include "dtrace/VBoxVMM.h"
43#include "PDMInline.h"
44
45
46/*********************************************************************************************************************************
47* Global Variables *
48*********************************************************************************************************************************/
49RT_C_DECLS_BEGIN
50extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
51extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing;
52extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
53extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp;
54extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
55extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp;
56extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
57extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
58RT_C_DECLS_END
59
60
61/*********************************************************************************************************************************
62* Internal Functions *
63*********************************************************************************************************************************/
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
71static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
72 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
73 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
74 void *pvUser)
75{
76 PDMDEV_ASSERT_DEVINS(pDevIns);
77 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
78 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
79 PGVM pGVM = pDevIns->Internal.s.pGVM;
80 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
81 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
82
83 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
84
85 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
86 return rc;
87}
88
89
90/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
91static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
92 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
93{
94 PDMDEV_ASSERT_DEVINS(pDevIns);
95 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
96 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
97 PGVM pGVM = pDevIns->Internal.s.pGVM;
98 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
99 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
100
101 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
102
103 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
104 return rc;
105}
106
107
108/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
109static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
110 size_t offSub, size_t cbSub, void **ppvMapping)
111{
112 PDMDEV_ASSERT_DEVINS(pDevIns);
113 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
114 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
115 *ppvMapping = NULL;
116
117 PGVM pGVM = pDevIns->Internal.s.pGVM;
118 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
119 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
120
121 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
122
123 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
124 return rc;
125}
126
127
128/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
129static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
130 void *pvBuf, size_t cbRead, uint32_t fFlags)
131{
132 PDMDEV_ASSERT_DEVINS(pDevIns);
133 if (!pPciDev) /* NULL is an alias for the default PCI device. */
134 pPciDev = pDevIns->apPciDevs[0];
135 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
136 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
137
138#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
139 /*
140 * Just check the busmaster setting here and forward the request to the generic read helper.
141 */
142 if (PCIDevIsBusmaster(pPciDev))
143 { /* likely */ }
144 else
145 {
146 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n", pDevIns, pDevIns->iInstance,
147 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
148 memset(pvBuf, 0xff, cbRead);
149 return VERR_PDM_NOT_PCI_BUS_MASTER;
150 }
151#endif
152
153#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
154 int rc = pdmIommuMemAccessRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, fFlags);
155 if ( rc == VERR_IOMMU_NOT_PRESENT
156 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
157 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
158 else
159 return rc;
160#endif
161
162 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
163}
164
165
166/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
167static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
168 const void *pvBuf, size_t cbWrite, uint32_t fFlags)
169{
170 PDMDEV_ASSERT_DEVINS(pDevIns);
171 if (!pPciDev) /* NULL is an alias for the default PCI device. */
172 pPciDev = pDevIns->apPciDevs[0];
173 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
174 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
175
176#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
177 /*
178 * Just check the busmaster setting here and forward the request to the generic read helper.
179 */
180 if (PCIDevIsBusmaster(pPciDev))
181 { /* likely */ }
182 else
183 {
184 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n", pDevIns, pDevIns->iInstance,
185 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
186 return VERR_PDM_NOT_PCI_BUS_MASTER;
187 }
188#endif
189
190#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
191 int rc = pdmIommuMemAccessWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, fFlags);
192 if ( rc == VERR_IOMMU_NOT_PRESENT
193 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
194 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
195 else
196 return rc;
197#endif
198
199 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
200}
201
202
203/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
204static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
205{
206 PDMDEV_ASSERT_DEVINS(pDevIns);
207 if (!pPciDev) /* NULL is an alias for the default PCI device. */
208 pPciDev = pDevIns->apPciDevs[0];
209 AssertReturnVoid(pPciDev);
210 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
211 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
212 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
213
214 PGVM pGVM = pDevIns->Internal.s.pGVM;
215 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
216 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
217 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
218
219 pdmLock(pGVM);
220
221 uint32_t uTagSrc;
222 if (iLevel & PDM_IRQ_LEVEL_HIGH)
223 {
224 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
225 if (iLevel == PDM_IRQ_LEVEL_HIGH)
226 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
227 else
228 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
229 }
230 else
231 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
232
233 if (pPciBusR0->pDevInsR0)
234 {
235 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
236
237 pdmUnlock(pGVM);
238
239 if (iLevel == PDM_IRQ_LEVEL_LOW)
240 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
241 }
242 else
243 {
244 pdmUnlock(pGVM);
245
246 /* queue for ring-3 execution. */
247 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
248 AssertReturnVoid(pTask);
249
250 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
251 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
252 pTask->u.PciSetIrq.iIrq = iIrq;
253 pTask->u.PciSetIrq.iLevel = iLevel;
254 pTask->u.PciSetIrq.uTagSrc = uTagSrc;
255 pTask->u.PciSetIrq.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
256
257 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
258 }
259
260 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
261}
262
263
264/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
265static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
266{
267 PDMDEV_ASSERT_DEVINS(pDevIns);
268 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
269 PGVM pGVM = pDevIns->Internal.s.pGVM;
270
271 pdmLock(pGVM);
272 uint32_t uTagSrc;
273 if (iLevel & PDM_IRQ_LEVEL_HIGH)
274 {
275 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
276 if (iLevel == PDM_IRQ_LEVEL_HIGH)
277 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
278 else
279 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
280 }
281 else
282 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
283
284 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
285
286 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
287 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
288 pdmUnlock(pGVM);
289 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
290}
291
292
293/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
294static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
295{
296 RT_NOREF(fFlags);
297
298 PDMDEV_ASSERT_DEVINS(pDevIns);
299 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
300 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
301
302 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
303 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
304
305 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
306 return VBOXSTRICTRC_VAL(rcStrict);
307}
308
309
310/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
311static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
312{
313 RT_NOREF(fFlags);
314
315 PDMDEV_ASSERT_DEVINS(pDevIns);
316 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
317 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
318
319 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
320 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
321
322 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
323 return VBOXSTRICTRC_VAL(rcStrict);
324}
325
326
327/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
328static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
329{
330 PDMDEV_ASSERT_DEVINS(pDevIns);
331 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
332
333 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
334
335 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
336 return fEnabled;
337}
338
339
340/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
341static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
342{
343 PDMDEV_ASSERT_DEVINS(pDevIns);
344
345 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
346
347 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
348 return enmVMState;
349}
350
351
352/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
353static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
354{
355 PDMDEV_ASSERT_DEVINS(pDevIns);
356 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
357 return pDevIns->Internal.s.pGVM;
358}
359
360
361/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
362static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
363{
364 PDMDEV_ASSERT_DEVINS(pDevIns);
365 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
366 return VMMGetCpu(pDevIns->Internal.s.pGVM);
367}
368
369
370/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
371static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
372{
373 PDMDEV_ASSERT_DEVINS(pDevIns);
374 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
375 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
376 return idCpu;
377}
378
379
380/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
381static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
382{
383 PDMDEV_ASSERT_DEVINS(pDevIns);
384 return TMTimerFromMicro(pDevIns->Internal.s.pGVM, hTimer, cMicroSecs);
385}
386
387
388/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
389static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
390{
391 PDMDEV_ASSERT_DEVINS(pDevIns);
392 return TMTimerFromMilli(pDevIns->Internal.s.pGVM, hTimer, cMilliSecs);
393}
394
395
396/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
397static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
398{
399 PDMDEV_ASSERT_DEVINS(pDevIns);
400 return TMTimerFromNano(pDevIns->Internal.s.pGVM, hTimer, cNanoSecs);
401}
402
403/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
404static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
405{
406 PDMDEV_ASSERT_DEVINS(pDevIns);
407 return TMTimerGet(pDevIns->Internal.s.pGVM, hTimer);
408}
409
410
411/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
412static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
413{
414 PDMDEV_ASSERT_DEVINS(pDevIns);
415 return TMTimerGetFreq(pDevIns->Internal.s.pGVM, hTimer);
416}
417
418
419/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
420static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
421{
422 PDMDEV_ASSERT_DEVINS(pDevIns);
423 return TMTimerGetNano(pDevIns->Internal.s.pGVM, hTimer);
424}
425
426
427/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
428static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
429{
430 PDMDEV_ASSERT_DEVINS(pDevIns);
431 return TMTimerIsActive(pDevIns->Internal.s.pGVM, hTimer);
432}
433
434
435/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
436static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
437{
438 PDMDEV_ASSERT_DEVINS(pDevIns);
439 return TMTimerIsLockOwner(pDevIns->Internal.s.pGVM, hTimer);
440}
441
442
443/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock} */
444static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
445{
446 PDMDEV_ASSERT_DEVINS(pDevIns);
447 return TMTimerLock(pDevIns->Internal.s.pGVM, hTimer, rcBusy);
448}
449
450
451/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock2} */
452static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
453 PPDMCRITSECT pCritSect, int rcBusy)
454{
455 PDMDEV_ASSERT_DEVINS(pDevIns);
456 PGVM const pGVM = pDevIns->Internal.s.pGVM;
457 VBOXSTRICTRC rc = TMTimerLock(pGVM, hTimer, rcBusy);
458 if (rc == VINF_SUCCESS)
459 {
460 rc = PDMCritSectEnter(pGVM, pCritSect, rcBusy);
461 if (rc == VINF_SUCCESS)
462 return rc;
463 AssertRC(VBOXSTRICTRC_VAL(rc));
464 TMTimerUnlock(pGVM, hTimer);
465 }
466 else
467 AssertRC(VBOXSTRICTRC_VAL(rc));
468 return rc;
469}
470
471
472/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
473static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
474{
475 PDMDEV_ASSERT_DEVINS(pDevIns);
476 return TMTimerSet(pDevIns->Internal.s.pGVM, hTimer, uExpire);
477}
478
479
480/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
481static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
482{
483 PDMDEV_ASSERT_DEVINS(pDevIns);
484 return TMTimerSetFrequencyHint(pDevIns->Internal.s.pGVM, hTimer, uHz);
485}
486
487
488/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
489static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
490{
491 PDMDEV_ASSERT_DEVINS(pDevIns);
492 return TMTimerSetMicro(pDevIns->Internal.s.pGVM, hTimer, cMicrosToNext);
493}
494
495
496/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
497static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
498{
499 PDMDEV_ASSERT_DEVINS(pDevIns);
500 return TMTimerSetMillies(pDevIns->Internal.s.pGVM, hTimer, cMilliesToNext);
501}
502
503
504/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
505static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
506{
507 PDMDEV_ASSERT_DEVINS(pDevIns);
508 return TMTimerSetNano(pDevIns->Internal.s.pGVM, hTimer, cNanosToNext);
509}
510
511
512/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
513static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
514{
515 PDMDEV_ASSERT_DEVINS(pDevIns);
516 return TMTimerSetRelative(pDevIns->Internal.s.pGVM, hTimer, cTicksToNext, pu64Now);
517}
518
519
520/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
521static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
522{
523 PDMDEV_ASSERT_DEVINS(pDevIns);
524 return TMTimerStop(pDevIns->Internal.s.pGVM, hTimer);
525}
526
527
528/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock} */
529static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
530{
531 PDMDEV_ASSERT_DEVINS(pDevIns);
532 TMTimerUnlock(pDevIns->Internal.s.pGVM, hTimer);
533}
534
535
536/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock2} */
537static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
538{
539 PDMDEV_ASSERT_DEVINS(pDevIns);
540 PGVM const pGVM = pDevIns->Internal.s.pGVM;
541 TMTimerUnlock(pGVM, hTimer);
542 int rc = PDMCritSectLeave(pGVM, pCritSect);
543 AssertRC(rc);
544}
545
546
547/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
548static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
549{
550 PDMDEV_ASSERT_DEVINS(pDevIns);
551 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
552 return TMVirtualGet(pDevIns->Internal.s.pGVM);
553}
554
555
556/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
557static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
558{
559 PDMDEV_ASSERT_DEVINS(pDevIns);
560 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
561 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
562}
563
564
565/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
566static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
567{
568 PDMDEV_ASSERT_DEVINS(pDevIns);
569 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
570 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
571}
572
573
574/** Converts a queue handle to a ring-0 queue pointer. */
575DECLINLINE(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
576{
577 PDMDEV_ASSERT_DEVINS(pDevIns);
578 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
579}
580
581
582/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
583static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
584{
585 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
586}
587
588
589/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
590static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
591{
592 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
593}
594
595
596/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
597static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
598{
599 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
600}
601
602
603/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
604static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
605{
606 PDMDEV_ASSERT_DEVINS(pDevIns);
607 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
608
609 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
610
611 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
612 return rc;
613}
614
615
616/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
617static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
618{
619 PDMDEV_ASSERT_DEVINS(pDevIns);
620 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
621
622 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
623
624 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
625 return rc;
626}
627
628
629/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
630static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
631{
632 PDMDEV_ASSERT_DEVINS(pDevIns);
633 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
634 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
635
636 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
637
638 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
639 return rc;
640}
641
642
643/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
644static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
645{
646 PDMDEV_ASSERT_DEVINS(pDevIns);
647 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
648 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
649
650 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
651
652 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
653 return rc;
654}
655
656
657/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
658static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
659{
660 PDMDEV_ASSERT_DEVINS(pDevIns);
661 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
662 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
663
664 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
665
666 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
667 return rc;
668}
669
670
671/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
672static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
673{
674 PDMDEV_ASSERT_DEVINS(pDevIns);
675 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
676
677 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
678
679 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
680 return cNsResolution;
681}
682
683
684/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
685static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
686{
687 PDMDEV_ASSERT_DEVINS(pDevIns);
688 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
689
690 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
691
692 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
693 return rc;
694}
695
696
697/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
698static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
699{
700 PDMDEV_ASSERT_DEVINS(pDevIns);
701 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
702
703 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
704
705 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
706 return rc;
707}
708
709
710/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
711static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
712 uint32_t cMillies)
713{
714 PDMDEV_ASSERT_DEVINS(pDevIns);
715 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
716 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
717
718 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
719
720 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
721 return rc;
722}
723
724
725/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
726static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
727 uint64_t uNsTimeout)
728{
729 PDMDEV_ASSERT_DEVINS(pDevIns);
730 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
731 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
732
733 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
734
735 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
736 return rc;
737}
738
739
740/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
741static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
742 uint64_t cNsTimeout)
743{
744 PDMDEV_ASSERT_DEVINS(pDevIns);
745 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
746 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
747
748 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
749
750 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
751 return rc;
752}
753
754
755/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
756static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
757{
758 PDMDEV_ASSERT_DEVINS(pDevIns);
759 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
760
761 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
762
763 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
764 return cNsResolution;
765}
766
767
768/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
769static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
770{
771 PDMDEV_ASSERT_DEVINS(pDevIns);
772 PGVM pGVM = pDevIns->Internal.s.pGVM;
773
774 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
775 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
776 return pCritSect;
777}
778
779
780/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
781static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
782{
783 /*
784 * Validate input.
785 *
786 * Note! We only allow the automatically created default critical section
787 * to be replaced by this API.
788 */
789 PDMDEV_ASSERT_DEVINS(pDevIns);
790 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
791 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p\n",
792 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
793 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
794 PGVM pGVM = pDevIns->Internal.s.pGVM;
795
796 VM_ASSERT_EMT(pGVM);
797 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
798
799 /*
800 * Check that ring-3 has already done this, then effect the change.
801 */
802 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
803 pDevIns->pCritSectRoR0 = pCritSect;
804
805 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
806 return VINF_SUCCESS;
807}
808
809
810/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
811static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
812{
813 PDMDEV_ASSERT_DEVINS(pDevIns);
814 return PDMCritSectEnter(pDevIns->Internal.s.pGVM, pCritSect, rcBusy);
815}
816
817
818/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
819static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
820{
821 PDMDEV_ASSERT_DEVINS(pDevIns);
822 return PDMCritSectEnterDebug(pDevIns->Internal.s.pGVM, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
823}
824
825
826/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
827static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
828{
829 PDMDEV_ASSERT_DEVINS(pDevIns);
830 return PDMCritSectTryEnter(pDevIns->Internal.s.pGVM, pCritSect);
831}
832
833
834/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
835static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
836{
837 PDMDEV_ASSERT_DEVINS(pDevIns);
838 return PDMCritSectTryEnterDebug(pDevIns->Internal.s.pGVM, pCritSect, uId, RT_SRC_POS_ARGS);
839}
840
841
842/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
843static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
844{
845 PDMDEV_ASSERT_DEVINS(pDevIns);
846 return PDMCritSectLeave(pDevIns->Internal.s.pGVM, pCritSect);
847}
848
849
850/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
851static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
852{
853 PDMDEV_ASSERT_DEVINS(pDevIns);
854 return PDMCritSectIsOwner(pDevIns->Internal.s.pGVM, pCritSect);
855}
856
857
858/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
859static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
860{
861 PDMDEV_ASSERT_DEVINS(pDevIns);
862 RT_NOREF(pDevIns);
863 return PDMCritSectIsInitialized(pCritSect);
864}
865
866
867/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
868static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
869{
870 PDMDEV_ASSERT_DEVINS(pDevIns);
871 return PDMCritSectHasWaiters(pDevIns->Internal.s.pGVM, pCritSect);
872}
873
874
875/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
876static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
877{
878 PDMDEV_ASSERT_DEVINS(pDevIns);
879 RT_NOREF(pDevIns);
880 return PDMCritSectGetRecursion(pCritSect);
881}
882
883
884/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
885static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
886 SUPSEMEVENT hEventToSignal)
887{
888 PDMDEV_ASSERT_DEVINS(pDevIns);
889 RT_NOREF(pDevIns);
890 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
891}
892
893
894/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterShared} */
895static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
896{
897 PDMDEV_ASSERT_DEVINS(pDevIns);
898 return PDMCritSectRwEnterShared(pDevIns->Internal.s.pGVM, pCritSect, rcBusy);
899}
900
901
902/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterSharedDebug} */
903static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy,
904 RTHCUINTPTR uId, RT_SRC_POS_DECL)
905{
906 PDMDEV_ASSERT_DEVINS(pDevIns);
907 return PDMCritSectRwEnterSharedDebug(pDevIns->Internal.s.pGVM, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
908}
909
910
911
912/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterShared} */
913static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
914{
915 PDMDEV_ASSERT_DEVINS(pDevIns);
916 return PDMCritSectRwTryEnterShared(pDevIns->Internal.s.pGVM, pCritSect);
917}
918
919
920/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterSharedDebug} */
921static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect,
922 RTHCUINTPTR uId, RT_SRC_POS_DECL)
923{
924 PDMDEV_ASSERT_DEVINS(pDevIns);
925 return PDMCritSectRwTryEnterSharedDebug(pDevIns->Internal.s.pGVM, pCritSect, uId, RT_SRC_POS_ARGS);
926}
927
928
929/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwLeaveShared} */
930static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
931{
932 PDMDEV_ASSERT_DEVINS(pDevIns);
933 return PDMCritSectRwLeaveShared(pDevIns->Internal.s.pGVM, pCritSect);
934}
935
936
937/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterExcl} */
938static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
939{
940 PDMDEV_ASSERT_DEVINS(pDevIns);
941 return PDMCritSectRwEnterExcl(pDevIns->Internal.s.pGVM, pCritSect, rcBusy);
942}
943
944
945/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterExclDebug} */
946static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy,
947 RTHCUINTPTR uId, RT_SRC_POS_DECL)
948{
949 PDMDEV_ASSERT_DEVINS(pDevIns);
950 return PDMCritSectRwEnterExclDebug(pDevIns->Internal.s.pGVM, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
951}
952
953
954/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterExcl} */
955static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
956{
957 PDMDEV_ASSERT_DEVINS(pDevIns);
958 return PDMCritSectRwTryEnterExcl(pDevIns->Internal.s.pGVM, pCritSect);
959}
960
961
962/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterExclDebug} */
963static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect,
964 RTHCUINTPTR uId, RT_SRC_POS_DECL)
965{
966 PDMDEV_ASSERT_DEVINS(pDevIns);
967 return PDMCritSectRwTryEnterExclDebug(pDevIns->Internal.s.pGVM, pCritSect, uId, RT_SRC_POS_ARGS);
968}
969
970
971/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwLeaveExcl} */
972static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
973{
974 PDMDEV_ASSERT_DEVINS(pDevIns);
975 return PDMCritSectRwLeaveExcl(pDevIns->Internal.s.pGVM, pCritSect);
976}
977
978
979/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwIsWriteOwner} */
980static DECLCALLBACK(bool) pdmR0DevHlp_CritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
981{
982 PDMDEV_ASSERT_DEVINS(pDevIns);
983 return PDMCritSectRwIsWriteOwner(pDevIns->Internal.s.pGVM, pCritSect);
984}
985
986
987/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwIsReadOwner} */
988static DECLCALLBACK(bool) pdmR0DevHlp_CritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
989{
990 PDMDEV_ASSERT_DEVINS(pDevIns);
991 return PDMCritSectRwIsReadOwner(pDevIns->Internal.s.pGVM, pCritSect, fWannaHear);
992}
993
994
995/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwGetWriteRecursion} */
996static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
997{
998 PDMDEV_ASSERT_DEVINS(pDevIns);
999 RT_NOREF(pDevIns);
1000 return PDMCritSectRwGetWriteRecursion(pCritSect);
1001}
1002
1003
1004/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwGetWriterReadRecursion} */
1005static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
1006{
1007 PDMDEV_ASSERT_DEVINS(pDevIns);
1008 RT_NOREF(pDevIns);
1009 return PDMCritSectRwGetWriterReadRecursion(pCritSect);
1010}
1011
1012
1013/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwGetReadCount} */
1014static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
1015{
1016 PDMDEV_ASSERT_DEVINS(pDevIns);
1017 RT_NOREF(pDevIns);
1018 return PDMCritSectRwGetReadCount(pCritSect);
1019}
1020
1021
1022/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwIsInitialized} */
1023static DECLCALLBACK(bool) pdmR0DevHlp_CritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
1024{
1025 PDMDEV_ASSERT_DEVINS(pDevIns);
1026 RT_NOREF(pDevIns);
1027 return PDMCritSectRwIsInitialized(pCritSect);
1028}
1029
1030
1031/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
1032static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1033{
1034 PDMDEV_ASSERT_DEVINS(pDevIns);
1035 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
1036 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
1037 return hTraceBuf;
1038}
1039
1040
1041/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
1042static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
1043{
1044 PDMDEV_ASSERT_DEVINS(pDevIns);
1045 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
1046 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
1047 pPciBusReg->u32EndVersion, ppPciHlp));
1048 PGVM pGVM = pDevIns->Internal.s.pGVM;
1049
1050 /*
1051 * Validate input.
1052 */
1053 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
1054 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
1055 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1056 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
1057 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
1058 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1059
1060 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
1061
1062 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1063 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1064
1065 /* Check the shared bus data (registered earlier from ring-3): */
1066 uint32_t iBus = pPciBusReg->iBus;
1067 ASMCompilerBarrier();
1068 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
1069 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
1070 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
1071 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
1072 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
1073
1074 /* Check that the bus isn't already registered in ring-0: */
1075 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
1076 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
1077 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
1078 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1079 VERR_ALREADY_EXISTS);
1080
1081 /*
1082 * Do the registering.
1083 */
1084 pPciBusR0->iBus = iBus;
1085 pPciBusR0->uPadding0 = 0xbeefbeef;
1086 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1087 pPciBusR0->pDevInsR0 = pDevIns;
1088
1089 *ppPciHlp = &g_pdmR0PciHlp;
1090
1091 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1092 return VINF_SUCCESS;
1093}
1094
1095
1096/** @interface_method_impl{PDMDEVHLPR0,pfnIommuSetUpContext} */
1097static DECLCALLBACK(int) pdmR0DevHlp_IommuSetUpContext(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp)
1098{
1099 PDMDEV_ASSERT_DEVINS(pDevIns);
1100 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: pIommuReg=%p{.u32Version=%#x, u32TheEnd=%#x} ppIommuHlp=%p\n",
1101 pDevIns, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
1102 PGVM pGVM = pDevIns->Internal.s.pGVM;
1103
1104 /*
1105 * Validate input.
1106 */
1107 AssertPtrReturn(pIommuReg, VERR_INVALID_POINTER);
1108 AssertLogRelMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGCC_VERSION,
1109 ("%#x vs %#x\n", pIommuReg->u32Version, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1110 AssertPtrReturn(pIommuReg->pfnMemAccess, VERR_INVALID_POINTER);
1111 AssertPtrReturn(pIommuReg->pfnMemBulkAccess, VERR_INVALID_POINTER);
1112 AssertPtrReturn(pIommuReg->pfnMsiRemap, VERR_INVALID_POINTER);
1113 AssertLogRelMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGCC_VERSION,
1114 ("%#x vs %#x\n", pIommuReg->u32TheEnd, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1115
1116 AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
1117
1118 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1119 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1120
1121 /* Check the IOMMU shared data (registered earlier from ring-3). */
1122 uint32_t const idxIommu = pIommuReg->idxIommu;
1123 ASMCompilerBarrier();
1124 AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pGVM->pdm.s.aIommus), ("idxIommu=%#x\n", idxIommu), VERR_OUT_OF_RANGE);
1125 PPDMIOMMUR3 pIommuShared = &pGVM->pdm.s.aIommus[idxIommu];
1126 AssertLogRelMsgReturn(pIommuShared->idxIommu == idxIommu, ("%u vs %u\n", pIommuShared->idxIommu, idxIommu), VERR_INVALID_PARAMETER);
1127 AssertLogRelMsgReturn(pIommuShared->pDevInsR3 == pDevIns->pDevInsForR3,
1128 ("%p vs %p (idxIommu=%u)\n", pIommuShared->pDevInsR3, pDevIns->pDevInsForR3, idxIommu), VERR_NOT_OWNER);
1129
1130 /* Check that the IOMMU isn't already registered in ring-0. */
1131 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aIommus) == RT_ELEMENTS(pGVM->pdmr0.s.aIommus));
1132 PPDMIOMMUR0 pIommuR0 = &pGVM->pdmr0.s.aIommus[idxIommu];
1133 AssertLogRelMsgReturn(pIommuR0->pDevInsR0 == NULL,
1134 ("%p (caller pDevIns=%p, idxIommu=%u)\n", pIommuR0->pDevInsR0, pDevIns, idxIommu),
1135 VERR_ALREADY_EXISTS);
1136
1137 /*
1138 * Register.
1139 */
1140 pIommuR0->idxIommu = idxIommu;
1141 pIommuR0->uPadding0 = 0xdeaddead;
1142 pIommuR0->pDevInsR0 = pDevIns;
1143 pIommuR0->pfnMemAccess = pIommuReg->pfnMemAccess;
1144 pIommuR0->pfnMemBulkAccess = pIommuReg->pfnMemBulkAccess;
1145 pIommuR0->pfnMsiRemap = pIommuReg->pfnMsiRemap;
1146
1147 *ppIommuHlp = &g_pdmR0IommuHlp;
1148
1149 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1150 return VINF_SUCCESS;
1151}
1152
1153
1154/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1155static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1156{
1157 PDMDEV_ASSERT_DEVINS(pDevIns);
1158 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1159 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1160 PGVM pGVM = pDevIns->Internal.s.pGVM;
1161
1162 /*
1163 * Validate input.
1164 */
1165 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1166 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1167 VERR_VERSION_MISMATCH);
1168 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1169 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1170 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1171 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1172 VERR_VERSION_MISMATCH);
1173 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1174
1175 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1176 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1177
1178 /* Check that it's the same device as made the ring-3 registrations: */
1179 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1180 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1181
1182 /* Check that it isn't already registered in ring-0: */
1183 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1184 VERR_ALREADY_EXISTS);
1185
1186 /*
1187 * Take down the callbacks and instance.
1188 */
1189 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1190 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1191 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1192 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1193
1194 /* set the helper pointer and return. */
1195 *ppPicHlp = &g_pdmR0PicHlp;
1196 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1197 return VINF_SUCCESS;
1198}
1199
1200
1201/** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
1202static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
1203{
1204 PDMDEV_ASSERT_DEVINS(pDevIns);
1205 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1206 PGVM pGVM = pDevIns->Internal.s.pGVM;
1207
1208 /*
1209 * Validate input.
1210 */
1211 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1212 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1213
1214 /* Check that it's the same device as made the ring-3 registrations: */
1215 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR3 == pDevIns->pDevInsForR3,
1216 ("%p vs %p\n", pGVM->pdm.s.Apic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1217
1218 /* Check that it isn't already registered in ring-0: */
1219 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Apic.pDevInsR0, pDevIns),
1220 VERR_ALREADY_EXISTS);
1221
1222 /*
1223 * Take down the instance.
1224 */
1225 pGVM->pdm.s.Apic.pDevInsR0 = pDevIns;
1226 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1227
1228 /* set the helper pointer and return. */
1229 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1230 return VINF_SUCCESS;
1231}
1232
1233
1234/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSetUpContext} */
1235static DECLCALLBACK(int) pdmR0DevHlp_IoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
1236{
1237 PDMDEV_ASSERT_DEVINS(pDevIns);
1238 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
1239 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
1240 PGVM pGVM = pDevIns->Internal.s.pGVM;
1241
1242 /*
1243 * Validate input.
1244 */
1245 AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
1246 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
1247 VERR_VERSION_MISMATCH);
1248 AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
1249 AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
1250 AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
1251 AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
1252 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
1253 VERR_VERSION_MISMATCH);
1254 AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
1255
1256 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1257 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1258
1259 /* Check that it's the same device as made the ring-3 registrations: */
1260 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR3 == pDevIns->pDevInsForR3,
1261 ("%p vs %p\n", pGVM->pdm.s.IoApic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1262
1263 /* Check that it isn't already registered in ring-0: */
1264 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.IoApic.pDevInsR0, pDevIns),
1265 VERR_ALREADY_EXISTS);
1266
1267 /*
1268 * Take down the callbacks and instance.
1269 */
1270 pGVM->pdm.s.IoApic.pDevInsR0 = pDevIns;
1271 pGVM->pdm.s.IoApic.pfnSetIrqR0 = pIoApicReg->pfnSetIrq;
1272 pGVM->pdm.s.IoApic.pfnSendMsiR0 = pIoApicReg->pfnSendMsi;
1273 pGVM->pdm.s.IoApic.pfnSetEoiR0 = pIoApicReg->pfnSetEoi;
1274 Log(("PDM: Registered IOAPIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1275
1276 /* set the helper pointer and return. */
1277 *ppIoApicHlp = &g_pdmR0IoApicHlp;
1278 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1279 return VINF_SUCCESS;
1280}
1281
1282
1283/** @interface_method_impl{PDMDEVHLPR0,pfnHpetSetUpContext} */
1284static DECLCALLBACK(int) pdmR0DevHlp_HpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp)
1285{
1286 PDMDEV_ASSERT_DEVINS(pDevIns);
1287 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: pHpetReg=%p:{.u32Version=%#x, } ppHpetHlp=%p\n",
1288 pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg, pHpetReg->u32Version, ppHpetHlp));
1289 PGVM pGVM = pDevIns->Internal.s.pGVM;
1290
1291 /*
1292 * Validate input.
1293 */
1294 AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
1295 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
1296 VERR_VERSION_MISMATCH);
1297 AssertPtrReturn(ppHpetHlp, VERR_INVALID_POINTER);
1298
1299 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1300 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1301
1302 /* Check that it's the same device as made the ring-3 registrations: */
1303 AssertLogRelMsgReturn(pGVM->pdm.s.pHpet == pDevIns->pDevInsForR3, ("%p vs %p\n", pGVM->pdm.s.pHpet, pDevIns->pDevInsForR3),
1304 VERR_NOT_OWNER);
1305
1306 ///* Check that it isn't already registered in ring-0: */
1307 //AssertLogRelMsgReturn(pGVM->pdm.s.Hpet.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Hpet.pDevInsR0, pDevIns),
1308 // VERR_ALREADY_EXISTS);
1309
1310 /*
1311 * Nothing to take down here at present.
1312 */
1313 Log(("PDM: Registered HPET device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1314
1315 /* set the helper pointer and return. */
1316 *ppHpetHlp = &g_pdmR0HpetHlp;
1317 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1318 return VINF_SUCCESS;
1319}
1320
1321
1322/** @interface_method_impl{PDMDEVHLPR0,pfnPGMHandlerPhysicalPageTempOff} */
1323static DECLCALLBACK(int) pdmR0DevHlp_PGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
1324{
1325 PDMDEV_ASSERT_DEVINS(pDevIns);
1326 LogFlow(("pdmR0DevHlp_PGMHandlerPhysicalPageTempOff: caller='%s'/%d: GCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
1327
1328 int rc = PGMHandlerPhysicalPageTempOff(pDevIns->Internal.s.pGVM, GCPhys, GCPhysPage);
1329
1330 Log(("pdmR0DevHlp_PGMHandlerPhysicalPageTempOff: caller='%s'/%d: returns %Rrc\n",
1331 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1332 return rc;
1333}
1334
1335
1336/** @interface_method_impl{PDMDEVHLPR0,pfnMmioMapMmio2Page} */
1337static DECLCALLBACK(int) pdmR0DevHlp_MmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
1338 uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
1339{
1340 PDMDEV_ASSERT_DEVINS(pDevIns);
1341 LogFlow(("pdmR0DevHlp_MmioMapMmio2Page: caller='%s'/%d: hRegion=%RX64 offRegion=%RGp hMmio2=%RX64 offMmio2=%RGp fPageFlags=%RX64\n",
1342 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offRegion, hMmio2, offMmio2, fPageFlags));
1343
1344 int rc = IOMMmioMapMmio2Page(pDevIns->Internal.s.pGVM, pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
1345
1346 Log(("pdmR0DevHlp_MmioMapMmio2Page: caller='%s'/%d: returns %Rrc\n",
1347 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1348 return rc;
1349}
1350
1351
1352/** @interface_method_impl{PDMDEVHLPR0,pfnMmioResetRegion} */
1353static DECLCALLBACK(int) pdmR0DevHlp_MmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
1354{
1355 PDMDEV_ASSERT_DEVINS(pDevIns);
1356 LogFlow(("pdmR0DevHlp_MmioResetRegion: caller='%s'/%d: hRegion=%RX64\n",
1357 pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
1358
1359 int rc = IOMMmioResetRegion(pDevIns->Internal.s.pGVM, pDevIns, hRegion);
1360
1361 Log(("pdmR0DevHlp_MmioResetRegion: caller='%s'/%d: returns %Rrc\n",
1362 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1363 return rc;
1364}
1365
1366
1367/**
1368 * The Ring-0 Device Helper Callbacks.
1369 */
1370extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1371{
1372 PDM_DEVHLPR0_VERSION,
1373 pdmR0DevHlp_IoPortSetUpContextEx,
1374 pdmR0DevHlp_MmioSetUpContextEx,
1375 pdmR0DevHlp_Mmio2SetUpContext,
1376 pdmR0DevHlp_PCIPhysRead,
1377 pdmR0DevHlp_PCIPhysWrite,
1378 pdmR0DevHlp_PCISetIrq,
1379 pdmR0DevHlp_ISASetIrq,
1380 pdmR0DevHlp_PhysRead,
1381 pdmR0DevHlp_PhysWrite,
1382 pdmR0DevHlp_A20IsEnabled,
1383 pdmR0DevHlp_VMState,
1384 pdmR0DevHlp_GetVM,
1385 pdmR0DevHlp_GetVMCPU,
1386 pdmR0DevHlp_GetCurrentCpuId,
1387 pdmR0DevHlp_TimerFromMicro,
1388 pdmR0DevHlp_TimerFromMilli,
1389 pdmR0DevHlp_TimerFromNano,
1390 pdmR0DevHlp_TimerGet,
1391 pdmR0DevHlp_TimerGetFreq,
1392 pdmR0DevHlp_TimerGetNano,
1393 pdmR0DevHlp_TimerIsActive,
1394 pdmR0DevHlp_TimerIsLockOwner,
1395 pdmR0DevHlp_TimerLockClock,
1396 pdmR0DevHlp_TimerLockClock2,
1397 pdmR0DevHlp_TimerSet,
1398 pdmR0DevHlp_TimerSetFrequencyHint,
1399 pdmR0DevHlp_TimerSetMicro,
1400 pdmR0DevHlp_TimerSetMillies,
1401 pdmR0DevHlp_TimerSetNano,
1402 pdmR0DevHlp_TimerSetRelative,
1403 pdmR0DevHlp_TimerStop,
1404 pdmR0DevHlp_TimerUnlockClock,
1405 pdmR0DevHlp_TimerUnlockClock2,
1406 pdmR0DevHlp_TMTimeVirtGet,
1407 pdmR0DevHlp_TMTimeVirtGetFreq,
1408 pdmR0DevHlp_TMTimeVirtGetNano,
1409 pdmR0DevHlp_QueueAlloc,
1410 pdmR0DevHlp_QueueInsert,
1411 pdmR0DevHlp_QueueFlushIfNecessary,
1412 pdmR0DevHlp_TaskTrigger,
1413 pdmR0DevHlp_SUPSemEventSignal,
1414 pdmR0DevHlp_SUPSemEventWaitNoResume,
1415 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1416 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1417 pdmR0DevHlp_SUPSemEventGetResolution,
1418 pdmR0DevHlp_SUPSemEventMultiSignal,
1419 pdmR0DevHlp_SUPSemEventMultiReset,
1420 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1421 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1422 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1423 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1424 pdmR0DevHlp_CritSectGetNop,
1425 pdmR0DevHlp_SetDeviceCritSect,
1426 pdmR0DevHlp_CritSectEnter,
1427 pdmR0DevHlp_CritSectEnterDebug,
1428 pdmR0DevHlp_CritSectTryEnter,
1429 pdmR0DevHlp_CritSectTryEnterDebug,
1430 pdmR0DevHlp_CritSectLeave,
1431 pdmR0DevHlp_CritSectIsOwner,
1432 pdmR0DevHlp_CritSectIsInitialized,
1433 pdmR0DevHlp_CritSectHasWaiters,
1434 pdmR0DevHlp_CritSectGetRecursion,
1435 pdmR0DevHlp_CritSectScheduleExitEvent,
1436 pdmR0DevHlp_CritSectRwEnterShared,
1437 pdmR0DevHlp_CritSectRwEnterSharedDebug,
1438 pdmR0DevHlp_CritSectRwTryEnterShared,
1439 pdmR0DevHlp_CritSectRwTryEnterSharedDebug,
1440 pdmR0DevHlp_CritSectRwLeaveShared,
1441 pdmR0DevHlp_CritSectRwEnterExcl,
1442 pdmR0DevHlp_CritSectRwEnterExclDebug,
1443 pdmR0DevHlp_CritSectRwTryEnterExcl,
1444 pdmR0DevHlp_CritSectRwTryEnterExclDebug,
1445 pdmR0DevHlp_CritSectRwLeaveExcl,
1446 pdmR0DevHlp_CritSectRwIsWriteOwner,
1447 pdmR0DevHlp_CritSectRwIsReadOwner,
1448 pdmR0DevHlp_CritSectRwGetWriteRecursion,
1449 pdmR0DevHlp_CritSectRwGetWriterReadRecursion,
1450 pdmR0DevHlp_CritSectRwGetReadCount,
1451 pdmR0DevHlp_CritSectRwIsInitialized,
1452 pdmR0DevHlp_DBGFTraceBuf,
1453 pdmR0DevHlp_PCIBusSetUpContext,
1454 pdmR0DevHlp_IommuSetUpContext,
1455 pdmR0DevHlp_PICSetUpContext,
1456 pdmR0DevHlp_ApicSetUpContext,
1457 pdmR0DevHlp_IoApicSetUpContext,
1458 pdmR0DevHlp_HpetSetUpContext,
1459 pdmR0DevHlp_PGMHandlerPhysicalPageTempOff,
1460 pdmR0DevHlp_MmioMapMmio2Page,
1461 pdmR0DevHlp_MmioResetRegion,
1462 NULL /*pfnReserved1*/,
1463 NULL /*pfnReserved2*/,
1464 NULL /*pfnReserved3*/,
1465 NULL /*pfnReserved4*/,
1466 NULL /*pfnReserved5*/,
1467 NULL /*pfnReserved6*/,
1468 NULL /*pfnReserved7*/,
1469 NULL /*pfnReserved8*/,
1470 NULL /*pfnReserved9*/,
1471 NULL /*pfnReserved10*/,
1472 PDM_DEVHLPR0_VERSION
1473};
1474
1475
1476#ifdef VBOX_WITH_DBGF_TRACING
1477/**
1478 * The Ring-0 Device Helper Callbacks - tracing variant.
1479 */
1480extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing =
1481{
1482 PDM_DEVHLPR0_VERSION,
1483 pdmR0DevHlpTracing_IoPortSetUpContextEx,
1484 pdmR0DevHlpTracing_MmioSetUpContextEx,
1485 pdmR0DevHlp_Mmio2SetUpContext,
1486 pdmR0DevHlpTracing_PCIPhysRead,
1487 pdmR0DevHlpTracing_PCIPhysWrite,
1488 pdmR0DevHlpTracing_PCISetIrq,
1489 pdmR0DevHlpTracing_ISASetIrq,
1490 pdmR0DevHlp_PhysRead,
1491 pdmR0DevHlp_PhysWrite,
1492 pdmR0DevHlp_A20IsEnabled,
1493 pdmR0DevHlp_VMState,
1494 pdmR0DevHlp_GetVM,
1495 pdmR0DevHlp_GetVMCPU,
1496 pdmR0DevHlp_GetCurrentCpuId,
1497 pdmR0DevHlp_TimerFromMicro,
1498 pdmR0DevHlp_TimerFromMilli,
1499 pdmR0DevHlp_TimerFromNano,
1500 pdmR0DevHlp_TimerGet,
1501 pdmR0DevHlp_TimerGetFreq,
1502 pdmR0DevHlp_TimerGetNano,
1503 pdmR0DevHlp_TimerIsActive,
1504 pdmR0DevHlp_TimerIsLockOwner,
1505 pdmR0DevHlp_TimerLockClock,
1506 pdmR0DevHlp_TimerLockClock2,
1507 pdmR0DevHlp_TimerSet,
1508 pdmR0DevHlp_TimerSetFrequencyHint,
1509 pdmR0DevHlp_TimerSetMicro,
1510 pdmR0DevHlp_TimerSetMillies,
1511 pdmR0DevHlp_TimerSetNano,
1512 pdmR0DevHlp_TimerSetRelative,
1513 pdmR0DevHlp_TimerStop,
1514 pdmR0DevHlp_TimerUnlockClock,
1515 pdmR0DevHlp_TimerUnlockClock2,
1516 pdmR0DevHlp_TMTimeVirtGet,
1517 pdmR0DevHlp_TMTimeVirtGetFreq,
1518 pdmR0DevHlp_TMTimeVirtGetNano,
1519 pdmR0DevHlp_QueueAlloc,
1520 pdmR0DevHlp_QueueInsert,
1521 pdmR0DevHlp_QueueFlushIfNecessary,
1522 pdmR0DevHlp_TaskTrigger,
1523 pdmR0DevHlp_SUPSemEventSignal,
1524 pdmR0DevHlp_SUPSemEventWaitNoResume,
1525 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1526 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1527 pdmR0DevHlp_SUPSemEventGetResolution,
1528 pdmR0DevHlp_SUPSemEventMultiSignal,
1529 pdmR0DevHlp_SUPSemEventMultiReset,
1530 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1531 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1532 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1533 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1534 pdmR0DevHlp_CritSectGetNop,
1535 pdmR0DevHlp_SetDeviceCritSect,
1536 pdmR0DevHlp_CritSectEnter,
1537 pdmR0DevHlp_CritSectEnterDebug,
1538 pdmR0DevHlp_CritSectTryEnter,
1539 pdmR0DevHlp_CritSectTryEnterDebug,
1540 pdmR0DevHlp_CritSectLeave,
1541 pdmR0DevHlp_CritSectIsOwner,
1542 pdmR0DevHlp_CritSectIsInitialized,
1543 pdmR0DevHlp_CritSectHasWaiters,
1544 pdmR0DevHlp_CritSectGetRecursion,
1545 pdmR0DevHlp_CritSectScheduleExitEvent,
1546 pdmR0DevHlp_CritSectRwEnterShared,
1547 pdmR0DevHlp_CritSectRwEnterSharedDebug,
1548 pdmR0DevHlp_CritSectRwTryEnterShared,
1549 pdmR0DevHlp_CritSectRwTryEnterSharedDebug,
1550 pdmR0DevHlp_CritSectRwLeaveShared,
1551 pdmR0DevHlp_CritSectRwEnterExcl,
1552 pdmR0DevHlp_CritSectRwEnterExclDebug,
1553 pdmR0DevHlp_CritSectRwTryEnterExcl,
1554 pdmR0DevHlp_CritSectRwTryEnterExclDebug,
1555 pdmR0DevHlp_CritSectRwLeaveExcl,
1556 pdmR0DevHlp_CritSectRwIsWriteOwner,
1557 pdmR0DevHlp_CritSectRwIsReadOwner,
1558 pdmR0DevHlp_CritSectRwGetWriteRecursion,
1559 pdmR0DevHlp_CritSectRwGetWriterReadRecursion,
1560 pdmR0DevHlp_CritSectRwGetReadCount,
1561 pdmR0DevHlp_CritSectRwIsInitialized,
1562 pdmR0DevHlp_DBGFTraceBuf,
1563 pdmR0DevHlp_PCIBusSetUpContext,
1564 pdmR0DevHlp_IommuSetUpContext,
1565 pdmR0DevHlp_PICSetUpContext,
1566 pdmR0DevHlp_ApicSetUpContext,
1567 pdmR0DevHlp_IoApicSetUpContext,
1568 pdmR0DevHlp_HpetSetUpContext,
1569 pdmR0DevHlp_PGMHandlerPhysicalPageTempOff,
1570 pdmR0DevHlp_MmioMapMmio2Page,
1571 pdmR0DevHlp_MmioResetRegion,
1572 NULL /*pfnReserved1*/,
1573 NULL /*pfnReserved2*/,
1574 NULL /*pfnReserved3*/,
1575 NULL /*pfnReserved4*/,
1576 NULL /*pfnReserved5*/,
1577 NULL /*pfnReserved6*/,
1578 NULL /*pfnReserved7*/,
1579 NULL /*pfnReserved8*/,
1580 NULL /*pfnReserved9*/,
1581 NULL /*pfnReserved10*/,
1582 PDM_DEVHLPR0_VERSION
1583};
1584#endif
1585
1586
1587/** @} */
1588
1589
1590/** @name PIC Ring-0 Helpers
1591 * @{
1592 */
1593
1594/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1595static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1596{
1597 PDMDEV_ASSERT_DEVINS(pDevIns);
1598 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1599 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1600 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1601 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1602}
1603
1604
1605/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1606static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1607{
1608 PDMDEV_ASSERT_DEVINS(pDevIns);
1609 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1610 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1611 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1612 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1613}
1614
1615
1616/** @interface_method_impl{PDMPICHLP,pfnLock} */
1617static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1618{
1619 PDMDEV_ASSERT_DEVINS(pDevIns);
1620 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1621}
1622
1623
1624/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1625static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1626{
1627 PDMDEV_ASSERT_DEVINS(pDevIns);
1628 pdmUnlock(pDevIns->Internal.s.pGVM);
1629}
1630
1631
1632/**
1633 * The Ring-0 PIC Helper Callbacks.
1634 */
1635extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1636{
1637 PDM_PICHLP_VERSION,
1638 pdmR0PicHlp_SetInterruptFF,
1639 pdmR0PicHlp_ClearInterruptFF,
1640 pdmR0PicHlp_Lock,
1641 pdmR0PicHlp_Unlock,
1642 PDM_PICHLP_VERSION
1643};
1644
1645/** @} */
1646
1647
1648/** @name I/O APIC Ring-0 Helpers
1649 * @{
1650 */
1651
1652/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
1653static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1654 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1655 uint8_t u8TriggerMode, uint32_t uTagSrc)
1656{
1657 PDMDEV_ASSERT_DEVINS(pDevIns);
1658 PGVM pGVM = pDevIns->Internal.s.pGVM;
1659 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1660 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1661 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1662}
1663
1664
1665/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
1666static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1667{
1668 PDMDEV_ASSERT_DEVINS(pDevIns);
1669 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1670}
1671
1672
1673/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
1674static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1675{
1676 PDMDEV_ASSERT_DEVINS(pDevIns);
1677 pdmUnlock(pDevIns->Internal.s.pGVM);
1678}
1679
1680
1681/** @interface_method_impl{PDMIOAPICHLP,pfnLockIsOwner} */
1682static DECLCALLBACK(bool) pdmR0IoApicHlp_LockIsOwner(PPDMDEVINS pDevIns)
1683{
1684 PDMDEV_ASSERT_DEVINS(pDevIns);
1685 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1686}
1687
1688
1689/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
1690static DECLCALLBACK(int) pdmR0IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1691{
1692 PDMDEV_ASSERT_DEVINS(pDevIns);
1693 LogFlow(("pdmR0IoApicHlp_IommuMsiRemap: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
1694 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
1695
1696#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1697 if (pdmIommuIsPresent(pDevIns))
1698 {
1699 PGVM pGVM = pDevIns->Internal.s.pGVM;
1700 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
1701 if (pIommu->pDevInsR0)
1702 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
1703 AssertMsgFailedReturn(("Implement queueing PDM task for remapping MSI via IOMMU in ring-3"), VERR_IOMMU_IPE_0);
1704 }
1705#else
1706 RT_NOREF(pDevIns, idDevice);
1707#endif
1708 return VERR_IOMMU_NOT_PRESENT;
1709}
1710
1711
1712/**
1713 * The Ring-0 I/O APIC Helper Callbacks.
1714 */
1715extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp =
1716{
1717 PDM_IOAPICHLP_VERSION,
1718 pdmR0IoApicHlp_ApicBusDeliver,
1719 pdmR0IoApicHlp_Lock,
1720 pdmR0IoApicHlp_Unlock,
1721 pdmR0IoApicHlp_LockIsOwner,
1722 pdmR0IoApicHlp_IommuMsiRemap,
1723 PDM_IOAPICHLP_VERSION
1724};
1725
1726/** @} */
1727
1728
1729
1730
1731/** @name PCI Bus Ring-0 Helpers
1732 * @{
1733 */
1734
1735/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1736static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1737{
1738 PDMDEV_ASSERT_DEVINS(pDevIns);
1739 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1740 PGVM pGVM = pDevIns->Internal.s.pGVM;
1741
1742 pdmLock(pGVM);
1743 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1744 pdmUnlock(pGVM);
1745}
1746
1747
1748/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1749static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
1750{
1751 PDMDEV_ASSERT_DEVINS(pDevIns);
1752 Log4(("pdmR0PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
1753 PGVM pGVM = pDevIns->Internal.s.pGVM;
1754
1755 if (pGVM->pdm.s.IoApic.pDevInsR0)
1756 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, iIrq, iLevel, uTagSrc);
1757 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1758 {
1759 /* queue for ring-3 execution. */
1760 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1761 if (pTask)
1762 {
1763 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1764 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1765 pTask->u.IoApicSetIrq.uBusDevFn = uBusDevFn;
1766 pTask->u.IoApicSetIrq.iIrq = iIrq;
1767 pTask->u.IoApicSetIrq.iLevel = iLevel;
1768 pTask->u.IoApicSetIrq.uTagSrc = uTagSrc;
1769
1770 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1771 }
1772 else
1773 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1774 }
1775}
1776
1777
1778/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1779static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
1780{
1781 PDMDEV_ASSERT_DEVINS(pDevIns);
1782 Assert(PCIBDF_IS_VALID(uBusDevFn));
1783 Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64,
1784 pMsi->Data.u32, uTagSrc));
1785 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, uBusDevFn, pMsi, uTagSrc);
1786}
1787
1788
1789/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1790static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1791{
1792 PDMDEV_ASSERT_DEVINS(pDevIns);
1793 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1794}
1795
1796
1797/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1798static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1799{
1800 PDMDEV_ASSERT_DEVINS(pDevIns);
1801 pdmUnlock(pDevIns->Internal.s.pGVM);
1802}
1803
1804
1805/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1806static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1807{
1808 PDMDEV_ASSERT_DEVINS(pDevIns);
1809 PGVM pGVM = pDevIns->Internal.s.pGVM;
1810 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1811 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1812 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1813 return pRetDevIns;
1814}
1815
1816
1817/**
1818 * The Ring-0 PCI Bus Helper Callbacks.
1819 */
1820extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1821{
1822 PDM_PCIHLPR0_VERSION,
1823 pdmR0PciHlp_IsaSetIrq,
1824 pdmR0PciHlp_IoApicSetIrq,
1825 pdmR0PciHlp_IoApicSendMsi,
1826 pdmR0PciHlp_Lock,
1827 pdmR0PciHlp_Unlock,
1828 pdmR0PciHlp_GetBusByNo,
1829 PDM_PCIHLPR0_VERSION, /* the end */
1830};
1831
1832/** @} */
1833
1834
1835/** @name IOMMU Ring-0 Helpers
1836 * @{
1837 */
1838
1839/** @interface_method_impl{PDMIOMMUHLPR0,pfnLock} */
1840static DECLCALLBACK(int) pdmR0IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
1841{
1842 PDMDEV_ASSERT_DEVINS(pDevIns);
1843 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1844}
1845
1846
1847/** @interface_method_impl{PDMIOMMUHLPR0,pfnUnlock} */
1848static DECLCALLBACK(void) pdmR0IommuHlp_Unlock(PPDMDEVINS pDevIns)
1849{
1850 PDMDEV_ASSERT_DEVINS(pDevIns);
1851 pdmUnlock(pDevIns->Internal.s.pGVM);
1852}
1853
1854
1855/** @interface_method_impl{PDMIOMMUHLPR0,pfnLockIsOwner} */
1856static DECLCALLBACK(bool) pdmR0IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
1857{
1858 PDMDEV_ASSERT_DEVINS(pDevIns);
1859 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1860}
1861
1862
1863/** @interface_method_impl{PDMIOMMUHLPR0,pfnSendMsi} */
1864static DECLCALLBACK(void) pdmR0IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
1865{
1866 PDMDEV_ASSERT_DEVINS(pDevIns);
1867 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, NIL_PCIBDF, pMsi, uTagSrc);
1868}
1869
1870
1871/**
1872 * The Ring-0 IOMMU Helper Callbacks.
1873 */
1874extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp =
1875{
1876 PDM_IOMMUHLPR0_VERSION,
1877 pdmR0IommuHlp_Lock,
1878 pdmR0IommuHlp_Unlock,
1879 pdmR0IommuHlp_LockIsOwner,
1880 pdmR0IommuHlp_SendMsi,
1881 PDM_IOMMUHLPR0_VERSION, /* the end */
1882};
1883
1884/** @} */
1885
1886
1887/** @name HPET Ring-0 Helpers
1888 * @{
1889 */
1890/* none */
1891
1892/**
1893 * The Ring-0 HPET Helper Callbacks.
1894 */
1895extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1896{
1897 PDM_HPETHLPR0_VERSION,
1898 PDM_HPETHLPR0_VERSION, /* the end */
1899};
1900
1901/** @} */
1902
1903
1904/** @name Raw PCI Ring-0 Helpers
1905 * @{
1906 */
1907/* none */
1908
1909/**
1910 * The Ring-0 PCI raw Helper Callbacks.
1911 */
1912extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1913{
1914 PDM_PCIRAWHLPR0_VERSION,
1915 PDM_PCIRAWHLPR0_VERSION, /* the end */
1916};
1917
1918/** @} */
1919
1920
1921
1922
1923/**
1924 * Sets an irq on the PIC and I/O APIC.
1925 *
1926 * @returns true if delivered, false if postponed.
1927 * @param pGVM The global (ring-0) VM structure.
1928 * @param iIrq The irq.
1929 * @param iLevel The new level.
1930 * @param uTagSrc The IRQ tag and source.
1931 *
1932 * @remarks The caller holds the PDM lock.
1933 */
1934DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1935{
1936 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1937 || !pGVM->pdm.s.IoApic.pDevInsR3)
1938 && ( pGVM->pdm.s.Pic.pDevInsR0
1939 || !pGVM->pdm.s.Pic.pDevInsR3)))
1940 {
1941 if (pGVM->pdm.s.Pic.pDevInsR0)
1942 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1943 if (pGVM->pdm.s.IoApic.pDevInsR0)
1944 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, NIL_PCIBDF, iIrq, iLevel, uTagSrc);
1945 return true;
1946 }
1947
1948 /* queue for ring-3 execution. */
1949 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1950 AssertReturn(pTask, false);
1951
1952 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1953 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1954 pTask->u.IsaSetIrq.uBusDevFn = NIL_PCIBDF;
1955 pTask->u.IsaSetIrq.iIrq = iIrq;
1956 pTask->u.IsaSetIrq.iLevel = iLevel;
1957 pTask->u.IsaSetIrq.uTagSrc = uTagSrc;
1958
1959 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1960 return false;
1961}
1962
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