VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp@ 95134

Last change on this file since 95134 was 93650, checked in by vboxsync, 3 years ago

VMM/PGM,*: Split the physical access handler type registration into separate ring-0 and ring-3 steps, expanding the type to 64-bit. bugref:10094
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File size: 77.5 KB
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1/* $Id: PDMR0DevHlp.cpp 93650 2022-02-08 10:43:53Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device Helper parts.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/vmcc.h>
32#include <VBox/vmm/gvmm.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/sup.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/ctype.h>
40#include <iprt/string.h>
41
42#include "dtrace/VBoxVMM.h"
43#include "PDMInline.h"
44
45
46/*********************************************************************************************************************************
47* Global Variables *
48*********************************************************************************************************************************/
49RT_C_DECLS_BEGIN
50extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
51extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing;
52extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
53extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp;
54extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
55extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp;
56extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
57extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
58RT_C_DECLS_END
59
60
61/*********************************************************************************************************************************
62* Internal Functions *
63*********************************************************************************************************************************/
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
71static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
72 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
73 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
74 void *pvUser)
75{
76 PDMDEV_ASSERT_DEVINS(pDevIns);
77 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
78 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
79 PGVM pGVM = pDevIns->Internal.s.pGVM;
80 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
81 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
82
83 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
84
85 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
86 return rc;
87}
88
89
90/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
91static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
92 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
93{
94 PDMDEV_ASSERT_DEVINS(pDevIns);
95 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
96 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
97 PGVM pGVM = pDevIns->Internal.s.pGVM;
98 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
99 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
100
101 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
102
103 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
104 return rc;
105}
106
107
108/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
109static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
110 size_t offSub, size_t cbSub, void **ppvMapping)
111{
112 PDMDEV_ASSERT_DEVINS(pDevIns);
113 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
114 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
115 *ppvMapping = NULL;
116
117 PGVM pGVM = pDevIns->Internal.s.pGVM;
118 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
119 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
120
121 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
122
123 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
124 return rc;
125}
126
127
128/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
129static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
130 void *pvBuf, size_t cbRead, uint32_t fFlags)
131{
132 PDMDEV_ASSERT_DEVINS(pDevIns);
133 if (!pPciDev) /* NULL is an alias for the default PCI device. */
134 pPciDev = pDevIns->apPciDevs[0];
135 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
136 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
137
138#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
139 /*
140 * Just check the busmaster setting here and forward the request to the generic read helper.
141 */
142 if (PCIDevIsBusmaster(pPciDev))
143 { /* likely */ }
144 else
145 {
146 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n", pDevIns, pDevIns->iInstance,
147 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
148 memset(pvBuf, 0xff, cbRead);
149 return VERR_PDM_NOT_PCI_BUS_MASTER;
150 }
151#endif
152
153#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
154 int rc = pdmIommuMemAccessRead(pDevIns, pPciDev, GCPhys, pvBuf, cbRead, fFlags);
155 if ( rc == VERR_IOMMU_NOT_PRESENT
156 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
157 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
158 else
159 return rc;
160#endif
161
162 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead, fFlags);
163}
164
165
166/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
167static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
168 const void *pvBuf, size_t cbWrite, uint32_t fFlags)
169{
170 PDMDEV_ASSERT_DEVINS(pDevIns);
171 if (!pPciDev) /* NULL is an alias for the default PCI device. */
172 pPciDev = pDevIns->apPciDevs[0];
173 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
174 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
175
176#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
177 /*
178 * Just check the busmaster setting here and forward the request to the generic read helper.
179 */
180 if (PCIDevIsBusmaster(pPciDev))
181 { /* likely */ }
182 else
183 {
184 LogFunc(("caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n", pDevIns, pDevIns->iInstance,
185 VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
186 return VERR_PDM_NOT_PCI_BUS_MASTER;
187 }
188#endif
189
190#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
191 int rc = pdmIommuMemAccessWrite(pDevIns, pPciDev, GCPhys, pvBuf, cbWrite, fFlags);
192 if ( rc == VERR_IOMMU_NOT_PRESENT
193 || rc == VERR_IOMMU_CANNOT_CALL_SELF)
194 { /* likely - ASSUMING most VMs won't be configured with an IOMMU. */ }
195 else
196 return rc;
197#endif
198
199 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite, fFlags);
200}
201
202
203/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
204static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
205{
206 PDMDEV_ASSERT_DEVINS(pDevIns);
207 if (!pPciDev) /* NULL is an alias for the default PCI device. */
208 pPciDev = pDevIns->apPciDevs[0];
209 AssertReturnVoid(pPciDev);
210 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
211 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
212 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
213
214 PGVM pGVM = pDevIns->Internal.s.pGVM;
215 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
216 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
217 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
218
219 pdmLock(pGVM);
220
221 uint32_t uTagSrc;
222 if (iLevel & PDM_IRQ_LEVEL_HIGH)
223 {
224 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
225 if (iLevel == PDM_IRQ_LEVEL_HIGH)
226 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
227 else
228 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
229 }
230 else
231 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
232
233 if (pPciBusR0->pDevInsR0)
234 {
235 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
236
237 pdmUnlock(pGVM);
238
239 if (iLevel == PDM_IRQ_LEVEL_LOW)
240 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
241 }
242 else
243 {
244 pdmUnlock(pGVM);
245
246 /* queue for ring-3 execution. */
247 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM, pGVM->pdm.s.hDevHlpQueue, pGVM);
248 AssertReturnVoid(pTask);
249
250 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
251 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
252 pTask->u.PciSetIrq.iIrq = iIrq;
253 pTask->u.PciSetIrq.iLevel = iLevel;
254 pTask->u.PciSetIrq.uTagSrc = uTagSrc;
255 pTask->u.PciSetIrq.idxPciDev = pPciDev->Int.s.idxSubDev;
256
257 PDMQueueInsert(pGVM, pGVM->pdm.s.hDevHlpQueue, pGVM, &pTask->Core);
258 }
259
260 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
261}
262
263
264/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
265static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
266{
267 PDMDEV_ASSERT_DEVINS(pDevIns);
268 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
269 PGVM pGVM = pDevIns->Internal.s.pGVM;
270
271 pdmLock(pGVM);
272 uint32_t uTagSrc;
273 if (iLevel & PDM_IRQ_LEVEL_HIGH)
274 {
275 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
276 if (iLevel == PDM_IRQ_LEVEL_HIGH)
277 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
278 else
279 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
280 }
281 else
282 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
283
284 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
285
286 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
287 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
288 pdmUnlock(pGVM);
289 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
290}
291
292
293/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
294static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead, uint32_t fFlags)
295{
296 RT_NOREF(fFlags);
297
298 PDMDEV_ASSERT_DEVINS(pDevIns);
299 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
300 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
301
302 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
303 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
304
305 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
306 return VBOXSTRICTRC_VAL(rcStrict);
307}
308
309
310/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
311static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite, uint32_t fFlags)
312{
313 RT_NOREF(fFlags);
314
315 PDMDEV_ASSERT_DEVINS(pDevIns);
316 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
317 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
318
319 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
320 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
321
322 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
323 return VBOXSTRICTRC_VAL(rcStrict);
324}
325
326
327/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
328static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
329{
330 PDMDEV_ASSERT_DEVINS(pDevIns);
331 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
332
333 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
334
335 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
336 return fEnabled;
337}
338
339
340/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
341static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
342{
343 PDMDEV_ASSERT_DEVINS(pDevIns);
344
345 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
346
347 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
348 return enmVMState;
349}
350
351
352/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
353static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
354{
355 PDMDEV_ASSERT_DEVINS(pDevIns);
356 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
357 return pDevIns->Internal.s.pGVM;
358}
359
360
361/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
362static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
363{
364 PDMDEV_ASSERT_DEVINS(pDevIns);
365 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
366 return VMMGetCpu(pDevIns->Internal.s.pGVM);
367}
368
369
370/** @interface_method_impl{PDMDEVHLPR0,pfnGetCurrentCpuId} */
371static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
372{
373 PDMDEV_ASSERT_DEVINS(pDevIns);
374 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
375 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
376 return idCpu;
377}
378
379
380/** @interface_method_impl{PDMDEVHLPR0,pfnGetMainExecutionEngine} */
381static DECLCALLBACK(uint8_t) pdmR0DevHlp_GetMainExecutionEngine(PPDMDEVINS pDevIns)
382{
383 PDMDEV_ASSERT_DEVINS(pDevIns);
384 LogFlow(("pdmR0DevHlp_GetMainExecutionEngine: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
385 return pDevIns->Internal.s.pGVM->bMainExecutionEngine;
386}
387
388
389/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
390static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
391{
392 PDMDEV_ASSERT_DEVINS(pDevIns);
393 return TMTimerFromMicro(pDevIns->Internal.s.pGVM, hTimer, cMicroSecs);
394}
395
396
397/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
398static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
399{
400 PDMDEV_ASSERT_DEVINS(pDevIns);
401 return TMTimerFromMilli(pDevIns->Internal.s.pGVM, hTimer, cMilliSecs);
402}
403
404
405/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
406static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
407{
408 PDMDEV_ASSERT_DEVINS(pDevIns);
409 return TMTimerFromNano(pDevIns->Internal.s.pGVM, hTimer, cNanoSecs);
410}
411
412/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
413static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
414{
415 PDMDEV_ASSERT_DEVINS(pDevIns);
416 return TMTimerGet(pDevIns->Internal.s.pGVM, hTimer);
417}
418
419
420/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
421static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
422{
423 PDMDEV_ASSERT_DEVINS(pDevIns);
424 return TMTimerGetFreq(pDevIns->Internal.s.pGVM, hTimer);
425}
426
427
428/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
429static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
430{
431 PDMDEV_ASSERT_DEVINS(pDevIns);
432 return TMTimerGetNano(pDevIns->Internal.s.pGVM, hTimer);
433}
434
435
436/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
437static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
438{
439 PDMDEV_ASSERT_DEVINS(pDevIns);
440 return TMTimerIsActive(pDevIns->Internal.s.pGVM, hTimer);
441}
442
443
444/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
445static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
446{
447 PDMDEV_ASSERT_DEVINS(pDevIns);
448 return TMTimerIsLockOwner(pDevIns->Internal.s.pGVM, hTimer);
449}
450
451
452/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock} */
453static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
454{
455 PDMDEV_ASSERT_DEVINS(pDevIns);
456 return TMTimerLock(pDevIns->Internal.s.pGVM, hTimer, rcBusy);
457}
458
459
460/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLockClock2} */
461static DECLCALLBACK(VBOXSTRICTRC) pdmR0DevHlp_TimerLockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer,
462 PPDMCRITSECT pCritSect, int rcBusy)
463{
464 PDMDEV_ASSERT_DEVINS(pDevIns);
465 PGVM const pGVM = pDevIns->Internal.s.pGVM;
466 VBOXSTRICTRC rc = TMTimerLock(pGVM, hTimer, rcBusy);
467 if (rc == VINF_SUCCESS)
468 {
469 rc = PDMCritSectEnter(pGVM, pCritSect, rcBusy);
470 if (rc == VINF_SUCCESS)
471 return rc;
472 AssertRC(VBOXSTRICTRC_VAL(rc));
473 TMTimerUnlock(pGVM, hTimer);
474 }
475 else
476 AssertRC(VBOXSTRICTRC_VAL(rc));
477 return rc;
478}
479
480
481/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
482static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
483{
484 PDMDEV_ASSERT_DEVINS(pDevIns);
485 return TMTimerSet(pDevIns->Internal.s.pGVM, hTimer, uExpire);
486}
487
488
489/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
490static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
491{
492 PDMDEV_ASSERT_DEVINS(pDevIns);
493 return TMTimerSetFrequencyHint(pDevIns->Internal.s.pGVM, hTimer, uHz);
494}
495
496
497/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
498static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
499{
500 PDMDEV_ASSERT_DEVINS(pDevIns);
501 return TMTimerSetMicro(pDevIns->Internal.s.pGVM, hTimer, cMicrosToNext);
502}
503
504
505/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
506static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
507{
508 PDMDEV_ASSERT_DEVINS(pDevIns);
509 return TMTimerSetMillies(pDevIns->Internal.s.pGVM, hTimer, cMilliesToNext);
510}
511
512
513/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
514static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
515{
516 PDMDEV_ASSERT_DEVINS(pDevIns);
517 return TMTimerSetNano(pDevIns->Internal.s.pGVM, hTimer, cNanosToNext);
518}
519
520
521/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
522static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
523{
524 PDMDEV_ASSERT_DEVINS(pDevIns);
525 return TMTimerSetRelative(pDevIns->Internal.s.pGVM, hTimer, cTicksToNext, pu64Now);
526}
527
528
529/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
530static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
531{
532 PDMDEV_ASSERT_DEVINS(pDevIns);
533 return TMTimerStop(pDevIns->Internal.s.pGVM, hTimer);
534}
535
536
537/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock} */
538static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
539{
540 PDMDEV_ASSERT_DEVINS(pDevIns);
541 TMTimerUnlock(pDevIns->Internal.s.pGVM, hTimer);
542}
543
544
545/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlockClock2} */
546static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlockClock2(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, PPDMCRITSECT pCritSect)
547{
548 PDMDEV_ASSERT_DEVINS(pDevIns);
549 PGVM const pGVM = pDevIns->Internal.s.pGVM;
550 TMTimerUnlock(pGVM, hTimer);
551 int rc = PDMCritSectLeave(pGVM, pCritSect);
552 AssertRC(rc);
553}
554
555
556/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
557static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
558{
559 PDMDEV_ASSERT_DEVINS(pDevIns);
560 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
561 return TMVirtualGet(pDevIns->Internal.s.pGVM);
562}
563
564
565/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
566static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
567{
568 PDMDEV_ASSERT_DEVINS(pDevIns);
569 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
570 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
571}
572
573
574/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
575static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
576{
577 PDMDEV_ASSERT_DEVINS(pDevIns);
578 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
579 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
580}
581
582
583/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
584static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
585{
586 PDMDEV_ASSERT_DEVINS(pDevIns);
587 return PDMQueueAlloc(pDevIns->Internal.s.pGVM, hQueue, pDevIns);
588}
589
590
591/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
592static DECLCALLBACK(int) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
593{
594 PDMDEV_ASSERT_DEVINS(pDevIns);
595 return PDMQueueInsert(pDevIns->Internal.s.pGVM, hQueue, pDevIns, pItem);
596}
597
598
599/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
600static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
601{
602 PDMDEV_ASSERT_DEVINS(pDevIns);
603 return PDMQueueFlushIfNecessary(pDevIns->Internal.s.pGVM, hQueue, pDevIns) == VINF_SUCCESS;
604}
605
606
607/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
608static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
609{
610 PDMDEV_ASSERT_DEVINS(pDevIns);
611 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
612
613 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
614
615 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
616 return rc;
617}
618
619
620/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
621static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
622{
623 PDMDEV_ASSERT_DEVINS(pDevIns);
624 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
625
626 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
627
628 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
629 return rc;
630}
631
632
633/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
634static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
635{
636 PDMDEV_ASSERT_DEVINS(pDevIns);
637 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
638 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
639
640 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
641
642 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
643 return rc;
644}
645
646
647/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
648static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
649{
650 PDMDEV_ASSERT_DEVINS(pDevIns);
651 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
652 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
653
654 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
655
656 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
657 return rc;
658}
659
660
661/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
662static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
663{
664 PDMDEV_ASSERT_DEVINS(pDevIns);
665 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
666 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
667
668 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
669
670 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
671 return rc;
672}
673
674
675/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
676static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
677{
678 PDMDEV_ASSERT_DEVINS(pDevIns);
679 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
680
681 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
682
683 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
684 return cNsResolution;
685}
686
687
688/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
689static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
690{
691 PDMDEV_ASSERT_DEVINS(pDevIns);
692 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
693
694 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
695
696 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
697 return rc;
698}
699
700
701/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
702static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
703{
704 PDMDEV_ASSERT_DEVINS(pDevIns);
705 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
706
707 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
708
709 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
710 return rc;
711}
712
713
714/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
715static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
716 uint32_t cMillies)
717{
718 PDMDEV_ASSERT_DEVINS(pDevIns);
719 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
720 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
721
722 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
723
724 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
725 return rc;
726}
727
728
729/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
730static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
731 uint64_t uNsTimeout)
732{
733 PDMDEV_ASSERT_DEVINS(pDevIns);
734 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
735 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
736
737 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
738
739 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
740 return rc;
741}
742
743
744/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
745static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
746 uint64_t cNsTimeout)
747{
748 PDMDEV_ASSERT_DEVINS(pDevIns);
749 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
750 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
751
752 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
753
754 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
755 return rc;
756}
757
758
759/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
760static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
761{
762 PDMDEV_ASSERT_DEVINS(pDevIns);
763 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
764
765 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
766
767 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
768 return cNsResolution;
769}
770
771
772/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
773static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
774{
775 PDMDEV_ASSERT_DEVINS(pDevIns);
776 PGVM pGVM = pDevIns->Internal.s.pGVM;
777
778 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
779 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
780 return pCritSect;
781}
782
783
784/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
785static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
786{
787 /*
788 * Validate input.
789 *
790 * Note! We only allow the automatically created default critical section
791 * to be replaced by this API.
792 */
793 PDMDEV_ASSERT_DEVINS(pDevIns);
794 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
795 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p\n",
796 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
797 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
798 PGVM pGVM = pDevIns->Internal.s.pGVM;
799
800 VM_ASSERT_EMT(pGVM);
801 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
802
803 /*
804 * Check that ring-3 has already done this, then effect the change.
805 */
806 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
807 pDevIns->pCritSectRoR0 = pCritSect;
808
809 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
810 return VINF_SUCCESS;
811}
812
813
814/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
815static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
816{
817 PDMDEV_ASSERT_DEVINS(pDevIns);
818 return PDMCritSectEnter(pDevIns->Internal.s.pGVM, pCritSect, rcBusy);
819}
820
821
822/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
823static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
824{
825 PDMDEV_ASSERT_DEVINS(pDevIns);
826 return PDMCritSectEnterDebug(pDevIns->Internal.s.pGVM, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
827}
828
829
830/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
831static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
832{
833 PDMDEV_ASSERT_DEVINS(pDevIns);
834 return PDMCritSectTryEnter(pDevIns->Internal.s.pGVM, pCritSect);
835}
836
837
838/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
839static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
840{
841 PDMDEV_ASSERT_DEVINS(pDevIns);
842 return PDMCritSectTryEnterDebug(pDevIns->Internal.s.pGVM, pCritSect, uId, RT_SRC_POS_ARGS);
843}
844
845
846/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
847static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
848{
849 PDMDEV_ASSERT_DEVINS(pDevIns);
850 return PDMCritSectLeave(pDevIns->Internal.s.pGVM, pCritSect);
851}
852
853
854/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
855static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
856{
857 PDMDEV_ASSERT_DEVINS(pDevIns);
858 return PDMCritSectIsOwner(pDevIns->Internal.s.pGVM, pCritSect);
859}
860
861
862/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
863static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
864{
865 PDMDEV_ASSERT_DEVINS(pDevIns);
866 RT_NOREF(pDevIns);
867 return PDMCritSectIsInitialized(pCritSect);
868}
869
870
871/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
872static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
873{
874 PDMDEV_ASSERT_DEVINS(pDevIns);
875 return PDMCritSectHasWaiters(pDevIns->Internal.s.pGVM, pCritSect);
876}
877
878
879/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
880static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
881{
882 PDMDEV_ASSERT_DEVINS(pDevIns);
883 RT_NOREF(pDevIns);
884 return PDMCritSectGetRecursion(pCritSect);
885}
886
887
888/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
889static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
890 SUPSEMEVENT hEventToSignal)
891{
892 PDMDEV_ASSERT_DEVINS(pDevIns);
893 RT_NOREF(pDevIns);
894 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
895}
896
897
898/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterShared} */
899static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
900{
901 PDMDEV_ASSERT_DEVINS(pDevIns);
902 return PDMCritSectRwEnterShared(pDevIns->Internal.s.pGVM, pCritSect, rcBusy);
903}
904
905
906/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterSharedDebug} */
907static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy,
908 RTHCUINTPTR uId, RT_SRC_POS_DECL)
909{
910 PDMDEV_ASSERT_DEVINS(pDevIns);
911 return PDMCritSectRwEnterSharedDebug(pDevIns->Internal.s.pGVM, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
912}
913
914
915
916/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterShared} */
917static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
918{
919 PDMDEV_ASSERT_DEVINS(pDevIns);
920 return PDMCritSectRwTryEnterShared(pDevIns->Internal.s.pGVM, pCritSect);
921}
922
923
924/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterSharedDebug} */
925static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterSharedDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect,
926 RTHCUINTPTR uId, RT_SRC_POS_DECL)
927{
928 PDMDEV_ASSERT_DEVINS(pDevIns);
929 return PDMCritSectRwTryEnterSharedDebug(pDevIns->Internal.s.pGVM, pCritSect, uId, RT_SRC_POS_ARGS);
930}
931
932
933/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwLeaveShared} */
934static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwLeaveShared(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
935{
936 PDMDEV_ASSERT_DEVINS(pDevIns);
937 return PDMCritSectRwLeaveShared(pDevIns->Internal.s.pGVM, pCritSect);
938}
939
940
941/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterExcl} */
942static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy)
943{
944 PDMDEV_ASSERT_DEVINS(pDevIns);
945 return PDMCritSectRwEnterExcl(pDevIns->Internal.s.pGVM, pCritSect, rcBusy);
946}
947
948
949/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwEnterExclDebug} */
950static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, int rcBusy,
951 RTHCUINTPTR uId, RT_SRC_POS_DECL)
952{
953 PDMDEV_ASSERT_DEVINS(pDevIns);
954 return PDMCritSectRwEnterExclDebug(pDevIns->Internal.s.pGVM, pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
955}
956
957
958/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterExcl} */
959static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
960{
961 PDMDEV_ASSERT_DEVINS(pDevIns);
962 return PDMCritSectRwTryEnterExcl(pDevIns->Internal.s.pGVM, pCritSect);
963}
964
965
966/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwTryEnterExclDebug} */
967static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwTryEnterExclDebug(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect,
968 RTHCUINTPTR uId, RT_SRC_POS_DECL)
969{
970 PDMDEV_ASSERT_DEVINS(pDevIns);
971 return PDMCritSectRwTryEnterExclDebug(pDevIns->Internal.s.pGVM, pCritSect, uId, RT_SRC_POS_ARGS);
972}
973
974
975/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwLeaveExcl} */
976static DECLCALLBACK(int) pdmR0DevHlp_CritSectRwLeaveExcl(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
977{
978 PDMDEV_ASSERT_DEVINS(pDevIns);
979 return PDMCritSectRwLeaveExcl(pDevIns->Internal.s.pGVM, pCritSect);
980}
981
982
983/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwIsWriteOwner} */
984static DECLCALLBACK(bool) pdmR0DevHlp_CritSectRwIsWriteOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
985{
986 PDMDEV_ASSERT_DEVINS(pDevIns);
987 return PDMCritSectRwIsWriteOwner(pDevIns->Internal.s.pGVM, pCritSect);
988}
989
990
991/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwIsReadOwner} */
992static DECLCALLBACK(bool) pdmR0DevHlp_CritSectRwIsReadOwner(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect, bool fWannaHear)
993{
994 PDMDEV_ASSERT_DEVINS(pDevIns);
995 return PDMCritSectRwIsReadOwner(pDevIns->Internal.s.pGVM, pCritSect, fWannaHear);
996}
997
998
999/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwGetWriteRecursion} */
1000static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectRwGetWriteRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
1001{
1002 PDMDEV_ASSERT_DEVINS(pDevIns);
1003 RT_NOREF(pDevIns);
1004 return PDMCritSectRwGetWriteRecursion(pCritSect);
1005}
1006
1007
1008/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwGetWriterReadRecursion} */
1009static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectRwGetWriterReadRecursion(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
1010{
1011 PDMDEV_ASSERT_DEVINS(pDevIns);
1012 RT_NOREF(pDevIns);
1013 return PDMCritSectRwGetWriterReadRecursion(pCritSect);
1014}
1015
1016
1017/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwGetReadCount} */
1018static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectRwGetReadCount(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
1019{
1020 PDMDEV_ASSERT_DEVINS(pDevIns);
1021 RT_NOREF(pDevIns);
1022 return PDMCritSectRwGetReadCount(pCritSect);
1023}
1024
1025
1026/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectRwIsInitialized} */
1027static DECLCALLBACK(bool) pdmR0DevHlp_CritSectRwIsInitialized(PPDMDEVINS pDevIns, PPDMCRITSECTRW pCritSect)
1028{
1029 PDMDEV_ASSERT_DEVINS(pDevIns);
1030 RT_NOREF(pDevIns);
1031 return PDMCritSectRwIsInitialized(pCritSect);
1032}
1033
1034
1035/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
1036static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1037{
1038 PDMDEV_ASSERT_DEVINS(pDevIns);
1039 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
1040 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
1041 return hTraceBuf;
1042}
1043
1044
1045/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
1046static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
1047{
1048 PDMDEV_ASSERT_DEVINS(pDevIns);
1049 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
1050 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
1051 pPciBusReg->u32EndVersion, ppPciHlp));
1052 PGVM pGVM = pDevIns->Internal.s.pGVM;
1053
1054 /*
1055 * Validate input.
1056 */
1057 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
1058 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
1059 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1060 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
1061 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
1062 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1063
1064 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
1065
1066 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1067 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1068
1069 /* Check the shared bus data (registered earlier from ring-3): */
1070 uint32_t iBus = pPciBusReg->iBus;
1071 ASMCompilerBarrier();
1072 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
1073 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
1074 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
1075 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
1076 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
1077
1078 /* Check that the bus isn't already registered in ring-0: */
1079 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
1080 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
1081 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
1082 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1083 VERR_ALREADY_EXISTS);
1084
1085 /*
1086 * Do the registering.
1087 */
1088 pPciBusR0->iBus = iBus;
1089 pPciBusR0->uPadding0 = 0xbeefbeef;
1090 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1091 pPciBusR0->pDevInsR0 = pDevIns;
1092
1093 *ppPciHlp = &g_pdmR0PciHlp;
1094
1095 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1096 return VINF_SUCCESS;
1097}
1098
1099
1100/** @interface_method_impl{PDMDEVHLPR0,pfnIommuSetUpContext} */
1101static DECLCALLBACK(int) pdmR0DevHlp_IommuSetUpContext(PPDMDEVINS pDevIns, PPDMIOMMUREGR0 pIommuReg, PCPDMIOMMUHLPR0 *ppIommuHlp)
1102{
1103 PDMDEV_ASSERT_DEVINS(pDevIns);
1104 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: pIommuReg=%p{.u32Version=%#x, u32TheEnd=%#x} ppIommuHlp=%p\n",
1105 pDevIns, pDevIns->iInstance, pIommuReg, pIommuReg->u32Version, pIommuReg->u32TheEnd, ppIommuHlp));
1106 PGVM pGVM = pDevIns->Internal.s.pGVM;
1107
1108 /*
1109 * Validate input.
1110 */
1111 AssertPtrReturn(pIommuReg, VERR_INVALID_POINTER);
1112 AssertLogRelMsgReturn(pIommuReg->u32Version == PDM_IOMMUREGCC_VERSION,
1113 ("%#x vs %#x\n", pIommuReg->u32Version, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1114 AssertPtrReturn(pIommuReg->pfnMemAccess, VERR_INVALID_POINTER);
1115 AssertPtrReturn(pIommuReg->pfnMemBulkAccess, VERR_INVALID_POINTER);
1116 AssertPtrReturn(pIommuReg->pfnMsiRemap, VERR_INVALID_POINTER);
1117 AssertLogRelMsgReturn(pIommuReg->u32TheEnd == PDM_IOMMUREGCC_VERSION,
1118 ("%#x vs %#x\n", pIommuReg->u32TheEnd, PDM_IOMMUREGCC_VERSION), VERR_VERSION_MISMATCH);
1119
1120 AssertPtrReturn(ppIommuHlp, VERR_INVALID_POINTER);
1121
1122 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1123 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1124
1125 /* Check the IOMMU shared data (registered earlier from ring-3). */
1126 uint32_t const idxIommu = pIommuReg->idxIommu;
1127 ASMCompilerBarrier();
1128 AssertLogRelMsgReturn(idxIommu < RT_ELEMENTS(pGVM->pdm.s.aIommus), ("idxIommu=%#x\n", idxIommu), VERR_OUT_OF_RANGE);
1129 PPDMIOMMUR3 pIommuShared = &pGVM->pdm.s.aIommus[idxIommu];
1130 AssertLogRelMsgReturn(pIommuShared->idxIommu == idxIommu, ("%u vs %u\n", pIommuShared->idxIommu, idxIommu), VERR_INVALID_PARAMETER);
1131 AssertLogRelMsgReturn(pIommuShared->pDevInsR3 == pDevIns->pDevInsForR3,
1132 ("%p vs %p (idxIommu=%u)\n", pIommuShared->pDevInsR3, pDevIns->pDevInsForR3, idxIommu), VERR_NOT_OWNER);
1133
1134 /* Check that the IOMMU isn't already registered in ring-0. */
1135 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aIommus) == RT_ELEMENTS(pGVM->pdmr0.s.aIommus));
1136 PPDMIOMMUR0 pIommuR0 = &pGVM->pdmr0.s.aIommus[idxIommu];
1137 AssertLogRelMsgReturn(pIommuR0->pDevInsR0 == NULL,
1138 ("%p (caller pDevIns=%p, idxIommu=%u)\n", pIommuR0->pDevInsR0, pDevIns, idxIommu),
1139 VERR_ALREADY_EXISTS);
1140
1141 /*
1142 * Register.
1143 */
1144 pIommuR0->idxIommu = idxIommu;
1145 pIommuR0->uPadding0 = 0xdeaddead;
1146 pIommuR0->pDevInsR0 = pDevIns;
1147 pIommuR0->pfnMemAccess = pIommuReg->pfnMemAccess;
1148 pIommuR0->pfnMemBulkAccess = pIommuReg->pfnMemBulkAccess;
1149 pIommuR0->pfnMsiRemap = pIommuReg->pfnMsiRemap;
1150
1151 *ppIommuHlp = &g_pdmR0IommuHlp;
1152
1153 LogFlow(("pdmR0DevHlp_IommuSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1154 return VINF_SUCCESS;
1155}
1156
1157
1158/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1159static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1160{
1161 PDMDEV_ASSERT_DEVINS(pDevIns);
1162 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1163 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1164 PGVM pGVM = pDevIns->Internal.s.pGVM;
1165
1166 /*
1167 * Validate input.
1168 */
1169 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1170 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1171 VERR_VERSION_MISMATCH);
1172 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1173 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1174 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1175 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1176 VERR_VERSION_MISMATCH);
1177 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1178
1179 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1180 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1181
1182 /* Check that it's the same device as made the ring-3 registrations: */
1183 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1184 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1185
1186 /* Check that it isn't already registered in ring-0: */
1187 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1188 VERR_ALREADY_EXISTS);
1189
1190 /*
1191 * Take down the callbacks and instance.
1192 */
1193 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1194 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1195 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1196 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1197
1198 /* set the helper pointer and return. */
1199 *ppPicHlp = &g_pdmR0PicHlp;
1200 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1201 return VINF_SUCCESS;
1202}
1203
1204
1205/** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
1206static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
1207{
1208 PDMDEV_ASSERT_DEVINS(pDevIns);
1209 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
1210 PGVM pGVM = pDevIns->Internal.s.pGVM;
1211
1212 /*
1213 * Validate input.
1214 */
1215 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1216 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1217
1218 /* Check that it's the same device as made the ring-3 registrations: */
1219 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR3 == pDevIns->pDevInsForR3,
1220 ("%p vs %p\n", pGVM->pdm.s.Apic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1221
1222 /* Check that it isn't already registered in ring-0: */
1223 AssertLogRelMsgReturn(pGVM->pdm.s.Apic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Apic.pDevInsR0, pDevIns),
1224 VERR_ALREADY_EXISTS);
1225
1226 /*
1227 * Take down the instance.
1228 */
1229 pGVM->pdm.s.Apic.pDevInsR0 = pDevIns;
1230 Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1231
1232 /* set the helper pointer and return. */
1233 LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1234 return VINF_SUCCESS;
1235}
1236
1237
1238/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSetUpContext} */
1239static DECLCALLBACK(int) pdmR0DevHlp_IoApicSetUpContext(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLP *ppIoApicHlp)
1240{
1241 PDMDEV_ASSERT_DEVINS(pDevIns);
1242 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnSendMsi=%p, .pfnSetEoi=%p, .u32TheEnd=%#x } ppIoApicHlp=%p\n",
1243 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrq, pIoApicReg->pfnSendMsi, pIoApicReg->pfnSetEoi, pIoApicReg->u32TheEnd, ppIoApicHlp));
1244 PGVM pGVM = pDevIns->Internal.s.pGVM;
1245
1246 /*
1247 * Validate input.
1248 */
1249 AssertMsgReturn(pIoApicReg->u32Version == PDM_IOAPICREG_VERSION,
1250 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32Version, PDM_IOAPICREG_VERSION),
1251 VERR_VERSION_MISMATCH);
1252 AssertPtrReturn(pIoApicReg->pfnSetIrq, VERR_INVALID_POINTER);
1253 AssertPtrReturn(pIoApicReg->pfnSendMsi, VERR_INVALID_POINTER);
1254 AssertPtrReturn(pIoApicReg->pfnSetEoi, VERR_INVALID_POINTER);
1255 AssertMsgReturn(pIoApicReg->u32TheEnd == PDM_IOAPICREG_VERSION,
1256 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg->u32TheEnd, PDM_IOAPICREG_VERSION),
1257 VERR_VERSION_MISMATCH);
1258 AssertPtrReturn(ppIoApicHlp, VERR_INVALID_POINTER);
1259
1260 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1261 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1262
1263 /* Check that it's the same device as made the ring-3 registrations: */
1264 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR3 == pDevIns->pDevInsForR3,
1265 ("%p vs %p\n", pGVM->pdm.s.IoApic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1266
1267 /* Check that it isn't already registered in ring-0: */
1268 AssertLogRelMsgReturn(pGVM->pdm.s.IoApic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.IoApic.pDevInsR0, pDevIns),
1269 VERR_ALREADY_EXISTS);
1270
1271 /*
1272 * Take down the callbacks and instance.
1273 */
1274 pGVM->pdm.s.IoApic.pDevInsR0 = pDevIns;
1275 pGVM->pdm.s.IoApic.pfnSetIrqR0 = pIoApicReg->pfnSetIrq;
1276 pGVM->pdm.s.IoApic.pfnSendMsiR0 = pIoApicReg->pfnSendMsi;
1277 pGVM->pdm.s.IoApic.pfnSetEoiR0 = pIoApicReg->pfnSetEoi;
1278 Log(("PDM: Registered IOAPIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1279
1280 /* set the helper pointer and return. */
1281 *ppIoApicHlp = &g_pdmR0IoApicHlp;
1282 LogFlow(("pdmR0DevHlp_IoApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1283 return VINF_SUCCESS;
1284}
1285
1286
1287/** @interface_method_impl{PDMDEVHLPR0,pfnHpetSetUpContext} */
1288static DECLCALLBACK(int) pdmR0DevHlp_HpetSetUpContext(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR0 *ppHpetHlp)
1289{
1290 PDMDEV_ASSERT_DEVINS(pDevIns);
1291 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: pHpetReg=%p:{.u32Version=%#x, } ppHpetHlp=%p\n",
1292 pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg, pHpetReg->u32Version, ppHpetHlp));
1293 PGVM pGVM = pDevIns->Internal.s.pGVM;
1294
1295 /*
1296 * Validate input.
1297 */
1298 AssertMsgReturn(pHpetReg->u32Version == PDM_HPETREG_VERSION,
1299 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pHpetReg->u32Version, PDM_HPETREG_VERSION),
1300 VERR_VERSION_MISMATCH);
1301 AssertPtrReturn(ppHpetHlp, VERR_INVALID_POINTER);
1302
1303 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1304 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1305
1306 /* Check that it's the same device as made the ring-3 registrations: */
1307 AssertLogRelMsgReturn(pGVM->pdm.s.pHpet == pDevIns->pDevInsForR3, ("%p vs %p\n", pGVM->pdm.s.pHpet, pDevIns->pDevInsForR3),
1308 VERR_NOT_OWNER);
1309
1310 ///* Check that it isn't already registered in ring-0: */
1311 //AssertLogRelMsgReturn(pGVM->pdm.s.Hpet.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Hpet.pDevInsR0, pDevIns),
1312 // VERR_ALREADY_EXISTS);
1313
1314 /*
1315 * Nothing to take down here at present.
1316 */
1317 Log(("PDM: Registered HPET device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1318
1319 /* set the helper pointer and return. */
1320 *ppHpetHlp = &g_pdmR0HpetHlp;
1321 LogFlow(("pdmR0DevHlp_HpetSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1322 return VINF_SUCCESS;
1323}
1324
1325
1326/** @interface_method_impl{PDMDEVHLPR0,pfnPGMHandlerPhysicalTypeSetUpContext} */
1327static DECLCALLBACK(int) pdmR0DevHlp_PGMHandlerPhysicalTypeSetUpContext(PPDMDEVINS pDevIns, PGMPHYSHANDLERKIND enmKind,
1328 PFNPGMPHYSHANDLER pfnHandler,
1329 PFNPGMRZPHYSPFHANDLER pfnPfHandler,
1330 const char *pszDesc, PGMPHYSHANDLERTYPE hType)
1331{
1332 PDMDEV_ASSERT_DEVINS(pDevIns);
1333 LogFlow(("pdmR0DevHlp_PGMHandlerPhysicalTypeSetUpContext: caller='%s'/%d: enmKind=%d pfnHandler=%p pfnPfHandler=%p pszDesc=%p:{%s} hType=%#x\n",
1334 pDevIns->pReg->szName, pDevIns->iInstance, enmKind, pfnHandler, pfnPfHandler, pszDesc, pszDesc, hType));
1335
1336 int rc = PGMR0HandlerPhysicalTypeSetUpContext(pDevIns->Internal.s.pGVM, enmKind, PGMPHYSHANDLER_F_R0_DEVINS_IDX,
1337 pfnHandler, pfnPfHandler, pszDesc, hType);
1338
1339 Log(("pdmR0DevHlp_PGMHandlerPhysicalTypeSetUpContext: caller='%s'/%d: returns %Rrc\n",
1340 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1341 return rc;
1342}
1343
1344
1345/** @interface_method_impl{PDMDEVHLPR0,pfnPGMHandlerPhysicalPageTempOff} */
1346static DECLCALLBACK(int) pdmR0DevHlp_PGMHandlerPhysicalPageTempOff(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPHYS GCPhysPage)
1347{
1348 PDMDEV_ASSERT_DEVINS(pDevIns);
1349 LogFlow(("pdmR0DevHlp_PGMHandlerPhysicalPageTempOff: caller='%s'/%d: GCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys));
1350
1351 int rc = PGMHandlerPhysicalPageTempOff(pDevIns->Internal.s.pGVM, GCPhys, GCPhysPage);
1352
1353 Log(("pdmR0DevHlp_PGMHandlerPhysicalPageTempOff: caller='%s'/%d: returns %Rrc\n",
1354 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1355 return rc;
1356}
1357
1358
1359/** @interface_method_impl{PDMDEVHLPR0,pfnMmioMapMmio2Page} */
1360static DECLCALLBACK(int) pdmR0DevHlp_MmioMapMmio2Page(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS offRegion,
1361 uint64_t hMmio2, RTGCPHYS offMmio2, uint64_t fPageFlags)
1362{
1363 PDMDEV_ASSERT_DEVINS(pDevIns);
1364 LogFlow(("pdmR0DevHlp_MmioMapMmio2Page: caller='%s'/%d: hRegion=%RX64 offRegion=%RGp hMmio2=%RX64 offMmio2=%RGp fPageFlags=%RX64\n",
1365 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offRegion, hMmio2, offMmio2, fPageFlags));
1366
1367 int rc = IOMMmioMapMmio2Page(pDevIns->Internal.s.pGVM, pDevIns, hRegion, offRegion, hMmio2, offMmio2, fPageFlags);
1368
1369 Log(("pdmR0DevHlp_MmioMapMmio2Page: caller='%s'/%d: returns %Rrc\n",
1370 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1371 return rc;
1372}
1373
1374
1375/** @interface_method_impl{PDMDEVHLPR0,pfnMmioResetRegion} */
1376static DECLCALLBACK(int) pdmR0DevHlp_MmioResetRegion(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
1377{
1378 PDMDEV_ASSERT_DEVINS(pDevIns);
1379 LogFlow(("pdmR0DevHlp_MmioResetRegion: caller='%s'/%d: hRegion=%RX64\n",
1380 pDevIns->pReg->szName, pDevIns->iInstance, hRegion));
1381
1382 int rc = IOMMmioResetRegion(pDevIns->Internal.s.pGVM, pDevIns, hRegion);
1383
1384 Log(("pdmR0DevHlp_MmioResetRegion: caller='%s'/%d: returns %Rrc\n",
1385 pDevIns->pReg->szName, pDevIns->iInstance, rc));
1386 return rc;
1387}
1388
1389
1390/** @interface_method_impl{PDMDEVHLPR0,pfnGIMGetMmio2Regions} */
1391static DECLCALLBACK(PGIMMMIO2REGION) pdmR0DevHlp_GIMGetMmio2Regions(PPDMDEVINS pDevIns, uint32_t *pcRegions)
1392{
1393 PDMDEV_ASSERT_DEVINS(pDevIns);
1394
1395 LogFlow(("pdmR0DevHlp_GIMGetMmio2Regions: caller='%s'/%d: pcRegions=%p\n",
1396 pDevIns->pReg->szName, pDevIns->iInstance, pcRegions));
1397
1398 PGIMMMIO2REGION pRegion = GIMGetMmio2Regions(pDevIns->Internal.s.pGVM, pcRegions);
1399
1400 LogFlow(("pdmR0DevHlp_GIMGetMmio2Regions: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRegion));
1401 return pRegion;
1402}
1403
1404
1405/**
1406 * The Ring-0 Device Helper Callbacks.
1407 */
1408extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1409{
1410 PDM_DEVHLPR0_VERSION,
1411 pdmR0DevHlp_IoPortSetUpContextEx,
1412 pdmR0DevHlp_MmioSetUpContextEx,
1413 pdmR0DevHlp_Mmio2SetUpContext,
1414 pdmR0DevHlp_PCIPhysRead,
1415 pdmR0DevHlp_PCIPhysWrite,
1416 pdmR0DevHlp_PCISetIrq,
1417 pdmR0DevHlp_ISASetIrq,
1418 pdmR0DevHlp_PhysRead,
1419 pdmR0DevHlp_PhysWrite,
1420 pdmR0DevHlp_A20IsEnabled,
1421 pdmR0DevHlp_VMState,
1422 pdmR0DevHlp_GetVM,
1423 pdmR0DevHlp_GetVMCPU,
1424 pdmR0DevHlp_GetCurrentCpuId,
1425 pdmR0DevHlp_GetMainExecutionEngine,
1426 pdmR0DevHlp_TimerFromMicro,
1427 pdmR0DevHlp_TimerFromMilli,
1428 pdmR0DevHlp_TimerFromNano,
1429 pdmR0DevHlp_TimerGet,
1430 pdmR0DevHlp_TimerGetFreq,
1431 pdmR0DevHlp_TimerGetNano,
1432 pdmR0DevHlp_TimerIsActive,
1433 pdmR0DevHlp_TimerIsLockOwner,
1434 pdmR0DevHlp_TimerLockClock,
1435 pdmR0DevHlp_TimerLockClock2,
1436 pdmR0DevHlp_TimerSet,
1437 pdmR0DevHlp_TimerSetFrequencyHint,
1438 pdmR0DevHlp_TimerSetMicro,
1439 pdmR0DevHlp_TimerSetMillies,
1440 pdmR0DevHlp_TimerSetNano,
1441 pdmR0DevHlp_TimerSetRelative,
1442 pdmR0DevHlp_TimerStop,
1443 pdmR0DevHlp_TimerUnlockClock,
1444 pdmR0DevHlp_TimerUnlockClock2,
1445 pdmR0DevHlp_TMTimeVirtGet,
1446 pdmR0DevHlp_TMTimeVirtGetFreq,
1447 pdmR0DevHlp_TMTimeVirtGetNano,
1448 pdmR0DevHlp_QueueAlloc,
1449 pdmR0DevHlp_QueueInsert,
1450 pdmR0DevHlp_QueueFlushIfNecessary,
1451 pdmR0DevHlp_TaskTrigger,
1452 pdmR0DevHlp_SUPSemEventSignal,
1453 pdmR0DevHlp_SUPSemEventWaitNoResume,
1454 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1455 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1456 pdmR0DevHlp_SUPSemEventGetResolution,
1457 pdmR0DevHlp_SUPSemEventMultiSignal,
1458 pdmR0DevHlp_SUPSemEventMultiReset,
1459 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1460 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1461 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1462 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1463 pdmR0DevHlp_CritSectGetNop,
1464 pdmR0DevHlp_SetDeviceCritSect,
1465 pdmR0DevHlp_CritSectEnter,
1466 pdmR0DevHlp_CritSectEnterDebug,
1467 pdmR0DevHlp_CritSectTryEnter,
1468 pdmR0DevHlp_CritSectTryEnterDebug,
1469 pdmR0DevHlp_CritSectLeave,
1470 pdmR0DevHlp_CritSectIsOwner,
1471 pdmR0DevHlp_CritSectIsInitialized,
1472 pdmR0DevHlp_CritSectHasWaiters,
1473 pdmR0DevHlp_CritSectGetRecursion,
1474 pdmR0DevHlp_CritSectScheduleExitEvent,
1475 pdmR0DevHlp_CritSectRwEnterShared,
1476 pdmR0DevHlp_CritSectRwEnterSharedDebug,
1477 pdmR0DevHlp_CritSectRwTryEnterShared,
1478 pdmR0DevHlp_CritSectRwTryEnterSharedDebug,
1479 pdmR0DevHlp_CritSectRwLeaveShared,
1480 pdmR0DevHlp_CritSectRwEnterExcl,
1481 pdmR0DevHlp_CritSectRwEnterExclDebug,
1482 pdmR0DevHlp_CritSectRwTryEnterExcl,
1483 pdmR0DevHlp_CritSectRwTryEnterExclDebug,
1484 pdmR0DevHlp_CritSectRwLeaveExcl,
1485 pdmR0DevHlp_CritSectRwIsWriteOwner,
1486 pdmR0DevHlp_CritSectRwIsReadOwner,
1487 pdmR0DevHlp_CritSectRwGetWriteRecursion,
1488 pdmR0DevHlp_CritSectRwGetWriterReadRecursion,
1489 pdmR0DevHlp_CritSectRwGetReadCount,
1490 pdmR0DevHlp_CritSectRwIsInitialized,
1491 pdmR0DevHlp_DBGFTraceBuf,
1492 pdmR0DevHlp_PCIBusSetUpContext,
1493 pdmR0DevHlp_IommuSetUpContext,
1494 pdmR0DevHlp_PICSetUpContext,
1495 pdmR0DevHlp_ApicSetUpContext,
1496 pdmR0DevHlp_IoApicSetUpContext,
1497 pdmR0DevHlp_HpetSetUpContext,
1498 pdmR0DevHlp_PGMHandlerPhysicalTypeSetUpContext,
1499 pdmR0DevHlp_PGMHandlerPhysicalPageTempOff,
1500 pdmR0DevHlp_MmioMapMmio2Page,
1501 pdmR0DevHlp_MmioResetRegion,
1502 pdmR0DevHlp_GIMGetMmio2Regions,
1503 NULL /*pfnReserved1*/,
1504 NULL /*pfnReserved2*/,
1505 NULL /*pfnReserved3*/,
1506 NULL /*pfnReserved4*/,
1507 NULL /*pfnReserved5*/,
1508 NULL /*pfnReserved6*/,
1509 NULL /*pfnReserved7*/,
1510 NULL /*pfnReserved8*/,
1511 NULL /*pfnReserved9*/,
1512 NULL /*pfnReserved10*/,
1513 PDM_DEVHLPR0_VERSION
1514};
1515
1516
1517#ifdef VBOX_WITH_DBGF_TRACING
1518/**
1519 * The Ring-0 Device Helper Callbacks - tracing variant.
1520 */
1521extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlpTracing =
1522{
1523 PDM_DEVHLPR0_VERSION,
1524 pdmR0DevHlpTracing_IoPortSetUpContextEx,
1525 pdmR0DevHlpTracing_MmioSetUpContextEx,
1526 pdmR0DevHlp_Mmio2SetUpContext,
1527 pdmR0DevHlpTracing_PCIPhysRead,
1528 pdmR0DevHlpTracing_PCIPhysWrite,
1529 pdmR0DevHlpTracing_PCISetIrq,
1530 pdmR0DevHlpTracing_ISASetIrq,
1531 pdmR0DevHlp_PhysRead,
1532 pdmR0DevHlp_PhysWrite,
1533 pdmR0DevHlp_A20IsEnabled,
1534 pdmR0DevHlp_VMState,
1535 pdmR0DevHlp_GetVM,
1536 pdmR0DevHlp_GetVMCPU,
1537 pdmR0DevHlp_GetCurrentCpuId,
1538 pdmR0DevHlp_GetMainExecutionEngine,
1539 pdmR0DevHlp_TimerFromMicro,
1540 pdmR0DevHlp_TimerFromMilli,
1541 pdmR0DevHlp_TimerFromNano,
1542 pdmR0DevHlp_TimerGet,
1543 pdmR0DevHlp_TimerGetFreq,
1544 pdmR0DevHlp_TimerGetNano,
1545 pdmR0DevHlp_TimerIsActive,
1546 pdmR0DevHlp_TimerIsLockOwner,
1547 pdmR0DevHlp_TimerLockClock,
1548 pdmR0DevHlp_TimerLockClock2,
1549 pdmR0DevHlp_TimerSet,
1550 pdmR0DevHlp_TimerSetFrequencyHint,
1551 pdmR0DevHlp_TimerSetMicro,
1552 pdmR0DevHlp_TimerSetMillies,
1553 pdmR0DevHlp_TimerSetNano,
1554 pdmR0DevHlp_TimerSetRelative,
1555 pdmR0DevHlp_TimerStop,
1556 pdmR0DevHlp_TimerUnlockClock,
1557 pdmR0DevHlp_TimerUnlockClock2,
1558 pdmR0DevHlp_TMTimeVirtGet,
1559 pdmR0DevHlp_TMTimeVirtGetFreq,
1560 pdmR0DevHlp_TMTimeVirtGetNano,
1561 pdmR0DevHlp_QueueAlloc,
1562 pdmR0DevHlp_QueueInsert,
1563 pdmR0DevHlp_QueueFlushIfNecessary,
1564 pdmR0DevHlp_TaskTrigger,
1565 pdmR0DevHlp_SUPSemEventSignal,
1566 pdmR0DevHlp_SUPSemEventWaitNoResume,
1567 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1568 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1569 pdmR0DevHlp_SUPSemEventGetResolution,
1570 pdmR0DevHlp_SUPSemEventMultiSignal,
1571 pdmR0DevHlp_SUPSemEventMultiReset,
1572 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1573 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1574 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1575 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1576 pdmR0DevHlp_CritSectGetNop,
1577 pdmR0DevHlp_SetDeviceCritSect,
1578 pdmR0DevHlp_CritSectEnter,
1579 pdmR0DevHlp_CritSectEnterDebug,
1580 pdmR0DevHlp_CritSectTryEnter,
1581 pdmR0DevHlp_CritSectTryEnterDebug,
1582 pdmR0DevHlp_CritSectLeave,
1583 pdmR0DevHlp_CritSectIsOwner,
1584 pdmR0DevHlp_CritSectIsInitialized,
1585 pdmR0DevHlp_CritSectHasWaiters,
1586 pdmR0DevHlp_CritSectGetRecursion,
1587 pdmR0DevHlp_CritSectScheduleExitEvent,
1588 pdmR0DevHlp_CritSectRwEnterShared,
1589 pdmR0DevHlp_CritSectRwEnterSharedDebug,
1590 pdmR0DevHlp_CritSectRwTryEnterShared,
1591 pdmR0DevHlp_CritSectRwTryEnterSharedDebug,
1592 pdmR0DevHlp_CritSectRwLeaveShared,
1593 pdmR0DevHlp_CritSectRwEnterExcl,
1594 pdmR0DevHlp_CritSectRwEnterExclDebug,
1595 pdmR0DevHlp_CritSectRwTryEnterExcl,
1596 pdmR0DevHlp_CritSectRwTryEnterExclDebug,
1597 pdmR0DevHlp_CritSectRwLeaveExcl,
1598 pdmR0DevHlp_CritSectRwIsWriteOwner,
1599 pdmR0DevHlp_CritSectRwIsReadOwner,
1600 pdmR0DevHlp_CritSectRwGetWriteRecursion,
1601 pdmR0DevHlp_CritSectRwGetWriterReadRecursion,
1602 pdmR0DevHlp_CritSectRwGetReadCount,
1603 pdmR0DevHlp_CritSectRwIsInitialized,
1604 pdmR0DevHlp_DBGFTraceBuf,
1605 pdmR0DevHlp_PCIBusSetUpContext,
1606 pdmR0DevHlp_IommuSetUpContext,
1607 pdmR0DevHlp_PICSetUpContext,
1608 pdmR0DevHlp_ApicSetUpContext,
1609 pdmR0DevHlp_IoApicSetUpContext,
1610 pdmR0DevHlp_HpetSetUpContext,
1611 pdmR0DevHlp_PGMHandlerPhysicalTypeSetUpContext,
1612 pdmR0DevHlp_PGMHandlerPhysicalPageTempOff,
1613 pdmR0DevHlp_MmioMapMmio2Page,
1614 pdmR0DevHlp_MmioResetRegion,
1615 pdmR0DevHlp_GIMGetMmio2Regions,
1616 NULL /*pfnReserved1*/,
1617 NULL /*pfnReserved2*/,
1618 NULL /*pfnReserved3*/,
1619 NULL /*pfnReserved4*/,
1620 NULL /*pfnReserved5*/,
1621 NULL /*pfnReserved6*/,
1622 NULL /*pfnReserved7*/,
1623 NULL /*pfnReserved8*/,
1624 NULL /*pfnReserved9*/,
1625 NULL /*pfnReserved10*/,
1626 PDM_DEVHLPR0_VERSION
1627};
1628#endif
1629
1630
1631/** @} */
1632
1633
1634/** @name PIC Ring-0 Helpers
1635 * @{
1636 */
1637
1638/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1639static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1640{
1641 PDMDEV_ASSERT_DEVINS(pDevIns);
1642 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1643 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1644 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1645 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1646}
1647
1648
1649/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1650static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1651{
1652 PDMDEV_ASSERT_DEVINS(pDevIns);
1653 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1654 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1655 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1656 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1657}
1658
1659
1660/** @interface_method_impl{PDMPICHLP,pfnLock} */
1661static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1662{
1663 PDMDEV_ASSERT_DEVINS(pDevIns);
1664 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1665}
1666
1667
1668/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1669static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1670{
1671 PDMDEV_ASSERT_DEVINS(pDevIns);
1672 pdmUnlock(pDevIns->Internal.s.pGVM);
1673}
1674
1675
1676/**
1677 * The Ring-0 PIC Helper Callbacks.
1678 */
1679extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1680{
1681 PDM_PICHLP_VERSION,
1682 pdmR0PicHlp_SetInterruptFF,
1683 pdmR0PicHlp_ClearInterruptFF,
1684 pdmR0PicHlp_Lock,
1685 pdmR0PicHlp_Unlock,
1686 PDM_PICHLP_VERSION
1687};
1688
1689/** @} */
1690
1691
1692/** @name I/O APIC Ring-0 Helpers
1693 * @{
1694 */
1695
1696/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
1697static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1698 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1699 uint8_t u8TriggerMode, uint32_t uTagSrc)
1700{
1701 PDMDEV_ASSERT_DEVINS(pDevIns);
1702 PGVM pGVM = pDevIns->Internal.s.pGVM;
1703 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1704 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1705 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1706}
1707
1708
1709/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
1710static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1711{
1712 PDMDEV_ASSERT_DEVINS(pDevIns);
1713 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1714}
1715
1716
1717/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
1718static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1719{
1720 PDMDEV_ASSERT_DEVINS(pDevIns);
1721 pdmUnlock(pDevIns->Internal.s.pGVM);
1722}
1723
1724
1725/** @interface_method_impl{PDMIOAPICHLP,pfnLockIsOwner} */
1726static DECLCALLBACK(bool) pdmR0IoApicHlp_LockIsOwner(PPDMDEVINS pDevIns)
1727{
1728 PDMDEV_ASSERT_DEVINS(pDevIns);
1729 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1730}
1731
1732
1733/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
1734static DECLCALLBACK(int) pdmR0IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
1735{
1736 PDMDEV_ASSERT_DEVINS(pDevIns);
1737 LogFlow(("pdmR0IoApicHlp_IommuMsiRemap: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
1738 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
1739
1740#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
1741 if (pdmIommuIsPresent(pDevIns))
1742 {
1743 PGVM pGVM = pDevIns->Internal.s.pGVM;
1744 PPDMIOMMUR0 pIommu = &pGVM->pdmr0.s.aIommus[0];
1745 if (pIommu->pDevInsR0)
1746 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
1747 AssertMsgFailedReturn(("Implement queueing PDM task for remapping MSI via IOMMU in ring-3"), VERR_IOMMU_IPE_0);
1748 }
1749#else
1750 RT_NOREF(pDevIns, idDevice);
1751#endif
1752 return VERR_IOMMU_NOT_PRESENT;
1753}
1754
1755
1756/**
1757 * The Ring-0 I/O APIC Helper Callbacks.
1758 */
1759extern DECLEXPORT(const PDMIOAPICHLP) g_pdmR0IoApicHlp =
1760{
1761 PDM_IOAPICHLP_VERSION,
1762 pdmR0IoApicHlp_ApicBusDeliver,
1763 pdmR0IoApicHlp_Lock,
1764 pdmR0IoApicHlp_Unlock,
1765 pdmR0IoApicHlp_LockIsOwner,
1766 pdmR0IoApicHlp_IommuMsiRemap,
1767 PDM_IOAPICHLP_VERSION
1768};
1769
1770/** @} */
1771
1772
1773
1774
1775/** @name PCI Bus Ring-0 Helpers
1776 * @{
1777 */
1778
1779/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1780static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1781{
1782 PDMDEV_ASSERT_DEVINS(pDevIns);
1783 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1784 PGVM pGVM = pDevIns->Internal.s.pGVM;
1785
1786 pdmLock(pGVM);
1787 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1788 pdmUnlock(pGVM);
1789}
1790
1791
1792/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1793static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
1794{
1795 PDMDEV_ASSERT_DEVINS(pDevIns);
1796 Log4(("pdmR0PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
1797 PGVM pGVM = pDevIns->Internal.s.pGVM;
1798
1799 if (pGVM->pdm.s.IoApic.pDevInsR0)
1800 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, uBusDevFn, iIrq, iLevel, uTagSrc);
1801 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1802 {
1803 /* queue for ring-3 execution. */
1804 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM, pGVM->pdm.s.hDevHlpQueue, pGVM);
1805 if (pTask)
1806 {
1807 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1808 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1809 pTask->u.IoApicSetIrq.uBusDevFn = uBusDevFn;
1810 pTask->u.IoApicSetIrq.iIrq = iIrq;
1811 pTask->u.IoApicSetIrq.iLevel = iLevel;
1812 pTask->u.IoApicSetIrq.uTagSrc = uTagSrc;
1813
1814 PDMQueueInsert(pGVM, pGVM->pdm.s.hDevHlpQueue, pGVM, &pTask->Core);
1815 }
1816 else
1817 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1818 }
1819}
1820
1821
1822/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1823static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
1824{
1825 PDMDEV_ASSERT_DEVINS(pDevIns);
1826 Assert(PCIBDF_IS_VALID(uBusDevFn));
1827 Log4(("pdmR0PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi=(Addr:%#RX64 Data:%#RX32) uTagSrc=%#x\n", uBusDevFn, pMsi->Addr.u64,
1828 pMsi->Data.u32, uTagSrc));
1829 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, uBusDevFn, pMsi, uTagSrc);
1830}
1831
1832
1833/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1834static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1835{
1836 PDMDEV_ASSERT_DEVINS(pDevIns);
1837 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1838}
1839
1840
1841/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1842static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1843{
1844 PDMDEV_ASSERT_DEVINS(pDevIns);
1845 pdmUnlock(pDevIns->Internal.s.pGVM);
1846}
1847
1848
1849/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1850static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1851{
1852 PDMDEV_ASSERT_DEVINS(pDevIns);
1853 PGVM pGVM = pDevIns->Internal.s.pGVM;
1854 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1855 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1856 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1857 return pRetDevIns;
1858}
1859
1860
1861/**
1862 * The Ring-0 PCI Bus Helper Callbacks.
1863 */
1864extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1865{
1866 PDM_PCIHLPR0_VERSION,
1867 pdmR0PciHlp_IsaSetIrq,
1868 pdmR0PciHlp_IoApicSetIrq,
1869 pdmR0PciHlp_IoApicSendMsi,
1870 pdmR0PciHlp_Lock,
1871 pdmR0PciHlp_Unlock,
1872 pdmR0PciHlp_GetBusByNo,
1873 PDM_PCIHLPR0_VERSION, /* the end */
1874};
1875
1876/** @} */
1877
1878
1879/** @name IOMMU Ring-0 Helpers
1880 * @{
1881 */
1882
1883/** @interface_method_impl{PDMIOMMUHLPR0,pfnLock} */
1884static DECLCALLBACK(int) pdmR0IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
1885{
1886 PDMDEV_ASSERT_DEVINS(pDevIns);
1887 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1888}
1889
1890
1891/** @interface_method_impl{PDMIOMMUHLPR0,pfnUnlock} */
1892static DECLCALLBACK(void) pdmR0IommuHlp_Unlock(PPDMDEVINS pDevIns)
1893{
1894 PDMDEV_ASSERT_DEVINS(pDevIns);
1895 pdmUnlock(pDevIns->Internal.s.pGVM);
1896}
1897
1898
1899/** @interface_method_impl{PDMIOMMUHLPR0,pfnLockIsOwner} */
1900static DECLCALLBACK(bool) pdmR0IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
1901{
1902 PDMDEV_ASSERT_DEVINS(pDevIns);
1903 return pdmLockIsOwner(pDevIns->Internal.s.pGVM);
1904}
1905
1906
1907/** @interface_method_impl{PDMIOMMUHLPR0,pfnSendMsi} */
1908static DECLCALLBACK(void) pdmR0IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
1909{
1910 PDMDEV_ASSERT_DEVINS(pDevIns);
1911 PDMIoApicSendMsi(pDevIns->Internal.s.pGVM, NIL_PCIBDF, pMsi, uTagSrc);
1912}
1913
1914
1915/**
1916 * The Ring-0 IOMMU Helper Callbacks.
1917 */
1918extern DECLEXPORT(const PDMIOMMUHLPR0) g_pdmR0IommuHlp =
1919{
1920 PDM_IOMMUHLPR0_VERSION,
1921 pdmR0IommuHlp_Lock,
1922 pdmR0IommuHlp_Unlock,
1923 pdmR0IommuHlp_LockIsOwner,
1924 pdmR0IommuHlp_SendMsi,
1925 PDM_IOMMUHLPR0_VERSION, /* the end */
1926};
1927
1928/** @} */
1929
1930
1931/** @name HPET Ring-0 Helpers
1932 * @{
1933 */
1934/* none */
1935
1936/**
1937 * The Ring-0 HPET Helper Callbacks.
1938 */
1939extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1940{
1941 PDM_HPETHLPR0_VERSION,
1942 PDM_HPETHLPR0_VERSION, /* the end */
1943};
1944
1945/** @} */
1946
1947
1948/** @name Raw PCI Ring-0 Helpers
1949 * @{
1950 */
1951/* none */
1952
1953/**
1954 * The Ring-0 PCI raw Helper Callbacks.
1955 */
1956extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1957{
1958 PDM_PCIRAWHLPR0_VERSION,
1959 PDM_PCIRAWHLPR0_VERSION, /* the end */
1960};
1961
1962/** @} */
1963
1964
1965
1966
1967/**
1968 * Sets an irq on the PIC and I/O APIC.
1969 *
1970 * @returns true if delivered, false if postponed.
1971 * @param pGVM The global (ring-0) VM structure.
1972 * @param iIrq The irq.
1973 * @param iLevel The new level.
1974 * @param uTagSrc The IRQ tag and source.
1975 *
1976 * @remarks The caller holds the PDM lock.
1977 */
1978DECLHIDDEN(bool) pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1979{
1980 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1981 || !pGVM->pdm.s.IoApic.pDevInsR3)
1982 && ( pGVM->pdm.s.Pic.pDevInsR0
1983 || !pGVM->pdm.s.Pic.pDevInsR3)))
1984 {
1985 if (pGVM->pdm.s.Pic.pDevInsR0)
1986 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1987 if (pGVM->pdm.s.IoApic.pDevInsR0)
1988 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, NIL_PCIBDF, iIrq, iLevel, uTagSrc);
1989 return true;
1990 }
1991
1992 /* queue for ring-3 execution. */
1993 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM, pGVM->pdm.s.hDevHlpQueue, pGVM);
1994 AssertReturn(pTask, false);
1995
1996 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1997 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1998 pTask->u.IsaSetIrq.uBusDevFn = NIL_PCIBDF;
1999 pTask->u.IsaSetIrq.iIrq = iIrq;
2000 pTask->u.IsaSetIrq.iLevel = iLevel;
2001 pTask->u.IsaSetIrq.uTagSrc = uTagSrc;
2002
2003 PDMQueueInsert(pGVM, pGVM->pdm.s.hDevHlpQueue, pGVM, &pTask->Core);
2004 return false;
2005}
2006
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