VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 29287

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1/* $Id: PDMR0Device.cpp 28800 2010-04-27 08:22:32Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2010 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/pdm.h>
25#include <VBox/pgm.h>
26#include <VBox/mm.h>
27#include <VBox/vm.h>
28#include <VBox/vmm.h>
29#include <VBox/patm.h>
30#include <VBox/hwaccm.h>
31
32#include <VBox/log.h>
33#include <VBox/err.h>
34#include <VBox/gvmm.h>
35#include <iprt/asm.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38
39
40/*******************************************************************************
41* Global Variables *
42*******************************************************************************/
43RT_C_DECLS_BEGIN
44extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
45extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
46extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
47extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
48extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
49extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
50extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
51RT_C_DECLS_END
52
53
54/*******************************************************************************
55* Internal Functions *
56*******************************************************************************/
57static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel);
58static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel);
59
60
61
62
63/** @name Ring-0 Device Helpers
64 * @{
65 */
66
67/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
68static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
69{
70 PDMDEV_ASSERT_DEVINS(pDevIns);
71 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
72
73 PVM pVM = pDevIns->Internal.s.pVMR0;
74 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
75 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
76 if ( pPciDev
77 && pPciBus
78 && pPciBus->pDevInsR0)
79 {
80 pdmLock(pVM);
81 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel);
82 pdmUnlock(pVM);
83 }
84 else
85 {
86 /* queue for ring-3 execution. */
87 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
88 if (pTask)
89 {
90 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
91 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
92 pTask->u.SetIRQ.iIrq = iIrq;
93 pTask->u.SetIRQ.iLevel = iLevel;
94
95 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
96 }
97 else
98 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
99 }
100
101 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
102}
103
104
105/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
106static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
107{
108 PDMDEV_ASSERT_DEVINS(pDevIns);
109 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
110
111 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
112
113 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance));
114}
115
116
117/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
118static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
119{
120 PDMDEV_ASSERT_DEVINS(pDevIns);
121 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
122 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
123
124 int rc = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead);
125 AssertRC(rc); /** @todo track down the users for this bugger. */
126
127 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
128 return rc;
129}
130
131
132/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
133static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
134{
135 PDMDEV_ASSERT_DEVINS(pDevIns);
136 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
137 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
138
139 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite);
140 AssertRC(rc); /** @todo track down the users for this bugger. */
141
142 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
143 return rc;
144}
145
146
147/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
148static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
149{
150 PDMDEV_ASSERT_DEVINS(pDevIns);
151 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
152
153 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
154
155 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
156 return fEnabled;
157}
158
159
160/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
161static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
162{
163 PDMDEV_ASSERT_DEVINS(pDevIns);
164
165 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
166
167 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
168 return enmVMState;
169}
170
171
172/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
173static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
174{
175 PDMDEV_ASSERT_DEVINS(pDevIns);
176 va_list args;
177 va_start(args, pszFormat);
178 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
179 va_end(args);
180 return rc;
181}
182
183
184/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
185static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
186{
187 PDMDEV_ASSERT_DEVINS(pDevIns);
188 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
189 return rc;
190}
191
192
193/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
194static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
195{
196 PDMDEV_ASSERT_DEVINS(pDevIns);
197 va_list va;
198 va_start(va, pszFormat);
199 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
200 va_end(va);
201 return rc;
202}
203
204
205/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
206static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
207{
208 PDMDEV_ASSERT_DEVINS(pDevIns);
209 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
210 return rc;
211}
212
213
214/** @copydoc PDMDEVHLPR0::pdmR0DevHlp_PATMSetMMIOPatchInfo*/
215static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
216{
217 PDMDEV_ASSERT_DEVINS(pDevIns);
218 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
219
220 AssertFailed();
221
222/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
223 return VINF_SUCCESS;
224}
225
226
227/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
228static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
229{
230 PDMDEV_ASSERT_DEVINS(pDevIns);
231 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
232 return pDevIns->Internal.s.pVMR0;
233}
234
235
236/** @interface_method_impl{PDMDEVHLPR0,pfnCanEmulateIoBlock} */
237static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
238{
239 PDMDEV_ASSERT_DEVINS(pDevIns);
240 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
241 return HWACCMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
242}
243
244
245/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
246static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
247{
248 PDMDEV_ASSERT_DEVINS(pDevIns);
249 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
250 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
251}
252
253
254/**
255 * The Ring-0 Device Helper Callbacks.
256 */
257extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
258{
259 PDM_DEVHLPR0_VERSION,
260 pdmR0DevHlp_PCISetIrq,
261 pdmR0DevHlp_ISASetIrq,
262 pdmR0DevHlp_PhysRead,
263 pdmR0DevHlp_PhysWrite,
264 pdmR0DevHlp_A20IsEnabled,
265 pdmR0DevHlp_VMState,
266 pdmR0DevHlp_VMSetError,
267 pdmR0DevHlp_VMSetErrorV,
268 pdmR0DevHlp_VMSetRuntimeError,
269 pdmR0DevHlp_VMSetRuntimeErrorV,
270 pdmR0DevHlp_PATMSetMMIOPatchInfo,
271 pdmR0DevHlp_GetVM,
272 pdmR0DevHlp_CanEmulateIoBlock,
273 pdmR0DevHlp_GetVMCPU,
274 PDM_DEVHLPR0_VERSION
275};
276
277/** @} */
278
279
280
281
282/** @name PIC Ring-0 Helpers
283 * @{
284 */
285
286/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
287static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
288{
289 PDMDEV_ASSERT_DEVINS(pDevIns);
290 PVM pVM = pDevIns->Internal.s.pVMR0;
291
292 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
293 {
294 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
295 pDevIns, pDevIns->iInstance));
296 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
297 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 1);
298 return;
299 }
300
301 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
302
303 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
304 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
305
306 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
307}
308
309
310/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
311static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
312{
313 PDMDEV_ASSERT_DEVINS(pDevIns);
314 PVM pVM = pDevIns->Internal.s.pVMR0;
315
316 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
317 {
318 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
319 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
320 pDevIns, pDevIns->iInstance));
321 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
322 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 0);
323 return;
324 }
325
326 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
327
328 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
329 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
330
331 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
332}
333
334
335/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
336static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
337{
338 PDMDEV_ASSERT_DEVINS(pDevIns);
339 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
340}
341
342
343/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
344static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
345{
346 PDMDEV_ASSERT_DEVINS(pDevIns);
347 pdmUnlock(pDevIns->Internal.s.pVMR0);
348}
349
350
351/**
352 * The Ring-0 PIC Helper Callbacks.
353 */
354extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
355{
356 PDM_PICHLPR0_VERSION,
357 pdmR0PicHlp_SetInterruptFF,
358 pdmR0PicHlp_ClearInterruptFF,
359 pdmR0PicHlp_Lock,
360 pdmR0PicHlp_Unlock,
361 PDM_PICHLPR0_VERSION
362};
363
364/** @} */
365
366
367
368
369/** @name APIC Ring-0 Helpers
370 * @{
371 */
372
373/** @interface_method_impl{PDMAPICHLPR0,pfnSetInterruptFF} */
374static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
375{
376 PDMDEV_ASSERT_DEVINS(pDevIns);
377 PVM pVM = pDevIns->Internal.s.pVMR0;
378 PVMCPU pVCpu = &pVM->aCpus[idCpu];
379
380 AssertReturnVoid(idCpu < pVM->cCpus);
381
382 LogFlow(("pdmR0ApicHlp_SetInterruptFF: CPU%d=caller=%p/%d: VM_FF_INTERRUPT %d -> 1 (CPU%d)\n",
383 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu));
384
385 switch (enmType)
386 {
387 case PDMAPICIRQ_HARDWARE:
388 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
389 break;
390 case PDMAPICIRQ_NMI:
391 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
392 break;
393 case PDMAPICIRQ_SMI:
394 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
395 break;
396 case PDMAPICIRQ_EXTINT:
397 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
398 break;
399 default:
400 AssertMsgFailed(("enmType=%d\n", enmType));
401 break;
402 }
403
404 /* We need to wait up the target CPU. */
405 if (VMMGetCpuId(pVM) != idCpu)
406 {
407 switch (VMCPU_GET_STATE(pVCpu))
408 {
409 case VMCPUSTATE_STARTED_EXEC:
410 GVMMR0SchedPokeEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
411 break;
412
413 case VMCPUSTATE_STARTED_HALTED:
414 GVMMR0SchedWakeUpEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
415 break;
416
417 default:
418 break; /* nothing to do in other states. */
419 }
420 }
421}
422
423
424/** @interface_method_impl{PDMAPICHLPR0,pfnClearInterruptFF} */
425static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
426{
427 PDMDEV_ASSERT_DEVINS(pDevIns);
428 PVM pVM = pDevIns->Internal.s.pVMR0;
429 PVMCPU pVCpu = &pVM->aCpus[idCpu];
430
431 AssertReturnVoid(idCpu < pVM->cCpus);
432
433 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
434 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
435
436 /* Note: NMI/SMI can't be cleared. */
437 switch (enmType)
438 {
439 case PDMAPICIRQ_HARDWARE:
440 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
441 break;
442 case PDMAPICIRQ_EXTINT:
443 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
444 break;
445 default:
446 AssertMsgFailed(("enmType=%d\n", enmType));
447 break;
448 }
449}
450
451
452/** @interface_method_impl{PDMAPICHLPR0,pfnChangeFeature} */
453static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
454{
455 PDMDEV_ASSERT_DEVINS(pDevIns);
456 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
457 switch (enmVersion)
458 {
459 case PDMAPICVERSION_NONE:
460 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
461 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
462 break;
463 case PDMAPICVERSION_APIC:
464 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
465 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
466 break;
467 case PDMAPICVERSION_X2APIC:
468 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
469 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
470 break;
471 default:
472 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
473 }
474}
475
476
477/** @interface_method_impl{PDMAPICHLPR0,pfnLock} */
478static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
479{
480 PDMDEV_ASSERT_DEVINS(pDevIns);
481 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
482}
483
484
485/** @interface_method_impl{PDMAPICHLPR0,pfnUnlock} */
486static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
487{
488 PDMDEV_ASSERT_DEVINS(pDevIns);
489 pdmUnlock(pDevIns->Internal.s.pVMR0);
490}
491
492
493/** @interface_method_impl{PDMAPICHLPR0,pfnGetCpuId} */
494static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
495{
496 PDMDEV_ASSERT_DEVINS(pDevIns);
497 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
498}
499
500
501/**
502 * The Ring-0 APIC Helper Callbacks.
503 */
504extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
505{
506 PDM_APICHLPR0_VERSION,
507 pdmR0ApicHlp_SetInterruptFF,
508 pdmR0ApicHlp_ClearInterruptFF,
509 pdmR0ApicHlp_ChangeFeature,
510 pdmR0ApicHlp_Lock,
511 pdmR0ApicHlp_Unlock,
512 pdmR0ApicHlp_GetCpuId,
513 PDM_APICHLPR0_VERSION
514};
515
516/** @} */
517
518
519
520
521/** @name I/O APIC Ring-0 Helpers
522 * @{
523 */
524
525/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
526static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
527 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode)
528{
529 PDMDEV_ASSERT_DEVINS(pDevIns);
530 PVM pVM = pDevIns->Internal.s.pVMR0;
531 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n",
532 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
533 Assert(pVM->pdm.s.Apic.pDevInsR0);
534 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
535 return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode);
536 return VINF_SUCCESS;
537}
538
539
540/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
541static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
542{
543 PDMDEV_ASSERT_DEVINS(pDevIns);
544 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
545}
546
547
548/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
549static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
550{
551 PDMDEV_ASSERT_DEVINS(pDevIns);
552 pdmUnlock(pDevIns->Internal.s.pVMR0);
553}
554
555
556/**
557 * The Ring-0 I/O APIC Helper Callbacks.
558 */
559extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
560{
561 PDM_IOAPICHLPR0_VERSION,
562 pdmR0IoApicHlp_ApicBusDeliver,
563 pdmR0IoApicHlp_Lock,
564 pdmR0IoApicHlp_Unlock,
565 PDM_IOAPICHLPR0_VERSION
566};
567
568/** @} */
569
570
571
572
573/** @name PCI Bus Ring-0 Helpers
574 * @{
575 */
576
577/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
578static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
579{
580 PDMDEV_ASSERT_DEVINS(pDevIns);
581 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
582 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
583}
584
585
586/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
587static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
588{
589 PDMDEV_ASSERT_DEVINS(pDevIns);
590 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel));
591 pdmR0IoApicSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel);
592}
593
594
595/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
596static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
597{
598 PDMDEV_ASSERT_DEVINS(pDevIns);
599 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
600}
601
602
603/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
604static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
605{
606 PDMDEV_ASSERT_DEVINS(pDevIns);
607 pdmUnlock(pDevIns->Internal.s.pVMR0);
608}
609
610
611/**
612 * The Ring-0 PCI Bus Helper Callbacks.
613 */
614extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
615{
616 PDM_PCIHLPR0_VERSION,
617 pdmR0PciHlp_IsaSetIrq,
618 pdmR0PciHlp_IoApicSetIrq,
619 pdmR0PciHlp_Lock,
620 pdmR0PciHlp_Unlock,
621 PDM_PCIHLPR0_VERSION, /* the end */
622};
623
624/** @} */
625
626
627
628
629/** @name HPET Ring-0 Helpers
630 * @{
631 */
632
633/**
634 * The Ring-0 HPET Helper Callbacks.
635 */
636extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
637{
638 PDM_HPETHLPR0_VERSION,
639 PDM_HPETHLPR0_VERSION, /* the end */
640};
641
642/** @} */
643
644
645
646
647/** @name Ring-0 Context Driver Helpers
648 * @{
649 */
650
651/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
652static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
653{
654 PDMDRV_ASSERT_DRVINS(pDrvIns);
655 va_list args;
656 va_start(args, pszFormat);
657 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
658 va_end(args);
659 return rc;
660}
661
662
663/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
664static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
665{
666 PDMDRV_ASSERT_DRVINS(pDrvIns);
667 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
668 return rc;
669}
670
671
672/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
673static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
674{
675 PDMDRV_ASSERT_DRVINS(pDrvIns);
676 va_list va;
677 va_start(va, pszFormat);
678 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
679 va_end(va);
680 return rc;
681}
682
683
684/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
685static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
686{
687 PDMDRV_ASSERT_DRVINS(pDrvIns);
688 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
689 return rc;
690}
691
692
693/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
694static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
695{
696 PDMDRV_ASSERT_DRVINS(pDrvIns);
697 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
698 return true;
699
700 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
701 RTAssertPanic();
702 return false;
703}
704
705
706/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
707static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
708{
709 PDMDRV_ASSERT_DRVINS(pDrvIns);
710 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
711 return true;
712
713 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
714 RTAssertPanic();
715 return false;
716}
717
718
719/**
720 * The Raw-Mode Context Driver Helper Callbacks.
721 */
722extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
723{
724 PDM_DRVHLPRC_VERSION,
725 pdmR0DrvHlp_VMSetError,
726 pdmR0DrvHlp_VMSetErrorV,
727 pdmR0DrvHlp_VMSetRuntimeError,
728 pdmR0DrvHlp_VMSetRuntimeErrorV,
729 pdmR0DrvHlp_AssertEMT,
730 pdmR0DrvHlp_AssertOther,
731 PDM_DRVHLPRC_VERSION
732};
733
734/** @} */
735
736
737
738
739/**
740 * Sets an irq on the I/O APIC.
741 *
742 * @param pVM The VM handle.
743 * @param iIrq The irq.
744 * @param iLevel The new level.
745 */
746static void pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel)
747{
748 if ( ( pVM->pdm.s.IoApic.pDevInsR0
749 || !pVM->pdm.s.IoApic.pDevInsR3)
750 && ( pVM->pdm.s.Pic.pDevInsR0
751 || !pVM->pdm.s.Pic.pDevInsR3))
752 {
753 pdmLock(pVM);
754 if (pVM->pdm.s.Pic.pDevInsR0)
755 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel);
756 if (pVM->pdm.s.IoApic.pDevInsR0)
757 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
758 pdmUnlock(pVM);
759 }
760 else
761 {
762 /* queue for ring-3 execution. */
763 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
764 if (pTask)
765 {
766 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
767 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
768 pTask->u.SetIRQ.iIrq = iIrq;
769 pTask->u.SetIRQ.iLevel = iLevel;
770
771 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
772 }
773 else
774 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
775 }
776}
777
778
779/**
780 * Sets an irq on the I/O APIC.
781 *
782 * @param pVM The VM handle.
783 * @param iIrq The irq.
784 * @param iLevel The new level.
785 */
786static void pdmR0IoApicSetIrq(PVM pVM, int iIrq, int iLevel)
787{
788 if (pVM->pdm.s.IoApic.pDevInsR0)
789 {
790 pdmLock(pVM);
791 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel);
792 pdmUnlock(pVM);
793 }
794 else if (pVM->pdm.s.IoApic.pDevInsR3)
795 {
796 /* queue for ring-3 execution. */
797 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
798 if (pTask)
799 {
800 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
801 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
802 pTask->u.SetIRQ.iIrq = iIrq;
803 pTask->u.SetIRQ.iLevel = iLevel;
804
805 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
806 }
807 else
808 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
809 }
810}
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