VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 53349

Last change on this file since 53349 was 49548, checked in by vboxsync, 11 years ago

DevAPIC: reverted r90537, r90540, r90551 -- actually we need to clear the CPUID bit if the APIC enable bit is unset
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File size: 32.5 KB
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1/* $Id: PDMR0Device.cpp 49548 2013-11-19 13:07:10Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/vmm.h>
29#include <VBox/vmm/patm.h>
30#include <VBox/vmm/hm.h>
31
32#include <VBox/log.h>
33#include <VBox/err.h>
34#include <VBox/vmm/gvmm.h>
35#include <iprt/asm.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38
39#include "dtrace/VBoxVMM.h"
40#include "PDMInline.h"
41
42
43/*******************************************************************************
44* Global Variables *
45*******************************************************************************/
46RT_C_DECLS_BEGIN
47extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
48extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
49extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
50extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
51extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
52extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
53extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
54extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
55RT_C_DECLS_END
56
57
58/*******************************************************************************
59* Internal Functions *
60*******************************************************************************/
61static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc);
62
63
64
65/** @name Ring-0 Device Helpers
66 * @{
67 */
68
69/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
70static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
71{
72 PDMDEV_ASSERT_DEVINS(pDevIns);
73
74#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
75 /*
76 * Just check the busmaster setting here and forward the request to the generic read helper.
77 */
78 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
79 AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
80
81 if (!PCIDevIsBusmaster(pPciDev))
82 {
83 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
84 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
85 return VERR_PDM_NOT_PCI_BUS_MASTER;
86 }
87#endif
88
89 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
90}
91
92
93/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
94static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
95{
96 PDMDEV_ASSERT_DEVINS(pDevIns);
97
98#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
99 /*
100 * Just check the busmaster setting here and forward the request to the generic read helper.
101 */
102 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
103 AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
104
105 if (!PCIDevIsBusmaster(pPciDev))
106 {
107 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
108 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
109 return VERR_PDM_NOT_PCI_BUS_MASTER;
110 }
111#endif
112
113 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
114}
115
116
117/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
118static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
119{
120 PDMDEV_ASSERT_DEVINS(pDevIns);
121 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
122 PVM pVM = pDevIns->Internal.s.pVMR0;
123 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
124 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
125
126 pdmLock(pVM);
127 uint32_t uTagSrc;
128 if (iLevel & PDM_IRQ_LEVEL_HIGH)
129 {
130 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
131 if (iLevel == PDM_IRQ_LEVEL_HIGH)
132 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
133 else
134 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
135 }
136 else
137 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
138
139 if ( pPciDev
140 && pPciBus
141 && pPciBus->pDevInsR0)
142 {
143 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
144
145 pdmUnlock(pVM);
146
147 if (iLevel == PDM_IRQ_LEVEL_LOW)
148 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
149 }
150 else
151 {
152 pdmUnlock(pVM);
153
154 /* queue for ring-3 execution. */
155 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
156 AssertReturnVoid(pTask);
157
158 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
159 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
160 pTask->u.SetIRQ.iIrq = iIrq;
161 pTask->u.SetIRQ.iLevel = iLevel;
162 pTask->u.SetIRQ.uTagSrc = uTagSrc;
163
164 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
165 }
166
167 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
168}
169
170
171/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
172static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
173{
174 PDMDEV_ASSERT_DEVINS(pDevIns);
175 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
176 PVM pVM = pDevIns->Internal.s.pVMR0;
177
178 pdmLock(pVM);
179 uint32_t uTagSrc;
180 if (iLevel & PDM_IRQ_LEVEL_HIGH)
181 {
182 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
183 if (iLevel == PDM_IRQ_LEVEL_HIGH)
184 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
185 else
186 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
187 }
188 else
189 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
190
191 bool fRc = pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
192
193 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
194 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
195 pdmUnlock(pVM);
196 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
197}
198
199
200/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
201static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
202{
203 PDMDEV_ASSERT_DEVINS(pDevIns);
204 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
205 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
206
207 int rc = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead);
208 AssertRC(rc); /** @todo track down the users for this bugger. */
209
210 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
211 return rc;
212}
213
214
215/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
216static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
217{
218 PDMDEV_ASSERT_DEVINS(pDevIns);
219 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
220 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
221
222 int rc = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite);
223 AssertRC(rc); /** @todo track down the users for this bugger. */
224
225 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, rc));
226 return rc;
227}
228
229
230/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
231static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
232{
233 PDMDEV_ASSERT_DEVINS(pDevIns);
234 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
235
236 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
237
238 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
239 return fEnabled;
240}
241
242
243/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
244static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
245{
246 PDMDEV_ASSERT_DEVINS(pDevIns);
247
248 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
249
250 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
251 return enmVMState;
252}
253
254
255/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
256static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
257{
258 PDMDEV_ASSERT_DEVINS(pDevIns);
259 va_list args;
260 va_start(args, pszFormat);
261 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
262 va_end(args);
263 return rc;
264}
265
266
267/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
268static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
269{
270 PDMDEV_ASSERT_DEVINS(pDevIns);
271 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
272 return rc;
273}
274
275
276/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
277static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
278{
279 PDMDEV_ASSERT_DEVINS(pDevIns);
280 va_list va;
281 va_start(va, pszFormat);
282 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
283 va_end(va);
284 return rc;
285}
286
287
288/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
289static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
290{
291 PDMDEV_ASSERT_DEVINS(pDevIns);
292 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
293 return rc;
294}
295
296
297/** @interface_method_impl{PDMDEVHLPR0,pfnPATMSetMMIOPatchInfo} */
298static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
299{
300 PDMDEV_ASSERT_DEVINS(pDevIns);
301 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
302
303 AssertFailed();
304 NOREF(GCPhys); NOREF(pCachedData);
305
306/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
307 return VINF_SUCCESS;
308}
309
310
311/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
312static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
313{
314 PDMDEV_ASSERT_DEVINS(pDevIns);
315 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
316 return pDevIns->Internal.s.pVMR0;
317}
318
319
320/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
321static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
322{
323 PDMDEV_ASSERT_DEVINS(pDevIns);
324 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
325 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
326}
327
328
329/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
330static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
331{
332 PDMDEV_ASSERT_DEVINS(pDevIns);
333 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
334 return TMVirtualGet(pDevIns->Internal.s.pVMR0);
335}
336
337
338/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
339static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
340{
341 PDMDEV_ASSERT_DEVINS(pDevIns);
342 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
343 return TMVirtualGetFreq(pDevIns->Internal.s.pVMR0);
344}
345
346
347/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
348static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
349{
350 PDMDEV_ASSERT_DEVINS(pDevIns);
351 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
352 return TMVirtualToNano(pDevIns->Internal.s.pVMR0, TMVirtualGet(pDevIns->Internal.s.pVMR0));
353}
354
355
356/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
357static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
358{
359 PDMDEV_ASSERT_DEVINS(pDevIns);
360 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR0->hTraceBufR0;
361 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
362 return hTraceBuf;
363}
364
365
366/** @interface_method_impl{PDMDEVHLPR0,pfnCanEmulateIoBlock} */
367static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
368{
369 PDMDEV_ASSERT_DEVINS(pDevIns);
370 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
371 return HMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
372}
373
374
375/**
376 * The Ring-0 Device Helper Callbacks.
377 */
378extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
379{
380 PDM_DEVHLPR0_VERSION,
381 pdmR0DevHlp_PCIPhysRead,
382 pdmR0DevHlp_PCIPhysWrite,
383 pdmR0DevHlp_PCISetIrq,
384 pdmR0DevHlp_ISASetIrq,
385 pdmR0DevHlp_PhysRead,
386 pdmR0DevHlp_PhysWrite,
387 pdmR0DevHlp_A20IsEnabled,
388 pdmR0DevHlp_VMState,
389 pdmR0DevHlp_VMSetError,
390 pdmR0DevHlp_VMSetErrorV,
391 pdmR0DevHlp_VMSetRuntimeError,
392 pdmR0DevHlp_VMSetRuntimeErrorV,
393 pdmR0DevHlp_PATMSetMMIOPatchInfo,
394 pdmR0DevHlp_GetVM,
395 pdmR0DevHlp_CanEmulateIoBlock,
396 pdmR0DevHlp_GetVMCPU,
397 pdmR0DevHlp_TMTimeVirtGet,
398 pdmR0DevHlp_TMTimeVirtGetFreq,
399 pdmR0DevHlp_TMTimeVirtGetNano,
400 pdmR0DevHlp_DBGFTraceBuf,
401 PDM_DEVHLPR0_VERSION
402};
403
404/** @} */
405
406
407
408
409/** @name PIC Ring-0 Helpers
410 * @{
411 */
412
413/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
414static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
415{
416 PDMDEV_ASSERT_DEVINS(pDevIns);
417 PVM pVM = pDevIns->Internal.s.pVMR0;
418
419 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
420 {
421 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
422 pDevIns, pDevIns->iInstance));
423 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
424 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 1);
425 return;
426 }
427
428 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
429
430 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
431 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
432
433 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
434}
435
436
437/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
438static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
439{
440 PDMDEV_ASSERT_DEVINS(pDevIns);
441 PVM pVM = pDevIns->Internal.s.pVMR0;
442
443 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
444 {
445 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
446 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
447 pDevIns, pDevIns->iInstance));
448 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
449 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 0);
450 return;
451 }
452
453 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
454
455 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
456 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
457
458 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
459}
460
461
462/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
463static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
464{
465 PDMDEV_ASSERT_DEVINS(pDevIns);
466 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
467}
468
469
470/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
471static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
472{
473 PDMDEV_ASSERT_DEVINS(pDevIns);
474 pdmUnlock(pDevIns->Internal.s.pVMR0);
475}
476
477
478/**
479 * The Ring-0 PIC Helper Callbacks.
480 */
481extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
482{
483 PDM_PICHLPR0_VERSION,
484 pdmR0PicHlp_SetInterruptFF,
485 pdmR0PicHlp_ClearInterruptFF,
486 pdmR0PicHlp_Lock,
487 pdmR0PicHlp_Unlock,
488 PDM_PICHLPR0_VERSION
489};
490
491/** @} */
492
493
494
495
496/** @name APIC Ring-0 Helpers
497 * @{
498 */
499
500/** @interface_method_impl{PDMAPICHLPR0,pfnSetInterruptFF} */
501static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
502{
503 PDMDEV_ASSERT_DEVINS(pDevIns);
504 PVM pVM = pDevIns->Internal.s.pVMR0;
505 PVMCPU pVCpu = &pVM->aCpus[idCpu];
506
507 AssertReturnVoid(idCpu < pVM->cCpus);
508
509 LogFlow(("pdmR0ApicHlp_SetInterruptFF: CPU%d=caller=%p/%d: VM_FF_INTERRUPT %d -> 1 (CPU%d)\n",
510 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu));
511
512 switch (enmType)
513 {
514 case PDMAPICIRQ_HARDWARE:
515 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
516 break;
517 case PDMAPICIRQ_NMI:
518 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
519 break;
520 case PDMAPICIRQ_SMI:
521 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
522 break;
523 case PDMAPICIRQ_EXTINT:
524 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
525 break;
526 default:
527 AssertMsgFailed(("enmType=%d\n", enmType));
528 break;
529 }
530
531 /* We need to wake up the target CPU. */
532 if (VMMGetCpuId(pVM) != idCpu)
533 {
534 switch (VMCPU_GET_STATE(pVCpu))
535 {
536 case VMCPUSTATE_STARTED_EXEC:
537 GVMMR0SchedPokeEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
538 break;
539
540 case VMCPUSTATE_STARTED_HALTED:
541 GVMMR0SchedWakeUpEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
542 break;
543
544 default:
545 break; /* nothing to do in other states. */
546 }
547 }
548}
549
550
551/** @interface_method_impl{PDMAPICHLPR0,pfnClearInterruptFF} */
552static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
553{
554 PDMDEV_ASSERT_DEVINS(pDevIns);
555 PVM pVM = pDevIns->Internal.s.pVMR0;
556 PVMCPU pVCpu = &pVM->aCpus[idCpu];
557
558 AssertReturnVoid(idCpu < pVM->cCpus);
559
560 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
561 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
562
563 /* Note: NMI/SMI can't be cleared. */
564 switch (enmType)
565 {
566 case PDMAPICIRQ_HARDWARE:
567 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
568 break;
569 case PDMAPICIRQ_EXTINT:
570 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
571 break;
572 default:
573 AssertMsgFailed(("enmType=%d\n", enmType));
574 break;
575 }
576}
577
578
579/** @interface_method_impl{PDMAPICHLPR0,pfnCalcIrqTag} */
580static DECLCALLBACK(uint32_t) pdmR0ApicHlp_CalcIrqTag(PPDMDEVINS pDevIns, uint8_t u8Level)
581{
582 PDMDEV_ASSERT_DEVINS(pDevIns);
583 PVM pVM = pDevIns->Internal.s.pVMR0;
584
585 pdmLock(pVM);
586
587 uint32_t uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
588 if (u8Level == PDM_IRQ_LEVEL_HIGH)
589 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
590 else
591 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
592
593
594 pdmUnlock(pVM);
595 LogFlow(("pdmR0ApicHlp_CalcIrqTag: caller=%p/%d: returns %#x (u8Level=%d)\n",
596 pDevIns, pDevIns->iInstance, uTagSrc, u8Level));
597 return uTagSrc;
598}
599
600
601/** @interface_method_impl{PDMAPICHLPR0,pfnChangeFeature} */
602static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
603{
604 PDMDEV_ASSERT_DEVINS(pDevIns);
605 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
606 switch (enmVersion)
607 {
608 case PDMAPICVERSION_NONE:
609 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
610 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
611 break;
612 case PDMAPICVERSION_APIC:
613 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
614 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
615 break;
616 case PDMAPICVERSION_X2APIC:
617 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
618 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
619 break;
620 default:
621 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
622 }
623}
624
625
626/** @interface_method_impl{PDMAPICHLPR0,pfnLock} */
627static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
628{
629 PDMDEV_ASSERT_DEVINS(pDevIns);
630 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
631}
632
633
634/** @interface_method_impl{PDMAPICHLPR0,pfnUnlock} */
635static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
636{
637 PDMDEV_ASSERT_DEVINS(pDevIns);
638 pdmUnlock(pDevIns->Internal.s.pVMR0);
639}
640
641
642/** @interface_method_impl{PDMAPICHLPR0,pfnGetCpuId} */
643static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
644{
645 PDMDEV_ASSERT_DEVINS(pDevIns);
646 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
647}
648
649
650/**
651 * The Ring-0 APIC Helper Callbacks.
652 */
653extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
654{
655 PDM_APICHLPR0_VERSION,
656 pdmR0ApicHlp_SetInterruptFF,
657 pdmR0ApicHlp_ClearInterruptFF,
658 pdmR0ApicHlp_CalcIrqTag,
659 pdmR0ApicHlp_ChangeFeature,
660 pdmR0ApicHlp_Lock,
661 pdmR0ApicHlp_Unlock,
662 pdmR0ApicHlp_GetCpuId,
663 PDM_APICHLPR0_VERSION
664};
665
666/** @} */
667
668
669
670
671/** @name I/O APIC Ring-0 Helpers
672 * @{
673 */
674
675/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
676static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
677 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc)
678{
679 PDMDEV_ASSERT_DEVINS(pDevIns);
680 PVM pVM = pDevIns->Internal.s.pVMR0;
681 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
682 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
683 Assert(pVM->pdm.s.Apic.pDevInsR0);
684 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
685 return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector,
686 u8Polarity, u8TriggerMode, uTagSrc);
687 return VINF_SUCCESS;
688}
689
690
691/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
692static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
693{
694 PDMDEV_ASSERT_DEVINS(pDevIns);
695 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
696}
697
698
699/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
700static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
701{
702 PDMDEV_ASSERT_DEVINS(pDevIns);
703 pdmUnlock(pDevIns->Internal.s.pVMR0);
704}
705
706
707/**
708 * The Ring-0 I/O APIC Helper Callbacks.
709 */
710extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
711{
712 PDM_IOAPICHLPR0_VERSION,
713 pdmR0IoApicHlp_ApicBusDeliver,
714 pdmR0IoApicHlp_Lock,
715 pdmR0IoApicHlp_Unlock,
716 PDM_IOAPICHLPR0_VERSION
717};
718
719/** @} */
720
721
722
723
724/** @name PCI Bus Ring-0 Helpers
725 * @{
726 */
727
728/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
729static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
730{
731 PDMDEV_ASSERT_DEVINS(pDevIns);
732 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
733 PVM pVM = pDevIns->Internal.s.pVMR0;
734
735 pdmLock(pVM);
736 pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
737 pdmUnlock(pVM);
738}
739
740
741/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
742static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
743{
744 PDMDEV_ASSERT_DEVINS(pDevIns);
745 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
746 PVM pVM = pDevIns->Internal.s.pVMR0;
747
748 if (pVM->pdm.s.IoApic.pDevInsR0)
749 {
750 pdmLock(pVM);
751 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
752 pdmUnlock(pVM);
753 }
754 else if (pVM->pdm.s.IoApic.pDevInsR3)
755 {
756 /* queue for ring-3 execution. */
757 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
758 if (pTask)
759 {
760 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
761 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
762 pTask->u.SetIRQ.iIrq = iIrq;
763 pTask->u.SetIRQ.iLevel = iLevel;
764 pTask->u.SetIRQ.uTagSrc = uTagSrc;
765
766 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
767 }
768 else
769 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
770 }
771}
772
773
774/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
775static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
776{
777 PDMDEV_ASSERT_DEVINS(pDevIns);
778 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
779 PVM pVM = pDevIns->Internal.s.pVMR0;
780 if (pVM->pdm.s.IoApic.pDevInsR0)
781 {
782 pdmLock(pVM);
783 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
784 pdmUnlock(pVM);
785 }
786 else
787 {
788 AssertFatalMsgFailed(("Lazy bastards!"));
789 }
790}
791
792
793/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
794static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
795{
796 PDMDEV_ASSERT_DEVINS(pDevIns);
797 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
798}
799
800
801/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
802static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
803{
804 PDMDEV_ASSERT_DEVINS(pDevIns);
805 pdmUnlock(pDevIns->Internal.s.pVMR0);
806}
807
808
809/**
810 * The Ring-0 PCI Bus Helper Callbacks.
811 */
812extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
813{
814 PDM_PCIHLPR0_VERSION,
815 pdmR0PciHlp_IsaSetIrq,
816 pdmR0PciHlp_IoApicSetIrq,
817 pdmR0PciHlp_IoApicSendMsi,
818 pdmR0PciHlp_Lock,
819 pdmR0PciHlp_Unlock,
820 PDM_PCIHLPR0_VERSION, /* the end */
821};
822
823/** @} */
824
825
826
827
828/** @name HPET Ring-0 Helpers
829 * @{
830 */
831/* none */
832
833/**
834 * The Ring-0 HPET Helper Callbacks.
835 */
836extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
837{
838 PDM_HPETHLPR0_VERSION,
839 PDM_HPETHLPR0_VERSION, /* the end */
840};
841
842/** @} */
843
844
845/** @name Raw PCI Ring-0 Helpers
846 * @{
847 */
848/* none */
849
850/**
851 * The Ring-0 PCI raw Helper Callbacks.
852 */
853extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
854{
855 PDM_PCIRAWHLPR0_VERSION,
856 PDM_PCIRAWHLPR0_VERSION, /* the end */
857};
858
859/** @} */
860
861
862/** @name Ring-0 Context Driver Helpers
863 * @{
864 */
865
866/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
867static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
868{
869 PDMDRV_ASSERT_DRVINS(pDrvIns);
870 va_list args;
871 va_start(args, pszFormat);
872 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
873 va_end(args);
874 return rc;
875}
876
877
878/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
879static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
880{
881 PDMDRV_ASSERT_DRVINS(pDrvIns);
882 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
883 return rc;
884}
885
886
887/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
888static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
889{
890 PDMDRV_ASSERT_DRVINS(pDrvIns);
891 va_list va;
892 va_start(va, pszFormat);
893 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
894 va_end(va);
895 return rc;
896}
897
898
899/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
900static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
901{
902 PDMDRV_ASSERT_DRVINS(pDrvIns);
903 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
904 return rc;
905}
906
907
908/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
909static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
910{
911 PDMDRV_ASSERT_DRVINS(pDrvIns);
912 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
913 return true;
914
915 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
916 RTAssertPanic();
917 return false;
918}
919
920
921/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
922static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
923{
924 PDMDRV_ASSERT_DRVINS(pDrvIns);
925 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
926 return true;
927
928 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
929 RTAssertPanic();
930 return false;
931}
932
933
934/** @interface_method_impl{PDMDRVHLPR0,pfnFTSetCheckpoint} */
935static DECLCALLBACK(int) pdmR0DrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
936{
937 PDMDRV_ASSERT_DRVINS(pDrvIns);
938 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMR0, enmType);
939}
940
941
942/**
943 * The Ring-0 Context Driver Helper Callbacks.
944 */
945extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
946{
947 PDM_DRVHLPRC_VERSION,
948 pdmR0DrvHlp_VMSetError,
949 pdmR0DrvHlp_VMSetErrorV,
950 pdmR0DrvHlp_VMSetRuntimeError,
951 pdmR0DrvHlp_VMSetRuntimeErrorV,
952 pdmR0DrvHlp_AssertEMT,
953 pdmR0DrvHlp_AssertOther,
954 pdmR0DrvHlp_FTSetCheckpoint,
955 PDM_DRVHLPRC_VERSION
956};
957
958/** @} */
959
960
961
962
963/**
964 * Sets an irq on the PIC and I/O APIC.
965 *
966 * @returns true if delivered, false if postponed.
967 * @param pVM Pointer to the VM.
968 * @param iIrq The irq.
969 * @param iLevel The new level.
970 * @param uTagSrc The IRQ tag and source.
971 *
972 * @remarks The caller holds the PDM lock.
973 */
974static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc)
975{
976 if (RT_LIKELY( ( pVM->pdm.s.IoApic.pDevInsR0
977 || !pVM->pdm.s.IoApic.pDevInsR3)
978 && ( pVM->pdm.s.Pic.pDevInsR0
979 || !pVM->pdm.s.Pic.pDevInsR3)))
980 {
981 if (pVM->pdm.s.Pic.pDevInsR0)
982 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
983 if (pVM->pdm.s.IoApic.pDevInsR0)
984 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
985 return true;
986 }
987
988 /* queue for ring-3 execution. */
989 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
990 AssertReturn(pTask, false);
991
992 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
993 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
994 pTask->u.SetIRQ.iIrq = iIrq;
995 pTask->u.SetIRQ.iLevel = iLevel;
996 pTask->u.SetIRQ.uTagSrc = uTagSrc;
997
998 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
999 return false;
1000}
1001
1002
1003/**
1004 * PDMDevHlpCallR0 helper.
1005 *
1006 * @returns See PFNPDMDEVREQHANDLERR0.
1007 * @param pVM Pointer to the VM (for validation).
1008 * @param pReq Pointer to the request buffer.
1009 */
1010VMMR0_INT_DECL(int) PDMR0DeviceCallReqHandler(PVM pVM, PPDMDEVICECALLREQHANDLERREQ pReq)
1011{
1012 /*
1013 * Validate input and make the call.
1014 */
1015 AssertPtrReturn(pVM, VERR_INVALID_POINTER);
1016 AssertPtrReturn(pReq, VERR_INVALID_POINTER);
1017 AssertMsgReturn(pReq->Hdr.cbReq == sizeof(*pReq), ("%#x != %#x\n", pReq->Hdr.cbReq, sizeof(*pReq)), VERR_INVALID_PARAMETER);
1018
1019 PPDMDEVINS pDevIns = pReq->pDevInsR0;
1020 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
1021 AssertReturn(pDevIns->Internal.s.pVMR0 == pVM, VERR_INVALID_PARAMETER);
1022
1023 PFNPDMDEVREQHANDLERR0 pfnReqHandlerR0 = pReq->pfnReqHandlerR0;
1024 AssertPtrReturn(pfnReqHandlerR0, VERR_INVALID_POINTER);
1025
1026 return pfnReqHandlerR0(pDevIns, pReq->uOperation, pReq->u64Arg);
1027}
1028
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