VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 58999

Last change on this file since 58999 was 58126, checked in by vboxsync, 9 years ago

VMM: Fixed almost all the Doxygen warnings.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 33.8 KB
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1/* $Id: PDMR0Device.cpp 58126 2015-10-08 20:59:48Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/vmm.h>
29#include <VBox/vmm/patm.h>
30#include <VBox/vmm/hm.h>
31
32#include <VBox/log.h>
33#include <VBox/err.h>
34#include <VBox/vmm/gvmm.h>
35#include <iprt/asm.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38
39#include "dtrace/VBoxVMM.h"
40#include "PDMInline.h"
41
42
43/*********************************************************************************************************************************
44* Global Variables *
45*********************************************************************************************************************************/
46RT_C_DECLS_BEGIN
47extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
48extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
49extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
50extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
51extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
52extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
53extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
54extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
55RT_C_DECLS_END
56
57
58/*********************************************************************************************************************************
59* Internal Functions *
60*********************************************************************************************************************************/
61static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc);
62
63
64
65/** @name Ring-0 Device Helpers
66 * @{
67 */
68
69/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
70static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
71{
72 PDMDEV_ASSERT_DEVINS(pDevIns);
73
74#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
75 /*
76 * Just check the busmaster setting here and forward the request to the generic read helper.
77 */
78 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
79 AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
80
81 if (!PCIDevIsBusmaster(pPciDev))
82 {
83 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
84 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
85 return VERR_PDM_NOT_PCI_BUS_MASTER;
86 }
87#endif
88
89 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
90}
91
92
93/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
94static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
95{
96 PDMDEV_ASSERT_DEVINS(pDevIns);
97
98#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
99 /*
100 * Just check the busmaster setting here and forward the request to the generic read helper.
101 */
102 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
103 AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
104
105 if (!PCIDevIsBusmaster(pPciDev))
106 {
107 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
108 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
109 return VERR_PDM_NOT_PCI_BUS_MASTER;
110 }
111#endif
112
113 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
114}
115
116
117/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
118static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
119{
120 PDMDEV_ASSERT_DEVINS(pDevIns);
121 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
122 PVM pVM = pDevIns->Internal.s.pVMR0;
123 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
124 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
125
126 pdmLock(pVM);
127 uint32_t uTagSrc;
128 if (iLevel & PDM_IRQ_LEVEL_HIGH)
129 {
130 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
131 if (iLevel == PDM_IRQ_LEVEL_HIGH)
132 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
133 else
134 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
135 }
136 else
137 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
138
139 if ( pPciDev
140 && pPciBus
141 && pPciBus->pDevInsR0)
142 {
143 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
144
145 pdmUnlock(pVM);
146
147 if (iLevel == PDM_IRQ_LEVEL_LOW)
148 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
149 }
150 else
151 {
152 pdmUnlock(pVM);
153
154 /* queue for ring-3 execution. */
155 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
156 AssertReturnVoid(pTask);
157
158 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
159 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
160 pTask->u.SetIRQ.iIrq = iIrq;
161 pTask->u.SetIRQ.iLevel = iLevel;
162 pTask->u.SetIRQ.uTagSrc = uTagSrc;
163
164 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
165 }
166
167 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
168}
169
170
171/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
172static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
173{
174 PDMDEV_ASSERT_DEVINS(pDevIns);
175 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
176 PVM pVM = pDevIns->Internal.s.pVMR0;
177
178 pdmLock(pVM);
179 uint32_t uTagSrc;
180 if (iLevel & PDM_IRQ_LEVEL_HIGH)
181 {
182 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
183 if (iLevel == PDM_IRQ_LEVEL_HIGH)
184 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
185 else
186 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
187 }
188 else
189 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
190
191 bool fRc = pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
192
193 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
194 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
195 pdmUnlock(pVM);
196 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
197}
198
199
200/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
201static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
202{
203 PDMDEV_ASSERT_DEVINS(pDevIns);
204 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
205 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
206
207 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
208 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
209
210 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
211 return VBOXSTRICTRC_VAL(rcStrict);
212}
213
214
215/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
216static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
217{
218 PDMDEV_ASSERT_DEVINS(pDevIns);
219 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
220 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
221
222 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
223 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
224
225 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
226 return VBOXSTRICTRC_VAL(rcStrict);
227}
228
229
230/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
231static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
232{
233 PDMDEV_ASSERT_DEVINS(pDevIns);
234 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
235
236 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
237
238 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
239 return fEnabled;
240}
241
242
243/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
244static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
245{
246 PDMDEV_ASSERT_DEVINS(pDevIns);
247
248 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
249
250 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
251 return enmVMState;
252}
253
254
255/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
256static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
257{
258 PDMDEV_ASSERT_DEVINS(pDevIns);
259 va_list args;
260 va_start(args, pszFormat);
261 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
262 va_end(args);
263 return rc;
264}
265
266
267/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
268static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
269{
270 PDMDEV_ASSERT_DEVINS(pDevIns);
271 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
272 return rc;
273}
274
275
276/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
277static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
278{
279 PDMDEV_ASSERT_DEVINS(pDevIns);
280 va_list va;
281 va_start(va, pszFormat);
282 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
283 va_end(va);
284 return rc;
285}
286
287
288/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
289static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
290{
291 PDMDEV_ASSERT_DEVINS(pDevIns);
292 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
293 return rc;
294}
295
296
297/** @interface_method_impl{PDMDEVHLPR0,pfnPATMSetMMIOPatchInfo} */
298static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
299{
300 PDMDEV_ASSERT_DEVINS(pDevIns);
301 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
302
303 AssertFailed();
304 NOREF(GCPhys); NOREF(pCachedData); NOREF(pDevIns);
305
306/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
307 return VINF_SUCCESS;
308}
309
310
311/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
312static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
313{
314 PDMDEV_ASSERT_DEVINS(pDevIns);
315 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
316 return pDevIns->Internal.s.pVMR0;
317}
318
319
320/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
321static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
322{
323 PDMDEV_ASSERT_DEVINS(pDevIns);
324 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
325 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
326}
327
328
329/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
330static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
331{
332 PDMDEV_ASSERT_DEVINS(pDevIns);
333 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR0);
334 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
335 return idCpu;
336}
337
338
339/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
340static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
341{
342 PDMDEV_ASSERT_DEVINS(pDevIns);
343 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
344 return TMVirtualGet(pDevIns->Internal.s.pVMR0);
345}
346
347
348/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
349static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
350{
351 PDMDEV_ASSERT_DEVINS(pDevIns);
352 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
353 return TMVirtualGetFreq(pDevIns->Internal.s.pVMR0);
354}
355
356
357/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
358static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
359{
360 PDMDEV_ASSERT_DEVINS(pDevIns);
361 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
362 return TMVirtualToNano(pDevIns->Internal.s.pVMR0, TMVirtualGet(pDevIns->Internal.s.pVMR0));
363}
364
365
366/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
367static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
368{
369 PDMDEV_ASSERT_DEVINS(pDevIns);
370 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR0->hTraceBufR0;
371 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
372 return hTraceBuf;
373}
374
375
376/** @interface_method_impl{PDMDEVHLPR0,pfnCanEmulateIoBlock} */
377static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
378{
379 PDMDEV_ASSERT_DEVINS(pDevIns);
380 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
381 return HMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
382}
383
384
385/**
386 * The Ring-0 Device Helper Callbacks.
387 */
388extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
389{
390 PDM_DEVHLPR0_VERSION,
391 pdmR0DevHlp_PCIPhysRead,
392 pdmR0DevHlp_PCIPhysWrite,
393 pdmR0DevHlp_PCISetIrq,
394 pdmR0DevHlp_ISASetIrq,
395 pdmR0DevHlp_PhysRead,
396 pdmR0DevHlp_PhysWrite,
397 pdmR0DevHlp_A20IsEnabled,
398 pdmR0DevHlp_VMState,
399 pdmR0DevHlp_VMSetError,
400 pdmR0DevHlp_VMSetErrorV,
401 pdmR0DevHlp_VMSetRuntimeError,
402 pdmR0DevHlp_VMSetRuntimeErrorV,
403 pdmR0DevHlp_PATMSetMMIOPatchInfo,
404 pdmR0DevHlp_GetVM,
405 pdmR0DevHlp_CanEmulateIoBlock,
406 pdmR0DevHlp_GetVMCPU,
407 pdmR0DevHlp_GetCurrentCpuId,
408 pdmR0DevHlp_TMTimeVirtGet,
409 pdmR0DevHlp_TMTimeVirtGetFreq,
410 pdmR0DevHlp_TMTimeVirtGetNano,
411 pdmR0DevHlp_DBGFTraceBuf,
412 PDM_DEVHLPR0_VERSION
413};
414
415/** @} */
416
417
418
419
420/** @name PIC Ring-0 Helpers
421 * @{
422 */
423
424/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
425static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
426{
427 PDMDEV_ASSERT_DEVINS(pDevIns);
428 PVM pVM = pDevIns->Internal.s.pVMR0;
429
430 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
431 {
432 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
433 pDevIns, pDevIns->iInstance));
434 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
435 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 1);
436 return;
437 }
438
439 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
440
441 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
442 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
443
444 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
445}
446
447
448/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
449static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
450{
451 PDMDEV_ASSERT_DEVINS(pDevIns);
452 PVM pVM = pDevIns->Internal.s.pVMR0;
453
454 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
455 {
456 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
457 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
458 pDevIns, pDevIns->iInstance));
459 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
460 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, 0, 0);
461 return;
462 }
463
464 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
465
466 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
467 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
468
469 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
470}
471
472
473/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
474static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
475{
476 PDMDEV_ASSERT_DEVINS(pDevIns);
477 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
478}
479
480
481/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
482static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
483{
484 PDMDEV_ASSERT_DEVINS(pDevIns);
485 pdmUnlock(pDevIns->Internal.s.pVMR0);
486}
487
488
489/**
490 * The Ring-0 PIC Helper Callbacks.
491 */
492extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
493{
494 PDM_PICHLPR0_VERSION,
495 pdmR0PicHlp_SetInterruptFF,
496 pdmR0PicHlp_ClearInterruptFF,
497 pdmR0PicHlp_Lock,
498 pdmR0PicHlp_Unlock,
499 PDM_PICHLPR0_VERSION
500};
501
502/** @} */
503
504
505
506
507/** @name APIC Ring-0 Helpers
508 * @{
509 */
510
511/** @interface_method_impl{PDMAPICHLPR0,pfnSetInterruptFF} */
512static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
513{
514 PDMDEV_ASSERT_DEVINS(pDevIns);
515 PVM pVM = pDevIns->Internal.s.pVMR0;
516 PVMCPU pVCpu = &pVM->aCpus[idCpu];
517
518 AssertReturnVoid(idCpu < pVM->cCpus);
519
520 LogFlow(("pdmR0ApicHlp_SetInterruptFF: CPU%d=caller=%p/%d: VM_FF_INTERRUPT %d -> 1 (CPU%d)\n",
521 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu));
522
523 switch (enmType)
524 {
525 case PDMAPICIRQ_HARDWARE:
526 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
527 break;
528 case PDMAPICIRQ_NMI:
529 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
530 break;
531 case PDMAPICIRQ_SMI:
532 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
533 break;
534 case PDMAPICIRQ_EXTINT:
535 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
536 break;
537 default:
538 AssertMsgFailed(("enmType=%d\n", enmType));
539 break;
540 }
541
542 /* We need to wake up the target CPU. */
543 if (VMMGetCpuId(pVM) != idCpu)
544 {
545 switch (VMCPU_GET_STATE(pVCpu))
546 {
547 case VMCPUSTATE_STARTED_EXEC:
548 GVMMR0SchedPokeEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
549 break;
550
551 case VMCPUSTATE_STARTED_HALTED:
552 GVMMR0SchedWakeUpEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
553 break;
554
555 default:
556 break; /* nothing to do in other states. */
557 }
558 }
559}
560
561
562/** @interface_method_impl{PDMAPICHLPR0,pfnClearInterruptFF} */
563static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
564{
565 PDMDEV_ASSERT_DEVINS(pDevIns);
566 PVM pVM = pDevIns->Internal.s.pVMR0;
567 PVMCPU pVCpu = &pVM->aCpus[idCpu];
568
569 AssertReturnVoid(idCpu < pVM->cCpus);
570
571 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
572 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
573
574 /* Note: NMI/SMI can't be cleared. */
575 switch (enmType)
576 {
577 case PDMAPICIRQ_HARDWARE:
578 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
579 break;
580 case PDMAPICIRQ_EXTINT:
581 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
582 break;
583 default:
584 AssertMsgFailed(("enmType=%d\n", enmType));
585 break;
586 }
587}
588
589
590/** @interface_method_impl{PDMAPICHLPR0,pfnCalcIrqTag} */
591static DECLCALLBACK(uint32_t) pdmR0ApicHlp_CalcIrqTag(PPDMDEVINS pDevIns, uint8_t u8Level)
592{
593 PDMDEV_ASSERT_DEVINS(pDevIns);
594 PVM pVM = pDevIns->Internal.s.pVMR0;
595
596 pdmLock(pVM);
597
598 uint32_t uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
599 if (u8Level == PDM_IRQ_LEVEL_HIGH)
600 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
601 else
602 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
603
604
605 pdmUnlock(pVM);
606 LogFlow(("pdmR0ApicHlp_CalcIrqTag: caller=%p/%d: returns %#x (u8Level=%d)\n",
607 pDevIns, pDevIns->iInstance, uTagSrc, u8Level));
608 return uTagSrc;
609}
610
611
612/** @interface_method_impl{PDMAPICHLPR0,pfnChangeFeature} */
613static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICVERSION enmVersion)
614{
615 PDMDEV_ASSERT_DEVINS(pDevIns);
616 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: version=%d\n", pDevIns, pDevIns->iInstance, (int)enmVersion));
617 switch (enmVersion)
618 {
619 case PDMAPICVERSION_NONE:
620 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
621 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
622 break;
623 case PDMAPICVERSION_APIC:
624 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
625 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
626 break;
627 case PDMAPICVERSION_X2APIC:
628 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
629 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
630 break;
631 default:
632 AssertMsgFailed(("Unknown APIC version: %d\n", (int)enmVersion));
633 }
634}
635
636
637/** @interface_method_impl{PDMAPICHLPR0,pfnLock} */
638static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
639{
640 PDMDEV_ASSERT_DEVINS(pDevIns);
641 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
642}
643
644
645/** @interface_method_impl{PDMAPICHLPR0,pfnUnlock} */
646static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
647{
648 PDMDEV_ASSERT_DEVINS(pDevIns);
649 pdmUnlock(pDevIns->Internal.s.pVMR0);
650}
651
652
653/** @interface_method_impl{PDMAPICHLPR0,pfnGetCpuId} */
654static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
655{
656 PDMDEV_ASSERT_DEVINS(pDevIns);
657 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
658}
659
660
661/**
662 * The Ring-0 APIC Helper Callbacks.
663 */
664extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
665{
666 PDM_APICHLPR0_VERSION,
667 pdmR0ApicHlp_SetInterruptFF,
668 pdmR0ApicHlp_ClearInterruptFF,
669 pdmR0ApicHlp_CalcIrqTag,
670 pdmR0ApicHlp_ChangeFeature,
671 pdmR0ApicHlp_Lock,
672 pdmR0ApicHlp_Unlock,
673 pdmR0ApicHlp_GetCpuId,
674 PDM_APICHLPR0_VERSION
675};
676
677/** @} */
678
679
680
681
682/** @name I/O APIC Ring-0 Helpers
683 * @{
684 */
685
686/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
687static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
688 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc)
689{
690 PDMDEV_ASSERT_DEVINS(pDevIns);
691 PVM pVM = pDevIns->Internal.s.pVMR0;
692 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
693 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
694 Assert(pVM->pdm.s.Apic.pDevInsR0);
695 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
696 return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector,
697 u8Polarity, u8TriggerMode, uTagSrc);
698 return VINF_SUCCESS;
699}
700
701
702/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
703static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
704{
705 PDMDEV_ASSERT_DEVINS(pDevIns);
706 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
707}
708
709
710/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
711static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
712{
713 PDMDEV_ASSERT_DEVINS(pDevIns);
714 pdmUnlock(pDevIns->Internal.s.pVMR0);
715}
716
717
718/**
719 * The Ring-0 I/O APIC Helper Callbacks.
720 */
721extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
722{
723 PDM_IOAPICHLPR0_VERSION,
724 pdmR0IoApicHlp_ApicBusDeliver,
725 pdmR0IoApicHlp_Lock,
726 pdmR0IoApicHlp_Unlock,
727 PDM_IOAPICHLPR0_VERSION
728};
729
730/** @} */
731
732
733
734
735/** @name PCI Bus Ring-0 Helpers
736 * @{
737 */
738
739/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
740static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
741{
742 PDMDEV_ASSERT_DEVINS(pDevIns);
743 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
744 PVM pVM = pDevIns->Internal.s.pVMR0;
745
746 pdmLock(pVM);
747 pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
748 pdmUnlock(pVM);
749}
750
751
752/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
753static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
754{
755 PDMDEV_ASSERT_DEVINS(pDevIns);
756 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
757 PVM pVM = pDevIns->Internal.s.pVMR0;
758
759 if (pVM->pdm.s.IoApic.pDevInsR0)
760 {
761 pdmLock(pVM);
762 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
763 pdmUnlock(pVM);
764 }
765 else if (pVM->pdm.s.IoApic.pDevInsR3)
766 {
767 /* queue for ring-3 execution. */
768 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
769 if (pTask)
770 {
771 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
772 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
773 pTask->u.SetIRQ.iIrq = iIrq;
774 pTask->u.SetIRQ.iLevel = iLevel;
775 pTask->u.SetIRQ.uTagSrc = uTagSrc;
776
777 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
778 }
779 else
780 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
781 }
782}
783
784
785/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
786static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
787{
788 PDMDEV_ASSERT_DEVINS(pDevIns);
789 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
790 PVM pVM = pDevIns->Internal.s.pVMR0;
791 if (pVM->pdm.s.IoApic.pDevInsR0)
792 {
793 pdmLock(pVM);
794 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
795 pdmUnlock(pVM);
796 }
797 else
798 {
799 AssertFatalMsgFailed(("Lazy bastards!"));
800 }
801}
802
803
804/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
805static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
806{
807 PDMDEV_ASSERT_DEVINS(pDevIns);
808 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
809}
810
811
812/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
813static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
814{
815 PDMDEV_ASSERT_DEVINS(pDevIns);
816 pdmUnlock(pDevIns->Internal.s.pVMR0);
817}
818
819
820/**
821 * The Ring-0 PCI Bus Helper Callbacks.
822 */
823extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
824{
825 PDM_PCIHLPR0_VERSION,
826 pdmR0PciHlp_IsaSetIrq,
827 pdmR0PciHlp_IoApicSetIrq,
828 pdmR0PciHlp_IoApicSendMsi,
829 pdmR0PciHlp_Lock,
830 pdmR0PciHlp_Unlock,
831 PDM_PCIHLPR0_VERSION, /* the end */
832};
833
834/** @} */
835
836
837
838
839/** @name HPET Ring-0 Helpers
840 * @{
841 */
842/* none */
843
844/**
845 * The Ring-0 HPET Helper Callbacks.
846 */
847extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
848{
849 PDM_HPETHLPR0_VERSION,
850 PDM_HPETHLPR0_VERSION, /* the end */
851};
852
853/** @} */
854
855
856/** @name Raw PCI Ring-0 Helpers
857 * @{
858 */
859/* none */
860
861/**
862 * The Ring-0 PCI raw Helper Callbacks.
863 */
864extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
865{
866 PDM_PCIRAWHLPR0_VERSION,
867 PDM_PCIRAWHLPR0_VERSION, /* the end */
868};
869
870/** @} */
871
872
873/** @name Ring-0 Context Driver Helpers
874 * @{
875 */
876
877/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
878static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
879{
880 PDMDRV_ASSERT_DRVINS(pDrvIns);
881 va_list args;
882 va_start(args, pszFormat);
883 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
884 va_end(args);
885 return rc;
886}
887
888
889/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
890static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
891{
892 PDMDRV_ASSERT_DRVINS(pDrvIns);
893 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
894 return rc;
895}
896
897
898/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
899static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
900 const char *pszFormat, ...)
901{
902 PDMDRV_ASSERT_DRVINS(pDrvIns);
903 va_list va;
904 va_start(va, pszFormat);
905 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
906 va_end(va);
907 return rc;
908}
909
910
911/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeErrorV} */
912static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
913 const char *pszFormat, va_list va)
914{
915 PDMDRV_ASSERT_DRVINS(pDrvIns);
916 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
917 return rc;
918}
919
920
921/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
922static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
923{
924 PDMDRV_ASSERT_DRVINS(pDrvIns);
925 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
926 return true;
927
928 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
929 RTAssertPanic();
930 return false;
931}
932
933
934/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
935static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
936{
937 PDMDRV_ASSERT_DRVINS(pDrvIns);
938 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
939 return true;
940
941 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
942 RTAssertPanic();
943 return false;
944}
945
946
947/** @interface_method_impl{PDMDRVHLPR0,pfnFTSetCheckpoint} */
948static DECLCALLBACK(int) pdmR0DrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
949{
950 PDMDRV_ASSERT_DRVINS(pDrvIns);
951 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMR0, enmType);
952}
953
954
955/**
956 * The Ring-0 Context Driver Helper Callbacks.
957 */
958extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
959{
960 PDM_DRVHLPRC_VERSION,
961 pdmR0DrvHlp_VMSetError,
962 pdmR0DrvHlp_VMSetErrorV,
963 pdmR0DrvHlp_VMSetRuntimeError,
964 pdmR0DrvHlp_VMSetRuntimeErrorV,
965 pdmR0DrvHlp_AssertEMT,
966 pdmR0DrvHlp_AssertOther,
967 pdmR0DrvHlp_FTSetCheckpoint,
968 PDM_DRVHLPRC_VERSION
969};
970
971/** @} */
972
973
974
975
976/**
977 * Sets an irq on the PIC and I/O APIC.
978 *
979 * @returns true if delivered, false if postponed.
980 * @param pVM The cross context VM structure.
981 * @param iIrq The irq.
982 * @param iLevel The new level.
983 * @param uTagSrc The IRQ tag and source.
984 *
985 * @remarks The caller holds the PDM lock.
986 */
987static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc)
988{
989 if (RT_LIKELY( ( pVM->pdm.s.IoApic.pDevInsR0
990 || !pVM->pdm.s.IoApic.pDevInsR3)
991 && ( pVM->pdm.s.Pic.pDevInsR0
992 || !pVM->pdm.s.Pic.pDevInsR3)))
993 {
994 if (pVM->pdm.s.Pic.pDevInsR0)
995 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
996 if (pVM->pdm.s.IoApic.pDevInsR0)
997 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
998 return true;
999 }
1000
1001 /* queue for ring-3 execution. */
1002 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
1003 AssertReturn(pTask, false);
1004
1005 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1006 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1007 pTask->u.SetIRQ.iIrq = iIrq;
1008 pTask->u.SetIRQ.iLevel = iLevel;
1009 pTask->u.SetIRQ.uTagSrc = uTagSrc;
1010
1011 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1012 return false;
1013}
1014
1015
1016/**
1017 * PDMDevHlpCallR0 helper.
1018 *
1019 * @returns See PFNPDMDEVREQHANDLERR0.
1020 * @param pVM The cross context VM structure. (For validation.)
1021 * @param pReq Pointer to the request buffer.
1022 */
1023VMMR0_INT_DECL(int) PDMR0DeviceCallReqHandler(PVM pVM, PPDMDEVICECALLREQHANDLERREQ pReq)
1024{
1025 /*
1026 * Validate input and make the call.
1027 */
1028 AssertPtrReturn(pVM, VERR_INVALID_POINTER);
1029 AssertPtrReturn(pReq, VERR_INVALID_POINTER);
1030 AssertMsgReturn(pReq->Hdr.cbReq == sizeof(*pReq), ("%#x != %#x\n", pReq->Hdr.cbReq, sizeof(*pReq)), VERR_INVALID_PARAMETER);
1031
1032 PPDMDEVINS pDevIns = pReq->pDevInsR0;
1033 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
1034 AssertReturn(pDevIns->Internal.s.pVMR0 == pVM, VERR_INVALID_PARAMETER);
1035
1036 PFNPDMDEVREQHANDLERR0 pfnReqHandlerR0 = pReq->pfnReqHandlerR0;
1037 AssertPtrReturn(pfnReqHandlerR0, VERR_INVALID_POINTER);
1038
1039 return pfnReqHandlerR0(pDevIns, pReq->uOperation, pReq->u64Arg);
1040}
1041
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