VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 61627

Last change on this file since 61627 was 61356, checked in by vboxsync, 9 years ago

VMM/PDM: comment nit.
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1/* $Id: PDMR0Device.cpp 61356 2016-06-01 07:32:20Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/vm.h>
28#include <VBox/vmm/vmm.h>
29#include <VBox/vmm/patm.h>
30#include <VBox/vmm/hm.h>
31
32#include <VBox/log.h>
33#include <VBox/err.h>
34#include <VBox/vmm/gvmm.h>
35#include <iprt/asm.h>
36#include <iprt/assert.h>
37#include <iprt/string.h>
38
39#include "dtrace/VBoxVMM.h"
40#include "PDMInline.h"
41
42
43/*********************************************************************************************************************************
44* Global Variables *
45*********************************************************************************************************************************/
46RT_C_DECLS_BEGIN
47extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
48extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
49extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp;
50extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
51extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
52extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
53extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
54extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
55RT_C_DECLS_END
56
57
58/*********************************************************************************************************************************
59* Internal Functions *
60*********************************************************************************************************************************/
61static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc);
62
63
64
65/** @name Ring-0 Device Helpers
66 * @{
67 */
68
69/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
70static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
71{
72 PDMDEV_ASSERT_DEVINS(pDevIns);
73
74#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
75 /*
76 * Just check the busmaster setting here and forward the request to the generic read helper.
77 */
78 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
79 AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
80
81 if (!PCIDevIsBusmaster(pPciDev))
82 {
83 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
84 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
85 return VERR_PDM_NOT_PCI_BUS_MASTER;
86 }
87#endif
88
89 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
90}
91
92
93/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
94static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
95{
96 PDMDEV_ASSERT_DEVINS(pDevIns);
97
98#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
99 /*
100 * Just check the busmaster setting here and forward the request to the generic read helper.
101 */
102 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
103 AssertReleaseMsg(pPciDev, ("No PCI device registered!\n"));
104
105 if (!PCIDevIsBusmaster(pPciDev))
106 {
107 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
108 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
109 return VERR_PDM_NOT_PCI_BUS_MASTER;
110 }
111#endif
112
113 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
114}
115
116
117/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
118static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
119{
120 PDMDEV_ASSERT_DEVINS(pDevIns);
121 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
122 PVM pVM = pDevIns->Internal.s.pVMR0;
123 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0;
124 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0;
125
126 pdmLock(pVM);
127 uint32_t uTagSrc;
128 if (iLevel & PDM_IRQ_LEVEL_HIGH)
129 {
130 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
131 if (iLevel == PDM_IRQ_LEVEL_HIGH)
132 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
133 else
134 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
135 }
136 else
137 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
138
139 if ( pPciDev
140 && pPciBus
141 && pPciBus->pDevInsR0)
142 {
143 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
144
145 pdmUnlock(pVM);
146
147 if (iLevel == PDM_IRQ_LEVEL_LOW)
148 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
149 }
150 else
151 {
152 pdmUnlock(pVM);
153
154 /* queue for ring-3 execution. */
155 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
156 AssertReturnVoid(pTask);
157
158 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
159 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
160 pTask->u.SetIRQ.iIrq = iIrq;
161 pTask->u.SetIRQ.iLevel = iLevel;
162 pTask->u.SetIRQ.uTagSrc = uTagSrc;
163
164 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
165 }
166
167 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
168}
169
170
171/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
172static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
173{
174 PDMDEV_ASSERT_DEVINS(pDevIns);
175 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
176 PVM pVM = pDevIns->Internal.s.pVMR0;
177
178 pdmLock(pVM);
179 uint32_t uTagSrc;
180 if (iLevel & PDM_IRQ_LEVEL_HIGH)
181 {
182 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
183 if (iLevel == PDM_IRQ_LEVEL_HIGH)
184 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
185 else
186 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
187 }
188 else
189 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
190
191 bool fRc = pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
192
193 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
194 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
195 pdmUnlock(pVM);
196 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
197}
198
199
200/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
201static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
202{
203 PDMDEV_ASSERT_DEVINS(pDevIns);
204 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
205 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
206
207 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
208 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
209
210 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
211 return VBOXSTRICTRC_VAL(rcStrict);
212}
213
214
215/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
216static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
217{
218 PDMDEV_ASSERT_DEVINS(pDevIns);
219 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
220 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
221
222 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
223 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
224
225 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
226 return VBOXSTRICTRC_VAL(rcStrict);
227}
228
229
230/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
231static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
232{
233 PDMDEV_ASSERT_DEVINS(pDevIns);
234 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
235
236 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
237
238 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
239 return fEnabled;
240}
241
242
243/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
244static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
245{
246 PDMDEV_ASSERT_DEVINS(pDevIns);
247
248 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
249
250 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
251 return enmVMState;
252}
253
254
255/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
256static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
257{
258 PDMDEV_ASSERT_DEVINS(pDevIns);
259 va_list args;
260 va_start(args, pszFormat);
261 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
262 va_end(args);
263 return rc;
264}
265
266
267/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
268static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
269{
270 PDMDEV_ASSERT_DEVINS(pDevIns);
271 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
272 return rc;
273}
274
275
276/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
277static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
278{
279 PDMDEV_ASSERT_DEVINS(pDevIns);
280 va_list va;
281 va_start(va, pszFormat);
282 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
283 va_end(va);
284 return rc;
285}
286
287
288/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
289static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
290{
291 PDMDEV_ASSERT_DEVINS(pDevIns);
292 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
293 return rc;
294}
295
296
297/** @interface_method_impl{PDMDEVHLPR0,pfnPATMSetMMIOPatchInfo} */
298static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
299{
300 PDMDEV_ASSERT_DEVINS(pDevIns);
301 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
302
303 AssertFailed();
304 NOREF(GCPhys); NOREF(pCachedData); NOREF(pDevIns);
305
306/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
307 return VINF_SUCCESS;
308}
309
310
311/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
312static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
313{
314 PDMDEV_ASSERT_DEVINS(pDevIns);
315 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
316 return pDevIns->Internal.s.pVMR0;
317}
318
319
320/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
321static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
322{
323 PDMDEV_ASSERT_DEVINS(pDevIns);
324 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
325 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
326}
327
328
329/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
330static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
331{
332 PDMDEV_ASSERT_DEVINS(pDevIns);
333 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR0);
334 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
335 return idCpu;
336}
337
338
339/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
340static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
341{
342 PDMDEV_ASSERT_DEVINS(pDevIns);
343 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
344 return TMVirtualGet(pDevIns->Internal.s.pVMR0);
345}
346
347
348/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
349static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
350{
351 PDMDEV_ASSERT_DEVINS(pDevIns);
352 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
353 return TMVirtualGetFreq(pDevIns->Internal.s.pVMR0);
354}
355
356
357/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
358static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
359{
360 PDMDEV_ASSERT_DEVINS(pDevIns);
361 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
362 return TMVirtualToNano(pDevIns->Internal.s.pVMR0, TMVirtualGet(pDevIns->Internal.s.pVMR0));
363}
364
365
366/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
367static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
368{
369 PDMDEV_ASSERT_DEVINS(pDevIns);
370 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR0->hTraceBufR0;
371 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
372 return hTraceBuf;
373}
374
375
376/** @interface_method_impl{PDMDEVHLPR0,pfnCanEmulateIoBlock} */
377static DECLCALLBACK(bool) pdmR0DevHlp_CanEmulateIoBlock(PPDMDEVINS pDevIns)
378{
379 PDMDEV_ASSERT_DEVINS(pDevIns);
380 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
381 return HMCanEmulateIoBlock(VMMGetCpu(pDevIns->Internal.s.pVMR0));
382}
383
384
385/**
386 * The Ring-0 Device Helper Callbacks.
387 */
388extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
389{
390 PDM_DEVHLPR0_VERSION,
391 pdmR0DevHlp_PCIPhysRead,
392 pdmR0DevHlp_PCIPhysWrite,
393 pdmR0DevHlp_PCISetIrq,
394 pdmR0DevHlp_ISASetIrq,
395 pdmR0DevHlp_PhysRead,
396 pdmR0DevHlp_PhysWrite,
397 pdmR0DevHlp_A20IsEnabled,
398 pdmR0DevHlp_VMState,
399 pdmR0DevHlp_VMSetError,
400 pdmR0DevHlp_VMSetErrorV,
401 pdmR0DevHlp_VMSetRuntimeError,
402 pdmR0DevHlp_VMSetRuntimeErrorV,
403 pdmR0DevHlp_PATMSetMMIOPatchInfo,
404 pdmR0DevHlp_GetVM,
405 pdmR0DevHlp_CanEmulateIoBlock,
406 pdmR0DevHlp_GetVMCPU,
407 pdmR0DevHlp_GetCurrentCpuId,
408 pdmR0DevHlp_TMTimeVirtGet,
409 pdmR0DevHlp_TMTimeVirtGetFreq,
410 pdmR0DevHlp_TMTimeVirtGetNano,
411 pdmR0DevHlp_DBGFTraceBuf,
412 PDM_DEVHLPR0_VERSION
413};
414
415/** @} */
416
417
418
419
420/** @name PIC Ring-0 Helpers
421 * @{
422 */
423
424/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
425static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
426{
427 PDMDEV_ASSERT_DEVINS(pDevIns);
428 PVM pVM = pDevIns->Internal.s.pVMR0;
429 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
430
431 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
432 {
433 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller='%p'/%d: Setting local interrupt on LAPIC\n",
434 pDevIns, pDevIns->iInstance));
435 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
436 /** @todo rcRZ propagation to pfnLocalInterrupt from caller. */
437 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, pVCpu, 0 /* u8Pin */, 1 /* u8Level */,
438 VINF_SUCCESS /* rcRZ */);
439 return;
440 }
441
442 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 1\n",
443 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
444
445 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
446}
447
448
449/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
450static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
451{
452 PDMDEV_ASSERT_DEVINS(pDevIns);
453 PVM pVM = pDevIns->Internal.s.pVMR0;
454 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
455
456 if (pVM->pdm.s.Apic.pfnLocalInterruptR0)
457 {
458 /* Raise the LAPIC's LINT0 line instead of signaling the CPU directly. */
459 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller='%s'/%d: Clearing local interrupt on LAPIC\n",
460 pDevIns, pDevIns->iInstance));
461 /* Lower the LAPIC's LINT0 line instead of signaling the CPU directly. */
462 /** @todo rcRZ propagation to pfnLocalInterrupt from caller. */
463 pVM->pdm.s.Apic.pfnLocalInterruptR0(pVM->pdm.s.Apic.pDevInsR0, pVCpu, 0 /* u8Pin */, 0 /* u8Level */,
464 VINF_SUCCESS /* rcRZ */);
465 return;
466 }
467
468 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VMCPU_FF_INTERRUPT_PIC %d -> 0\n",
469 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)));
470
471 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
472}
473
474
475/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
476static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
477{
478 PDMDEV_ASSERT_DEVINS(pDevIns);
479 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
480}
481
482
483/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
484static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
485{
486 PDMDEV_ASSERT_DEVINS(pDevIns);
487 pdmUnlock(pDevIns->Internal.s.pVMR0);
488}
489
490
491/**
492 * The Ring-0 PIC Helper Callbacks.
493 */
494extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
495{
496 PDM_PICHLPR0_VERSION,
497 pdmR0PicHlp_SetInterruptFF,
498 pdmR0PicHlp_ClearInterruptFF,
499 pdmR0PicHlp_Lock,
500 pdmR0PicHlp_Unlock,
501 PDM_PICHLPR0_VERSION
502};
503
504/** @} */
505
506
507
508
509/** @name APIC Ring-0 Helpers
510 * @{
511 */
512
513/** @interface_method_impl{PDMAPICHLPR0,pfnSetInterruptFF} */
514static DECLCALLBACK(void) pdmR0ApicHlp_SetInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
515{
516 PDMDEV_ASSERT_DEVINS(pDevIns);
517 PVM pVM = pDevIns->Internal.s.pVMR0;
518 PVMCPU pVCpu = &pVM->aCpus[idCpu];
519
520 AssertReturnVoid(idCpu < pVM->cCpus);
521
522 LogFlow(("pdmR0ApicHlp_SetInterruptFF: CPU%d=caller=%p/%d: VM_FF_INTERRUPT %d -> 1 (CPU%d)\n",
523 VMMGetCpuId(pVM), pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC), idCpu));
524
525 switch (enmType)
526 {
527 case PDMAPICIRQ_UPDATE_PENDING:
528 VMCPU_FF_SET(pVCpu, VMCPU_FF_UPDATE_APIC);
529 break;
530 case PDMAPICIRQ_HARDWARE:
531#ifdef VBOX_WITH_NEW_APIC
532 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
533#endif
534 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
535 break;
536 case PDMAPICIRQ_NMI:
537 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI);
538 break;
539 case PDMAPICIRQ_SMI:
540 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI);
541 break;
542 case PDMAPICIRQ_EXTINT:
543 VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
544 break;
545 default:
546 AssertMsgFailed(("enmType=%d\n", enmType));
547 break;
548 }
549
550 /* We need to wake up the target CPU. */
551 if (
552#ifdef VBOX_WITH_NEW_APIC
553 /* We are already on EMT if enmType is PDMAPICIRQ_HARDWARE. Don't bother with poking! */
554 enmType != PDMAPICIRQ_HARDWARE &&
555#endif
556 VMMGetCpuId(pVM) != idCpu)
557 {
558 switch (VMCPU_GET_STATE(pVCpu))
559 {
560 case VMCPUSTATE_STARTED_EXEC:
561 GVMMR0SchedPokeEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
562 break;
563
564 case VMCPUSTATE_STARTED_HALTED:
565 GVMMR0SchedWakeUpEx(pVM, pVCpu->idCpu, false /* don't take the used lock */);
566 break;
567
568 default:
569 break; /* nothing to do in other states. */
570 }
571 }
572}
573
574
575/** @interface_method_impl{PDMAPICHLPR0,pfnClearInterruptFF} */
576static DECLCALLBACK(void) pdmR0ApicHlp_ClearInterruptFF(PPDMDEVINS pDevIns, PDMAPICIRQ enmType, VMCPUID idCpu)
577{
578 PDMDEV_ASSERT_DEVINS(pDevIns);
579 PVM pVM = pDevIns->Internal.s.pVMR0;
580 PVMCPU pVCpu = &pVM->aCpus[idCpu];
581
582 AssertReturnVoid(idCpu < pVM->cCpus);
583
584 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n",
585 pDevIns, pDevIns->iInstance, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC)));
586
587 /* Note: NMI/SMI can't be cleared. */
588 switch (enmType)
589 {
590 case PDMAPICIRQ_UPDATE_PENDING:
591 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
592 VMCPU_FF_CLEAR(pVCpu, PDMAPICIRQ_UPDATE_PENDING);
593 break;
594 case PDMAPICIRQ_HARDWARE:
595 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
596 break;
597 case PDMAPICIRQ_EXTINT:
598 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
599 break;
600 default:
601 AssertMsgFailed(("enmType=%d\n", enmType));
602 break;
603 }
604}
605
606
607/** @interface_method_impl{PDMAPICHLPR0,pfnBusBroadcastEoi} */
608static DECLCALLBACK(void) pdmR0ApicHlp_BusBroadcastEoi(PPDMDEVINS pDevIns, uint8_t u8Vector)
609{
610 /* pfnSetEoi will be NULL in the old IOAPIC code as it's not implemented. */
611#ifdef VBOX_WITH_NEW_IOAPIC
612 PDMDEV_ASSERT_DEVINS(pDevIns);
613 PVM pVM = pDevIns->Internal.s.CTX_SUFF(pVM);
614
615 /* At present, we support only a maximum of one I/O APIC per-VM. If we ever implement having
616 multiple I/O APICs per-VM, we'll have to broadcast this EOI to all of the I/O APICs. */
617 if (pVM->pdm.s.IoApic.CTX_SUFF(pDevIns))
618 {
619 Assert(pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi));
620 pdmLock(pVM);
621 pVM->pdm.s.IoApic.CTX_SUFF(pfnSetEoi)(pVM->pdm.s.IoApic.CTX_SUFF(pDevIns), u8Vector);
622 pdmUnlock(pVM);
623 }
624#endif
625}
626
627
628/** @interface_method_impl{PDMAPICHLPR0,pfnCalcIrqTag} */
629static DECLCALLBACK(uint32_t) pdmR0ApicHlp_CalcIrqTag(PPDMDEVINS pDevIns, uint8_t u8Level)
630{
631 PDMDEV_ASSERT_DEVINS(pDevIns);
632 PVM pVM = pDevIns->Internal.s.pVMR0;
633
634 pdmLock(pVM);
635
636 uint32_t uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
637 if (u8Level == PDM_IRQ_LEVEL_HIGH)
638 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
639 else
640 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
641
642
643 pdmUnlock(pVM);
644 LogFlow(("pdmR0ApicHlp_CalcIrqTag: caller=%p/%d: returns %#x (u8Level=%d)\n",
645 pDevIns, pDevIns->iInstance, uTagSrc, u8Level));
646 return uTagSrc;
647}
648
649
650/** @interface_method_impl{PDMAPICHLPR0,pfnChangeFeature} */
651static DECLCALLBACK(void) pdmR0ApicHlp_ChangeFeature(PPDMDEVINS pDevIns, PDMAPICMODE enmMode)
652{
653 PDMDEV_ASSERT_DEVINS(pDevIns);
654 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: mode=%d\n", pDevIns, pDevIns->iInstance, (int)enmMode));
655 switch (enmMode)
656 {
657 case PDMAPICMODE_NONE:
658 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
659 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
660 break;
661 case PDMAPICMODE_APIC:
662 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
663 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
664 break;
665 case PDMAPICMODE_X2APIC:
666 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_X2APIC);
667 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC);
668 break;
669 default:
670 AssertMsgFailed(("Unknown APIC mode: %d\n", (int)enmMode));
671 }
672}
673
674
675/** @interface_method_impl{PDMAPICHLPR0,pfnLock} */
676static DECLCALLBACK(int) pdmR0ApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
677{
678 PDMDEV_ASSERT_DEVINS(pDevIns);
679 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
680}
681
682
683/** @interface_method_impl{PDMAPICHLPR0,pfnUnlock} */
684static DECLCALLBACK(void) pdmR0ApicHlp_Unlock(PPDMDEVINS pDevIns)
685{
686 PDMDEV_ASSERT_DEVINS(pDevIns);
687 pdmUnlock(pDevIns->Internal.s.pVMR0);
688}
689
690
691/** @interface_method_impl{PDMAPICHLPR0,pfnGetCpuId} */
692static DECLCALLBACK(VMCPUID) pdmR0ApicHlp_GetCpuId(PPDMDEVINS pDevIns)
693{
694 PDMDEV_ASSERT_DEVINS(pDevIns);
695 return VMMGetCpuId(pDevIns->Internal.s.pVMR0);
696}
697
698
699/**
700 * The Ring-0 APIC Helper Callbacks.
701 */
702extern DECLEXPORT(const PDMAPICHLPR0) g_pdmR0ApicHlp =
703{
704 PDM_APICHLPR0_VERSION,
705 pdmR0ApicHlp_SetInterruptFF,
706 pdmR0ApicHlp_ClearInterruptFF,
707 pdmR0ApicHlp_BusBroadcastEoi,
708 pdmR0ApicHlp_CalcIrqTag,
709 pdmR0ApicHlp_ChangeFeature,
710 pdmR0ApicHlp_Lock,
711 pdmR0ApicHlp_Unlock,
712 pdmR0ApicHlp_GetCpuId,
713 PDM_APICHLPR0_VERSION
714};
715
716/** @} */
717
718
719
720
721/** @name I/O APIC Ring-0 Helpers
722 * @{
723 */
724
725/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
726static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode, uint8_t u8DeliveryMode,
727 uint8_t iVector, uint8_t u8Polarity, uint8_t u8TriggerMode, uint32_t uTagSrc)
728{
729 PDMDEV_ASSERT_DEVINS(pDevIns);
730 PVM pVM = pDevIns->Internal.s.pVMR0;
731 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
732 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode, uTagSrc));
733 Assert(pVM->pdm.s.Apic.pDevInsR0);
734 if (pVM->pdm.s.Apic.pfnBusDeliverR0)
735 return pVM->pdm.s.Apic.pfnBusDeliverR0(pVM->pdm.s.Apic.pDevInsR0, u8Dest, u8DestMode, u8DeliveryMode, iVector,
736 u8Polarity, u8TriggerMode, uTagSrc);
737 return VINF_SUCCESS;
738}
739
740
741/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
742static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
743{
744 PDMDEV_ASSERT_DEVINS(pDevIns);
745 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
746}
747
748
749/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
750static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
751{
752 PDMDEV_ASSERT_DEVINS(pDevIns);
753 pdmUnlock(pDevIns->Internal.s.pVMR0);
754}
755
756
757/**
758 * The Ring-0 I/O APIC Helper Callbacks.
759 */
760extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
761{
762 PDM_IOAPICHLPR0_VERSION,
763 pdmR0IoApicHlp_ApicBusDeliver,
764 pdmR0IoApicHlp_Lock,
765 pdmR0IoApicHlp_Unlock,
766 PDM_IOAPICHLPR0_VERSION
767};
768
769/** @} */
770
771
772
773
774/** @name PCI Bus Ring-0 Helpers
775 * @{
776 */
777
778/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
779static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
780{
781 PDMDEV_ASSERT_DEVINS(pDevIns);
782 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
783 PVM pVM = pDevIns->Internal.s.pVMR0;
784
785 pdmLock(pVM);
786 pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
787 pdmUnlock(pVM);
788}
789
790
791/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
792static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
793{
794 PDMDEV_ASSERT_DEVINS(pDevIns);
795 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
796 PVM pVM = pDevIns->Internal.s.pVMR0;
797
798 if (pVM->pdm.s.IoApic.pDevInsR0)
799 {
800 pdmLock(pVM);
801 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
802 pdmUnlock(pVM);
803 }
804 else if (pVM->pdm.s.IoApic.pDevInsR3)
805 {
806 /* queue for ring-3 execution. */
807 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
808 if (pTask)
809 {
810 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
811 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
812 pTask->u.SetIRQ.iIrq = iIrq;
813 pTask->u.SetIRQ.iLevel = iLevel;
814 pTask->u.SetIRQ.uTagSrc = uTagSrc;
815
816 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
817 }
818 else
819 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
820 }
821}
822
823
824/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
825static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
826{
827 PDMDEV_ASSERT_DEVINS(pDevIns);
828 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
829 PVM pVM = pDevIns->Internal.s.pVMR0;
830 if (pVM->pdm.s.IoApic.pDevInsR0)
831 {
832 pdmLock(pVM);
833 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
834 pdmUnlock(pVM);
835 }
836 else
837 {
838 AssertFatalMsgFailed(("Lazy bastards!"));
839 }
840}
841
842
843/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
844static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
845{
846 PDMDEV_ASSERT_DEVINS(pDevIns);
847 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
848}
849
850
851/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
852static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
853{
854 PDMDEV_ASSERT_DEVINS(pDevIns);
855 pdmUnlock(pDevIns->Internal.s.pVMR0);
856}
857
858
859/**
860 * The Ring-0 PCI Bus Helper Callbacks.
861 */
862extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
863{
864 PDM_PCIHLPR0_VERSION,
865 pdmR0PciHlp_IsaSetIrq,
866 pdmR0PciHlp_IoApicSetIrq,
867 pdmR0PciHlp_IoApicSendMsi,
868 pdmR0PciHlp_Lock,
869 pdmR0PciHlp_Unlock,
870 PDM_PCIHLPR0_VERSION, /* the end */
871};
872
873/** @} */
874
875
876
877
878/** @name HPET Ring-0 Helpers
879 * @{
880 */
881/* none */
882
883/**
884 * The Ring-0 HPET Helper Callbacks.
885 */
886extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
887{
888 PDM_HPETHLPR0_VERSION,
889 PDM_HPETHLPR0_VERSION, /* the end */
890};
891
892/** @} */
893
894
895/** @name Raw PCI Ring-0 Helpers
896 * @{
897 */
898/* none */
899
900/**
901 * The Ring-0 PCI raw Helper Callbacks.
902 */
903extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
904{
905 PDM_PCIRAWHLPR0_VERSION,
906 PDM_PCIRAWHLPR0_VERSION, /* the end */
907};
908
909/** @} */
910
911
912/** @name Ring-0 Context Driver Helpers
913 * @{
914 */
915
916/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
917static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
918{
919 PDMDRV_ASSERT_DRVINS(pDrvIns);
920 va_list args;
921 va_start(args, pszFormat);
922 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
923 va_end(args);
924 return rc;
925}
926
927
928/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
929static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
930{
931 PDMDRV_ASSERT_DRVINS(pDrvIns);
932 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
933 return rc;
934}
935
936
937/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
938static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
939 const char *pszFormat, ...)
940{
941 PDMDRV_ASSERT_DRVINS(pDrvIns);
942 va_list va;
943 va_start(va, pszFormat);
944 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
945 va_end(va);
946 return rc;
947}
948
949
950/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeErrorV} */
951static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
952 const char *pszFormat, va_list va)
953{
954 PDMDRV_ASSERT_DRVINS(pDrvIns);
955 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
956 return rc;
957}
958
959
960/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
961static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
962{
963 PDMDRV_ASSERT_DRVINS(pDrvIns);
964 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
965 return true;
966
967 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
968 RTAssertPanic();
969 return false;
970}
971
972
973/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
974static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
975{
976 PDMDRV_ASSERT_DRVINS(pDrvIns);
977 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
978 return true;
979
980 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
981 RTAssertPanic();
982 return false;
983}
984
985
986/** @interface_method_impl{PDMDRVHLPR0,pfnFTSetCheckpoint} */
987static DECLCALLBACK(int) pdmR0DrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
988{
989 PDMDRV_ASSERT_DRVINS(pDrvIns);
990 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMR0, enmType);
991}
992
993
994/**
995 * The Ring-0 Context Driver Helper Callbacks.
996 */
997extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
998{
999 PDM_DRVHLPRC_VERSION,
1000 pdmR0DrvHlp_VMSetError,
1001 pdmR0DrvHlp_VMSetErrorV,
1002 pdmR0DrvHlp_VMSetRuntimeError,
1003 pdmR0DrvHlp_VMSetRuntimeErrorV,
1004 pdmR0DrvHlp_AssertEMT,
1005 pdmR0DrvHlp_AssertOther,
1006 pdmR0DrvHlp_FTSetCheckpoint,
1007 PDM_DRVHLPRC_VERSION
1008};
1009
1010/** @} */
1011
1012
1013
1014
1015/**
1016 * Sets an irq on the PIC and I/O APIC.
1017 *
1018 * @returns true if delivered, false if postponed.
1019 * @param pVM The cross context VM structure.
1020 * @param iIrq The irq.
1021 * @param iLevel The new level.
1022 * @param uTagSrc The IRQ tag and source.
1023 *
1024 * @remarks The caller holds the PDM lock.
1025 */
1026static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc)
1027{
1028 if (RT_LIKELY( ( pVM->pdm.s.IoApic.pDevInsR0
1029 || !pVM->pdm.s.IoApic.pDevInsR3)
1030 && ( pVM->pdm.s.Pic.pDevInsR0
1031 || !pVM->pdm.s.Pic.pDevInsR3)))
1032 {
1033 if (pVM->pdm.s.Pic.pDevInsR0)
1034 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1035 if (pVM->pdm.s.IoApic.pDevInsR0)
1036 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
1037 return true;
1038 }
1039
1040 /* queue for ring-3 execution. */
1041 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
1042 AssertReturn(pTask, false);
1043
1044 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1045 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1046 pTask->u.SetIRQ.iIrq = iIrq;
1047 pTask->u.SetIRQ.iLevel = iLevel;
1048 pTask->u.SetIRQ.uTagSrc = uTagSrc;
1049
1050 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1051 return false;
1052}
1053
1054
1055/**
1056 * PDMDevHlpCallR0 helper.
1057 *
1058 * @returns See PFNPDMDEVREQHANDLERR0.
1059 * @param pVM The cross context VM structure. (For validation.)
1060 * @param pReq Pointer to the request buffer.
1061 */
1062VMMR0_INT_DECL(int) PDMR0DeviceCallReqHandler(PVM pVM, PPDMDEVICECALLREQHANDLERREQ pReq)
1063{
1064 /*
1065 * Validate input and make the call.
1066 */
1067 AssertPtrReturn(pVM, VERR_INVALID_POINTER);
1068 AssertPtrReturn(pReq, VERR_INVALID_POINTER);
1069 AssertMsgReturn(pReq->Hdr.cbReq == sizeof(*pReq), ("%#x != %#x\n", pReq->Hdr.cbReq, sizeof(*pReq)), VERR_INVALID_PARAMETER);
1070
1071 PPDMDEVINS pDevIns = pReq->pDevInsR0;
1072 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
1073 AssertReturn(pDevIns->Internal.s.pVMR0 == pVM, VERR_INVALID_PARAMETER);
1074
1075 PFNPDMDEVREQHANDLERR0 pfnReqHandlerR0 = pReq->pfnReqHandlerR0;
1076 AssertPtrReturn(pfnReqHandlerR0, VERR_INVALID_POINTER);
1077
1078 return pfnReqHandlerR0(pDevIns, pReq->uOperation, pReq->u64Arg);
1079}
1080
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