VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 78125

Last change on this file since 78125 was 76553, checked in by vboxsync, 6 years ago

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1/* $Id: PDMR0Device.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmm.h>
30#include <VBox/vmm/patm.h>
31#include <VBox/vmm/hm.h>
32#include <VBox/vmm/apic.h>
33
34#include <VBox/log.h>
35#include <VBox/err.h>
36#include <VBox/vmm/gvmm.h>
37#include <iprt/asm.h>
38#include <iprt/assert.h>
39#include <iprt/string.h>
40
41#include "dtrace/VBoxVMM.h"
42#include "PDMInline.h"
43
44
45/*********************************************************************************************************************************
46* Global Variables *
47*********************************************************************************************************************************/
48RT_C_DECLS_BEGIN
49extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
50extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
51extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
52extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
53extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
54extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
55extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
56RT_C_DECLS_END
57
58
59/*********************************************************************************************************************************
60* Internal Functions *
61*********************************************************************************************************************************/
62static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc);
63
64
65
66/** @name Ring-0 Device Helpers
67 * @{
68 */
69
70/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
71static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
72 void *pvBuf, size_t cbRead)
73{
74 PDMDEV_ASSERT_DEVINS(pDevIns);
75 if (!pPciDev) /* NULL is an alias for the default PCI device. */
76 pPciDev = pDevIns->Internal.s.pHeadPciDevR0;
77 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
78
79#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
80 /*
81 * Just check the busmaster setting here and forward the request to the generic read helper.
82 */
83 if (PCIDevIsBusmaster(pPciDev))
84 { /* likely */ }
85 else
86 {
87 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
88 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
89 memset(pvBuf, 0xff, cbRead);
90 return VERR_PDM_NOT_PCI_BUS_MASTER;
91 }
92#endif
93
94 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
95}
96
97
98/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
99static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
100 const void *pvBuf, size_t cbWrite)
101{
102 PDMDEV_ASSERT_DEVINS(pDevIns);
103 if (!pPciDev) /* NULL is an alias for the default PCI device. */
104 pPciDev = pDevIns->Internal.s.pHeadPciDevR0;
105 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
106
107#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
108 /*
109 * Just check the busmaster setting here and forward the request to the generic read helper.
110 */
111 if (PCIDevIsBusmaster(pPciDev))
112 { /* likely */ }
113 else
114 {
115 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
116 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
117 return VERR_PDM_NOT_PCI_BUS_MASTER;
118 }
119#endif
120
121 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
122}
123
124
125/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
126static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
127{
128 PDMDEV_ASSERT_DEVINS(pDevIns);
129 if (!pPciDev) /* NULL is an alias for the default PCI device. */
130 pPciDev = pDevIns->Internal.s.pHeadPciDevR0;
131 AssertReturnVoid(pPciDev);
132 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
133 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
134 PVM pVM = pDevIns->Internal.s.pVMR0;
135 PPDMPCIBUS pPciBus = pPciDev->Int.s.pPdmBusR0;
136
137 pdmLock(pVM);
138 uint32_t uTagSrc;
139 if (iLevel & PDM_IRQ_LEVEL_HIGH)
140 {
141 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
142 if (iLevel == PDM_IRQ_LEVEL_HIGH)
143 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
144 else
145 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
146 }
147 else
148 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
149
150 if ( pPciBus
151 && pPciBus->pDevInsR0)
152 {
153 pPciBus->pfnSetIrqR0(pPciBus->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
154
155 pdmUnlock(pVM);
156
157 if (iLevel == PDM_IRQ_LEVEL_LOW)
158 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
159 }
160 else
161 {
162 pdmUnlock(pVM);
163
164 /* queue for ring-3 execution. */
165 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
166 AssertReturnVoid(pTask);
167
168 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
169 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
170 pTask->u.PciSetIRQ.iIrq = iIrq;
171 pTask->u.PciSetIRQ.iLevel = iLevel;
172 pTask->u.PciSetIRQ.uTagSrc = uTagSrc;
173 pTask->u.PciSetIRQ.pPciDevR3 = MMHyperR0ToR3(pVM, pPciDev);
174
175 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
176 }
177
178 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
179}
180
181
182/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
183static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
184{
185 PDMDEV_ASSERT_DEVINS(pDevIns);
186 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
187 PVM pVM = pDevIns->Internal.s.pVMR0;
188
189 pdmLock(pVM);
190 uint32_t uTagSrc;
191 if (iLevel & PDM_IRQ_LEVEL_HIGH)
192 {
193 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
194 if (iLevel == PDM_IRQ_LEVEL_HIGH)
195 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
196 else
197 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
198 }
199 else
200 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
201
202 bool fRc = pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
203
204 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
205 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
206 pdmUnlock(pVM);
207 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
208}
209
210
211/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSendMsi} */
212static DECLCALLBACK(void) pdmR0DevHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
213{
214 PDMDEV_ASSERT_DEVINS(pDevIns);
215 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: GCPhys=%RGp uValue=%#x\n", pDevIns, pDevIns->iInstance, GCPhys, uValue));
216 PVM pVM = pDevIns->Internal.s.pVMR0;
217
218 uint32_t uTagSrc;
219 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
220 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
221
222 if (pVM->pdm.s.IoApic.pDevInsR0)
223 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
224 else
225 AssertFatalMsgFailed(("Lazy bastards!"));
226
227 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
228}
229
230
231/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
232static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
233{
234 PDMDEV_ASSERT_DEVINS(pDevIns);
235 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
236 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
237
238 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
239 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
240
241 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
242 return VBOXSTRICTRC_VAL(rcStrict);
243}
244
245
246/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
247static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
248{
249 PDMDEV_ASSERT_DEVINS(pDevIns);
250 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
251 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
252
253 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
254 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
255
256 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
257 return VBOXSTRICTRC_VAL(rcStrict);
258}
259
260
261/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
262static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
263{
264 PDMDEV_ASSERT_DEVINS(pDevIns);
265 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
266
267 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR0));
268
269 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
270 return fEnabled;
271}
272
273
274/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
275static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
276{
277 PDMDEV_ASSERT_DEVINS(pDevIns);
278
279 VMSTATE enmVMState = pDevIns->Internal.s.pVMR0->enmVMState;
280
281 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
282 return enmVMState;
283}
284
285
286/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
287static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
288{
289 PDMDEV_ASSERT_DEVINS(pDevIns);
290 va_list args;
291 va_start(args, pszFormat);
292 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
293 va_end(args);
294 return rc;
295}
296
297
298/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
299static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
300{
301 PDMDEV_ASSERT_DEVINS(pDevIns);
302 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
303 return rc;
304}
305
306
307/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
308static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
309{
310 PDMDEV_ASSERT_DEVINS(pDevIns);
311 va_list va;
312 va_start(va, pszFormat);
313 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
314 va_end(va);
315 return rc;
316}
317
318
319/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
320static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
321{
322 PDMDEV_ASSERT_DEVINS(pDevIns);
323 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
324 return rc;
325}
326
327
328/** @interface_method_impl{PDMDEVHLPR0,pfnPATMSetMMIOPatchInfo} */
329static DECLCALLBACK(int) pdmR0DevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData)
330{
331 PDMDEV_ASSERT_DEVINS(pDevIns);
332 LogFlow(("pdmR0DevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
333
334 AssertFailed();
335 NOREF(GCPhys); NOREF(pCachedData); NOREF(pDevIns);
336
337/* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */
338 return VINF_SUCCESS;
339}
340
341
342/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
343static DECLCALLBACK(PVM) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
344{
345 PDMDEV_ASSERT_DEVINS(pDevIns);
346 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
347 return pDevIns->Internal.s.pVMR0;
348}
349
350
351/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
352static DECLCALLBACK(PVMCPU) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
353{
354 PDMDEV_ASSERT_DEVINS(pDevIns);
355 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
356 return VMMGetCpu(pDevIns->Internal.s.pVMR0);
357}
358
359
360/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
361static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
362{
363 PDMDEV_ASSERT_DEVINS(pDevIns);
364 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR0);
365 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
366 return idCpu;
367}
368
369
370/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
371static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
372{
373 PDMDEV_ASSERT_DEVINS(pDevIns);
374 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
375 return TMVirtualGet(pDevIns->Internal.s.pVMR0);
376}
377
378
379/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
380static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
381{
382 PDMDEV_ASSERT_DEVINS(pDevIns);
383 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
384 return TMVirtualGetFreq(pDevIns->Internal.s.pVMR0);
385}
386
387
388/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
389static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
390{
391 PDMDEV_ASSERT_DEVINS(pDevIns);
392 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
393 return TMVirtualToNano(pDevIns->Internal.s.pVMR0, TMVirtualGet(pDevIns->Internal.s.pVMR0));
394}
395
396
397/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
398static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
399{
400 PDMDEV_ASSERT_DEVINS(pDevIns);
401 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR0->hTraceBufR0;
402 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
403 return hTraceBuf;
404}
405
406
407/**
408 * The Ring-0 Device Helper Callbacks.
409 */
410extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
411{
412 PDM_DEVHLPR0_VERSION,
413 pdmR0DevHlp_PCIPhysRead,
414 pdmR0DevHlp_PCIPhysWrite,
415 pdmR0DevHlp_PCISetIrq,
416 pdmR0DevHlp_ISASetIrq,
417 pdmR0DevHlp_IoApicSendMsi,
418 pdmR0DevHlp_PhysRead,
419 pdmR0DevHlp_PhysWrite,
420 pdmR0DevHlp_A20IsEnabled,
421 pdmR0DevHlp_VMState,
422 pdmR0DevHlp_VMSetError,
423 pdmR0DevHlp_VMSetErrorV,
424 pdmR0DevHlp_VMSetRuntimeError,
425 pdmR0DevHlp_VMSetRuntimeErrorV,
426 pdmR0DevHlp_PATMSetMMIOPatchInfo,
427 pdmR0DevHlp_GetVM,
428 pdmR0DevHlp_GetVMCPU,
429 pdmR0DevHlp_GetCurrentCpuId,
430 pdmR0DevHlp_TMTimeVirtGet,
431 pdmR0DevHlp_TMTimeVirtGetFreq,
432 pdmR0DevHlp_TMTimeVirtGetNano,
433 pdmR0DevHlp_DBGFTraceBuf,
434 NULL,
435 NULL,
436 NULL,
437 NULL,
438 NULL,
439 NULL,
440 NULL,
441 NULL,
442 NULL,
443 NULL,
444 PDM_DEVHLPR0_VERSION
445};
446
447/** @} */
448
449
450
451
452/** @name PIC Ring-0 Helpers
453 * @{
454 */
455
456/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
457static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
458{
459 PDMDEV_ASSERT_DEVINS(pDevIns);
460 PVM pVM = pDevIns->Internal.s.pVMR0;
461 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
462 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
463 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
464}
465
466
467/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
468static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
469{
470 PDMDEV_ASSERT_DEVINS(pDevIns);
471 PVM pVM = pDevIns->Internal.s.pVMR0;
472 PVMCPU pVCpu = &pVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
473 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
474 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
475}
476
477
478/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
479static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
480{
481 PDMDEV_ASSERT_DEVINS(pDevIns);
482 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
483}
484
485
486/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
487static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
488{
489 PDMDEV_ASSERT_DEVINS(pDevIns);
490 pdmUnlock(pDevIns->Internal.s.pVMR0);
491}
492
493
494/**
495 * The Ring-0 PIC Helper Callbacks.
496 */
497extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
498{
499 PDM_PICHLPR0_VERSION,
500 pdmR0PicHlp_SetInterruptFF,
501 pdmR0PicHlp_ClearInterruptFF,
502 pdmR0PicHlp_Lock,
503 pdmR0PicHlp_Unlock,
504 PDM_PICHLPR0_VERSION
505};
506
507/** @} */
508
509
510/** @name I/O APIC Ring-0 Helpers
511 * @{
512 */
513
514/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
515static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
516 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
517 uint8_t u8TriggerMode, uint32_t uTagSrc)
518{
519 PDMDEV_ASSERT_DEVINS(pDevIns);
520 PVM pVM = pDevIns->Internal.s.pVMR0;
521 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
522 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
523 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
524}
525
526
527/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
528static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
529{
530 PDMDEV_ASSERT_DEVINS(pDevIns);
531 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
532}
533
534
535/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
536static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
537{
538 PDMDEV_ASSERT_DEVINS(pDevIns);
539 pdmUnlock(pDevIns->Internal.s.pVMR0);
540}
541
542
543/**
544 * The Ring-0 I/O APIC Helper Callbacks.
545 */
546extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
547{
548 PDM_IOAPICHLPR0_VERSION,
549 pdmR0IoApicHlp_ApicBusDeliver,
550 pdmR0IoApicHlp_Lock,
551 pdmR0IoApicHlp_Unlock,
552 PDM_IOAPICHLPR0_VERSION
553};
554
555/** @} */
556
557
558
559
560/** @name PCI Bus Ring-0 Helpers
561 * @{
562 */
563
564/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
565static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
566{
567 PDMDEV_ASSERT_DEVINS(pDevIns);
568 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
569 PVM pVM = pDevIns->Internal.s.pVMR0;
570
571 pdmLock(pVM);
572 pdmR0IsaSetIrq(pVM, iIrq, iLevel, uTagSrc);
573 pdmUnlock(pVM);
574}
575
576
577/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
578static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
579{
580 PDMDEV_ASSERT_DEVINS(pDevIns);
581 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
582 PVM pVM = pDevIns->Internal.s.pVMR0;
583
584 if (pVM->pdm.s.IoApic.pDevInsR0)
585 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
586 else if (pVM->pdm.s.IoApic.pDevInsR3)
587 {
588 /* queue for ring-3 execution. */
589 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
590 if (pTask)
591 {
592 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
593 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
594 pTask->u.IoApicSetIRQ.iIrq = iIrq;
595 pTask->u.IoApicSetIRQ.iLevel = iLevel;
596 pTask->u.IoApicSetIRQ.uTagSrc = uTagSrc;
597
598 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
599 }
600 else
601 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
602 }
603}
604
605
606/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
607static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
608{
609 PDMDEV_ASSERT_DEVINS(pDevIns);
610 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
611 PVM pVM = pDevIns->Internal.s.pVMR0;
612 if (pVM->pdm.s.IoApic.pDevInsR0)
613 pVM->pdm.s.IoApic.pfnSendMsiR0(pVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
614 else
615 AssertFatalMsgFailed(("Lazy bastards!"));
616}
617
618
619/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
620static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
621{
622 PDMDEV_ASSERT_DEVINS(pDevIns);
623 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc);
624}
625
626
627/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
628static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
629{
630 PDMDEV_ASSERT_DEVINS(pDevIns);
631 pdmUnlock(pDevIns->Internal.s.pVMR0);
632}
633
634
635/**
636 * The Ring-0 PCI Bus Helper Callbacks.
637 */
638extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
639{
640 PDM_PCIHLPR0_VERSION,
641 pdmR0PciHlp_IsaSetIrq,
642 pdmR0PciHlp_IoApicSetIrq,
643 pdmR0PciHlp_IoApicSendMsi,
644 pdmR0PciHlp_Lock,
645 pdmR0PciHlp_Unlock,
646 PDM_PCIHLPR0_VERSION, /* the end */
647};
648
649/** @} */
650
651
652
653
654/** @name HPET Ring-0 Helpers
655 * @{
656 */
657/* none */
658
659/**
660 * The Ring-0 HPET Helper Callbacks.
661 */
662extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
663{
664 PDM_HPETHLPR0_VERSION,
665 PDM_HPETHLPR0_VERSION, /* the end */
666};
667
668/** @} */
669
670
671/** @name Raw PCI Ring-0 Helpers
672 * @{
673 */
674/* none */
675
676/**
677 * The Ring-0 PCI raw Helper Callbacks.
678 */
679extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
680{
681 PDM_PCIRAWHLPR0_VERSION,
682 PDM_PCIRAWHLPR0_VERSION, /* the end */
683};
684
685/** @} */
686
687
688/** @name Ring-0 Context Driver Helpers
689 * @{
690 */
691
692/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
693static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
694{
695 PDMDRV_ASSERT_DRVINS(pDrvIns);
696 va_list args;
697 va_start(args, pszFormat);
698 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
699 va_end(args);
700 return rc;
701}
702
703
704/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
705static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
706{
707 PDMDRV_ASSERT_DRVINS(pDrvIns);
708 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
709 return rc;
710}
711
712
713/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
714static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
715 const char *pszFormat, ...)
716{
717 PDMDRV_ASSERT_DRVINS(pDrvIns);
718 va_list va;
719 va_start(va, pszFormat);
720 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
721 va_end(va);
722 return rc;
723}
724
725
726/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeErrorV} */
727static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
728 const char *pszFormat, va_list va)
729{
730 PDMDRV_ASSERT_DRVINS(pDrvIns);
731 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
732 return rc;
733}
734
735
736/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
737static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
738{
739 PDMDRV_ASSERT_DRVINS(pDrvIns);
740 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
741 return true;
742
743 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
744 RTAssertPanic();
745 return false;
746}
747
748
749/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
750static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
751{
752 PDMDRV_ASSERT_DRVINS(pDrvIns);
753 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
754 return true;
755
756 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
757 RTAssertPanic();
758 return false;
759}
760
761
762/** @interface_method_impl{PDMDRVHLPR0,pfnFTSetCheckpoint} */
763static DECLCALLBACK(int) pdmR0DrvHlp_FTSetCheckpoint(PPDMDRVINS pDrvIns, FTMCHECKPOINTTYPE enmType)
764{
765 PDMDRV_ASSERT_DRVINS(pDrvIns);
766 return FTMSetCheckpoint(pDrvIns->Internal.s.pVMR0, enmType);
767}
768
769
770/**
771 * The Ring-0 Context Driver Helper Callbacks.
772 */
773extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
774{
775 PDM_DRVHLPRC_VERSION,
776 pdmR0DrvHlp_VMSetError,
777 pdmR0DrvHlp_VMSetErrorV,
778 pdmR0DrvHlp_VMSetRuntimeError,
779 pdmR0DrvHlp_VMSetRuntimeErrorV,
780 pdmR0DrvHlp_AssertEMT,
781 pdmR0DrvHlp_AssertOther,
782 pdmR0DrvHlp_FTSetCheckpoint,
783 PDM_DRVHLPRC_VERSION
784};
785
786/** @} */
787
788
789
790
791/**
792 * Sets an irq on the PIC and I/O APIC.
793 *
794 * @returns true if delivered, false if postponed.
795 * @param pVM The cross context VM structure.
796 * @param iIrq The irq.
797 * @param iLevel The new level.
798 * @param uTagSrc The IRQ tag and source.
799 *
800 * @remarks The caller holds the PDM lock.
801 */
802static bool pdmR0IsaSetIrq(PVM pVM, int iIrq, int iLevel, uint32_t uTagSrc)
803{
804 if (RT_LIKELY( ( pVM->pdm.s.IoApic.pDevInsR0
805 || !pVM->pdm.s.IoApic.pDevInsR3)
806 && ( pVM->pdm.s.Pic.pDevInsR0
807 || !pVM->pdm.s.Pic.pDevInsR3)))
808 {
809 if (pVM->pdm.s.Pic.pDevInsR0)
810 pVM->pdm.s.Pic.pfnSetIrqR0(pVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
811 if (pVM->pdm.s.IoApic.pDevInsR0)
812 pVM->pdm.s.IoApic.pfnSetIrqR0(pVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
813 return true;
814 }
815
816 /* queue for ring-3 execution. */
817 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pVM->pdm.s.pDevHlpQueueR0);
818 AssertReturn(pTask, false);
819
820 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
821 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
822 pTask->u.IsaSetIRQ.iIrq = iIrq;
823 pTask->u.IsaSetIRQ.iLevel = iLevel;
824 pTask->u.IsaSetIRQ.uTagSrc = uTagSrc;
825
826 PDMQueueInsertEx(pVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
827 return false;
828}
829
830
831/**
832 * PDMDevHlpCallR0 helper.
833 *
834 * @returns See PFNPDMDEVREQHANDLERR0.
835 * @param pGVM The global (ring-0) VM structure. (For validation.)
836 * @param pVM The cross context VM structure. (For validation.)
837 * @param pReq Pointer to the request buffer.
838 */
839VMMR0_INT_DECL(int) PDMR0DeviceCallReqHandler(PGVM pGVM, PVM pVM, PPDMDEVICECALLREQHANDLERREQ pReq)
840{
841 /*
842 * Validate input and make the call.
843 */
844 int rc = GVMMR0ValidateGVMandVM(pGVM, pVM);
845 if (RT_SUCCESS(rc))
846 {
847 AssertPtrReturn(pReq, VERR_INVALID_POINTER);
848 AssertMsgReturn(pReq->Hdr.cbReq == sizeof(*pReq), ("%#x != %#x\n", pReq->Hdr.cbReq, sizeof(*pReq)), VERR_INVALID_PARAMETER);
849
850 PPDMDEVINS pDevIns = pReq->pDevInsR0;
851 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
852 AssertReturn(pDevIns->Internal.s.pVMR0 == pVM, VERR_INVALID_PARAMETER);
853
854 PFNPDMDEVREQHANDLERR0 pfnReqHandlerR0 = pReq->pfnReqHandlerR0;
855 AssertPtrReturn(pfnReqHandlerR0, VERR_INVALID_POINTER);
856
857 rc = pfnReqHandlerR0(pDevIns, pReq->uOperation, pReq->u64Arg);
858 }
859 return rc;
860}
861
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