VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 81850

Last change on this file since 81850 was 81850, checked in by vboxsync, 5 years ago

PDMDevHlp: Adding PDMDevHlpCritSectScheduleExitEvent. bugref:9218
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1/* $Id: PDMR0Device.cpp 81850 2019-11-14 21:36:00Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/hm.h>
32#include <VBox/vmm/vmcc.h>
33#include <VBox/vmm/gvmm.h>
34
35#include <VBox/log.h>
36#include <VBox/err.h>
37#include <VBox/msi.h>
38#include <VBox/sup.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/ctype.h>
42#include <iprt/mem.h>
43#include <iprt/memobj.h>
44#include <iprt/process.h>
45#include <iprt/string.h>
46
47#include "dtrace/VBoxVMM.h"
48#include "PDMInline.h"
49
50
51/*********************************************************************************************************************************
52* Global Variables *
53*********************************************************************************************************************************/
54RT_C_DECLS_BEGIN
55extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
56extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp;
57extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
58extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
59extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
60extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
61extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
62RT_C_DECLS_END
63
64/** List of PDMDEVMODREGR0 structures protected by the loader lock. */
65static RTLISTANCHOR g_PDMDevModList;
66
67
68/**
69 * Pointer to the ring-0 device registrations for VMMR0.
70 */
71static const PDMDEVREGR0 *g_apVMM0DevRegs[] =
72{
73 &g_DeviceAPIC,
74};
75
76/**
77 * Module device registration record for VMMR0.
78 */
79static PDMDEVMODREGR0 g_VBoxDDR0ModDevReg =
80{
81 /* .u32Version = */ PDM_DEVMODREGR0_VERSION,
82 /* .cDevRegs = */ RT_ELEMENTS(g_apVMM0DevRegs),
83 /* .papDevRegs = */ &g_apVMM0DevRegs[0],
84 /* .hMod = */ NULL,
85 /* .ListEntry = */ { NULL, NULL },
86};
87
88
89/*********************************************************************************************************************************
90* Internal Functions *
91*********************************************************************************************************************************/
92static bool pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
93
94
95/**
96 * Initializes the global ring-0 PDM data.
97 */
98VMMR0_INT_DECL(void) PDMR0Init(void *hMod)
99{
100 RTListInit(&g_PDMDevModList);
101 g_VBoxDDR0ModDevReg.hMod = hMod;
102 RTListAppend(&g_PDMDevModList, &g_VBoxDDR0ModDevReg.ListEntry);
103}
104
105
106/**
107 * Used by PDMR0CleanupVM to destroy a device instance.
108 *
109 * This is done during VM cleanup so that we're sure there are no active threads
110 * inside the device code.
111 *
112 * @param pGVM The global (ring-0) VM structure.
113 * @param pDevIns The device instance.
114 * @param idxR0Device The device instance handle.
115 */
116static int pdmR0DeviceDestroy(PGVM pGVM, PPDMDEVINSR0 pDevIns, uint32_t idxR0Device)
117{
118 /*
119 * Assert sanity.
120 */
121 Assert(idxR0Device < pGVM->pdmr0.s.cDevInstances);
122 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
123 Assert(pDevIns->u32Version == PDM_DEVINSR0_VERSION);
124 Assert(pDevIns->Internal.s.idxR0Device == idxR0Device);
125
126 /*
127 * Call the final destructor if there is one.
128 */
129 if (pDevIns->pReg->pfnFinalDestruct)
130 pDevIns->pReg->pfnFinalDestruct(pDevIns);
131 pDevIns->u32Version = ~PDM_DEVINSR0_VERSION;
132
133 /*
134 * Remove the device from the instance table.
135 */
136 Assert(pGVM->pdmr0.s.apDevInstances[idxR0Device] == pDevIns);
137 pGVM->pdmr0.s.apDevInstances[idxR0Device] = NULL;
138 if (idxR0Device + 1 == pGVM->pdmr0.s.cDevInstances)
139 pGVM->pdmr0.s.cDevInstances = idxR0Device;
140
141 /*
142 * Free the ring-3 mapping and instance memory.
143 */
144 RTR0MEMOBJ hMemObj = pDevIns->Internal.s.hMapObj;
145 pDevIns->Internal.s.hMapObj = NIL_RTR0MEMOBJ;
146 RTR0MemObjFree(hMemObj, true);
147
148 hMemObj = pDevIns->Internal.s.hMemObj;
149 pDevIns->Internal.s.hMemObj = NIL_RTR0MEMOBJ;
150 RTR0MemObjFree(hMemObj, true);
151
152 return VINF_SUCCESS;
153}
154
155
156/**
157 * Initializes the per-VM data for the PDM.
158 *
159 * This is called from under the GVMM lock, so it only need to initialize the
160 * data so PDMR0CleanupVM and others will work smoothly.
161 *
162 * @param pGVM Pointer to the global VM structure.
163 */
164VMMR0_INT_DECL(void) PDMR0InitPerVMData(PGVM pGVM)
165{
166 AssertCompile(sizeof(pGVM->pdm.s) <= sizeof(pGVM->pdm.padding));
167 AssertCompile(sizeof(pGVM->pdmr0.s) <= sizeof(pGVM->pdmr0.padding));
168
169 pGVM->pdmr0.s.cDevInstances = 0;
170}
171
172
173/**
174 * Cleans up any loose ends before the GVM structure is destroyed.
175 */
176VMMR0_INT_DECL(void) PDMR0CleanupVM(PGVM pGVM)
177{
178 uint32_t i = pGVM->pdmr0.s.cDevInstances;
179 while (i-- > 0)
180 {
181 PPDMDEVINSR0 pDevIns = pGVM->pdmr0.s.apDevInstances[i];
182 if (pDevIns)
183 pdmR0DeviceDestroy(pGVM, pDevIns, i);
184 }
185}
186
187
188/** @name Ring-0 Device Helpers
189 * @{
190 */
191
192/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
193static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
194 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
195 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
196 void *pvUser)
197{
198 PDMDEV_ASSERT_DEVINS(pDevIns);
199 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
200 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
201 PGVM pGVM = pDevIns->Internal.s.pGVM;
202 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
203 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
204
205 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
206
207 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
208 return rc;
209}
210
211
212/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
213static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
214 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
215{
216 PDMDEV_ASSERT_DEVINS(pDevIns);
217 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
218 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
219 PGVM pGVM = pDevIns->Internal.s.pGVM;
220 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
221 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
222
223 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
224
225 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
226 return rc;
227}
228
229
230/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
231static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
232 size_t offSub, size_t cbSub, void **ppvMapping)
233{
234 PDMDEV_ASSERT_DEVINS(pDevIns);
235 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
236 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
237 *ppvMapping = NULL;
238
239 PGVM pGVM = pDevIns->Internal.s.pGVM;
240 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
241 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
242
243 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
244
245 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
246 return rc;
247}
248
249
250/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
251static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
252 void *pvBuf, size_t cbRead)
253{
254 PDMDEV_ASSERT_DEVINS(pDevIns);
255 if (!pPciDev) /* NULL is an alias for the default PCI device. */
256 pPciDev = pDevIns->apPciDevs[0];
257 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
258 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
259
260#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
261 /*
262 * Just check the busmaster setting here and forward the request to the generic read helper.
263 */
264 if (PCIDevIsBusmaster(pPciDev))
265 { /* likely */ }
266 else
267 {
268 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
269 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
270 memset(pvBuf, 0xff, cbRead);
271 return VERR_PDM_NOT_PCI_BUS_MASTER;
272 }
273#endif
274
275 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
276}
277
278
279/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
280static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
281 const void *pvBuf, size_t cbWrite)
282{
283 PDMDEV_ASSERT_DEVINS(pDevIns);
284 if (!pPciDev) /* NULL is an alias for the default PCI device. */
285 pPciDev = pDevIns->apPciDevs[0];
286 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
287 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
288
289#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
290 /*
291 * Just check the busmaster setting here and forward the request to the generic read helper.
292 */
293 if (PCIDevIsBusmaster(pPciDev))
294 { /* likely */ }
295 else
296 {
297 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
298 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
299 return VERR_PDM_NOT_PCI_BUS_MASTER;
300 }
301#endif
302
303 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
304}
305
306
307/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
308static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
309{
310 PDMDEV_ASSERT_DEVINS(pDevIns);
311 if (!pPciDev) /* NULL is an alias for the default PCI device. */
312 pPciDev = pDevIns->apPciDevs[0];
313 AssertReturnVoid(pPciDev);
314 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
315 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
316 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
317
318 PGVM pGVM = pDevIns->Internal.s.pGVM;
319 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
320 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
321 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
322
323 pdmLock(pGVM);
324
325 uint32_t uTagSrc;
326 if (iLevel & PDM_IRQ_LEVEL_HIGH)
327 {
328 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
329 if (iLevel == PDM_IRQ_LEVEL_HIGH)
330 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
331 else
332 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
333 }
334 else
335 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
336
337 if (pPciBusR0->pDevInsR0)
338 {
339 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
340
341 pdmUnlock(pGVM);
342
343 if (iLevel == PDM_IRQ_LEVEL_LOW)
344 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
345 }
346 else
347 {
348 pdmUnlock(pGVM);
349
350 /* queue for ring-3 execution. */
351 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
352 AssertReturnVoid(pTask);
353
354 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
355 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
356 pTask->u.PciSetIRQ.iIrq = iIrq;
357 pTask->u.PciSetIRQ.iLevel = iLevel;
358 pTask->u.PciSetIRQ.uTagSrc = uTagSrc;
359 pTask->u.PciSetIRQ.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
360
361 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
362 }
363
364 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
365}
366
367
368/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
369static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
370{
371 PDMDEV_ASSERT_DEVINS(pDevIns);
372 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
373 PGVM pGVM = pDevIns->Internal.s.pGVM;
374
375 pdmLock(pGVM);
376 uint32_t uTagSrc;
377 if (iLevel & PDM_IRQ_LEVEL_HIGH)
378 {
379 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
380 if (iLevel == PDM_IRQ_LEVEL_HIGH)
381 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
382 else
383 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
384 }
385 else
386 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
387
388 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
389
390 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
391 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
392 pdmUnlock(pGVM);
393 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
394}
395
396
397/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSendMsi} */
398static DECLCALLBACK(void) pdmR0DevHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
399{
400 PDMDEV_ASSERT_DEVINS(pDevIns);
401 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: GCPhys=%RGp uValue=%#x\n", pDevIns, pDevIns->iInstance, GCPhys, uValue));
402 PGVM pGVM = pDevIns->Internal.s.pGVM;
403
404 uint32_t uTagSrc;
405 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
406 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
407
408 if (pGVM->pdm.s.IoApic.pDevInsR0)
409 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
410 else
411 AssertFatalMsgFailed(("Lazy bastards!"));
412
413 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
414}
415
416
417/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
418static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
419{
420 PDMDEV_ASSERT_DEVINS(pDevIns);
421 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
422 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
423
424 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
425 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
426
427 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
428 return VBOXSTRICTRC_VAL(rcStrict);
429}
430
431
432/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
433static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
434{
435 PDMDEV_ASSERT_DEVINS(pDevIns);
436 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
437 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
438
439 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
440 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
441
442 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
443 return VBOXSTRICTRC_VAL(rcStrict);
444}
445
446
447/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
448static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
449{
450 PDMDEV_ASSERT_DEVINS(pDevIns);
451 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
452
453 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
454
455 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
456 return fEnabled;
457}
458
459
460/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
461static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
462{
463 PDMDEV_ASSERT_DEVINS(pDevIns);
464
465 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
466
467 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
468 return enmVMState;
469}
470
471
472/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
473static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
474{
475 PDMDEV_ASSERT_DEVINS(pDevIns);
476 va_list args;
477 va_start(args, pszFormat);
478 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
479 va_end(args);
480 return rc;
481}
482
483
484/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
485static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
486{
487 PDMDEV_ASSERT_DEVINS(pDevIns);
488 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
489 return rc;
490}
491
492
493/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
494static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
495{
496 PDMDEV_ASSERT_DEVINS(pDevIns);
497 va_list va;
498 va_start(va, pszFormat);
499 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
500 va_end(va);
501 return rc;
502}
503
504
505/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
506static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
507{
508 PDMDEV_ASSERT_DEVINS(pDevIns);
509 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
510 return rc;
511}
512
513
514
515/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
516static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
517{
518 PDMDEV_ASSERT_DEVINS(pDevIns);
519 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
520 return pDevIns->Internal.s.pGVM;
521}
522
523
524/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
525static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
526{
527 PDMDEV_ASSERT_DEVINS(pDevIns);
528 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
529 return VMMGetCpu(pDevIns->Internal.s.pGVM);
530}
531
532
533/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
534static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
535{
536 PDMDEV_ASSERT_DEVINS(pDevIns);
537 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
538 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
539 return idCpu;
540}
541
542
543/** @interface_method_impl{PDMDEVHLPR0,pfnTimerToPtr} */
544static DECLCALLBACK(PTMTIMERR0) pdmR0DevHlp_TimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
545{
546 PDMDEV_ASSERT_DEVINS(pDevIns);
547 RT_NOREF(pDevIns);
548 return (PTMTIMERR0)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hTimer);
549}
550
551
552/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
553static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
554{
555 return TMTimerFromMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicroSecs);
556}
557
558
559/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
560static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
561{
562 return TMTimerFromMilli(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliSecs);
563}
564
565
566/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
567static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
568{
569 return TMTimerFromNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanoSecs);
570}
571
572/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
573static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
574{
575 return TMTimerGet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
576}
577
578
579/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
580static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
581{
582 return TMTimerGetFreq(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
583}
584
585
586/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
587static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
588{
589 return TMTimerGetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
590}
591
592
593/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
594static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
595{
596 return TMTimerIsActive(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
597}
598
599
600/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
601static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
602{
603 return TMTimerIsLockOwner(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
604}
605
606
607/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLock} */
608static DECLCALLBACK(int) pdmR0DevHlp_TimerLock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
609{
610 return TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
611}
612
613
614/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
615static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
616{
617 return TMTimerSet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uExpire);
618}
619
620
621/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
622static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
623{
624 return TMTimerSetFrequencyHint(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uHz);
625}
626
627
628/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
629static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
630{
631 return TMTimerSetMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicrosToNext);
632}
633
634
635/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
636static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
637{
638 return TMTimerSetMillies(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliesToNext);
639}
640
641
642/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
643static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
644{
645 return TMTimerSetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanosToNext);
646}
647
648
649/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
650static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
651{
652 return TMTimerSetRelative(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cTicksToNext, pu64Now);
653}
654
655
656/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
657static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
658{
659 return TMTimerStop(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
660}
661
662
663/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlock} */
664static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
665{
666 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
667}
668
669
670/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
671static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
672{
673 PDMDEV_ASSERT_DEVINS(pDevIns);
674 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
675 return TMVirtualGet(pDevIns->Internal.s.pGVM);
676}
677
678
679/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
680static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
681{
682 PDMDEV_ASSERT_DEVINS(pDevIns);
683 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
684 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
685}
686
687
688/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
689static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
690{
691 PDMDEV_ASSERT_DEVINS(pDevIns);
692 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
693 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
694}
695
696
697/** @interface_method_impl{PDMDEVHLPR0,pfnQueueToPtr} */
698static DECLCALLBACK(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
699{
700 PDMDEV_ASSERT_DEVINS(pDevIns);
701 RT_NOREF(pDevIns);
702 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
703}
704
705
706/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
707static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
708{
709 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
710}
711
712
713/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
714static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
715{
716 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
717}
718
719
720/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsertEx} */
721static DECLCALLBACK(void) pdmR0DevHlp_QueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem,
722 uint64_t cNanoMaxDelay)
723{
724 return PDMQueueInsertEx(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem, cNanoMaxDelay);
725}
726
727
728/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
729static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
730{
731 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
732}
733
734
735/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
736static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
737{
738 PDMDEV_ASSERT_DEVINS(pDevIns);
739 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
740
741 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
742
743 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
744 return rc;
745}
746
747
748/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
749static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
750{
751 PDMDEV_ASSERT_DEVINS(pDevIns);
752 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
753
754 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
755
756 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
757 return rc;
758}
759
760
761/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
762static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
763{
764 PDMDEV_ASSERT_DEVINS(pDevIns);
765 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
766 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
767
768 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
769
770 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
771 return rc;
772}
773
774
775/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
776static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
777{
778 PDMDEV_ASSERT_DEVINS(pDevIns);
779 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
780 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
781
782 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
783
784 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
785 return rc;
786}
787
788
789/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
790static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
791{
792 PDMDEV_ASSERT_DEVINS(pDevIns);
793 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
794 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
795
796 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
797
798 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
799 return rc;
800}
801
802
803/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
804static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
805{
806 PDMDEV_ASSERT_DEVINS(pDevIns);
807 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
808
809 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
810
811 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
812 return cNsResolution;
813}
814
815
816/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
817static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
818{
819 PDMDEV_ASSERT_DEVINS(pDevIns);
820 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
821
822 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
823
824 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
825 return rc;
826}
827
828
829/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
830static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
831{
832 PDMDEV_ASSERT_DEVINS(pDevIns);
833 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
834
835 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
836
837 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
838 return rc;
839}
840
841
842/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
843static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
844 uint32_t cMillies)
845{
846 PDMDEV_ASSERT_DEVINS(pDevIns);
847 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
848 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
849
850 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
851
852 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
853 return rc;
854}
855
856
857/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
858static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
859 uint64_t uNsTimeout)
860{
861 PDMDEV_ASSERT_DEVINS(pDevIns);
862 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
863 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
864
865 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
866
867 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
868 return rc;
869}
870
871
872/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
873static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
874 uint64_t cNsTimeout)
875{
876 PDMDEV_ASSERT_DEVINS(pDevIns);
877 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
878 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
879
880 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
881
882 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
883 return rc;
884}
885
886
887/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
888static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
889{
890 PDMDEV_ASSERT_DEVINS(pDevIns);
891 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
892
893 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
894
895 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
896 return cNsResolution;
897}
898
899
900/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
901static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
902{
903 PDMDEV_ASSERT_DEVINS(pDevIns);
904 PGVM pGVM = pDevIns->Internal.s.pGVM;
905
906 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
907 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
908 return pCritSect;
909}
910
911
912/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
913static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
914{
915 /*
916 * Validate input.
917 *
918 * Note! We only allow the automatically created default critical section
919 * to be replaced by this API.
920 */
921 PDMDEV_ASSERT_DEVINS(pDevIns);
922 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
923 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
924 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
925 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
926 PGVM pGVM = pDevIns->Internal.s.pGVM;
927 AssertReturn(pCritSect->s.pVMR0 == pGVM, VERR_INVALID_PARAMETER);
928
929 VM_ASSERT_EMT(pGVM);
930 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
931
932 /*
933 * Check that ring-3 has already done this, then effect the change.
934 */
935 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
936 pDevIns->pCritSectRoR0 = pCritSect;
937
938 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
939 return VINF_SUCCESS;
940}
941
942
943/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
944static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
945{
946 PDMDEV_ASSERT_DEVINS(pDevIns);
947 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
948 return PDMCritSectEnter(pCritSect, rcBusy);
949}
950
951
952/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
953static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
954{
955 PDMDEV_ASSERT_DEVINS(pDevIns);
956 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
957 return PDMCritSectEnterDebug(pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
958}
959
960
961/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
962static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
963{
964 PDMDEV_ASSERT_DEVINS(pDevIns);
965 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
966 return PDMCritSectTryEnter(pCritSect);
967}
968
969
970/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
971static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
972{
973 PDMDEV_ASSERT_DEVINS(pDevIns);
974 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
975 return PDMCritSectTryEnterDebug(pCritSect, uId, RT_SRC_POS_ARGS);
976}
977
978
979/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
980static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
981{
982 PDMDEV_ASSERT_DEVINS(pDevIns);
983 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
984 return PDMCritSectLeave(pCritSect);
985}
986
987
988/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
989static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
990{
991 PDMDEV_ASSERT_DEVINS(pDevIns);
992 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
993 return PDMCritSectIsOwner(pCritSect);
994}
995
996
997/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
998static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
999{
1000 PDMDEV_ASSERT_DEVINS(pDevIns);
1001 RT_NOREF(pDevIns);
1002 return PDMCritSectIsInitialized(pCritSect);
1003}
1004
1005
1006/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
1007static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
1008{
1009 PDMDEV_ASSERT_DEVINS(pDevIns);
1010 RT_NOREF(pDevIns);
1011 return PDMCritSectHasWaiters(pCritSect);
1012}
1013
1014
1015/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
1016static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
1017{
1018 PDMDEV_ASSERT_DEVINS(pDevIns);
1019 RT_NOREF(pDevIns);
1020 return PDMCritSectGetRecursion(pCritSect);
1021}
1022
1023
1024/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
1025static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
1026 SUPSEMEVENT hEventToSignal)
1027{
1028 PDMDEV_ASSERT_DEVINS(pDevIns);
1029 RT_NOREF(pDevIns);
1030 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
1031}
1032
1033
1034/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
1035static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1036{
1037 PDMDEV_ASSERT_DEVINS(pDevIns);
1038 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
1039 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
1040 return hTraceBuf;
1041}
1042
1043
1044/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
1045static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
1046{
1047 PDMDEV_ASSERT_DEVINS(pDevIns);
1048 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
1049 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
1050 pPciBusReg->u32EndVersion, ppPciHlp));
1051 PGVM pGVM = pDevIns->Internal.s.pGVM;
1052
1053 /*
1054 * Validate input.
1055 */
1056 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
1057 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
1058 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1059 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
1060 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
1061 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1062
1063 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
1064
1065 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1066 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1067
1068 /* Check the shared bus data (registered earlier from ring-3): */
1069 uint32_t iBus = pPciBusReg->iBus;
1070 ASMCompilerBarrier();
1071 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
1072 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
1073 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
1074 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
1075 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
1076
1077 /* Check that the bus isn't already registered in ring-0: */
1078 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
1079 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
1080 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
1081 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1082 VERR_ALREADY_EXISTS);
1083
1084 /*
1085 * Do the registering.
1086 */
1087 pPciBusR0->iBus = iBus;
1088 pPciBusR0->uPadding0 = 0xbeefbeef;
1089 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1090 pPciBusR0->pDevInsR0 = pDevIns;
1091
1092 *ppPciHlp = &g_pdmR0PciHlp;
1093
1094 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1095 return VINF_SUCCESS;
1096}
1097
1098
1099/**
1100 * The Ring-0 Device Helper Callbacks.
1101 */
1102extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1103{
1104 PDM_DEVHLPR0_VERSION,
1105 pdmR0DevHlp_IoPortSetUpContextEx,
1106 pdmR0DevHlp_MmioSetUpContextEx,
1107 pdmR0DevHlp_Mmio2SetUpContext,
1108 pdmR0DevHlp_PCIPhysRead,
1109 pdmR0DevHlp_PCIPhysWrite,
1110 pdmR0DevHlp_PCISetIrq,
1111 pdmR0DevHlp_ISASetIrq,
1112 pdmR0DevHlp_IoApicSendMsi,
1113 pdmR0DevHlp_PhysRead,
1114 pdmR0DevHlp_PhysWrite,
1115 pdmR0DevHlp_A20IsEnabled,
1116 pdmR0DevHlp_VMState,
1117 pdmR0DevHlp_VMSetError,
1118 pdmR0DevHlp_VMSetErrorV,
1119 pdmR0DevHlp_VMSetRuntimeError,
1120 pdmR0DevHlp_VMSetRuntimeErrorV,
1121 pdmR0DevHlp_GetVM,
1122 pdmR0DevHlp_GetVMCPU,
1123 pdmR0DevHlp_GetCurrentCpuId,
1124 pdmR0DevHlp_TimerToPtr,
1125 pdmR0DevHlp_TimerFromMicro,
1126 pdmR0DevHlp_TimerFromMilli,
1127 pdmR0DevHlp_TimerFromNano,
1128 pdmR0DevHlp_TimerGet,
1129 pdmR0DevHlp_TimerGetFreq,
1130 pdmR0DevHlp_TimerGetNano,
1131 pdmR0DevHlp_TimerIsActive,
1132 pdmR0DevHlp_TimerIsLockOwner,
1133 pdmR0DevHlp_TimerLock,
1134 pdmR0DevHlp_TimerSet,
1135 pdmR0DevHlp_TimerSetFrequencyHint,
1136 pdmR0DevHlp_TimerSetMicro,
1137 pdmR0DevHlp_TimerSetMillies,
1138 pdmR0DevHlp_TimerSetNano,
1139 pdmR0DevHlp_TimerSetRelative,
1140 pdmR0DevHlp_TimerStop,
1141 pdmR0DevHlp_TimerUnlock,
1142 pdmR0DevHlp_TMTimeVirtGet,
1143 pdmR0DevHlp_TMTimeVirtGetFreq,
1144 pdmR0DevHlp_TMTimeVirtGetNano,
1145 pdmR0DevHlp_QueueToPtr,
1146 pdmR0DevHlp_QueueAlloc,
1147 pdmR0DevHlp_QueueInsert,
1148 pdmR0DevHlp_QueueInsertEx,
1149 pdmR0DevHlp_QueueFlushIfNecessary,
1150 pdmR0DevHlp_TaskTrigger,
1151 pdmR0DevHlp_SUPSemEventSignal,
1152 pdmR0DevHlp_SUPSemEventWaitNoResume,
1153 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1154 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1155 pdmR0DevHlp_SUPSemEventGetResolution,
1156 pdmR0DevHlp_SUPSemEventMultiSignal,
1157 pdmR0DevHlp_SUPSemEventMultiReset,
1158 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1159 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1160 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1161 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1162 pdmR0DevHlp_CritSectGetNop,
1163 pdmR0DevHlp_SetDeviceCritSect,
1164 pdmR0DevHlp_CritSectEnter,
1165 pdmR0DevHlp_CritSectEnterDebug,
1166 pdmR0DevHlp_CritSectTryEnter,
1167 pdmR0DevHlp_CritSectTryEnterDebug,
1168 pdmR0DevHlp_CritSectLeave,
1169 pdmR0DevHlp_CritSectIsOwner,
1170 pdmR0DevHlp_CritSectIsInitialized,
1171 pdmR0DevHlp_CritSectHasWaiters,
1172 pdmR0DevHlp_CritSectGetRecursion,
1173 pdmR0DevHlp_CritSectScheduleExitEvent,
1174 pdmR0DevHlp_DBGFTraceBuf,
1175 pdmR0DevHlp_PCIBusSetUpContext,
1176 NULL /*pfnReserved1*/,
1177 NULL /*pfnReserved2*/,
1178 NULL /*pfnReserved3*/,
1179 NULL /*pfnReserved4*/,
1180 NULL /*pfnReserved5*/,
1181 NULL /*pfnReserved6*/,
1182 NULL /*pfnReserved7*/,
1183 NULL /*pfnReserved8*/,
1184 NULL /*pfnReserved9*/,
1185 NULL /*pfnReserved10*/,
1186 PDM_DEVHLPR0_VERSION
1187};
1188
1189/** @} */
1190
1191
1192
1193
1194/** @name PIC Ring-0 Helpers
1195 * @{
1196 */
1197
1198/** @interface_method_impl{PDMPICHLPR0,pfnSetInterruptFF} */
1199static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1200{
1201 PDMDEV_ASSERT_DEVINS(pDevIns);
1202 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1203 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1204 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1205 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1206}
1207
1208
1209/** @interface_method_impl{PDMPICHLPR0,pfnClearInterruptFF} */
1210static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1211{
1212 PDMDEV_ASSERT_DEVINS(pDevIns);
1213 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1214 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1215 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1216 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1217}
1218
1219
1220/** @interface_method_impl{PDMPICHLPR0,pfnLock} */
1221static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1222{
1223 PDMDEV_ASSERT_DEVINS(pDevIns);
1224 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1225}
1226
1227
1228/** @interface_method_impl{PDMPICHLPR0,pfnUnlock} */
1229static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1230{
1231 PDMDEV_ASSERT_DEVINS(pDevIns);
1232 pdmUnlock(pDevIns->Internal.s.pGVM);
1233}
1234
1235
1236/**
1237 * The Ring-0 PIC Helper Callbacks.
1238 */
1239extern DECLEXPORT(const PDMPICHLPR0) g_pdmR0PicHlp =
1240{
1241 PDM_PICHLPR0_VERSION,
1242 pdmR0PicHlp_SetInterruptFF,
1243 pdmR0PicHlp_ClearInterruptFF,
1244 pdmR0PicHlp_Lock,
1245 pdmR0PicHlp_Unlock,
1246 PDM_PICHLPR0_VERSION
1247};
1248
1249/** @} */
1250
1251
1252/** @name I/O APIC Ring-0 Helpers
1253 * @{
1254 */
1255
1256/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
1257static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1258 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1259 uint8_t u8TriggerMode, uint32_t uTagSrc)
1260{
1261 PDMDEV_ASSERT_DEVINS(pDevIns);
1262 PGVM pGVM = pDevIns->Internal.s.pGVM;
1263 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1264 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1265 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1266}
1267
1268
1269/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
1270static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1271{
1272 PDMDEV_ASSERT_DEVINS(pDevIns);
1273 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1274}
1275
1276
1277/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
1278static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1279{
1280 PDMDEV_ASSERT_DEVINS(pDevIns);
1281 pdmUnlock(pDevIns->Internal.s.pGVM);
1282}
1283
1284
1285/**
1286 * The Ring-0 I/O APIC Helper Callbacks.
1287 */
1288extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
1289{
1290 PDM_IOAPICHLPR0_VERSION,
1291 pdmR0IoApicHlp_ApicBusDeliver,
1292 pdmR0IoApicHlp_Lock,
1293 pdmR0IoApicHlp_Unlock,
1294 PDM_IOAPICHLPR0_VERSION
1295};
1296
1297/** @} */
1298
1299
1300
1301
1302/** @name PCI Bus Ring-0 Helpers
1303 * @{
1304 */
1305
1306/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1307static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1308{
1309 PDMDEV_ASSERT_DEVINS(pDevIns);
1310 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1311 PGVM pGVM = pDevIns->Internal.s.pGVM;
1312
1313 pdmLock(pGVM);
1314 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1315 pdmUnlock(pGVM);
1316}
1317
1318
1319/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1320static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1321{
1322 PDMDEV_ASSERT_DEVINS(pDevIns);
1323 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1324 PGVM pGVM = pDevIns->Internal.s.pGVM;
1325
1326 if (pGVM->pdm.s.IoApic.pDevInsR0)
1327 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
1328 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1329 {
1330 /* queue for ring-3 execution. */
1331 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1332 if (pTask)
1333 {
1334 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1335 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1336 pTask->u.IoApicSetIRQ.iIrq = iIrq;
1337 pTask->u.IoApicSetIRQ.iLevel = iLevel;
1338 pTask->u.IoApicSetIRQ.uTagSrc = uTagSrc;
1339
1340 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1341 }
1342 else
1343 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1344 }
1345}
1346
1347
1348/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1349static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
1350{
1351 PDMDEV_ASSERT_DEVINS(pDevIns);
1352 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
1353 PGVM pGVM = pDevIns->Internal.s.pGVM;
1354 if (pGVM->pdm.s.IoApic.pDevInsR0)
1355 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
1356 else
1357 AssertFatalMsgFailed(("Lazy bastards!"));
1358}
1359
1360
1361/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1362static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1363{
1364 PDMDEV_ASSERT_DEVINS(pDevIns);
1365 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1366}
1367
1368
1369/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1370static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1371{
1372 PDMDEV_ASSERT_DEVINS(pDevIns);
1373 pdmUnlock(pDevIns->Internal.s.pGVM);
1374}
1375
1376
1377/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1378static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1379{
1380 PDMDEV_ASSERT_DEVINS(pDevIns);
1381 PGVM pGVM = pDevIns->Internal.s.pGVM;
1382 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1383 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1384 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1385 return pRetDevIns;
1386}
1387
1388
1389/**
1390 * The Ring-0 PCI Bus Helper Callbacks.
1391 */
1392extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1393{
1394 PDM_PCIHLPR0_VERSION,
1395 pdmR0PciHlp_IsaSetIrq,
1396 pdmR0PciHlp_IoApicSetIrq,
1397 pdmR0PciHlp_IoApicSendMsi,
1398 pdmR0PciHlp_Lock,
1399 pdmR0PciHlp_Unlock,
1400 pdmR0PciHlp_GetBusByNo,
1401 PDM_PCIHLPR0_VERSION, /* the end */
1402};
1403
1404/** @} */
1405
1406
1407
1408
1409/** @name HPET Ring-0 Helpers
1410 * @{
1411 */
1412/* none */
1413
1414/**
1415 * The Ring-0 HPET Helper Callbacks.
1416 */
1417extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1418{
1419 PDM_HPETHLPR0_VERSION,
1420 PDM_HPETHLPR0_VERSION, /* the end */
1421};
1422
1423/** @} */
1424
1425
1426/** @name Raw PCI Ring-0 Helpers
1427 * @{
1428 */
1429/* none */
1430
1431/**
1432 * The Ring-0 PCI raw Helper Callbacks.
1433 */
1434extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1435{
1436 PDM_PCIRAWHLPR0_VERSION,
1437 PDM_PCIRAWHLPR0_VERSION, /* the end */
1438};
1439
1440/** @} */
1441
1442
1443/** @name Ring-0 Context Driver Helpers
1444 * @{
1445 */
1446
1447/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
1448static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
1449{
1450 PDMDRV_ASSERT_DRVINS(pDrvIns);
1451 va_list args;
1452 va_start(args, pszFormat);
1453 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
1454 va_end(args);
1455 return rc;
1456}
1457
1458
1459/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
1460static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
1461{
1462 PDMDRV_ASSERT_DRVINS(pDrvIns);
1463 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
1464 return rc;
1465}
1466
1467
1468/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
1469static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
1470 const char *pszFormat, ...)
1471{
1472 PDMDRV_ASSERT_DRVINS(pDrvIns);
1473 va_list va;
1474 va_start(va, pszFormat);
1475 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
1476 va_end(va);
1477 return rc;
1478}
1479
1480
1481/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeErrorV} */
1482static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
1483 const char *pszFormat, va_list va)
1484{
1485 PDMDRV_ASSERT_DRVINS(pDrvIns);
1486 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
1487 return rc;
1488}
1489
1490
1491/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
1492static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
1493{
1494 PDMDRV_ASSERT_DRVINS(pDrvIns);
1495 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
1496 return true;
1497
1498 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
1499 RTAssertPanic();
1500 return false;
1501}
1502
1503
1504/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
1505static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
1506{
1507 PDMDRV_ASSERT_DRVINS(pDrvIns);
1508 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
1509 return true;
1510
1511 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
1512 RTAssertPanic();
1513 return false;
1514}
1515
1516
1517/**
1518 * The Ring-0 Context Driver Helper Callbacks.
1519 */
1520extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
1521{
1522 PDM_DRVHLPRC_VERSION,
1523 pdmR0DrvHlp_VMSetError,
1524 pdmR0DrvHlp_VMSetErrorV,
1525 pdmR0DrvHlp_VMSetRuntimeError,
1526 pdmR0DrvHlp_VMSetRuntimeErrorV,
1527 pdmR0DrvHlp_AssertEMT,
1528 pdmR0DrvHlp_AssertOther,
1529 PDM_DRVHLPRC_VERSION
1530};
1531
1532/** @} */
1533
1534
1535
1536
1537/**
1538 * Sets an irq on the PIC and I/O APIC.
1539 *
1540 * @returns true if delivered, false if postponed.
1541 * @param pGVM The global (ring-0) VM structure.
1542 * @param iIrq The irq.
1543 * @param iLevel The new level.
1544 * @param uTagSrc The IRQ tag and source.
1545 *
1546 * @remarks The caller holds the PDM lock.
1547 */
1548static bool pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1549{
1550 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1551 || !pGVM->pdm.s.IoApic.pDevInsR3)
1552 && ( pGVM->pdm.s.Pic.pDevInsR0
1553 || !pGVM->pdm.s.Pic.pDevInsR3)))
1554 {
1555 if (pGVM->pdm.s.Pic.pDevInsR0)
1556 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1557 if (pGVM->pdm.s.IoApic.pDevInsR0)
1558 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
1559 return true;
1560 }
1561
1562 /* queue for ring-3 execution. */
1563 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1564 AssertReturn(pTask, false);
1565
1566 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1567 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1568 pTask->u.IsaSetIRQ.iIrq = iIrq;
1569 pTask->u.IsaSetIRQ.iLevel = iLevel;
1570 pTask->u.IsaSetIRQ.uTagSrc = uTagSrc;
1571
1572 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1573 return false;
1574}
1575
1576
1577/**
1578 * Worker for PDMR0DeviceCreate that does the actual instantiation.
1579 *
1580 * Allocates a memory object and divides it up as follows:
1581 * @verbatim
1582 --------------------------------------
1583 ring-0 devins
1584 --------------------------------------
1585 ring-0 instance data
1586 --------------------------------------
1587 ring-0 PCI device data (optional) ??
1588 --------------------------------------
1589 page alignment padding
1590 --------------------------------------
1591 ring-3 devins
1592 --------------------------------------
1593 ring-3 instance data
1594 --------------------------------------
1595 ring-3 PCI device data (optional) ??
1596 --------------------------------------
1597 [page alignment padding ] -
1598 [--------------------------------------] \
1599 [raw-mode devins ] \
1600 [--------------------------------------] - Optional, only when raw-mode is enabled.
1601 [raw-mode instance data ] /
1602 [--------------------------------------] /
1603 [raw-mode PCI device data (optional)?? ] -
1604 --------------------------------------
1605 shared instance data
1606 --------------------------------------
1607 default crit section
1608 --------------------------------------
1609 shared PCI device data (optional)
1610 --------------------------------------
1611 @endverbatim
1612 *
1613 * @returns VBox status code.
1614 * @param pGVM The global (ring-0) VM structure.
1615 * @param pDevReg The device registration structure.
1616 * @param iInstance The device instance number.
1617 * @param cbInstanceR3 The size of the ring-3 instance data.
1618 * @param cbInstanceRC The size of the raw-mode instance data.
1619 * @param hMod The module implementing the device. On success, the
1620 * @param RCPtrMapping The raw-mode context mapping address, NIL_RTGCPTR if
1621 * not to include raw-mode.
1622 * @param ppDevInsR3 Where to return the ring-3 device instance address.
1623 * @thread EMT(0)
1624 */
1625static int pdmR0DeviceCreateWorker(PGVM pGVM, PCPDMDEVREGR0 pDevReg, uint32_t iInstance, uint32_t cbInstanceR3,
1626 uint32_t cbInstanceRC, RTRGPTR RCPtrMapping, void *hMod, PPDMDEVINSR3 *ppDevInsR3)
1627{
1628 /*
1629 * Check that the instance number isn't a duplicate.
1630 */
1631 for (size_t i = 0; i < pGVM->pdmr0.s.cDevInstances; i++)
1632 {
1633 PPDMDEVINS pCur = pGVM->pdmr0.s.apDevInstances[i];
1634 AssertLogRelReturn(!pCur || pCur->pReg != pDevReg || pCur->iInstance != iInstance, VERR_DUPLICATE);
1635 }
1636
1637 /*
1638 * Figure out how much memory we need and allocate it.
1639 */
1640 uint32_t const cbRing0 = RT_ALIGN_32(RT_UOFFSETOF(PDMDEVINSR0, achInstanceData) + pDevReg->cbInstanceCC, PAGE_SIZE);
1641 uint32_t const cbRing3 = RT_ALIGN_32(RT_UOFFSETOF(PDMDEVINSR3, achInstanceData) + cbInstanceR3,
1642 RCPtrMapping != NIL_RTRGPTR ? PAGE_SIZE : 64);
1643 uint32_t const cbRC = RCPtrMapping != NIL_RTRGPTR ? 0
1644 : RT_ALIGN_32(RT_UOFFSETOF(PDMDEVINSRC, achInstanceData) + cbInstanceRC, 64);
1645 uint32_t const cbShared = RT_ALIGN_32(pDevReg->cbInstanceShared, 64);
1646 uint32_t const cbCritSect = RT_ALIGN_32(sizeof(PDMCRITSECT), 64);
1647 uint32_t const cbMsixState = RT_ALIGN_32(pDevReg->cMaxMsixVectors * 16 + (pDevReg->cMaxMsixVectors + 7) / 8, _4K);
1648 uint32_t const cbPciDev = RT_ALIGN_32(RT_UOFFSETOF_DYN(PDMPCIDEV, abMsixState[cbMsixState]), 64);
1649 uint32_t const cPciDevs = RT_MIN(pDevReg->cMaxPciDevices, 8);
1650 uint32_t const cbPciDevs = cbPciDev * cPciDevs;
1651 uint32_t const cbTotal = RT_ALIGN_32(cbRing0 + cbRing3 + cbRC + cbShared + cbCritSect + cbPciDevs, PAGE_SIZE);
1652 AssertLogRelMsgReturn(cbTotal <= PDM_MAX_DEVICE_INSTANCE_SIZE,
1653 ("Instance of '%s' is too big: cbTotal=%u, max %u\n",
1654 pDevReg->szName, cbTotal, PDM_MAX_DEVICE_INSTANCE_SIZE),
1655 VERR_OUT_OF_RANGE);
1656
1657 RTR0MEMOBJ hMemObj;
1658 int rc = RTR0MemObjAllocPage(&hMemObj, cbTotal, false /*fExecutable*/);
1659 if (RT_FAILURE(rc))
1660 return rc;
1661 RT_BZERO(RTR0MemObjAddress(hMemObj), cbTotal);
1662
1663 /* Map it. */
1664 RTR0MEMOBJ hMapObj;
1665 rc = RTR0MemObjMapUserEx(&hMapObj, hMemObj, (RTR3PTR)-1, 0, RTMEM_PROT_READ | RTMEM_PROT_WRITE, RTR0ProcHandleSelf(),
1666 cbRing0, cbTotal - cbRing0);
1667 if (RT_SUCCESS(rc))
1668 {
1669 PPDMDEVINSR0 pDevIns = (PPDMDEVINSR0)RTR0MemObjAddress(hMemObj);
1670 struct PDMDEVINSR3 *pDevInsR3 = (struct PDMDEVINSR3 *)((uint8_t *)pDevIns + cbRing0);
1671
1672 /*
1673 * Initialize the ring-0 instance.
1674 */
1675 pDevIns->u32Version = PDM_DEVINSR0_VERSION;
1676 pDevIns->iInstance = iInstance;
1677 pDevIns->pHlpR0 = &g_pdmR0DevHlp;
1678 pDevIns->pvInstanceDataR0 = (uint8_t *)pDevIns + cbRing0 + cbRing3 + cbRC;
1679 pDevIns->pvInstanceDataForR0 = &pDevIns->achInstanceData[0];
1680 pDevIns->pCritSectRoR0 = (PPDMCRITSECT)((uint8_t *)pDevIns->pvInstanceDataR0 + cbShared);
1681 pDevIns->pReg = pDevReg;
1682 pDevIns->pDevInsForR3 = RTR0MemObjAddressR3(hMapObj);
1683 pDevIns->pDevInsForR3R0 = pDevInsR3;
1684 pDevIns->pvInstanceDataForR3R0 = &pDevInsR3->achInstanceData[0];
1685 pDevIns->cbPciDev = cbPciDev;
1686 pDevIns->cPciDevs = cPciDevs;
1687 for (uint32_t iPciDev = 0; iPciDev < cPciDevs; iPciDev++)
1688 {
1689 /* Note! PDMDevice.cpp has a copy of this code. Keep in sync. */
1690 PPDMPCIDEV pPciDev = (PPDMPCIDEV)((uint8_t *)pDevIns->pCritSectRoR0 + cbCritSect + cbPciDev * iPciDev);
1691 if (iPciDev < RT_ELEMENTS(pDevIns->apPciDevs))
1692 pDevIns->apPciDevs[iPciDev] = pPciDev;
1693 pPciDev->cbConfig = _4K;
1694 pPciDev->cbMsixState = cbMsixState;
1695 pPciDev->idxSubDev = (uint16_t)iPciDev;
1696 pPciDev->Int.s.idxSubDev = (uint16_t)iPciDev;
1697 pPciDev->u32Magic = PDMPCIDEV_MAGIC;
1698 }
1699 pDevIns->Internal.s.pGVM = pGVM;
1700 pDevIns->Internal.s.pRegR0 = pDevReg;
1701 pDevIns->Internal.s.hMod = hMod;
1702 pDevIns->Internal.s.hMemObj = hMemObj;
1703 pDevIns->Internal.s.hMapObj = hMapObj;
1704 pDevIns->Internal.s.pInsR3R0 = pDevInsR3;
1705 pDevIns->Internal.s.pIntR3R0 = &pDevInsR3->Internal.s;
1706
1707 /*
1708 * Initialize the ring-3 instance data as much as we can.
1709 * Note! PDMDevice.cpp does this job for ring-3 only devices. Keep in sync.
1710 */
1711 pDevInsR3->u32Version = PDM_DEVINSR3_VERSION;
1712 pDevInsR3->iInstance = iInstance;
1713 pDevInsR3->cbRing3 = cbTotal - cbRing0;
1714 pDevInsR3->fR0Enabled = true;
1715 pDevInsR3->fRCEnabled = RCPtrMapping != NIL_RTRGPTR;
1716 pDevInsR3->pvInstanceDataR3 = pDevIns->pDevInsForR3 + cbRing3 + cbRC;
1717 pDevInsR3->pvInstanceDataForR3 = pDevIns->pDevInsForR3 + RT_UOFFSETOF(PDMDEVINSR3, achInstanceData);
1718 pDevInsR3->pCritSectRoR3 = pDevIns->pDevInsForR3 + cbRing3 + cbRC + cbShared;
1719 pDevInsR3->pDevInsR0RemoveMe = pDevIns;
1720 pDevInsR3->pvInstanceDataR0 = pDevIns->pvInstanceDataR0;
1721 pDevInsR3->pvInstanceDataRC = RCPtrMapping == NIL_RTRGPTR
1722 ? NIL_RTRGPTR : pDevIns->pDevInsForRC + RT_UOFFSETOF(PDMDEVINSRC, achInstanceData);
1723 pDevInsR3->pDevInsForRC = pDevIns->pDevInsForRC;
1724 pDevInsR3->pDevInsForRCR3 = pDevIns->pDevInsForR3 + cbRing3;
1725 pDevInsR3->pDevInsForRCR3 = pDevInsR3->pDevInsForRCR3 + RT_UOFFSETOF(PDMDEVINSRC, achInstanceData);
1726 pDevInsR3->cbPciDev = cbPciDev;
1727 pDevInsR3->cPciDevs = cPciDevs;
1728 for (uint32_t i = 0; i < RT_MIN(cPciDevs, RT_ELEMENTS(pDevIns->apPciDevs)); i++)
1729 pDevInsR3->apPciDevs[i] = pDevInsR3->pCritSectRoR3 + cbCritSect + cbPciDev * i;
1730
1731 pDevInsR3->Internal.s.pVMR3 = pGVM->pVMR3;
1732 pDevInsR3->Internal.s.fIntFlags = RCPtrMapping == NIL_RTRGPTR ? PDMDEVINSINT_FLAGS_R0_ENABLED
1733 : PDMDEVINSINT_FLAGS_R0_ENABLED | PDMDEVINSINT_FLAGS_RC_ENABLED;
1734
1735 /*
1736 * Initialize the raw-mode instance data as much as possible.
1737 */
1738 if (RCPtrMapping != NIL_RTRGPTR)
1739 {
1740 struct PDMDEVINSRC *pDevInsRC = RCPtrMapping == NIL_RTRGPTR ? NULL
1741 : (struct PDMDEVINSRC *)((uint8_t *)pDevIns + cbRing0 + cbRing3);
1742
1743 pDevIns->pDevInsForRC = RCPtrMapping;
1744 pDevIns->pDevInsForRCR0 = pDevInsRC;
1745 pDevIns->pvInstanceDataForRCR0 = &pDevInsRC->achInstanceData[0];
1746
1747 pDevInsRC->u32Version = PDM_DEVINSRC_VERSION;
1748 pDevInsRC->iInstance = iInstance;
1749 pDevInsRC->pvInstanceDataRC = pDevIns->pDevInsForRC + cbRC;
1750 pDevInsRC->pvInstanceDataForRC = pDevIns->pDevInsForRC + RT_UOFFSETOF(PDMDEVINSRC, achInstanceData);
1751 pDevInsRC->pCritSectRoRC = pDevIns->pDevInsForRC + cbRC + cbShared;
1752 pDevInsRC->cbPciDev = cbPciDev;
1753 pDevInsRC->cPciDevs = cPciDevs;
1754 for (uint32_t i = 0; i < RT_MIN(cPciDevs, RT_ELEMENTS(pDevIns->apPciDevs)); i++)
1755 pDevInsRC->apPciDevs[i] = pDevInsRC->pCritSectRoRC + cbCritSect + cbPciDev * i;
1756
1757 pDevInsRC->Internal.s.pVMRC = pGVM->pVMRC;
1758 }
1759
1760 /*
1761 * Add to the device instance array and set its handle value.
1762 */
1763 AssertCompile(sizeof(pGVM->pdmr0.padding) == sizeof(pGVM->pdmr0));
1764 uint32_t idxR0Device = pGVM->pdmr0.s.cDevInstances;
1765 if (idxR0Device < RT_ELEMENTS(pGVM->pdmr0.s.apDevInstances))
1766 {
1767 pGVM->pdmr0.s.apDevInstances[idxR0Device] = pDevIns;
1768 pGVM->pdmr0.s.cDevInstances = idxR0Device + 1;
1769 pDevIns->Internal.s.idxR0Device = idxR0Device;
1770 pDevInsR3->Internal.s.idxR0Device = idxR0Device;
1771
1772 /*
1773 * Call the early constructor if present.
1774 */
1775 if (pDevReg->pfnEarlyConstruct)
1776 rc = pDevReg->pfnEarlyConstruct(pDevIns);
1777 if (RT_SUCCESS(rc))
1778 {
1779 /*
1780 * We're done.
1781 */
1782 *ppDevInsR3 = RTR0MemObjAddressR3(hMapObj);
1783 return rc;
1784 }
1785
1786 /*
1787 * Bail out.
1788 */
1789 if (pDevIns->pReg->pfnFinalDestruct)
1790 pDevIns->pReg->pfnFinalDestruct(pDevIns);
1791
1792 pGVM->pdmr0.s.apDevInstances[idxR0Device] = NULL;
1793 Assert(pGVM->pdmr0.s.cDevInstances == idxR0Device + 1);
1794 pGVM->pdmr0.s.cDevInstances = idxR0Device;
1795 }
1796
1797 RTR0MemObjFree(hMapObj, true);
1798 }
1799 RTR0MemObjFree(hMemObj, true);
1800 return rc;
1801}
1802
1803
1804/**
1805 * Used by ring-3 PDM to create a device instance that operates both in ring-3
1806 * and ring-0.
1807 *
1808 * Creates an instance of a device (for both ring-3 and ring-0, and optionally
1809 * raw-mode context).
1810 *
1811 * @returns VBox status code.
1812 * @param pGVM The global (ring-0) VM structure.
1813 * @param pReq Pointer to the request buffer.
1814 * @thread EMT(0)
1815 */
1816VMMR0_INT_DECL(int) PDMR0DeviceCreateReqHandler(PGVM pGVM, PPDMDEVICECREATEREQ pReq)
1817{
1818 LogFlow(("PDMR0DeviceCreateReqHandler: %s in %s\n", pReq->szDevName, pReq->szModName));
1819
1820 /*
1821 * Validate the request.
1822 */
1823 AssertReturn(pReq->Hdr.cbReq == sizeof(*pReq), VERR_INVALID_PARAMETER);
1824 pReq->pDevInsR3 = NIL_RTR3PTR;
1825
1826 int rc = GVMMR0ValidateGVMandEMT(pGVM, 0);
1827 AssertRCReturn(rc, rc);
1828
1829 AssertReturn(pReq->fFlags != 0, VERR_INVALID_FLAGS);
1830 AssertReturn(pReq->fClass != 0, VERR_WRONG_TYPE);
1831 AssertReturn(pReq->uSharedVersion != 0, VERR_INVALID_PARAMETER);
1832 AssertReturn(pReq->cbInstanceShared != 0, VERR_INVALID_PARAMETER);
1833 size_t const cchDevName = RTStrNLen(pReq->szDevName, sizeof(pReq->szDevName));
1834 AssertReturn(cchDevName < sizeof(pReq->szDevName), VERR_NO_STRING_TERMINATOR);
1835 AssertReturn(cchDevName > 0, VERR_EMPTY_STRING);
1836 AssertReturn(cchDevName < RT_SIZEOFMEMB(PDMDEVREG, szName), VERR_NOT_FOUND);
1837
1838 size_t const cchModName = RTStrNLen(pReq->szModName, sizeof(pReq->szModName));
1839 AssertReturn(cchModName < sizeof(pReq->szModName), VERR_NO_STRING_TERMINATOR);
1840 AssertReturn(cchModName > 0, VERR_EMPTY_STRING);
1841 AssertReturn(pReq->cbInstanceShared <= PDM_MAX_DEVICE_INSTANCE_SIZE, VERR_OUT_OF_RANGE);
1842 AssertReturn(pReq->cbInstanceR3 <= PDM_MAX_DEVICE_INSTANCE_SIZE, VERR_OUT_OF_RANGE);
1843 AssertReturn(pReq->cbInstanceRC <= PDM_MAX_DEVICE_INSTANCE_SIZE, VERR_OUT_OF_RANGE);
1844 AssertReturn(pReq->iInstance < 1024, VERR_OUT_OF_RANGE);
1845 AssertReturn(pReq->iInstance < pReq->cMaxInstances, VERR_OUT_OF_RANGE);
1846 AssertReturn(pReq->cMaxPciDevices <= 8, VERR_OUT_OF_RANGE);
1847 AssertReturn(pReq->cMaxMsixVectors <= VBOX_MSIX_MAX_ENTRIES, VERR_OUT_OF_RANGE);
1848
1849 /*
1850 * Reference the module.
1851 */
1852 void *hMod = NULL;
1853 rc = SUPR0LdrModByName(pGVM->pSession, pReq->szModName, &hMod);
1854 if (RT_FAILURE(rc))
1855 {
1856 LogRel(("PDMR0DeviceCreateReqHandler: SUPR0LdrModByName(,%s,) failed: %Rrc\n", pReq->szModName, rc));
1857 return rc;
1858 }
1859
1860 /*
1861 * Look for the the module and the device registration structure.
1862 */
1863 int rcLock = SUPR0LdrLock(pGVM->pSession);
1864 AssertRC(rc);
1865
1866 rc = VERR_NOT_FOUND;
1867 PPDMDEVMODREGR0 pMod;
1868 RTListForEach(&g_PDMDevModList, pMod, PDMDEVMODREGR0, ListEntry)
1869 {
1870 if (pMod->hMod == hMod)
1871 {
1872 /*
1873 * Found the module. We can drop the loader lock now before we
1874 * search the devices it registers.
1875 */
1876 if (RT_SUCCESS(rcLock))
1877 {
1878 rcLock = SUPR0LdrUnlock(pGVM->pSession);
1879 AssertRC(rcLock);
1880 }
1881 rcLock = VERR_ALREADY_RESET;
1882
1883 PCPDMDEVREGR0 *papDevRegs = pMod->papDevRegs;
1884 size_t i = pMod->cDevRegs;
1885 while (i-- > 0)
1886 {
1887 PCPDMDEVREGR0 pDevReg = papDevRegs[i];
1888 LogFlow(("PDMR0DeviceCreateReqHandler: candidate #%u: %s %#x\n", i, pReq->szDevName, pDevReg->u32Version));
1889 if ( PDM_VERSION_ARE_COMPATIBLE(pDevReg->u32Version, PDM_DEVREGR0_VERSION)
1890 && pDevReg->szName[cchDevName] == '\0'
1891 && memcmp(pDevReg->szName, pReq->szDevName, cchDevName) == 0)
1892 {
1893
1894 /*
1895 * Found the device, now check whether it matches the ring-3 registration.
1896 */
1897 if ( pReq->uSharedVersion == pDevReg->uSharedVersion
1898 && pReq->cbInstanceShared == pDevReg->cbInstanceShared
1899 && pReq->cbInstanceRC == pDevReg->cbInstanceRC
1900 && pReq->fFlags == pDevReg->fFlags
1901 && pReq->fClass == pDevReg->fClass
1902 && pReq->cMaxInstances == pDevReg->cMaxInstances
1903 && pReq->cMaxPciDevices == pDevReg->cMaxPciDevices
1904 && pReq->cMaxMsixVectors == pDevReg->cMaxMsixVectors)
1905 {
1906 rc = pdmR0DeviceCreateWorker(pGVM, pDevReg, pReq->iInstance, pReq->cbInstanceR3, pReq->cbInstanceRC,
1907 NIL_RTRCPTR /** @todo new raw-mode */, hMod, &pReq->pDevInsR3);
1908 if (RT_SUCCESS(rc))
1909 hMod = NULL; /* keep the module reference */
1910 }
1911 else
1912 {
1913 LogRel(("PDMR0DeviceCreate: Ring-3 does not match ring-0 device registration (%s):\n"
1914 " uSharedVersion: %#x vs %#x\n"
1915 " cbInstanceShared: %#x vs %#x\n"
1916 " cbInstanceRC: %#x vs %#x\n"
1917 " fFlags: %#x vs %#x\n"
1918 " fClass: %#x vs %#x\n"
1919 " cMaxInstances: %#x vs %#x\n"
1920 " cMaxPciDevices: %#x vs %#x\n"
1921 " cMaxMsixVectors: %#x vs %#x\n"
1922 ,
1923 pReq->szDevName,
1924 pReq->uSharedVersion, pDevReg->uSharedVersion,
1925 pReq->cbInstanceShared, pDevReg->cbInstanceShared,
1926 pReq->cbInstanceRC, pDevReg->cbInstanceRC,
1927 pReq->fFlags, pDevReg->fFlags,
1928 pReq->fClass, pDevReg->fClass,
1929 pReq->cMaxInstances, pDevReg->cMaxInstances,
1930 pReq->cMaxPciDevices, pDevReg->cMaxPciDevices,
1931 pReq->cMaxMsixVectors, pDevReg->cMaxMsixVectors));
1932 rc = VERR_INCOMPATIBLE_CONFIG;
1933 }
1934 }
1935 }
1936 break;
1937 }
1938 }
1939
1940 if (RT_SUCCESS_NP(rcLock))
1941 {
1942 rcLock = SUPR0LdrUnlock(pGVM->pSession);
1943 AssertRC(rcLock);
1944 }
1945 SUPR0LdrModRelease(pGVM->pSession, hMod);
1946 return rc;
1947}
1948
1949
1950/**
1951 * Used by ring-3 PDM to call standard ring-0 device methods.
1952 *
1953 * @returns VBox status code.
1954 * @param pGVM The global (ring-0) VM structure.
1955 * @param pReq Pointer to the request buffer.
1956 * @param idCpu The ID of the calling EMT.
1957 * @thread EMT(0), except for PDMDEVICEGENCALL_REQUEST which can be any EMT.
1958 */
1959VMMR0_INT_DECL(int) PDMR0DeviceGenCallReqHandler(PGVM pGVM, PPDMDEVICEGENCALLREQ pReq, VMCPUID idCpu)
1960{
1961 /*
1962 * Validate the request.
1963 */
1964 AssertReturn(pReq->Hdr.cbReq == sizeof(*pReq), VERR_INVALID_PARAMETER);
1965
1966 int rc = GVMMR0ValidateGVMandEMT(pGVM, idCpu);
1967 AssertRCReturn(rc, rc);
1968
1969 AssertReturn(pReq->idxR0Device < pGVM->pdmr0.s.cDevInstances, VERR_INVALID_HANDLE);
1970 PPDMDEVINSR0 pDevIns = pGVM->pdmr0.s.apDevInstances[pReq->idxR0Device];
1971 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
1972 AssertReturn(pDevIns->pDevInsForR3 == pReq->pDevInsR3, VERR_INVALID_HANDLE);
1973
1974 /*
1975 * Make the call.
1976 */
1977 rc = VINF_SUCCESS /*VINF_NOT_IMPLEMENTED*/;
1978 switch (pReq->enmCall)
1979 {
1980 case PDMDEVICEGENCALL_CONSTRUCT:
1981 AssertMsgBreakStmt(pGVM->enmVMState < VMSTATE_CREATED, ("enmVMState=%d\n", pGVM->enmVMState), rc = VERR_INVALID_STATE);
1982 AssertReturn(idCpu == 0, VERR_VM_THREAD_NOT_EMT);
1983 if (pDevIns->pReg->pfnConstruct)
1984 rc = pDevIns->pReg->pfnConstruct(pDevIns);
1985 break;
1986
1987 case PDMDEVICEGENCALL_DESTRUCT:
1988 AssertMsgBreakStmt(pGVM->enmVMState < VMSTATE_CREATED || pGVM->enmVMState >= VMSTATE_DESTROYING,
1989 ("enmVMState=%d\n", pGVM->enmVMState), rc = VERR_INVALID_STATE);
1990 AssertReturn(idCpu == 0, VERR_VM_THREAD_NOT_EMT);
1991 if (pDevIns->pReg->pfnDestruct)
1992 {
1993 pDevIns->pReg->pfnDestruct(pDevIns);
1994 rc = VINF_SUCCESS;
1995 }
1996 break;
1997
1998 case PDMDEVICEGENCALL_REQUEST:
1999 if (pDevIns->pReg->pfnRequest)
2000 rc = pDevIns->pReg->pfnRequest(pDevIns, pReq->Params.Req.uReq, pReq->Params.Req.uArg);
2001 else
2002 rc = VERR_INVALID_FUNCTION;
2003 break;
2004
2005 default:
2006 AssertMsgFailed(("enmCall=%d\n", pReq->enmCall));
2007 rc = VERR_INVALID_FUNCTION;
2008 break;
2009 }
2010
2011 return rc;
2012}
2013
2014
2015/**
2016 * Legacy device mode compatiblity.
2017 *
2018 * @returns VBox status code.
2019 * @param pGVM The global (ring-0) VM structure.
2020 * @param pReq Pointer to the request buffer.
2021 * @thread EMT(0)
2022 */
2023VMMR0_INT_DECL(int) PDMR0DeviceCompatSetCritSectReqHandler(PGVM pGVM, PPDMDEVICECOMPATSETCRITSECTREQ pReq)
2024{
2025 /*
2026 * Validate the request.
2027 */
2028 AssertReturn(pReq->Hdr.cbReq == sizeof(*pReq), VERR_INVALID_PARAMETER);
2029
2030 int rc = GVMMR0ValidateGVMandEMT(pGVM, 0);
2031 AssertRCReturn(rc, rc);
2032
2033 AssertReturn(pReq->idxR0Device < pGVM->pdmr0.s.cDevInstances, VERR_INVALID_HANDLE);
2034 PPDMDEVINSR0 pDevIns = pGVM->pdmr0.s.apDevInstances[pReq->idxR0Device];
2035 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
2036 AssertReturn(pDevIns->pDevInsForR3 == pReq->pDevInsR3, VERR_INVALID_HANDLE);
2037
2038 AssertReturn(pGVM->enmVMState == VMSTATE_CREATING, VERR_INVALID_STATE);
2039
2040 /*
2041 * The critical section address can be in a few different places:
2042 * 1. shared data.
2043 * 2. nop section.
2044 * 3. pdm critsect.
2045 */
2046 PPDMCRITSECT pCritSect;
2047 if (pReq->pCritSectR3 == pGVM->pVMR3 + RT_UOFFSETOF(VM, pdm.s.NopCritSect))
2048 {
2049 pCritSect = &pGVM->pdm.s.NopCritSect;
2050 Log(("PDMR0DeviceCompatSetCritSectReqHandler: Nop - %p %#x\n", pCritSect, pCritSect->s.Core.u32Magic));
2051 }
2052 else if (pReq->pCritSectR3 == pGVM->pVMR3 + RT_UOFFSETOF(VM, pdm.s.CritSect))
2053 {
2054 pCritSect = &pGVM->pdm.s.CritSect;
2055 Log(("PDMR0DeviceCompatSetCritSectReqHandler: PDM - %p %#x\n", pCritSect, pCritSect->s.Core.u32Magic));
2056 }
2057 else
2058 {
2059 size_t offCritSect = pReq->pCritSectR3 - pDevIns->pDevInsForR3R0->pvInstanceDataR3;
2060 AssertLogRelMsgReturn( offCritSect < pDevIns->pReg->cbInstanceShared
2061 && offCritSect + sizeof(PDMCRITSECT) <= pDevIns->pReg->cbInstanceShared,
2062 ("offCritSect=%p pCritSectR3=%p cbInstanceShared=%#x (%s)\n",
2063 offCritSect, pReq->pCritSectR3, pDevIns->pReg->cbInstanceShared, pDevIns->pReg->szName),
2064 VERR_INVALID_POINTER);
2065 pCritSect = (PPDMCRITSECT)((uint8_t *)pDevIns->pvInstanceDataR0 + offCritSect);
2066 Log(("PDMR0DeviceCompatSetCritSectReqHandler: custom - %#x/%p %#x\n", offCritSect, pCritSect, pCritSect->s.Core.u32Magic));
2067 }
2068 AssertLogRelMsgReturn(pCritSect->s.Core.u32Magic == RTCRITSECT_MAGIC,
2069 ("cs=%p magic=%#x dev=%s\n", pCritSect, pCritSect->s.Core.u32Magic, pDevIns->pReg->szName),
2070 VERR_INVALID_MAGIC);
2071
2072 /*
2073 * Make the update.
2074 */
2075 pDevIns->pCritSectRoR0 = pCritSect;
2076
2077 return VINF_SUCCESS;
2078}
2079
2080
2081/**
2082 * Registers the device implementations living in a module.
2083 *
2084 * This should normally only be called during ModuleInit(). The should be a
2085 * call to PDMR0DeviceDeregisterModule from the ModuleTerm() function to undo
2086 * the effects of this call.
2087 *
2088 * @returns VBox status code.
2089 * @param hMod The module handle of the module being registered.
2090 * @param pModReg The module registration structure. This will be
2091 * used directly so it must live as long as the module
2092 * and be writable.
2093 *
2094 * @note Caller must own the loader lock!
2095 */
2096VMMR0DECL(int) PDMR0DeviceRegisterModule(void *hMod, PPDMDEVMODREGR0 pModReg)
2097{
2098 /*
2099 * Validate the input.
2100 */
2101 AssertPtrReturn(hMod, VERR_INVALID_HANDLE);
2102 Assert(SUPR0LdrIsLockOwnerByMod(hMod, true));
2103
2104 AssertPtrReturn(pModReg, VERR_INVALID_POINTER);
2105 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE(pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2106 ("pModReg->u32Version=%#x vs %#x\n", pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2107 VERR_VERSION_MISMATCH);
2108 AssertLogRelMsgReturn(pModReg->cDevRegs <= 256 && pModReg->cDevRegs > 0, ("cDevRegs=%u\n", pModReg->cDevRegs),
2109 VERR_OUT_OF_RANGE);
2110 AssertLogRelMsgReturn(pModReg->hMod == NULL, ("hMod=%p\n", pModReg->hMod), VERR_INVALID_PARAMETER);
2111 AssertLogRelMsgReturn(pModReg->ListEntry.pNext == NULL, ("pNext=%p\n", pModReg->ListEntry.pNext), VERR_INVALID_PARAMETER);
2112 AssertLogRelMsgReturn(pModReg->ListEntry.pPrev == NULL, ("pPrev=%p\n", pModReg->ListEntry.pPrev), VERR_INVALID_PARAMETER);
2113
2114 for (size_t i = 0; i < pModReg->cDevRegs; i++)
2115 {
2116 PCPDMDEVREGR0 pDevReg = pModReg->papDevRegs[i];
2117 AssertLogRelMsgReturn(RT_VALID_PTR(pDevReg), ("[%u]: %p\n", i, pDevReg), VERR_INVALID_POINTER);
2118 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE(pDevReg->u32Version, PDM_DEVREGR0_VERSION),
2119 ("pDevReg->u32Version=%#x vs %#x\n", pModReg->u32Version, PDM_DEVREGR0_VERSION), VERR_VERSION_MISMATCH);
2120 AssertLogRelMsgReturn(RT_VALID_PTR(pDevReg->pszDescription), ("[%u]: %p\n", i, pDevReg->pszDescription), VERR_INVALID_POINTER);
2121 AssertLogRelMsgReturn(pDevReg->uReserved0 == 0, ("[%u]: %#x\n", i, pDevReg->uReserved0), VERR_INVALID_PARAMETER);
2122 AssertLogRelMsgReturn(pDevReg->fClass != 0, ("[%u]: %#x\n", i, pDevReg->fClass), VERR_INVALID_PARAMETER);
2123 AssertLogRelMsgReturn(pDevReg->fFlags != 0, ("[%u]: %#x\n", i, pDevReg->fFlags), VERR_INVALID_PARAMETER);
2124 AssertLogRelMsgReturn(pDevReg->cMaxInstances > 0, ("[%u]: %#x\n", i, pDevReg->cMaxInstances), VERR_INVALID_PARAMETER);
2125 AssertLogRelMsgReturn(pDevReg->cMaxPciDevices <= 8, ("[%u]: %#x\n", i, pDevReg->cMaxPciDevices), VERR_INVALID_PARAMETER);
2126 AssertLogRelMsgReturn(pDevReg->cMaxMsixVectors <= VBOX_MSIX_MAX_ENTRIES,
2127 ("[%u]: %#x\n", i, pDevReg->cMaxMsixVectors), VERR_INVALID_PARAMETER);
2128
2129 /* The name must be printable ascii and correctly terminated. */
2130 for (size_t off = 0; off < RT_ELEMENTS(pDevReg->szName); off++)
2131 {
2132 char ch = pDevReg->szName[off];
2133 AssertLogRelMsgReturn(RT_C_IS_PRINT(ch) || (ch == '\0' && off > 0),
2134 ("[%u]: off=%u szName: %.*Rhxs\n", i, off, sizeof(pDevReg->szName), &pDevReg->szName[0]),
2135 VERR_INVALID_NAME);
2136 if (ch == '\0')
2137 break;
2138 }
2139 }
2140
2141 /*
2142 * Add it, assuming we're being called at ModuleInit/ModuleTerm time only, or
2143 * that the caller has already taken the loader lock.
2144 */
2145 pModReg->hMod = hMod;
2146 RTListAppend(&g_PDMDevModList, &pModReg->ListEntry);
2147
2148 return VINF_SUCCESS;
2149}
2150
2151
2152/**
2153 * Deregisters the device implementations living in a module.
2154 *
2155 * This should normally only be called during ModuleTerm().
2156 *
2157 * @returns VBox status code.
2158 * @param hMod The module handle of the module being registered.
2159 * @param pModReg The module registration structure. This will be
2160 * used directly so it must live as long as the module
2161 * and be writable.
2162 *
2163 * @note Caller must own the loader lock!
2164 */
2165VMMR0DECL(int) PDMR0DeviceDeregisterModule(void *hMod, PPDMDEVMODREGR0 pModReg)
2166{
2167 /*
2168 * Validate the input.
2169 */
2170 AssertPtrReturn(hMod, VERR_INVALID_HANDLE);
2171 Assert(SUPR0LdrIsLockOwnerByMod(hMod, true));
2172
2173 AssertPtrReturn(pModReg, VERR_INVALID_POINTER);
2174 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE(pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2175 ("pModReg->u32Version=%#x vs %#x\n", pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2176 VERR_VERSION_MISMATCH);
2177 AssertLogRelMsgReturn(pModReg->hMod == hMod || pModReg->hMod == NULL, ("pModReg->hMod=%p vs %p\n", pModReg->hMod, hMod),
2178 VERR_INVALID_PARAMETER);
2179
2180 /*
2181 * Unlink the registration record and return it to virgin conditions. Ignore
2182 * the call if not registered.
2183 */
2184 if (pModReg->hMod)
2185 {
2186 pModReg->hMod = NULL;
2187 RTListNodeRemove(&pModReg->ListEntry);
2188 pModReg->ListEntry.pNext = NULL;
2189 pModReg->ListEntry.pPrev = NULL;
2190 return VINF_SUCCESS;
2191 }
2192 return VWRN_NOT_FOUND;
2193}
2194
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