VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp@ 81916

Last change on this file since 81916 was 81916, checked in by vboxsync, 5 years ago

PDM: logging fixes. bugref:9218
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File size: 87.1 KB
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1/* $Id: PDMR0Device.cpp 81916 2019-11-17 20:43:45Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, R0 Device parts.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/apic.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/gvm.h>
30#include <VBox/vmm/vmm.h>
31#include <VBox/vmm/hm.h>
32#include <VBox/vmm/vmcc.h>
33#include <VBox/vmm/gvmm.h>
34
35#include <VBox/log.h>
36#include <VBox/err.h>
37#include <VBox/msi.h>
38#include <VBox/sup.h>
39#include <iprt/asm.h>
40#include <iprt/assert.h>
41#include <iprt/ctype.h>
42#include <iprt/mem.h>
43#include <iprt/memobj.h>
44#include <iprt/process.h>
45#include <iprt/string.h>
46
47#include "dtrace/VBoxVMM.h"
48#include "PDMInline.h"
49
50
51/*********************************************************************************************************************************
52* Global Variables *
53*********************************************************************************************************************************/
54RT_C_DECLS_BEGIN
55extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp;
56extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp;
57extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp;
58extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp;
59extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp;
60extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp;
61extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp;
62RT_C_DECLS_END
63
64/** List of PDMDEVMODREGR0 structures protected by the loader lock. */
65static RTLISTANCHOR g_PDMDevModList;
66
67
68/**
69 * Pointer to the ring-0 device registrations for VMMR0.
70 */
71static const PDMDEVREGR0 *g_apVMM0DevRegs[] =
72{
73 &g_DeviceAPIC,
74};
75
76/**
77 * Module device registration record for VMMR0.
78 */
79static PDMDEVMODREGR0 g_VBoxDDR0ModDevReg =
80{
81 /* .u32Version = */ PDM_DEVMODREGR0_VERSION,
82 /* .cDevRegs = */ RT_ELEMENTS(g_apVMM0DevRegs),
83 /* .papDevRegs = */ &g_apVMM0DevRegs[0],
84 /* .hMod = */ NULL,
85 /* .ListEntry = */ { NULL, NULL },
86};
87
88
89/*********************************************************************************************************************************
90* Internal Functions *
91*********************************************************************************************************************************/
92static bool pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc);
93
94
95/**
96 * Initializes the global ring-0 PDM data.
97 */
98VMMR0_INT_DECL(void) PDMR0Init(void *hMod)
99{
100 RTListInit(&g_PDMDevModList);
101 g_VBoxDDR0ModDevReg.hMod = hMod;
102 RTListAppend(&g_PDMDevModList, &g_VBoxDDR0ModDevReg.ListEntry);
103}
104
105
106/**
107 * Used by PDMR0CleanupVM to destroy a device instance.
108 *
109 * This is done during VM cleanup so that we're sure there are no active threads
110 * inside the device code.
111 *
112 * @param pGVM The global (ring-0) VM structure.
113 * @param pDevIns The device instance.
114 * @param idxR0Device The device instance handle.
115 */
116static int pdmR0DeviceDestroy(PGVM pGVM, PPDMDEVINSR0 pDevIns, uint32_t idxR0Device)
117{
118 /*
119 * Assert sanity.
120 */
121 Assert(idxR0Device < pGVM->pdmr0.s.cDevInstances);
122 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
123 Assert(pDevIns->u32Version == PDM_DEVINSR0_VERSION);
124 Assert(pDevIns->Internal.s.idxR0Device == idxR0Device);
125
126 /*
127 * Call the final destructor if there is one.
128 */
129 if (pDevIns->pReg->pfnFinalDestruct)
130 pDevIns->pReg->pfnFinalDestruct(pDevIns);
131 pDevIns->u32Version = ~PDM_DEVINSR0_VERSION;
132
133 /*
134 * Remove the device from the instance table.
135 */
136 Assert(pGVM->pdmr0.s.apDevInstances[idxR0Device] == pDevIns);
137 pGVM->pdmr0.s.apDevInstances[idxR0Device] = NULL;
138 if (idxR0Device + 1 == pGVM->pdmr0.s.cDevInstances)
139 pGVM->pdmr0.s.cDevInstances = idxR0Device;
140
141 /*
142 * Free the ring-3 mapping and instance memory.
143 */
144 RTR0MEMOBJ hMemObj = pDevIns->Internal.s.hMapObj;
145 pDevIns->Internal.s.hMapObj = NIL_RTR0MEMOBJ;
146 RTR0MemObjFree(hMemObj, true);
147
148 hMemObj = pDevIns->Internal.s.hMemObj;
149 pDevIns->Internal.s.hMemObj = NIL_RTR0MEMOBJ;
150 RTR0MemObjFree(hMemObj, true);
151
152 return VINF_SUCCESS;
153}
154
155
156/**
157 * Initializes the per-VM data for the PDM.
158 *
159 * This is called from under the GVMM lock, so it only need to initialize the
160 * data so PDMR0CleanupVM and others will work smoothly.
161 *
162 * @param pGVM Pointer to the global VM structure.
163 */
164VMMR0_INT_DECL(void) PDMR0InitPerVMData(PGVM pGVM)
165{
166 AssertCompile(sizeof(pGVM->pdm.s) <= sizeof(pGVM->pdm.padding));
167 AssertCompile(sizeof(pGVM->pdmr0.s) <= sizeof(pGVM->pdmr0.padding));
168
169 pGVM->pdmr0.s.cDevInstances = 0;
170}
171
172
173/**
174 * Cleans up any loose ends before the GVM structure is destroyed.
175 */
176VMMR0_INT_DECL(void) PDMR0CleanupVM(PGVM pGVM)
177{
178 uint32_t i = pGVM->pdmr0.s.cDevInstances;
179 while (i-- > 0)
180 {
181 PPDMDEVINSR0 pDevIns = pGVM->pdmr0.s.apDevInstances[i];
182 if (pDevIns)
183 pdmR0DeviceDestroy(pGVM, pDevIns, i);
184 }
185}
186
187
188/** @name Ring-0 Device Helpers
189 * @{
190 */
191
192/** @interface_method_impl{PDMDEVHLPR0,pfnIoPortSetUpContextEx} */
193static DECLCALLBACK(int) pdmR0DevHlp_IoPortSetUpContextEx(PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts,
194 PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
195 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr,
196 void *pvUser)
197{
198 PDMDEV_ASSERT_DEVINS(pDevIns);
199 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: hIoPorts=%#x pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p pvUser=%p\n",
200 pDevIns->pReg->szName, pDevIns->iInstance, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser));
201 PGVM pGVM = pDevIns->Internal.s.pGVM;
202 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
203 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
204
205 int rc = IOMR0IoPortSetUpContext(pGVM, pDevIns, hIoPorts, pfnOut, pfnIn, pfnOutStr, pfnInStr, pvUser);
206
207 LogFlow(("pdmR0DevHlp_IoPortSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
208 return rc;
209}
210
211
212/** @interface_method_impl{PDMDEVHLPR0,pfnMmioSetUpContextEx} */
213static DECLCALLBACK(int) pdmR0DevHlp_MmioSetUpContextEx(PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, PFNIOMMMIONEWWRITE pfnWrite,
214 PFNIOMMMIONEWREAD pfnRead, PFNIOMMMIONEWFILL pfnFill, void *pvUser)
215{
216 PDMDEV_ASSERT_DEVINS(pDevIns);
217 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: hRegion=%#x pfnWrite=%p pfnRead=%p pfnFill=%p pvUser=%p\n",
218 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, pfnWrite, pfnRead, pfnFill, pvUser));
219 PGVM pGVM = pDevIns->Internal.s.pGVM;
220 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
221 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
222
223 int rc = IOMR0MmioSetUpContext(pGVM, pDevIns, hRegion, pfnWrite, pfnRead, pfnFill, pvUser);
224
225 LogFlow(("pdmR0DevHlp_MmioSetUpContextEx: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
226 return rc;
227}
228
229
230/** @interface_method_impl{PDMDEVHLPR0,pfnMmio2SetUpContext} */
231static DECLCALLBACK(int) pdmR0DevHlp_Mmio2SetUpContext(PPDMDEVINS pDevIns, PGMMMIO2HANDLE hRegion,
232 size_t offSub, size_t cbSub, void **ppvMapping)
233{
234 PDMDEV_ASSERT_DEVINS(pDevIns);
235 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: hRegion=%#x offSub=%#zx cbSub=%#zx ppvMapping=%p\n",
236 pDevIns->pReg->szName, pDevIns->iInstance, hRegion, offSub, cbSub, ppvMapping));
237 *ppvMapping = NULL;
238
239 PGVM pGVM = pDevIns->Internal.s.pGVM;
240 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
241 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
242
243 int rc = PGMR0PhysMMIO2MapKernel(pGVM, pDevIns, hRegion, offSub, cbSub, ppvMapping);
244
245 LogFlow(("pdmR0DevHlp_Mmio2SetUpContext: caller='%s'/%d: returns %Rrc (%p)\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppvMapping));
246 return rc;
247}
248
249
250/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysRead} */
251static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
252 void *pvBuf, size_t cbRead)
253{
254 PDMDEV_ASSERT_DEVINS(pDevIns);
255 if (!pPciDev) /* NULL is an alias for the default PCI device. */
256 pPciDev = pDevIns->apPciDevs[0];
257 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
258 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
259
260#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
261 /*
262 * Just check the busmaster setting here and forward the request to the generic read helper.
263 */
264 if (PCIDevIsBusmaster(pPciDev))
265 { /* likely */ }
266 else
267 {
268 Log(("pdmRCDevHlp_PCIPhysRead: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
269 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
270 memset(pvBuf, 0xff, cbRead);
271 return VERR_PDM_NOT_PCI_BUS_MASTER;
272 }
273#endif
274
275 return pDevIns->pHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
276}
277
278
279/** @interface_method_impl{PDMDEVHLPR0,pfnPCIPhysWrite} */
280static DECLCALLBACK(int) pdmR0DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys,
281 const void *pvBuf, size_t cbWrite)
282{
283 PDMDEV_ASSERT_DEVINS(pDevIns);
284 if (!pPciDev) /* NULL is an alias for the default PCI device. */
285 pPciDev = pDevIns->apPciDevs[0];
286 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
287 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
288
289#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
290 /*
291 * Just check the busmaster setting here and forward the request to the generic read helper.
292 */
293 if (PCIDevIsBusmaster(pPciDev))
294 { /* likely */ }
295 else
296 {
297 Log(("pdmRCDevHlp_PCIPhysWrite: caller=%p/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
298 pDevIns, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
299 return VERR_PDM_NOT_PCI_BUS_MASTER;
300 }
301#endif
302
303 return pDevIns->pHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
304}
305
306
307/** @interface_method_impl{PDMDEVHLPR0,pfnPCISetIrq} */
308static DECLCALLBACK(void) pdmR0DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
309{
310 PDMDEV_ASSERT_DEVINS(pDevIns);
311 if (!pPciDev) /* NULL is an alias for the default PCI device. */
312 pPciDev = pDevIns->apPciDevs[0];
313 AssertReturnVoid(pPciDev);
314 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
315 pDevIns, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
316 PDMPCIDEV_ASSERT_VALID_AND_REGISTERED(pDevIns, pPciDev);
317
318 PGVM pGVM = pDevIns->Internal.s.pGVM;
319 size_t const idxBus = pPciDev->Int.s.idxPdmBus;
320 AssertReturnVoid(idxBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
321 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[idxBus];
322
323 pdmLock(pGVM);
324
325 uint32_t uTagSrc;
326 if (iLevel & PDM_IRQ_LEVEL_HIGH)
327 {
328 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
329 if (iLevel == PDM_IRQ_LEVEL_HIGH)
330 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
331 else
332 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
333 }
334 else
335 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
336
337 if (pPciBusR0->pDevInsR0)
338 {
339 pPciBusR0->pfnSetIrqR0(pPciBusR0->pDevInsR0, pPciDev, iIrq, iLevel, uTagSrc);
340
341 pdmUnlock(pGVM);
342
343 if (iLevel == PDM_IRQ_LEVEL_LOW)
344 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
345 }
346 else
347 {
348 pdmUnlock(pGVM);
349
350 /* queue for ring-3 execution. */
351 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
352 AssertReturnVoid(pTask);
353
354 pTask->enmOp = PDMDEVHLPTASKOP_PCI_SET_IRQ;
355 pTask->pDevInsR3 = PDMDEVINS_2_R3PTR(pDevIns);
356 pTask->u.PciSetIRQ.iIrq = iIrq;
357 pTask->u.PciSetIRQ.iLevel = iLevel;
358 pTask->u.PciSetIRQ.uTagSrc = uTagSrc;
359 pTask->u.PciSetIRQ.pPciDevR3 = MMHyperR0ToR3(pGVM, pPciDev);
360
361 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
362 }
363
364 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
365}
366
367
368/** @interface_method_impl{PDMDEVHLPR0,pfnISASetIrq} */
369static DECLCALLBACK(void) pdmR0DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
370{
371 PDMDEV_ASSERT_DEVINS(pDevIns);
372 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel));
373 PGVM pGVM = pDevIns->Internal.s.pGVM;
374
375 pdmLock(pGVM);
376 uint32_t uTagSrc;
377 if (iLevel & PDM_IRQ_LEVEL_HIGH)
378 {
379 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
380 if (iLevel == PDM_IRQ_LEVEL_HIGH)
381 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
382 else
383 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
384 }
385 else
386 uTagSrc = pDevIns->Internal.s.pIntR3R0->uLastIrqTag;
387
388 bool fRc = pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
389
390 if (iLevel == PDM_IRQ_LEVEL_LOW && fRc)
391 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
392 pdmUnlock(pGVM);
393 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
394}
395
396
397/** @interface_method_impl{PDMDEVHLPR0,pfnIoApicSendMsi} */
398static DECLCALLBACK(void) pdmR0DevHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
399{
400 PDMDEV_ASSERT_DEVINS(pDevIns);
401 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: GCPhys=%RGp uValue=%#x\n", pDevIns, pDevIns->iInstance, GCPhys, uValue));
402 PGVM pGVM = pDevIns->Internal.s.pGVM;
403
404 uint32_t uTagSrc;
405 pDevIns->Internal.s.pIntR3R0->uLastIrqTag = uTagSrc = pdmCalcIrqTag(pGVM, pDevIns->Internal.s.pInsR3R0->idTracing);
406 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pGVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
407
408 if (pGVM->pdm.s.IoApic.pDevInsR0)
409 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
410 else
411 AssertFatalMsgFailed(("Lazy bastards!"));
412
413 LogFlow(("pdmR0DevHlp_IoApicSendMsi: caller=%p/%d: returns void; uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, uTagSrc));
414}
415
416
417/** @interface_method_impl{PDMDEVHLPR0,pfnPhysRead} */
418static DECLCALLBACK(int) pdmR0DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
419{
420 PDMDEV_ASSERT_DEVINS(pDevIns);
421 LogFlow(("pdmR0DevHlp_PhysRead: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
422 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
423
424 VBOXSTRICTRC rcStrict = PGMPhysRead(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
425 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
426
427 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
428 return VBOXSTRICTRC_VAL(rcStrict);
429}
430
431
432/** @interface_method_impl{PDMDEVHLPR0,pfnPhysWrite} */
433static DECLCALLBACK(int) pdmR0DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
434{
435 PDMDEV_ASSERT_DEVINS(pDevIns);
436 LogFlow(("pdmR0DevHlp_PhysWrite: caller=%p/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
437 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
438
439 VBOXSTRICTRC rcStrict = PGMPhysWrite(pDevIns->Internal.s.pGVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
440 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
441
442 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns %Rrc\n", pDevIns, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
443 return VBOXSTRICTRC_VAL(rcStrict);
444}
445
446
447/** @interface_method_impl{PDMDEVHLPR0,pfnA20IsEnabled} */
448static DECLCALLBACK(bool) pdmR0DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
449{
450 PDMDEV_ASSERT_DEVINS(pDevIns);
451 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance));
452
453 bool fEnabled = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pGVM));
454
455 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled));
456 return fEnabled;
457}
458
459
460/** @interface_method_impl{PDMDEVHLPR0,pfnVMState} */
461static DECLCALLBACK(VMSTATE) pdmR0DevHlp_VMState(PPDMDEVINS pDevIns)
462{
463 PDMDEV_ASSERT_DEVINS(pDevIns);
464
465 VMSTATE enmVMState = pDevIns->Internal.s.pGVM->enmVMState;
466
467 LogFlow(("pdmR0DevHlp_VMState: caller=%p/%d: returns %d\n", pDevIns, pDevIns->iInstance, enmVMState));
468 return enmVMState;
469}
470
471
472/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetError} */
473static DECLCALLBACK(int) pdmR0DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
474{
475 PDMDEV_ASSERT_DEVINS(pDevIns);
476 va_list args;
477 va_start(args, pszFormat);
478 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
479 va_end(args);
480 return rc;
481}
482
483
484/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetErrorV} */
485static DECLCALLBACK(int) pdmR0DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
486{
487 PDMDEV_ASSERT_DEVINS(pDevIns);
488 int rc2 = VMSetErrorV(pDevIns->Internal.s.pGVM, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
489 return rc;
490}
491
492
493/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeError} */
494static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
495{
496 PDMDEV_ASSERT_DEVINS(pDevIns);
497 va_list va;
498 va_start(va, pszFormat);
499 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
500 va_end(va);
501 return rc;
502}
503
504
505/** @interface_method_impl{PDMDEVHLPR0,pfnVMSetRuntimeErrorV} */
506static DECLCALLBACK(int) pdmR0DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
507{
508 PDMDEV_ASSERT_DEVINS(pDevIns);
509 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pGVM, fFlags, pszErrorId, pszFormat, va);
510 return rc;
511}
512
513
514
515/** @interface_method_impl{PDMDEVHLPR0,pfnGetVM} */
516static DECLCALLBACK(PVMCC) pdmR0DevHlp_GetVM(PPDMDEVINS pDevIns)
517{
518 PDMDEV_ASSERT_DEVINS(pDevIns);
519 LogFlow(("pdmR0DevHlp_GetVM: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
520 return pDevIns->Internal.s.pGVM;
521}
522
523
524/** @interface_method_impl{PDMDEVHLPR0,pfnGetVMCPU} */
525static DECLCALLBACK(PVMCPUCC) pdmR0DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
526{
527 PDMDEV_ASSERT_DEVINS(pDevIns);
528 LogFlow(("pdmR0DevHlp_GetVMCPU: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
529 return VMMGetCpu(pDevIns->Internal.s.pGVM);
530}
531
532
533/** @interface_method_impl{PDMDEVHLPRC,pfnGetCurrentCpuId} */
534static DECLCALLBACK(VMCPUID) pdmR0DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
535{
536 PDMDEV_ASSERT_DEVINS(pDevIns);
537 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pGVM);
538 LogFlow(("pdmR0DevHlp_GetCurrentCpuId: caller='%p'/%d for CPU %u\n", pDevIns, pDevIns->iInstance, idCpu));
539 return idCpu;
540}
541
542
543/** @interface_method_impl{PDMDEVHLPR0,pfnTimerToPtr} */
544static DECLCALLBACK(PTMTIMERR0) pdmR0DevHlp_TimerToPtr(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
545{
546 PDMDEV_ASSERT_DEVINS(pDevIns);
547 RT_NOREF(pDevIns);
548 return (PTMTIMERR0)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hTimer);
549}
550
551
552/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMicro} */
553static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicroSecs)
554{
555 return TMTimerFromMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicroSecs);
556}
557
558
559/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromMilli} */
560static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromMilli(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliSecs)
561{
562 return TMTimerFromMilli(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliSecs);
563}
564
565
566/** @interface_method_impl{PDMDEVHLPR0,pfnTimerFromNano} */
567static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerFromNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanoSecs)
568{
569 return TMTimerFromNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanoSecs);
570}
571
572/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGet} */
573static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
574{
575 return TMTimerGet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
576}
577
578
579/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetFreq} */
580static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetFreq(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
581{
582 return TMTimerGetFreq(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
583}
584
585
586/** @interface_method_impl{PDMDEVHLPR0,pfnTimerGetNano} */
587static DECLCALLBACK(uint64_t) pdmR0DevHlp_TimerGetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
588{
589 return TMTimerGetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
590}
591
592
593/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsActive} */
594static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsActive(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
595{
596 return TMTimerIsActive(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
597}
598
599
600/** @interface_method_impl{PDMDEVHLPR0,pfnTimerIsLockOwner} */
601static DECLCALLBACK(bool) pdmR0DevHlp_TimerIsLockOwner(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
602{
603 return TMTimerIsLockOwner(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
604}
605
606
607/** @interface_method_impl{PDMDEVHLPR0,pfnTimerLock} */
608static DECLCALLBACK(int) pdmR0DevHlp_TimerLock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, int rcBusy)
609{
610 return TMTimerLock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), rcBusy);
611}
612
613
614/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSet} */
615static DECLCALLBACK(int) pdmR0DevHlp_TimerSet(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t uExpire)
616{
617 return TMTimerSet(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uExpire);
618}
619
620
621/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetFrequencyHint} */
622static DECLCALLBACK(int) pdmR0DevHlp_TimerSetFrequencyHint(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint32_t uHz)
623{
624 return TMTimerSetFrequencyHint(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), uHz);
625}
626
627
628/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMicro} */
629static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMicro(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMicrosToNext)
630{
631 return TMTimerSetMicro(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMicrosToNext);
632}
633
634
635/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetMillies} */
636static DECLCALLBACK(int) pdmR0DevHlp_TimerSetMillies(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cMilliesToNext)
637{
638 return TMTimerSetMillies(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cMilliesToNext);
639}
640
641
642/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetNano} */
643static DECLCALLBACK(int) pdmR0DevHlp_TimerSetNano(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cNanosToNext)
644{
645 return TMTimerSetNano(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cNanosToNext);
646}
647
648
649/** @interface_method_impl{PDMDEVHLPR0,pfnTimerSetRelative} */
650static DECLCALLBACK(int) pdmR0DevHlp_TimerSetRelative(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, uint64_t cTicksToNext, uint64_t *pu64Now)
651{
652 return TMTimerSetRelative(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer), cTicksToNext, pu64Now);
653}
654
655
656/** @interface_method_impl{PDMDEVHLPR0,pfnTimerStop} */
657static DECLCALLBACK(int) pdmR0DevHlp_TimerStop(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
658{
659 return TMTimerStop(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
660}
661
662
663/** @interface_method_impl{PDMDEVHLPR0,pfnTimerUnlock} */
664static DECLCALLBACK(void) pdmR0DevHlp_TimerUnlock(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer)
665{
666 TMTimerUnlock(pdmR0DevHlp_TimerToPtr(pDevIns, hTimer));
667}
668
669
670/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGet} */
671static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
672{
673 PDMDEV_ASSERT_DEVINS(pDevIns);
674 LogFlow(("pdmR0DevHlp_TMTimeVirtGet: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
675 return TMVirtualGet(pDevIns->Internal.s.pGVM);
676}
677
678
679/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetFreq} */
680static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
681{
682 PDMDEV_ASSERT_DEVINS(pDevIns);
683 LogFlow(("pdmR0DevHlp_TMTimeVirtGetFreq: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
684 return TMVirtualGetFreq(pDevIns->Internal.s.pGVM);
685}
686
687
688/** @interface_method_impl{PDMDEVHLPR0,pfnTMTimeVirtGetNano} */
689static DECLCALLBACK(uint64_t) pdmR0DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
690{
691 PDMDEV_ASSERT_DEVINS(pDevIns);
692 LogFlow(("pdmR0DevHlp_TMTimeVirtGetNano: caller='%p'/%d\n", pDevIns, pDevIns->iInstance));
693 return TMVirtualToNano(pDevIns->Internal.s.pGVM, TMVirtualGet(pDevIns->Internal.s.pGVM));
694}
695
696
697/** @interface_method_impl{PDMDEVHLPR0,pfnQueueToPtr} */
698static DECLCALLBACK(PPDMQUEUE) pdmR0DevHlp_QueueToPtr(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
699{
700 PDMDEV_ASSERT_DEVINS(pDevIns);
701 RT_NOREF(pDevIns);
702 return (PPDMQUEUE)MMHyperR3ToCC(pDevIns->Internal.s.pGVM, hQueue);
703}
704
705
706/** @interface_method_impl{PDMDEVHLPR0,pfnQueueAlloc} */
707static DECLCALLBACK(PPDMQUEUEITEMCORE) pdmR0DevHlp_QueueAlloc(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
708{
709 return PDMQueueAlloc(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
710}
711
712
713/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsert} */
714static DECLCALLBACK(void) pdmR0DevHlp_QueueInsert(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem)
715{
716 return PDMQueueInsert(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem);
717}
718
719
720/** @interface_method_impl{PDMDEVHLPR0,pfnQueueInsertEx} */
721static DECLCALLBACK(void) pdmR0DevHlp_QueueInsertEx(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue, PPDMQUEUEITEMCORE pItem,
722 uint64_t cNanoMaxDelay)
723{
724 return PDMQueueInsertEx(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue), pItem, cNanoMaxDelay);
725}
726
727
728/** @interface_method_impl{PDMDEVHLPR0,pfnQueueFlushIfNecessary} */
729static DECLCALLBACK(bool) pdmR0DevHlp_QueueFlushIfNecessary(PPDMDEVINS pDevIns, PDMQUEUEHANDLE hQueue)
730{
731 return PDMQueueFlushIfNecessary(pdmR0DevHlp_QueueToPtr(pDevIns, hQueue));
732}
733
734
735/** @interface_method_impl{PDMDEVHLPR0,pfnTaskTrigger} */
736static DECLCALLBACK(int) pdmR0DevHlp_TaskTrigger(PPDMDEVINS pDevIns, PDMTASKHANDLE hTask)
737{
738 PDMDEV_ASSERT_DEVINS(pDevIns);
739 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: hTask=%RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, hTask));
740
741 int rc = PDMTaskTrigger(pDevIns->Internal.s.pGVM, PDMTASKTYPE_DEV, pDevIns->pDevInsForR3, hTask);
742
743 LogFlow(("pdmR0DevHlp_TaskTrigger: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
744 return rc;
745}
746
747
748/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventSignal} */
749static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventSignal(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent)
750{
751 PDMDEV_ASSERT_DEVINS(pDevIns);
752 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: hEvent=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEvent));
753
754 int rc = SUPSemEventSignal(pDevIns->Internal.s.pGVM->pSession, hEvent);
755
756 LogFlow(("pdmR0DevHlp_SUPSemEventSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
757 return rc;
758}
759
760
761/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNoResume} */
762static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint32_t cMillies)
763{
764 PDMDEV_ASSERT_DEVINS(pDevIns);
765 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: hEvent=%p cNsTimeout=%RU32\n",
766 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cMillies));
767
768 int rc = SUPSemEventWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEvent, cMillies);
769
770 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
771 return rc;
772}
773
774
775/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsAbsIntr} */
776static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t uNsTimeout)
777{
778 PDMDEV_ASSERT_DEVINS(pDevIns);
779 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: hEvent=%p uNsTimeout=%RU64\n",
780 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, uNsTimeout));
781
782 int rc = SUPSemEventWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, uNsTimeout);
783
784 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
785 return rc;
786}
787
788
789/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventWaitNsRelIntr} */
790static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENT hEvent, uint64_t cNsTimeout)
791{
792 PDMDEV_ASSERT_DEVINS(pDevIns);
793 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: hEvent=%p cNsTimeout=%RU64\n",
794 pDevIns->pReg->szName, pDevIns->iInstance, hEvent, cNsTimeout));
795
796 int rc = SUPSemEventWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEvent, cNsTimeout);
797
798 LogFlow(("pdmR0DevHlp_SUPSemEventWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
799 return rc;
800}
801
802
803/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventGetResolution} */
804static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventGetResolution(PPDMDEVINS pDevIns)
805{
806 PDMDEV_ASSERT_DEVINS(pDevIns);
807 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
808
809 uint32_t cNsResolution = SUPSemEventGetResolution(pDevIns->Internal.s.pGVM->pSession);
810
811 LogFlow(("pdmR0DevHlp_SUPSemEventGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
812 return cNsResolution;
813}
814
815
816/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiSignal} */
817static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiSignal(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
818{
819 PDMDEV_ASSERT_DEVINS(pDevIns);
820 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
821
822 int rc = SUPSemEventMultiSignal(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
823
824 LogFlow(("pdmR0DevHlp_SUPSemEventMultiSignal: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
825 return rc;
826}
827
828
829/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiReset} */
830static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiReset(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti)
831{
832 PDMDEV_ASSERT_DEVINS(pDevIns);
833 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: hEventMulti=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti));
834
835 int rc = SUPSemEventMultiReset(pDevIns->Internal.s.pGVM->pSession, hEventMulti);
836
837 LogFlow(("pdmR0DevHlp_SUPSemEventMultiReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
838 return rc;
839}
840
841
842/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNoResume} */
843static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNoResume(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
844 uint32_t cMillies)
845{
846 PDMDEV_ASSERT_DEVINS(pDevIns);
847 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: hEventMulti=%p cMillies=%RU32\n",
848 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cMillies));
849
850 int rc = SUPSemEventMultiWaitNoResume(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cMillies);
851
852 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNoResume: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
853 return rc;
854}
855
856
857/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsAbsIntr} */
858static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
859 uint64_t uNsTimeout)
860{
861 PDMDEV_ASSERT_DEVINS(pDevIns);
862 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: hEventMulti=%p uNsTimeout=%RU64\n",
863 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, uNsTimeout));
864
865 int rc = SUPSemEventMultiWaitNsAbsIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, uNsTimeout);
866
867 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
868 return rc;
869}
870
871
872/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiWaitNsRelIntr} */
873static DECLCALLBACK(int) pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr(PPDMDEVINS pDevIns, SUPSEMEVENTMULTI hEventMulti,
874 uint64_t cNsTimeout)
875{
876 PDMDEV_ASSERT_DEVINS(pDevIns);
877 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: hEventMulti=%p cNsTimeout=%RU64\n",
878 pDevIns->pReg->szName, pDevIns->iInstance, hEventMulti, cNsTimeout));
879
880 int rc = SUPSemEventMultiWaitNsRelIntr(pDevIns->Internal.s.pGVM->pSession, hEventMulti, cNsTimeout);
881
882 LogFlow(("pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
883 return rc;
884}
885
886
887/** @interface_method_impl{PDMDEVHLPR0,pfnSUPSemEventMultiGetResolution} */
888static DECLCALLBACK(uint32_t) pdmR0DevHlp_SUPSemEventMultiGetResolution(PPDMDEVINS pDevIns)
889{
890 PDMDEV_ASSERT_DEVINS(pDevIns);
891 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
892
893 uint32_t cNsResolution = SUPSemEventMultiGetResolution(pDevIns->Internal.s.pGVM->pSession);
894
895 LogFlow(("pdmR0DevHlp_SUPSemEventMultiGetResolution: caller='%s'/%d: returns %u\n", pDevIns->pReg->szName, pDevIns->iInstance, cNsResolution));
896 return cNsResolution;
897}
898
899
900/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetNop} */
901static DECLCALLBACK(PPDMCRITSECT) pdmR0DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
902{
903 PDMDEV_ASSERT_DEVINS(pDevIns);
904 PGVM pGVM = pDevIns->Internal.s.pGVM;
905
906 PPDMCRITSECT pCritSect = &pGVM->pdm.s.NopCritSect;
907 LogFlow(("pdmR0DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
908 return pCritSect;
909}
910
911
912/** @interface_method_impl{PDMDEVHLPR0,pfnSetDeviceCritSect} */
913static DECLCALLBACK(int) pdmR0DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
914{
915 /*
916 * Validate input.
917 *
918 * Note! We only allow the automatically created default critical section
919 * to be replaced by this API.
920 */
921 PDMDEV_ASSERT_DEVINS(pDevIns);
922 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
923 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
924 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
925 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
926 PGVM pGVM = pDevIns->Internal.s.pGVM;
927 AssertReturn(pCritSect->s.pVMR0 == pGVM, VERR_INVALID_PARAMETER);
928
929 VM_ASSERT_EMT(pGVM);
930 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
931
932 /*
933 * Check that ring-3 has already done this, then effect the change.
934 */
935 AssertReturn(pDevIns->pDevInsForR3R0->Internal.s.fIntFlags & PDMDEVINSINT_FLAGS_CHANGED_CRITSECT, VERR_WRONG_ORDER);
936 pDevIns->pCritSectRoR0 = pCritSect;
937
938 LogFlow(("pdmR0DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
939 return VINF_SUCCESS;
940}
941
942
943/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnter} */
944static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy)
945{
946 PDMDEV_ASSERT_DEVINS(pDevIns);
947 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
948 return PDMCritSectEnter(pCritSect, rcBusy);
949}
950
951
952/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectEnterDebug} */
953static DECLCALLBACK(int) pdmR0DevHlp_CritSectEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, int rcBusy, RTHCUINTPTR uId, RT_SRC_POS_DECL)
954{
955 PDMDEV_ASSERT_DEVINS(pDevIns);
956 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
957 return PDMCritSectEnterDebug(pCritSect, rcBusy, uId, RT_SRC_POS_ARGS);
958}
959
960
961/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnter} */
962static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnter(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
963{
964 PDMDEV_ASSERT_DEVINS(pDevIns);
965 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
966 return PDMCritSectTryEnter(pCritSect);
967}
968
969
970/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectTryEnterDebug} */
971static DECLCALLBACK(int) pdmR0DevHlp_CritSectTryEnterDebug(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RTHCUINTPTR uId, RT_SRC_POS_DECL)
972{
973 PDMDEV_ASSERT_DEVINS(pDevIns);
974 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
975 return PDMCritSectTryEnterDebug(pCritSect, uId, RT_SRC_POS_ARGS);
976}
977
978
979/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectLeave} */
980static DECLCALLBACK(int) pdmR0DevHlp_CritSectLeave(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
981{
982 PDMDEV_ASSERT_DEVINS(pDevIns);
983 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
984 return PDMCritSectLeave(pCritSect);
985}
986
987
988/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsOwner} */
989static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsOwner(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
990{
991 PDMDEV_ASSERT_DEVINS(pDevIns);
992 RT_NOREF(pDevIns); /** @todo pass pDevIns->Internal.s.pGVM to the crit sect code. */
993 return PDMCritSectIsOwner(pCritSect);
994}
995
996
997/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectIsInitialized} */
998static DECLCALLBACK(bool) pdmR0DevHlp_CritSectIsInitialized(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
999{
1000 PDMDEV_ASSERT_DEVINS(pDevIns);
1001 RT_NOREF(pDevIns);
1002 return PDMCritSectIsInitialized(pCritSect);
1003}
1004
1005
1006/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectHasWaiters} */
1007static DECLCALLBACK(bool) pdmR0DevHlp_CritSectHasWaiters(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
1008{
1009 PDMDEV_ASSERT_DEVINS(pDevIns);
1010 RT_NOREF(pDevIns);
1011 return PDMCritSectHasWaiters(pCritSect);
1012}
1013
1014
1015/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectGetRecursion} */
1016static DECLCALLBACK(uint32_t) pdmR0DevHlp_CritSectGetRecursion(PPDMDEVINS pDevIns, PCPDMCRITSECT pCritSect)
1017{
1018 PDMDEV_ASSERT_DEVINS(pDevIns);
1019 RT_NOREF(pDevIns);
1020 return PDMCritSectGetRecursion(pCritSect);
1021}
1022
1023
1024/** @interface_method_impl{PDMDEVHLPR0,pfnCritSectScheduleExitEvent} */
1025static DECLCALLBACK(int) pdmR0DevHlp_CritSectScheduleExitEvent(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect,
1026 SUPSEMEVENT hEventToSignal)
1027{
1028 PDMDEV_ASSERT_DEVINS(pDevIns);
1029 RT_NOREF(pDevIns);
1030 return PDMHCCritSectScheduleExitEvent(pCritSect, hEventToSignal);
1031}
1032
1033
1034/** @interface_method_impl{PDMDEVHLPR0,pfnDBGFTraceBuf} */
1035static DECLCALLBACK(RTTRACEBUF) pdmR0DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1036{
1037 PDMDEV_ASSERT_DEVINS(pDevIns);
1038 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pGVM->hTraceBufR0;
1039 LogFlow(("pdmR0DevHlp_DBGFTraceBuf: caller='%p'/%d: returns %p\n", pDevIns, pDevIns->iInstance, hTraceBuf));
1040 return hTraceBuf;
1041}
1042
1043
1044/** @interface_method_impl{PDMDEVHLPR0,pfnPCIBusSetUpContext} */
1045static DECLCALLBACK(int) pdmR0DevHlp_PCIBusSetUpContext(PPDMDEVINS pDevIns, PPDMPCIBUSREGR0 pPciBusReg, PCPDMPCIHLPR0 *ppPciHlp)
1046{
1047 PDMDEV_ASSERT_DEVINS(pDevIns);
1048 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: pPciBusReg=%p{.u32Version=%#x, .iBus=%#u, .pfnSetIrq=%p, u32EnvVersion=%#x} ppPciHlp=%p\n",
1049 pDevIns, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->iBus, pPciBusReg->pfnSetIrq,
1050 pPciBusReg->u32EndVersion, ppPciHlp));
1051 PGVM pGVM = pDevIns->Internal.s.pGVM;
1052
1053 /*
1054 * Validate input.
1055 */
1056 AssertPtrReturn(pPciBusReg, VERR_INVALID_POINTER);
1057 AssertLogRelMsgReturn(pPciBusReg->u32Version == PDM_PCIBUSREGCC_VERSION,
1058 ("%#x vs %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1059 AssertPtrReturn(pPciBusReg->pfnSetIrq, VERR_INVALID_POINTER);
1060 AssertLogRelMsgReturn(pPciBusReg->u32EndVersion == PDM_PCIBUSREGCC_VERSION,
1061 ("%#x vs %#x\n", pPciBusReg->u32EndVersion, PDM_PCIBUSREGCC_VERSION), VERR_VERSION_MISMATCH);
1062
1063 AssertPtrReturn(ppPciHlp, VERR_INVALID_POINTER);
1064
1065 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1066 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1067
1068 /* Check the shared bus data (registered earlier from ring-3): */
1069 uint32_t iBus = pPciBusReg->iBus;
1070 ASMCompilerBarrier();
1071 AssertLogRelMsgReturn(iBus < RT_ELEMENTS(pGVM->pdm.s.aPciBuses), ("iBus=%#x\n", iBus), VERR_OUT_OF_RANGE);
1072 PPDMPCIBUS pPciBusShared = &pGVM->pdm.s.aPciBuses[iBus];
1073 AssertLogRelMsgReturn(pPciBusShared->iBus == iBus, ("%u vs %u\n", pPciBusShared->iBus, iBus), VERR_INVALID_PARAMETER);
1074 AssertLogRelMsgReturn(pPciBusShared->pDevInsR3 == pDevIns->pDevInsForR3,
1075 ("%p vs %p (iBus=%u)\n", pPciBusShared->pDevInsR3, pDevIns->pDevInsForR3, iBus), VERR_NOT_OWNER);
1076
1077 /* Check that the bus isn't already registered in ring-0: */
1078 AssertCompile(RT_ELEMENTS(pGVM->pdm.s.aPciBuses) == RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses));
1079 PPDMPCIBUSR0 pPciBusR0 = &pGVM->pdmr0.s.aPciBuses[iBus];
1080 AssertLogRelMsgReturn(pPciBusR0->pDevInsR0 == NULL,
1081 ("%p (caller pDevIns=%p, iBus=%u)\n", pPciBusR0->pDevInsR0, pDevIns, iBus),
1082 VERR_ALREADY_EXISTS);
1083
1084 /*
1085 * Do the registering.
1086 */
1087 pPciBusR0->iBus = iBus;
1088 pPciBusR0->uPadding0 = 0xbeefbeef;
1089 pPciBusR0->pfnSetIrqR0 = pPciBusReg->pfnSetIrq;
1090 pPciBusR0->pDevInsR0 = pDevIns;
1091
1092 *ppPciHlp = &g_pdmR0PciHlp;
1093
1094 LogFlow(("pdmR0DevHlp_PCIBusSetUpContext: caller='%p'/%d: returns VINF_SUCCESS\n", pDevIns, pDevIns->iInstance));
1095 return VINF_SUCCESS;
1096}
1097
1098
1099/** @interface_method_impl{PDMDEVHLPR0,pfnPICSetUpContext} */
1100static DECLCALLBACK(int) pdmR0DevHlp_PICSetUpContext(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLP *ppPicHlp)
1101{
1102 PDMDEV_ASSERT_DEVINS(pDevIns);
1103 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrq=%p, .pfnGetInterrupt=%p, .u32TheEnd=%#x } ppPicHlp=%p\n",
1104 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrq, pPicReg->pfnGetInterrupt, pPicReg->u32TheEnd, ppPicHlp));
1105 PGVM pGVM = pDevIns->Internal.s.pGVM;
1106
1107 /*
1108 * Validate input.
1109 */
1110 AssertMsgReturn(pPicReg->u32Version == PDM_PICREG_VERSION,
1111 ("%s/%d: u32Version=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32Version, PDM_PICREG_VERSION),
1112 VERR_INVALID_PARAMETER);
1113 AssertPtrReturn(pPicReg->pfnSetIrq, VERR_INVALID_POINTER);
1114 AssertPtrReturn(pPicReg->pfnGetInterrupt, VERR_INVALID_POINTER);
1115 AssertMsgReturn(pPicReg->u32TheEnd == PDM_PICREG_VERSION,
1116 ("%s/%d: u32TheEnd=%#x expected %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, pPicReg->u32TheEnd, PDM_PICREG_VERSION),
1117 VERR_INVALID_PARAMETER);
1118 AssertPtrReturn(ppPicHlp, VERR_INVALID_POINTER);
1119
1120 VM_ASSERT_STATE_RETURN(pGVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1121 VM_ASSERT_EMT0_RETURN(pGVM, VERR_VM_THREAD_NOT_EMT);
1122
1123 /* Check that it's the same device as made the ring-3 registrations: */
1124 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR3 == pDevIns->pDevInsForR3,
1125 ("%p vs %p\n", pGVM->pdm.s.Pic.pDevInsR3, pDevIns->pDevInsForR3), VERR_NOT_OWNER);
1126
1127 /* Check that it isn't already registered in ring-0: */
1128 AssertLogRelMsgReturn(pGVM->pdm.s.Pic.pDevInsR0 == NULL, ("%p (caller pDevIns=%p)\n", pGVM->pdm.s.Pic.pDevInsR0, pDevIns),
1129 VERR_ALREADY_EXISTS);
1130
1131 /*
1132 * Take down the callbacks and instance.
1133 */
1134 pGVM->pdm.s.Pic.pDevInsR0 = pDevIns;
1135 pGVM->pdm.s.Pic.pfnSetIrqR0 = pPicReg->pfnSetIrq;
1136 pGVM->pdm.s.Pic.pfnGetInterruptR0 = pPicReg->pfnGetInterrupt;
1137 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
1138
1139 /* set the helper pointer and return. */
1140 *ppPicHlp = &g_pdmR0PicHlp;
1141 LogFlow(("pdmR0DevHlp_PICSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
1142 return VINF_SUCCESS;
1143}
1144
1145
1146/**
1147 * The Ring-0 Device Helper Callbacks.
1148 */
1149extern DECLEXPORT(const PDMDEVHLPR0) g_pdmR0DevHlp =
1150{
1151 PDM_DEVHLPR0_VERSION,
1152 pdmR0DevHlp_IoPortSetUpContextEx,
1153 pdmR0DevHlp_MmioSetUpContextEx,
1154 pdmR0DevHlp_Mmio2SetUpContext,
1155 pdmR0DevHlp_PCIPhysRead,
1156 pdmR0DevHlp_PCIPhysWrite,
1157 pdmR0DevHlp_PCISetIrq,
1158 pdmR0DevHlp_ISASetIrq,
1159 pdmR0DevHlp_IoApicSendMsi,
1160 pdmR0DevHlp_PhysRead,
1161 pdmR0DevHlp_PhysWrite,
1162 pdmR0DevHlp_A20IsEnabled,
1163 pdmR0DevHlp_VMState,
1164 pdmR0DevHlp_VMSetError,
1165 pdmR0DevHlp_VMSetErrorV,
1166 pdmR0DevHlp_VMSetRuntimeError,
1167 pdmR0DevHlp_VMSetRuntimeErrorV,
1168 pdmR0DevHlp_GetVM,
1169 pdmR0DevHlp_GetVMCPU,
1170 pdmR0DevHlp_GetCurrentCpuId,
1171 pdmR0DevHlp_TimerToPtr,
1172 pdmR0DevHlp_TimerFromMicro,
1173 pdmR0DevHlp_TimerFromMilli,
1174 pdmR0DevHlp_TimerFromNano,
1175 pdmR0DevHlp_TimerGet,
1176 pdmR0DevHlp_TimerGetFreq,
1177 pdmR0DevHlp_TimerGetNano,
1178 pdmR0DevHlp_TimerIsActive,
1179 pdmR0DevHlp_TimerIsLockOwner,
1180 pdmR0DevHlp_TimerLock,
1181 pdmR0DevHlp_TimerSet,
1182 pdmR0DevHlp_TimerSetFrequencyHint,
1183 pdmR0DevHlp_TimerSetMicro,
1184 pdmR0DevHlp_TimerSetMillies,
1185 pdmR0DevHlp_TimerSetNano,
1186 pdmR0DevHlp_TimerSetRelative,
1187 pdmR0DevHlp_TimerStop,
1188 pdmR0DevHlp_TimerUnlock,
1189 pdmR0DevHlp_TMTimeVirtGet,
1190 pdmR0DevHlp_TMTimeVirtGetFreq,
1191 pdmR0DevHlp_TMTimeVirtGetNano,
1192 pdmR0DevHlp_QueueToPtr,
1193 pdmR0DevHlp_QueueAlloc,
1194 pdmR0DevHlp_QueueInsert,
1195 pdmR0DevHlp_QueueInsertEx,
1196 pdmR0DevHlp_QueueFlushIfNecessary,
1197 pdmR0DevHlp_TaskTrigger,
1198 pdmR0DevHlp_SUPSemEventSignal,
1199 pdmR0DevHlp_SUPSemEventWaitNoResume,
1200 pdmR0DevHlp_SUPSemEventWaitNsAbsIntr,
1201 pdmR0DevHlp_SUPSemEventWaitNsRelIntr,
1202 pdmR0DevHlp_SUPSemEventGetResolution,
1203 pdmR0DevHlp_SUPSemEventMultiSignal,
1204 pdmR0DevHlp_SUPSemEventMultiReset,
1205 pdmR0DevHlp_SUPSemEventMultiWaitNoResume,
1206 pdmR0DevHlp_SUPSemEventMultiWaitNsAbsIntr,
1207 pdmR0DevHlp_SUPSemEventMultiWaitNsRelIntr,
1208 pdmR0DevHlp_SUPSemEventMultiGetResolution,
1209 pdmR0DevHlp_CritSectGetNop,
1210 pdmR0DevHlp_SetDeviceCritSect,
1211 pdmR0DevHlp_CritSectEnter,
1212 pdmR0DevHlp_CritSectEnterDebug,
1213 pdmR0DevHlp_CritSectTryEnter,
1214 pdmR0DevHlp_CritSectTryEnterDebug,
1215 pdmR0DevHlp_CritSectLeave,
1216 pdmR0DevHlp_CritSectIsOwner,
1217 pdmR0DevHlp_CritSectIsInitialized,
1218 pdmR0DevHlp_CritSectHasWaiters,
1219 pdmR0DevHlp_CritSectGetRecursion,
1220 pdmR0DevHlp_CritSectScheduleExitEvent,
1221 pdmR0DevHlp_DBGFTraceBuf,
1222 pdmR0DevHlp_PCIBusSetUpContext,
1223 pdmR0DevHlp_PICSetUpContext,
1224 NULL /*pfnReserved1*/,
1225 NULL /*pfnReserved2*/,
1226 NULL /*pfnReserved3*/,
1227 NULL /*pfnReserved4*/,
1228 NULL /*pfnReserved5*/,
1229 NULL /*pfnReserved6*/,
1230 NULL /*pfnReserved7*/,
1231 NULL /*pfnReserved8*/,
1232 NULL /*pfnReserved9*/,
1233 NULL /*pfnReserved10*/,
1234 PDM_DEVHLPR0_VERSION
1235};
1236
1237/** @} */
1238
1239
1240
1241
1242/** @name PIC Ring-0 Helpers
1243 * @{
1244 */
1245
1246/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
1247static DECLCALLBACK(void) pdmR0PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
1248{
1249 PDMDEV_ASSERT_DEVINS(pDevIns);
1250 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1251 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1252 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1253 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1254}
1255
1256
1257/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
1258static DECLCALLBACK(void) pdmR0PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
1259{
1260 PDMDEV_ASSERT_DEVINS(pDevIns);
1261 PGVM pGVM = (PGVM)pDevIns->Internal.s.pGVM;
1262 PVMCPUCC pVCpu = &pGVM->aCpus[0]; /* for PIC we always deliver to CPU 0, MP use APIC */
1263 /** @todo r=ramshankar: Propagating rcRZ and make all callers handle it? */
1264 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
1265}
1266
1267
1268/** @interface_method_impl{PDMPICHLP,pfnLock} */
1269static DECLCALLBACK(int) pdmR0PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1270{
1271 PDMDEV_ASSERT_DEVINS(pDevIns);
1272 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1273}
1274
1275
1276/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
1277static DECLCALLBACK(void) pdmR0PicHlp_Unlock(PPDMDEVINS pDevIns)
1278{
1279 PDMDEV_ASSERT_DEVINS(pDevIns);
1280 pdmUnlock(pDevIns->Internal.s.pGVM);
1281}
1282
1283
1284/**
1285 * The Ring-0 PIC Helper Callbacks.
1286 */
1287extern DECLEXPORT(const PDMPICHLP) g_pdmR0PicHlp =
1288{
1289 PDM_PICHLP_VERSION,
1290 pdmR0PicHlp_SetInterruptFF,
1291 pdmR0PicHlp_ClearInterruptFF,
1292 pdmR0PicHlp_Lock,
1293 pdmR0PicHlp_Unlock,
1294 PDM_PICHLP_VERSION
1295};
1296
1297/** @} */
1298
1299
1300/** @name I/O APIC Ring-0 Helpers
1301 * @{
1302 */
1303
1304/** @interface_method_impl{PDMIOAPICHLPR0,pfnApicBusDeliver} */
1305static DECLCALLBACK(int) pdmR0IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
1306 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
1307 uint8_t u8TriggerMode, uint32_t uTagSrc)
1308{
1309 PDMDEV_ASSERT_DEVINS(pDevIns);
1310 PGVM pGVM = pDevIns->Internal.s.pGVM;
1311 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
1312 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
1313 return APICBusDeliver(pGVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
1314}
1315
1316
1317/** @interface_method_impl{PDMIOAPICHLPR0,pfnLock} */
1318static DECLCALLBACK(int) pdmR0IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
1319{
1320 PDMDEV_ASSERT_DEVINS(pDevIns);
1321 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1322}
1323
1324
1325/** @interface_method_impl{PDMIOAPICHLPR0,pfnUnlock} */
1326static DECLCALLBACK(void) pdmR0IoApicHlp_Unlock(PPDMDEVINS pDevIns)
1327{
1328 PDMDEV_ASSERT_DEVINS(pDevIns);
1329 pdmUnlock(pDevIns->Internal.s.pGVM);
1330}
1331
1332
1333/**
1334 * The Ring-0 I/O APIC Helper Callbacks.
1335 */
1336extern DECLEXPORT(const PDMIOAPICHLPR0) g_pdmR0IoApicHlp =
1337{
1338 PDM_IOAPICHLPR0_VERSION,
1339 pdmR0IoApicHlp_ApicBusDeliver,
1340 pdmR0IoApicHlp_Lock,
1341 pdmR0IoApicHlp_Unlock,
1342 PDM_IOAPICHLPR0_VERSION
1343};
1344
1345/** @} */
1346
1347
1348
1349
1350/** @name PCI Bus Ring-0 Helpers
1351 * @{
1352 */
1353
1354/** @interface_method_impl{PDMPCIHLPR0,pfnIsaSetIrq} */
1355static DECLCALLBACK(void) pdmR0PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1356{
1357 PDMDEV_ASSERT_DEVINS(pDevIns);
1358 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1359 PGVM pGVM = pDevIns->Internal.s.pGVM;
1360
1361 pdmLock(pGVM);
1362 pdmR0IsaSetIrq(pGVM, iIrq, iLevel, uTagSrc);
1363 pdmUnlock(pGVM);
1364}
1365
1366
1367/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSetIrq} */
1368static DECLCALLBACK(void) pdmR0PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
1369{
1370 PDMDEV_ASSERT_DEVINS(pDevIns);
1371 Log4(("pdmR0PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
1372 PGVM pGVM = pDevIns->Internal.s.pGVM;
1373
1374 if (pGVM->pdm.s.IoApic.pDevInsR0)
1375 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
1376 else if (pGVM->pdm.s.IoApic.pDevInsR3)
1377 {
1378 /* queue for ring-3 execution. */
1379 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1380 if (pTask)
1381 {
1382 pTask->enmOp = PDMDEVHLPTASKOP_IOAPIC_SET_IRQ;
1383 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1384 pTask->u.IoApicSetIRQ.iIrq = iIrq;
1385 pTask->u.IoApicSetIRQ.iLevel = iLevel;
1386 pTask->u.IoApicSetIRQ.uTagSrc = uTagSrc;
1387
1388 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1389 }
1390 else
1391 AssertMsgFailed(("We're out of devhlp queue items!!!\n"));
1392 }
1393}
1394
1395
1396/** @interface_method_impl{PDMPCIHLPR0,pfnIoApicSendMsi} */
1397static DECLCALLBACK(void) pdmR0PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
1398{
1399 PDMDEV_ASSERT_DEVINS(pDevIns);
1400 Log4(("pdmR0PciHlp_IoApicSendMsi: GCPhys=%p uValue=%d uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
1401 PGVM pGVM = pDevIns->Internal.s.pGVM;
1402 if (pGVM->pdm.s.IoApic.pDevInsR0)
1403 pGVM->pdm.s.IoApic.pfnSendMsiR0(pGVM->pdm.s.IoApic.pDevInsR0, GCPhys, uValue, uTagSrc);
1404 else
1405 AssertFatalMsgFailed(("Lazy bastards!"));
1406}
1407
1408
1409/** @interface_method_impl{PDMPCIHLPR0,pfnLock} */
1410static DECLCALLBACK(int) pdmR0PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
1411{
1412 PDMDEV_ASSERT_DEVINS(pDevIns);
1413 return pdmLockEx(pDevIns->Internal.s.pGVM, rc);
1414}
1415
1416
1417/** @interface_method_impl{PDMPCIHLPR0,pfnUnlock} */
1418static DECLCALLBACK(void) pdmR0PciHlp_Unlock(PPDMDEVINS pDevIns)
1419{
1420 PDMDEV_ASSERT_DEVINS(pDevIns);
1421 pdmUnlock(pDevIns->Internal.s.pGVM);
1422}
1423
1424
1425/** @interface_method_impl{PDMPCIHLPR0,pfnGetBusByNo} */
1426static DECLCALLBACK(PPDMDEVINS) pdmR0PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
1427{
1428 PDMDEV_ASSERT_DEVINS(pDevIns);
1429 PGVM pGVM = pDevIns->Internal.s.pGVM;
1430 AssertReturn(idxPdmBus < RT_ELEMENTS(pGVM->pdmr0.s.aPciBuses), NULL);
1431 PPDMDEVINS pRetDevIns = pGVM->pdmr0.s.aPciBuses[idxPdmBus].pDevInsR0;
1432 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
1433 return pRetDevIns;
1434}
1435
1436
1437/**
1438 * The Ring-0 PCI Bus Helper Callbacks.
1439 */
1440extern DECLEXPORT(const PDMPCIHLPR0) g_pdmR0PciHlp =
1441{
1442 PDM_PCIHLPR0_VERSION,
1443 pdmR0PciHlp_IsaSetIrq,
1444 pdmR0PciHlp_IoApicSetIrq,
1445 pdmR0PciHlp_IoApicSendMsi,
1446 pdmR0PciHlp_Lock,
1447 pdmR0PciHlp_Unlock,
1448 pdmR0PciHlp_GetBusByNo,
1449 PDM_PCIHLPR0_VERSION, /* the end */
1450};
1451
1452/** @} */
1453
1454
1455
1456
1457/** @name HPET Ring-0 Helpers
1458 * @{
1459 */
1460/* none */
1461
1462/**
1463 * The Ring-0 HPET Helper Callbacks.
1464 */
1465extern DECLEXPORT(const PDMHPETHLPR0) g_pdmR0HpetHlp =
1466{
1467 PDM_HPETHLPR0_VERSION,
1468 PDM_HPETHLPR0_VERSION, /* the end */
1469};
1470
1471/** @} */
1472
1473
1474/** @name Raw PCI Ring-0 Helpers
1475 * @{
1476 */
1477/* none */
1478
1479/**
1480 * The Ring-0 PCI raw Helper Callbacks.
1481 */
1482extern DECLEXPORT(const PDMPCIRAWHLPR0) g_pdmR0PciRawHlp =
1483{
1484 PDM_PCIRAWHLPR0_VERSION,
1485 PDM_PCIRAWHLPR0_VERSION, /* the end */
1486};
1487
1488/** @} */
1489
1490
1491/** @name Ring-0 Context Driver Helpers
1492 * @{
1493 */
1494
1495/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetError} */
1496static DECLCALLBACK(int) pdmR0DrvHlp_VMSetError(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
1497{
1498 PDMDRV_ASSERT_DRVINS(pDrvIns);
1499 va_list args;
1500 va_start(args, pszFormat);
1501 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
1502 va_end(args);
1503 return rc;
1504}
1505
1506
1507/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetErrorV} */
1508static DECLCALLBACK(int) pdmR0DrvHlp_VMSetErrorV(PPDMDRVINS pDrvIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
1509{
1510 PDMDRV_ASSERT_DRVINS(pDrvIns);
1511 int rc2 = VMSetErrorV(pDrvIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
1512 return rc;
1513}
1514
1515
1516/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeError} */
1517static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeError(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
1518 const char *pszFormat, ...)
1519{
1520 PDMDRV_ASSERT_DRVINS(pDrvIns);
1521 va_list va;
1522 va_start(va, pszFormat);
1523 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
1524 va_end(va);
1525 return rc;
1526}
1527
1528
1529/** @interface_method_impl{PDMDRVHLPR0,pfnVMSetRuntimeErrorV} */
1530static DECLCALLBACK(int) pdmR0DrvHlp_VMSetRuntimeErrorV(PPDMDRVINS pDrvIns, uint32_t fFlags, const char *pszErrorId,
1531 const char *pszFormat, va_list va)
1532{
1533 PDMDRV_ASSERT_DRVINS(pDrvIns);
1534 int rc = VMSetRuntimeErrorV(pDrvIns->Internal.s.pVMR0, fFlags, pszErrorId, pszFormat, va);
1535 return rc;
1536}
1537
1538
1539/** @interface_method_impl{PDMDRVHLPR0,pfnAssertEMT} */
1540static DECLCALLBACK(bool) pdmR0DrvHlp_AssertEMT(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
1541{
1542 PDMDRV_ASSERT_DRVINS(pDrvIns);
1543 if (VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
1544 return true;
1545
1546 RTAssertMsg1Weak("AssertEMT", iLine, pszFile, pszFunction);
1547 RTAssertPanic();
1548 return false;
1549}
1550
1551
1552/** @interface_method_impl{PDMDRVHLPR0,pfnAssertOther} */
1553static DECLCALLBACK(bool) pdmR0DrvHlp_AssertOther(PPDMDRVINS pDrvIns, const char *pszFile, unsigned iLine, const char *pszFunction)
1554{
1555 PDMDRV_ASSERT_DRVINS(pDrvIns);
1556 if (!VM_IS_EMT(pDrvIns->Internal.s.pVMR0))
1557 return true;
1558
1559 RTAssertMsg1Weak("AssertOther", iLine, pszFile, pszFunction);
1560 RTAssertPanic();
1561 return false;
1562}
1563
1564
1565/**
1566 * The Ring-0 Context Driver Helper Callbacks.
1567 */
1568extern DECLEXPORT(const PDMDRVHLPR0) g_pdmR0DrvHlp =
1569{
1570 PDM_DRVHLPRC_VERSION,
1571 pdmR0DrvHlp_VMSetError,
1572 pdmR0DrvHlp_VMSetErrorV,
1573 pdmR0DrvHlp_VMSetRuntimeError,
1574 pdmR0DrvHlp_VMSetRuntimeErrorV,
1575 pdmR0DrvHlp_AssertEMT,
1576 pdmR0DrvHlp_AssertOther,
1577 PDM_DRVHLPRC_VERSION
1578};
1579
1580/** @} */
1581
1582
1583
1584
1585/**
1586 * Sets an irq on the PIC and I/O APIC.
1587 *
1588 * @returns true if delivered, false if postponed.
1589 * @param pGVM The global (ring-0) VM structure.
1590 * @param iIrq The irq.
1591 * @param iLevel The new level.
1592 * @param uTagSrc The IRQ tag and source.
1593 *
1594 * @remarks The caller holds the PDM lock.
1595 */
1596static bool pdmR0IsaSetIrq(PGVM pGVM, int iIrq, int iLevel, uint32_t uTagSrc)
1597{
1598 if (RT_LIKELY( ( pGVM->pdm.s.IoApic.pDevInsR0
1599 || !pGVM->pdm.s.IoApic.pDevInsR3)
1600 && ( pGVM->pdm.s.Pic.pDevInsR0
1601 || !pGVM->pdm.s.Pic.pDevInsR3)))
1602 {
1603 if (pGVM->pdm.s.Pic.pDevInsR0)
1604 pGVM->pdm.s.Pic.pfnSetIrqR0(pGVM->pdm.s.Pic.pDevInsR0, iIrq, iLevel, uTagSrc);
1605 if (pGVM->pdm.s.IoApic.pDevInsR0)
1606 pGVM->pdm.s.IoApic.pfnSetIrqR0(pGVM->pdm.s.IoApic.pDevInsR0, iIrq, iLevel, uTagSrc);
1607 return true;
1608 }
1609
1610 /* queue for ring-3 execution. */
1611 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)PDMQueueAlloc(pGVM->pdm.s.pDevHlpQueueR0);
1612 AssertReturn(pTask, false);
1613
1614 pTask->enmOp = PDMDEVHLPTASKOP_ISA_SET_IRQ;
1615 pTask->pDevInsR3 = NIL_RTR3PTR; /* not required */
1616 pTask->u.IsaSetIRQ.iIrq = iIrq;
1617 pTask->u.IsaSetIRQ.iLevel = iLevel;
1618 pTask->u.IsaSetIRQ.uTagSrc = uTagSrc;
1619
1620 PDMQueueInsertEx(pGVM->pdm.s.pDevHlpQueueR0, &pTask->Core, 0);
1621 return false;
1622}
1623
1624
1625/**
1626 * Worker for PDMR0DeviceCreate that does the actual instantiation.
1627 *
1628 * Allocates a memory object and divides it up as follows:
1629 * @verbatim
1630 --------------------------------------
1631 ring-0 devins
1632 --------------------------------------
1633 ring-0 instance data
1634 --------------------------------------
1635 ring-0 PCI device data (optional) ??
1636 --------------------------------------
1637 page alignment padding
1638 --------------------------------------
1639 ring-3 devins
1640 --------------------------------------
1641 ring-3 instance data
1642 --------------------------------------
1643 ring-3 PCI device data (optional) ??
1644 --------------------------------------
1645 [page alignment padding ] -
1646 [--------------------------------------] \
1647 [raw-mode devins ] \
1648 [--------------------------------------] - Optional, only when raw-mode is enabled.
1649 [raw-mode instance data ] /
1650 [--------------------------------------] /
1651 [raw-mode PCI device data (optional)?? ] -
1652 --------------------------------------
1653 shared instance data
1654 --------------------------------------
1655 default crit section
1656 --------------------------------------
1657 shared PCI device data (optional)
1658 --------------------------------------
1659 @endverbatim
1660 *
1661 * @returns VBox status code.
1662 * @param pGVM The global (ring-0) VM structure.
1663 * @param pDevReg The device registration structure.
1664 * @param iInstance The device instance number.
1665 * @param cbInstanceR3 The size of the ring-3 instance data.
1666 * @param cbInstanceRC The size of the raw-mode instance data.
1667 * @param hMod The module implementing the device. On success, the
1668 * @param RCPtrMapping The raw-mode context mapping address, NIL_RTGCPTR if
1669 * not to include raw-mode.
1670 * @param ppDevInsR3 Where to return the ring-3 device instance address.
1671 * @thread EMT(0)
1672 */
1673static int pdmR0DeviceCreateWorker(PGVM pGVM, PCPDMDEVREGR0 pDevReg, uint32_t iInstance, uint32_t cbInstanceR3,
1674 uint32_t cbInstanceRC, RTRGPTR RCPtrMapping, void *hMod, PPDMDEVINSR3 *ppDevInsR3)
1675{
1676 /*
1677 * Check that the instance number isn't a duplicate.
1678 */
1679 for (size_t i = 0; i < pGVM->pdmr0.s.cDevInstances; i++)
1680 {
1681 PPDMDEVINS pCur = pGVM->pdmr0.s.apDevInstances[i];
1682 AssertLogRelReturn(!pCur || pCur->pReg != pDevReg || pCur->iInstance != iInstance, VERR_DUPLICATE);
1683 }
1684
1685 /*
1686 * Figure out how much memory we need and allocate it.
1687 */
1688 uint32_t const cbRing0 = RT_ALIGN_32(RT_UOFFSETOF(PDMDEVINSR0, achInstanceData) + pDevReg->cbInstanceCC, PAGE_SIZE);
1689 uint32_t const cbRing3 = RT_ALIGN_32(RT_UOFFSETOF(PDMDEVINSR3, achInstanceData) + cbInstanceR3,
1690 RCPtrMapping != NIL_RTRGPTR ? PAGE_SIZE : 64);
1691 uint32_t const cbRC = RCPtrMapping != NIL_RTRGPTR ? 0
1692 : RT_ALIGN_32(RT_UOFFSETOF(PDMDEVINSRC, achInstanceData) + cbInstanceRC, 64);
1693 uint32_t const cbShared = RT_ALIGN_32(pDevReg->cbInstanceShared, 64);
1694 uint32_t const cbCritSect = RT_ALIGN_32(sizeof(PDMCRITSECT), 64);
1695 uint32_t const cbMsixState = RT_ALIGN_32(pDevReg->cMaxMsixVectors * 16 + (pDevReg->cMaxMsixVectors + 7) / 8, _4K);
1696 uint32_t const cbPciDev = RT_ALIGN_32(RT_UOFFSETOF_DYN(PDMPCIDEV, abMsixState[cbMsixState]), 64);
1697 uint32_t const cPciDevs = RT_MIN(pDevReg->cMaxPciDevices, 8);
1698 uint32_t const cbPciDevs = cbPciDev * cPciDevs;
1699 uint32_t const cbTotal = RT_ALIGN_32(cbRing0 + cbRing3 + cbRC + cbShared + cbCritSect + cbPciDevs, PAGE_SIZE);
1700 AssertLogRelMsgReturn(cbTotal <= PDM_MAX_DEVICE_INSTANCE_SIZE,
1701 ("Instance of '%s' is too big: cbTotal=%u, max %u\n",
1702 pDevReg->szName, cbTotal, PDM_MAX_DEVICE_INSTANCE_SIZE),
1703 VERR_OUT_OF_RANGE);
1704
1705 RTR0MEMOBJ hMemObj;
1706 int rc = RTR0MemObjAllocPage(&hMemObj, cbTotal, false /*fExecutable*/);
1707 if (RT_FAILURE(rc))
1708 return rc;
1709 RT_BZERO(RTR0MemObjAddress(hMemObj), cbTotal);
1710
1711 /* Map it. */
1712 RTR0MEMOBJ hMapObj;
1713 rc = RTR0MemObjMapUserEx(&hMapObj, hMemObj, (RTR3PTR)-1, 0, RTMEM_PROT_READ | RTMEM_PROT_WRITE, RTR0ProcHandleSelf(),
1714 cbRing0, cbTotal - cbRing0);
1715 if (RT_SUCCESS(rc))
1716 {
1717 PPDMDEVINSR0 pDevIns = (PPDMDEVINSR0)RTR0MemObjAddress(hMemObj);
1718 struct PDMDEVINSR3 *pDevInsR3 = (struct PDMDEVINSR3 *)((uint8_t *)pDevIns + cbRing0);
1719
1720 /*
1721 * Initialize the ring-0 instance.
1722 */
1723 pDevIns->u32Version = PDM_DEVINSR0_VERSION;
1724 pDevIns->iInstance = iInstance;
1725 pDevIns->pHlpR0 = &g_pdmR0DevHlp;
1726 pDevIns->pvInstanceDataR0 = (uint8_t *)pDevIns + cbRing0 + cbRing3 + cbRC;
1727 pDevIns->pvInstanceDataForR0 = &pDevIns->achInstanceData[0];
1728 pDevIns->pCritSectRoR0 = (PPDMCRITSECT)((uint8_t *)pDevIns->pvInstanceDataR0 + cbShared);
1729 pDevIns->pReg = pDevReg;
1730 pDevIns->pDevInsForR3 = RTR0MemObjAddressR3(hMapObj);
1731 pDevIns->pDevInsForR3R0 = pDevInsR3;
1732 pDevIns->pvInstanceDataForR3R0 = &pDevInsR3->achInstanceData[0];
1733 pDevIns->cbPciDev = cbPciDev;
1734 pDevIns->cPciDevs = cPciDevs;
1735 for (uint32_t iPciDev = 0; iPciDev < cPciDevs; iPciDev++)
1736 {
1737 /* Note! PDMDevice.cpp has a copy of this code. Keep in sync. */
1738 PPDMPCIDEV pPciDev = (PPDMPCIDEV)((uint8_t *)pDevIns->pCritSectRoR0 + cbCritSect + cbPciDev * iPciDev);
1739 if (iPciDev < RT_ELEMENTS(pDevIns->apPciDevs))
1740 pDevIns->apPciDevs[iPciDev] = pPciDev;
1741 pPciDev->cbConfig = _4K;
1742 pPciDev->cbMsixState = cbMsixState;
1743 pPciDev->idxSubDev = (uint16_t)iPciDev;
1744 pPciDev->Int.s.idxSubDev = (uint16_t)iPciDev;
1745 pPciDev->u32Magic = PDMPCIDEV_MAGIC;
1746 }
1747 pDevIns->Internal.s.pGVM = pGVM;
1748 pDevIns->Internal.s.pRegR0 = pDevReg;
1749 pDevIns->Internal.s.hMod = hMod;
1750 pDevIns->Internal.s.hMemObj = hMemObj;
1751 pDevIns->Internal.s.hMapObj = hMapObj;
1752 pDevIns->Internal.s.pInsR3R0 = pDevInsR3;
1753 pDevIns->Internal.s.pIntR3R0 = &pDevInsR3->Internal.s;
1754
1755 /*
1756 * Initialize the ring-3 instance data as much as we can.
1757 * Note! PDMDevice.cpp does this job for ring-3 only devices. Keep in sync.
1758 */
1759 pDevInsR3->u32Version = PDM_DEVINSR3_VERSION;
1760 pDevInsR3->iInstance = iInstance;
1761 pDevInsR3->cbRing3 = cbTotal - cbRing0;
1762 pDevInsR3->fR0Enabled = true;
1763 pDevInsR3->fRCEnabled = RCPtrMapping != NIL_RTRGPTR;
1764 pDevInsR3->pvInstanceDataR3 = pDevIns->pDevInsForR3 + cbRing3 + cbRC;
1765 pDevInsR3->pvInstanceDataForR3 = pDevIns->pDevInsForR3 + RT_UOFFSETOF(PDMDEVINSR3, achInstanceData);
1766 pDevInsR3->pCritSectRoR3 = pDevIns->pDevInsForR3 + cbRing3 + cbRC + cbShared;
1767 pDevInsR3->pDevInsR0RemoveMe = pDevIns;
1768 pDevInsR3->pvInstanceDataR0 = pDevIns->pvInstanceDataR0;
1769 pDevInsR3->pvInstanceDataRC = RCPtrMapping == NIL_RTRGPTR
1770 ? NIL_RTRGPTR : pDevIns->pDevInsForRC + RT_UOFFSETOF(PDMDEVINSRC, achInstanceData);
1771 pDevInsR3->pDevInsForRC = pDevIns->pDevInsForRC;
1772 pDevInsR3->pDevInsForRCR3 = pDevIns->pDevInsForR3 + cbRing3;
1773 pDevInsR3->pDevInsForRCR3 = pDevInsR3->pDevInsForRCR3 + RT_UOFFSETOF(PDMDEVINSRC, achInstanceData);
1774 pDevInsR3->cbPciDev = cbPciDev;
1775 pDevInsR3->cPciDevs = cPciDevs;
1776 for (uint32_t i = 0; i < RT_MIN(cPciDevs, RT_ELEMENTS(pDevIns->apPciDevs)); i++)
1777 pDevInsR3->apPciDevs[i] = pDevInsR3->pCritSectRoR3 + cbCritSect + cbPciDev * i;
1778
1779 pDevInsR3->Internal.s.pVMR3 = pGVM->pVMR3;
1780 pDevInsR3->Internal.s.fIntFlags = RCPtrMapping == NIL_RTRGPTR ? PDMDEVINSINT_FLAGS_R0_ENABLED
1781 : PDMDEVINSINT_FLAGS_R0_ENABLED | PDMDEVINSINT_FLAGS_RC_ENABLED;
1782
1783 /*
1784 * Initialize the raw-mode instance data as much as possible.
1785 */
1786 if (RCPtrMapping != NIL_RTRGPTR)
1787 {
1788 struct PDMDEVINSRC *pDevInsRC = RCPtrMapping == NIL_RTRGPTR ? NULL
1789 : (struct PDMDEVINSRC *)((uint8_t *)pDevIns + cbRing0 + cbRing3);
1790
1791 pDevIns->pDevInsForRC = RCPtrMapping;
1792 pDevIns->pDevInsForRCR0 = pDevInsRC;
1793 pDevIns->pvInstanceDataForRCR0 = &pDevInsRC->achInstanceData[0];
1794
1795 pDevInsRC->u32Version = PDM_DEVINSRC_VERSION;
1796 pDevInsRC->iInstance = iInstance;
1797 pDevInsRC->pvInstanceDataRC = pDevIns->pDevInsForRC + cbRC;
1798 pDevInsRC->pvInstanceDataForRC = pDevIns->pDevInsForRC + RT_UOFFSETOF(PDMDEVINSRC, achInstanceData);
1799 pDevInsRC->pCritSectRoRC = pDevIns->pDevInsForRC + cbRC + cbShared;
1800 pDevInsRC->cbPciDev = cbPciDev;
1801 pDevInsRC->cPciDevs = cPciDevs;
1802 for (uint32_t i = 0; i < RT_MIN(cPciDevs, RT_ELEMENTS(pDevIns->apPciDevs)); i++)
1803 pDevInsRC->apPciDevs[i] = pDevInsRC->pCritSectRoRC + cbCritSect + cbPciDev * i;
1804
1805 pDevInsRC->Internal.s.pVMRC = pGVM->pVMRC;
1806 }
1807
1808 /*
1809 * Add to the device instance array and set its handle value.
1810 */
1811 AssertCompile(sizeof(pGVM->pdmr0.padding) == sizeof(pGVM->pdmr0));
1812 uint32_t idxR0Device = pGVM->pdmr0.s.cDevInstances;
1813 if (idxR0Device < RT_ELEMENTS(pGVM->pdmr0.s.apDevInstances))
1814 {
1815 pGVM->pdmr0.s.apDevInstances[idxR0Device] = pDevIns;
1816 pGVM->pdmr0.s.cDevInstances = idxR0Device + 1;
1817 pDevIns->Internal.s.idxR0Device = idxR0Device;
1818 pDevInsR3->Internal.s.idxR0Device = idxR0Device;
1819
1820 /*
1821 * Call the early constructor if present.
1822 */
1823 if (pDevReg->pfnEarlyConstruct)
1824 rc = pDevReg->pfnEarlyConstruct(pDevIns);
1825 if (RT_SUCCESS(rc))
1826 {
1827 /*
1828 * We're done.
1829 */
1830 *ppDevInsR3 = RTR0MemObjAddressR3(hMapObj);
1831 return rc;
1832 }
1833
1834 /*
1835 * Bail out.
1836 */
1837 if (pDevIns->pReg->pfnFinalDestruct)
1838 pDevIns->pReg->pfnFinalDestruct(pDevIns);
1839
1840 pGVM->pdmr0.s.apDevInstances[idxR0Device] = NULL;
1841 Assert(pGVM->pdmr0.s.cDevInstances == idxR0Device + 1);
1842 pGVM->pdmr0.s.cDevInstances = idxR0Device;
1843 }
1844
1845 RTR0MemObjFree(hMapObj, true);
1846 }
1847 RTR0MemObjFree(hMemObj, true);
1848 return rc;
1849}
1850
1851
1852/**
1853 * Used by ring-3 PDM to create a device instance that operates both in ring-3
1854 * and ring-0.
1855 *
1856 * Creates an instance of a device (for both ring-3 and ring-0, and optionally
1857 * raw-mode context).
1858 *
1859 * @returns VBox status code.
1860 * @param pGVM The global (ring-0) VM structure.
1861 * @param pReq Pointer to the request buffer.
1862 * @thread EMT(0)
1863 */
1864VMMR0_INT_DECL(int) PDMR0DeviceCreateReqHandler(PGVM pGVM, PPDMDEVICECREATEREQ pReq)
1865{
1866 LogFlow(("PDMR0DeviceCreateReqHandler: %s in %s\n", pReq->szDevName, pReq->szModName));
1867
1868 /*
1869 * Validate the request.
1870 */
1871 AssertReturn(pReq->Hdr.cbReq == sizeof(*pReq), VERR_INVALID_PARAMETER);
1872 pReq->pDevInsR3 = NIL_RTR3PTR;
1873
1874 int rc = GVMMR0ValidateGVMandEMT(pGVM, 0);
1875 AssertRCReturn(rc, rc);
1876
1877 AssertReturn(pReq->fFlags != 0, VERR_INVALID_FLAGS);
1878 AssertReturn(pReq->fClass != 0, VERR_WRONG_TYPE);
1879 AssertReturn(pReq->uSharedVersion != 0, VERR_INVALID_PARAMETER);
1880 AssertReturn(pReq->cbInstanceShared != 0, VERR_INVALID_PARAMETER);
1881 size_t const cchDevName = RTStrNLen(pReq->szDevName, sizeof(pReq->szDevName));
1882 AssertReturn(cchDevName < sizeof(pReq->szDevName), VERR_NO_STRING_TERMINATOR);
1883 AssertReturn(cchDevName > 0, VERR_EMPTY_STRING);
1884 AssertReturn(cchDevName < RT_SIZEOFMEMB(PDMDEVREG, szName), VERR_NOT_FOUND);
1885
1886 size_t const cchModName = RTStrNLen(pReq->szModName, sizeof(pReq->szModName));
1887 AssertReturn(cchModName < sizeof(pReq->szModName), VERR_NO_STRING_TERMINATOR);
1888 AssertReturn(cchModName > 0, VERR_EMPTY_STRING);
1889 AssertReturn(pReq->cbInstanceShared <= PDM_MAX_DEVICE_INSTANCE_SIZE, VERR_OUT_OF_RANGE);
1890 AssertReturn(pReq->cbInstanceR3 <= PDM_MAX_DEVICE_INSTANCE_SIZE, VERR_OUT_OF_RANGE);
1891 AssertReturn(pReq->cbInstanceRC <= PDM_MAX_DEVICE_INSTANCE_SIZE, VERR_OUT_OF_RANGE);
1892 AssertReturn(pReq->iInstance < 1024, VERR_OUT_OF_RANGE);
1893 AssertReturn(pReq->iInstance < pReq->cMaxInstances, VERR_OUT_OF_RANGE);
1894 AssertReturn(pReq->cMaxPciDevices <= 8, VERR_OUT_OF_RANGE);
1895 AssertReturn(pReq->cMaxMsixVectors <= VBOX_MSIX_MAX_ENTRIES, VERR_OUT_OF_RANGE);
1896
1897 /*
1898 * Reference the module.
1899 */
1900 void *hMod = NULL;
1901 rc = SUPR0LdrModByName(pGVM->pSession, pReq->szModName, &hMod);
1902 if (RT_FAILURE(rc))
1903 {
1904 LogRel(("PDMR0DeviceCreateReqHandler: SUPR0LdrModByName(,%s,) failed: %Rrc\n", pReq->szModName, rc));
1905 return rc;
1906 }
1907
1908 /*
1909 * Look for the the module and the device registration structure.
1910 */
1911 int rcLock = SUPR0LdrLock(pGVM->pSession);
1912 AssertRC(rc);
1913
1914 rc = VERR_NOT_FOUND;
1915 PPDMDEVMODREGR0 pMod;
1916 RTListForEach(&g_PDMDevModList, pMod, PDMDEVMODREGR0, ListEntry)
1917 {
1918 if (pMod->hMod == hMod)
1919 {
1920 /*
1921 * Found the module. We can drop the loader lock now before we
1922 * search the devices it registers.
1923 */
1924 if (RT_SUCCESS(rcLock))
1925 {
1926 rcLock = SUPR0LdrUnlock(pGVM->pSession);
1927 AssertRC(rcLock);
1928 }
1929 rcLock = VERR_ALREADY_RESET;
1930
1931 PCPDMDEVREGR0 *papDevRegs = pMod->papDevRegs;
1932 size_t i = pMod->cDevRegs;
1933 while (i-- > 0)
1934 {
1935 PCPDMDEVREGR0 pDevReg = papDevRegs[i];
1936 LogFlow(("PDMR0DeviceCreateReqHandler: candidate #%u: %s %#x\n", i, pReq->szDevName, pDevReg->u32Version));
1937 if ( PDM_VERSION_ARE_COMPATIBLE(pDevReg->u32Version, PDM_DEVREGR0_VERSION)
1938 && pDevReg->szName[cchDevName] == '\0'
1939 && memcmp(pDevReg->szName, pReq->szDevName, cchDevName) == 0)
1940 {
1941
1942 /*
1943 * Found the device, now check whether it matches the ring-3 registration.
1944 */
1945 if ( pReq->uSharedVersion == pDevReg->uSharedVersion
1946 && pReq->cbInstanceShared == pDevReg->cbInstanceShared
1947 && pReq->cbInstanceRC == pDevReg->cbInstanceRC
1948 && pReq->fFlags == pDevReg->fFlags
1949 && pReq->fClass == pDevReg->fClass
1950 && pReq->cMaxInstances == pDevReg->cMaxInstances
1951 && pReq->cMaxPciDevices == pDevReg->cMaxPciDevices
1952 && pReq->cMaxMsixVectors == pDevReg->cMaxMsixVectors)
1953 {
1954 rc = pdmR0DeviceCreateWorker(pGVM, pDevReg, pReq->iInstance, pReq->cbInstanceR3, pReq->cbInstanceRC,
1955 NIL_RTRCPTR /** @todo new raw-mode */, hMod, &pReq->pDevInsR3);
1956 if (RT_SUCCESS(rc))
1957 hMod = NULL; /* keep the module reference */
1958 }
1959 else
1960 {
1961 LogRel(("PDMR0DeviceCreate: Ring-3 does not match ring-0 device registration (%s):\n"
1962 " uSharedVersion: %#x vs %#x\n"
1963 " cbInstanceShared: %#x vs %#x\n"
1964 " cbInstanceRC: %#x vs %#x\n"
1965 " fFlags: %#x vs %#x\n"
1966 " fClass: %#x vs %#x\n"
1967 " cMaxInstances: %#x vs %#x\n"
1968 " cMaxPciDevices: %#x vs %#x\n"
1969 " cMaxMsixVectors: %#x vs %#x\n"
1970 ,
1971 pReq->szDevName,
1972 pReq->uSharedVersion, pDevReg->uSharedVersion,
1973 pReq->cbInstanceShared, pDevReg->cbInstanceShared,
1974 pReq->cbInstanceRC, pDevReg->cbInstanceRC,
1975 pReq->fFlags, pDevReg->fFlags,
1976 pReq->fClass, pDevReg->fClass,
1977 pReq->cMaxInstances, pDevReg->cMaxInstances,
1978 pReq->cMaxPciDevices, pDevReg->cMaxPciDevices,
1979 pReq->cMaxMsixVectors, pDevReg->cMaxMsixVectors));
1980 rc = VERR_INCOMPATIBLE_CONFIG;
1981 }
1982 }
1983 }
1984 break;
1985 }
1986 }
1987
1988 if (RT_SUCCESS_NP(rcLock))
1989 {
1990 rcLock = SUPR0LdrUnlock(pGVM->pSession);
1991 AssertRC(rcLock);
1992 }
1993 SUPR0LdrModRelease(pGVM->pSession, hMod);
1994 return rc;
1995}
1996
1997
1998/**
1999 * Used by ring-3 PDM to call standard ring-0 device methods.
2000 *
2001 * @returns VBox status code.
2002 * @param pGVM The global (ring-0) VM structure.
2003 * @param pReq Pointer to the request buffer.
2004 * @param idCpu The ID of the calling EMT.
2005 * @thread EMT(0), except for PDMDEVICEGENCALL_REQUEST which can be any EMT.
2006 */
2007VMMR0_INT_DECL(int) PDMR0DeviceGenCallReqHandler(PGVM pGVM, PPDMDEVICEGENCALLREQ pReq, VMCPUID idCpu)
2008{
2009 /*
2010 * Validate the request.
2011 */
2012 AssertReturn(pReq->Hdr.cbReq == sizeof(*pReq), VERR_INVALID_PARAMETER);
2013
2014 int rc = GVMMR0ValidateGVMandEMT(pGVM, idCpu);
2015 AssertRCReturn(rc, rc);
2016
2017 AssertReturn(pReq->idxR0Device < pGVM->pdmr0.s.cDevInstances, VERR_INVALID_HANDLE);
2018 PPDMDEVINSR0 pDevIns = pGVM->pdmr0.s.apDevInstances[pReq->idxR0Device];
2019 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
2020 AssertReturn(pDevIns->pDevInsForR3 == pReq->pDevInsR3, VERR_INVALID_HANDLE);
2021
2022 /*
2023 * Make the call.
2024 */
2025 rc = VINF_SUCCESS /*VINF_NOT_IMPLEMENTED*/;
2026 switch (pReq->enmCall)
2027 {
2028 case PDMDEVICEGENCALL_CONSTRUCT:
2029 AssertMsgBreakStmt(pGVM->enmVMState < VMSTATE_CREATED, ("enmVMState=%d\n", pGVM->enmVMState), rc = VERR_INVALID_STATE);
2030 AssertReturn(idCpu == 0, VERR_VM_THREAD_NOT_EMT);
2031 if (pDevIns->pReg->pfnConstruct)
2032 rc = pDevIns->pReg->pfnConstruct(pDevIns);
2033 break;
2034
2035 case PDMDEVICEGENCALL_DESTRUCT:
2036 AssertMsgBreakStmt(pGVM->enmVMState < VMSTATE_CREATED || pGVM->enmVMState >= VMSTATE_DESTROYING,
2037 ("enmVMState=%d\n", pGVM->enmVMState), rc = VERR_INVALID_STATE);
2038 AssertReturn(idCpu == 0, VERR_VM_THREAD_NOT_EMT);
2039 if (pDevIns->pReg->pfnDestruct)
2040 {
2041 pDevIns->pReg->pfnDestruct(pDevIns);
2042 rc = VINF_SUCCESS;
2043 }
2044 break;
2045
2046 case PDMDEVICEGENCALL_REQUEST:
2047 if (pDevIns->pReg->pfnRequest)
2048 rc = pDevIns->pReg->pfnRequest(pDevIns, pReq->Params.Req.uReq, pReq->Params.Req.uArg);
2049 else
2050 rc = VERR_INVALID_FUNCTION;
2051 break;
2052
2053 default:
2054 AssertMsgFailed(("enmCall=%d\n", pReq->enmCall));
2055 rc = VERR_INVALID_FUNCTION;
2056 break;
2057 }
2058
2059 return rc;
2060}
2061
2062
2063/**
2064 * Legacy device mode compatiblity.
2065 *
2066 * @returns VBox status code.
2067 * @param pGVM The global (ring-0) VM structure.
2068 * @param pReq Pointer to the request buffer.
2069 * @thread EMT(0)
2070 */
2071VMMR0_INT_DECL(int) PDMR0DeviceCompatSetCritSectReqHandler(PGVM pGVM, PPDMDEVICECOMPATSETCRITSECTREQ pReq)
2072{
2073 /*
2074 * Validate the request.
2075 */
2076 AssertReturn(pReq->Hdr.cbReq == sizeof(*pReq), VERR_INVALID_PARAMETER);
2077
2078 int rc = GVMMR0ValidateGVMandEMT(pGVM, 0);
2079 AssertRCReturn(rc, rc);
2080
2081 AssertReturn(pReq->idxR0Device < pGVM->pdmr0.s.cDevInstances, VERR_INVALID_HANDLE);
2082 PPDMDEVINSR0 pDevIns = pGVM->pdmr0.s.apDevInstances[pReq->idxR0Device];
2083 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
2084 AssertReturn(pDevIns->pDevInsForR3 == pReq->pDevInsR3, VERR_INVALID_HANDLE);
2085
2086 AssertReturn(pGVM->enmVMState == VMSTATE_CREATING, VERR_INVALID_STATE);
2087
2088 /*
2089 * The critical section address can be in a few different places:
2090 * 1. shared data.
2091 * 2. nop section.
2092 * 3. pdm critsect.
2093 */
2094 PPDMCRITSECT pCritSect;
2095 if (pReq->pCritSectR3 == pGVM->pVMR3 + RT_UOFFSETOF(VM, pdm.s.NopCritSect))
2096 {
2097 pCritSect = &pGVM->pdm.s.NopCritSect;
2098 Log(("PDMR0DeviceCompatSetCritSectReqHandler: Nop - %p %#x\n", pCritSect, pCritSect->s.Core.u32Magic));
2099 }
2100 else if (pReq->pCritSectR3 == pGVM->pVMR3 + RT_UOFFSETOF(VM, pdm.s.CritSect))
2101 {
2102 pCritSect = &pGVM->pdm.s.CritSect;
2103 Log(("PDMR0DeviceCompatSetCritSectReqHandler: PDM - %p %#x\n", pCritSect, pCritSect->s.Core.u32Magic));
2104 }
2105 else
2106 {
2107 size_t offCritSect = pReq->pCritSectR3 - pDevIns->pDevInsForR3R0->pvInstanceDataR3;
2108 AssertLogRelMsgReturn( offCritSect < pDevIns->pReg->cbInstanceShared
2109 && offCritSect + sizeof(PDMCRITSECT) <= pDevIns->pReg->cbInstanceShared,
2110 ("offCritSect=%p pCritSectR3=%p cbInstanceShared=%#x (%s)\n",
2111 offCritSect, pReq->pCritSectR3, pDevIns->pReg->cbInstanceShared, pDevIns->pReg->szName),
2112 VERR_INVALID_POINTER);
2113 pCritSect = (PPDMCRITSECT)((uint8_t *)pDevIns->pvInstanceDataR0 + offCritSect);
2114 Log(("PDMR0DeviceCompatSetCritSectReqHandler: custom - %#x/%p %#x\n", offCritSect, pCritSect, pCritSect->s.Core.u32Magic));
2115 }
2116 AssertLogRelMsgReturn(pCritSect->s.Core.u32Magic == RTCRITSECT_MAGIC,
2117 ("cs=%p magic=%#x dev=%s\n", pCritSect, pCritSect->s.Core.u32Magic, pDevIns->pReg->szName),
2118 VERR_INVALID_MAGIC);
2119
2120 /*
2121 * Make the update.
2122 */
2123 pDevIns->pCritSectRoR0 = pCritSect;
2124
2125 return VINF_SUCCESS;
2126}
2127
2128
2129/**
2130 * Registers the device implementations living in a module.
2131 *
2132 * This should normally only be called during ModuleInit(). The should be a
2133 * call to PDMR0DeviceDeregisterModule from the ModuleTerm() function to undo
2134 * the effects of this call.
2135 *
2136 * @returns VBox status code.
2137 * @param hMod The module handle of the module being registered.
2138 * @param pModReg The module registration structure. This will be
2139 * used directly so it must live as long as the module
2140 * and be writable.
2141 *
2142 * @note Caller must own the loader lock!
2143 */
2144VMMR0DECL(int) PDMR0DeviceRegisterModule(void *hMod, PPDMDEVMODREGR0 pModReg)
2145{
2146 /*
2147 * Validate the input.
2148 */
2149 AssertPtrReturn(hMod, VERR_INVALID_HANDLE);
2150 Assert(SUPR0LdrIsLockOwnerByMod(hMod, true));
2151
2152 AssertPtrReturn(pModReg, VERR_INVALID_POINTER);
2153 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE(pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2154 ("pModReg->u32Version=%#x vs %#x\n", pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2155 VERR_VERSION_MISMATCH);
2156 AssertLogRelMsgReturn(pModReg->cDevRegs <= 256 && pModReg->cDevRegs > 0, ("cDevRegs=%u\n", pModReg->cDevRegs),
2157 VERR_OUT_OF_RANGE);
2158 AssertLogRelMsgReturn(pModReg->hMod == NULL, ("hMod=%p\n", pModReg->hMod), VERR_INVALID_PARAMETER);
2159 AssertLogRelMsgReturn(pModReg->ListEntry.pNext == NULL, ("pNext=%p\n", pModReg->ListEntry.pNext), VERR_INVALID_PARAMETER);
2160 AssertLogRelMsgReturn(pModReg->ListEntry.pPrev == NULL, ("pPrev=%p\n", pModReg->ListEntry.pPrev), VERR_INVALID_PARAMETER);
2161
2162 for (size_t i = 0; i < pModReg->cDevRegs; i++)
2163 {
2164 PCPDMDEVREGR0 pDevReg = pModReg->papDevRegs[i];
2165 AssertLogRelMsgReturn(RT_VALID_PTR(pDevReg), ("[%u]: %p\n", i, pDevReg), VERR_INVALID_POINTER);
2166 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE(pDevReg->u32Version, PDM_DEVREGR0_VERSION),
2167 ("pDevReg->u32Version=%#x vs %#x\n", pModReg->u32Version, PDM_DEVREGR0_VERSION), VERR_VERSION_MISMATCH);
2168 AssertLogRelMsgReturn(RT_VALID_PTR(pDevReg->pszDescription), ("[%u]: %p\n", i, pDevReg->pszDescription), VERR_INVALID_POINTER);
2169 AssertLogRelMsgReturn(pDevReg->uReserved0 == 0, ("[%u]: %#x\n", i, pDevReg->uReserved0), VERR_INVALID_PARAMETER);
2170 AssertLogRelMsgReturn(pDevReg->fClass != 0, ("[%u]: %#x\n", i, pDevReg->fClass), VERR_INVALID_PARAMETER);
2171 AssertLogRelMsgReturn(pDevReg->fFlags != 0, ("[%u]: %#x\n", i, pDevReg->fFlags), VERR_INVALID_PARAMETER);
2172 AssertLogRelMsgReturn(pDevReg->cMaxInstances > 0, ("[%u]: %#x\n", i, pDevReg->cMaxInstances), VERR_INVALID_PARAMETER);
2173 AssertLogRelMsgReturn(pDevReg->cMaxPciDevices <= 8, ("[%u]: %#x\n", i, pDevReg->cMaxPciDevices), VERR_INVALID_PARAMETER);
2174 AssertLogRelMsgReturn(pDevReg->cMaxMsixVectors <= VBOX_MSIX_MAX_ENTRIES,
2175 ("[%u]: %#x\n", i, pDevReg->cMaxMsixVectors), VERR_INVALID_PARAMETER);
2176
2177 /* The name must be printable ascii and correctly terminated. */
2178 for (size_t off = 0; off < RT_ELEMENTS(pDevReg->szName); off++)
2179 {
2180 char ch = pDevReg->szName[off];
2181 AssertLogRelMsgReturn(RT_C_IS_PRINT(ch) || (ch == '\0' && off > 0),
2182 ("[%u]: off=%u szName: %.*Rhxs\n", i, off, sizeof(pDevReg->szName), &pDevReg->szName[0]),
2183 VERR_INVALID_NAME);
2184 if (ch == '\0')
2185 break;
2186 }
2187 }
2188
2189 /*
2190 * Add it, assuming we're being called at ModuleInit/ModuleTerm time only, or
2191 * that the caller has already taken the loader lock.
2192 */
2193 pModReg->hMod = hMod;
2194 RTListAppend(&g_PDMDevModList, &pModReg->ListEntry);
2195
2196 return VINF_SUCCESS;
2197}
2198
2199
2200/**
2201 * Deregisters the device implementations living in a module.
2202 *
2203 * This should normally only be called during ModuleTerm().
2204 *
2205 * @returns VBox status code.
2206 * @param hMod The module handle of the module being registered.
2207 * @param pModReg The module registration structure. This will be
2208 * used directly so it must live as long as the module
2209 * and be writable.
2210 *
2211 * @note Caller must own the loader lock!
2212 */
2213VMMR0DECL(int) PDMR0DeviceDeregisterModule(void *hMod, PPDMDEVMODREGR0 pModReg)
2214{
2215 /*
2216 * Validate the input.
2217 */
2218 AssertPtrReturn(hMod, VERR_INVALID_HANDLE);
2219 Assert(SUPR0LdrIsLockOwnerByMod(hMod, true));
2220
2221 AssertPtrReturn(pModReg, VERR_INVALID_POINTER);
2222 AssertLogRelMsgReturn(PDM_VERSION_ARE_COMPATIBLE(pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2223 ("pModReg->u32Version=%#x vs %#x\n", pModReg->u32Version, PDM_DEVMODREGR0_VERSION),
2224 VERR_VERSION_MISMATCH);
2225 AssertLogRelMsgReturn(pModReg->hMod == hMod || pModReg->hMod == NULL, ("pModReg->hMod=%p vs %p\n", pModReg->hMod, hMod),
2226 VERR_INVALID_PARAMETER);
2227
2228 /*
2229 * Unlink the registration record and return it to virgin conditions. Ignore
2230 * the call if not registered.
2231 */
2232 if (pModReg->hMod)
2233 {
2234 pModReg->hMod = NULL;
2235 RTListNodeRemove(&pModReg->ListEntry);
2236 pModReg->ListEntry.pNext = NULL;
2237 pModReg->ListEntry.pPrev = NULL;
2238 return VINF_SUCCESS;
2239 }
2240 return VWRN_NOT_FOUND;
2241}
2242
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