1 | /* $Id: PGMR0DynMap.cpp 14404 2008-11-20 12:20:49Z vboxsync $ */
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2 | /** @file
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3 | * PGM - Page Manager and Monitor, ring-0 dynamic mapping cache.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2008 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | /*******************************************************************************
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23 | * Internal Functions *
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24 | *******************************************************************************/
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25 | #include <VBox/pgm.h>
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26 | #include "../PGMInternal.h"
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27 | #include <VBox/vm.h>
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28 | #include <VBox/sup.h>
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29 | #include <VBox/err.h>
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30 | #include <iprt/asm.h>
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31 | #include <iprt/alloc.h>
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32 | #include <iprt/assert.h>
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33 | #include <iprt/cpuset.h>
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34 | #include <iprt/memobj.h>
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35 | #include <iprt/mp.h>
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36 | #include <iprt/spinlock.h>
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37 | #include <iprt/semaphore.h>
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38 |
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39 |
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40 | /*******************************************************************************
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41 | * Structures and Typedefs *
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42 | *******************************************************************************/
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43 | /**
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44 | * Ring-0 dynamic mapping cache segment.
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45 | *
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46 | * The dynamic mapping cache can be extended with additional segments if the
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47 | * load is found to be too high. This done the next time a VM is created, under
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48 | * the protection of the init mutex. The arrays is reallocated and the new
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49 | * segment is added to the end of these. Nothing is rehashed of course, as the
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50 | * indexes / addresses must remain unchanged.
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51 | *
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52 | * This structure is only modified while owning the init mutex or during module
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53 | * init / term.
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54 | */
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55 | typedef struct PGMR0DYNMAPSEG
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56 | {
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57 | /** Pointer to the next segment. */
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58 | struct PGMR0DYNMAPSEG *pNext;
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59 | /** The memory object for the virtual address range that we're abusing. */
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60 | RTR0MEMOBJ hMemObj;
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61 | /** The memory object for the page tables. */
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62 | RTR0MEMOBJ hMemObjPT;
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63 | /** The start page in the cache. (I.e. index into the arrays.) */
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64 | uint32_t iPage;
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65 | /** The number of pages this segment contributes. */
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66 | uint32_t cPages;
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67 | } PGMR0DYNMAPSEG;
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68 | /** Pointer to a ring-0 dynamic mapping cache segment. */
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69 | typedef PGMR0DYNMAPSEG *PPGMR0DYNMAPSEG;
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70 |
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71 |
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72 | /**
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73 | * Ring-0 dynamic mapping cache entry.
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74 | *
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75 | * This structure tracks
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76 | */
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77 | typedef struct PGMR0DYNMAPENTRY
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78 | {
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79 | /** The physical address of the currently mapped page.
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80 | * This is duplicate for three reasons: cache locality, cache policy of the PT
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81 | * mappings and sanity checks. */
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82 | RTHCPHYS HCPhys;
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83 | /** Pointer to the page. */
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84 | void *pvPage;
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85 | /** The number of references. */
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86 | int32_t volatile cRefs;
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87 | /** PTE pointer union. */
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88 | union PGMR0DYNMAPENTRY_PPTE
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89 | {
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90 | /** PTE pointer, 32-bit legacy version. */
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91 | PX86PTE pLegacy;
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92 | /** PTE pointer, PAE version. */
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93 | PX86PTEPAE pPae;
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94 | } uPte;
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95 | /** CPUs that haven't invalidated this entry after it's last update. */
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96 | RTCPUSET PendingSet;
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97 | } PGMR0DYNMAPENTRY;
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98 | /** Pointer to a ring-0 dynamic mapping cache entry. */
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99 | typedef PGMR0DYNMAPENTRY *PPGMR0DYNMAPENTRY;
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100 |
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101 |
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102 | /**
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103 | * Ring-0 dynamic mapping cache.
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104 | *
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105 | * This is initialized during VMMR0 module init but no segments are allocated at
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106 | * that time. Segments will be added when the first VM is started and removed
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107 | * again when the last VM shuts down, thus avoid consuming memory while dormant.
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108 | * At module termination, the remaining bits will be freed up.
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109 | */
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110 | typedef struct PGMR0DYNMAP
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111 | {
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112 | /** The usual magic number / eye catcher (PGMR0DYNMAP_MAGIC). */
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113 | uint32_t u32Magic;
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114 | /** Spinlock serializing the normal operation of the cache. */
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115 | RTSPINLOCK hSpinlock;
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116 | /** Array for tracking and managing the pages. */
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117 | PPGMR0DYNMAPENTRY paPages;
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118 | /** The cache size given as a number of pages. */
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119 | uint32_t cPages;
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120 | /** Whether it's 32-bit legacy or PAE/AMD64 paging mode. */
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121 | bool fLegacyMode;
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122 | /** The current load. */
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123 | uint32_t cLoad;
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124 | /** The max load.
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125 | * This is maintained to get trigger adding of more mapping space. */
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126 | uint32_t cMaxLoad;
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127 | /** Initialization / termination lock. */
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128 | RTSEMFASTMUTEX hInitLock;
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129 | /** The number of users (protected by hInitLock). */
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130 | uint32_t cUsers;
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131 | /** Array containing a copy of the original page tables.
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132 | * The entries are either X86PTE or X86PTEPAE according to fLegacyMode. */
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133 | void *pvSavedPTEs;
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134 | /** List of segments. */
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135 | PPGMR0DYNMAPSEG pSegHead;
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136 | } PGMR0DYNMAP;
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137 | /** Pointer to the ring-0 dynamic mapping cache */
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138 | typedef PGMR0DYNMAP *PPGMR0DYNMAP;
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139 |
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140 | /** PGMR0DYNMAP::u32Magic. (Jens Christian Bugge Wesseltoft) */
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141 | #define PGMR0DYNMAP_MAGIC 0x19640201
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142 |
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143 |
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144 | /*******************************************************************************
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145 | * Global Variables *
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146 | *******************************************************************************/
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147 | /** Pointer to the ring-0 dynamic mapping cache. */
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148 | static PPGMR0DYNMAP g_pPGMR0DynMap;
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149 |
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150 |
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151 | /*******************************************************************************
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152 | * Internal Functions *
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153 | *******************************************************************************/
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154 | static void pgmR0DynMapReleasePage(PPGMR0DYNMAP pThis, uint32_t iPage, uint32_t cRefs);
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155 | static int pgmR0DynMapSetup(PPGMR0DYNMAP pThis);
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156 | static int pgmR0DynMapGrow(PPGMR0DYNMAP pThis);
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157 | static void pgmR0DynMapTearDown(PPGMR0DYNMAP pThis);
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158 |
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159 |
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160 | /**
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161 | * Initializes the ring-0 dynamic mapping cache.
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162 | *
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163 | * @returns VBox status code.
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164 | */
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165 | VMMR0DECL(int) PGMR0DynMapInit(void)
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166 | {
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167 | #ifndef DEBUG_bird
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168 | return VINF_SUCCESS;
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169 | #else
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170 | Assert(!g_pPGMR0DynMap);
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171 |
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172 | /*
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173 | * Create and initialize the cache instance.
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174 | */
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175 | PPGMR0DYNMAP pThis = (PPGMR0DYNMAP)RTMemAllocZ(sizeof(*pThis));
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176 | AssertLogRelReturn(pThis, VERR_NO_MEMORY);
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177 | int rc = VINF_SUCCESS;
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178 | SUPPAGINGMODE enmMode = SUPR0GetPagingMode();
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179 | switch (enmMode)
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180 | {
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181 | case SUPPAGINGMODE_32_BIT:
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182 | case SUPPAGINGMODE_32_BIT_GLOBAL:
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183 | pThis->fLegacyMode = false;
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184 | break;
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185 | case SUPPAGINGMODE_PAE:
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186 | case SUPPAGINGMODE_PAE_GLOBAL:
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187 | case SUPPAGINGMODE_PAE_NX:
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188 | case SUPPAGINGMODE_PAE_GLOBAL_NX:
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189 | case SUPPAGINGMODE_AMD64:
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190 | case SUPPAGINGMODE_AMD64_GLOBAL:
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191 | case SUPPAGINGMODE_AMD64_NX:
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192 | case SUPPAGINGMODE_AMD64_GLOBAL_NX:
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193 | pThis->fLegacyMode = false;
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194 | break;
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195 | default:
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196 | rc = VERR_INTERNAL_ERROR;
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197 | break;
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198 | }
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199 | if (RT_SUCCESS(rc))
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200 | {
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201 | rc = RTSemFastMutexCreate(&pThis->hInitLock);
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202 | if (RT_SUCCESS(rc))
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203 | {
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204 | rc = RTSpinlockCreate(&pThis->hSpinlock);
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205 | if (RT_SUCCESS(rc))
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206 | {
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207 | pThis->u32Magic = PGMR0DYNMAP_MAGIC;
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208 | g_pPGMR0DynMap = pThis;
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209 | return VINF_SUCCESS;
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210 | }
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211 | RTSemFastMutexDestroy(pThis->hInitLock);
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212 | }
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213 | }
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214 | RTMemFree(pThis);
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215 | return rc;
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216 | #endif
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217 | }
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218 |
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219 |
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220 | /**
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221 | * Terminates the ring-0 dynamic mapping cache.
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222 | */
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223 | VMMR0DECL(void) PGMR0DynMapTerm(void)
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224 | {
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225 | #ifdef DEBUG_bird
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226 | /*
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227 | * Destroy the cache.
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228 | *
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229 | * There is not supposed to be any races here, the loader should
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230 | * make sure about that. So, don't bother locking anything.
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231 | *
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232 | * The VM objects should all be destroyed by now, so there is no
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233 | * dangling users or anything like that to clean up. This routine
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234 | * is just a mirror image of PGMR0DynMapInit.
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235 | */
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236 | PPGMR0DYNMAP pThis = g_pPGMR0DynMap;
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237 | if (pThis)
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238 | {
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239 | AssertPtr(pThis);
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240 | g_pPGMR0DynMap = NULL;
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241 |
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242 | AssertLogRelMsg(!pThis->cUsers && !pThis->paPages && !pThis->cPages,
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243 | ("cUsers=%d paPages=%p cPages=%#x\n",
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244 | pThis->cUsers, pThis->paPages, pThis->cPages));
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245 |
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246 | /* Free the associated resources. */
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247 | RTSemFastMutexDestroy(pThis->hInitLock);
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248 | pThis->hInitLock = NIL_RTSEMFASTMUTEX;
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249 | RTSpinlockDestroy(pThis->hSpinlock);
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250 | pThis->hSpinlock = NIL_RTSPINLOCK;
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251 | pThis->u32Magic = UINT32_MAX;
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252 | RTMemFree(pThis);
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253 | }
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254 | #endif
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255 | }
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256 |
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257 |
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258 | /**
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259 | * Initializes the dynamic mapping cache for a new VM.
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260 | *
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261 | * @returns VBox status code.
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262 | * @param pVM Pointer to the shared VM structure.
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263 | */
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264 | VMMR0DECL(int) PGMR0DynMapInitVM(PVM pVM)
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265 | {
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266 | #ifndef DEBUG_bird
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267 | return VINF_SUCCESS;
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268 | #else
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269 | /*
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270 | * Initialize the auto sets.
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271 | */
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272 | VMCPUID idCpu = pVM->cCPUs;
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273 | while (idCpu-- > 0)
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274 | {
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275 | PPGMMAPSET pSet = &pVM->aCpus[idCpu].pgm.s.AutoSet;
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276 | uint32_t j = RT_ELEMENTS(pSet->aEntries);
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277 | while (j-- > 0)
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278 | {
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279 | pSet->aEntries[j].iPage = UINT16_MAX;
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280 | pSet->aEntries[j].cRefs = 0;
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281 | }
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282 | pSet->cEntries = PGMMAPSET_CLOSED;
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283 | }
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284 |
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285 | /*
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286 | * Do we need the cache? Skip the last bit if we don't.
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287 | */
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288 | Assert(!pVM->pgm.s.pvR0DynMapUsed);
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289 | pVM->pgm.s.pvR0DynMapUsed = NULL;
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290 | if (!HWACCMIsEnabled(pVM))
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291 | return VINF_SUCCESS;
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292 |
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293 | /*
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294 | * Reference and if necessary setup or grow the cache.
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295 | */
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296 | PPGMR0DYNMAP pThis = g_pPGMR0DynMap;
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297 | AssertPtrReturn(pThis, VERR_INTERNAL_ERROR);
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298 | int rc = RTSemFastMutexRequest(pThis->hInitLock);
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299 | AssertLogRelRCReturn(rc, rc);
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300 |
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301 | pThis->cUsers++;
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302 | if (pThis->cUsers == 1)
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303 | rc = pgmR0DynMapSetup(pThis);
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304 | else if (pThis->cMaxLoad > pThis->cPages / 2)
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305 | rc = pgmR0DynMapGrow(pThis);
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306 | if (RT_FAILURE(rc))
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307 | pThis->cUsers--;
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308 |
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309 | RTSemFastMutexRelease(pThis->hInitLock);
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310 |
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311 | return rc;
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312 | #endif
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313 | }
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314 |
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315 |
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316 | /**
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317 | * Terminates the dynamic mapping cache usage for a VM.
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318 | *
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319 | * @param pVM Pointer to the shared VM structure.
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320 | */
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321 | VMMR0DECL(void) PGMR0DynMapTermVM(PVM pVM)
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322 | {
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323 | #ifdef DEBUG_bird
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324 | /*
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325 | * Return immediately if we're not using the cache.
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326 | */
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327 | if (!pVM->pgm.s.pvR0DynMapUsed)
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328 | return;
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329 |
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330 | PPGMR0DYNMAP pThis = g_pPGMR0DynMap;
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331 | AssertPtrReturnVoid(pThis);
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332 |
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333 | int rc = RTSemFastMutexRequest(pThis->hInitLock);
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334 | AssertLogRelRCReturnVoid(rc);
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335 |
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336 | if (pVM->pgm.s.pvR0DynMapUsed == pThis)
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337 | {
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338 | pVM->pgm.s.pvR0DynMapUsed = NULL;
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339 |
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340 | /*
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341 | * Clean up and check the auto sets.
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342 | */
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343 | VMCPUID idCpu = pVM->cCPUs;
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344 | while (idCpu-- > 0)
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345 | {
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346 | PPGMMAPSET pSet = &pVM->aCpus[idCpu].pgm.s.AutoSet;
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347 | uint32_t j = pSet->cEntries;
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348 | if (j <= RT_ELEMENTS(pSet->aEntries))
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349 | {
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350 | /*
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351 | * The set is open, close it.
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352 | */
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353 | while (j-- > 0)
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354 | {
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355 | int32_t cRefs = pSet->aEntries[j].cRefs;
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356 | uint32_t iPage = pSet->aEntries[j].iPage;
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357 | LogRel(("PGMR0DynMapTermVM: %d dangling refs to %#x\n", cRefs, iPage));
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358 | if (iPage < pThis->cPages && cRefs > 0)
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359 | pgmR0DynMapReleasePage(pThis, iPage, cRefs);
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360 | else
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361 | AssertMsgFailed(("cRefs=%d iPage=%#x cPages=%u\n", cRefs, iPage, pThis->cPages));
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362 |
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363 | pSet->aEntries[j].iPage = UINT16_MAX;
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364 | pSet->aEntries[j].cRefs = 0;
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365 | }
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366 | pSet->cEntries = PGMMAPSET_CLOSED;
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367 | }
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368 |
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369 | j = RT_ELEMENTS(pSet->aEntries);
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370 | while (j-- > 0)
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371 | {
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372 | Assert(pSet->aEntries[j].iPage == UINT16_MAX);
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373 | Assert(!pSet->aEntries[j].cRefs);
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374 | }
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375 | }
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376 |
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377 | /*
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378 | * Release our reference to the mapping cache.
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379 | */
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380 | Assert(pThis->cUsers > 0);
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381 | pThis->cUsers--;
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382 | if (!pThis->cUsers)
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383 | pgmR0DynMapTearDown(pThis);
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384 | }
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385 | else
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386 | AssertMsgFailed(("pvR0DynMapUsed=%p pThis=%p\n", pVM->pgm.s.pvR0DynMapUsed, pThis));
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387 |
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388 | RTSemFastMutexRelease(pThis->hInitLock);
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389 | #endif
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390 | }
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391 |
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392 |
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393 | /**
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394 | * Called by PGMR0DynMapInitVM under the init lock.
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395 | *
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396 | * @returns VBox status code.
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397 | * @param pThis The dynamic mapping cache instance.
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398 | */
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399 | static int pgmR0DynMapSetup(PPGMR0DYNMAP pThis)
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400 | {
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401 | return VINF_SUCCESS;
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402 | }
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403 |
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404 |
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405 | /**
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406 | * Called by PGMR0DynMapInitVM under the init lock.
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407 | *
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408 | * @returns VBox status code.
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409 | * @param pThis The dynamic mapping cache instance.
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410 | */
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411 | static int pgmR0DynMapGrow(PPGMR0DYNMAP pThis)
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412 | {
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413 | return VINF_SUCCESS;
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414 | }
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415 |
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416 |
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417 | /**
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418 | * Shoots down the TLBs for all the cache pages, pgmR0DynMapTearDown helper.
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419 | *
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420 | * @param idCpu The current CPU.
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421 | * @param pvUser1 The dynamic mapping cache instance.
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422 | * @param pvUser2 Unused, NULL.
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423 | */
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424 | static DECLCALLBACK(void) pgmR0DynMapShootDownTlbs(RTCPUID idCpu, void *pvUser1, void *pvUser2)
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425 | {
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426 | Assert(!pvUser2);
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427 | PPGMR0DYNMAP pThis = (PPGMR0DYNMAP)pvUser1;
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428 | AssertPtr(pThis == g_pPGMR0DynMap);
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429 | PPGMR0DYNMAPENTRY paPages = pThis->paPages;
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430 | uint32_t iPage = pThis->cPages;
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431 | while (iPage-- > 0)
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432 | ASMInvalidatePage(paPages[iPage].pvPage);
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433 | }
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434 |
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435 |
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436 | /**
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437 | * Called by PGMR0DynMapTermVM under the init lock.
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438 | *
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439 | * @returns VBox status code.
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440 | * @param pThis The dynamic mapping cache instance.
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441 | */
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442 | static void pgmR0DynMapTearDown(PPGMR0DYNMAP pThis)
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443 | {
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444 | /*
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445 | * Restore the original page table entries
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446 | */
|
---|
447 | PPGMR0DYNMAPENTRY paPages = pThis->paPages;
|
---|
448 | uint32_t iPage = pThis->cPages;
|
---|
449 | if (pThis->fLegacyMode)
|
---|
450 | {
|
---|
451 | X86PGUINT const *paSavedPTEs = (X86PGUINT const *)pThis->pvSavedPTEs;
|
---|
452 | while (iPage-- > 0)
|
---|
453 | {
|
---|
454 | X86PGUINT uOld = paPages[iPage].uPte.pLegacy->u;
|
---|
455 | X86PGUINT uOld2 = uOld; NOREF(uOld2);
|
---|
456 | X86PGUINT uNew = paSavedPTEs[iPage];
|
---|
457 | while (!ASMAtomicCmpXchgExU32(&paPages[iPage].uPte.pLegacy->u, uNew, uOld, &uOld))
|
---|
458 | AssertMsgFailed(("uOld=%#x uOld2=%#x uNew=%#x\n", uOld, uOld2, uNew));
|
---|
459 | }
|
---|
460 | }
|
---|
461 | else
|
---|
462 | {
|
---|
463 | X86PGPAEUINT const *paSavedPTEs = (X86PGPAEUINT const *)pThis->pvSavedPTEs;
|
---|
464 | while (iPage-- > 0)
|
---|
465 | {
|
---|
466 | X86PGPAEUINT uOld = paPages[iPage].uPte.pPae->u;
|
---|
467 | X86PGPAEUINT uOld2 = uOld; NOREF(uOld2);
|
---|
468 | X86PGPAEUINT uNew = paSavedPTEs[iPage];
|
---|
469 | while (!ASMAtomicCmpXchgExU64(&paPages[iPage].uPte.pPae->u, uNew, uOld, &uOld))
|
---|
470 | AssertMsgFailed(("uOld=%#llx uOld2=%#llx uNew=%#llx\n", uOld, uOld2, uNew));
|
---|
471 | }
|
---|
472 | }
|
---|
473 |
|
---|
474 | /*
|
---|
475 | * Shoot down the TLBs on all CPUs before freeing them.
|
---|
476 | * If RTMpOnAll fails, make sure the TLBs are invalidated on the current CPU at least.
|
---|
477 | */
|
---|
478 | int rc = RTMpOnAll(pgmR0DynMapShootDownTlbs, pThis, NULL);
|
---|
479 | AssertRC(rc);
|
---|
480 | if (RT_FAILURE(rc))
|
---|
481 | {
|
---|
482 | iPage = pThis->cPages;
|
---|
483 | while (iPage-- > 0)
|
---|
484 | ASMInvalidatePage(paPages[iPage].pvPage);
|
---|
485 | }
|
---|
486 |
|
---|
487 | /*
|
---|
488 | * Free the segments.
|
---|
489 | */
|
---|
490 | while (pThis->pSegHead)
|
---|
491 | {
|
---|
492 | PPGMR0DYNMAPSEG pSeg = pThis->pSegHead;
|
---|
493 | pThis->pSegHead = pSeg->pNext;
|
---|
494 |
|
---|
495 | int rc;
|
---|
496 | rc = RTR0MemObjFree(pSeg->hMemObjPT, true /* fFreeMappings */); AssertRC(rc);
|
---|
497 | pSeg->hMemObjPT = NIL_RTR0MEMOBJ;
|
---|
498 | rc = RTR0MemObjFree(pSeg->hMemObj, true /* fFreeMappings */); AssertRC(rc);
|
---|
499 | pSeg->hMemObj = NIL_RTR0MEMOBJ;
|
---|
500 | pSeg->pNext = NULL;
|
---|
501 | pSeg->iPage = UINT32_MAX;
|
---|
502 | pSeg->cPages = 0;
|
---|
503 | RTMemFree(pSeg);
|
---|
504 | }
|
---|
505 |
|
---|
506 | /*
|
---|
507 | * Free the arrays and restore the initial state.
|
---|
508 | * The cLoadMax value is left behind for the next setup.
|
---|
509 | */
|
---|
510 | RTMemFree(pThis->paPages);
|
---|
511 | pThis->paPages = NULL;
|
---|
512 | RTMemFree(pThis->pvSavedPTEs);
|
---|
513 | pThis->pvSavedPTEs = NULL;
|
---|
514 | pThis->cPages = 0;
|
---|
515 | pThis->cLoad = 0;
|
---|
516 | }
|
---|
517 |
|
---|
518 |
|
---|
519 | /**
|
---|
520 | * Release references to a page, caller owns the spin lock.
|
---|
521 | *
|
---|
522 | * @param pThis The dynamic mapping cache instance.
|
---|
523 | * @param iPage The page.
|
---|
524 | * @param cRefs The number of references to release.
|
---|
525 | */
|
---|
526 | DECLINLINE(void) pgmR0DynMapReleasePageLocked(PPGMR0DYNMAP pThis, uint32_t iPage, int32_t cRefs)
|
---|
527 | {
|
---|
528 | cRefs = ASMAtomicSubS32(&pThis->paPages[iPage].cRefs, cRefs);
|
---|
529 | AssertMsg(cRefs >= 0, ("%d\n", cRefs));
|
---|
530 | if (!cRefs)
|
---|
531 | pThis->cLoad--;
|
---|
532 | }
|
---|
533 |
|
---|
534 |
|
---|
535 | /**
|
---|
536 | * Release references to a page, caller does not own the spin lock.
|
---|
537 | *
|
---|
538 | * @param pThis The dynamic mapping cache instance.
|
---|
539 | * @param iPage The page.
|
---|
540 | * @param cRefs The number of references to release.
|
---|
541 | */
|
---|
542 | static void pgmR0DynMapReleasePage(PPGMR0DYNMAP pThis, uint32_t iPage, uint32_t cRefs)
|
---|
543 | {
|
---|
544 | RTSPINLOCKTMP Tmp = RTSPINLOCKTMP_INITIALIZER;
|
---|
545 | RTSpinlockAcquire(pThis->hSpinlock, &Tmp);
|
---|
546 | pgmR0DynMapReleasePageLocked(pThis, iPage, cRefs);
|
---|
547 | RTSpinlockRelease(pThis->hSpinlock, &Tmp);
|
---|
548 | }
|
---|
549 |
|
---|
550 |
|
---|
551 | /**
|
---|
552 | * pgmR0DynMapPage worker that deals with the tedious bits.
|
---|
553 | *
|
---|
554 | * @returns The page index on success, UINT32_MAX on failure.
|
---|
555 | * @param pThis The dynamic mapping cache instance.
|
---|
556 | * @param HCPhys The address of the page to be mapped.
|
---|
557 | * @param iPage The page index pgmR0DynMapPage hashed HCPhys to.
|
---|
558 | */
|
---|
559 | static uint32_t pgmR0DynMapPageSlow(PPGMR0DYNMAP pThis, RTHCPHYS HCPhys, uint32_t iPage)
|
---|
560 | {
|
---|
561 | /*
|
---|
562 | * Check if any of the first 5 pages are unreferenced since the caller
|
---|
563 | * already has made sure they aren't matching.
|
---|
564 | */
|
---|
565 | uint32_t const cPages = cPages;
|
---|
566 | PPGMR0DYNMAPENTRY paPages = pThis->paPages;
|
---|
567 | uint32_t iFreePage;
|
---|
568 | if (!paPages[iPage].cRefs)
|
---|
569 | iFreePage = iPage;
|
---|
570 | else if (!paPages[(iPage + 1) % cPages].cRefs)
|
---|
571 | iFreePage = iPage;
|
---|
572 | else if (!paPages[(iPage + 2) % cPages].cRefs)
|
---|
573 | iFreePage = iPage;
|
---|
574 | else if (!paPages[(iPage + 3) % cPages].cRefs)
|
---|
575 | iFreePage = iPage;
|
---|
576 | else if (!paPages[(iPage + 4) % cPages].cRefs)
|
---|
577 | iFreePage = iPage;
|
---|
578 | else
|
---|
579 | {
|
---|
580 | /*
|
---|
581 | * Search for an unused or matching entry.
|
---|
582 | */
|
---|
583 | iFreePage = (iPage + 5) % pThis->cPages;
|
---|
584 | for (;;)
|
---|
585 | {
|
---|
586 | if (paPages[iFreePage].HCPhys == HCPhys)
|
---|
587 | return iFreePage;
|
---|
588 | if (!paPages[iFreePage].cRefs)
|
---|
589 | break;
|
---|
590 |
|
---|
591 | /* advance */
|
---|
592 | iFreePage = (iFreePage + 1) % cPages;
|
---|
593 | if (RT_UNLIKELY(iFreePage != iPage))
|
---|
594 | return UINT32_MAX;
|
---|
595 | }
|
---|
596 | }
|
---|
597 |
|
---|
598 | /*
|
---|
599 | * Setup the new entry.
|
---|
600 | */
|
---|
601 | paPages[iFreePage].HCPhys = HCPhys;
|
---|
602 | RTCpuSetFill(&paPages[iFreePage].PendingSet);
|
---|
603 | if (pThis->fLegacyMode)
|
---|
604 | {
|
---|
605 | X86PGUINT uOld = paPages[iFreePage].uPte.pLegacy->u;
|
---|
606 | X86PGUINT uOld2 = uOld; NOREF(uOld2);
|
---|
607 | X86PGUINT uNew = (uOld & X86_PTE_G | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT)
|
---|
608 | | X86_PTE_P | X86_PTE_A | X86_PTE_D
|
---|
609 | | (HCPhys & X86_PTE_PG_MASK);
|
---|
610 | while (!ASMAtomicCmpXchgExU32(&paPages[iFreePage].uPte.pLegacy->u, uNew, uOld, &uOld))
|
---|
611 | AssertMsgFailed(("uOld=%#x uOld2=%#x uNew=%#x\n", uOld, uOld2, uNew));
|
---|
612 | }
|
---|
613 | else
|
---|
614 | {
|
---|
615 | X86PGPAEUINT uOld = paPages[iFreePage].uPte.pPae->u;
|
---|
616 | X86PGPAEUINT uOld2 = uOld; NOREF(uOld2);
|
---|
617 | X86PGPAEUINT uNew = (uOld & X86_PTE_G | X86_PTE_PAT | X86_PTE_PCD | X86_PTE_PWT)
|
---|
618 | | X86_PTE_P | X86_PTE_A | X86_PTE_D
|
---|
619 | | (HCPhys & X86_PTE_PAE_PG_MASK);
|
---|
620 | while (!ASMAtomicCmpXchgExU64(&paPages[iFreePage].uPte.pPae->u, uNew, uOld, &uOld))
|
---|
621 | AssertMsgFailed(("uOld=%#llx uOld2=%#llx uNew=%#llx\n", uOld, uOld2, uNew));
|
---|
622 | }
|
---|
623 | return iFreePage;
|
---|
624 | }
|
---|
625 |
|
---|
626 |
|
---|
627 | /**
|
---|
628 | * Maps a page into the pool.
|
---|
629 | *
|
---|
630 | * @returns Pointer to the mapping.
|
---|
631 | * @param pThis The dynamic mapping cache instance.
|
---|
632 | * @param HCPhys The address of the page to be mapped.
|
---|
633 | * @param piPage Where to store the page index.
|
---|
634 | */
|
---|
635 | DECLINLINE(void *) pgmR0DynMapPage(PPGMR0DYNMAP pThis, RTHCPHYS HCPhys, uint32_t *piPage)
|
---|
636 | {
|
---|
637 | RTSPINLOCKTMP Tmp = RTSPINLOCKTMP_INITIALIZER;
|
---|
638 | RTSpinlockAcquire(pThis->hSpinlock, &Tmp);
|
---|
639 | AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
|
---|
640 |
|
---|
641 | /*
|
---|
642 | * Find an entry, if possible a matching one. The HCPhys address is hashed
|
---|
643 | * down to a page index, collisions are handled by linear searching. Optimize
|
---|
644 | * for a hit in the first 5 pages.
|
---|
645 | *
|
---|
646 | * To the cheap hits here and defer the tedious searching and inserting
|
---|
647 | * to a helper function.
|
---|
648 | */
|
---|
649 | uint32_t const cPages = cPages;
|
---|
650 | uint32_t iPage = (HCPhys >> PAGE_SHIFT) % cPages;
|
---|
651 | PPGMR0DYNMAPENTRY paPages = pThis->paPages;
|
---|
652 | if (paPages[iPage].HCPhys != HCPhys)
|
---|
653 | {
|
---|
654 | uint32_t iPage2 = (iPage + 1) % cPages;
|
---|
655 | if (paPages[iPage2].HCPhys != HCPhys)
|
---|
656 | {
|
---|
657 | iPage2 = (iPage + 2) % cPages;
|
---|
658 | if (paPages[iPage2].HCPhys != HCPhys)
|
---|
659 | {
|
---|
660 | iPage2 = (iPage + 3) % cPages;
|
---|
661 | if (paPages[iPage2].HCPhys != HCPhys)
|
---|
662 | {
|
---|
663 | iPage2 = (iPage + 4) % cPages;
|
---|
664 | if (paPages[iPage2].HCPhys != HCPhys)
|
---|
665 | {
|
---|
666 | iPage = pgmR0DynMapPageSlow(pThis, HCPhys, iPage);
|
---|
667 | if (RT_UNLIKELY(iPage == UINT32_MAX))
|
---|
668 | {
|
---|
669 | RTSpinlockRelease(pThis->hSpinlock, &Tmp);
|
---|
670 | return NULL;
|
---|
671 | }
|
---|
672 | }
|
---|
673 | else
|
---|
674 | iPage = iPage2;
|
---|
675 | }
|
---|
676 | else
|
---|
677 | iPage = iPage2;
|
---|
678 | }
|
---|
679 | else
|
---|
680 | iPage = iPage2;
|
---|
681 | }
|
---|
682 | else
|
---|
683 | iPage = iPage2;
|
---|
684 | }
|
---|
685 |
|
---|
686 | /*
|
---|
687 | * Reference it, update statistics and get the return address.
|
---|
688 | */
|
---|
689 | if (ASMAtomicIncS32(&paPages[iPage].cRefs) == 1)
|
---|
690 | {
|
---|
691 | pThis->cLoad++;
|
---|
692 | if (pThis->cLoad > pThis->cMaxLoad)
|
---|
693 | pThis->cMaxLoad = pThis->cLoad;
|
---|
694 | Assert(pThis->cLoad <= pThis->cPages);
|
---|
695 | }
|
---|
696 | void *pvPage = paPages[iPage].pvPage;
|
---|
697 |
|
---|
698 | /*
|
---|
699 | * Invalidate the entry?
|
---|
700 | */
|
---|
701 | RTCPUID idRealCpu = RTMpCpuId();
|
---|
702 | bool fInvalidateIt = RTCpuSetIsMember(&paPages[iPage].PendingSet, idRealCpu);
|
---|
703 | if (fInvalidateIt)
|
---|
704 | RTCpuSetDel(&paPages[iPage].PendingSet, idRealCpu);
|
---|
705 |
|
---|
706 | RTSpinlockRelease(pThis->hSpinlock, &Tmp);
|
---|
707 |
|
---|
708 | /*
|
---|
709 | * Do the actual invalidation outside the spinlock.
|
---|
710 | */
|
---|
711 | ASMInvalidatePage(pvPage);
|
---|
712 |
|
---|
713 | *piPage = iPage;
|
---|
714 | return pvPage;
|
---|
715 | }
|
---|
716 |
|
---|
717 |
|
---|
718 | /**
|
---|
719 | * Signals the start of a new set of mappings.
|
---|
720 | *
|
---|
721 | * Mostly for strictness. PGMDynMapHCPage won't work unless this
|
---|
722 | * API is called.
|
---|
723 | *
|
---|
724 | * @param pVCpu The shared data for the current virtual CPU.
|
---|
725 | */
|
---|
726 | VMMDECL(void) PGMDynMapStartAutoSet(PVMCPU pVCpu)
|
---|
727 | {
|
---|
728 | Assert(pVCpu->pgm.s.AutoSet.cEntries == PGMMAPSET_CLOSED);
|
---|
729 | pVCpu->pgm.s.AutoSet.cEntries = 0;
|
---|
730 | }
|
---|
731 |
|
---|
732 |
|
---|
733 | /**
|
---|
734 | * Releases the dynamic memory mappings made by PGMDynMapHCPage and associates
|
---|
735 | * since the PGMDynMapStartAutoSet call.
|
---|
736 | *
|
---|
737 | * @param pVCpu The shared data for the current virtual CPU.
|
---|
738 | */
|
---|
739 | VMMDECL(void) PGMDynMapReleaseAutoSet(PVMCPU pVCpu)
|
---|
740 | {
|
---|
741 | PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
|
---|
742 |
|
---|
743 | /* close the set */
|
---|
744 | uint32_t i = pVCpu->pgm.s.AutoSet.cEntries;
|
---|
745 | AssertMsg(i <= RT_ELEMENTS(pVCpu->pgm.s.AutoSet.aEntries), ("%#x (%u)\n", i, i));
|
---|
746 | pVCpu->pgm.s.AutoSet.cEntries = PGMMAPSET_CLOSED;
|
---|
747 |
|
---|
748 | /* release any pages we're referencing. */
|
---|
749 | if (i != 0 && RT_LIKELY(i <= RT_ELEMENTS(pVCpu->pgm.s.AutoSet.aEntries)))
|
---|
750 | {
|
---|
751 | PPGMR0DYNMAP pThis = g_pPGMR0DynMap;
|
---|
752 | RTSPINLOCKTMP Tmp = RTSPINLOCKTMP_INITIALIZER;
|
---|
753 | RTSpinlockAcquire(pThis->hSpinlock, &Tmp);
|
---|
754 |
|
---|
755 | while (i-- > 0)
|
---|
756 | {
|
---|
757 | uint32_t iPage = pSet->aEntries[i].iPage;
|
---|
758 | Assert(iPage < pThis->cPages);
|
---|
759 | int32_t cRefs = pSet->aEntries[i].cRefs;
|
---|
760 | Assert(cRefs > 0);
|
---|
761 | pgmR0DynMapReleasePageLocked(pThis, iPage, cRefs);
|
---|
762 |
|
---|
763 | pSet->aEntries[i].iPage = UINT16_MAX;
|
---|
764 | pSet->aEntries[i].cRefs = 0;
|
---|
765 | }
|
---|
766 |
|
---|
767 | Assert(pThis->cLoad <= pThis->cPages);
|
---|
768 | RTSpinlockRelease(pThis->hSpinlock, &Tmp);
|
---|
769 | }
|
---|
770 | }
|
---|
771 |
|
---|
772 |
|
---|
773 | /**
|
---|
774 | * Migrates the automatic mapping set of the current vCPU if necessary.
|
---|
775 | *
|
---|
776 | * This is called when re-entering the hardware assisted execution mode after a
|
---|
777 | * nip down to ring-3. We run the risk that the CPU might have change and we
|
---|
778 | * will therefore make sure all the cache entries currently in the auto set will
|
---|
779 | * be valid on the new CPU. If the cpu didn't change nothing will happen as all
|
---|
780 | * the entries will have been flagged as invalidated.
|
---|
781 | *
|
---|
782 | * @param pVCpu The shared data for the current virtual CPU.
|
---|
783 | * @thread EMT
|
---|
784 | */
|
---|
785 | VMMDECL(void) PGMDynMapMigrateAutoSet(PVMCPU pVCpu)
|
---|
786 | {
|
---|
787 | PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
|
---|
788 | uint32_t i = pVCpu->pgm.s.AutoSet.cEntries;
|
---|
789 | AssertMsg(i <= RT_ELEMENTS(pVCpu->pgm.s.AutoSet.aEntries), ("%#x (%u)\n", i, i));
|
---|
790 | if (i != 0 && RT_LIKELY(i <= RT_ELEMENTS(pVCpu->pgm.s.AutoSet.aEntries)))
|
---|
791 | {
|
---|
792 | PPGMR0DYNMAP pThis = g_pPGMR0DynMap;
|
---|
793 | RTCPUID idRealCpu = RTMpCpuId();
|
---|
794 |
|
---|
795 | while (i-- > 0)
|
---|
796 | {
|
---|
797 | Assert(pSet->aEntries[i].cRefs > 0);
|
---|
798 | uint32_t iPage = pSet->aEntries[i].iPage;
|
---|
799 | Assert(iPage < pThis->cPages);
|
---|
800 | if (RTCpuSetIsMember(&pThis->paPages[iPage].PendingSet, idRealCpu))
|
---|
801 | {
|
---|
802 | RTCpuSetDel(&pThis->paPages[iPage].PendingSet, idRealCpu);
|
---|
803 | ASMInvalidatePage(pThis->paPages[iPage].pvPage);
|
---|
804 | }
|
---|
805 | }
|
---|
806 | }
|
---|
807 | }
|
---|
808 |
|
---|
809 |
|
---|
810 | /**
|
---|
811 | * As a final resort for a full auto set, try merge duplicate entries.
|
---|
812 | *
|
---|
813 | * @param pSet The set.
|
---|
814 | */
|
---|
815 | static void pgmDynMapOptimizeAutoSet(PPGMMAPSET pSet)
|
---|
816 | {
|
---|
817 | for (uint32_t i = 0 ; i < pSet->cEntries; i++)
|
---|
818 | {
|
---|
819 | uint16_t const iPage = pSet->aEntries[i].iPage;
|
---|
820 | uint32_t j = i + 1;
|
---|
821 | while (j < pSet->cEntries)
|
---|
822 | {
|
---|
823 | if (pSet->aEntries[j].iPage != iPage)
|
---|
824 | j++;
|
---|
825 | else
|
---|
826 | {
|
---|
827 | /* merge j with i removing j. */
|
---|
828 | pSet->aEntries[i].cRefs += pSet->aEntries[j].cRefs;
|
---|
829 | pSet->cEntries--;
|
---|
830 | if (j < pSet->cEntries)
|
---|
831 | {
|
---|
832 | pSet->aEntries[j] = pSet->aEntries[pSet->cEntries];
|
---|
833 | pSet->aEntries[pSet->cEntries].iPage = UINT16_MAX;
|
---|
834 | pSet->aEntries[pSet->cEntries].cRefs = 0;
|
---|
835 | }
|
---|
836 | else
|
---|
837 | {
|
---|
838 | pSet->aEntries[j].iPage = UINT16_MAX;
|
---|
839 | pSet->aEntries[j].cRefs = 0;
|
---|
840 | }
|
---|
841 | }
|
---|
842 | }
|
---|
843 | }
|
---|
844 | }
|
---|
845 |
|
---|
846 |
|
---|
847 | /* documented elsewhere - a bit of a mess. */
|
---|
848 | VMMDECL(int) PGMDynMapHCPage(PVM pVM, RTHCPHYS HCPhys, void **ppv)
|
---|
849 | {
|
---|
850 | /*
|
---|
851 | * Validate state.
|
---|
852 | */
|
---|
853 | AssertMsgReturn(pVM->pgm.s.pvR0DynMapUsed == g_pPGMR0DynMap,
|
---|
854 | ("%p != %p\n", pVM->pgm.s.pvR0DynMapUsed, g_pPGMR0DynMap),
|
---|
855 | VERR_ACCESS_DENIED);
|
---|
856 | AssertMsg(!(HCPhys & PAGE_OFFSET_MASK), ("HCPhys=%RHp\n", HCPhys));
|
---|
857 | PVMCPU pVCpu = VMMGetCpu(pVM);
|
---|
858 | PPGMMAPSET pSet = &pVCpu->pgm.s.AutoSet;
|
---|
859 | AssertPtrReturn(pVCpu, VERR_INTERNAL_ERROR);
|
---|
860 | AssertMsgReturn(pSet->cEntries > RT_ELEMENTS(pSet->aEntries),
|
---|
861 | ("%#x (%u)\n", pSet->cEntries, pSet->cEntries), VERR_WRONG_ORDER);
|
---|
862 |
|
---|
863 | /*
|
---|
864 | * Map it.
|
---|
865 | */
|
---|
866 | uint32_t iPage;
|
---|
867 | void *pvPage = pgmR0DynMapPage(g_pPGMR0DynMap, HCPhys, &iPage);
|
---|
868 | if (RT_UNLIKELY(!pvPage))
|
---|
869 | {
|
---|
870 | static uint32_t s_cBitched = 0;
|
---|
871 | if (++s_cBitched < 10)
|
---|
872 | LogRel(("PGMDynMapHCPage: cLoad=%u/%u cPages=%u\n",
|
---|
873 | g_pPGMR0DynMap->cLoad, g_pPGMR0DynMap->cMaxLoad, g_pPGMR0DynMap->cPages));
|
---|
874 | return VERR_PGM_DYNMAP_FAILED;
|
---|
875 | }
|
---|
876 |
|
---|
877 | /*
|
---|
878 | * Add the page to the auto reference set.
|
---|
879 | * If it's less than half full, don't bother looking for duplicates.
|
---|
880 | */
|
---|
881 | if (pSet->cEntries < RT_ELEMENTS(pSet->aEntries) / 2)
|
---|
882 | {
|
---|
883 | pSet->aEntries[pSet->cEntries].cRefs = 1;
|
---|
884 | pSet->aEntries[pSet->cEntries].iPage = iPage;
|
---|
885 | }
|
---|
886 | else
|
---|
887 | {
|
---|
888 | Assert(pSet->cEntries <= RT_ELEMENTS(pSet->aEntries));
|
---|
889 | int32_t i = pSet->cEntries;
|
---|
890 | while (i-- > 0)
|
---|
891 | if (pSet->aEntries[i].iPage)
|
---|
892 | {
|
---|
893 | pSet->aEntries[i].cRefs++;
|
---|
894 | break;
|
---|
895 | }
|
---|
896 | if (i < 0)
|
---|
897 | {
|
---|
898 | if (RT_UNLIKELY(pSet->cEntries >= RT_ELEMENTS(pSet->aEntries)))
|
---|
899 | pgmDynMapOptimizeAutoSet(pSet);
|
---|
900 | if (RT_LIKELY(pSet->cEntries < RT_ELEMENTS(pSet->aEntries)))
|
---|
901 | {
|
---|
902 | pSet->aEntries[pSet->cEntries].cRefs = 1;
|
---|
903 | pSet->aEntries[pSet->cEntries].iPage = iPage;
|
---|
904 | }
|
---|
905 | else
|
---|
906 | {
|
---|
907 | /* We're screwed. */
|
---|
908 | pgmR0DynMapReleasePage(g_pPGMR0DynMap, iPage, 1);
|
---|
909 |
|
---|
910 | static uint32_t s_cBitched = 0;
|
---|
911 | if (++s_cBitched < 10)
|
---|
912 | LogRel(("PGMDynMapHCPage: set is full!\n"));
|
---|
913 | return VERR_PGM_DYNMAP_FULL_SET;
|
---|
914 | }
|
---|
915 | }
|
---|
916 | }
|
---|
917 |
|
---|
918 | return VINF_SUCCESS;
|
---|
919 | }
|
---|
920 |
|
---|