| 1 | ; $Id: TRPMR0A.asm 22949 2009-09-11 10:14:48Z vboxsync $
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| 2 | ;; @file
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| 3 | ; TRPM - Host Context Ring-0
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 | ; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 18 | ; Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 19 | ; additional information or have any questions.
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| 20 | ;
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| 21 |
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| 22 | ;*******************************************************************************
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| 23 | ;* Header Files *
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| 24 | ;*******************************************************************************
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| 25 | %include "VBox/asmdefs.mac"
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| 26 | %include "VBox/x86.mac"
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| 27 |
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| 28 |
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| 29 | BEGINCODE
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| 30 |
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| 31 | ;;
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| 32 | ; Calls the interrupt gate as if we received an interrupt while in Ring-0.
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| 33 | ;
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| 34 | ; @param uIP x86:[ebp+8] msc:rcx gcc:rdi The interrupt gate IP.
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| 35 | ; @param SelCS x86:[ebp+12] msc:dx gcc:si The interrupt gate CS.
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| 36 | ; @param RSP msc:r8 gcc:rdx The interrupt gate RSP. ~0 if no stack switch should take place. (only AMD64)
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| 37 | ;DECLASM(void) trpmR0DispatchHostInterrupt(RTR0UINTPTR uIP, RTSEL SelCS, RTR0UINTPTR RSP);
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| 38 | ALIGNCODE(16)
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| 39 | BEGINPROC trpmR0DispatchHostInterrupt
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| 40 | push xBP
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| 41 | mov xBP, xSP
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| 42 |
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| 43 | %ifdef RT_ARCH_AMD64
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| 44 | mov r11, rsp ; save the RSP for the iret frame.
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| 45 | and rsp, 0fffffffffffffff0h ; align the stack. (do it unconditionally saves some jump mess)
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| 46 |
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| 47 | ; switch stack?
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| 48 | %ifdef ASM_CALL64_MSC
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| 49 | cmp r8, 0ffffffffffffffffh
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| 50 | je .no_stack_switch
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| 51 | mov rsp, r8
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| 52 | %else
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| 53 | cmp rdx, 0ffffffffffffffffh
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| 54 | je .no_stack_switch
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| 55 | mov rsp, rdx
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| 56 | %endif
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| 57 | .no_stack_switch:
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| 58 |
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| 59 | ; create the iret frame
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| 60 | push 0 ; SS
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| 61 | push r11 ; RSP
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| 62 | pushfq ; RFLAGS
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| 63 | and dword [rsp], ~X86_EFL_IF
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| 64 | mov ax, cs
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| 65 | push rax ; CS
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| 66 | lea r10, [.return wrt rip] ; RIP
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| 67 | push r10
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| 68 |
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| 69 | ; create the retf frame
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| 70 | %ifdef ASM_CALL64_MSC
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| 71 | movzx rdx, dx
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| 72 | cmp rdx, r11
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| 73 | je .dir_jump
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| 74 | push rdx
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| 75 | push rcx
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| 76 | %else
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| 77 | movzx rsi, si
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| 78 | cmp rsi, r11
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| 79 | je .dir_jump
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| 80 | push rsi
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| 81 | push rdi
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| 82 | %endif
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| 83 |
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| 84 | ; dispatch it
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| 85 | db 048h
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| 86 | retf
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| 87 |
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| 88 | ; dispatch it by a jmp (don't mess up the IST stack)
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| 89 | .dir_jump:
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| 90 | %ifdef ASM_CALL64_MSC
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| 91 | jmp rcx
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| 92 | %else
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| 93 | jmp rdi
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| 94 | %endif
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| 95 |
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| 96 | %else ; 32-bit:
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| 97 | mov ecx, [ebp + 8] ; uIP
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| 98 | movzx edx, word [ebp + 12] ; SelCS
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| 99 |
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| 100 | ; create the iret frame
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| 101 | pushfd ; EFLAGS
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| 102 | and dword [esp], ~X86_EFL_IF
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| 103 | push cs ; CS
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| 104 | push .return ; EIP
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| 105 |
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| 106 | ; create the retf frame
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| 107 | push edx
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| 108 | push ecx
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| 109 |
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| 110 | ; dispatch it!
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| 111 | retf
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| 112 | %endif
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| 113 | .return:
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| 114 | cli
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| 115 |
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| 116 | leave
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| 117 | ret
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| 118 | ENDPROC trpmR0DispatchHostInterrupt
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| 119 |
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| 120 |
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| 121 | ;;
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| 122 | ; Issues a software interrupt to the specified interrupt vector.
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| 123 | ;
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| 124 | ; @param uActiveVector x86:[esp+4] msc:rcx gcc:rdi The vector number.
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| 125 | ;
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| 126 | ;DECLASM(void) trpmR0DispatchHostInterruptSimple(RTUINT uActiveVector);
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| 127 | ALIGNCODE(16)
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| 128 | BEGINPROC trpmR0DispatchHostInterruptSimple
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| 129 | %ifdef RT_ARCH_X86
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| 130 | mov eax, [esp + 4]
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| 131 | jmp dword [.jmp_table + eax * 4]
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| 132 | %else
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| 133 | lea r9, [.jmp_table wrt rip]
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| 134 | %ifdef ASM_CALL64_MSC
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| 135 | jmp qword [r9 + rcx * 8]
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| 136 | %else
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| 137 | jmp qword [r9 + rdi * 8]
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| 138 | %endif
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| 139 | %endif
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| 140 |
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| 141 | ALIGNCODE(4)
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| 142 | .jmp_table:
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| 143 | %assign i 0
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| 144 | %rep 256
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| 145 | RTCCPTR_DEF .int_ %+ i
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| 146 | %assign i i+1
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| 147 | %endrep
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| 148 |
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| 149 | %assign i 0
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| 150 | %rep 256
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| 151 | ALIGNCODE(4)
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| 152 | .int_ %+ i:
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| 153 | int i
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| 154 | ret
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| 155 | %assign i i+1
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| 156 | %endrep
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| 157 |
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| 158 | ENDPROC trpmR0DispatchHostInterruptSimple
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| 159 |
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