1 | ; $Id: TRPMR0A.asm 69221 2017-10-24 15:07:46Z vboxsync $
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2 | ;; @file
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3 | ; TRPM - Host Context Ring-0
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4 | ;
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5 |
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6 | ;
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7 | ; Copyright (C) 2006-2017 Oracle Corporation
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8 | ;
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9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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10 | ; available from http://www.virtualbox.org. This file is free software;
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11 | ; you can redistribute it and/or modify it under the terms of the GNU
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12 | ; General Public License (GPL) as published by the Free Software
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13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | ;
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17 |
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18 | ;*******************************************************************************
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19 | ;* Header Files *
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20 | ;*******************************************************************************
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21 | %include "VBox/asmdefs.mac"
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22 | %include "iprt/x86.mac"
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23 |
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24 |
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25 | BEGINCODE
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26 |
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27 | ;;
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28 | ; Calls the interrupt gate as if we received an interrupt while in Ring-0.
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29 | ;
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30 | ; @param uIP x86:[ebp+8] msc:rcx gcc:rdi The interrupt gate IP.
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31 | ; @param SelCS x86:[ebp+12] msc:dx gcc:si The interrupt gate CS.
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32 | ; @param RSP msc:r8 gcc:rdx The interrupt gate RSP. ~0 if no stack switch should take place. (only AMD64)
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33 | ;DECLASM(void) trpmR0DispatchHostInterrupt(RTR0UINTPTR uIP, RTSEL SelCS, RTR0UINTPTR RSP);
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34 | ALIGNCODE(16)
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35 | BEGINPROC trpmR0DispatchHostInterrupt
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36 | push xBP
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37 | mov xBP, xSP
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38 |
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39 | %ifdef RT_ARCH_AMD64
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40 | mov r11, rsp ; save the RSP for the iret frame.
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41 | and rsp, 0fffffffffffffff0h ; align the stack. (do it unconditionally saves some jump mess)
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42 |
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43 | ; switch stack?
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44 | %ifdef ASM_CALL64_MSC
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45 | cmp r8, 0ffffffffffffffffh
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46 | je .no_stack_switch
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47 | mov rsp, r8
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48 | %else
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49 | cmp rdx, 0ffffffffffffffffh
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50 | je .no_stack_switch
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51 | mov rsp, rdx
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52 | %endif
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53 | .no_stack_switch:
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54 |
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55 | ; create the iret frame
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56 | push 0 ; SS
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57 | push r11 ; RSP
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58 | pushfq ; RFLAGS
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59 | and dword [rsp], ~X86_EFL_IF
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60 | mov ax, cs
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61 | push rax ; CS
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62 | lea r10, [.return wrt rip] ; RIP
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63 | push r10
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64 |
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65 | ; create the retf frame
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66 | %ifdef ASM_CALL64_MSC
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67 | movzx rdx, dx
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68 | cmp rdx, r11
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69 | je .dir_jump
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70 | push rdx
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71 | push rcx
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72 | %else
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73 | movzx rsi, si
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74 | cmp rsi, r11
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75 | je .dir_jump
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76 | push rsi
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77 | push rdi
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78 | %endif
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79 |
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80 | ; dispatch it
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81 | db 048h
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82 | retf
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83 |
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84 | ; dispatch it by a jmp (don't mess up the IST stack)
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85 | .dir_jump:
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86 | %ifdef ASM_CALL64_MSC
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87 | jmp rcx
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88 | %else
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89 | jmp rdi
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90 | %endif
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91 |
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92 | %else ; 32-bit:
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93 | mov ecx, [ebp + 8] ; uIP
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94 | movzx edx, word [ebp + 12] ; SelCS
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95 |
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96 | ; create the iret frame
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97 | pushfd ; EFLAGS
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98 | and dword [esp], ~X86_EFL_IF
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99 | push cs ; CS
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100 | push .return ; EIP
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101 |
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102 | ; create the retf frame
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103 | push edx
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104 | push ecx
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105 |
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106 | ; dispatch it!
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107 | retf
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108 | %endif
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109 | .return:
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110 | cli
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111 |
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112 | leave
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113 | ret
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114 | ENDPROC trpmR0DispatchHostInterrupt
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115 |
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116 |
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117 | ;;
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118 | ; Issues a software interrupt to the specified interrupt vector.
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119 | ;
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120 | ; @param uActiveVector x86:[esp+4] msc:rcx gcc:rdi The vector number.
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121 | ;
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122 | ;DECLASM(void) trpmR0DispatchHostInterruptSimple(RTUINT uActiveVector);
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123 | ALIGNCODE(16)
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124 | BEGINPROC trpmR0DispatchHostInterruptSimple
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125 | %ifdef RT_ARCH_X86
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126 | mov eax, [esp + 4]
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127 | jmp dword [.jmp_table + eax * 4]
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128 | %else
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129 | lea r9, [.jmp_table wrt rip]
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130 | %ifdef ASM_CALL64_MSC
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131 | jmp qword [r9 + rcx * 8]
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132 | %else
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133 | jmp qword [r9 + rdi * 8]
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134 | %endif
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135 | %endif
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136 |
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137 | ALIGNCODE(4)
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138 | .jmp_table:
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139 | %assign i 0
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140 | %rep 256
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141 | RTCCPTR_DEF .int_ %+ i
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142 | %assign i i+1
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143 | %endrep
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144 |
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145 | %assign i 0
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146 | %rep 256
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147 | ALIGNCODE(4)
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148 | .int_ %+ i:
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149 | int i
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150 | ret
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151 | %assign i i+1
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152 | %endrep
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153 |
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154 | ENDPROC trpmR0DispatchHostInterruptSimple
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155 |
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