VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 60652

Last change on this file since 60652 was 60652, checked in by vboxsync, 9 years ago

VMM/APIC: More flow logging.
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1/* $Id: APIC.cpp 60652 2016-04-22 14:34:46Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37/** The current APIC saved state version. */
38#define APIC_SAVED_STATE_VERSION 4
39/** The saved state version used by VirtualBox 5.0 and
40 * earlier. */
41#define APIC_SAVED_STATE_VERSION_VBOX_50 3
42/** The saved state version used by VirtualBox v3 and earlier.
43 * This does not include the config. */
44#define APIC_SAVED_STATE_VERSION_VBOX_30 2
45/** Some ancient version... */
46#define APIC_SAVED_STATE_VERSION_ANCIENT 1
47
48
49/*********************************************************************************************************************************
50* Global Variables *
51*********************************************************************************************************************************/
52/** Saved state field descriptors for XAPICPAGE. */
53static const SSMFIELD g_aXApicPageFields[] =
54{
55 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
56 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
57 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
58 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
59 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
60 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
61 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
62 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
63 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
64 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
65 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
66 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
67 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
68 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
69 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
70 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
71 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
72 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
73 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
74 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
75 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
76 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
77 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
78 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
79 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
80 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
81 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
82 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
83 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
84 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
85 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
86 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
87 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
88 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
89 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
90 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
91 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
92 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
93 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
94 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
95 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
96 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
97 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
98 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
99 SSMFIELD_ENTRY_TERM()
100};
101
102/** Saved state field descriptors for X2APICPAGE. */
103static const SSMFIELD g_aX2ApicPageFields[] =
104{
105 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
106 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
107 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
108 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
109 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
110 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
111 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
112 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
113 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
114 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
115 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
116 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
117 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
118 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
119 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
120 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
121 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
122 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
123 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
124 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
125 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
126 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
127 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
128 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
129 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
130 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
131 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
132 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
133 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
134 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
135 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
136 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
137 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
138 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
139 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
140 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
141 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
142 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
143 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
144 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
145 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
146 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
147 SSMFIELD_ENTRY_TERM()
148};
149
150/** Saved state field descriptors for APICPIB. */
151static const SSMFIELD g_aApicPibFields[] =
152{
153 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[0]),
154 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[1]),
155 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[2]),
156 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[3]),
157 SSMFIELD_ENTRY(APICPIB, fOutstandingNotification),
158 SSMFIELD_ENTRY_TERM()
159};
160
161/**
162 * Initializes per-VCPU APIC to the state following an INIT reset
163 * ("Wait-for-SIPI" state).
164 *
165 * @param pVCpu The cross context virtual CPU structure.
166 */
167static void apicR3InitIpi(PVMCPU pVCpu)
168{
169 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
170 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
171
172 /*
173 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
174 * and AMD spec 16.3.2 "APIC Registers".
175 */
176 memset((void *)&pXApicPage->irr, 0, sizeof(pXApicPage->irr));
177 memset((void *)&pXApicPage->isr, 0, sizeof(pXApicPage->isr));
178 memset((void *)&pXApicPage->tmr, 0, sizeof(pXApicPage->tmr));
179 memset((void *)&pXApicPage->icr_hi, 0, sizeof(pXApicPage->icr_hi));
180 memset((void *)&pXApicPage->icr_lo, 0, sizeof(pXApicPage->icr_lo));
181 memset((void *)&pXApicPage->ldr, 0, sizeof(pXApicPage->ldr));
182 memset((void *)&pXApicPage->tpr, 0, sizeof(pXApicPage->tpr));
183 memset((void *)&pXApicPage->timer_icr, 0, sizeof(pXApicPage->timer_icr));
184 memset((void *)&pXApicPage->timer_ccr, 0, sizeof(pXApicPage->timer_ccr));
185 memset((void *)&pXApicPage->timer_dcr, 0, sizeof(pXApicPage->timer_dcr));
186
187 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
188 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
189
190 /** @todo CMCI. */
191
192 memset((void *)&pXApicPage->lvt_timer, 0, sizeof(pXApicPage->lvt_timer));
193 pXApicPage->lvt_timer.u.u1Mask = 1;
194
195#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
196 memset((void *)&pXApicPage->lvt_thermal, 0, sizeof(pXApicPage->lvt_thermal));
197 pXApicPage->lvt_thermal.u.u1Mask = 1;
198#endif
199
200 memset((void *)&pXApicPage->lvt_perf, 0, sizeof(pXApicPage->lvt_perf));
201 pXApicPage->lvt_perf.u.u1Mask = 1;
202
203 memset((void *)&pXApicPage->lvt_lint0, 0, sizeof(pXApicPage->lvt_lint0));
204 pXApicPage->lvt_lint0.u.u1Mask = 1;
205
206 memset((void *)&pXApicPage->lvt_lint1, 0, sizeof(pXApicPage->lvt_lint1));
207 pXApicPage->lvt_lint1.u.u1Mask = 1;
208
209 memset((void *)&pXApicPage->lvt_error, 0, sizeof(pXApicPage->lvt_error));
210 pXApicPage->lvt_error.u.u1Mask = 1;
211
212 memset((void *)&pXApicPage->svr, 0, sizeof(pXApicPage->svr));
213 pXApicPage->svr.u.u8SpuriousVector = 0xff;
214
215 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
216 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
217 memset((void *)&pX2ApicPage->self_ipi, 0, sizeof(pX2ApicPage->self_ipi));
218
219 /* Clear the pending-interrupt bitmaps. */
220 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
221 memset((void *)&pApicCpu->ApicPibLevel, 0, sizeof(APICPIB));
222 memset((void *)pApicCpu->pvApicPibR3, 0, sizeof(APICPIB));
223}
224
225
226/**
227 * Resets the APIC base MSR.
228 *
229 * @param pVCpu The cross context virtual CPU structure.
230 */
231static void apicR3ResetBaseMsr(PVMCPU pVCpu)
232{
233 /*
234 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
235 *
236 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
237 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
238 *
239 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
240 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
241 */
242 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
243 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
244 pApicCpu->uApicBaseMsr = XAPIC_APICBASE_PHYSADDR
245 | MSR_APICBASE_XAPIC_ENABLE_BIT;
246 if (pVCpu->idCpu == 0)
247 pApicCpu->uApicBaseMsr |= MSR_APICBASE_BOOTSTRAP_CPU_BIT;
248}
249
250
251/**
252 * Initializes per-VCPU APIC to the state following a power-up or hardware
253 * reset.
254 *
255 * @param pVCpu The cross context virtual CPU structure.
256 * @param fResetApicBaseMsr Whether to reset the APIC base MSR.
257 */
258VMMR3_INT_DECL(void) APICR3Reset(PVMCPU pVCpu, bool fResetApicBaseMsr)
259{
260 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
261
262 LogFlow(("APIC%u: APICR3Reset: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
263
264#ifdef VBOX_STRICT
265 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
266 uint32_t uEax, uEbx, uEcx, uEdx;
267 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
268 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
269 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
270#endif
271
272 /*
273 * The state following a power-up or reset is a superset of the INIT state.
274 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
275 */
276 apicR3InitIpi(pVCpu);
277
278 /*
279 * The APIC version register is read-only, so just initialize it here.
280 * It is not clear from the specs, where exactly it is initalized.
281 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
282 */
283 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
284#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
285 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
286 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
287 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
288#else
289# error "Implement Pentium and P6 family APIC architectures"
290#endif
291
292 /** @todo It isn't clear in the spec. where exactly the default base address
293 * is (re)initialized, atm we do it here in Reset. */
294 if (fResetApicBaseMsr)
295 apicR3ResetBaseMsr(pVCpu);
296
297 /*
298 * Initialize the APIC ID register to xAPIC format.
299 */
300 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
301 pXApicPage->id.u8ApicId = pVCpu->idCpu;
302}
303
304
305/**
306 * Receives an INIT IPI.
307 *
308 * @param pVCpu The cross context virtual CPU structure.
309 */
310VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
311{
312 VMCPU_ASSERT_EMT(pVCpu);
313 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
314 apicR3InitIpi(pVCpu);
315}
316
317
318/**
319 * Helper for dumping an APIC 256-bit sparse register.
320 *
321 * @param pApicReg The APIC 256-bit spare register.
322 * @param pHlp The debug output helper.
323 */
324static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
325{
326 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
327 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
328 XAPIC256BITREG ApicReg;
329 RT_ZERO(ApicReg);
330
331 pHlp->pfnPrintf(pHlp, " ");
332 for (ssize_t i = cFragments - 1; i >= 0; i--)
333 {
334 uint32_t const uFragment = pApicReg->u[i].u32Reg;
335 ApicReg.u[i].u32Reg = uFragment;
336 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
337 }
338 pHlp->pfnPrintf(pHlp, "\n");
339
340 size_t cPending = 0;
341 pHlp->pfnPrintf(pHlp, " Pending:\n");
342 pHlp->pfnPrintf(pHlp, " ");
343 for (ssize_t i = cFragments - 1; i >= 0; i--)
344 {
345 uint32_t uFragment = ApicReg.u[i].u32Reg;
346 if (uFragment)
347 {
348 do
349 {
350 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
351 --idxSetBit;
352 ASMBitClear(&uFragment, idxSetBit);
353
354 idxSetBit += (i * cBitsPerFragment);
355 pHlp->pfnPrintf(pHlp, " %02x", idxSetBit);
356 ++cPending;
357 } while (uFragment);
358 }
359 }
360 if (!cPending)
361 pHlp->pfnPrintf(pHlp, " None");
362 pHlp->pfnPrintf(pHlp, "\n");
363}
364
365
366/**
367 * Dumps basic APIC state.
368 *
369 * @param pVCpu The cross context virtual CPU structure.
370 * @param pHlp The debug output helper.
371 */
372static void apicR3DbgInfoBasic(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
373{
374 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
375 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
376 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
377
378 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
379 APICMODE const enmMode = apicGetMode(uBaseMsr);
380 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
381
382 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC:\n", pVCpu->idCpu);
383 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
384 MSR_APICBASE_GET_PHYSADDR(uBaseMsr));
385 pHlp->pfnPrintf(pHlp, " Mode = %#x (%s)\n", enmMode, apicGetModeName(enmMode));
386 if (fX2ApicMode)
387 {
388 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
389 pX2ApicPage->id.u32ApicId);
390 }
391 else
392 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
393 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
394 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
395 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
396 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
397 if (!fX2ApicMode)
398 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
399 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
400 pHlp->pfnPrintf(pHlp, " Task-priority class = %u\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr));
401 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %u\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
402 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
403 pHlp->pfnPrintf(pHlp, " Processor-priority class = %u\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr));
404 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %u\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
405 if (!fX2ApicMode)
406 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
407 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
408 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
409 : pXApicPage->ldr.u.u8LogicalApicId);
410 if (!fX2ApicMode)
411 {
412 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
413 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
414 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
415 }
416 pHlp->pfnPrintf(pHlp, " SVR\n");
417 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
418 pXApicPage->svr.u.u8SpuriousVector);
419 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
420 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
421 pHlp->pfnPrintf(pHlp, " ISR\n");
422 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
423 pHlp->pfnPrintf(pHlp, " TMR\n");
424 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
425 pHlp->pfnPrintf(pHlp, " IRR\n");
426 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
427 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
428 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
429 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
430 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
431 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
432 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
433 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
434 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
435 pXApicPage->icr_lo.u.u8Vector);
436 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
437 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
438 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
439 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
440 if (!fX2ApicMode)
441 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
442 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
443 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
444 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
445 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
446 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
447 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
448 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
449 : pXApicPage->icr_hi.u.u8Dest);
450}
451
452
453/**
454 * Helper for dumping the LVT timer.
455 *
456 * @param pVCpu The cross context virtual CPU structure.
457 * @param pHlp The debug output helper.
458 */
459static void apicR3DbgInfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
460{
461 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
462 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
463 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
464 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
465 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
466 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
467 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
468 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
469 pHlp->pfnPrintf(pHlp, "\n");
470}
471
472
473/**
474 * Dumps APIC Local Vector Table (LVT) state.
475 *
476 * @param pVCpu The cross context virtual CPU structure.
477 * @param pHlp The debug output helper.
478 */
479static void apicR3DbgInfoLvt(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
480{
481 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
482
483 apicR3DbgInfoLvtTimer(pVCpu, pHlp);
484
485#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
486 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
487 pHlp->pfnPrintf(pHlp, "LVT Thermal = %#RX32)\n", uLvtThermal);
488 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_thermal.u.u8Vector, pXApicPage->lvt_thermal.u.u8Vector);
489 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_thermal.u.u3DeliveryMode,
490 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_thermal.u.u3DeliveryMode));
491 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_thermal.u.u1DeliveryStatus);
492 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtThermal));
493 pHlp->pfnPrintf(pHlp, "\n");
494#endif
495
496 uint32_t const uLvtPerf = pXApicPage->lvt_perf.all.u32LvtPerf;
497 pHlp->pfnPrintf(pHlp, "LVT Perf = %#RX32\n", uLvtPerf);
498 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_perf.u.u8Vector, pXApicPage->lvt_perf.u.u8Vector);
499 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_perf.u.u3DeliveryMode,
500 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_perf.u.u3DeliveryMode));
501 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_perf.u.u1DeliveryStatus);
502 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtPerf));
503 pHlp->pfnPrintf(pHlp, "\n");
504
505 uint32_t const uLvtLint0 = pXApicPage->lvt_lint0.all.u32LvtLint0;
506 pHlp->pfnPrintf(pHlp, "LVT LINT0 = %#RX32\n", uLvtLint0);
507 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_lint0.u.u8Vector, pXApicPage->lvt_lint0.u.u8Vector);
508 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_lint0.u.u3DeliveryMode,
509 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_lint0.u.u3DeliveryMode));
510 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_lint0.u.u1DeliveryStatus);
511 pHlp->pfnPrintf(pHlp, " Pin polarity = %u\n", pXApicPage->lvt_lint0.u.u1IntrPolarity);
512 pHlp->pfnPrintf(pHlp, " Remote IRR = %u\n", pXApicPage->lvt_lint0.u.u1RemoteIrr);
513 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->lvt_lint0.u.u1TriggerMode,
514 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->lvt_lint0.u.u1TriggerMode));
515 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtLint0));
516 pHlp->pfnPrintf(pHlp, "\n");
517
518 uint32_t const uLvtLint1 = pXApicPage->lvt_lint1.all.u32LvtLint1;
519 pHlp->pfnPrintf(pHlp, "LVT LINT1 = %#RX32\n", uLvtLint1);
520 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_lint1.u.u8Vector, pXApicPage->lvt_lint1.u.u8Vector);
521 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_lint1.u.u3DeliveryMode,
522 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_lint1.u.u3DeliveryMode));
523 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_lint1.u.u1DeliveryStatus);
524 pHlp->pfnPrintf(pHlp, " Pin polarity = %u\n", pXApicPage->lvt_lint1.u.u1IntrPolarity);
525 pHlp->pfnPrintf(pHlp, " Remote IRR = %u\n", pXApicPage->lvt_lint1.u.u1RemoteIrr);
526 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->lvt_lint1.u.u1TriggerMode,
527 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->lvt_lint1.u.u1TriggerMode));
528 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtLint1));
529 pHlp->pfnPrintf(pHlp, "\n");
530
531 uint32_t const uLvtError = pXApicPage->lvt_error.all.u32LvtError;
532 pHlp->pfnPrintf(pHlp, "LVT Error = %#RX32\n", uLvtError);
533 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_error.u.u8Vector, pXApicPage->lvt_error.u.u8Vector);
534 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_error.u.u1DeliveryStatus);
535 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtError));
536 pHlp->pfnPrintf(pHlp, "\n");
537}
538
539
540/**
541 * Dumps APIC Timer state.
542 *
543 * @param pVCpu The cross context virtual CPU structure.
544 * @param pHlp The debug output helper.
545 */
546static void apicR3DbgInfoTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
547{
548 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
549 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
550
551 pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
552 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
553 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
554 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
555 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
556 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
557 pHlp->pfnPrintf(pHlp, "\n");
558
559 apicR3DbgInfoLvtTimer(pVCpu, pHlp);
560}
561
562
563/**
564 * @callback_method_impl{FNDBGFHANDLERDEV,
565 * Dumps the APIC state according to given argument for debugging purposes.}
566 */
567static DECLCALLBACK(void) apicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
568{
569 PVM pVM = PDMDevHlpGetVM(pDevIns);
570 PVMCPU pVCpu = VMMGetCpu(pVM);
571 Assert(pVCpu);
572
573 if (pszArgs == NULL || !*pszArgs || !strcmp(pszArgs, "basic"))
574 apicR3DbgInfoBasic(pVCpu, pHlp);
575 else if (!strcmp(pszArgs, "lvt"))
576 apicR3DbgInfoLvt(pVCpu, pHlp);
577 else if (!strcmp(pszArgs, "timer"))
578 apicR3DbgInfoTimer(pVCpu, pHlp);
579 else
580 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'\n");
581}
582
583
584/**
585 * Converts legacy PDMAPICMODE to the new APICMODE enum.
586 *
587 * @returns The new APIC mode.
588 * @param enmLegacyMode The legacy mode to convert.
589 */
590static APICMODE apicR3ConvertFromLegacyApicMode(PDMAPICMODE enmLegacyMode)
591{
592 switch (enmLegacyMode)
593 {
594 case PDMAPICMODE_NONE: return APICMODE_DISABLED;
595 case PDMAPICMODE_APIC: return APICMODE_XAPIC;
596 case PDMAPICMODE_X2APIC: return APICMODE_X2APIC;
597 case PDMAPICMODE_INVALID: return APICMODE_INVALID;
598 default: break;
599 }
600 return (APICMODE)enmLegacyMode;
601}
602
603
604/**
605 * Converts the new APICMODE enum to the legacy PDMAPICMODE enum.
606 *
607 * @returns The legacy APIC mode.
608 * @param enmMode The APIC mode to convert.
609 */
610static PDMAPICMODE apicR3ConvertToLegacyApicMode(APICMODE enmMode)
611{
612 switch (enmMode)
613 {
614 case APICMODE_DISABLED: return PDMAPICMODE_NONE;
615 case APICMODE_XAPIC: return PDMAPICMODE_APIC;
616 case APICMODE_X2APIC: return PDMAPICMODE_X2APIC;
617 case APICMODE_INVALID: return PDMAPICMODE_INVALID;
618 default: break;
619 }
620 return (PDMAPICMODE)enmMode;
621}
622
623
624#ifdef DEBUG_ramshankar
625/**
626 * Helper for dumping per-VCPU APIC state to the release logger.
627 *
628 * This is primarily concerned about the APIC state relevant for saved-states.
629 *
630 * @param pVCpu The cross context virtual CPU structure.
631 * @param pszPrefix A caller supplied prefix before dumping the state.
632 */
633static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix)
634{
635 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
636
637 /* The auxiliary state. */
638 LogRel(("APIC%u: %s\n", pVCpu->idCpu, pszPrefix));
639 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
640 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
641
642 /* The timer. */
643 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
644 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
645 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
646
647 /* The PIBs. */
648 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
649 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
650
651 /* The APIC page. */
652 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
653}
654#endif
655
656
657/**
658 * Worker for saving per-VM APIC data.
659 *
660 * @returns VBox status code.
661 * @param pVM The cross context VM structure.
662 * @param pSSM The SSM handle.
663 */
664static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
665{
666 PAPIC pApic = VM_TO_APIC(pVM);
667 SSMR3PutU32(pSSM, pVM->cCpus);
668 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
669 return SSMR3PutU32(pSSM, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode));
670}
671
672
673/**
674 * Worker for loading per-VM APIC data.
675 *
676 * @returns VBox status code.
677 * @param pVM The cross context VM structure.
678 * @param pSSM The SSM handle.
679 */
680static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
681{
682 PAPIC pApic = VM_TO_APIC(pVM);
683
684 /* Load and verify number of CPUs. */
685 uint32_t cCpus;
686 int rc = SSMR3GetU32(pSSM, &cCpus);
687 AssertRCReturn(rc, rc);
688 if (cCpus != pVM->cCpus)
689 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
690
691 /* Load and verify I/O APIC presence. */
692 bool fIoApicPresent;
693 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
694 AssertRCReturn(rc, rc);
695 if (fIoApicPresent != pApic->fIoApicPresent)
696 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
697 fIoApicPresent, pApic->fIoApicPresent);
698
699 /* Load and verify configured APIC mode. */
700 uint32_t uLegacyApicMode;
701 rc = SSMR3GetU32(pSSM, &uLegacyApicMode);
702 AssertRCReturn(rc, rc);
703 APICMODE const enmApicMode = apicR3ConvertFromLegacyApicMode((PDMAPICMODE)uLegacyApicMode);
704 if (enmApicMode != pApic->enmOriginalMode)
705 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%#x(%#x) config=%#x(%#x)"),
706 uLegacyApicMode, enmApicMode, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode),
707 pApic->enmOriginalMode);
708 return VINF_SUCCESS;
709}
710
711
712/**
713 * @copydoc FNSSMDEVLIVEEXEC
714 */
715static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
716{
717 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
718 PVM pVM = PDMDevHlpGetVM(pApicDev->pDevInsR3);
719
720 LogFlow(("APIC: apicR3LiveExec: uPass=%u\n", uPass));
721
722 int rc = apicR3SaveVMData(pVM, pSSM);
723 AssertRCReturn(rc, rc);
724 return VINF_SSM_DONT_CALL_AGAIN;
725}
726
727
728/**
729 * @copydoc FNSSMDEVSAVEEXEC
730 */
731static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
732{
733 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
734 PVM pVM = PDMDevHlpGetVM(pDevIns);
735 PAPIC pApic = VM_TO_APIC(pVM);
736 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
737
738 LogFlow(("APIC: apicR3SaveExec\n"));
739
740 /* Save per-VM data. */
741 int rc = apicR3SaveVMData(pVM, pSSM);
742 AssertRCReturn(rc, rc);
743
744 /* Save per-VCPU data.*/
745 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
746 {
747 PVMCPU pVCpu = &pVM->aCpus[idCpu];
748 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
749
750 /* Save the auxiliary data. */
751 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
752 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
753
754 /* Save the APIC page. */
755 if (XAPIC_IN_X2APIC_MODE(pVCpu))
756 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
757 else
758 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
759
760 /* Save the PIBs: In theory, we could push them to vIRR and avoid saving them here, but
761 with posted-interrupts we can't at this point as HM is paralyzed, so just save PIBs always. */
762 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPibR3, &g_aApicPibFields[0]);
763 SSMR3PutStruct(pSSM, (const void *)&pApicCpu->ApicPibLevel, &g_aApicPibFields[0]);
764
765 /* Save the timer. */
766 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
767 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
768
769#ifdef DEBUG_ramshankar
770 apicR3DumpState(pVCpu, "Saved state:");
771#endif
772 }
773
774 return rc;
775}
776
777
778/**
779 * @copydoc FNSSMDEVLOADEXEC
780 */
781static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
782{
783 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
784 PVM pVM = PDMDevHlpGetVM(pDevIns);
785 PAPIC pApic = VM_TO_APIC(pVM);
786 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
787
788 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%u\n", uVersion, uPass));
789
790 /* Weed out invalid versions. */
791 if ( uVersion != APIC_SAVED_STATE_VERSION
792 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
793 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
794 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
795 {
796 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
797 }
798
799 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
800 {
801 int rc2 = apicR3LoadVMData(pVM, pSSM);
802 AssertRCReturn(rc2, rc2);
803
804 if (uVersion == APIC_SAVED_STATE_VERSION)
805 { /* Load any new additional per-VM data. */ }
806 }
807
808 if (uPass != SSM_PASS_FINAL)
809 return VINF_SUCCESS;
810
811 int rc = VINF_SUCCESS;
812 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
813 {
814 PVMCPU pVCpu = &pVM->aCpus[idCpu];
815 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
816
817 if (uVersion == APIC_SAVED_STATE_VERSION)
818 {
819 /* Load the auxiliary data. */
820 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
821 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
822
823 /* Load the APIC page. */
824 if (XAPIC_IN_X2APIC_MODE(pVCpu))
825 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
826 else
827 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
828
829 /* Load the PIBs. */
830 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPibR3, &g_aApicPibFields[0]);
831 SSMR3GetStruct(pSSM, (void *)&pApicCpu->ApicPibLevel, &g_aApicPibFields[0]);
832
833 /* Load the timer. */
834 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
835 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
836 Assert(pApicCpu->uHintedTimerShift == 0);
837 Assert(pApicCpu->uHintedTimerInitialCount == 0);
838 if (TMTimerIsActive(pApicCpu->pTimerR3))
839 {
840 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
841 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
842 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
843 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
844 }
845
846#ifdef DEBUG_ramshankar
847 apicR3DumpState(pVCpu, "Loaded state:");
848#endif
849 }
850 else
851 {
852 /** @todo load & translate old per-VCPU data to new APIC code. */
853 uint32_t uApicBaseMsrLo;
854 SSMR3GetU32(pSSM, &uApicBaseMsrLo);
855 pApicCpu->uApicBaseMsr = uApicBaseMsrLo;
856 }
857 }
858
859 return rc;
860}
861
862
863/**
864 * The timer callback.
865 *
866 * @param pDevIns The device instance.
867 * @param pTimer The timer handle.
868 * @param pvUser Opaque pointer to the VMCPU.
869 *
870 * @thread Any.
871 * @remarks Currently this function is invoked on the last EMT, see @c
872 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
873 * rely on this and is designed to work with being invoked on any
874 * thread.
875 */
876static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
877{
878 PVMCPU pVCpu = (PVMCPU)pvUser;
879 Assert(TMTimerIsLockOwner(pTimer));
880 Assert(pVCpu);
881 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
882
883 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
884 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
885 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
886 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
887 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
888 {
889 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
890 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
891 APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
892 }
893
894 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
895 switch (enmTimerMode)
896 {
897 case XAPICTIMERMODE_PERIODIC:
898 {
899 /* The initial-count register determines if the periodic timer is re-armed. */
900 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
901 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
902 if (uInitialCount)
903 {
904 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
905 APICStartTimer(pVCpu, uInitialCount);
906 }
907 break;
908 }
909
910 case XAPICTIMERMODE_ONESHOT:
911 {
912 pXApicPage->timer_ccr.u32CurrentCount = 0;
913 break;
914 }
915
916 case XAPICTIMERMODE_TSC_DEADLINE:
917 {
918 /** @todo implement TSC deadline. */
919 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
920 break;
921 }
922 }
923}
924
925
926/**
927 * @interface_method_impl{PDMDEVREG,pfnReset}
928 */
929static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
930{
931 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
932 PVM pVM = PDMDevHlpGetVM(pDevIns);
933 VM_ASSERT_EMT0(pVM);
934 VM_ASSERT_IS_NOT_RUNNING(pVM);
935
936 LogFlow(("APIC: apicR3Reset\n"));
937
938 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
939 {
940 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
941 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
942
943 if (TMTimerIsActive(pApicCpu->pTimerR3))
944 TMTimerStop(pApicCpu->pTimerR3);
945
946 APICR3Reset(pVCpuDest, true /* fResetApicBaseMsr */);
947
948 /* Clear the interrupt pending force flag. */
949 APICClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
950 }
951}
952
953
954/**
955 * @interface_method_impl{PDMDEVREG,pfnRelocate}
956 */
957static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
958{
959 PVM pVM = PDMDevHlpGetVM(pDevIns);
960 PAPIC pApic = VM_TO_APIC(pVM);
961 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
962
963 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
964
965 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
966 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
967 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
968
969 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
970 if (pApic->pvApicPibRC != NIL_RTRCPTR)
971 pApic->pvApicPibRC = MMHyperR3ToRC(pVM, (RTR3PTR)pApic->pvApicPibR3);
972
973 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
974 {
975 PVMCPU pVCpu = &pVM->aCpus[idCpu];
976 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
977 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
978
979 if (pApicCpu->pvApicPageRC != NIL_RTRCPTR)
980 pApicCpu->pvApicPageRC = MMHyperR3ToRC(pVM, (RTR3PTR)pApicCpu->pvApicPageR3);
981 if (pApicCpu->pvApicPibRC != NIL_RTRCPTR)
982 pApicCpu->pvApicPibRC = MMHyperR3ToRC(pVM, (RTR3PTR)pApicCpu->pvApicPibR3);
983 }
984}
985
986
987/**
988 * Terminates the APIC state.
989 *
990 * @param pVM The cross context VM structure.
991 */
992static void apicR3TermState(PVM pVM)
993{
994 PAPIC pApic = VM_TO_APIC(pVM);
995 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
996
997 /* Unmap and free the PIB. */
998 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
999 {
1000 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1001 if (cPages == 1)
1002 SUPR3PageFreeEx((void *)pApic->pvApicPibR3, cPages);
1003 else
1004 SUPR3ContFree((void *)pApic->pvApicPibR3, cPages);
1005 pApic->pvApicPibR3 = NIL_RTR3PTR;
1006 pApic->pvApicPibR0 = NIL_RTR0PTR;
1007 pApic->pvApicPibRC = NIL_RTRCPTR;
1008 }
1009
1010 /* Unmap and free the virtual-APIC pages. */
1011 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1012 {
1013 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1014 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1015
1016 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1017 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1018 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1019
1020 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1021 {
1022 SUPR3PageFreeEx((void *)pApicCpu->pvApicPageR3, 1 /* cPages */);
1023 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1024 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1025 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1026 }
1027 }
1028}
1029
1030
1031/**
1032 * Initializes the APIC state.
1033 *
1034 * @returns VBox status code.
1035 * @param pVM The cross context VM structure.
1036 */
1037static int apicR3InitState(PVM pVM)
1038{
1039 PAPIC pApic = VM_TO_APIC(pVM);
1040 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1041
1042 /* With hardware virtualization, we don't need to map the APIC in GC. */
1043 bool const fNeedsGCMapping = !HMIsEnabled(pVM);
1044
1045 /*
1046 * Allocate and map the pending-interrupt bitmap (PIB).
1047 *
1048 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1049 * physically contiguous allocations are rounded to a multiple of page size.
1050 */
1051 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1052 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1053 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1054 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1055 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1056 if (cPages == 1)
1057 {
1058 SUPPAGE SupApicPib;
1059 RT_ZERO(SupApicPib);
1060 SupApicPib.Phys = NIL_RTHCPHYS;
1061 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, (void **)&pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1062 if (RT_SUCCESS(rc))
1063 {
1064 pApic->HCPhysApicPib = SupApicPib.Phys;
1065 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1066 }
1067 else
1068 {
1069 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1070 return rc;
1071 }
1072 }
1073 else
1074 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1075
1076 if (pApic->pvApicPibR3)
1077 {
1078 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1079 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1080
1081 /* Initialize the PIB. */
1082 memset((void *)pApic->pvApicPibR3, 0, pApic->cbApicPib);
1083
1084 /* Map the PIB into GC. */
1085 if (fNeedsGCMapping)
1086 {
1087 pApic->pvApicPibRC = NIL_RTRCPTR;
1088 int rc = MMR3HyperMapHCPhys(pVM, (void *)pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1089 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1090 if (RT_FAILURE(rc))
1091 {
1092 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1093 rc));
1094 apicR3TermState(pVM);
1095 return rc;
1096 }
1097
1098 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1099 }
1100
1101 /*
1102 * Allocate the map the virtual-APIC pages.
1103 */
1104 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1105 {
1106 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1107 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1108
1109 SUPPAGE SupApicPage;
1110 RT_ZERO(SupApicPage);
1111 SupApicPage.Phys = NIL_RTHCPHYS;
1112
1113 Assert(pVCpu->idCpu == idCpu);
1114 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1115 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1116 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1117 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1118 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1119 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, (void **)&pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1120 &SupApicPage);
1121 if (RT_SUCCESS(rc))
1122 {
1123 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1124 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1125 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1126
1127 /* Map the virtual-APIC page into GC. */
1128 if (fNeedsGCMapping)
1129 {
1130 rc = MMR3HyperMapHCPhys(pVM, (void *)pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1131 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1132 if (RT_FAILURE(rc))
1133 {
1134 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1135 pApicCpu->cbApicPage, rc));
1136 apicR3TermState(pVM);
1137 return rc;
1138 }
1139
1140 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1141 }
1142
1143 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1144 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1145 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1146 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1147 if (fNeedsGCMapping)
1148 pApicCpu->pvApicPibRC += offApicPib;
1149
1150 /* Initialize the virtual-APIC state. */
1151 memset((void *)pApicCpu->pvApicPageR3, 0, pApicCpu->cbApicPage);
1152 APICR3Reset(pVCpu, true /* fResetApicBaseMsr */);
1153
1154#ifdef DEBUG_ramshankar
1155 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1156 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1157 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1158 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1159 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1160 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1161#endif
1162 }
1163 else
1164 {
1165 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", pApicCpu->cbApicPage, rc));
1166 apicR3TermState(pVM);
1167 return rc;
1168 }
1169 }
1170
1171#ifdef DEBUG_ramshankar
1172 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1173 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1174 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1175#endif
1176 return VINF_SUCCESS;
1177 }
1178
1179 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1180 pApic->cbApicPib));
1181 return VERR_NO_MEMORY;
1182}
1183
1184
1185/**
1186 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1187 */
1188static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1189{
1190 PVM pVM = PDMDevHlpGetVM(pDevIns);
1191 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1192
1193 apicR3TermState(pVM);
1194 return VINF_SUCCESS;
1195}
1196
1197
1198/**
1199 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1200 */
1201static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1202{
1203 PVM pVM = PDMDevHlpGetVM(pDevIns);
1204 PAPIC pApic = VM_TO_APIC(pVM);
1205
1206 /*
1207 * Init APIC settings that rely on HM and CPUM configurations.
1208 */
1209 CPUMCPUIDLEAF CpuLeaf;
1210 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1211 AssertRCReturn(rc, rc);
1212
1213 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1214 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1215 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1216
1217 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1218 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1219
1220 return VINF_SUCCESS;
1221}
1222
1223
1224/**
1225 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1226 */
1227static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1228{
1229 /*
1230 * Validate inputs.
1231 */
1232 Assert(iInstance == 0);
1233 Assert(pDevIns);
1234
1235 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1236 PVM pVM = PDMDevHlpGetVM(pDevIns);
1237 PAPIC pApic = VM_TO_APIC(pVM);
1238
1239 /*
1240 * Validate APIC settings.
1241 */
1242 int rc = CFGMR3ValidateConfig(pCfg, "/APIC/",
1243 "RZEnabled"
1244 "|Mode"
1245 "|IOAPIC"
1246 "|NumCPUs",
1247 "" /* pszValidNodes */, "APIC" /* pszWho */, 0 /* uInstance */);
1248 if (RT_FAILURE(rc))
1249 return rc;
1250
1251 rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1252 AssertLogRelRCReturn(rc, rc);
1253
1254 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1255 AssertLogRelRCReturn(rc, rc);
1256
1257 uint8_t uOriginalMode;
1258 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uOriginalMode, APICMODE_XAPIC);
1259 AssertLogRelRCReturn(rc, rc);
1260 /* Validate APIC modes. */
1261 switch (uOriginalMode)
1262 {
1263 case APICMODE_DISABLED:
1264 case APICMODE_X2APIC:
1265 case APICMODE_XAPIC:
1266 pApic->enmOriginalMode = (APICMODE)uOriginalMode;
1267 break;
1268 default:
1269 return VMR3SetError(pVM->pUVM, VERR_INVALID_STATE, RT_SRC_POS, "APIC mode %#x unknown.", uOriginalMode);
1270 }
1271
1272 /*
1273 * Initialize the APIC state.
1274 */
1275 pApicDev->pDevInsR3 = pDevIns;
1276 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1277 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1278
1279 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1280 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1281 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1282
1283 rc = apicR3InitState(pVM);
1284 AssertRCReturn(rc, rc);
1285
1286 /*
1287 * Disable automatic PDM locking for this device.
1288 */
1289 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1290 AssertRCReturn(rc, rc);
1291
1292 /*
1293 * Register the APIC.
1294 */
1295 PDMAPICREG ApicReg;
1296 RT_ZERO(ApicReg);
1297 ApicReg.u32Version = PDM_APICREG_VERSION;
1298 ApicReg.pfnGetInterruptR3 = APICGetInterrupt;
1299 ApicReg.pfnHasPendingIrqR3 = APICHasPendingIrq;
1300 ApicReg.pfnSetBaseMsrR3 = APICSetBaseMsr;
1301 ApicReg.pfnGetBaseMsrR3 = APICGetBaseMsr;
1302 ApicReg.pfnSetTprR3 = APICSetTpr;
1303 ApicReg.pfnGetTprR3 = APICGetTpr;
1304 ApicReg.pfnWriteMsrR3 = APICWriteMsr;
1305 ApicReg.pfnReadMsrR3 = APICReadMsr;
1306 ApicReg.pfnBusDeliverR3 = APICBusDeliver;
1307 ApicReg.pfnLocalInterruptR3 = APICLocalInterrupt;
1308 ApicReg.pfnGetTimerFreqR3 = APICGetTimerFreq;
1309
1310 /*
1311 * We always require R0 functionality (e.g. APICGetTpr() called by HMR0 VT-x/AMD-V code).
1312 * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
1313 * to ring-3. We still need other handlers like APICGetTpr() in ring-0 for now.
1314 */
1315 {
1316 ApicReg.pszGetInterruptRC = "APICGetInterrupt";
1317 ApicReg.pszHasPendingIrqRC = "APICHasPendingIrq";
1318 ApicReg.pszSetBaseMsrRC = "APICSetBaseMsr";
1319 ApicReg.pszGetBaseMsrRC = "APICGetBaseMsr";
1320 ApicReg.pszSetTprRC = "APICSetTpr";
1321 ApicReg.pszGetTprRC = "APICGetTpr";
1322 ApicReg.pszWriteMsrRC = "APICWriteMsr";
1323 ApicReg.pszReadMsrRC = "APICReadMsr";
1324 ApicReg.pszBusDeliverRC = "APICBusDeliver";
1325 ApicReg.pszLocalInterruptRC = "APICLocalInterrupt";
1326 ApicReg.pszGetTimerFreqRC = "APICGetTimerFreq";
1327
1328 ApicReg.pszGetInterruptR0 = "APICGetInterrupt";
1329 ApicReg.pszHasPendingIrqR0 = "APICHasPendingIrq";
1330 ApicReg.pszSetBaseMsrR0 = "APICSetBaseMsr";
1331 ApicReg.pszGetBaseMsrR0 = "APICGetBaseMsr";
1332 ApicReg.pszSetTprR0 = "APICSetTpr";
1333 ApicReg.pszGetTprR0 = "APICGetTpr";
1334 ApicReg.pszWriteMsrR0 = "APICWriteMsr";
1335 ApicReg.pszReadMsrR0 = "APICReadMsr";
1336 ApicReg.pszBusDeliverR0 = "APICBusDeliver";
1337 ApicReg.pszLocalInterruptR0 = "APICLocalInterrupt";
1338 ApicReg.pszGetTimerFreqR0 = "APICGetTimerFreq";
1339 }
1340
1341 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pApicDev->pApicHlpR3);
1342 AssertLogRelRCReturn(rc, rc);
1343 pApicDev->pCritSectR3 = pApicDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
1344
1345 /*
1346 * Update the CPUID bits.
1347 */
1348 APICUpdateCpuIdForMode(pVM, pApic->enmOriginalMode);
1349 LogRel(("APIC: Switched mode to %s\n", apicGetModeName(pApic->enmOriginalMode)));
1350
1351 /*
1352 * Register the MMIO range.
1353 */
1354 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1355 RTGCPHYS GCPhysApicBase = MSR_APICBASE_GET_PHYSADDR(pApicCpu0->uApicBaseMsr);
1356
1357 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1358 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1359 APICWriteMmio, APICReadMmio, "APIC");
1360 if (RT_FAILURE(rc))
1361 return rc;
1362
1363 if (pApic->fRZEnabled)
1364 {
1365 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1366 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1367 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1368 "APICWriteMmio", "APICReadMmio");
1369 if (RT_FAILURE(rc))
1370 return rc;
1371
1372 pApicDev->pApicHlpR0 = pApicDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
1373 pApicDev->pCritSectR0 = pApicDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
1374 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1375 "APICWriteMmio", "APICReadMmio");
1376 if (RT_FAILURE(rc))
1377 return rc;
1378 }
1379
1380 /*
1381 * Create the APIC timers.
1382 */
1383 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1384 {
1385 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1386 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1387 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1388 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1389 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1390 if (RT_SUCCESS(rc))
1391 {
1392 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1393 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1394 }
1395 else
1396 return rc;
1397 }
1398
1399 /*
1400 * Register saved state callbacks.
1401 */
1402 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1403 apicR3LoadExec);
1404 if (RT_FAILURE(rc))
1405 return rc;
1406
1407 /*
1408 * Register debugger info callback.
1409 */
1410 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "apic", "Display local APIC state for current CPU. Recognizes "
1411 "'basic', 'lvt', 'timer' as arguments, defaults to 'basic'.", apicR3DbgInfo);
1412 AssertRCReturn(rc, rc);
1413
1414#ifdef VBOX_WITH_STATISTICS
1415 /*
1416 * Statistics.
1417 */
1418#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1419 do { \
1420 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1421 AssertRCReturn(rc, rc); \
1422 } while(0)
1423
1424#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1425 do { \
1426 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1427 idCpu); \
1428 AssertRCReturn(rc, rc); \
1429 } while(0)
1430
1431 bool const fHasRC = !HMIsEnabled(pVM);
1432 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1433 {
1434 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1435 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1436
1437 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR0, "Number of APIC MMIO reads in R0.", "/Devices/APIC/%u/R0/MmioRead");
1438 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR0, "Number of APIC MMIO writes in R0.", "/Devices/APIC/%u/R0/MmioWrite");
1439 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR0, "Number of APIC MSR reads in R0.", "/Devices/APIC/%u/R0/MsrRead");
1440 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR0, "Number of APIC MSR writes in R0.", "/Devices/APIC/%u/R0/MsrWrite");
1441
1442 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1443 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1444 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1445 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1446
1447 if (fHasRC)
1448 {
1449 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRC, "Number of APIC MMIO reads in RC.", "/Devices/APIC/%u/RC/MmioRead");
1450 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRC, "Number of APIC MMIO writes in RC.", "/Devices/APIC/%u/RC/MmioWrite");
1451 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRC, "Number of APIC MSR reads in RC.", "/Devices/APIC/%u/RC/MsrRead");
1452 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRC, "Number of APIC MSR writes in RC.", "/Devices/APIC/%u/RC/MsrWrite");
1453 }
1454
1455 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1456 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1457 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1458
1459 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1460 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1461 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
1462 "/Devices/APIC/%u/TimerCallback");
1463 }
1464# undef APIC_PROF_COUNTER
1465# undef APIC_REG_ACCESS_COUNTER
1466#endif
1467
1468 return VINF_SUCCESS;
1469}
1470
1471
1472/**
1473 * APIC device registration structure.
1474 */
1475const PDMDEVREG g_DeviceAPIC =
1476{
1477 /* u32Version */
1478 PDM_DEVREG_VERSION,
1479 /* szName */
1480 "apic",
1481 /* szRCMod */
1482 "VMMRC.rc",
1483 /* szR0Mod */
1484 "VMMR0.r0",
1485 /* pszDescription */
1486 "Advanced Programmable Interrupt Controller",
1487 /* fFlags */
1488 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1489 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1490 /* fClass */
1491 PDM_DEVREG_CLASS_PIC,
1492 /* cMaxInstances */
1493 1,
1494 /* cbInstance */
1495 sizeof(APICDEV),
1496 /* pfnConstruct */
1497 apicR3Construct,
1498 /* pfnDestruct */
1499 apicR3Destruct,
1500 /* pfnRelocate */
1501 apicR3Relocate,
1502 /* pfnMemSetup */
1503 NULL,
1504 /* pfnPowerOn */
1505 NULL,
1506 /* pfnReset */
1507 apicR3Reset,
1508 /* pfnSuspend */
1509 NULL,
1510 /* pfnResume */
1511 NULL,
1512 /* pfnAttach */
1513 NULL,
1514 /* pfnDetach */
1515 NULL,
1516 /* pfnQueryInterface. */
1517 NULL,
1518 /* pfnInitComplete */
1519 apicR3InitComplete,
1520 /* pfnPowerOff */
1521 NULL,
1522 /* pfnSoftReset */
1523 NULL,
1524 /* u32VersionEnd */
1525 PDM_DEVREG_VERSION
1526};
1527
1528#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1529
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