VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 60624

Last change on this file since 60624 was 60624, checked in by vboxsync, 9 years ago

VMM/APIC: Diagnostics.
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1/* $Id: APIC.cpp 60624 2016-04-21 13:16:47Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37/** The current APIC saved state version. */
38#define APIC_SAVED_STATE_VERSION 4
39/** The saved state version used by VirtualBox 5.0 and
40 * earlier. */
41#define APIC_SAVED_STATE_VERSION_VBOX_50 3
42/** The saved state version used by VirtualBox v3 and earlier.
43 * This does not include the config. */
44#define APIC_SAVED_STATE_VERSION_VBOX_30 2
45/** Some ancient version... */
46#define APIC_SAVED_STATE_VERSION_ANCIENT 1
47
48
49/*********************************************************************************************************************************
50* Global Variables *
51*********************************************************************************************************************************/
52/** Saved state field descriptors for XAPICPAGE. */
53static const SSMFIELD g_aXApicPageFields[] =
54{
55 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
56 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
57 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
58 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
59 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
60 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
61 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
62 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
63 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
64 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
65 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
66 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
67 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
68 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
69 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
70 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
71 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
72 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
73 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
74 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
75 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
76 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
77 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
78 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
79 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
80 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
81 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
82 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
83 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
84 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
85 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
86 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
87 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
88 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
89 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
90 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
91 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
92 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
93 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
94 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
95 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
96 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
97 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
98 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
99 SSMFIELD_ENTRY_TERM()
100};
101
102/** Saved state field descriptors for X2APICPAGE. */
103static const SSMFIELD g_aX2ApicPageFields[] =
104{
105 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
106 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
107 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
108 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
109 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
110 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
111 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
112 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
113 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
114 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
115 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
116 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
117 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
118 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
119 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
120 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
121 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
122 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
123 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
124 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
125 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
126 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
127 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
128 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
129 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
130 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
131 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
132 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
133 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
134 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
135 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
136 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
137 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
138 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
139 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
140 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
141 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
142 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
143 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
144 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
145 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
146 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
147 SSMFIELD_ENTRY_TERM()
148};
149
150/** Saved state field descriptors for APICPIB. */
151static const SSMFIELD g_aApicPibFields[] =
152{
153 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[0]),
154 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[1]),
155 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[2]),
156 SSMFIELD_ENTRY(APICPIB, aVectorBitmap[3]),
157 SSMFIELD_ENTRY(APICPIB, fOutstandingNotification),
158 SSMFIELD_ENTRY_TERM()
159};
160
161/**
162 * Initializes per-VCPU APIC to the state following an INIT reset
163 * ("Wait-for-SIPI" state).
164 *
165 * @param pVCpu The cross context virtual CPU structure.
166 */
167static void apicR3InitIpi(PVMCPU pVCpu)
168{
169 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
170 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
171
172 /*
173 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
174 * and AMD spec 16.3.2 "APIC Registers".
175 */
176 memset((void *)&pXApicPage->irr, 0, sizeof(pXApicPage->irr));
177 memset((void *)&pXApicPage->isr, 0, sizeof(pXApicPage->isr));
178 memset((void *)&pXApicPage->tmr, 0, sizeof(pXApicPage->tmr));
179 memset((void *)&pXApicPage->icr_hi, 0, sizeof(pXApicPage->icr_hi));
180 memset((void *)&pXApicPage->icr_lo, 0, sizeof(pXApicPage->icr_lo));
181 memset((void *)&pXApicPage->ldr, 0, sizeof(pXApicPage->ldr));
182 memset((void *)&pXApicPage->tpr, 0, sizeof(pXApicPage->tpr));
183 memset((void *)&pXApicPage->timer_icr, 0, sizeof(pXApicPage->timer_icr));
184 memset((void *)&pXApicPage->timer_ccr, 0, sizeof(pXApicPage->timer_ccr));
185 memset((void *)&pXApicPage->timer_dcr, 0, sizeof(pXApicPage->timer_dcr));
186
187 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
188 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
189
190 /** @todo CMCI. */
191
192 memset((void *)&pXApicPage->lvt_timer, 0, sizeof(pXApicPage->lvt_timer));
193 pXApicPage->lvt_timer.u.u1Mask = 1;
194
195#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
196 memset((void *)&pXApicPage->lvt_thermal, 0, sizeof(pXApicPage->lvt_thermal));
197 pXApicPage->lvt_thermal.u.u1Mask = 1;
198#endif
199
200 memset((void *)&pXApicPage->lvt_perf, 0, sizeof(pXApicPage->lvt_perf));
201 pXApicPage->lvt_perf.u.u1Mask = 1;
202
203 memset((void *)&pXApicPage->lvt_lint0, 0, sizeof(pXApicPage->lvt_lint0));
204 pXApicPage->lvt_lint0.u.u1Mask = 1;
205
206 memset((void *)&pXApicPage->lvt_lint1, 0, sizeof(pXApicPage->lvt_lint1));
207 pXApicPage->lvt_lint1.u.u1Mask = 1;
208
209 memset((void *)&pXApicPage->lvt_error, 0, sizeof(pXApicPage->lvt_error));
210 pXApicPage->lvt_error.u.u1Mask = 1;
211
212 memset((void *)&pXApicPage->svr, 0, sizeof(pXApicPage->svr));
213 pXApicPage->svr.u.u8SpuriousVector = 0xff;
214
215 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
216 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
217 memset((void *)&pX2ApicPage->self_ipi, 0, sizeof(pX2ApicPage->self_ipi));
218
219 /* Clear the pending-interrupt bitmaps. */
220 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
221 memset((void *)&pApicCpu->ApicPibLevel, 0, sizeof(APICPIB));
222 memset((void *)pApicCpu->pvApicPibR3, 0, sizeof(APICPIB));
223}
224
225
226/**
227 * Resets the APIC base MSR.
228 *
229 * @param pVCpu The cross context virtual CPU structure.
230 */
231static void apicR3ResetBaseMsr(PVMCPU pVCpu)
232{
233 /*
234 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
235 *
236 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
237 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
238 *
239 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
240 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
241 */
242 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
243 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
244 pApicCpu->uApicBaseMsr = XAPIC_APICBASE_PHYSADDR
245 | MSR_APICBASE_XAPIC_ENABLE_BIT;
246 if (pVCpu->idCpu == 0)
247 pApicCpu->uApicBaseMsr |= MSR_APICBASE_BOOTSTRAP_CPU_BIT;
248}
249
250
251/**
252 * Initializes per-VCPU APIC to the state following a power-up or hardware
253 * reset.
254 *
255 * @param pVCpu The cross context virtual CPU structure.
256 */
257VMMR3_INT_DECL(void) APICR3Reset(PVMCPU pVCpu)
258{
259 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
260
261 LogFlow(("APIC%u: APICR3Reset\n", pVCpu->idCpu));
262
263#ifdef VBOX_STRICT
264 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
265 uint32_t uEax, uEbx, uEcx, uEdx;
266 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
267 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
268 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
269#endif
270
271 /*
272 * The state following a power-up or reset is a superset of the INIT state.
273 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
274 */
275 apicR3InitIpi(pVCpu);
276
277 /*
278 * The APIC version register is read-only, so just initialize it here.
279 * It is not clear from the specs, where exactly it is initalized.
280 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
281 */
282 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
283#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
284 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
285 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
286 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
287#else
288# error "Implement Pentium and P6 family APIC architectures"
289#endif
290
291 /** @todo It isn't clear in the spec. where exactly the default base address
292 * is (re)initialized, atm we do it here in Reset. */
293 apicR3ResetBaseMsr(pVCpu);
294
295 /*
296 * Initialize the APIC ID register to xAPIC format.
297 */
298 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
299 pXApicPage->id.u8ApicId = pVCpu->idCpu;
300}
301
302
303/**
304 * Receives an INIT IPI.
305 *
306 * @param pVCpu The cross context virtual CPU structure.
307 */
308VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
309{
310 VMCPU_ASSERT_EMT(pVCpu);
311 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
312 apicR3InitIpi(pVCpu);
313}
314
315
316/**
317 * Helper for dumping an APIC 256-bit sparse register.
318 *
319 * @param pApicReg The APIC 256-bit spare register.
320 * @param pHlp The debug output helper.
321 */
322static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
323{
324 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
325 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
326 XAPIC256BITREG ApicReg;
327 RT_ZERO(ApicReg);
328
329 pHlp->pfnPrintf(pHlp, " ");
330 for (ssize_t i = cFragments - 1; i >= 0; i--)
331 {
332 uint32_t const uFragment = pApicReg->u[i].u32Reg;
333 ApicReg.u[i].u32Reg = uFragment;
334 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
335 }
336 pHlp->pfnPrintf(pHlp, "\n");
337
338 size_t cPending = 0;
339 pHlp->pfnPrintf(pHlp, " Pending:\n");
340 pHlp->pfnPrintf(pHlp, " ");
341 for (ssize_t i = cFragments - 1; i >= 0; i--)
342 {
343 uint32_t uFragment = ApicReg.u[i].u32Reg;
344 if (uFragment)
345 {
346 do
347 {
348 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
349 --idxSetBit;
350 ASMBitClear(&uFragment, idxSetBit);
351
352 idxSetBit += (i * cBitsPerFragment);
353 pHlp->pfnPrintf(pHlp, " %02x", idxSetBit);
354 ++cPending;
355 } while (uFragment);
356 }
357 }
358 if (!cPending)
359 pHlp->pfnPrintf(pHlp, " None");
360 pHlp->pfnPrintf(pHlp, "\n");
361}
362
363
364/**
365 * Dumps basic APIC state.
366 *
367 * @param pVCpu The cross context virtual CPU structure.
368 * @param pHlp The debug output helper.
369 */
370static void apicR3DbgInfoBasic(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
371{
372 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
373 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
374 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
375 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
376
377 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC at %#RGp\n", pVCpu->idCpu, MSR_APICBASE_GET_PHYSADDR(pApicCpu->uApicBaseMsr));
378 pHlp->pfnPrintf(pHlp, " Mode = %s\n", fX2ApicMode ? "x2Apic" : "xApic");
379 if (fX2ApicMode)
380 {
381 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
382 pX2ApicPage->id.u32ApicId);
383 }
384 else
385 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
386 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
387 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
388 pHlp->pfnPrintf(pHlp, " Max LVT entries = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
389 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
390 if (!fX2ApicMode)
391 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
392 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
393 pHlp->pfnPrintf(pHlp, " Task-priority class = %u\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr));
394 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %u\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
395 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
396 pHlp->pfnPrintf(pHlp, " Processor-priority class = %u\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr));
397 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %u\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
398 if (!fX2ApicMode)
399 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
400 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
401 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
402 : pXApicPage->ldr.u.u8LogicalApicId);
403 if (!fX2ApicMode)
404 {
405 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
406 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
407 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
408 }
409 pHlp->pfnPrintf(pHlp, " SVR\n");
410 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
411 pXApicPage->svr.u.u8SpuriousVector);
412 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
413 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
414 pHlp->pfnPrintf(pHlp, " ISR\n");
415 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
416 pHlp->pfnPrintf(pHlp, " TMR\n");
417 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
418 pHlp->pfnPrintf(pHlp, " IRR\n");
419 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
420 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
421 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
422 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
423 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
424 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
425 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
426 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
427 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
428 pXApicPage->icr_lo.u.u8Vector);
429 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
430 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
431 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
432 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
433 if (!fX2ApicMode)
434 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
435 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
436 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
437 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
438 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
439 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
440 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
441 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
442 : pXApicPage->icr_hi.u.u8Dest);
443}
444
445
446/**
447 * Helper for dumping the LVT timer.
448 *
449 * @param pVCpu The cross context virtual CPU structure.
450 * @param pHlp The debug output helper.
451 */
452static void apicR3DbgInfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
453{
454 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
455 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
456 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
457 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
458 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
459 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
460 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
461 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
462 pHlp->pfnPrintf(pHlp, "\n");
463}
464
465
466/**
467 * Dumps APIC Local Vector Table (LVT) state.
468 *
469 * @param pVCpu The cross context virtual CPU structure.
470 * @param pHlp The debug output helper.
471 */
472static void apicR3DbgInfoLvt(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
473{
474 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
475
476 apicR3DbgInfoLvtTimer(pVCpu, pHlp);
477
478#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
479 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
480 pHlp->pfnPrintf(pHlp, "LVT Thermal = %#RX32)\n", uLvtThermal);
481 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_thermal.u.u8Vector, pXApicPage->lvt_thermal.u.u8Vector);
482 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_thermal.u.u3DeliveryMode,
483 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_thermal.u.u3DeliveryMode));
484 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_thermal.u.u1DeliveryStatus);
485 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtThermal));
486 pHlp->pfnPrintf(pHlp, "\n");
487#endif
488
489 uint32_t const uLvtPerf = pXApicPage->lvt_perf.all.u32LvtPerf;
490 pHlp->pfnPrintf(pHlp, "LVT Perf = %#RX32\n", uLvtPerf);
491 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_perf.u.u8Vector, pXApicPage->lvt_perf.u.u8Vector);
492 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_perf.u.u3DeliveryMode,
493 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_perf.u.u3DeliveryMode));
494 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_perf.u.u1DeliveryStatus);
495 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtPerf));
496 pHlp->pfnPrintf(pHlp, "\n");
497
498 uint32_t const uLvtLint0 = pXApicPage->lvt_lint0.all.u32LvtLint0;
499 pHlp->pfnPrintf(pHlp, "LVT LINT0 = %#RX32\n", uLvtLint0);
500 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_lint0.u.u8Vector, pXApicPage->lvt_lint0.u.u8Vector);
501 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_lint0.u.u3DeliveryMode,
502 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_lint0.u.u3DeliveryMode));
503 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_lint0.u.u1DeliveryStatus);
504 pHlp->pfnPrintf(pHlp, " Pin polarity = %u\n", pXApicPage->lvt_lint0.u.u1IntrPolarity);
505 pHlp->pfnPrintf(pHlp, " Remote IRR = %u\n", pXApicPage->lvt_lint0.u.u1RemoteIrr);
506 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->lvt_lint0.u.u1TriggerMode,
507 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->lvt_lint0.u.u1TriggerMode));
508 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtLint0));
509 pHlp->pfnPrintf(pHlp, "\n");
510
511 uint32_t const uLvtLint1 = pXApicPage->lvt_lint1.all.u32LvtLint1;
512 pHlp->pfnPrintf(pHlp, "LVT LINT1 = %#RX32\n", uLvtLint1);
513 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_lint1.u.u8Vector, pXApicPage->lvt_lint1.u.u8Vector);
514 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->lvt_lint1.u.u3DeliveryMode,
515 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->lvt_lint1.u.u3DeliveryMode));
516 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_lint1.u.u1DeliveryStatus);
517 pHlp->pfnPrintf(pHlp, " Pin polarity = %u\n", pXApicPage->lvt_lint1.u.u1IntrPolarity);
518 pHlp->pfnPrintf(pHlp, " Remote IRR = %u\n", pXApicPage->lvt_lint1.u.u1RemoteIrr);
519 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->lvt_lint1.u.u1TriggerMode,
520 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->lvt_lint1.u.u1TriggerMode));
521 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtLint1));
522 pHlp->pfnPrintf(pHlp, "\n");
523
524 uint32_t const uLvtError = pXApicPage->lvt_error.all.u32LvtError;
525 pHlp->pfnPrintf(pHlp, "LVT Perf = %#RX32\n", uLvtError);
526 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_error.u.u8Vector, pXApicPage->lvt_error.u.u8Vector);
527 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_error.u.u1DeliveryStatus);
528 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtError));
529 pHlp->pfnPrintf(pHlp, "\n");
530}
531
532
533/**
534 * Dumps APIC Timer state.
535 *
536 * @param pVCpu The cross context virtual CPU structure.
537 * @param pHlp The debug output helper.
538 */
539static void apicR3DbgInfoTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
540{
541 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
542 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
543
544 pHlp->pfnPrintf(pHlp, "Local APIC timer:\n");
545 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
546 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
547 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
548 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
549 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
550 pHlp->pfnPrintf(pHlp, "\n");
551
552 apicR3DbgInfoLvtTimer(pVCpu, pHlp);
553}
554
555
556/**
557 * @callback_method_impl{FNDBGFHANDLERDEV,
558 * Dumps the APIC state according to given argument for debugging purposes.}
559 */
560static DECLCALLBACK(void) apicR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
561{
562 PVM pVM = PDMDevHlpGetVM(pDevIns);
563 PVMCPU pVCpu = VMMGetCpu(pVM);
564 Assert(pVCpu);
565
566 if (pszArgs == NULL || !*pszArgs || !strcmp(pszArgs, "basic"))
567 apicR3DbgInfoBasic(pVCpu, pHlp);
568 else if (!strcmp(pszArgs, "lvt"))
569 apicR3DbgInfoLvt(pVCpu, pHlp);
570 else if (!strcmp(pszArgs, "timer"))
571 apicR3DbgInfoTimer(pVCpu, pHlp);
572 else
573 pHlp->pfnPrintf(pHlp, "Invalid argument. Recognized arguments are 'basic', 'lvt', 'timer'\n");
574}
575
576
577/**
578 * Converts legacy PDMAPICMODE to the new APICMODE enum.
579 *
580 * @returns The new APIC mode.
581 * @param enmLegacyMode The legacy mode to convert.
582 */
583static APICMODE apicR3ConvertFromLegacyApicMode(PDMAPICMODE enmLegacyMode)
584{
585 switch (enmLegacyMode)
586 {
587 case PDMAPICMODE_NONE: return APICMODE_DISABLED;
588 case PDMAPICMODE_APIC: return APICMODE_XAPIC;
589 case PDMAPICMODE_X2APIC: return APICMODE_X2APIC;
590 case PDMAPICMODE_INVALID: return APICMODE_INVALID;
591 default: break;
592 }
593 return (APICMODE)enmLegacyMode;
594}
595
596
597/**
598 * Converts the new APICMODE enum to the legacy PDMAPICMODE enum.
599 *
600 * @returns The legacy APIC mode.
601 * @param enmMode The APIC mode to convert.
602 */
603static PDMAPICMODE apicR3ConvertToLegacyApicMode(APICMODE enmMode)
604{
605 switch (enmMode)
606 {
607 case APICMODE_DISABLED: return PDMAPICMODE_NONE;
608 case APICMODE_XAPIC: return PDMAPICMODE_APIC;
609 case APICMODE_X2APIC: return PDMAPICMODE_X2APIC;
610 case APICMODE_INVALID: return PDMAPICMODE_INVALID;
611 default: break;
612 }
613 return (PDMAPICMODE)enmMode;
614}
615
616
617#ifdef DEBUG_ramshankar
618/**
619 * Helper for dumping per-VCPU APIC state to the release logger.
620 *
621 * This is primarily concerned about the APIC state relevant for saved-states.
622 *
623 * @param pVCpu The cross context virtual CPU structure.
624 * @param pszPrefix A caller supplied prefix before dumping parts of the
625 * state.
626 */
627static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix)
628{
629 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
630
631 /* The auxiliary state. */
632 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
633 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
634
635 /* The timer. */
636 LogRel(("APIC%u: %s APIC Timer:\n", pVCpu->idCpu));
637 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
638
639 /* The PIBs. */
640 LogRel(("APIC%u: %s APIC PIB:\n", pVCpu->idCpu, pszPrefix));
641 LogRel(("%.*Rhxs\n", sizeof(APICPIB), pApicCpu->pvApicPibR3));
642 LogRel(("APIC%u: %s APIC Level PIB:\n", pVCpu->idCpu, pszPrefix));
643 LogRel(("%.*Rhxs\n", sizeof(APICPIB), &pApicCpu->ApicPibLevel));
644
645 /* The APIC page. */
646 LogRel(("APIC%u: %s APIC page\n:", pVCpu->idCpu, pszPrefix));
647 LogRel(("%.*Rhxs\n", sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
648}
649#endif
650
651
652/**
653 * Worker for saving per-VM APIC data.
654 *
655 * @returns VBox status code.
656 * @param pVM The cross context VM structure.
657 * @param pSSM The SSM handle.
658 */
659static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
660{
661 PAPIC pApic = VM_TO_APIC(pVM);
662 SSMR3PutU32(pSSM, pVM->cCpus);
663 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
664 return SSMR3PutU32(pSSM, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode));
665}
666
667
668/**
669 * Worker for loading per-VM APIC data.
670 *
671 * @returns VBox status code.
672 * @param pVM The cross context VM structure.
673 * @param pSSM The SSM handle.
674 */
675static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
676{
677 PAPIC pApic = VM_TO_APIC(pVM);
678
679 /* Load and verify number of CPUs. */
680 uint32_t cCpus;
681 int rc = SSMR3GetU32(pSSM, &cCpus);
682 AssertRCReturn(rc, rc);
683 if (cCpus != pVM->cCpus)
684 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
685
686 /* Load and verify I/O APIC presence. */
687 bool fIoApicPresent;
688 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
689 AssertRCReturn(rc, rc);
690 if (fIoApicPresent != pApic->fIoApicPresent)
691 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
692 fIoApicPresent, pApic->fIoApicPresent);
693
694 /* Load and verify configured APIC mode. */
695 uint32_t uLegacyApicMode;
696 rc = SSMR3GetU32(pSSM, &uLegacyApicMode);
697 AssertRCReturn(rc, rc);
698 APICMODE const enmApicMode = apicR3ConvertFromLegacyApicMode((PDMAPICMODE)uLegacyApicMode);
699 if (enmApicMode != pApic->enmOriginalMode)
700 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%#x(%#x) config=%#x(%#x)"),
701 uLegacyApicMode, enmApicMode, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode),
702 pApic->enmOriginalMode);
703 return VINF_SUCCESS;
704}
705
706
707/**
708 * @copydoc FNSSMDEVLIVEEXEC
709 */
710static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
711{
712 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
713 PVM pVM = PDMDevHlpGetVM(pApicDev->pDevInsR3);
714
715 int rc = apicR3SaveVMData(pVM, pSSM);
716 AssertRCReturn(rc, rc);
717 return VINF_SSM_DONT_CALL_AGAIN;
718}
719
720
721/**
722 * @copydoc FNSSMDEVSAVEEXEC
723 */
724static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
725{
726 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
727 PVM pVM = PDMDevHlpGetVM(pDevIns);
728 PAPIC pApic = VM_TO_APIC(pVM);
729 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
730
731 /* Save per-VM data. */
732 int rc = apicR3SaveVMData(pVM, pSSM);
733 AssertRCReturn(rc, rc);
734
735 /* Save per-VCPU data.*/
736 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
737 {
738 PVMCPU pVCpu = &pVM->aCpus[idCpu];
739 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
740
741 /* Save the auxiliary data. */
742 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
743 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
744
745 /* Save the APIC page. */
746 if (XAPIC_IN_X2APIC_MODE(pVCpu))
747 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
748 else
749 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
750
751 /* Save the PIBs: In theory, we could push them to vIRR and avoid saving them here, but
752 with posted-interrupts we can't at this point as HM is paralyzed, so just save PIBs always. */
753 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPibR3, &g_aApicPibFields[0]);
754 SSMR3PutStruct(pSSM, (const void *)&pApicCpu->ApicPibLevel, &g_aApicPibFields[0]);
755
756 /* Save the timer. */
757 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
758 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
759
760#ifdef DEBUG_ramshankar
761 apicR3DumpState(pVCpu, "Saved");
762#endif
763 }
764
765 return rc;
766}
767
768
769/**
770 * @copydoc FNSSMDEVLOADEXEC
771 */
772static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
773{
774 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
775 PVM pVM = PDMDevHlpGetVM(pDevIns);
776 PAPIC pApic = VM_TO_APIC(pVM);
777 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
778
779 /* Weed out invalid versions. */
780 if ( uVersion != APIC_SAVED_STATE_VERSION
781 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
782 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
783 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
784 {
785 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
786 }
787
788 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
789 {
790 int rc2 = apicR3LoadVMData(pVM, pSSM);
791 AssertRCReturn(rc2, rc2);
792
793 if (uVersion == APIC_SAVED_STATE_VERSION)
794 { /* Load any new additional per-VM data. */ }
795 }
796
797 if (uPass != SSM_PASS_FINAL)
798 return VINF_SUCCESS;
799
800 int rc = VINF_SUCCESS;
801 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
802 {
803 PVMCPU pVCpu = &pVM->aCpus[idCpu];
804 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
805
806 if (uVersion == APIC_SAVED_STATE_VERSION)
807 {
808 /* Load the auxiliary data. */
809 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
810 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
811
812 /* Load the APIC page. */
813 if (XAPIC_IN_X2APIC_MODE(pVCpu))
814 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
815 else
816 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
817
818 /* Load the PIBs. */
819 SSMR3GetStruct(pSSM, (void *)pApicCpu->pvApicPibR3, &g_aApicPibFields[0]);
820 SSMR3GetStruct(pSSM, (void *)&pApicCpu->ApicPibLevel, &g_aApicPibFields[0]);
821
822 /* Load the timer. */
823 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
824 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
825 Assert(pApicCpu->uHintedTimerShift == 0);
826 Assert(pApicCpu->uHintedTimerInitialCount == 0);
827 if (TMTimerIsActive(pApicCpu->pTimerR3))
828 {
829 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
830 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
831 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
832 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
833 }
834
835#ifdef DEBUG_ramshankar
836 apicR3DumpState(pVCpu, "Loaded");
837#endif
838 }
839 else
840 {
841 /** @todo load & translate old per-VCPU data to new APIC code. */
842 uint32_t uApicBaseMsrLo;
843 SSMR3GetU32(pSSM, &uApicBaseMsrLo);
844 pApicCpu->uApicBaseMsr = uApicBaseMsrLo;
845 }
846 }
847
848 return rc;
849}
850
851
852/**
853 * The timer callback.
854 *
855 * @param pDevIns The device instance.
856 * @param pTimer The timer handle.
857 * @param pvUser Opaque pointer to the VMCPU.
858 *
859 * @thread Any.
860 * @remarks Currently this function is invoked on the last EMT, see @c
861 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
862 * rely on this and is designed to work with being invoked on any
863 * thread.
864 */
865static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
866{
867 PVMCPU pVCpu = (PVMCPU)pvUser;
868 Assert(TMTimerIsLockOwner(pTimer));
869 Assert(pVCpu);
870 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
871
872 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
873 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
874 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
875 {
876 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
877 Log4(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
878 APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
879 }
880
881 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
882 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
883 switch (enmTimerMode)
884 {
885 case XAPICTIMERMODE_PERIODIC:
886 {
887 /* The initial-count register determines if the periodic timer is re-armed. */
888 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
889 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
890 if (uInitialCount)
891 {
892 Log4(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
893 APICStartTimer(pApicCpu, uInitialCount);
894 }
895 break;
896 }
897
898 case XAPICTIMERMODE_ONESHOT:
899 {
900 pXApicPage->timer_ccr.u32CurrentCount = 0;
901 break;
902 }
903
904 case XAPICTIMERMODE_TSC_DEADLINE:
905 {
906 /** @todo implement TSC deadline. */
907 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
908 break;
909 }
910 }
911}
912
913
914/**
915 * @interface_method_impl{PDMDEVREG,pfnReset}
916 */
917static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
918{
919 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
920 PVM pVM = PDMDevHlpGetVM(pDevIns);
921 VM_ASSERT_EMT0(pVM);
922 VM_ASSERT_IS_NOT_RUNNING(pVM);
923
924 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
925 {
926 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
927 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
928
929 if (TMTimerIsActive(pApicCpu->pTimerR3))
930 TMTimerStop(pApicCpu->pTimerR3);
931
932 APICR3Reset(pVCpuDest);
933
934 /* Clear the interrupt pending force flag. */
935 APICClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
936 }
937}
938
939
940/**
941 * @interface_method_impl{PDMDEVREG,pfnRelocate}
942 */
943static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
944{
945 PVM pVM = PDMDevHlpGetVM(pDevIns);
946 PAPIC pApic = VM_TO_APIC(pVM);
947 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
948
949 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
950
951 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
952 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
953 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
954
955 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
956 if (pApic->pvApicPibRC != NIL_RTRCPTR)
957 pApic->pvApicPibRC = MMHyperR3ToRC(pVM, (RTR3PTR)pApic->pvApicPibR3);
958
959 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
960 {
961 PVMCPU pVCpu = &pVM->aCpus[idCpu];
962 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
963 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
964
965 if (pApicCpu->pvApicPageRC != NIL_RTRCPTR)
966 pApicCpu->pvApicPageRC = MMHyperR3ToRC(pVM, (RTR3PTR)pApicCpu->pvApicPageR3);
967 if (pApicCpu->pvApicPibRC != NIL_RTRCPTR)
968 pApicCpu->pvApicPibRC = MMHyperR3ToRC(pVM, (RTR3PTR)pApicCpu->pvApicPibR3);
969 }
970}
971
972
973/**
974 * Terminates the APIC state.
975 *
976 * @param pVM The cross context VM structure.
977 */
978static void apicR3TermState(PVM pVM)
979{
980 PAPIC pApic = VM_TO_APIC(pVM);
981 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
982
983 /* Unmap and free the PIB. */
984 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
985 {
986 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
987 if (cPages == 1)
988 SUPR3PageFreeEx((void *)pApic->pvApicPibR3, cPages);
989 else
990 SUPR3ContFree((void *)pApic->pvApicPibR3, cPages);
991 pApic->pvApicPibR3 = NIL_RTR3PTR;
992 pApic->pvApicPibR0 = NIL_RTR0PTR;
993 pApic->pvApicPibRC = NIL_RTRCPTR;
994 }
995
996 /* Unmap and free the virtual-APIC pages. */
997 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
998 {
999 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1000 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1001
1002 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1003 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1004 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1005
1006 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1007 {
1008 SUPR3PageFreeEx((void *)pApicCpu->pvApicPageR3, 1 /* cPages */);
1009 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1010 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1011 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1012 }
1013 }
1014}
1015
1016
1017/**
1018 * Initializes the APIC state.
1019 *
1020 * @returns VBox status code.
1021 * @param pVM The cross context VM structure.
1022 */
1023static int apicR3InitState(PVM pVM)
1024{
1025 PAPIC pApic = VM_TO_APIC(pVM);
1026 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1027
1028 /* With hardware virtualization, we don't need to map the APIC in GC. */
1029 bool const fNeedsGCMapping = !HMIsEnabled(pVM);
1030
1031 /*
1032 * Allocate and map the pending-interrupt bitmap (PIB).
1033 *
1034 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1035 * physically contiguous allocations are rounded to a multiple of page size.
1036 */
1037 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1038 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1039 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1040 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1041 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1042 if (cPages == 1)
1043 {
1044 SUPPAGE SupApicPib;
1045 RT_ZERO(SupApicPib);
1046 SupApicPib.Phys = NIL_RTHCPHYS;
1047 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, (void **)&pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1048 if (RT_SUCCESS(rc))
1049 {
1050 pApic->HCPhysApicPib = SupApicPib.Phys;
1051 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1052 }
1053 else
1054 {
1055 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1056 return rc;
1057 }
1058 }
1059 else
1060 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1061
1062 if (pApic->pvApicPibR3)
1063 {
1064 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1065 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1066
1067 /* Initialize the PIB. */
1068 memset((void *)pApic->pvApicPibR3, 0, pApic->cbApicPib);
1069
1070 /* Map the PIB into GC. */
1071 if (fNeedsGCMapping)
1072 {
1073 pApic->pvApicPibRC == NIL_RTRCPTR;
1074 int rc = MMR3HyperMapHCPhys(pVM, (void *)pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1075 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1076 if (RT_FAILURE(rc))
1077 {
1078 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1079 rc));
1080 apicR3TermState(pVM);
1081 return rc;
1082 }
1083
1084 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1085 }
1086
1087 /*
1088 * Allocate the map the virtual-APIC pages.
1089 */
1090 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1091 {
1092 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1093 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1094
1095 SUPPAGE SupApicPage;
1096 RT_ZERO(SupApicPage);
1097 SupApicPage.Phys = NIL_RTHCPHYS;
1098
1099 Assert(pVCpu->idCpu == idCpu);
1100 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1101 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1102 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1103 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1104 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1105 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, (void **)&pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1106 &SupApicPage);
1107 if (RT_SUCCESS(rc))
1108 {
1109 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1110 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1111 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1112
1113 /* Map the virtual-APIC page into GC. */
1114 if (fNeedsGCMapping)
1115 {
1116 rc = MMR3HyperMapHCPhys(pVM, (void *)pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1117 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1118 if (RT_FAILURE(rc))
1119 {
1120 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1121 pApicCpu->cbApicPage, rc));
1122 apicR3TermState(pVM);
1123 return rc;
1124 }
1125
1126 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1127 }
1128
1129 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1130 size_t const offApicPib = idCpu * sizeof(APICPIB);
1131 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1132 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1133 if (fNeedsGCMapping)
1134 pApicCpu->pvApicPibRC += offApicPib;
1135
1136 /* Initialize the virtual-APIC state. */
1137 memset((void *)pApicCpu->pvApicPageR3, 0, pApicCpu->cbApicPage);
1138 APICR3Reset(pVCpu);
1139
1140#ifdef DEBUG_ramshankar
1141 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1142 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1143 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1144 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1145 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1146 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1147#endif
1148 }
1149 else
1150 {
1151 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", pApicCpu->cbApicPage, rc));
1152 apicR3TermState(pVM);
1153 return rc;
1154 }
1155 }
1156
1157#ifdef DEBUG_ramshankar
1158 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1159 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1160 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1161#endif
1162 return VINF_SUCCESS;
1163 }
1164
1165 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1166 pApic->cbApicPib));
1167 return VERR_NO_MEMORY;
1168}
1169
1170
1171/**
1172 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1173 */
1174static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1175{
1176 PVM pVM = PDMDevHlpGetVM(pDevIns);
1177 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1178
1179 apicR3TermState(pVM);
1180 return VINF_SUCCESS;
1181}
1182
1183
1184/**
1185 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1186 */
1187static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1188{
1189 PVM pVM = PDMDevHlpGetVM(pDevIns);
1190 PAPIC pApic = VM_TO_APIC(pVM);
1191
1192 /*
1193 * Init APIC settings that rely on HM and CPUM configurations.
1194 */
1195 CPUMCPUIDLEAF CpuLeaf;
1196 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1197 AssertRCReturn(rc, rc);
1198
1199 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1200 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1201 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1202
1203 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1204 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1205
1206 return VINF_SUCCESS;
1207}
1208
1209
1210/**
1211 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1212 */
1213static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1214{
1215 /*
1216 * Validate inputs.
1217 */
1218 Assert(iInstance == 0);
1219 Assert(pDevIns);
1220
1221 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1222 PVM pVM = PDMDevHlpGetVM(pDevIns);
1223 PAPIC pApic = VM_TO_APIC(pVM);
1224
1225 /*
1226 * Validate APIC settings.
1227 */
1228 int rc = CFGMR3ValidateConfig(pCfg, "/APIC/",
1229 "RZEnabled"
1230 "|Mode"
1231 "|IOAPIC"
1232 "|NumCPUs",
1233 "" /* pszValidNodes */, "APIC" /* pszWho */, 0 /* uInstance */);
1234 if (RT_FAILURE(rc))
1235 return rc;
1236
1237 rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1238 AssertLogRelRCReturn(rc, rc);
1239
1240 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1241 AssertLogRelRCReturn(rc, rc);
1242
1243 uint8_t uOriginalMode;
1244 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uOriginalMode, APICMODE_XAPIC);
1245 AssertLogRelRCReturn(rc, rc);
1246 /* Validate APIC modes. */
1247 switch (uOriginalMode)
1248 {
1249 case APICMODE_DISABLED:
1250 case APICMODE_X2APIC:
1251 case APICMODE_XAPIC:
1252 pApic->enmOriginalMode = (APICMODE)uOriginalMode;
1253 break;
1254 default:
1255 return VMR3SetError(pVM->pUVM, VERR_INVALID_STATE, RT_SRC_POS, "APIC mode %#x unknown.", uOriginalMode);
1256 }
1257
1258 /*
1259 * Initialize the APIC state.
1260 */
1261 pApicDev->pDevInsR3 = pDevIns;
1262 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1263 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1264
1265 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1266 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1267 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1268
1269 rc = apicR3InitState(pVM);
1270 AssertRCReturn(rc, rc);
1271
1272 /*
1273 * Disable automatic PDM locking for this device.
1274 */
1275 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1276 AssertRCReturn(rc, rc);
1277
1278 /*
1279 * Register the APIC.
1280 */
1281 PDMAPICREG ApicReg;
1282 RT_ZERO(ApicReg);
1283 ApicReg.u32Version = PDM_APICREG_VERSION;
1284 ApicReg.pfnGetInterruptR3 = APICGetInterrupt;
1285 ApicReg.pfnHasPendingIrqR3 = APICHasPendingIrq;
1286 ApicReg.pfnSetBaseMsrR3 = APICSetBaseMsr;
1287 ApicReg.pfnGetBaseMsrR3 = APICGetBaseMsr;
1288 ApicReg.pfnSetTprR3 = APICSetTpr;
1289 ApicReg.pfnGetTprR3 = APICGetTpr;
1290 ApicReg.pfnWriteMsrR3 = APICWriteMsr;
1291 ApicReg.pfnReadMsrR3 = APICReadMsr;
1292 ApicReg.pfnBusDeliverR3 = APICBusDeliver;
1293 ApicReg.pfnLocalInterruptR3 = APICLocalInterrupt;
1294 ApicReg.pfnGetTimerFreqR3 = APICGetTimerFreq;
1295
1296 /*
1297 * We always require R0 functionality (e.g. APICGetTpr() called by HMR0 VT-x/AMD-V code).
1298 * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
1299 * to ring-3. We still need other handlers like APICGetTpr() in ring-0 for now.
1300 */
1301 {
1302 ApicReg.pszGetInterruptRC = "APICGetInterrupt";
1303 ApicReg.pszHasPendingIrqRC = "APICHasPendingIrq";
1304 ApicReg.pszSetBaseMsrRC = "APICSetBaseMsr";
1305 ApicReg.pszGetBaseMsrRC = "APICGetBaseMsr";
1306 ApicReg.pszSetTprRC = "APICSetTpr";
1307 ApicReg.pszGetTprRC = "APICGetTpr";
1308 ApicReg.pszWriteMsrRC = "APICWriteMsr";
1309 ApicReg.pszReadMsrRC = "APICReadMsr";
1310 ApicReg.pszBusDeliverRC = "APICBusDeliver";
1311 ApicReg.pszLocalInterruptRC = "APICLocalInterrupt";
1312 ApicReg.pszGetTimerFreqRC = "APICGetTimerFreq";
1313
1314 ApicReg.pszGetInterruptR0 = "APICGetInterrupt";
1315 ApicReg.pszHasPendingIrqR0 = "APICHasPendingIrq";
1316 ApicReg.pszSetBaseMsrR0 = "APICSetBaseMsr";
1317 ApicReg.pszGetBaseMsrR0 = "APICGetBaseMsr";
1318 ApicReg.pszSetTprR0 = "APICSetTpr";
1319 ApicReg.pszGetTprR0 = "APICGetTpr";
1320 ApicReg.pszWriteMsrR0 = "APICWriteMsr";
1321 ApicReg.pszReadMsrR0 = "APICReadMsr";
1322 ApicReg.pszBusDeliverR0 = "APICBusDeliver";
1323 ApicReg.pszLocalInterruptR0 = "APICLocalInterrupt";
1324 ApicReg.pszGetTimerFreqR0 = "APICGetTimerFreq";
1325 }
1326
1327 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pApicDev->pApicHlpR3);
1328 AssertLogRelRCReturn(rc, rc);
1329 pApicDev->pCritSectR3 = pApicDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
1330
1331 /*
1332 * Update the CPUID bits.
1333 */
1334 APICUpdateCpuIdForMode(pVM, pApic->enmOriginalMode);
1335 LogRel(("APIC: Switched mode to %s\n", apicGetModeName(pApic->enmOriginalMode)));
1336
1337 /*
1338 * Register the MMIO range.
1339 */
1340 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1341 RTGCPHYS GCPhysApicBase = MSR_APICBASE_GET_PHYSADDR(pApicCpu0->uApicBaseMsr);
1342
1343 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1344 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1345 APICWriteMmio, APICReadMmio, "APIC");
1346 if (RT_FAILURE(rc))
1347 return rc;
1348
1349 if (pApic->fRZEnabled)
1350 {
1351 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1352 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1353 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1354 "APICWriteMmio", "APICReadMmio");
1355 if (RT_FAILURE(rc))
1356 return rc;
1357
1358 pApicDev->pApicHlpR0 = pApicDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
1359 pApicDev->pCritSectR0 = pApicDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
1360 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1361 "APICWriteMmio", "APICReadMmio");
1362 if (RT_FAILURE(rc))
1363 return rc;
1364 }
1365
1366 /*
1367 * Create the APIC timers.
1368 */
1369 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1370 {
1371 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1372 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1373 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1374 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1375 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1376 if (RT_SUCCESS(rc))
1377 {
1378 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1379 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1380 }
1381 else
1382 return rc;
1383 }
1384
1385 /*
1386 * Register saved state callbacks.
1387 */
1388 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1389 apicR3LoadExec);
1390 if (RT_FAILURE(rc))
1391 return rc;
1392
1393 /*
1394 * Register debugger info callback.
1395 */
1396 rc = PDMDevHlpDBGFInfoRegister(pDevIns, "apic", "Display local APIC state for current CPU. Recognizes "
1397 "'basic', 'lvt', 'timer' as arguments, defaults to 'basic'.", apicR3DbgInfo);
1398 AssertRCReturn(rc, rc);
1399
1400#ifdef VBOX_WITH_STATISTICS
1401 /*
1402 * Statistics.
1403 */
1404#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1405 do { \
1406 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1407 AssertRCReturn(rc, rc); \
1408 } while(0)
1409
1410#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1411 do { \
1412 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1413 idCpu); \
1414 AssertRCReturn(rc, rc); \
1415 } while(0)
1416
1417 bool const fHasRC = !HMIsEnabled(pVM);
1418 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1419 {
1420 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1421 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1422
1423 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR0, "Number of APIC MMIO reads in R0.", "/Devices/APIC/%u/R0/MmioRead");
1424 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR0, "Number of APIC MMIO writes in R0.", "/Devices/APIC/%u/R0/MmioWrite");
1425 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR0, "Number of APIC MSR reads in R0.", "/Devices/APIC/%u/R0/MsrRead");
1426 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR0, "Number of APIC MSR writes in R0.", "/Devices/APIC/%u/R0/MsrWrite");
1427
1428 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1429 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1430 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1431 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1432
1433 if (fHasRC)
1434 {
1435 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRC, "Number of APIC MMIO reads in RC.", "/Devices/APIC/%u/RC/MmioRead");
1436 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRC, "Number of APIC MMIO writes in RC.", "/Devices/APIC/%u/RC/MmioWrite");
1437 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRC, "Number of APIC MSR reads in RC.", "/Devices/APIC/%u/RC/MsrRead");
1438 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRC, "Number of APIC MSR writes in RC.", "/Devices/APIC/%u/RC/MsrWrite");
1439 }
1440
1441 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1442 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1443 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1444
1445 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1446 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1447 }
1448# undef APIC_PROF_COUNTER
1449# undef APIC_REG_ACCESS_COUNTER
1450#endif
1451
1452 return VINF_SUCCESS;
1453}
1454
1455
1456/**
1457 * APIC device registration structure.
1458 */
1459const PDMDEVREG g_DeviceAPIC =
1460{
1461 /* u32Version */
1462 PDM_DEVREG_VERSION,
1463 /* szName */
1464 "apic",
1465 /* szRCMod */
1466 "VMMRC.rc",
1467 /* szR0Mod */
1468 "VMMR0.r0",
1469 /* pszDescription */
1470 "Advanced Programmable Interrupt Controller",
1471 /* fFlags */
1472 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1473 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1474 /* fClass */
1475 PDM_DEVREG_CLASS_PIC,
1476 /* cMaxInstances */
1477 1,
1478 /* cbInstance */
1479 sizeof(APICDEV),
1480 /* pfnConstruct */
1481 apicR3Construct,
1482 /* pfnDestruct */
1483 apicR3Destruct,
1484 /* pfnRelocate */
1485 apicR3Relocate,
1486 /* pfnMemSetup */
1487 NULL,
1488 /* pfnPowerOn */
1489 NULL,
1490 /* pfnReset */
1491 apicR3Reset,
1492 /* pfnSuspend */
1493 NULL,
1494 /* pfnResume */
1495 NULL,
1496 /* pfnAttach */
1497 NULL,
1498 /* pfnDetach */
1499 NULL,
1500 /* pfnQueryInterface. */
1501 NULL,
1502 /* pfnInitComplete */
1503 apicR3InitComplete,
1504 /* pfnPowerOff */
1505 NULL,
1506 /* pfnSoftReset */
1507 NULL,
1508 /* u32VersionEnd */
1509 PDM_DEVREG_VERSION
1510};
1511
1512#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1513
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