VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/APIC.cpp@ 61769

Last change on this file since 61769 was 61769, checked in by vboxsync, 9 years ago

VMM/APIC: Fix misleading TPR/PPR priority (vs subclass) values in info debugger output.
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1/* $Id: APIC.cpp 61769 2016-06-20 15:09:04Z vboxsync $ */
2/** @file
3 * APIC - Advanced Programmable Interrupt Controller.
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_APIC
23#include <VBox/log.h>
24#include "APICInternal.h"
25#include <VBox/vmm/cpum.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/mm.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/ssm.h>
30#include <VBox/vmm/vm.h>
31
32
33#ifndef VBOX_DEVICE_STRUCT_TESTCASE
34/*********************************************************************************************************************************
35* Defined Constants And Macros *
36*********************************************************************************************************************************/
37/** The current APIC saved state version. */
38#define APIC_SAVED_STATE_VERSION 5
39/** VirtualBox 5.1 beta2 - pre fActiveLintX. */
40#define APIC_SAVED_STATE_VERSION_VBOX_51_BETA2 4
41/** The saved state version used by VirtualBox 5.0 and
42 * earlier. */
43#define APIC_SAVED_STATE_VERSION_VBOX_50 3
44/** The saved state version used by VirtualBox v3 and earlier.
45 * This does not include the config. */
46#define APIC_SAVED_STATE_VERSION_VBOX_30 2
47/** Some ancient version... */
48#define APIC_SAVED_STATE_VERSION_ANCIENT 1
49
50#ifdef VBOX_WITH_STATISTICS
51# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
52 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
53#else
54# define X2APIC_MSRRANGE(a_uFirst, a_uLast, a_szName) \
55 { (a_uFirst), (a_uLast), kCpumMsrRdFn_Ia32X2ApicN, kCpumMsrWrFn_Ia32X2ApicN, 0, 0, 0, 0, 0, a_szName }
56#endif
57
58
59/*********************************************************************************************************************************
60* Global Variables *
61*********************************************************************************************************************************/
62/**
63 * MSR range supported by the x2APIC.
64 * See Intel spec. 10.12.2 "x2APIC Register Availability".
65 */
66static CPUMMSRRANGE const g_MsrRange_x2Apic = X2APIC_MSRRANGE(MSR_IA32_X2APIC_START, MSR_IA32_X2APIC_END, "x2APIC range");
67#undef X2APIC_MSRRANGE
68
69/** Saved state field descriptors for XAPICPAGE. */
70static const SSMFIELD g_aXApicPageFields[] =
71{
72 SSMFIELD_ENTRY( XAPICPAGE, id.u8ApicId),
73 SSMFIELD_ENTRY( XAPICPAGE, version.all.u32Version),
74 SSMFIELD_ENTRY( XAPICPAGE, tpr.u8Tpr),
75 SSMFIELD_ENTRY( XAPICPAGE, apr.u8Apr),
76 SSMFIELD_ENTRY( XAPICPAGE, ppr.u8Ppr),
77 SSMFIELD_ENTRY( XAPICPAGE, ldr.all.u32Ldr),
78 SSMFIELD_ENTRY( XAPICPAGE, dfr.all.u32Dfr),
79 SSMFIELD_ENTRY( XAPICPAGE, svr.all.u32Svr),
80 SSMFIELD_ENTRY( XAPICPAGE, isr.u[0].u32Reg),
81 SSMFIELD_ENTRY( XAPICPAGE, isr.u[1].u32Reg),
82 SSMFIELD_ENTRY( XAPICPAGE, isr.u[2].u32Reg),
83 SSMFIELD_ENTRY( XAPICPAGE, isr.u[3].u32Reg),
84 SSMFIELD_ENTRY( XAPICPAGE, isr.u[4].u32Reg),
85 SSMFIELD_ENTRY( XAPICPAGE, isr.u[5].u32Reg),
86 SSMFIELD_ENTRY( XAPICPAGE, isr.u[6].u32Reg),
87 SSMFIELD_ENTRY( XAPICPAGE, isr.u[7].u32Reg),
88 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[0].u32Reg),
89 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[1].u32Reg),
90 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[2].u32Reg),
91 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[3].u32Reg),
92 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[4].u32Reg),
93 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[5].u32Reg),
94 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[6].u32Reg),
95 SSMFIELD_ENTRY( XAPICPAGE, tmr.u[7].u32Reg),
96 SSMFIELD_ENTRY( XAPICPAGE, irr.u[0].u32Reg),
97 SSMFIELD_ENTRY( XAPICPAGE, irr.u[1].u32Reg),
98 SSMFIELD_ENTRY( XAPICPAGE, irr.u[2].u32Reg),
99 SSMFIELD_ENTRY( XAPICPAGE, irr.u[3].u32Reg),
100 SSMFIELD_ENTRY( XAPICPAGE, irr.u[4].u32Reg),
101 SSMFIELD_ENTRY( XAPICPAGE, irr.u[5].u32Reg),
102 SSMFIELD_ENTRY( XAPICPAGE, irr.u[6].u32Reg),
103 SSMFIELD_ENTRY( XAPICPAGE, irr.u[7].u32Reg),
104 SSMFIELD_ENTRY( XAPICPAGE, esr.all.u32Errors),
105 SSMFIELD_ENTRY( XAPICPAGE, icr_lo.all.u32IcrLo),
106 SSMFIELD_ENTRY( XAPICPAGE, icr_hi.all.u32IcrHi),
107 SSMFIELD_ENTRY( XAPICPAGE, lvt_timer.all.u32LvtTimer),
108 SSMFIELD_ENTRY( XAPICPAGE, lvt_thermal.all.u32LvtThermal),
109 SSMFIELD_ENTRY( XAPICPAGE, lvt_perf.all.u32LvtPerf),
110 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint0.all.u32LvtLint0),
111 SSMFIELD_ENTRY( XAPICPAGE, lvt_lint1.all.u32LvtLint1),
112 SSMFIELD_ENTRY( XAPICPAGE, lvt_error.all.u32LvtError),
113 SSMFIELD_ENTRY( XAPICPAGE, timer_icr.u32InitialCount),
114 SSMFIELD_ENTRY( XAPICPAGE, timer_ccr.u32CurrentCount),
115 SSMFIELD_ENTRY( XAPICPAGE, timer_dcr.all.u32DivideValue),
116 SSMFIELD_ENTRY_TERM()
117};
118
119/** Saved state field descriptors for X2APICPAGE. */
120static const SSMFIELD g_aX2ApicPageFields[] =
121{
122 SSMFIELD_ENTRY(X2APICPAGE, id.u32ApicId),
123 SSMFIELD_ENTRY(X2APICPAGE, version.all.u32Version),
124 SSMFIELD_ENTRY(X2APICPAGE, tpr.u8Tpr),
125 SSMFIELD_ENTRY(X2APICPAGE, ppr.u8Ppr),
126 SSMFIELD_ENTRY(X2APICPAGE, ldr.u32LogicalApicId),
127 SSMFIELD_ENTRY(X2APICPAGE, svr.all.u32Svr),
128 SSMFIELD_ENTRY(X2APICPAGE, isr.u[0].u32Reg),
129 SSMFIELD_ENTRY(X2APICPAGE, isr.u[1].u32Reg),
130 SSMFIELD_ENTRY(X2APICPAGE, isr.u[2].u32Reg),
131 SSMFIELD_ENTRY(X2APICPAGE, isr.u[3].u32Reg),
132 SSMFIELD_ENTRY(X2APICPAGE, isr.u[4].u32Reg),
133 SSMFIELD_ENTRY(X2APICPAGE, isr.u[5].u32Reg),
134 SSMFIELD_ENTRY(X2APICPAGE, isr.u[6].u32Reg),
135 SSMFIELD_ENTRY(X2APICPAGE, isr.u[7].u32Reg),
136 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[0].u32Reg),
137 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[1].u32Reg),
138 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[2].u32Reg),
139 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[3].u32Reg),
140 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[4].u32Reg),
141 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[5].u32Reg),
142 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[6].u32Reg),
143 SSMFIELD_ENTRY(X2APICPAGE, tmr.u[7].u32Reg),
144 SSMFIELD_ENTRY(X2APICPAGE, irr.u[0].u32Reg),
145 SSMFIELD_ENTRY(X2APICPAGE, irr.u[1].u32Reg),
146 SSMFIELD_ENTRY(X2APICPAGE, irr.u[2].u32Reg),
147 SSMFIELD_ENTRY(X2APICPAGE, irr.u[3].u32Reg),
148 SSMFIELD_ENTRY(X2APICPAGE, irr.u[4].u32Reg),
149 SSMFIELD_ENTRY(X2APICPAGE, irr.u[5].u32Reg),
150 SSMFIELD_ENTRY(X2APICPAGE, irr.u[6].u32Reg),
151 SSMFIELD_ENTRY(X2APICPAGE, irr.u[7].u32Reg),
152 SSMFIELD_ENTRY(X2APICPAGE, esr.all.u32Errors),
153 SSMFIELD_ENTRY(X2APICPAGE, icr_lo.all.u32IcrLo),
154 SSMFIELD_ENTRY(X2APICPAGE, icr_hi.u32IcrHi),
155 SSMFIELD_ENTRY(X2APICPAGE, lvt_timer.all.u32LvtTimer),
156 SSMFIELD_ENTRY(X2APICPAGE, lvt_thermal.all.u32LvtThermal),
157 SSMFIELD_ENTRY(X2APICPAGE, lvt_perf.all.u32LvtPerf),
158 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint0.all.u32LvtLint0),
159 SSMFIELD_ENTRY(X2APICPAGE, lvt_lint1.all.u32LvtLint1),
160 SSMFIELD_ENTRY(X2APICPAGE, lvt_error.all.u32LvtError),
161 SSMFIELD_ENTRY(X2APICPAGE, timer_icr.u32InitialCount),
162 SSMFIELD_ENTRY(X2APICPAGE, timer_ccr.u32CurrentCount),
163 SSMFIELD_ENTRY(X2APICPAGE, timer_dcr.all.u32DivideValue),
164 SSMFIELD_ENTRY_TERM()
165};
166
167
168/**
169 * Initializes per-VCPU APIC to the state following an INIT reset
170 * ("Wait-for-SIPI" state).
171 *
172 * @param pVCpu The cross context virtual CPU structure.
173 */
174static void apicR3InitIpi(PVMCPU pVCpu)
175{
176 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
177 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
178
179 /*
180 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
181 * and AMD spec 16.3.2 "APIC Registers".
182 *
183 * The reason we don't simply zero out the entire APIC page and only set the non-zero members
184 * is because there are some registers that are not touched by the INIT IPI (e.g. version)
185 * operation and this function is only a subset of the reset operation.
186 */
187 RT_ZERO(pXApicPage->irr);
188 RT_ZERO(pXApicPage->irr);
189 RT_ZERO(pXApicPage->isr);
190 RT_ZERO(pXApicPage->tmr);
191 RT_ZERO(pXApicPage->icr_hi);
192 RT_ZERO(pXApicPage->icr_lo);
193 RT_ZERO(pXApicPage->ldr);
194 RT_ZERO(pXApicPage->tpr);
195 RT_ZERO(pXApicPage->ppr);
196 RT_ZERO(pXApicPage->timer_icr);
197 RT_ZERO(pXApicPage->timer_ccr);
198 RT_ZERO(pXApicPage->timer_dcr);
199
200 pXApicPage->dfr.u.u4Model = XAPICDESTFORMAT_FLAT;
201 pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
202
203 /** @todo CMCI. */
204
205 RT_ZERO(pXApicPage->lvt_timer);
206 pXApicPage->lvt_timer.u.u1Mask = 1;
207
208#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
209 RT_ZERO(pXApicPage->lvt_thermal);
210 pXApicPage->lvt_thermal.u.u1Mask = 1;
211#endif
212
213 RT_ZERO(pXApicPage->lvt_perf);
214 pXApicPage->lvt_perf.u.u1Mask = 1;
215
216 RT_ZERO(pXApicPage->lvt_lint0);
217 pXApicPage->lvt_lint0.u.u1Mask = 1;
218
219 RT_ZERO(pXApicPage->lvt_lint1);
220 pXApicPage->lvt_lint1.u.u1Mask = 1;
221
222 RT_ZERO(pXApicPage->lvt_error);
223 pXApicPage->lvt_error.u.u1Mask = 1;
224
225 RT_ZERO(pXApicPage->svr);
226 pXApicPage->svr.u.u8SpuriousVector = 0xff;
227
228 /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
229 PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
230 RT_ZERO(pX2ApicPage->self_ipi);
231
232 /* Clear the pending-interrupt bitmaps. */
233 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
234 RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
235 RT_BZERO(pApicCpu->pvApicPibR3, sizeof(APICPIB));
236
237 /* Clear the interrupt line states for LINT0 and LINT1 pins. */
238 pApicCpu->fActiveLint0 = false;
239 pApicCpu->fActiveLint1 = false;
240}
241
242
243/**
244 * Resets the APIC base MSR.
245 *
246 * @param pVCpu The cross context virtual CPU structure.
247 */
248static void apicR3ResetBaseMsr(PVMCPU pVCpu)
249{
250 /*
251 * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
252 *
253 * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
254 * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
255 *
256 * [1] See AMD spec. 14.1.3 "Processor Initialization State"
257 * [2] See Intel spec. 10.12.5.1 "x2APIC States".
258 */
259 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
260
261 /* Construct. */
262 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
263 PAPIC pApic = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
264 uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;;
265 if (pVCpu->idCpu == 0)
266 uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
267
268 /* If the VM was configured with disabled mode, don't enable xAPIC mode. */
269 if (pApic->enmOriginalMode != APICMODE_DISABLED)
270 {
271 uApicBaseMsr |= MSR_IA32_APICBASE_EN;
272
273 /*
274 * While coming out of a reset the APIC is enabled and in xAPIC mode. If software had previously
275 * disabled the APIC (which results in the CPUID bit being cleared as well) we re-enable it here.
276 * See Intel spec. 10.12.5.1 "x2APIC States".
277 */
278 /** @todo CPUID bits needs to be done on a per-VCPU basis! */
279 if (!CPUMGetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC))
280 {
281 LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
282 CPUMSetGuestCpuIdFeature(pVCpu->CTX_SUFF(pVM), CPUMCPUIDFEATURE_APIC);
283 }
284 }
285
286 /* Commit. */
287 ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
288}
289
290
291/**
292 * Initializes per-VCPU APIC to the state following a power-up or hardware
293 * reset.
294 *
295 * @param pVCpu The cross context virtual CPU structure.
296 * @param fResetApicBaseMsr Whether to reset the APIC base MSR.
297 */
298VMMR3_INT_DECL(void) APICR3Reset(PVMCPU pVCpu, bool fResetApicBaseMsr)
299{
300 VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
301
302 LogFlow(("APIC%u: APICR3Reset: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
303
304#ifdef VBOX_STRICT
305 /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
306 uint32_t uEax, uEbx, uEcx, uEdx;
307 uEax = uEbx = uEcx = uEdx = UINT32_MAX;
308 CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
309 Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
310#endif
311
312 /*
313 * The state following a power-up or reset is a superset of the INIT state.
314 * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
315 */
316 apicR3InitIpi(pVCpu);
317
318 /*
319 * The APIC version register is read-only, so just initialize it here.
320 * It is not clear from the specs, where exactly it is initialized.
321 * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
322 */
323 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
324#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
325 pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
326 pXApicPage->version.u.u8Version = XAPIC_HARDWARE_VERSION_P4;
327 AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
328#else
329# error "Implement Pentium and P6 family APIC architectures"
330#endif
331
332 /** @todo It isn't clear in the spec. where exactly the default base address
333 * is (re)initialized, atm we do it here in Reset. */
334 if (fResetApicBaseMsr)
335 apicR3ResetBaseMsr(pVCpu);
336
337 /*
338 * Initialize the APIC ID register to xAPIC format.
339 */
340 ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
341 pXApicPage->id.u8ApicId = pVCpu->idCpu;
342}
343
344
345/**
346 * Receives an INIT IPI.
347 *
348 * @param pVCpu The cross context virtual CPU structure.
349 */
350VMMR3_INT_DECL(void) APICR3InitIpi(PVMCPU pVCpu)
351{
352 VMCPU_ASSERT_EMT(pVCpu);
353 LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
354 apicR3InitIpi(pVCpu);
355}
356
357
358/**
359 * Helper for dumping an APIC 256-bit sparse register.
360 *
361 * @param pApicReg The APIC 256-bit spare register.
362 * @param pHlp The debug output helper.
363 */
364static void apicR3DbgInfo256BitReg(volatile const XAPIC256BITREG *pApicReg, PCDBGFINFOHLP pHlp)
365{
366 ssize_t const cFragments = RT_ELEMENTS(pApicReg->u);
367 unsigned const cBitsPerFragment = sizeof(pApicReg->u[0].u32Reg) * 8;
368 XAPIC256BITREG ApicReg;
369 RT_ZERO(ApicReg);
370
371 pHlp->pfnPrintf(pHlp, " ");
372 for (ssize_t i = cFragments - 1; i >= 0; i--)
373 {
374 uint32_t const uFragment = pApicReg->u[i].u32Reg;
375 ApicReg.u[i].u32Reg = uFragment;
376 pHlp->pfnPrintf(pHlp, "%08x", uFragment);
377 }
378 pHlp->pfnPrintf(pHlp, "\n");
379
380 uint32_t cPending = 0;
381 pHlp->pfnPrintf(pHlp, " Pending:");
382 for (ssize_t i = cFragments - 1; i >= 0; i--)
383 {
384 uint32_t uFragment = ApicReg.u[i].u32Reg;
385 if (uFragment)
386 {
387 do
388 {
389 unsigned idxSetBit = ASMBitLastSetU32(uFragment);
390 --idxSetBit;
391 ASMBitClear(&uFragment, idxSetBit);
392
393 idxSetBit += (i * cBitsPerFragment);
394 pHlp->pfnPrintf(pHlp, " %#02x", idxSetBit);
395 ++cPending;
396 } while (uFragment);
397 }
398 }
399 if (!cPending)
400 pHlp->pfnPrintf(pHlp, " None");
401 pHlp->pfnPrintf(pHlp, "\n");
402}
403
404
405/**
406 * Helper for dumping an APIC pending-interrupt bitmap.
407 *
408 * @param pApicPib The pending-interrupt bitmap.
409 * @param pHlp The debug output helper.
410 */
411static void apicR3DbgInfoPib(PCAPICPIB pApicPib, PCDBGFINFOHLP pHlp)
412{
413 /* Copy the pending-interrupt bitmap as an APIC 256-bit sparse register. */
414 XAPIC256BITREG ApicReg;
415 RT_ZERO(ApicReg);
416 ssize_t const cFragmentsDst = RT_ELEMENTS(ApicReg.u);
417 ssize_t const cFragmentsSrc = RT_ELEMENTS(pApicPib->aVectorBitmap);
418 AssertCompile(RT_ELEMENTS(ApicReg.u) == 2 * RT_ELEMENTS(pApicPib->aVectorBitmap));
419 for (ssize_t idxPib = cFragmentsSrc - 1, idxReg = cFragmentsDst - 1; idxPib >= 0; idxPib--, idxReg -= 2)
420 {
421 uint64_t const uFragment = pApicPib->aVectorBitmap[idxPib];
422 uint32_t const uFragmentLo = RT_LO_U32(uFragment);
423 uint32_t const uFragmentHi = RT_HI_U32(uFragment);
424 ApicReg.u[idxReg].u32Reg = uFragmentHi;
425 ApicReg.u[idxReg - 1].u32Reg = uFragmentLo;
426 }
427
428 /* Dump it. */
429 apicR3DbgInfo256BitReg(&ApicReg, pHlp);
430}
431
432
433/**
434 * Dumps basic APIC state.
435 *
436 * @param pVM The cross context VM structure.
437 * @param pHlp The info helpers.
438 * @param pszArgs Arguments, ignored.
439 */
440static DECLCALLBACK(void) apicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
441{
442 NOREF(pszArgs);
443 PVMCPU pVCpu = VMMGetCpu(pVM);
444 if (!pVCpu)
445 pVCpu = &pVM->aCpus[0];
446
447 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
448 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
449 PCX2APICPAGE pX2ApicPage = VMCPU_TO_CX2APICPAGE(pVCpu);
450
451 uint64_t const uBaseMsr = pApicCpu->uApicBaseMsr;
452 APICMODE const enmMode = apicGetMode(uBaseMsr);
453 bool const fX2ApicMode = XAPIC_IN_X2APIC_MODE(pVCpu);
454
455 pHlp->pfnPrintf(pHlp, "APIC%u:\n", pVCpu->idCpu);
456 pHlp->pfnPrintf(pHlp, " APIC Base MSR = %#RX64 (Addr=%#RX64)\n", uBaseMsr,
457 MSR_IA32_APICBASE_GET_ADDR(uBaseMsr));
458 pHlp->pfnPrintf(pHlp, " Mode = %u (%s)\n", enmMode, apicGetModeName(enmMode));
459 if (fX2ApicMode)
460 {
461 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pX2ApicPage->id.u32ApicId,
462 pX2ApicPage->id.u32ApicId);
463 }
464 else
465 pHlp->pfnPrintf(pHlp, " APIC ID = %u (%#x)\n", pXApicPage->id.u8ApicId, pXApicPage->id.u8ApicId);
466 pHlp->pfnPrintf(pHlp, " Version = %#x\n", pXApicPage->version.all.u32Version);
467 pHlp->pfnPrintf(pHlp, " APIC Version = %#x\n", pXApicPage->version.u.u8Version);
468 pHlp->pfnPrintf(pHlp, " Max LVT entry index (0..N) = %u\n", pXApicPage->version.u.u8MaxLvtEntry);
469 pHlp->pfnPrintf(pHlp, " EOI Broadcast supression = %RTbool\n", pXApicPage->version.u.fEoiBroadcastSupression);
470 if (!fX2ApicMode)
471 pHlp->pfnPrintf(pHlp, " APR = %u (%#x)\n", pXApicPage->apr.u8Apr, pXApicPage->apr.u8Apr);
472 pHlp->pfnPrintf(pHlp, " TPR = %u (%#x)\n", pXApicPage->tpr.u8Tpr, pXApicPage->tpr.u8Tpr);
473 pHlp->pfnPrintf(pHlp, " Task-priority class = %#x\n", XAPIC_TPR_GET_TP(pXApicPage->tpr.u8Tpr) >> 4);
474 pHlp->pfnPrintf(pHlp, " Task-priority subclass = %#x\n", XAPIC_TPR_GET_TP_SUBCLASS(pXApicPage->tpr.u8Tpr));
475 pHlp->pfnPrintf(pHlp, " PPR = %u (%#x)\n", pXApicPage->ppr.u8Ppr, pXApicPage->ppr.u8Ppr);
476 pHlp->pfnPrintf(pHlp, " Processor-priority class = %#x\n", XAPIC_PPR_GET_PP(pXApicPage->ppr.u8Ppr) >> 4);
477 pHlp->pfnPrintf(pHlp, " Processor-priority subclass = %#x\n", XAPIC_PPR_GET_PP_SUBCLASS(pXApicPage->ppr.u8Ppr));
478 if (!fX2ApicMode)
479 pHlp->pfnPrintf(pHlp, " RRD = %u (%#x)\n", pXApicPage->rrd.u32Rrd, pXApicPage->rrd.u32Rrd);
480 pHlp->pfnPrintf(pHlp, " LDR = %#x\n", pXApicPage->ldr.all.u32Ldr);
481 pHlp->pfnPrintf(pHlp, " Logical APIC ID = %#x\n", fX2ApicMode ? pX2ApicPage->ldr.u32LogicalApicId
482 : pXApicPage->ldr.u.u8LogicalApicId);
483 if (!fX2ApicMode)
484 {
485 pHlp->pfnPrintf(pHlp, " DFR = %#x\n", pXApicPage->dfr.all.u32Dfr);
486 pHlp->pfnPrintf(pHlp, " Model = %#x (%s)\n", pXApicPage->dfr.u.u4Model,
487 apicGetDestFormatName((XAPICDESTFORMAT)pXApicPage->dfr.u.u4Model));
488 }
489 pHlp->pfnPrintf(pHlp, " SVR = %#x\n", pXApicPage->svr.all.u32Svr);
490 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->svr.u.u8SpuriousVector,
491 pXApicPage->svr.u.u8SpuriousVector);
492 pHlp->pfnPrintf(pHlp, " Software Enabled = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fApicSoftwareEnable));
493 pHlp->pfnPrintf(pHlp, " Supress EOI broadcast = %RTbool\n", RT_BOOL(pXApicPage->svr.u.fSupressEoiBroadcast));
494 pHlp->pfnPrintf(pHlp, " ISR\n");
495 apicR3DbgInfo256BitReg(&pXApicPage->isr, pHlp);
496 pHlp->pfnPrintf(pHlp, " TMR\n");
497 apicR3DbgInfo256BitReg(&pXApicPage->tmr, pHlp);
498 pHlp->pfnPrintf(pHlp, " IRR\n");
499 apicR3DbgInfo256BitReg(&pXApicPage->irr, pHlp);
500 pHlp->pfnPrintf(pHlp, " PIB\n");
501 apicR3DbgInfoPib((PCAPICPIB)pApicCpu->pvApicPibR3, pHlp);
502 pHlp->pfnPrintf(pHlp, " Level PIB\n");
503 apicR3DbgInfoPib(&pApicCpu->ApicPibLevel, pHlp);
504 pHlp->pfnPrintf(pHlp, " ESR Internal = %#x\n", pApicCpu->uEsrInternal);
505 pHlp->pfnPrintf(pHlp, " ESR = %#x\n", pXApicPage->esr.all.u32Errors);
506 pHlp->pfnPrintf(pHlp, " Redirectable IPI = %RTbool\n", pXApicPage->esr.u.fRedirectableIpi);
507 pHlp->pfnPrintf(pHlp, " Send Illegal Vector = %RTbool\n", pXApicPage->esr.u.fSendIllegalVector);
508 pHlp->pfnPrintf(pHlp, " Recv Illegal Vector = %RTbool\n", pXApicPage->esr.u.fRcvdIllegalVector);
509 pHlp->pfnPrintf(pHlp, " Illegal Register Address = %RTbool\n", pXApicPage->esr.u.fIllegalRegAddr);
510 pHlp->pfnPrintf(pHlp, " ICR Low = %#x\n", pXApicPage->icr_lo.all.u32IcrLo);
511 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->icr_lo.u.u8Vector,
512 pXApicPage->icr_lo.u.u8Vector);
513 pHlp->pfnPrintf(pHlp, " Delivery Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u3DeliveryMode,
514 apicGetDeliveryModeName((XAPICDELIVERYMODE)pXApicPage->icr_lo.u.u3DeliveryMode));
515 pHlp->pfnPrintf(pHlp, " Destination Mode = %#x (%s)\n", pXApicPage->icr_lo.u.u1DestMode,
516 apicGetDestModeName((XAPICDESTMODE)pXApicPage->icr_lo.u.u1DestMode));
517 if (!fX2ApicMode)
518 pHlp->pfnPrintf(pHlp, " Delivery Status = %u\n", pXApicPage->icr_lo.u.u1DeliveryStatus);
519 pHlp->pfnPrintf(pHlp, " Level = %u\n", pXApicPage->icr_lo.u.u1Level);
520 pHlp->pfnPrintf(pHlp, " Trigger Mode = %u (%s)\n", pXApicPage->icr_lo.u.u1TriggerMode,
521 apicGetTriggerModeName((XAPICTRIGGERMODE)pXApicPage->icr_lo.u.u1TriggerMode));
522 pHlp->pfnPrintf(pHlp, " Destination shorthand = %#x (%s)\n", pXApicPage->icr_lo.u.u2DestShorthand,
523 apicGetDestShorthandName((XAPICDESTSHORTHAND)pXApicPage->icr_lo.u.u2DestShorthand));
524 pHlp->pfnPrintf(pHlp, " ICR High = %#x\n", pXApicPage->icr_hi.all.u32IcrHi);
525 pHlp->pfnPrintf(pHlp, " Destination field/mask = %#x\n", fX2ApicMode ? pX2ApicPage->icr_hi.u32IcrHi
526 : pXApicPage->icr_hi.u.u8Dest);
527}
528
529
530/**
531 * Helper for dumping the LVT timer.
532 *
533 * @param pVCpu The cross context virtual CPU structure.
534 * @param pHlp The debug output helper.
535 */
536static void apicR3InfoLvtTimer(PVMCPU pVCpu, PCDBGFINFOHLP pHlp)
537{
538 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
539 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
540 pHlp->pfnPrintf(pHlp, "LVT Timer = %#RX32\n", uLvtTimer);
541 pHlp->pfnPrintf(pHlp, " Vector = %u (%#x)\n", pXApicPage->lvt_timer.u.u8Vector, pXApicPage->lvt_timer.u.u8Vector);
542 pHlp->pfnPrintf(pHlp, " Delivery status = %u\n", pXApicPage->lvt_timer.u.u1DeliveryStatus);
543 pHlp->pfnPrintf(pHlp, " Masked = %RTbool\n", XAPIC_LVT_IS_MASKED(uLvtTimer));
544 pHlp->pfnPrintf(pHlp, " Timer Mode = %#x (%s)\n", pXApicPage->lvt_timer.u.u2TimerMode,
545 apicGetTimerModeName((XAPICTIMERMODE)pXApicPage->lvt_timer.u.u2TimerMode));
546}
547
548
549/**
550 * Dumps APIC Local Vector Table (LVT) information.
551 *
552 * @param pVM The cross context VM structure.
553 * @param pHlp The info helpers.
554 * @param pszArgs Arguments, ignored.
555 */
556static DECLCALLBACK(void) apicR3InfoLvt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
557{
558 NOREF(pszArgs);
559 PVMCPU pVCpu = VMMGetCpu(pVM);
560 if (!pVCpu)
561 pVCpu = &pVM->aCpus[0];
562
563 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
564
565 /*
566 * Delivery modes available in the LVT entries. They're different (more reserved stuff) from the
567 * ICR delivery modes and hence we don't use apicGetDeliveryMode but mostly because we want small,
568 * fixed-length strings to fit our formatting needs here.
569 */
570 static const char * const s_apszLvtDeliveryModes[] =
571 {
572 "Fixed ",
573 "Rsvd ",
574 "SMI ",
575 "Rsvd ",
576 "NMI ",
577 "INIT ",
578 "Rsvd ",
579 "ExtINT"
580 };
581 /* Delivery Status. */
582 static const char * const s_apszLvtDeliveryStatus[] =
583 {
584 "Idle",
585 "Pend"
586 };
587 const char *pszNotApplicable = "";
588
589 pHlp->pfnPrintf(pHlp, "VCPU[%u] APIC Local Vector Table (LVT):\n", pVCpu->idCpu);
590 pHlp->pfnPrintf(pHlp, "lvt timermode mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
591 /* Timer. */
592 {
593 /* Timer modes. */
594 static const char * const s_apszLvtTimerModes[] =
595 {
596 "One-shot ",
597 "Periodic ",
598 "TSC-dline"
599 };
600 const uint32_t uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
601 const XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
602 const char *pszTimerMode = s_apszLvtTimerModes[enmTimerMode];
603 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtTimer);
604 const uint8_t uDeliveryStatus = uLvtTimer & XAPIC_LVT_DELIVERY_STATUS;
605 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
606 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
607
608 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
609 "Timer",
610 pszTimerMode,
611 uMask,
612 pszNotApplicable, /* TriggerMode */
613 pszNotApplicable, /* Remote IRR */
614 pszNotApplicable, /* Polarity */
615 pszDeliveryStatus,
616 pszNotApplicable, /* Delivery Mode */
617 uVector,
618 uVector);
619 }
620
621#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
622 /* Thermal sensor. */
623 {
624 uint32_t const uLvtThermal = pXApicPage->lvt_thermal.all.u32LvtThermal;
625 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtThermal);
626 const uint8_t uDeliveryStatus = uLvtThermal & XAPIC_LVT_DELIVERY_STATUS;
627 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
628 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtThermal);
629 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
630 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtThermal);
631
632 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
633 "Thermal",
634 pszNotApplicable, /* Timer mode */
635 uMask,
636 pszNotApplicable, /* TriggerMode */
637 pszNotApplicable, /* Remote IRR */
638 pszNotApplicable, /* Polarity */
639 pszDeliveryStatus,
640 pszDeliveryMode,
641 uVector,
642 uVector);
643 }
644#endif
645
646 /* Performance Monitor Counters. */
647 {
648 uint32_t const uLvtPerf = pXApicPage->lvt_thermal.all.u32LvtThermal;
649 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtPerf);
650 const uint8_t uDeliveryStatus = uLvtPerf & XAPIC_LVT_DELIVERY_STATUS;
651 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
652 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtPerf);
653 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
654 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtPerf);
655
656 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
657 "Perf",
658 pszNotApplicable, /* Timer mode */
659 uMask,
660 pszNotApplicable, /* TriggerMode */
661 pszNotApplicable, /* Remote IRR */
662 pszNotApplicable, /* Polarity */
663 pszDeliveryStatus,
664 pszDeliveryMode,
665 uVector,
666 uVector);
667 }
668
669 /* LINT0, LINT1. */
670 {
671 /* LINTx name. */
672 static const char * const s_apszLvtLint[] =
673 {
674 "LINT0",
675 "LINT1"
676 };
677 /* Trigger mode. */
678 static const char * const s_apszLvtTriggerModes[] =
679 {
680 "Edge ",
681 "Level"
682 };
683 /* Polarity. */
684 static const char * const s_apszLvtPolarity[] =
685 {
686 "ActiveHi",
687 "ActiveLo"
688 };
689
690 uint32_t aLvtLint[2];
691 aLvtLint[0] = pXApicPage->lvt_lint0.all.u32LvtLint0;
692 aLvtLint[1] = pXApicPage->lvt_lint1.all.u32LvtLint1;
693 for (size_t i = 0; i < RT_ELEMENTS(aLvtLint); i++)
694 {
695 uint32_t const uLvtLint = aLvtLint[i];
696 const char *pszLint = s_apszLvtLint[i];
697 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtLint);
698 const XAPICTRIGGERMODE enmTriggerMode = XAPIC_LVT_GET_TRIGGER_MODE(uLvtLint);
699 const char *pszTriggerMode = s_apszLvtTriggerModes[enmTriggerMode];
700 const uint8_t uRemoteIrr = XAPIC_LVT_GET_REMOTE_IRR(uLvtLint);
701 const uint8_t uPolarity = XAPIC_LVT_GET_POLARITY(uLvtLint);
702 const char *pszPolarity = s_apszLvtPolarity[uPolarity];
703 const uint8_t uDeliveryStatus = uLvtLint & XAPIC_LVT_DELIVERY_STATUS;
704 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
705 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtLint);
706 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
707 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtLint);
708
709 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %u %8s %4s %6s %3u (%#x)\n",
710 pszLint,
711 pszNotApplicable, /* Timer mode */
712 uMask,
713 pszTriggerMode,
714 uRemoteIrr,
715 pszPolarity,
716 pszDeliveryStatus,
717 pszDeliveryMode,
718 uVector,
719 uVector);
720 }
721 }
722
723 /* Error. */
724 {
725 uint32_t const uLvtError = pXApicPage->lvt_thermal.all.u32LvtThermal;
726 const uint8_t uMask = XAPIC_LVT_IS_MASKED(uLvtError);
727 const uint8_t uDeliveryStatus = uLvtError & XAPIC_LVT_DELIVERY_STATUS;
728 const char *pszDeliveryStatus = s_apszLvtDeliveryStatus[uDeliveryStatus];
729 const XAPICDELIVERYMODE enmDeliveryMode = XAPIC_LVT_GET_DELIVERY_MODE(uLvtError);
730 const char *pszDeliveryMode = s_apszLvtDeliveryModes[enmDeliveryMode];
731 const uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtError);
732
733 pHlp->pfnPrintf(pHlp, "%-7s %9s %u %5s %1s %8s %4s %6s %3u (%#x)\n",
734 "Error",
735 pszNotApplicable, /* Timer mode */
736 uMask,
737 pszNotApplicable, /* TriggerMode */
738 pszNotApplicable, /* Remote IRR */
739 pszNotApplicable, /* Polarity */
740 pszDeliveryStatus,
741 pszDeliveryMode,
742 uVector,
743 uVector);
744 }
745}
746
747
748/**
749 * Dumps the APIC timer information.
750 *
751 * @param pVM The cross context VM structure.
752 * @param pHlp The info helpers.
753 * @param pszArgs Arguments, ignored.
754 */
755static DECLCALLBACK(void) apicR3InfoTimer(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
756{
757 NOREF(pszArgs);
758 PVMCPU pVCpu = VMMGetCpu(pVM);
759 if (!pVCpu)
760 pVCpu = &pVM->aCpus[0];
761
762 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
763 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
764
765 pHlp->pfnPrintf(pHlp, "VCPU[%u] Local APIC timer:\n", pVCpu->idCpu);
766 pHlp->pfnPrintf(pHlp, " ICR = %#RX32\n", pXApicPage->timer_icr.u32InitialCount);
767 pHlp->pfnPrintf(pHlp, " CCR = %#RX32\n", pXApicPage->timer_ccr.u32CurrentCount);
768 pHlp->pfnPrintf(pHlp, " DCR = %#RX32\n", pXApicPage->timer_dcr.all.u32DivideValue);
769 pHlp->pfnPrintf(pHlp, " Timer shift = %#x\n", apicGetTimerShift(pXApicPage));
770 pHlp->pfnPrintf(pHlp, " Timer initial TS = %#RU64\n", pApicCpu->u64TimerInitial);
771 apicR3InfoLvtTimer(pVCpu, pHlp);
772}
773
774
775/**
776 * Converts legacy PDMAPICMODE to the new APICMODE enum.
777 *
778 * @returns The new APIC mode.
779 * @param enmLegacyMode The legacy mode to convert.
780 */
781static APICMODE apicR3ConvertFromLegacyApicMode(PDMAPICMODE enmLegacyMode)
782{
783 switch (enmLegacyMode)
784 {
785 case PDMAPICMODE_NONE: return APICMODE_DISABLED;
786 case PDMAPICMODE_APIC: return APICMODE_XAPIC;
787 case PDMAPICMODE_X2APIC: return APICMODE_X2APIC;
788 case PDMAPICMODE_INVALID: return APICMODE_INVALID;
789 default: break;
790 }
791 return (APICMODE)enmLegacyMode;
792}
793
794
795/**
796 * Converts the new APICMODE enum to the legacy PDMAPICMODE enum.
797 *
798 * @returns The legacy APIC mode.
799 * @param enmMode The APIC mode to convert.
800 */
801static PDMAPICMODE apicR3ConvertToLegacyApicMode(APICMODE enmMode)
802{
803 switch (enmMode)
804 {
805 case APICMODE_DISABLED: return PDMAPICMODE_NONE;
806 case APICMODE_XAPIC: return PDMAPICMODE_APIC;
807 case APICMODE_X2APIC: return PDMAPICMODE_X2APIC;
808 case APICMODE_INVALID: return PDMAPICMODE_INVALID;
809 default: break;
810 }
811 return (PDMAPICMODE)enmMode;
812}
813
814
815#ifdef APIC_FUZZY_SSM_COMPAT_TEST
816/**
817 * Reads a 32-bit register at a specified offset.
818 *
819 * @returns The value at the specified offset.
820 * @param pXApicPage The xAPIC page.
821 * @param offReg The offset of the register being read.
822 *
823 * @remarks Duplicate of apicReadRaw32()!
824 */
825static uint32_t apicR3ReadRawR32(PCXAPICPAGE pXApicPage, uint16_t offReg)
826{
827 Assert(offReg < sizeof(*pXApicPage) - sizeof(uint32_t));
828 uint8_t const *pbXApic = (const uint8_t *)pXApicPage;
829 uint32_t const uValue = *(const uint32_t *)(pbXApic + offReg);
830 return uValue;
831}
832
833
834/**
835 * Helper for dumping per-VCPU APIC state to the release logger.
836 *
837 * This is primarily concerned about the APIC state relevant for saved-states.
838 *
839 * @param pVCpu The cross context virtual CPU structure.
840 * @param pszPrefix A caller supplied prefix before dumping the state.
841 * @param uVersion Data layout version.
842 */
843static void apicR3DumpState(PVMCPU pVCpu, const char *pszPrefix, uint32_t uVersion)
844{
845 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
846
847 LogRel(("APIC%u: %s (version %u):\n", pVCpu->idCpu, pszPrefix, uVersion));
848
849 switch (uVersion)
850 {
851 case APIC_SAVED_STATE_VERSION:
852 case APIC_SAVED_STATE_VERSION_VBOX_51_BETA2:
853 {
854 /* The auxiliary state. */
855 LogRel(("APIC%u: uApicBaseMsr = %#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
856 LogRel(("APIC%u: uEsrInternal = %#RX64\n", pVCpu->idCpu, pApicCpu->uEsrInternal));
857
858 /* The timer. */
859 LogRel(("APIC%u: u64TimerInitial = %#RU64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
860 LogRel(("APIC%u: uHintedTimerInitialCount = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerInitialCount));
861 LogRel(("APIC%u: uHintedTimerShift = %#RU64\n", pVCpu->idCpu, pApicCpu->uHintedTimerShift));
862
863 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
864 LogRel(("APIC%u: uTimerICR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
865 LogRel(("APIC%u: uTimerCCR = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
866
867 /* The PIBs. */
868 LogRel(("APIC%u: Edge PIB : %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), pApicCpu->pvApicPibR3));
869 LogRel(("APIC%u: Level PIB: %.*Rhxs\n", pVCpu->idCpu, sizeof(APICPIB), &pApicCpu->ApicPibLevel));
870
871 /* The LINT0, LINT1 interrupt line active states. */
872 LogRel(("APIC%u: fActiveLint0 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint0));
873 LogRel(("APIC%u: fActiveLint1 = %RTbool\n", pVCpu->idCpu, pApicCpu->fActiveLint1));
874
875 /* The APIC page. */
876 LogRel(("APIC%u: APIC page: %.*Rhxs\n", pVCpu->idCpu, sizeof(XAPICPAGE), pApicCpu->pvApicPageR3));
877 break;
878 }
879
880 case APIC_SAVED_STATE_VERSION_VBOX_50:
881 case APIC_SAVED_STATE_VERSION_VBOX_30:
882 case APIC_SAVED_STATE_VERSION_ANCIENT:
883 {
884 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
885 LogRel(("APIC%u: uApicBaseMsr = %#RX32\n", pVCpu->idCpu, RT_LO_U32(pApicCpu->uApicBaseMsr)));
886 LogRel(("APIC%u: uId = %#RX32\n", pVCpu->idCpu, pXApicPage->id.u8ApicId));
887 LogRel(("APIC%u: uPhysId = N/A\n", pVCpu->idCpu));
888 LogRel(("APIC%u: uArbId = N/A\n", pVCpu->idCpu));
889 LogRel(("APIC%u: uTpr = %#RX32\n", pVCpu->idCpu, pXApicPage->tpr.u8Tpr));
890 LogRel(("APIC%u: uSvr = %#RX32\n", pVCpu->idCpu, pXApicPage->svr.all.u32Svr));
891 LogRel(("APIC%u: uLdr = %#x\n", pVCpu->idCpu, pXApicPage->ldr.all.u32Ldr));
892 LogRel(("APIC%u: uDfr = %#x\n", pVCpu->idCpu, pXApicPage->dfr.all.u32Dfr));
893
894 for (size_t i = 0; i < 8; i++)
895 {
896 LogRel(("APIC%u: Isr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->isr.u[i].u32Reg));
897 LogRel(("APIC%u: Tmr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->tmr.u[i].u32Reg));
898 LogRel(("APIC%u: Irr[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, pXApicPage->irr.u[i].u32Reg));
899 }
900
901 for (size_t i = 0; i < XAPIC_MAX_LVT_ENTRIES_P4; i++)
902 {
903 uint16_t const offReg = XAPIC_OFF_LVT_START + (i << 4);
904 LogRel(("APIC%u: Lvt[%u].u32Reg = %#RX32\n", pVCpu->idCpu, i, apicR3ReadRawR32(pXApicPage, offReg)));
905 }
906
907 LogRel(("APIC%u: uEsr = %#RX32\n", pVCpu->idCpu, pXApicPage->esr.all.u32Errors));
908 LogRel(("APIC%u: uIcr_Lo = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_lo.all.u32IcrLo));
909 LogRel(("APIC%u: uIcr_Hi = %#RX32\n", pVCpu->idCpu, pXApicPage->icr_hi.all.u32IcrHi));
910 LogRel(("APIC%u: uTimerDcr = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_dcr.all.u32DivideValue));
911 LogRel(("APIC%u: uCountShift = %#RX32\n", pVCpu->idCpu, apicGetTimerShift(pXApicPage)));
912 LogRel(("APIC%u: uInitialCount = %#RX32\n", pVCpu->idCpu, pXApicPage->timer_icr.u32InitialCount));
913 LogRel(("APIC%u: u64InitialCountLoadTime = %#RX64\n", pVCpu->idCpu, pApicCpu->u64TimerInitial));
914 LogRel(("APIC%u: u64NextTime / TimerCCR = %#RX64\n", pVCpu->idCpu, pXApicPage->timer_ccr.u32CurrentCount));
915 break;
916 }
917
918 default:
919 {
920 LogRel(("APIC: apicR3DumpState: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
921 break;
922 }
923 }
924}
925#endif /* APIC_FUZZY_SSM_COMPAT_TEST */
926
927
928/**
929 * Worker for saving per-VM APIC data.
930 *
931 * @returns VBox status code.
932 * @param pVM The cross context VM structure.
933 * @param pSSM The SSM handle.
934 */
935static int apicR3SaveVMData(PVM pVM, PSSMHANDLE pSSM)
936{
937 PAPIC pApic = VM_TO_APIC(pVM);
938 SSMR3PutU32(pSSM, pVM->cCpus);
939 SSMR3PutBool(pSSM, pApic->fIoApicPresent);
940 return SSMR3PutU32(pSSM, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode));
941}
942
943
944/**
945 * Worker for loading per-VM APIC data.
946 *
947 * @returns VBox status code.
948 * @param pVM The cross context VM structure.
949 * @param pSSM The SSM handle.
950 */
951static int apicR3LoadVMData(PVM pVM, PSSMHANDLE pSSM)
952{
953 PAPIC pApic = VM_TO_APIC(pVM);
954
955 /* Load and verify number of CPUs. */
956 uint32_t cCpus;
957 int rc = SSMR3GetU32(pSSM, &cCpus);
958 AssertRCReturn(rc, rc);
959 if (cCpus != pVM->cCpus)
960 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
961
962 /* Load and verify I/O APIC presence. */
963 bool fIoApicPresent;
964 rc = SSMR3GetBool(pSSM, &fIoApicPresent);
965 AssertRCReturn(rc, rc);
966 if (fIoApicPresent != pApic->fIoApicPresent)
967 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApicPresent: saved=%RTbool config=%RTbool"),
968 fIoApicPresent, pApic->fIoApicPresent);
969
970 /* Load and verify configured APIC mode. */
971 uint32_t uLegacyApicMode;
972 rc = SSMR3GetU32(pSSM, &uLegacyApicMode);
973 AssertRCReturn(rc, rc);
974 APICMODE const enmApicMode = apicR3ConvertFromLegacyApicMode((PDMAPICMODE)uLegacyApicMode);
975 if (enmApicMode != pApic->enmOriginalMode)
976 return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicMode: saved=%u (%u) config=%u (%u)"),
977 uLegacyApicMode, enmApicMode, apicR3ConvertToLegacyApicMode(pApic->enmOriginalMode),
978 pApic->enmOriginalMode);
979 return VINF_SUCCESS;
980}
981
982
983/**
984 * Worker for loading per-VCPU APIC data for legacy (old) saved-states.
985 *
986 * @returns VBox status code.
987 * @param pVM The cross context VM structure.
988 * @param pVCpu The cross context virtual CPU structure.
989 * @param pSSM The SSM handle.
990 * @param uVersion Data layout version.
991 */
992static int apicR3LoadLegacyVCpuData(PVM pVM, PVMCPU pVCpu, PSSMHANDLE pSSM, uint32_t uVersion)
993{
994 AssertReturn(uVersion <= APIC_SAVED_STATE_VERSION_VBOX_50, VERR_NOT_SUPPORTED);
995
996 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
997 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
998
999 uint32_t uApicBaseLo;
1000 int rc = SSMR3GetU32(pSSM, &uApicBaseLo);
1001 AssertRCReturn(rc, rc);
1002 pApicCpu->uApicBaseMsr = uApicBaseLo;
1003 Log2(("APIC%u: apicR3LoadLegacyVCpuData: uApicBaseMsr=%#RX64\n", pVCpu->idCpu, pApicCpu->uApicBaseMsr));
1004
1005 switch (uVersion)
1006 {
1007 case APIC_SAVED_STATE_VERSION_VBOX_50:
1008 case APIC_SAVED_STATE_VERSION_VBOX_30:
1009 {
1010 uint32_t uApicId, uPhysApicId, uArbId;
1011 SSMR3GetU32(pSSM, &uApicId); pXApicPage->id.u8ApicId = uApicId;
1012 SSMR3GetU32(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
1013 SSMR3GetU32(pSSM, &uArbId); NOREF(uArbId); /* ArbID is & was unused. */
1014 break;
1015 }
1016
1017 case APIC_SAVED_STATE_VERSION_ANCIENT:
1018 {
1019 uint8_t uPhysApicId;
1020 SSMR3GetU8(pSSM, &pXApicPage->id.u8ApicId);
1021 SSMR3GetU8(pSSM, &uPhysApicId); NOREF(uPhysApicId); /* PhysId == pVCpu->idCpu */
1022 break;
1023 }
1024
1025 default:
1026 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1027 }
1028
1029 uint32_t u32Tpr;
1030 SSMR3GetU32(pSSM, &u32Tpr);
1031 pXApicPage->tpr.u8Tpr = u32Tpr & XAPIC_TPR_VALID;
1032
1033 SSMR3GetU32(pSSM, &pXApicPage->svr.all.u32Svr);
1034 SSMR3GetU8(pSSM, &pXApicPage->ldr.u.u8LogicalApicId);
1035
1036 uint8_t uDfr;
1037 SSMR3GetU8(pSSM, &uDfr);
1038 pXApicPage->dfr.u.u4Model = uDfr >> 4;
1039
1040 AssertCompile(RT_ELEMENTS(pXApicPage->isr.u) == 8);
1041 AssertCompile(RT_ELEMENTS(pXApicPage->tmr.u) == 8);
1042 AssertCompile(RT_ELEMENTS(pXApicPage->irr.u) == 8);
1043 for (size_t i = 0; i < 8; i++)
1044 {
1045 SSMR3GetU32(pSSM, &pXApicPage->isr.u[i].u32Reg);
1046 SSMR3GetU32(pSSM, &pXApicPage->tmr.u[i].u32Reg);
1047 SSMR3GetU32(pSSM, &pXApicPage->irr.u[i].u32Reg);
1048 }
1049
1050 SSMR3GetU32(pSSM, &pXApicPage->lvt_timer.all.u32LvtTimer);
1051 SSMR3GetU32(pSSM, &pXApicPage->lvt_thermal.all.u32LvtThermal);
1052 SSMR3GetU32(pSSM, &pXApicPage->lvt_perf.all.u32LvtPerf);
1053 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint0.all.u32LvtLint0);
1054 SSMR3GetU32(pSSM, &pXApicPage->lvt_lint1.all.u32LvtLint1);
1055 SSMR3GetU32(pSSM, &pXApicPage->lvt_error.all.u32LvtError);
1056
1057 SSMR3GetU32(pSSM, &pXApicPage->esr.all.u32Errors);
1058 SSMR3GetU32(pSSM, &pXApicPage->icr_lo.all.u32IcrLo);
1059 SSMR3GetU32(pSSM, &pXApicPage->icr_hi.all.u32IcrHi);
1060
1061 uint32_t u32TimerShift;
1062 SSMR3GetU32(pSSM, &pXApicPage->timer_dcr.all.u32DivideValue);
1063 SSMR3GetU32(pSSM, &u32TimerShift);
1064 /*
1065 * Old implementation may have left the timer shift uninitialized until
1066 * the timer configuration register was written. Unfortunately zero is
1067 * also a valid timer shift value, so we're just going to ignore it
1068 * completely. The shift count can always be derived from the DCR.
1069 * See @bugref{8245#c98}.
1070 */
1071 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1072
1073 SSMR3GetU32(pSSM, &pXApicPage->timer_icr.u32InitialCount);
1074 SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial);
1075 uint64_t uNextTS;
1076 rc = SSMR3GetU64(pSSM, &uNextTS); AssertRCReturn(rc, rc);
1077 if (uNextTS >= pApicCpu->u64TimerInitial + ((pXApicPage->timer_icr.u32InitialCount + 1) << uTimerShift))
1078 pXApicPage->timer_ccr.u32CurrentCount = pXApicPage->timer_icr.u32InitialCount;
1079
1080 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM);
1081 AssertRCReturn(rc, rc);
1082 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1083 Assert(pApicCpu->uHintedTimerShift == 0);
1084 if (TMTimerIsActive(pApicCpu->pTimerR3))
1085 {
1086 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1087 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1088 }
1089
1090 return rc;
1091}
1092
1093
1094/**
1095 * @copydoc FNSSMDEVLIVEEXEC
1096 */
1097static DECLCALLBACK(int) apicR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
1098{
1099 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1100 PVM pVM = PDMDevHlpGetVM(pApicDev->pDevInsR3);
1101
1102 LogFlow(("APIC: apicR3LiveExec: uPass=%u\n", uPass));
1103
1104 int rc = apicR3SaveVMData(pVM, pSSM);
1105 AssertRCReturn(rc, rc);
1106 return VINF_SSM_DONT_CALL_AGAIN;
1107}
1108
1109
1110/**
1111 * @copydoc FNSSMDEVSAVEEXEC
1112 */
1113static DECLCALLBACK(int) apicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
1114{
1115 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1116 PVM pVM = PDMDevHlpGetVM(pDevIns);
1117 PAPIC pApic = VM_TO_APIC(pVM);
1118 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1119
1120 LogFlow(("APIC: apicR3SaveExec\n"));
1121
1122 /* Save per-VM data. */
1123 int rc = apicR3SaveVMData(pVM, pSSM);
1124 AssertRCReturn(rc, rc);
1125
1126 /* Save per-VCPU data.*/
1127 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1128 {
1129 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1130 PCAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1131
1132 /* Update interrupts from the pending-interrupts bitmaps to the IRR. */
1133 APICUpdatePendingInterrupts(pVCpu);
1134
1135 /* Save the auxiliary data. */
1136 SSMR3PutU64(pSSM, pApicCpu->uApicBaseMsr);
1137 SSMR3PutU32(pSSM, pApicCpu->uEsrInternal);
1138
1139 /* Save the APIC page. */
1140 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1141 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1142 else
1143 SSMR3PutStruct(pSSM, (const void *)pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1144
1145 /* Save the timer. */
1146 SSMR3PutU64(pSSM, pApicCpu->u64TimerInitial);
1147 TMR3TimerSave(pApicCpu->pTimerR3, pSSM);
1148
1149 /* Save the LINT0, LINT1 interrupt line states. */
1150 SSMR3PutBool(pSSM, pApicCpu->fActiveLint0);
1151 SSMR3PutBool(pSSM, pApicCpu->fActiveLint1);
1152
1153#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1154 apicR3DumpState(pVCpu, "Saved state", APIC_SAVED_STATE_VERSION);
1155#endif
1156 }
1157
1158#ifdef APIC_FUZZY_SSM_COMPAT_TEST
1159 /* The state is fuzzy, don't even bother trying to load the guest. */
1160 return VERR_INVALID_STATE;
1161#else
1162 return rc;
1163#endif
1164}
1165
1166
1167/**
1168 * @copydoc FNSSMDEVLOADEXEC
1169 */
1170static DECLCALLBACK(int) apicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1171{
1172 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1173 PVM pVM = PDMDevHlpGetVM(pDevIns);
1174 PAPIC pApic = VM_TO_APIC(pVM);
1175
1176 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
1177 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
1178
1179 LogFlow(("APIC: apicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
1180
1181 /* Weed out invalid versions. */
1182 if ( uVersion != APIC_SAVED_STATE_VERSION
1183 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_51_BETA2
1184 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_50
1185 && uVersion != APIC_SAVED_STATE_VERSION_VBOX_30
1186 && uVersion != APIC_SAVED_STATE_VERSION_ANCIENT)
1187 {
1188 LogRel(("APIC: apicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
1189 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1190 }
1191
1192 int rc = VINF_SUCCESS;
1193 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30)
1194 {
1195 rc = apicR3LoadVMData(pVM, pSSM);
1196 AssertRCReturn(rc, rc);
1197
1198 if (uVersion == APIC_SAVED_STATE_VERSION)
1199 { /* Load any new additional per-VM data. */ }
1200 }
1201
1202 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1203 {
1204 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1205 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1206
1207 if ( uVersion == APIC_SAVED_STATE_VERSION
1208 || uVersion == APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
1209 {
1210 /* Load the auxiliary data. */
1211 SSMR3GetU64(pSSM, (uint64_t *)&pApicCpu->uApicBaseMsr);
1212 SSMR3GetU32(pSSM, &pApicCpu->uEsrInternal);
1213
1214 /* Load the APIC page. */
1215 if (XAPIC_IN_X2APIC_MODE(pVCpu))
1216 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aX2ApicPageFields[0]);
1217 else
1218 SSMR3GetStruct(pSSM, pApicCpu->pvApicPageR3, &g_aXApicPageFields[0]);
1219
1220 /* Load the timer. */
1221 rc = SSMR3GetU64(pSSM, &pApicCpu->u64TimerInitial); AssertRCReturn(rc, rc);
1222 rc = TMR3TimerLoad(pApicCpu->pTimerR3, pSSM); AssertRCReturn(rc, rc);
1223 Assert(pApicCpu->uHintedTimerShift == 0);
1224 Assert(pApicCpu->uHintedTimerInitialCount == 0);
1225 if (TMTimerIsActive(pApicCpu->pTimerR3))
1226 {
1227 PCXAPICPAGE pXApicPage = VMCPU_TO_CXAPICPAGE(pVCpu);
1228 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1229 uint8_t const uTimerShift = apicGetTimerShift(pXApicPage);
1230 apicHintTimerFreq(pApicCpu, uInitialCount, uTimerShift);
1231 }
1232
1233 /* Load the LINT0, LINT1 interrupt line states. */
1234 if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_51_BETA2)
1235 {
1236 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint0);
1237 SSMR3GetBool(pSSM, (bool *)&pApicCpu->fActiveLint1);
1238 }
1239 }
1240 else
1241 {
1242 rc = apicR3LoadLegacyVCpuData(pVM, pVCpu, pSSM, uVersion);
1243 AssertRCReturn(rc, rc);
1244 }
1245
1246#if defined(APIC_FUZZY_SSM_COMPAT_TEST) || defined(DEBUG_ramshankar)
1247 apicR3DumpState(pVCpu, "Loaded state", uVersion);
1248#endif
1249 }
1250
1251 return rc;
1252}
1253
1254
1255/**
1256 * The timer callback.
1257 *
1258 * @param pDevIns The device instance.
1259 * @param pTimer The timer handle.
1260 * @param pvUser Opaque pointer to the VMCPU.
1261 *
1262 * @thread Any.
1263 * @remarks Currently this function is invoked on the last EMT, see @c
1264 * idTimerCpu in tmR3TimerCallback(). However, the code does -not-
1265 * rely on this and is designed to work with being invoked on any
1266 * thread.
1267 */
1268static DECLCALLBACK(void) apicR3TimerCallback(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
1269{
1270 PVMCPU pVCpu = (PVMCPU)pvUser;
1271 Assert(TMTimerIsLockOwner(pTimer));
1272 Assert(pVCpu);
1273 LogFlow(("APIC%u: apicR3TimerCallback\n", pVCpu->idCpu));
1274
1275 PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
1276 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1277 uint32_t const uLvtTimer = pXApicPage->lvt_timer.all.u32LvtTimer;
1278 STAM_COUNTER_INC(&pApicCpu->StatTimerCallback);
1279 if (!XAPIC_LVT_IS_MASKED(uLvtTimer))
1280 {
1281 uint8_t uVector = XAPIC_LVT_GET_VECTOR(uLvtTimer);
1282 Log2(("APIC%u: apicR3TimerCallback: Raising timer interrupt. uVector=%#x\n", pVCpu->idCpu, uVector));
1283 APICPostInterrupt(pVCpu, uVector, XAPICTRIGGERMODE_EDGE);
1284 }
1285
1286 XAPICTIMERMODE enmTimerMode = XAPIC_LVT_GET_TIMER_MODE(uLvtTimer);
1287 switch (enmTimerMode)
1288 {
1289 case XAPICTIMERMODE_PERIODIC:
1290 {
1291 /* The initial-count register determines if the periodic timer is re-armed. */
1292 uint32_t const uInitialCount = pXApicPage->timer_icr.u32InitialCount;
1293 pXApicPage->timer_ccr.u32CurrentCount = uInitialCount;
1294 if (uInitialCount)
1295 {
1296 Log2(("APIC%u: apicR3TimerCallback: Re-arming timer. uInitialCount=%#RX32\n", pVCpu->idCpu, uInitialCount));
1297 APICStartTimer(pVCpu, uInitialCount);
1298 }
1299 break;
1300 }
1301
1302 case XAPICTIMERMODE_ONESHOT:
1303 {
1304 pXApicPage->timer_ccr.u32CurrentCount = 0;
1305 break;
1306 }
1307
1308 case XAPICTIMERMODE_TSC_DEADLINE:
1309 {
1310 /** @todo implement TSC deadline. */
1311 AssertMsgFailed(("APIC: TSC deadline mode unimplemented\n"));
1312 break;
1313 }
1314 }
1315}
1316
1317
1318/**
1319 * @interface_method_impl{PDMDEVREG,pfnReset}
1320 */
1321static DECLCALLBACK(void) apicR3Reset(PPDMDEVINS pDevIns)
1322{
1323 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1324 PVM pVM = PDMDevHlpGetVM(pDevIns);
1325 VM_ASSERT_EMT0(pVM);
1326 VM_ASSERT_IS_NOT_RUNNING(pVM);
1327
1328 LogFlow(("APIC: apicR3Reset\n"));
1329
1330 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1331 {
1332 PVMCPU pVCpuDest = &pVM->aCpus[idCpu];
1333 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpuDest);
1334
1335 if (TMTimerIsActive(pApicCpu->pTimerR3))
1336 TMTimerStop(pApicCpu->pTimerR3);
1337
1338 APICR3Reset(pVCpuDest, true /* fResetApicBaseMsr */);
1339
1340 /* Clear the interrupt pending force flag. */
1341 APICClearInterruptFF(pVCpuDest, PDMAPICIRQ_HARDWARE);
1342 }
1343}
1344
1345
1346/**
1347 * @interface_method_impl{PDMDEVREG,pfnRelocate}
1348 */
1349static DECLCALLBACK(void) apicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
1350{
1351 PVM pVM = PDMDevHlpGetVM(pDevIns);
1352 PAPIC pApic = VM_TO_APIC(pVM);
1353 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1354
1355 LogFlow(("APIC: apicR3Relocate: pVM=%p pDevIns=%p offDelta=%RGi\n", pVM, pDevIns, offDelta));
1356
1357 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1358 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1359 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1360
1361 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1362 pApic->pvApicPibRC += offDelta;
1363
1364 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1365 {
1366 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1367 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1368 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1369
1370 pApicCpu->pvApicPageRC += offDelta;
1371 pApicCpu->pvApicPibRC += offDelta;
1372 Log2(("APIC%u: apicR3Relocate: APIC PIB at %RGv\n", pVCpu->idCpu, pApicCpu->pvApicPibRC));
1373 }
1374}
1375
1376
1377/**
1378 * Terminates the APIC state.
1379 *
1380 * @param pVM The cross context VM structure.
1381 */
1382static void apicR3TermState(PVM pVM)
1383{
1384 PAPIC pApic = VM_TO_APIC(pVM);
1385 LogFlow(("APIC: apicR3TermState: pVM=%p\n", pVM));
1386
1387 /* Unmap and free the PIB. */
1388 if (pApic->pvApicPibR3 != NIL_RTR3PTR)
1389 {
1390 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1391 if (cPages == 1)
1392 SUPR3PageFreeEx(pApic->pvApicPibR3, cPages);
1393 else
1394 SUPR3ContFree(pApic->pvApicPibR3, cPages);
1395 pApic->pvApicPibR3 = NIL_RTR3PTR;
1396 pApic->pvApicPibR0 = NIL_RTR0PTR;
1397 pApic->pvApicPibRC = NIL_RTRCPTR;
1398 }
1399
1400 /* Unmap and free the virtual-APIC pages. */
1401 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1402 {
1403 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1404 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1405
1406 pApicCpu->pvApicPibR3 = NIL_RTR3PTR;
1407 pApicCpu->pvApicPibR0 = NIL_RTR0PTR;
1408 pApicCpu->pvApicPibRC = NIL_RTRCPTR;
1409
1410 if (pApicCpu->pvApicPageR3 != NIL_RTR3PTR)
1411 {
1412 SUPR3PageFreeEx(pApicCpu->pvApicPageR3, 1 /* cPages */);
1413 pApicCpu->pvApicPageR3 = NIL_RTR3PTR;
1414 pApicCpu->pvApicPageR0 = NIL_RTR0PTR;
1415 pApicCpu->pvApicPageRC = NIL_RTRCPTR;
1416 }
1417 }
1418}
1419
1420
1421/**
1422 * Initializes the APIC state.
1423 *
1424 * @returns VBox status code.
1425 * @param pVM The cross context VM structure.
1426 */
1427static int apicR3InitState(PVM pVM)
1428{
1429 PAPIC pApic = VM_TO_APIC(pVM);
1430 LogFlow(("APIC: apicR3InitState: pVM=%p\n", pVM));
1431
1432 /* With hardware virtualization, we don't need to map the APIC in GC. */
1433 bool const fNeedsGCMapping = !HMIsEnabled(pVM);
1434
1435 /*
1436 * Allocate and map the pending-interrupt bitmap (PIB).
1437 *
1438 * We allocate all the VCPUs' PIBs contiguously in order to save space as
1439 * physically contiguous allocations are rounded to a multiple of page size.
1440 */
1441 Assert(pApic->pvApicPibR3 == NIL_RTR3PTR);
1442 Assert(pApic->pvApicPibR0 == NIL_RTR0PTR);
1443 Assert(pApic->pvApicPibRC == NIL_RTRCPTR);
1444 pApic->cbApicPib = RT_ALIGN_Z(pVM->cCpus * sizeof(APICPIB), PAGE_SIZE);
1445 size_t const cPages = pApic->cbApicPib >> PAGE_SHIFT;
1446 if (cPages == 1)
1447 {
1448 SUPPAGE SupApicPib;
1449 RT_ZERO(SupApicPib);
1450 SupApicPib.Phys = NIL_RTHCPHYS;
1451 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApic->pvApicPibR3, &pApic->pvApicPibR0, &SupApicPib);
1452 if (RT_SUCCESS(rc))
1453 {
1454 pApic->HCPhysApicPib = SupApicPib.Phys;
1455 AssertLogRelReturn(pApic->pvApicPibR3, VERR_INTERNAL_ERROR);
1456 }
1457 else
1458 {
1459 LogRel(("APIC: Failed to allocate %u bytes for the pending-interrupt bitmap, rc=%Rrc\n", pApic->cbApicPib, rc));
1460 return rc;
1461 }
1462 }
1463 else
1464 pApic->pvApicPibR3 = SUPR3ContAlloc(cPages, &pApic->pvApicPibR0, &pApic->HCPhysApicPib);
1465
1466 if (pApic->pvApicPibR3)
1467 {
1468 AssertLogRelReturn(pApic->pvApicPibR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
1469 AssertLogRelReturn(pApic->HCPhysApicPib != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1470
1471 /* Initialize the PIB. */
1472 RT_BZERO(pApic->pvApicPibR3, pApic->cbApicPib);
1473
1474 /* Map the PIB into GC. */
1475 if (fNeedsGCMapping)
1476 {
1477 pApic->pvApicPibRC = NIL_RTRCPTR;
1478 int rc = MMR3HyperMapHCPhys(pVM, pApic->pvApicPibR3, NIL_RTR0PTR, pApic->HCPhysApicPib, pApic->cbApicPib,
1479 "APIC PIB", (PRTGCPTR)&pApic->pvApicPibRC);
1480 if (RT_FAILURE(rc))
1481 {
1482 LogRel(("APIC: Failed to map %u bytes for the pending-interrupt bitmap into GC, rc=%Rrc\n", pApic->cbApicPib,
1483 rc));
1484 apicR3TermState(pVM);
1485 return rc;
1486 }
1487
1488 AssertLogRelReturn(pApic->pvApicPibRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1489 }
1490
1491 /*
1492 * Allocate the map the virtual-APIC pages.
1493 */
1494 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1495 {
1496 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1497 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1498
1499 SUPPAGE SupApicPage;
1500 RT_ZERO(SupApicPage);
1501 SupApicPage.Phys = NIL_RTHCPHYS;
1502
1503 Assert(pVCpu->idCpu == idCpu);
1504 Assert(pApicCpu->pvApicPageR3 == NIL_RTR0PTR);
1505 Assert(pApicCpu->pvApicPageR0 == NIL_RTR0PTR);
1506 Assert(pApicCpu->pvApicPageRC == NIL_RTRCPTR);
1507 AssertCompile(sizeof(XAPICPAGE) == PAGE_SIZE);
1508 pApicCpu->cbApicPage = sizeof(XAPICPAGE);
1509 int rc = SUPR3PageAllocEx(1 /* cPages */, 0 /* fFlags */, &pApicCpu->pvApicPageR3, &pApicCpu->pvApicPageR0,
1510 &SupApicPage);
1511 if (RT_SUCCESS(rc))
1512 {
1513 AssertLogRelReturn(pApicCpu->pvApicPageR3 != NIL_RTR3PTR, VERR_INTERNAL_ERROR);
1514 AssertLogRelReturn(pApicCpu->HCPhysApicPage != NIL_RTHCPHYS, VERR_INTERNAL_ERROR);
1515 pApicCpu->HCPhysApicPage = SupApicPage.Phys;
1516
1517 /* Map the virtual-APIC page into GC. */
1518 if (fNeedsGCMapping)
1519 {
1520 rc = MMR3HyperMapHCPhys(pVM, pApicCpu->pvApicPageR3, NIL_RTR0PTR, pApicCpu->HCPhysApicPage,
1521 pApicCpu->cbApicPage, "APIC", (PRTGCPTR)&pApicCpu->pvApicPageRC);
1522 if (RT_FAILURE(rc))
1523 {
1524 LogRel(("APIC%u: Failed to map %u bytes for the virtual-APIC page into GC, rc=%Rrc", idCpu,
1525 pApicCpu->cbApicPage, rc));
1526 apicR3TermState(pVM);
1527 return rc;
1528 }
1529
1530 AssertLogRelReturn(pApicCpu->pvApicPageRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
1531 }
1532
1533 /* Associate the per-VCPU PIB pointers to the per-VM PIB mapping. */
1534 uint32_t const offApicPib = idCpu * sizeof(APICPIB);
1535 pApicCpu->pvApicPibR0 = (RTR0PTR)((RTR0UINTPTR)pApic->pvApicPibR0 + offApicPib);
1536 pApicCpu->pvApicPibR3 = (RTR3PTR)((RTR3UINTPTR)pApic->pvApicPibR3 + offApicPib);
1537 if (fNeedsGCMapping)
1538 pApicCpu->pvApicPibRC = (RTRCPTR)((RTRCUINTPTR)pApic->pvApicPibRC + offApicPib);
1539
1540 /* Initialize the virtual-APIC state. */
1541 RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
1542 APICR3Reset(pVCpu, true /* fResetApicBaseMsr */);
1543
1544#ifdef DEBUG_ramshankar
1545 Assert(pApicCpu->pvApicPibR3 != NIL_RTR3PTR);
1546 Assert(pApicCpu->pvApicPibR0 != NIL_RTR0PTR);
1547 Assert(!fNeedsGCMapping || pApicCpu->pvApicPibRC != NIL_RTRCPTR);
1548 Assert(pApicCpu->pvApicPageR3 != NIL_RTR3PTR);
1549 Assert(pApicCpu->pvApicPageR0 != NIL_RTR0PTR);
1550 Assert(!fNeedsGCMapping || pApicCpu->pvApicPageRC != NIL_RTRCPTR);
1551 Assert(!fNeedsGCMapping || pApic->pvApicPibRC == pVM->aCpus[0].apic.s.pvApicPibRC);
1552#endif
1553 }
1554 else
1555 {
1556 LogRel(("APIC%u: Failed to allocate %u bytes for the virtual-APIC page, rc=%Rrc\n", idCpu, pApicCpu->cbApicPage, rc));
1557 apicR3TermState(pVM);
1558 return rc;
1559 }
1560 }
1561
1562#ifdef DEBUG_ramshankar
1563 Assert(pApic->pvApicPibR3 != NIL_RTR3PTR);
1564 Assert(pApic->pvApicPibR0 != NIL_RTR0PTR);
1565 Assert(!fNeedsGCMapping || pApic->pvApicPibRC != NIL_RTRCPTR);
1566#endif
1567 return VINF_SUCCESS;
1568 }
1569
1570 LogRel(("APIC: Failed to allocate %u bytes of physically contiguous memory for the pending-interrupt bitmap\n",
1571 pApic->cbApicPib));
1572 return VERR_NO_MEMORY;
1573}
1574
1575
1576/**
1577 * @interface_method_impl{PDMDEVREG,pfnDestruct}
1578 */
1579static DECLCALLBACK(int) apicR3Destruct(PPDMDEVINS pDevIns)
1580{
1581 PVM pVM = PDMDevHlpGetVM(pDevIns);
1582 LogFlow(("APIC: apicR3Destruct: pVM=%p\n", pVM));
1583
1584 apicR3TermState(pVM);
1585 return VINF_SUCCESS;
1586}
1587
1588
1589/**
1590 * @interface_method_impl{PDMDEVREG,pfnInitComplete}
1591 */
1592static DECLCALLBACK(int) apicR3InitComplete(PPDMDEVINS pDevIns)
1593{
1594 PVM pVM = PDMDevHlpGetVM(pDevIns);
1595 PAPIC pApic = VM_TO_APIC(pVM);
1596
1597 /*
1598 * Init APIC settings that rely on HM and CPUM configurations.
1599 */
1600 CPUMCPUIDLEAF CpuLeaf;
1601 int rc = CPUMR3CpuIdGetLeaf(pVM, &CpuLeaf, 1, 0);
1602 AssertRCReturn(rc, rc);
1603
1604 pApic->fSupportsTscDeadline = RT_BOOL(CpuLeaf.uEcx & X86_CPUID_FEATURE_ECX_TSCDEADL);
1605 pApic->fPostedIntrsEnabled = HMR3IsPostedIntrsEnabled(pVM->pUVM);
1606 pApic->fVirtApicRegsEnabled = HMR3IsVirtApicRegsEnabled(pVM->pUVM);
1607
1608 LogRel(("APIC: fPostedIntrsEnabled=%RTbool fVirtApicRegsEnabled=%RTbool fSupportsTscDeadline=%RTbool\n",
1609 pApic->fPostedIntrsEnabled, pApic->fVirtApicRegsEnabled, pApic->fSupportsTscDeadline));
1610
1611 return VINF_SUCCESS;
1612}
1613
1614
1615/**
1616 * @interface_method_impl{PDMDEVREG,pfnConstruct}
1617 */
1618static DECLCALLBACK(int) apicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
1619{
1620 /*
1621 * Validate inputs.
1622 */
1623 Assert(iInstance == 0);
1624 Assert(pDevIns);
1625
1626 PAPICDEV pApicDev = PDMINS_2_DATA(pDevIns, PAPICDEV);
1627 PVM pVM = PDMDevHlpGetVM(pDevIns);
1628 PAPIC pApic = VM_TO_APIC(pVM);
1629
1630 /*
1631 * Validate APIC settings.
1632 */
1633 if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
1634 "Mode\0"
1635 "IOAPIC\0"
1636 "NumCPUs\0"))
1637 {
1638 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
1639 N_("APIC configuration error: unknown option specified"));
1640 }
1641
1642 int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pApic->fRZEnabled, true);
1643 AssertLogRelRCReturn(rc, rc);
1644
1645 rc = CFGMR3QueryBoolDef(pCfg, "IOAPIC", &pApic->fIoApicPresent, true);
1646 AssertLogRelRCReturn(rc, rc);
1647
1648 uint8_t uOriginalMode;
1649 rc = CFGMR3QueryU8Def(pCfg, "Mode", &uOriginalMode, APICMODE_XAPIC);
1650 AssertLogRelRCReturn(rc, rc);
1651
1652 /* Validate APIC modes. */
1653 APICMODE const enmOriginalMode = (APICMODE)uOriginalMode;
1654 switch (enmOriginalMode)
1655 {
1656 case APICMODE_DISABLED:
1657 {
1658 /** @todo permanently disabling the APIC won't really work (needs
1659 * fixing in HM, CPUM, PDM and possibly other places). See
1660 * @bugref{8353}. */
1661#if 0
1662 pApic->enmOriginalMode = enmOriginalMode;
1663 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_APIC);
1664 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
1665 break;
1666#else
1667 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode 'disabled' is not supported yet.");
1668#endif
1669 }
1670
1671 case APICMODE_X2APIC:
1672 {
1673 pApic->enmOriginalMode = enmOriginalMode;
1674 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_X2APIC);
1675
1676 /* Insert the MSR range of the x2APIC. */
1677 rc = CPUMR3MsrRangesInsert(pVM, &g_MsrRange_x2Apic);
1678 AssertLogRelRCReturn(rc, rc);
1679 break;
1680 }
1681
1682 case APICMODE_XAPIC:
1683 pApic->enmOriginalMode = enmOriginalMode;
1684 /* The CPUID bit will be updated in apicR3ResetBaseMsr(). */
1685 break;
1686
1687 default:
1688 return VMR3SetError(pVM->pUVM, VERR_INVALID_PARAMETER, RT_SRC_POS, "APIC mode %#x unknown.", uOriginalMode);
1689 }
1690
1691 /*
1692 * Initialize the APIC state.
1693 */
1694 pApicDev->pDevInsR3 = pDevIns;
1695 pApicDev->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1696 pApicDev->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1697
1698 pApic->pApicDevR0 = PDMINS_2_DATA_R0PTR(pDevIns);
1699 pApic->pApicDevR3 = (PAPICDEV)PDMINS_2_DATA_R3PTR(pDevIns);
1700 pApic->pApicDevRC = PDMINS_2_DATA_RCPTR(pDevIns);
1701
1702 rc = apicR3InitState(pVM);
1703 AssertRCReturn(rc, rc);
1704
1705 /*
1706 * Disable automatic PDM locking for this device.
1707 */
1708 rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
1709 AssertRCReturn(rc, rc);
1710
1711 /*
1712 * Register the APIC.
1713 */
1714 PDMAPICREG ApicReg;
1715 RT_ZERO(ApicReg);
1716 ApicReg.u32Version = PDM_APICREG_VERSION;
1717 ApicReg.pfnGetInterruptR3 = APICGetInterrupt;
1718 ApicReg.pfnSetBaseMsrR3 = APICSetBaseMsr;
1719 ApicReg.pfnGetBaseMsrR3 = APICGetBaseMsr;
1720 ApicReg.pfnSetTprR3 = APICSetTpr;
1721 ApicReg.pfnGetTprR3 = APICGetTpr;
1722 ApicReg.pfnWriteMsrR3 = APICWriteMsr;
1723 ApicReg.pfnReadMsrR3 = APICReadMsr;
1724 ApicReg.pfnBusDeliverR3 = APICBusDeliver;
1725 ApicReg.pfnLocalInterruptR3 = APICLocalInterrupt;
1726 ApicReg.pfnGetTimerFreqR3 = APICGetTimerFreq;
1727
1728 /*
1729 * We always require R0 functionality (e.g. APICGetTpr() called by HMR0 VT-x/AMD-V code).
1730 * Hence, 'fRZEnabled' strictly only applies to MMIO and MSR read/write handlers returning
1731 * to ring-3. We still need other handlers like APICGetTpr() in ring-0 for now.
1732 */
1733 {
1734 ApicReg.pszGetInterruptRC = "APICGetInterrupt";
1735 ApicReg.pszSetBaseMsrRC = "APICSetBaseMsr";
1736 ApicReg.pszGetBaseMsrRC = "APICGetBaseMsr";
1737 ApicReg.pszSetTprRC = "APICSetTpr";
1738 ApicReg.pszGetTprRC = "APICGetTpr";
1739 ApicReg.pszWriteMsrRC = "APICWriteMsr";
1740 ApicReg.pszReadMsrRC = "APICReadMsr";
1741 ApicReg.pszBusDeliverRC = "APICBusDeliver";
1742 ApicReg.pszLocalInterruptRC = "APICLocalInterrupt";
1743 ApicReg.pszGetTimerFreqRC = "APICGetTimerFreq";
1744
1745 ApicReg.pszGetInterruptR0 = "APICGetInterrupt";
1746 ApicReg.pszSetBaseMsrR0 = "APICSetBaseMsr";
1747 ApicReg.pszGetBaseMsrR0 = "APICGetBaseMsr";
1748 ApicReg.pszSetTprR0 = "APICSetTpr";
1749 ApicReg.pszGetTprR0 = "APICGetTpr";
1750 ApicReg.pszWriteMsrR0 = "APICWriteMsr";
1751 ApicReg.pszReadMsrR0 = "APICReadMsr";
1752 ApicReg.pszBusDeliverR0 = "APICBusDeliver";
1753 ApicReg.pszLocalInterruptR0 = "APICLocalInterrupt";
1754 ApicReg.pszGetTimerFreqR0 = "APICGetTimerFreq";
1755 }
1756
1757 rc = PDMDevHlpAPICRegister(pDevIns, &ApicReg, &pApicDev->pApicHlpR3);
1758 AssertLogRelRCReturn(rc, rc);
1759 pApicDev->pCritSectR3 = pApicDev->pApicHlpR3->pfnGetR3CritSect(pDevIns);
1760
1761 /*
1762 * Register the MMIO range.
1763 */
1764 PAPICCPU pApicCpu0 = VMCPU_TO_APICCPU(&pVM->aCpus[0]);
1765 RTGCPHYS GCPhysApicBase = MSR_IA32_APICBASE_GET_ADDR(pApicCpu0->uApicBaseMsr);
1766
1767 rc = PDMDevHlpMMIORegister(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NULL /* pvUser */,
1768 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED,
1769 APICWriteMmio, APICReadMmio, "APIC");
1770 if (RT_FAILURE(rc))
1771 return rc;
1772
1773 if (pApic->fRZEnabled)
1774 {
1775 pApicDev->pApicHlpRC = pApicDev->pApicHlpR3->pfnGetRCHelpers(pDevIns);
1776 pApicDev->pCritSectRC = pApicDev->pApicHlpR3->pfnGetRCCritSect(pDevIns);
1777 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTRCPTR /*pvUser*/,
1778 "APICWriteMmio", "APICReadMmio");
1779 if (RT_FAILURE(rc))
1780 return rc;
1781
1782 pApicDev->pApicHlpR0 = pApicDev->pApicHlpR3->pfnGetR0Helpers(pDevIns);
1783 pApicDev->pCritSectR0 = pApicDev->pApicHlpR3->pfnGetR0CritSect(pDevIns);
1784 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), NIL_RTR0PTR /*pvUser*/,
1785 "APICWriteMmio", "APICReadMmio");
1786 if (RT_FAILURE(rc))
1787 return rc;
1788 }
1789
1790 /*
1791 * Create the APIC timers.
1792 */
1793 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1794 {
1795 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1796 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1797 RTStrPrintf(&pApicCpu->szTimerDesc[0], sizeof(pApicCpu->szTimerDesc), "APIC Timer %u", pVCpu->idCpu);
1798 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, apicR3TimerCallback, pVCpu, TMTIMER_FLAGS_NO_CRIT_SECT,
1799 pApicCpu->szTimerDesc, &pApicCpu->pTimerR3);
1800 if (RT_SUCCESS(rc))
1801 {
1802 pApicCpu->pTimerR0 = TMTimerR0Ptr(pApicCpu->pTimerR3);
1803 pApicCpu->pTimerRC = TMTimerRCPtr(pApicCpu->pTimerR3);
1804 }
1805 else
1806 return rc;
1807 }
1808
1809 /*
1810 * Register saved state callbacks.
1811 */
1812 rc = PDMDevHlpSSMRegister3(pDevIns, APIC_SAVED_STATE_VERSION, sizeof(*pApicDev), NULL /*pfnLiveExec*/, apicR3SaveExec,
1813 apicR3LoadExec);
1814 if (RT_FAILURE(rc))
1815 return rc;
1816
1817 /*
1818 * Register debugger info callbacks.
1819 *
1820 * We use separate callbacks rather than arguments so they can also be
1821 * dumped in an automated fashion while collecting crash diagnostics and
1822 * not just used during live debugging via the VM debugger.
1823 */
1824 rc = DBGFR3InfoRegisterInternalEx(pVM, "apic", "Dumps APIC basic information.", apicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
1825 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apiclvt", "Dumps APIC LVT information.", apicR3InfoLvt, DBGFINFO_FLAGS_ALL_EMTS);
1826 rc |= DBGFR3InfoRegisterInternalEx(pVM, "apictimer", "Dumps APIC timer information.", apicR3InfoTimer, DBGFINFO_FLAGS_ALL_EMTS);
1827 AssertRCReturn(rc, rc);
1828
1829#ifdef VBOX_WITH_STATISTICS
1830 /*
1831 * Statistics.
1832 */
1833#define APIC_REG_COUNTER(a_Reg, a_Desc, a_Key) \
1834 do { \
1835 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, a_Desc, a_Key, idCpu); \
1836 AssertRCReturn(rc, rc); \
1837 } while(0)
1838
1839#define APIC_PROF_COUNTER(a_Reg, a_Desc, a_Key) \
1840 do { \
1841 rc = STAMR3RegisterF(pVM, a_Reg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, a_Desc, a_Key, \
1842 idCpu); \
1843 AssertRCReturn(rc, rc); \
1844 } while(0)
1845
1846 bool const fHasRC = !HMIsEnabled(pVM);
1847 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1848 {
1849 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1850 PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
1851
1852 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR0, "Number of APIC MMIO reads in R0.", "/Devices/APIC/%u/R0/MmioRead");
1853 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR0, "Number of APIC MMIO writes in R0.", "/Devices/APIC/%u/R0/MmioWrite");
1854 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR0, "Number of APIC MSR reads in R0.", "/Devices/APIC/%u/R0/MsrRead");
1855 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR0, "Number of APIC MSR writes in R0.", "/Devices/APIC/%u/R0/MsrWrite");
1856
1857 APIC_REG_COUNTER(&pApicCpu->StatMmioReadR3, "Number of APIC MMIO reads in R3.", "/Devices/APIC/%u/R3/MmioReadR3");
1858 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteR3, "Number of APIC MMIO writes in R3.", "/Devices/APIC/%u/R3/MmioWriteR3");
1859 APIC_REG_COUNTER(&pApicCpu->StatMsrReadR3, "Number of APIC MSR reads in R3.", "/Devices/APIC/%u/R3/MsrReadR3");
1860 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteR3, "Number of APIC MSR writes in R3.", "/Devices/APIC/%u/R3/MsrWriteR3");
1861
1862 if (fHasRC)
1863 {
1864 APIC_REG_COUNTER(&pApicCpu->StatMmioReadRC, "Number of APIC MMIO reads in RC.", "/Devices/APIC/%u/RC/MmioRead");
1865 APIC_REG_COUNTER(&pApicCpu->StatMmioWriteRC, "Number of APIC MMIO writes in RC.", "/Devices/APIC/%u/RC/MmioWrite");
1866 APIC_REG_COUNTER(&pApicCpu->StatMsrReadRC, "Number of APIC MSR reads in RC.", "/Devices/APIC/%u/RC/MsrRead");
1867 APIC_REG_COUNTER(&pApicCpu->StatMsrWriteRC, "Number of APIC MSR writes in RC.", "/Devices/APIC/%u/RC/MsrWrite");
1868 }
1869
1870 APIC_PROF_COUNTER(&pApicCpu->StatUpdatePendingIntrs, "Profiling of APICUpdatePendingInterrupts",
1871 "/PROF/CPU%d/APIC/UpdatePendingInterrupts");
1872 APIC_PROF_COUNTER(&pApicCpu->StatPostIntr, "Profiling of APICPostInterrupt", "/PROF/CPU%d/APIC/PostInterrupt");
1873
1874 APIC_REG_COUNTER(&pApicCpu->StatPostIntrAlreadyPending, "Number of times an interrupt is already pending.",
1875 "/Devices/APIC/%u/PostInterruptAlreadyPending");
1876 APIC_REG_COUNTER(&pApicCpu->StatTimerCallback, "Number of times the timer callback is invoked.",
1877 "/Devices/APIC/%u/TimerCallback");
1878
1879 APIC_REG_COUNTER(&pApicCpu->StatTprWrite, "Number of TPR writes.", "/Devices/APIC/%u/TprWrite");
1880 APIC_REG_COUNTER(&pApicCpu->StatTprRead, "Number of TPR reads.", "/Devices/APIC/%u/TprRead");
1881 APIC_REG_COUNTER(&pApicCpu->StatEoiWrite, "Number of EOI writes.", "/Devices/APIC/%u/EoiWrite");
1882 APIC_REG_COUNTER(&pApicCpu->StatMaskedByTpr, "Number of times TPR masks an interrupt in APICGetInterrupt.",
1883 "/Devices/APIC/%u/MaskedByTpr");
1884 APIC_REG_COUNTER(&pApicCpu->StatMaskedByPpr, "Number of times PPR masks an interrupt in APICGetInterrupt.",
1885 "/Devices/APIC/%u/MaskedByPpr");
1886 APIC_REG_COUNTER(&pApicCpu->StatTimerIcrWrite, "Number of times the timer ICR is written.",
1887 "/Devices/APIC/%u/TimerIcrWrite");
1888 APIC_REG_COUNTER(&pApicCpu->StatIcrLoWrite, "Number of times the ICR Lo (send IPI) is written.",
1889 "/Devices/APIC/%u/IcrLoWrite");
1890 }
1891# undef APIC_PROF_COUNTER
1892# undef APIC_REG_ACCESS_COUNTER
1893#endif
1894
1895 return VINF_SUCCESS;
1896}
1897
1898
1899/**
1900 * APIC device registration structure.
1901 */
1902const PDMDEVREG g_DeviceAPIC =
1903{
1904 /* u32Version */
1905 PDM_DEVREG_VERSION,
1906 /* szName */
1907 "apic",
1908 /* szRCMod */
1909 "VMMRC.rc",
1910 /* szR0Mod */
1911 "VMMR0.r0",
1912 /* pszDescription */
1913 "Advanced Programmable Interrupt Controller",
1914 /* fFlags */
1915 PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
1916 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
1917 /* fClass */
1918 PDM_DEVREG_CLASS_PIC,
1919 /* cMaxInstances */
1920 1,
1921 /* cbInstance */
1922 sizeof(APICDEV),
1923 /* pfnConstruct */
1924 apicR3Construct,
1925 /* pfnDestruct */
1926 apicR3Destruct,
1927 /* pfnRelocate */
1928 apicR3Relocate,
1929 /* pfnMemSetup */
1930 NULL,
1931 /* pfnPowerOn */
1932 NULL,
1933 /* pfnReset */
1934 apicR3Reset,
1935 /* pfnSuspend */
1936 NULL,
1937 /* pfnResume */
1938 NULL,
1939 /* pfnAttach */
1940 NULL,
1941 /* pfnDetach */
1942 NULL,
1943 /* pfnQueryInterface. */
1944 NULL,
1945 /* pfnInitComplete */
1946 apicR3InitComplete,
1947 /* pfnPowerOff */
1948 NULL,
1949 /* pfnSoftReset */
1950 NULL,
1951 /* u32VersionEnd */
1952 PDM_DEVREG_VERSION
1953};
1954
1955#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1956
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