CPUM.cpp@ 35368

Last change on this file since 35368 was 35346, checked in by vboxsync, 14 years ago
VMM reorg: Moving the public include files from include/VBox to include/VBox/vmm.
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1	/* $Id: CPUM.cpp 35346 2010-12-27 16:13:13Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/cpumdis.h>
40	#include <VBox/vmm/pgm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/selm.h>
43	#include <VBox/vmm/dbgf.h>
44	#include <VBox/vmm/patm.h>
45	#include <VBox/vmm/hwaccm.h>
46	#include <VBox/vmm/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vmm/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include "internal/pgm.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The current saved state version. */
66	#define CPUM_SAVED_STATE_VERSION 12
67	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
68	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
69	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatibility. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detect the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	/*
232	* Initialize the Guest CPUID state.
233	*/
234	rc = cpumR3CpuIdInit(pVM);
235	if (RT_FAILURE(rc))
236	return rc;
237	CPUMR3Reset(pVM);
238	return VINF_SUCCESS;
239	}
240
241
242	/**
243	* Detect the CPU vendor give n the
244	*
245	* @returns The vendor.
246	* @param uEAX EAX from CPUID(0).
247	* @param uEBX EBX from CPUID(0).
248	* @param uECX ECX from CPUID(0).
249	* @param uEDX EDX from CPUID(0).
250	*/
251	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
252	{
253	if ( uEAX >= 1
254	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
255	&& uECX == X86_CPUID_VENDOR_AMD_ECX
256	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
257	return CPUMCPUVENDOR_AMD;
258
259	if ( uEAX >= 1
260	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
261	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
262	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
263	return CPUMCPUVENDOR_INTEL;
264
265	/** @todo detect the other buggers... */
266	return CPUMCPUVENDOR_UNKNOWN;
267	}
268
269
270	/**
271	* Fetches overrides for a CPUID leaf.
272	*
273	* @returns VBox status code.
274	* @param pLeaf The leaf to load the overrides into.
275	* @param pCfgNode The CFGM node containing the overrides
276	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
277	* @param iLeaf The CPUID leaf number.
278	*/
279	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
280	{
281	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
282	if (pLeafNode)
283	{
284	uint32_t u32;
285	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
286	if (RT_SUCCESS(rc))
287	pLeaf->eax = u32;
288	else
289	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
290
291	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
292	if (RT_SUCCESS(rc))
293	pLeaf->ebx = u32;
294	else
295	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
296
297	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
298	if (RT_SUCCESS(rc))
299	pLeaf->ecx = u32;
300	else
301	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
302
303	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
304	if (RT_SUCCESS(rc))
305	pLeaf->edx = u32;
306	else
307	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
308
309	}
310	return VINF_SUCCESS;
311	}
312
313
314	/**
315	* Load the overrides for a set of CPUID leaves.
316	*
317	* @returns VBox status code.
318	* @param paLeaves The leaf array.
319	* @param cLeaves The number of leaves.
320	* @param uStart The start leaf number.
321	* @param pCfgNode The CFGM node containing the overrides
322	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
323	*/
324	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
325	{
326	for (uint32_t i = 0; i < cLeaves; i++)
327	{
328	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
329	if (RT_FAILURE(rc))
330	return rc;
331	}
332
333	return VINF_SUCCESS;
334	}
335
336	/**
337	* Init a set of host CPUID leaves.
338	*
339	* @returns VBox status code.
340	* @param paLeaves The leaf array.
341	* @param cLeaves The number of leaves.
342	* @param uStart The start leaf number.
343	* @param pCfgNode The /CPUM/HostCPUID/ node.
344	*/
345	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
346	{
347	/* Using the ECX variant for all of them can't hurt... */
348	for (uint32_t i = 0; i < cLeaves; i++)
349	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
350
351	/* Load CPUID leaf override; we currently don't care if the user
352	specifies features the host CPU doesn't support. */
353	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
354	}
355
356
357	/**
358	* Initializes the emulated CPU's cpuid information.
359	*
360	* @returns VBox status code.
361	* @param pVM The VM to operate on.
362	*/
363	static int cpumR3CpuIdInit(PVM pVM)
364	{
365	PCPUM pCPUM = &pVM->cpum.s;
366	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
367	uint32_t i;
368	int rc;
369
370	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
371	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
372	{ \
373	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
374	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
375	}
376	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
377	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
378	{ \
379	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
380	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
381	}
382
383	/*
384	* Read the configuration.
385	*/
386	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
387	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
388	* completely overridden by VirtualBox custom strings. Some
389	* CPUID information is withheld, like the cache info. */
390	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
391	AssertRCReturn(rc, rc);
392
393	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
394	* When non-zero CPUID features that could cause portability issues will be
395	* stripped. The higher the value the more features gets stripped. Higher
396	* values should only be used when older CPUs are involved since it may
397	* harm performance and maybe also cause problems with specific guests. */
398	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
399	AssertRCReturn(rc, rc);
400
401	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_INTERNAL_ERROR_2);
402
403	/*
404	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
405	* been overridden).
406	*/
407	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
408	* Overrides the host CPUID leaf values used for calculating the guest CPUID
409	* leaves. This can be used to preserve the CPUID values when moving a VM
410	* to a different machine. Another use is restricting (or extending) the
411	* feature set exposed to the guest. */
412	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
413	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
414	AssertRCReturn(rc, rc);
415	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
416	AssertRCReturn(rc, rc);
417	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
418	AssertRCReturn(rc, rc);
419
420	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
421	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
422
423	/*
424	* Determine the default leaf.
425	*
426	* Intel returns values of the highest standard function, while AMD
427	* returns zeros. VIA on the other hand seems to returning nothing or
428	* perhaps some random garbage, we don't try to duplicate this behavior.
429	*/
430	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
431	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
432	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
433
434
435	/* Cpuid 1 & 0x80000001:
436	* Only report features we can support.
437	*
438	* Note! When enabling new features the Synthetic CPU and Portable CPUID
439	* options may require adjusting (i.e. stripping what was enabled).
440	*/
441	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
442	\| X86_CPUID_FEATURE_EDX_VME
443	\| X86_CPUID_FEATURE_EDX_DE
444	\| X86_CPUID_FEATURE_EDX_PSE
445	\| X86_CPUID_FEATURE_EDX_TSC
446	\| X86_CPUID_FEATURE_EDX_MSR
447	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
448	\| X86_CPUID_FEATURE_EDX_MCE
449	\| X86_CPUID_FEATURE_EDX_CX8
450	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
451	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
452	//\| X86_CPUID_FEATURE_EDX_SEP
453	\| X86_CPUID_FEATURE_EDX_MTRR
454	\| X86_CPUID_FEATURE_EDX_PGE
455	\| X86_CPUID_FEATURE_EDX_MCA
456	\| X86_CPUID_FEATURE_EDX_CMOV
457	\| X86_CPUID_FEATURE_EDX_PAT
458	\| X86_CPUID_FEATURE_EDX_PSE36
459	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
460	\| X86_CPUID_FEATURE_EDX_CLFSH
461	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
462	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
463	\| X86_CPUID_FEATURE_EDX_MMX
464	\| X86_CPUID_FEATURE_EDX_FXSR
465	\| X86_CPUID_FEATURE_EDX_SSE
466	\| X86_CPUID_FEATURE_EDX_SSE2
467	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
468	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
469	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
470	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
471	\| 0;
472	pCPUM->aGuestCpuIdStd[1].ecx &= 0
473	\| X86_CPUID_FEATURE_ECX_SSE3
474	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
475	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
476	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
477	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
478	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
479	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
480	\| X86_CPUID_FEATURE_ECX_SSSE3
481	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
482	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
483	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
484	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
485	/* ECX Bit 21 - x2APIC support - not yet. */
486	// \| X86_CPUID_FEATURE_ECX_X2APIC
487	/* ECX Bit 23 - POPCNT instruction. */
488	//\| X86_CPUID_FEATURE_ECX_POPCNT
489	\| 0;
490	if (pCPUM->u8PortableCpuIdLevel > 0)
491	{
492	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
493	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
494	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
495	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
496	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
497	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
498	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
499
500	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
501	\| X86_CPUID_FEATURE_EDX_PSN
502	\| X86_CPUID_FEATURE_EDX_DS
503	\| X86_CPUID_FEATURE_EDX_ACPI
504	\| X86_CPUID_FEATURE_EDX_SS
505	\| X86_CPUID_FEATURE_EDX_TM
506	\| X86_CPUID_FEATURE_EDX_PBE
507	)));
508	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
509	\| X86_CPUID_FEATURE_ECX_DTES64
510	\| X86_CPUID_FEATURE_ECX_CPLDS
511	\| X86_CPUID_FEATURE_ECX_VMX
512	\| X86_CPUID_FEATURE_ECX_SMX
513	\| X86_CPUID_FEATURE_ECX_EST
514	\| X86_CPUID_FEATURE_ECX_TM2
515	\| X86_CPUID_FEATURE_ECX_CNTXID
516	\| X86_CPUID_FEATURE_ECX_FMA
517	\| X86_CPUID_FEATURE_ECX_CX16
518	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
519	\| X86_CPUID_FEATURE_ECX_PDCM
520	\| X86_CPUID_FEATURE_ECX_DCA
521	\| X86_CPUID_FEATURE_ECX_MOVBE
522	\| X86_CPUID_FEATURE_ECX_AES
523	\| X86_CPUID_FEATURE_ECX_POPCNT
524	\| X86_CPUID_FEATURE_ECX_XSAVE
525	\| X86_CPUID_FEATURE_ECX_OSXSAVE
526	\| X86_CPUID_FEATURE_ECX_AVX
527	)));
528	}
529
530	/* Cpuid 0x80000001:
531	* Only report features we can support.
532	*
533	* Note! When enabling new features the Synthetic CPU and Portable CPUID
534	* options may require adjusting (i.e. stripping what was enabled).
535	*
536	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
537	*/
538	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
539	\| X86_CPUID_AMD_FEATURE_EDX_VME
540	\| X86_CPUID_AMD_FEATURE_EDX_DE
541	\| X86_CPUID_AMD_FEATURE_EDX_PSE
542	\| X86_CPUID_AMD_FEATURE_EDX_TSC
543	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
544	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
545	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
546	\| X86_CPUID_AMD_FEATURE_EDX_CX8
547	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
548	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
549	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
550	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
551	\| X86_CPUID_AMD_FEATURE_EDX_PGE
552	\| X86_CPUID_AMD_FEATURE_EDX_MCA
553	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
554	\| X86_CPUID_AMD_FEATURE_EDX_PAT
555	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
556	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
557	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
558	\| X86_CPUID_AMD_FEATURE_EDX_MMX
559	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
560	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
561	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
562	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
563	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
564	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
565	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
566	\| 0;
567	pCPUM->aGuestCpuIdExt[1].ecx &= 0
568	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
569	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
570	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
571	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
572	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
573	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
574	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
575	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
576	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
577	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
578	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
579	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
580	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
581	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
582	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
583	\| 0;
584	if (pCPUM->u8PortableCpuIdLevel > 0)
585	{
586	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
587	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
588	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
589	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
590	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
591	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
592	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
593
594	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
595	\| X86_CPUID_AMD_FEATURE_ECX_SVM
596	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
597	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
598	\| X86_CPUID_AMD_FEATURE_ECX_ABM
599	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
600	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
601	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
602	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
603	\| X86_CPUID_AMD_FEATURE_ECX_IBS
604	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
605	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
606	\| X86_CPUID_AMD_FEATURE_ECX_WDT
607	\| UINT32_C(0xffffc000)
608	)));
609	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
610	\| X86_CPUID_AMD_FEATURE_EDX_SEP
611	\| RT_BIT(18)
612	\| RT_BIT(19)
613	\| RT_BIT(21)
614	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
615	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
616	\| RT_BIT(28)
617	)));
618	}
619
620	/*
621	* Apply the Synthetic CPU modifications. (TODO: move this up)
622	*/
623	if (pCPUM->fSyntheticCpu)
624	{
625	static const char s_szVendor[13] = "VirtualBox ";
626	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
627
628	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
629
630	/* Limit the nr of standard leaves; 5 for monitor/mwait */
631	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
632
633	/* 0: Vendor */
634	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
635	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
636	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
637
638	/* 1.eax: Version information. family : model : stepping */
639	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
640
641	/* Leaves 2 - 4 are Intel only - zero them out */
642	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
643	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
644	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
645
646	/* Leaf 5 = monitor/mwait */
647
648	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
649	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
650	/* AMD only - set to zero. */
651	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
652
653	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
654	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
655
656	/* 0x800000002-4: Processor Name String Identifier. */
657	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
658	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
659	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
660	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
661	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
662	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
663	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
664	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
665	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
666	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
667	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
668	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
669
670	/* 0x800000005-7 - reserved -> zero */
671	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
672	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
673	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
674
675	/* 0x800000008: only the max virtual and physical address size. */
676	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
677	}
678
679	/*
680	* Hide HTT, multicode, SMP, whatever.
681	* (APIC-ID := 0 and #LogCpus := 0)
682	*/
683	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
684	#ifdef VBOX_WITH_MULTI_CORE
685	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
686	&& pVM->cCpus > 1)
687	{
688	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
689	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
690	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
691	}
692	#endif
693
694	/* Cpuid 2:
695	* Intel: Cache and TLB information
696	* AMD: Reserved
697	* Safe to expose; restrict the number of calls to 1 for the portable case.
698	*/
699	if ( pCPUM->u8PortableCpuIdLevel > 0
700	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
701	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
702	{
703	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
704	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
705	}
706
707	/* Cpuid 3:
708	* Intel: EAX, EBX - reserved (transmeta uses these)
709	* ECX, EDX - Processor Serial Number if available, otherwise reserved
710	* AMD: Reserved
711	* Safe to expose
712	*/
713	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
714	{
715	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
716	if (pCPUM->u8PortableCpuIdLevel > 0)
717	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
718	}
719
720	/* Cpuid 4:
721	* Intel: Deterministic Cache Parameters Leaf
722	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
723	* AMD: Reserved
724	* Safe to expose, except for EAX:
725	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
726	* Bits 31-26: Maximum number of processor cores in this physical package**
727	* Note: These SMP values are constant regardless of ECX
728	*/
729	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
730	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
731	#ifdef VBOX_WITH_MULTI_CORE
732	if ( pVM->cCpus > 1
733	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
734	{
735	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
736	/* One logical processor with possibly multiple cores. */
737	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
738	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
739	}
740	#endif
741
742	/* Cpuid 5: Monitor/mwait Leaf
743	* Intel: ECX, EDX - reserved
744	* EAX, EBX - Smallest and largest monitor line size
745	* AMD: EDX - reserved
746	* EAX, EBX - Smallest and largest monitor line size
747	* ECX - extensions (ignored for now)
748	* Safe to expose
749	*/
750	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
751	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
752
753	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
754	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
755	* Expose MWAIT extended features to the guest. For now we expose
756	* just MWAIT break on interrupt feature (bit 1).
757	*/
758	bool fMWaitExtensions;
759	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
760	if (fMWaitExtensions)
761	{
762	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
763	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
764	it shall be part of our power management virtualization model */
765	#if 0
766	/* MWAIT sub C-states */
767	pCPUM->aGuestCpuIdStd[5].edx =
768	(0 << 0) /* 0 in C0 */ \|
769	(2 << 4) /* 2 in C1 */ \|
770	(2 << 8) /* 2 in C2 */ \|
771	(2 << 12) /* 2 in C3 */ \|
772	(0 << 16) /* 0 in C4 */
773	;
774	#endif
775	}
776	else
777	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
778
779	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
780	* Safe to pass on to the guest.
781	*
782	* Intel: 0x800000005 reserved
783	* 0x800000006 L2 cache information
784	* AMD: 0x800000005 L1 cache information
785	* 0x800000006 L2/L3 cache information
786	*/
787
788	/* Cpuid 0x800000007:
789	* AMD: EAX, EBX, ECX - reserved
790	* EDX: Advanced Power Management Information
791	* Intel: Reserved
792	*/
793	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
794	{
795	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
796
797	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
798
799	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
800	{
801	/* Only expose the TSC invariant capability bit to the guest. */
802	pCPUM->aGuestCpuIdExt[7].edx &= 0
803	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
804	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
805	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
806	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
807	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
808	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
809	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
810	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
811	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
812	* Linux kernels blindly assume that the AMD performance counters work
813	* if this is set for 64 bits guests. (Can't really find a CPUID feature
814	* bit for them though.) */
815	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
816	#endif
817	\| 0;
818	}
819	else
820	pCPUM->aGuestCpuIdExt[7].edx = 0;
821	}
822
823	/* Cpuid 0x800000008:
824	* AMD: EBX, EDX - reserved
825	* EAX: Virtual/Physical/Guest address Size
826	* ECX: Number of cores + APICIdCoreIdSize
827	* Intel: EAX: Virtual/Physical address Size
828	* EBX, ECX, EDX - reserved
829	*/
830	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
831	{
832	/* Only expose the virtual and physical address sizes to the guest. */
833	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
834	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
835	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
836	* NC (0-7) Number of cores; 0 equals 1 core */
837	pCPUM->aGuestCpuIdExt[8].ecx = 0;
838	#ifdef VBOX_WITH_MULTI_CORE
839	if ( pVM->cCpus > 1
840	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
841	{
842	/* Legacy method to determine the number of cores. */
843	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
844	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
845	}
846	#endif
847	}
848
849	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
850	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
851	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
852	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
853	*/
854	bool fNt4LeafLimit;
855	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
856	if (fNt4LeafLimit)
857	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
858
859	/*
860	* Limit it the number of entries and fill the remaining with the defaults.
861	*
862	* The limits are masking off stuff about power saving and similar, this
863	* is perhaps a bit crudely done as there is probably some relatively harmless
864	* info too in these leaves (like words about having a constant TSC).
865	*/
866	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
867	pCPUM->aGuestCpuIdStd[0].eax = 5;
868	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
869	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
870
871	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
872	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
873	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
874	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
875	: 0;
876	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
877	i++)
878	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
879
880	/*
881	* Centaur stuff (VIA).
882	*
883	* The important part here (we think) is to make sure the 0xc0000000
884	* function returns 0xc0000001. As for the features, we don't currently
885	* let on about any of those... 0xc0000002 seems to be some
886	* temperature/hz/++ stuff, include it as well (static).
887	*/
888	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
889	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
890	{
891	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
892	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
893	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
894	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
895	i++)
896	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
897	}
898	else
899	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
900	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
901
902
903	/*
904	* Load CPUID overrides from configuration.
905	* Note: Kind of redundant now, but allows unchanged overrides
906	*/
907	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
908	* Overrides the CPUID leaf values. */
909	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
910	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
911	AssertRCReturn(rc, rc);
912	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
913	AssertRCReturn(rc, rc);
914	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
915	AssertRCReturn(rc, rc);
916
917	/*
918	* Check if PAE was explicitely enabled by the user.
919	*/
920	bool fEnable;
921	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
922	if (fEnable)
923	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
924
925	/*
926	* We don't normally enable NX for raw-mode, so give the user a chance to
927	* force it on.
928	*/
929	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
930	if (fEnable)
931	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
932
933	/*
934	* Log the cpuid and we're good.
935	*/
936	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
937	RTCPUSET OnlineSet;
938	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
939	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
940	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
941	LogRel(("*********************** CPUID dump **********************\n"));
942	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
943	LogRel(("\n"));
944	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
945	RTLogRelSetBuffering(fOldBuffered);
946	LogRel(("****************** End of CPUID dump ********************\n"));
947
948	#undef PORTABLE_DISABLE_FEATURE_BIT
949	#undef PORTABLE_CLEAR_BITS_WHEN
950
951	return VINF_SUCCESS;
952	}
953
954
955	/**
956	* Applies relocations to data and code managed by this
957	* component. This function will be called at init and
958	* whenever the VMM need to relocate it self inside the GC.
959	*
960	* The CPUM will update the addresses used by the switcher.
961	*
962	* @param pVM The VM.
963	*/
964	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
965	{
966	LogFlow(("CPUMR3Relocate\n"));
967	for (VMCPUID i = 0; i < pVM->cCpus; i++)
968	{
969	/*
970	* Switcher pointers.
971	*/
972	PVMCPU pVCpu = &pVM->aCpus[i];
973	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
974	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
975
976	}
977	}
978
979
980	/**
981	* Apply late CPUM property changes based on the fHWVirtEx setting
982	*
983	* @param pVM The VM to operate on.
984	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
985	*/
986	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
987	{
988	/*
989	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
990	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
991	* of processors from (cpuid(4).eax >> 26) + 1.
992	*
993	* Note: this code is obsolete, but let's keep it here for reference.
994	* Purpose is valid when we artificially cap the max std id to less than 4.
995	*/
996	if (!fHWVirtExEnabled)
997	{
998	Assert(pVM->cpum.s.aGuestCpuIdStd[4].eax == 0);
999	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1000	}
1001	}
1002
1003	/**
1004	* Terminates the CPUM.
1005	*
1006	* Termination means cleaning up and freeing all resources,
1007	* the VM it self is at this point powered off or suspended.
1008	*
1009	* @returns VBox status code.
1010	* @param pVM The VM to operate on.
1011	*/
1012	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1013	{
1014	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1015	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1016	{
1017	PVMCPU pVCpu = &pVM->aCpus[i];
1018	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1019
1020	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1021	pVCpu->cpum.s.uMagic = 0;
1022	pCtx->dr[5] = 0;
1023	}
1024	#endif
1025	return 0;
1026	}
1027
1028
1029	/**
1030	* Resets a virtual CPU.
1031	*
1032	* Used by CPUMR3Reset and CPU hot plugging.
1033	*
1034	* @param pVCpu The virtual CPU handle.
1035	*/
1036	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1037	{
1038	/** @todo anything different for VCPU > 0? */
1039	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1040
1041	/*
1042	* Initialize everything to ZERO first.
1043	*/
1044	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1045	memset(pCtx, 0, sizeof(*pCtx));
1046	pVCpu->cpum.s.fUseFlags = fUseFlags;
1047
1048	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1049	pCtx->eip = 0x0000fff0;
1050	pCtx->edx = 0x00000600; /* P6 processor */
1051	pCtx->eflags.Bits.u1Reserved0 = 1;
1052
1053	pCtx->cs = 0xf000;
1054	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1055	pCtx->csHid.u32Limit = 0x0000ffff;
1056	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1057	pCtx->csHid.Attr.n.u1Present = 1;
1058	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1059
1060	pCtx->dsHid.u32Limit = 0x0000ffff;
1061	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1062	pCtx->dsHid.Attr.n.u1Present = 1;
1063	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1064
1065	pCtx->esHid.u32Limit = 0x0000ffff;
1066	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1067	pCtx->esHid.Attr.n.u1Present = 1;
1068	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1069
1070	pCtx->fsHid.u32Limit = 0x0000ffff;
1071	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1072	pCtx->fsHid.Attr.n.u1Present = 1;
1073	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1074
1075	pCtx->gsHid.u32Limit = 0x0000ffff;
1076	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1077	pCtx->gsHid.Attr.n.u1Present = 1;
1078	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1079
1080	pCtx->ssHid.u32Limit = 0x0000ffff;
1081	pCtx->ssHid.Attr.n.u1Present = 1;
1082	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1083	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1084
1085	pCtx->idtr.cbIdt = 0xffff;
1086	pCtx->gdtr.cbGdt = 0xffff;
1087
1088	pCtx->ldtrHid.u32Limit = 0xffff;
1089	pCtx->ldtrHid.Attr.n.u1Present = 1;
1090	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1091
1092	pCtx->trHid.u32Limit = 0xffff;
1093	pCtx->trHid.Attr.n.u1Present = 1;
1094	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
1095
1096	pCtx->dr[6] = X86_DR6_INIT_VAL;
1097	pCtx->dr[7] = X86_DR7_INIT_VAL;
1098
1099	pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
1100	pCtx->fpu.FCW = 0x37f;
1101
1102	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
1103	pCtx->fpu.MXCSR = 0x1F80;
1104
1105	/* Init PAT MSR */
1106	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1107
1108	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1109	* The Intel docs don't mention it.
1110	*/
1111	pCtx->msrEFER = 0;
1112	}
1113
1114
1115	/**
1116	* Resets the CPU.
1117	*
1118	* @returns VINF_SUCCESS.
1119	* @param pVM The VM handle.
1120	*/
1121	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1122	{
1123	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1124	{
1125	CPUMR3ResetCpu(&pVM->aCpus[i]);
1126
1127	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1128	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1129
1130	/* Magic marker for searching in crash dumps. */
1131	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1132	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1133	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1134	#endif
1135	}
1136	}
1137
1138
1139	/**
1140	* Called both in pass 0 and the final pass.
1141	*
1142	* @param pVM The VM handle.
1143	* @param pSSM The saved state handle.
1144	*/
1145	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1146	{
1147	/*
1148	* Save all the CPU ID leaves here so we can check them for compatibility
1149	* upon loading.
1150	*/
1151	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1152	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1153
1154	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1155	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1156
1157	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1158	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1159
1160	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1161
1162	/*
1163	* Save a good portion of the raw CPU IDs as well as they may come in
1164	* handy when validating features for raw mode.
1165	*/
1166	CPUMCPUID aRawStd[16];
1167	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1168	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1169	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1170	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1171
1172	CPUMCPUID aRawExt[32];
1173	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1174	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1175	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1176	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1177	}
1178
1179
1180	/**
1181	* Loads the CPU ID leaves saved by pass 0.
1182	*
1183	* @returns VBox status code.
1184	* @param pVM The VM handle.
1185	* @param pSSM The saved state handle.
1186	* @param uVersion The format version.
1187	*/
1188	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1189	{
1190	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1191
1192	/*
1193	* Define a bunch of macros for simplifying the code.
1194	*/
1195	/* Generic expression + failure message. */
1196	#define CPUID_CHECK_RET(expr, fmt) \
1197	do { \
1198	if (!(expr)) \
1199	{ \
1200	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
1201	if (fStrictCpuIdChecks) \
1202	{ \
1203	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1204	RTStrFree(pszMsg); \
1205	return rcCpuid; \
1206	} \
1207	LogRel(("CPUM: %s\n", pszMsg)); \
1208	RTStrFree(pszMsg); \
1209	} \
1210	} while (0)
1211	#define CPUID_CHECK_WRN(expr, fmt) \
1212	do { \
1213	if (!(expr)) \
1214	LogRel(fmt); \
1215	} while (0)
1216
1217	/* For comparing two values and bitch if they differs. */
1218	#define CPUID_CHECK2_RET(what, host, saved) \
1219	do { \
1220	if ((host) != (saved)) \
1221	{ \
1222	if (fStrictCpuIdChecks) \
1223	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1224	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1225	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1226	} \
1227	} while (0)
1228	#define CPUID_CHECK2_WRN(what, host, saved) \
1229	do { \
1230	if ((host) != (saved)) \
1231	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1232	} while (0)
1233
1234	/* For checking raw cpu features (raw mode). */
1235	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1236	do { \
1237	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1238	{ \
1239	if (fStrictCpuIdChecks) \
1240	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1241	N_(#bit " mismatch: host=%d saved=%d"), \
1242	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1243	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1244	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1245	} \
1246	} while (0)
1247	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1248	do { \
1249	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1250	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1251	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1252	} while (0)
1253	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1254
1255	/* For checking guest features. */
1256	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1257	do { \
1258	if ( (aGuestCpuId##set [1].reg & bit) \
1259	&& !(aHostRaw##set [1].reg & bit) \
1260	&& !(aHostOverride##set [1].reg & bit) \
1261	&& !(aGuestOverride##set [1].reg & bit) \
1262	) \
1263	{ \
1264	if (fStrictCpuIdChecks) \
1265	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1266	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1267	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1268	} \
1269	} while (0)
1270	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1271	do { \
1272	if ( (aGuestCpuId##set [1].reg & bit) \
1273	&& !(aHostRaw##set [1].reg & bit) \
1274	&& !(aHostOverride##set [1].reg & bit) \
1275	&& !(aGuestOverride##set [1].reg & bit) \
1276	) \
1277	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1278	} while (0)
1279	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1280	do { \
1281	if ( (aGuestCpuId##set [1].reg & bit) \
1282	&& !(aHostRaw##set [1].reg & bit) \
1283	&& !(aHostOverride##set [1].reg & bit) \
1284	&& !(aGuestOverride##set [1].reg & bit) \
1285	) \
1286	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1287	} while (0)
1288	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1289
1290	/* For checking guest features if AMD guest CPU. */
1291	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1292	do { \
1293	if ( (aGuestCpuId##set [1].reg & bit) \
1294	&& fGuestAmd \
1295	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1296	&& !(aHostOverride##set [1].reg & bit) \
1297	&& !(aGuestOverride##set [1].reg & bit) \
1298	) \
1299	{ \
1300	if (fStrictCpuIdChecks) \
1301	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1302	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1303	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1304	} \
1305	} while (0)
1306	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1307	do { \
1308	if ( (aGuestCpuId##set [1].reg & bit) \
1309	&& fGuestAmd \
1310	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1311	&& !(aHostOverride##set [1].reg & bit) \
1312	&& !(aGuestOverride##set [1].reg & bit) \
1313	) \
1314	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1315	} while (0)
1316	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1317	do { \
1318	if ( (aGuestCpuId##set [1].reg & bit) \
1319	&& fGuestAmd \
1320	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1321	&& !(aHostOverride##set [1].reg & bit) \
1322	&& !(aGuestOverride##set [1].reg & bit) \
1323	) \
1324	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1325	} while (0)
1326	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1327
1328	/* For checking AMD features which have a corresponding bit in the standard
1329	range. (Intel defines very few bits in the extended feature sets.) */
1330	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1331	do { \
1332	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1333	&& !(fHostAmd \
1334	? aHostRawExt[1].reg & (ExtBit) \
1335	: aHostRawStd[1].reg & (StdBit)) \
1336	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1337	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1338	) \
1339	{ \
1340	if (fStrictCpuIdChecks) \
1341	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1342	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1343	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1344	} \
1345	} while (0)
1346	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1347	do { \
1348	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1349	&& !(fHostAmd \
1350	? aHostRawExt[1].reg & (ExtBit) \
1351	: aHostRawStd[1].reg & (StdBit)) \
1352	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1353	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1354	) \
1355	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1356	} while (0)
1357	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1358	do { \
1359	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1360	&& !(fHostAmd \
1361	? aHostRawExt[1].reg & (ExtBit) \
1362	: aHostRawStd[1].reg & (StdBit)) \
1363	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1364	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1365	) \
1366	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1367	} while (0)
1368	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1369
1370	/*
1371	* Load them into stack buffers first.
1372	*/
1373	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1374	uint32_t cGuestCpuIdStd;
1375	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1376	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1377	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1378	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1379
1380	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1381	uint32_t cGuestCpuIdExt;
1382	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1383	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1384	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1385	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1386
1387	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1388	uint32_t cGuestCpuIdCentaur;
1389	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1390	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1391	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1392	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1393
1394	CPUMCPUID GuestCpuIdDef;
1395	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1396	AssertRCReturn(rc, rc);
1397
1398	CPUMCPUID aRawStd[16];
1399	uint32_t cRawStd;
1400	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1401	if (cRawStd > RT_ELEMENTS(aRawStd))
1402	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1403	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1404
1405	CPUMCPUID aRawExt[32];
1406	uint32_t cRawExt;
1407	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1408	if (cRawExt > RT_ELEMENTS(aRawExt))
1409	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1410	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1411	AssertRCReturn(rc, rc);
1412
1413	/*
1414	* Note that we support restoring less than the current amount of standard
1415	* leaves because we've been allowed more is newer version of VBox.
1416	*
1417	* So, pad new entries with the default.
1418	*/
1419	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1420	aGuestCpuIdStd[i] = GuestCpuIdDef;
1421
1422	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1423	aGuestCpuIdExt[i] = GuestCpuIdDef;
1424
1425	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1426	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1427
1428	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1429	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1430
1431	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1432	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1433
1434	/*
1435	* Get the raw CPU IDs for the current host.
1436	*/
1437	CPUMCPUID aHostRawStd[16];
1438	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1439	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1440
1441	CPUMCPUID aHostRawExt[32];
1442	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1443	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1444
1445	/*
1446	* Get the host and guest overrides so we don't reject the state because
1447	* some feature was enabled thru these interfaces.
1448	* Note! We currently only need the feature leaves, so skip rest.
1449	*/
1450	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1451	CPUMCPUID aGuestOverrideStd[2];
1452	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1453	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1454
1455	CPUMCPUID aGuestOverrideExt[2];
1456	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1457	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1458
1459	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1460	CPUMCPUID aHostOverrideStd[2];
1461	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1462	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1463
1464	CPUMCPUID aHostOverrideExt[2];
1465	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1466	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1467
1468	/*
1469	* This can be skipped.
1470	*/
1471	bool fStrictCpuIdChecks;
1472	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1473
1474
1475
1476	/*
1477	* For raw-mode we'll require that the CPUs are very similar since we don't
1478	* intercept CPUID instructions for user mode applications.
1479	*/
1480	if (!HWACCMIsEnabled(pVM))
1481	{
1482	/* CPUID(0) */
1483	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1484	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1485	&& aHostRawStd[0].edx == aRawStd[0].edx,
1486	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1487	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1488	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1489	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1490	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1491	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1492
1493	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1494
1495	/* CPUID(1).eax */
1496	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1497	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1498	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1499
1500	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1501	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1502	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1503
1504	/* CPUID(1).ecx */
1505	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1506	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1507	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1508	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1509	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1510	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1511	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1512	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1513	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1514	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1515	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1516	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1517	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1518	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1519	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1520	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1521	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1522	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1523	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1524	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1525	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1526	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1527	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1528	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1529	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1530	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1531	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1532	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1533	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1534	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1535	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1536	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1537
1538	/* CPUID(1).edx */
1539	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1540	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1541	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1542	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1543	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1544	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1545	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1546	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1547	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1548	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1549	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1550	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1551	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1552	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1553	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1554	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1555	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1556	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1557	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1558	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1559	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1560	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1561	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1562	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1563	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1564	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1565	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1566	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1567	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1568	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1569	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1570	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1571
1572	/* CPUID(2) - config, mostly about caches. ignore. */
1573	/* CPUID(3) - processor serial number. ignore. */
1574	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1575	/* CPUID(5) - mwait/monitor config. ignore. */
1576	/* CPUID(6) - power management. ignore. */
1577	/* CPUID(7) - ???. ignore. */
1578	/* CPUID(8) - ???. ignore. */
1579	/* CPUID(9) - DCA. ignore for now. */
1580	/* CPUID(a) - PeMo info. ignore for now. */
1581	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1582
1583	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1584	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1585	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1586	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1587	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1588	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1589	{
1590	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1591	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1592	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1593	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1594	}
1595
1596	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1597	Note! Intel have/is marking many of the fields here as reserved. We
1598	will verify them as if it's an AMD CPU. */
1599	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1600	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1601	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1602	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1603	{
1604	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1605	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1606	&& aHostRawExt[0].edx == aRawExt[0].edx,
1607	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1608	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1609	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1610	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1611
1612	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1613	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1614	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1615	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1616	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1617	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1618
1619	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1620	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1621	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1622	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1623
1624	/* CPUID(0x80000001).ecx */
1625	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1626	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1627	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1628	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1629	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1630	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1631	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1632	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1633	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1634	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1635	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1636	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1637	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1638	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1639	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1640	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1641	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1642	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1643	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1644	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1645	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1646	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1647	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1648	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1649	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1650	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1651	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1652	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1653	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1654	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1655	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1656	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1657
1658	/* CPUID(0x80000001).edx */
1659	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1660	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1661	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1662	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1663	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1664	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1665	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1666	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1667	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1668	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1669	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1670	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1671	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1672	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1673	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1674	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1675	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1676	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1677	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1678	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1679	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1680	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1681	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1682	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1683	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1684	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1685	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1686	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1687	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1688	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1689	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1690	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1691
1692	/** @todo verify the rest as well. */
1693	}
1694	}
1695
1696
1697
1698	/*
1699	* Verify that we can support the features already exposed to the guest on
1700	* this host.
1701	*
1702	* Most of the features we're emulating requires intercepting instruction
1703	* and doing it the slow way, so there is no need to warn when they aren't
1704	* present in the host CPU. Thus we use IGN instead of EMU on these.
1705	*
1706	* Trailing comments:
1707	* "EMU" - Possible to emulate, could be lots of work and very slow.
1708	* "EMU?" - Can this be emulated?
1709	*/
1710	/* CPUID(1).ecx */
1711	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1712	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1713	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1714	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1715	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1716	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1717	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1718	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1719	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1720	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1721	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1722	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1723	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1724	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1725	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1726	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1727	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1728	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1729	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1730	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1731	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1732	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1733	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1734	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1735	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1736	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1739	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1740	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1741	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1742	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1743
1744	/* CPUID(1).edx */
1745	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1746	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1747	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1748	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1749	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1750	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1751	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1752	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1753	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1754	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1755	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1756	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1757	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1758	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1759	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1760	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1761	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1762	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1763	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1764	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1765	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1766	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1767	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1768	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1769	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1770	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1771	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1772	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1773	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1774	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1775	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1776	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1777
1778	/* CPUID(0x80000000). */
1779	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1780	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1781	{
1782	/** @todo deal with no 0x80000001 on the host. */
1783	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1784	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1785
1786	/* CPUID(0x80000001).ecx */
1787	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1788	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1789	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1790	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1791	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1792	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1793	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1794	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1795	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1796	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1797	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1798	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1799	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1800	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1801	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1802	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1803	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1804	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1805	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1806	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1807	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1808	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1809	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1810	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1811	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1812	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1813	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1814	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1815	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1816	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1817	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1818	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1819
1820	/* CPUID(0x80000001).edx */
1821	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1822	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1823	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1824	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1825	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1826	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1827	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1828	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1829	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1830	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1831	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1832	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1833	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1834	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1835	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1836	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1837	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1838	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1839	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1840	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1841	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1842	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1843	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1844	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1845	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1846	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1847	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1848	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1849	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1850	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1851	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1852	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1853	}
1854
1855	/*
1856	* We're good, commit the CPU ID leaves.
1857	*/
1858	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1859	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1860	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1861	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1862
1863	#undef CPUID_CHECK_RET
1864	#undef CPUID_CHECK_WRN
1865	#undef CPUID_CHECK2_RET
1866	#undef CPUID_CHECK2_WRN
1867	#undef CPUID_RAW_FEATURE_RET
1868	#undef CPUID_RAW_FEATURE_WRN
1869	#undef CPUID_RAW_FEATURE_IGN
1870	#undef CPUID_GST_FEATURE_RET
1871	#undef CPUID_GST_FEATURE_WRN
1872	#undef CPUID_GST_FEATURE_EMU
1873	#undef CPUID_GST_FEATURE_IGN
1874	#undef CPUID_GST_FEATURE2_RET
1875	#undef CPUID_GST_FEATURE2_WRN
1876	#undef CPUID_GST_FEATURE2_EMU
1877	#undef CPUID_GST_FEATURE2_IGN
1878	#undef CPUID_GST_AMD_FEATURE_RET
1879	#undef CPUID_GST_AMD_FEATURE_WRN
1880	#undef CPUID_GST_AMD_FEATURE_EMU
1881	#undef CPUID_GST_AMD_FEATURE_IGN
1882
1883	return VINF_SUCCESS;
1884	}
1885
1886
1887	/**
1888	* Pass 0 live exec callback.
1889	*
1890	* @returns VINF_SSM_DONT_CALL_AGAIN.
1891	* @param pVM The VM handle.
1892	* @param pSSM The saved state handle.
1893	* @param uPass The pass (0).
1894	*/
1895	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1896	{
1897	AssertReturn(uPass == 0, VERR_INTERNAL_ERROR_4);
1898	cpumR3SaveCpuId(pVM, pSSM);
1899	return VINF_SSM_DONT_CALL_AGAIN;
1900	}
1901
1902
1903	/**
1904	* Execute state save operation.
1905	*
1906	* @returns VBox status code.
1907	* @param pVM VM Handle.
1908	* @param pSSM SSM operation handle.
1909	*/
1910	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1911	{
1912	/*
1913	* Save.
1914	*/
1915	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1916	{
1917	PVMCPU pVCpu = &pVM->aCpus[i];
1918
1919	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1920	}
1921
1922	SSMR3PutU32(pSSM, pVM->cCpus);
1923	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1924	{
1925	PVMCPU pVCpu = &pVM->aCpus[i];
1926
1927	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1928	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1929	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1930	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1931	}
1932
1933	cpumR3SaveCpuId(pVM, pSSM);
1934	return VINF_SUCCESS;
1935	}
1936
1937
1938	/**
1939	* Load a version 1.6 CPUMCTX structure.
1940	*
1941	* @returns VBox status code.
1942	* @param pVM VM Handle.
1943	* @param pCpumctx16 Version 1.6 CPUMCTX
1944	*/
1945	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1946	{
1947	#define CPUMCTX16_LOADREG(RegName) \
1948	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1949
1950	#define CPUMCTX16_LOADDRXREG(RegName) \
1951	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1952
1953	#define CPUMCTX16_LOADHIDREG(RegName) \
1954	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1955	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1956	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1957
1958	#define CPUMCTX16_LOADSEGREG(RegName) \
1959	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1960	CPUMCTX16_LOADHIDREG(RegName);
1961
1962	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1963
1964	CPUMCTX16_LOADREG(rax);
1965	CPUMCTX16_LOADREG(rbx);
1966	CPUMCTX16_LOADREG(rcx);
1967	CPUMCTX16_LOADREG(rdx);
1968	CPUMCTX16_LOADREG(rdi);
1969	CPUMCTX16_LOADREG(rsi);
1970	CPUMCTX16_LOADREG(rbp);
1971	CPUMCTX16_LOADREG(esp);
1972	CPUMCTX16_LOADREG(rip);
1973	CPUMCTX16_LOADREG(rflags);
1974
1975	CPUMCTX16_LOADSEGREG(cs);
1976	CPUMCTX16_LOADSEGREG(ds);
1977	CPUMCTX16_LOADSEGREG(es);
1978	CPUMCTX16_LOADSEGREG(fs);
1979	CPUMCTX16_LOADSEGREG(gs);
1980	CPUMCTX16_LOADSEGREG(ss);
1981
1982	CPUMCTX16_LOADREG(r8);
1983	CPUMCTX16_LOADREG(r9);
1984	CPUMCTX16_LOADREG(r10);
1985	CPUMCTX16_LOADREG(r11);
1986	CPUMCTX16_LOADREG(r12);
1987	CPUMCTX16_LOADREG(r13);
1988	CPUMCTX16_LOADREG(r14);
1989	CPUMCTX16_LOADREG(r15);
1990
1991	CPUMCTX16_LOADREG(cr0);
1992	CPUMCTX16_LOADREG(cr2);
1993	CPUMCTX16_LOADREG(cr3);
1994	CPUMCTX16_LOADREG(cr4);
1995
1996	CPUMCTX16_LOADDRXREG(0);
1997	CPUMCTX16_LOADDRXREG(1);
1998	CPUMCTX16_LOADDRXREG(2);
1999	CPUMCTX16_LOADDRXREG(3);
2000	CPUMCTX16_LOADDRXREG(4);
2001	CPUMCTX16_LOADDRXREG(5);
2002	CPUMCTX16_LOADDRXREG(6);
2003	CPUMCTX16_LOADDRXREG(7);
2004
2005	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2006	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2007	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2008	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2009
2010	CPUMCTX16_LOADREG(ldtr);
2011	CPUMCTX16_LOADREG(tr);
2012
2013	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2014
2015	CPUMCTX16_LOADREG(msrEFER);
2016	CPUMCTX16_LOADREG(msrSTAR);
2017	CPUMCTX16_LOADREG(msrPAT);
2018	CPUMCTX16_LOADREG(msrLSTAR);
2019	CPUMCTX16_LOADREG(msrCSTAR);
2020	CPUMCTX16_LOADREG(msrSFMASK);
2021	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2022
2023	CPUMCTX16_LOADHIDREG(ldtr);
2024	CPUMCTX16_LOADHIDREG(tr);
2025
2026	#undef CPUMCTX16_LOADSEGREG
2027	#undef CPUMCTX16_LOADHIDREG
2028	#undef CPUMCTX16_LOADDRXREG
2029	#undef CPUMCTX16_LOADREG
2030	}
2031
2032
2033	/**
2034	* @copydoc FNSSMINTLOADPREP
2035	*/
2036	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2037	{
2038	pVM->cpum.s.fPendingRestore = true;
2039	return VINF_SUCCESS;
2040	}
2041
2042
2043	/**
2044	* @copydoc FNSSMINTLOADEXEC
2045	*/
2046	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2047	{
2048	/*
2049	* Validate version.
2050	*/
2051	if ( uVersion != CPUM_SAVED_STATE_VERSION
2052	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2053	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2054	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2055	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2056	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2057	{
2058	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2059	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2060	}
2061
2062	if (uPass == SSM_PASS_FINAL)
2063	{
2064	/*
2065	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2066	* really old SSM file versions.)
2067	*/
2068	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2069	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2070	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2071	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2072
2073	/*
2074	* Restore.
2075	*/
2076	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2077	{
2078	PVMCPU pVCpu = &pVM->aCpus[i];
2079	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2080	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2081
2082	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2083	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2084	pVCpu->cpum.s.Hyper.esp = uESP;
2085	}
2086
2087	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2088	{
2089	CPUMCTX_VER1_6 cpumctx16;
2090	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2091	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2092
2093	/* Save the old cpumctx state into the new one. */
2094	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2095
2096	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2097	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2098	}
2099	else
2100	{
2101	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2102	{
2103	uint32_t cCpus;
2104	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2105	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2106	VERR_SSM_UNEXPECTED_DATA);
2107	}
2108	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2109	\|\| pVM->cCpus == 1,
2110	("cCpus=%u\n", pVM->cCpus),
2111	VERR_SSM_UNEXPECTED_DATA);
2112
2113	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2114	{
2115	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2116	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2117	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2118	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2119	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2120	}
2121	}
2122
2123	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2124	raw-mode guest, so we have to do it ourselves. */
2125	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2126	&& !HWACCMIsEnabled(pVM))
2127	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2128	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2129	}
2130
2131	pVM->cpum.s.fPendingRestore = false;
2132
2133	/*
2134	* Guest CPUIDs.
2135	*/
2136	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2137	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2138
2139	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2140	* actually required. */
2141
2142	/*
2143	* Restore the CPUID leaves.
2144	*
2145	* Note that we support restoring less than the current amount of standard
2146	* leaves because we've been allowed more is newer version of VBox.
2147	*/
2148	uint32_t cElements;
2149	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2150	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2151	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2152	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2153
2154	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2155	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2156	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2157	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2158
2159	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2160	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2161	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2162	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2163
2164	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2165
2166	/*
2167	* Check that the basic cpuid id information is unchanged.
2168	*/
2169	/** @todo we should check the 64 bits capabilities too! */
2170	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2171	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2172	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2173	uint32_t au32CpuIdSaved[8];
2174	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2175	if (RT_SUCCESS(rc))
2176	{
2177	/* Ignore CPU stepping. */
2178	au32CpuId[4] &= 0xfffffff0;
2179	au32CpuIdSaved[4] &= 0xfffffff0;
2180
2181	/* Ignore APIC ID (AMD specs). */
2182	au32CpuId[5] &= ~0xff000000;
2183	au32CpuIdSaved[5] &= ~0xff000000;
2184
2185	/* Ignore the number of Logical CPUs (AMD specs). */
2186	au32CpuId[5] &= ~0x00ff0000;
2187	au32CpuIdSaved[5] &= ~0x00ff0000;
2188
2189	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2190	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2191	\| X86_CPUID_FEATURE_ECX_VMX
2192	\| X86_CPUID_FEATURE_ECX_SMX
2193	\| X86_CPUID_FEATURE_ECX_EST
2194	\| X86_CPUID_FEATURE_ECX_TM2
2195	\| X86_CPUID_FEATURE_ECX_CNTXID
2196	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2197	\| X86_CPUID_FEATURE_ECX_PDCM
2198	\| X86_CPUID_FEATURE_ECX_DCA
2199	\| X86_CPUID_FEATURE_ECX_X2APIC
2200	);
2201	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2202	\| X86_CPUID_FEATURE_ECX_VMX
2203	\| X86_CPUID_FEATURE_ECX_SMX
2204	\| X86_CPUID_FEATURE_ECX_EST
2205	\| X86_CPUID_FEATURE_ECX_TM2
2206	\| X86_CPUID_FEATURE_ECX_CNTXID
2207	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2208	\| X86_CPUID_FEATURE_ECX_PDCM
2209	\| X86_CPUID_FEATURE_ECX_DCA
2210	\| X86_CPUID_FEATURE_ECX_X2APIC
2211	);
2212
2213	/* Make sure we don't forget to update the masks when enabling
2214	* features in the future.
2215	*/
2216	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2217	( X86_CPUID_FEATURE_ECX_DTES64
2218	\| X86_CPUID_FEATURE_ECX_VMX
2219	\| X86_CPUID_FEATURE_ECX_SMX
2220	\| X86_CPUID_FEATURE_ECX_EST
2221	\| X86_CPUID_FEATURE_ECX_TM2
2222	\| X86_CPUID_FEATURE_ECX_CNTXID
2223	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2224	\| X86_CPUID_FEATURE_ECX_PDCM
2225	\| X86_CPUID_FEATURE_ECX_DCA
2226	\| X86_CPUID_FEATURE_ECX_X2APIC
2227	)));
2228	/* do the compare */
2229	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2230	{
2231	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2232	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2233	"Saved=%.*Rhxs\n"
2234	"Real =%.*Rhxs\n",
2235	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2236	sizeof(au32CpuId), au32CpuId));
2237	else
2238	{
2239	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2240	"Saved=%.*Rhxs\n"
2241	"Real =%.*Rhxs\n",
2242	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2243	sizeof(au32CpuId), au32CpuId));
2244	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2245	}
2246	}
2247	}
2248
2249	return rc;
2250	}
2251
2252
2253	/**
2254	* @copydoc FNSSMINTLOADPREP
2255	*/
2256	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2257	{
2258	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2259	return VINF_SUCCESS;
2260
2261	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2262	if (pVM->cpum.s.fPendingRestore)
2263	{
2264	LogRel(("CPUM: Missing state!\n"));
2265	return VERR_INTERNAL_ERROR_2;
2266	}
2267
2268	/* Notify PGM of the NXE states in case they've changed. */
2269	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2270	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2271	return VINF_SUCCESS;
2272	}
2273
2274
2275	/**
2276	* Checks if the CPUM state restore is still pending.
2277	*
2278	* @returns true / false.
2279	* @param pVM The VM handle.
2280	*/
2281	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2282	{
2283	return pVM->cpum.s.fPendingRestore;
2284	}
2285
2286
2287	/**
2288	* Formats the EFLAGS value into mnemonics.
2289	*
2290	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2291	* @param efl The EFLAGS value.
2292	*/
2293	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2294	{
2295	/*
2296	* Format the flags.
2297	*/
2298	static const struct
2299	{
2300	const char pszSet; const char pszClear; uint32_t fFlag;
2301	} s_aFlags[] =
2302	{
2303	{ "vip",NULL, X86_EFL_VIP },
2304	{ "vif",NULL, X86_EFL_VIF },
2305	{ "ac", NULL, X86_EFL_AC },
2306	{ "vm", NULL, X86_EFL_VM },
2307	{ "rf", NULL, X86_EFL_RF },
2308	{ "nt", NULL, X86_EFL_NT },
2309	{ "ov", "nv", X86_EFL_OF },
2310	{ "dn", "up", X86_EFL_DF },
2311	{ "ei", "di", X86_EFL_IF },
2312	{ "tf", NULL, X86_EFL_TF },
2313	{ "nt", "pl", X86_EFL_SF },
2314	{ "nz", "zr", X86_EFL_ZF },
2315	{ "ac", "na", X86_EFL_AF },
2316	{ "po", "pe", X86_EFL_PF },
2317	{ "cy", "nc", X86_EFL_CF },
2318	};
2319	char *psz = pszEFlags;
2320	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2321	{
2322	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2323	if (pszAdd)
2324	{
2325	strcpy(psz, pszAdd);
2326	psz += strlen(pszAdd);
2327	*psz++ = ' ';
2328	}
2329	}
2330	psz[-1] = '\0';
2331	}
2332
2333
2334	/**
2335	* Formats a full register dump.
2336	*
2337	* @param pVM VM Handle.
2338	* @param pCtx The context to format.
2339	* @param pCtxCore The context core to format.
2340	* @param pHlp Output functions.
2341	* @param enmType The dump type.
2342	* @param pszPrefix Register name prefix.
2343	*/
2344	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
2345	{
2346	/*
2347	* Format the EFLAGS.
2348	*/
2349	uint32_t efl = pCtxCore->eflags.u32;
2350	char szEFlags[80];
2351	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2352
2353	/*
2354	* Format the registers.
2355	*/
2356	switch (enmType)
2357	{
2358	case CPUMDUMPTYPE_TERSE:
2359	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2360	pHlp->pfnPrintf(pHlp,
2361	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2362	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2363	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2364	"%sr14=%016RX64 %sr15=%016RX64\n"
2365	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2366	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2367	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2368	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2369	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2370	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2371	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2372	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2373	else
2374	pHlp->pfnPrintf(pHlp,
2375	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2376	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2377	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2378	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2379	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2380	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2381	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2382	break;
2383
2384	case CPUMDUMPTYPE_DEFAULT:
2385	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2386	pHlp->pfnPrintf(pHlp,
2387	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2388	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2389	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2390	"%sr14=%016RX64 %sr15=%016RX64\n"
2391	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2392	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2393	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2394	,
2395	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2396	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2397	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2398	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2399	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2400	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2401	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2402	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2403	else
2404	pHlp->pfnPrintf(pHlp,
2405	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2406	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2407	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2408	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2409	,
2410	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2411	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2412	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2413	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2414	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2415	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2416	break;
2417
2418	case CPUMDUMPTYPE_VERBOSE:
2419	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2420	pHlp->pfnPrintf(pHlp,
2421	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2422	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2423	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2424	"%sr14=%016RX64 %sr15=%016RX64\n"
2425	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2426	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2427	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2428	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2429	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2430	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2431	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2432	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2433	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2434	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2435	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2436	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2437	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2438	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2439	,
2440	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2441	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2442	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2443	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2444	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2445	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2446	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2447	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2448	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2449	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2450	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2451	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2452	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2453	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2454	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2455	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2456	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2457	else
2458	pHlp->pfnPrintf(pHlp,
2459	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2460	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2461	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2462	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2463	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2464	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2465	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2466	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2467	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2468	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2469	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2470	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2471	,
2472	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2473	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2474	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2475	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2476	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2477	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2478	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2479	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2480	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2481	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2482	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2483	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2484
2485	pHlp->pfnPrintf(pHlp,
2486	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2487	"%sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2488	,
2489	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2490	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2491	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
2492	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2493	);
2494	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2495	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2496	{
2497	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2498	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2499	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2500	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2501	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2502	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2503	/** @todo This isn't entirenly correct and needs more work! */
2504	pHlp->pfnPrintf(pHlp,
2505	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2506	pszPrefix, iST, pszPrefix, iFPR,
2507	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2508	uTag, chSign, iInteger, u64Fraction, uExponent);
2509	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2510	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2511	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2512	else
2513	pHlp->pfnPrintf(pHlp, "\n");
2514	}
2515	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2516	pHlp->pfnPrintf(pHlp,
2517	iXMM & 1
2518	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2519	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2520	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2521	pCtx->fpu.aXMM[iXMM].au32[3],
2522	pCtx->fpu.aXMM[iXMM].au32[2],
2523	pCtx->fpu.aXMM[iXMM].au32[1],
2524	pCtx->fpu.aXMM[iXMM].au32[0]);
2525	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2526	if (pCtx->fpu.au32RsrvdRest[i])
2527	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2528	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2529
2530	pHlp->pfnPrintf(pHlp,
2531	"%sEFER =%016RX64\n"
2532	"%sPAT =%016RX64\n"
2533	"%sSTAR =%016RX64\n"
2534	"%sCSTAR =%016RX64\n"
2535	"%sLSTAR =%016RX64\n"
2536	"%sSFMASK =%016RX64\n"
2537	"%sKERNELGSBASE =%016RX64\n",
2538	pszPrefix, pCtx->msrEFER,
2539	pszPrefix, pCtx->msrPAT,
2540	pszPrefix, pCtx->msrSTAR,
2541	pszPrefix, pCtx->msrCSTAR,
2542	pszPrefix, pCtx->msrLSTAR,
2543	pszPrefix, pCtx->msrSFMASK,
2544	pszPrefix, pCtx->msrKERNELGSBASE);
2545	break;
2546	}
2547	}
2548
2549
2550	/**
2551	* Display all cpu states and any other cpum info.
2552	*
2553	* @param pVM VM Handle.
2554	* @param pHlp The info helper functions.
2555	* @param pszArgs Arguments, ignored.
2556	*/
2557	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2558	{
2559	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2560	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2561	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2562	cpumR3InfoHost(pVM, pHlp, pszArgs);
2563	}
2564
2565
2566	/**
2567	* Parses the info argument.
2568	*
2569	* The argument starts with 'verbose', 'terse' or 'default' and then
2570	* continues with the comment string.
2571	*
2572	* @param pszArgs The pointer to the argument string.
2573	* @param penmType Where to store the dump type request.
2574	* @param ppszComment Where to store the pointer to the comment string.
2575	*/
2576	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2577	{
2578	if (!pszArgs)
2579	{
2580	*penmType = CPUMDUMPTYPE_DEFAULT;
2581	*ppszComment = "";
2582	}
2583	else
2584	{
2585	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2586	{
2587	pszArgs += 5;
2588	*penmType = CPUMDUMPTYPE_VERBOSE;
2589	}
2590	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2591	{
2592	pszArgs += 5;
2593	*penmType = CPUMDUMPTYPE_TERSE;
2594	}
2595	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2596	{
2597	pszArgs += 7;
2598	*penmType = CPUMDUMPTYPE_DEFAULT;
2599	}
2600	else
2601	*penmType = CPUMDUMPTYPE_DEFAULT;
2602	*ppszComment = RTStrStripL(pszArgs);
2603	}
2604	}
2605
2606
2607	/**
2608	* Display the guest cpu state.
2609	*
2610	* @param pVM VM Handle.
2611	* @param pHlp The info helper functions.
2612	* @param pszArgs Arguments, ignored.
2613	*/
2614	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2615	{
2616	CPUMDUMPTYPE enmType;
2617	const char *pszComment;
2618	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2619
2620	/* @todo SMP support! */
2621	PVMCPU pVCpu = VMMGetCpu(pVM);
2622	if (!pVCpu)
2623	pVCpu = &pVM->aCpus[0];
2624
2625	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2626
2627	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2628	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2629	}
2630
2631
2632	/**
2633	* Display the current guest instruction
2634	*
2635	* @param pVM VM Handle.
2636	* @param pHlp The info helper functions.
2637	* @param pszArgs Arguments, ignored.
2638	*/
2639	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2640	{
2641	char szInstruction[256];
2642	/* @todo SMP support! */
2643	PVMCPU pVCpu = VMMGetCpu(pVM);
2644	if (!pVCpu)
2645	pVCpu = &pVM->aCpus[0];
2646
2647	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2648	if (RT_SUCCESS(rc))
2649	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2650	}
2651
2652
2653	/**
2654	* Display the hypervisor cpu state.
2655	*
2656	* @param pVM VM Handle.
2657	* @param pHlp The info helper functions.
2658	* @param pszArgs Arguments, ignored.
2659	*/
2660	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2661	{
2662	CPUMDUMPTYPE enmType;
2663	const char *pszComment;
2664	/* @todo SMP */
2665	PVMCPU pVCpu = &pVM->aCpus[0];
2666
2667	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2668	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2669	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2670	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2671	}
2672
2673
2674	/**
2675	* Display the host cpu state.
2676	*
2677	* @param pVM VM Handle.
2678	* @param pHlp The info helper functions.
2679	* @param pszArgs Arguments, ignored.
2680	*/
2681	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2682	{
2683	CPUMDUMPTYPE enmType;
2684	const char *pszComment;
2685	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2686	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2687
2688	/*
2689	* Format the EFLAGS.
2690	*/
2691	/* @todo SMP */
2692	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2693	#if HC_ARCH_BITS == 32
2694	uint32_t efl = pCtx->eflags.u32;
2695	#else
2696	uint64_t efl = pCtx->rflags;
2697	#endif
2698	char szEFlags[80];
2699	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2700
2701	/*
2702	* Format the registers.
2703	*/
2704	#if HC_ARCH_BITS == 32
2705	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2706	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2707	# endif
2708	{
2709	pHlp->pfnPrintf(pHlp,
2710	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2711	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2712	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2713	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2714	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2715	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2716	,
2717	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2718	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2719	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2720	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2721	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2722	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2723	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2724	}
2725	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2726	else
2727	# endif
2728	#endif
2729	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2730	{
2731	pHlp->pfnPrintf(pHlp,
2732	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2733	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2734	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2735	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2736	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2737	"r14=%016RX64 r15=%016RX64\n"
2738	"iopl=%d %31s\n"
2739	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2740	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2741	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2742	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2743	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2744	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2745	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2746	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2747	,
2748	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2749	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2750	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2751	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2752	pCtx->r11, pCtx->r12, pCtx->r13,
2753	pCtx->r14, pCtx->r15,
2754	X86_EFL_GET_IOPL(efl), szEFlags,
2755	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2756	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2757	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2758	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2759	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2760	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2761	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2762	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2763	}
2764	#endif
2765	}
2766
2767
2768	/**
2769	* Get L1 cache / TLS associativity.
2770	*/
2771	static const char getCacheAss(unsigned u, char pszBuf)
2772	{
2773	if (u == 0)
2774	return "res0 ";
2775	if (u == 1)
2776	return "direct";
2777	if (u == 255)
2778	return "fully";
2779	if (u >= 256)
2780	return "???";
2781
2782	RTStrPrintf(pszBuf, 16, "%d way", u);
2783	return pszBuf;
2784	}
2785
2786
2787	/**
2788	* Get L2 cache associativity.
2789	*/
2790	const char *getL2CacheAss(unsigned u)
2791	{
2792	switch (u)
2793	{
2794	case 0: return "off ";
2795	case 1: return "direct";
2796	case 2: return "2 way ";
2797	case 3: return "res3 ";
2798	case 4: return "4 way ";
2799	case 5: return "res5 ";
2800	case 6: return "8 way ";
2801	case 7: return "res7 ";
2802	case 8: return "16 way";
2803	case 9: return "res9 ";
2804	case 10: return "res10 ";
2805	case 11: return "res11 ";
2806	case 12: return "res12 ";
2807	case 13: return "res13 ";
2808	case 14: return "res14 ";
2809	case 15: return "fully ";
2810	default: return "????";
2811	}
2812	}
2813
2814
2815	/**
2816	* Display the guest CpuId leaves.
2817	*
2818	* @param pVM VM Handle.
2819	* @param pHlp The info helper functions.
2820	* @param pszArgs "terse", "default" or "verbose".
2821	*/
2822	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2823	{
2824	/*
2825	* Parse the argument.
2826	*/
2827	unsigned iVerbosity = 1;
2828	if (pszArgs)
2829	{
2830	pszArgs = RTStrStripL(pszArgs);
2831	if (!strcmp(pszArgs, "terse"))
2832	iVerbosity--;
2833	else if (!strcmp(pszArgs, "verbose"))
2834	iVerbosity++;
2835	}
2836
2837	/*
2838	* Start cracking.
2839	*/
2840	CPUMCPUID Host;
2841	CPUMCPUID Guest;
2842	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2843
2844	pHlp->pfnPrintf(pHlp,
2845	" RAW Standard CPUIDs\n"
2846	" Function eax ebx ecx edx\n");
2847	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2848	{
2849	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2850	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2851
2852	pHlp->pfnPrintf(pHlp,
2853	"Gst: %08x %08x %08x %08x %08x%s\n"
2854	"Hst: %08x %08x %08x %08x\n",
2855	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2856	i <= cStdMax ? "" : "*",
2857	Host.eax, Host.ebx, Host.ecx, Host.edx);
2858	}
2859
2860	/*
2861	* If verbose, decode it.
2862	*/
2863	if (iVerbosity)
2864	{
2865	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2866	pHlp->pfnPrintf(pHlp,
2867	"Name: %.04s%.04s%.04s\n"
2868	"Supports: 0-%x\n",
2869	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2870	}
2871
2872	/*
2873	* Get Features.
2874	*/
2875	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2876	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2877	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2878	if (cStdMax >= 1 && iVerbosity)
2879	{
2880	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2881
2882	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2883	uint32_t uEAX = Guest.eax;
2884
2885	pHlp->pfnPrintf(pHlp,
2886	"Family: %d \tExtended: %d \tEffective: %d\n"
2887	"Model: %d \tExtended: %d \tEffective: %d\n"
2888	"Stepping: %d\n"
2889	"Type: %d (%s)\n"
2890	"APIC ID: %#04x\n"
2891	"Logical CPUs: %d\n"
2892	"CLFLUSH Size: %d\n"
2893	"Brand ID: %#04x\n",
2894	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2895	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2896	ASMGetCpuStepping(uEAX),
2897	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2898	(Guest.ebx >> 24) & 0xff,
2899	(Guest.ebx >> 16) & 0xff,
2900	(Guest.ebx >> 8) & 0xff,
2901	(Guest.ebx >> 0) & 0xff);
2902	if (iVerbosity == 1)
2903	{
2904	uint32_t uEDX = Guest.edx;
2905	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2906	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2907	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2908	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2909	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2910	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2911	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2912	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2913	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2914	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2915	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2916	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2917	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2918	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2919	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2920	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2921	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2922	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2923	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2924	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2925	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2926	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2927	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2928	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2929	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2930	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2931	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2932	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2933	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2934	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2935	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2936	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2937	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2938	pHlp->pfnPrintf(pHlp, "\n");
2939
2940	uint32_t uECX = Guest.ecx;
2941	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2942	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2943	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2944	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2945	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2946	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2947	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2948	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2949	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2950	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2951	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2952	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2953	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2954	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2955	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2956	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2957	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2958	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2959	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
2960	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2961	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
2962	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
2963	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2964	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2965	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2966	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
2967	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2968	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2969	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2970	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2971	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2972	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2973	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2974	pHlp->pfnPrintf(pHlp, "\n");
2975	}
2976	else
2977	{
2978	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2979
2980	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
2981	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
2982	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
2983	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
2984
2985	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
2986	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
2987	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
2988	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
2989	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
2990	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
2991	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
2992	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
2993	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
2994	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
2995	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
2996	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
2997	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
2998	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
2999	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3000	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3001	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3002	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3003	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3004	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3005	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3006	pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3007	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3008	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3009	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3010	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3011	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3012	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3013	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3014	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3015	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3016	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3017	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3018
3019	pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3020	pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3021	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3022	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3023	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3024	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3025	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3026	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3027	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3028	pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3029	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3030	pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3031	pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3032	pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3033	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3034	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3035	pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3036	pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3037	pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3038	pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3039	pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3040	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3041	pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3042	pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3043	pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3044	pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3045	pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3046	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3047	pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3048	pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3049	pHlp->pfnPrintf(pHlp, "31 - Reserved (always 0) = %d (%d)\n", EcxGuest.u1Reserved4, EcxHost.u1Reserved4);
3050	}
3051	}
3052	if (cStdMax >= 2 && iVerbosity)
3053	{
3054	/** @todo */
3055	}
3056
3057	/*
3058	* Extended.
3059	* Implemented after AMD specs.
3060	*/
3061	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3062
3063	pHlp->pfnPrintf(pHlp,
3064	"\n"
3065	" RAW Extended CPUIDs\n"
3066	" Function eax ebx ecx edx\n");
3067	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3068	{
3069	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3070	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3071
3072	pHlp->pfnPrintf(pHlp,
3073	"Gst: %08x %08x %08x %08x %08x%s\n"
3074	"Hst: %08x %08x %08x %08x\n",
3075	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3076	i <= cExtMax ? "" : "*",
3077	Host.eax, Host.ebx, Host.ecx, Host.edx);
3078	}
3079
3080	/*
3081	* Understandable output
3082	*/
3083	if (iVerbosity)
3084	{
3085	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3086	pHlp->pfnPrintf(pHlp,
3087	"Ext Name: %.4s%.4s%.4s\n"
3088	"Ext Supports: 0x80000000-%#010x\n",
3089	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3090	}
3091
3092	if (iVerbosity && cExtMax >= 1)
3093	{
3094	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3095	uint32_t uEAX = Guest.eax;
3096	pHlp->pfnPrintf(pHlp,
3097	"Family: %d \tExtended: %d \tEffective: %d\n"
3098	"Model: %d \tExtended: %d \tEffective: %d\n"
3099	"Stepping: %d\n"
3100	"Brand ID: %#05x\n",
3101	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3102	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3103	ASMGetCpuStepping(uEAX),
3104	Guest.ebx & 0xfff);
3105
3106	if (iVerbosity == 1)
3107	{
3108	uint32_t uEDX = Guest.edx;
3109	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3110	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3111	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3112	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3113	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3114	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3115	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3116	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3117	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3118	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3119	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3120	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3121	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3122	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3123	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3124	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3125	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3126	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3127	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3128	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3129	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3130	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3131	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3132	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3133	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3134	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3135	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3136	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3137	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3138	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3139	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3140	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3141	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3142	pHlp->pfnPrintf(pHlp, "\n");
3143
3144	uint32_t uECX = Guest.ecx;
3145	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3146	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3147	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3148	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3149	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3150	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3151	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3152	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3153	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3154	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3155	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3156	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3157	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3158	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3159	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3160	for (unsigned iBit = 5; iBit < 32; iBit++)
3161	if (uECX & RT_BIT(iBit))
3162	pHlp->pfnPrintf(pHlp, " %d", iBit);
3163	pHlp->pfnPrintf(pHlp, "\n");
3164	}
3165	else
3166	{
3167	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3168
3169	uint32_t uEdxGst = Guest.edx;
3170	uint32_t uEdxHst = Host.edx;
3171	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3172	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3173	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3174	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3175	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3176	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3177	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3178	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3179	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3180	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3181	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3182	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3183	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3184	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3185	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3186	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3187	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3188	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3189	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3190	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3191	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3192	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3193	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3194	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3195	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3196	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3197	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3198	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3199	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3200	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3201	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3202	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3203	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3204
3205	uint32_t uEcxGst = Guest.ecx;
3206	uint32_t uEcxHst = Host.ecx;
3207	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3208	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3209	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3210	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3211	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3212	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3213	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3214	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3215	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3216	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3217	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3218	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3219	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3220	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3221	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3222	}
3223	}
3224
3225	if (iVerbosity && cExtMax >= 2)
3226	{
3227	char szString[443+1] = {0};
3228	uint32_t pu32 = (uint32_t )szString;
3229	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3230	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3231	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3232	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3233	if (cExtMax >= 3)
3234	{
3235	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3236	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3237	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3238	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3239	}
3240	if (cExtMax >= 4)
3241	{
3242	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3243	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3244	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3245	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3246	}
3247	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3248	}
3249
3250	if (iVerbosity && cExtMax >= 5)
3251	{
3252	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3253	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3254	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3255	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3256	char sz1[32];
3257	char sz2[32];
3258
3259	pHlp->pfnPrintf(pHlp,
3260	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3261	"TLB 2/4M Data: %s %3d entries\n",
3262	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3263	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3264	pHlp->pfnPrintf(pHlp,
3265	"TLB 4K Instr/Uni: %s %3d entries\n"
3266	"TLB 4K Data: %s %3d entries\n",
3267	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3268	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3269	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3270	"L1 Instr Cache Lines Per Tag: %d\n"
3271	"L1 Instr Cache Associativity: %s\n"
3272	"L1 Instr Cache Size: %d KB\n",
3273	(uEDX >> 0) & 0xff,
3274	(uEDX >> 8) & 0xff,
3275	getCacheAss((uEDX >> 16) & 0xff, sz1),
3276	(uEDX >> 24) & 0xff);
3277	pHlp->pfnPrintf(pHlp,
3278	"L1 Data Cache Line Size: %d bytes\n"
3279	"L1 Data Cache Lines Per Tag: %d\n"
3280	"L1 Data Cache Associativity: %s\n"
3281	"L1 Data Cache Size: %d KB\n",
3282	(uECX >> 0) & 0xff,
3283	(uECX >> 8) & 0xff,
3284	getCacheAss((uECX >> 16) & 0xff, sz1),
3285	(uECX >> 24) & 0xff);
3286	}
3287
3288	if (iVerbosity && cExtMax >= 6)
3289	{
3290	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3291	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3292	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3293
3294	pHlp->pfnPrintf(pHlp,
3295	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3296	"L2 TLB 2/4M Data: %s %4d entries\n",
3297	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3298	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3299	pHlp->pfnPrintf(pHlp,
3300	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3301	"L2 TLB 4K Data: %s %4d entries\n",
3302	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3303	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3304	pHlp->pfnPrintf(pHlp,
3305	"L2 Cache Line Size: %d bytes\n"
3306	"L2 Cache Lines Per Tag: %d\n"
3307	"L2 Cache Associativity: %s\n"
3308	"L2 Cache Size: %d KB\n",
3309	(uEDX >> 0) & 0xff,
3310	(uEDX >> 8) & 0xf,
3311	getL2CacheAss((uEDX >> 12) & 0xf),
3312	(uEDX >> 16) & 0xffff);
3313	}
3314
3315	if (iVerbosity && cExtMax >= 7)
3316	{
3317	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3318
3319	pHlp->pfnPrintf(pHlp, "APM Features: ");
3320	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3321	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3322	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3323	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3324	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3325	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3326	for (unsigned iBit = 6; iBit < 32; iBit++)
3327	if (uEDX & RT_BIT(iBit))
3328	pHlp->pfnPrintf(pHlp, " %d", iBit);
3329	pHlp->pfnPrintf(pHlp, "\n");
3330	}
3331
3332	if (iVerbosity && cExtMax >= 8)
3333	{
3334	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3335	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3336
3337	pHlp->pfnPrintf(pHlp,
3338	"Physical Address Width: %d bits\n"
3339	"Virtual Address Width: %d bits\n"
3340	"Guest Physical Address Width: %d bits\n",
3341	(uEAX >> 0) & 0xff,
3342	(uEAX >> 8) & 0xff,
3343	(uEAX >> 16) & 0xff);
3344	pHlp->pfnPrintf(pHlp,
3345	"Physical Core Count: %d\n",
3346	(uECX >> 0) & 0xff);
3347	}
3348
3349
3350	/*
3351	* Centaur.
3352	*/
3353	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3354
3355	pHlp->pfnPrintf(pHlp,
3356	"\n"
3357	" RAW Centaur CPUIDs\n"
3358	" Function eax ebx ecx edx\n");
3359	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3360	{
3361	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3362	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3363
3364	pHlp->pfnPrintf(pHlp,
3365	"Gst: %08x %08x %08x %08x %08x%s\n"
3366	"Hst: %08x %08x %08x %08x\n",
3367	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3368	i <= cCentaurMax ? "" : "*",
3369	Host.eax, Host.ebx, Host.ecx, Host.edx);
3370	}
3371
3372	/*
3373	* Understandable output
3374	*/
3375	if (iVerbosity)
3376	{
3377	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3378	pHlp->pfnPrintf(pHlp,
3379	"Centaur Supports: 0xc0000000-%#010x\n",
3380	Guest.eax);
3381	}
3382
3383	if (iVerbosity && cCentaurMax >= 1)
3384	{
3385	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3386	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3387	uint32_t uEdxHst = Host.edx;
3388
3389	if (iVerbosity == 1)
3390	{
3391	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3392	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3393	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3394	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3395	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3396	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3397	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3398	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3399	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3400	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3401	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3402	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3403	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3404	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3405	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3406	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3407	for (unsigned iBit = 14; iBit < 32; iBit++)
3408	if (uEdxGst & RT_BIT(iBit))
3409	pHlp->pfnPrintf(pHlp, " %d", iBit);
3410	pHlp->pfnPrintf(pHlp, "\n");
3411	}
3412	else
3413	{
3414	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3415	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3416	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3417	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3418	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3419	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3420	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3421	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3422	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3423	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3424	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3425	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3426	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3427	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3428	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3429	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3430	for (unsigned iBit = 14; iBit < 32; iBit++)
3431	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3432	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3433	pHlp->pfnPrintf(pHlp, "\n");
3434	}
3435	}
3436	}
3437
3438
3439	/**
3440	* Structure used when disassembling and instructions in DBGF.
3441	* This is used so the reader function can get the stuff it needs.
3442	*/
3443	typedef struct CPUMDISASSTATE
3444	{
3445	/** Pointer to the CPU structure. */
3446	PDISCPUSTATE pCpu;
3447	/** The VM handle. */
3448	PVM pVM;
3449	/** The VMCPU handle. */
3450	PVMCPU pVCpu;
3451	/** Pointer to the first byte in the segment. */
3452	RTGCUINTPTR GCPtrSegBase;
3453	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3454	RTGCUINTPTR GCPtrSegEnd;
3455	/** The size of the segment minus 1. */
3456	RTGCUINTPTR cbSegLimit;
3457	/** Pointer to the current page - R3 Ptr. */
3458	void const *pvPageR3;
3459	/** Pointer to the current page - GC Ptr. */
3460	RTGCPTR pvPageGC;
3461	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3462	PGMPAGEMAPLOCK PageMapLock;
3463	/** Whether the PageMapLock is valid or not. */
3464	bool fLocked;
3465	/** 64 bits mode or not. */
3466	bool f64Bits;
3467	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3468
3469
3470	/**
3471	* Instruction reader.
3472	*
3473	* @returns VBox status code.
3474	* @param PtrSrc Address to read from.
3475	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3476	* @param pu8Dst Where to store the bytes.
3477	* @param cbRead Number of bytes to read.
3478	* @param uDisCpu Pointer to the disassembler cpu state.
3479	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3480	*/
3481	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3482	{
3483	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3484	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3485	Assert(cbRead > 0);
3486	for (;;)
3487	{
3488	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3489
3490	/* Need to update the page translation? */
3491	if ( !pState->pvPageR3
3492	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3493	{
3494	int rc = VINF_SUCCESS;
3495
3496	/* translate the address */
3497	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3498	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3499	&& !HWACCMIsEnabled(pState->pVM))
3500	{
3501	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3502	if (!pState->pvPageR3)
3503	rc = VERR_INVALID_POINTER;
3504	}
3505	else
3506	{
3507	/* Release mapping lock previously acquired. */
3508	if (pState->fLocked)
3509	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3510	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3511	pState->fLocked = RT_SUCCESS_NP(rc);
3512	}
3513	if (RT_FAILURE(rc))
3514	{
3515	pState->pvPageR3 = NULL;
3516	return rc;
3517	}
3518	}
3519
3520	/* check the segment limit */
3521	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3522	return VERR_OUT_OF_SELECTOR_BOUNDS;
3523
3524	/* calc how much we can read */
3525	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3526	if (!pState->f64Bits)
3527	{
3528	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3529	if (cb > cbSeg && cbSeg)
3530	cb = cbSeg;
3531	}
3532	if (cb > cbRead)
3533	cb = cbRead;
3534
3535	/* read and advance */
3536	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3537	cbRead -= cb;
3538	if (!cbRead)
3539	return VINF_SUCCESS;
3540	pu8Dst += cb;
3541	PtrSrc += cb;
3542	}
3543	}
3544
3545
3546	/**
3547	* Disassemble an instruction and return the information in the provided structure.
3548	*
3549	* @returns VBox status code.
3550	* @param pVM VM Handle
3551	* @param pVCpu VMCPU Handle
3552	* @param pCtx CPU context
3553	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3554	* @param pCpu Disassembly state
3555	* @param pszPrefix String prefix for logging (debug only)
3556	*
3557	*/
3558	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3559	{
3560	CPUMDISASSTATE State;
3561	int rc;
3562
3563	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3564	State.pCpu = pCpu;
3565	State.pvPageGC = 0;
3566	State.pvPageR3 = NULL;
3567	State.pVM = pVM;
3568	State.pVCpu = pVCpu;
3569	State.fLocked = false;
3570	State.f64Bits = false;
3571
3572	/*
3573	* Get selector information.
3574	*/
3575	if ( (pCtx->cr0 & X86_CR0_PE)
3576	&& pCtx->eflags.Bits.u1VM == 0)
3577	{
3578	if (CPUMAreHiddenSelRegsValid(pVCpu))
3579	{
3580	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3581	State.GCPtrSegBase = pCtx->csHid.u64Base;
3582	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3583	State.cbSegLimit = pCtx->csHid.u32Limit;
3584	pCpu->mode = (State.f64Bits)
3585	? CPUMODE_64BIT
3586	: pCtx->csHid.Attr.n.u1DefBig
3587	? CPUMODE_32BIT
3588	: CPUMODE_16BIT;
3589	}
3590	else
3591	{
3592	DBGFSELINFO SelInfo;
3593
3594	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3595	if (RT_FAILURE(rc))
3596	{
3597	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3598	return rc;
3599	}
3600
3601	/*
3602	* Validate the selector.
3603	*/
3604	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3605	if (RT_FAILURE(rc))
3606	{
3607	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3608	return rc;
3609	}
3610	State.GCPtrSegBase = SelInfo.GCPtrBase;
3611	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3612	State.cbSegLimit = SelInfo.cbLimit;
3613	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3614	}
3615	}
3616	else
3617	{
3618	/* real or V86 mode */
3619	pCpu->mode = CPUMODE_16BIT;
3620	State.GCPtrSegBase = pCtx->cs * 16;
3621	State.GCPtrSegEnd = 0xFFFFFFFF;
3622	State.cbSegLimit = 0xFFFFFFFF;
3623	}
3624
3625	/*
3626	* Disassemble the instruction.
3627	*/
3628	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3629	pCpu->apvUserData[0] = &State;
3630
3631	uint32_t cbInstr;
3632	#ifndef LOG_ENABLED
3633	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3634	if (RT_SUCCESS(rc))
3635	{
3636	#else
3637	char szOutput[160];
3638	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3639	if (RT_SUCCESS(rc))
3640	{
3641	/* log it */
3642	if (pszPrefix)
3643	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3644	else
3645	Log(("%s", szOutput));
3646	#endif
3647	rc = VINF_SUCCESS;
3648	}
3649	else
3650	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3651
3652	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3653	if (State.fLocked)
3654	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3655
3656	return rc;
3657	}
3658
3659	#ifdef DEBUG
3660
3661	/**
3662	* Disassemble an instruction and dump it to the log
3663	*
3664	* @returns VBox status code.
3665	* @param pVM VM Handle
3666	* @param pVCpu VMCPU Handle
3667	* @param pCtx CPU context
3668	* @param pc GC instruction pointer
3669	* @param pszPrefix String prefix for logging
3670	*
3671	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3672	*/
3673	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3674	{
3675	DISCPUSTATE Cpu;
3676	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3677	}
3678
3679
3680	/**
3681	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3682	*
3683	* @internal
3684	*/
3685	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3686	{
3687	/** @todo SMP support!! */
3688	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3689	}
3690
3691	#endif /* DEBUG */
3692
3693	/**
3694	* API for controlling a few of the CPU features found in CR4.
3695	*
3696	* Currently only X86_CR4_TSD is accepted as input.
3697	*
3698	* @returns VBox status code.
3699	*
3700	* @param pVM The VM handle.
3701	* @param fOr The CR4 OR mask.
3702	* @param fAnd The CR4 AND mask.
3703	*/
3704	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3705	{
3706	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3707	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3708
3709	pVM->cpum.s.CR4.OrMask &= fAnd;
3710	pVM->cpum.s.CR4.OrMask \|= fOr;
3711
3712	return VINF_SUCCESS;
3713	}
3714
3715
3716	/**
3717	* Gets a pointer to the array of standard CPUID leaves.
3718	*
3719	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3720	*
3721	* @returns Pointer to the standard CPUID leaves (read-only).
3722	* @param pVM The VM handle.
3723	* @remark Intended for PATM.
3724	*/
3725	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3726	{
3727	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3728	}
3729
3730
3731	/**
3732	* Gets a pointer to the array of extended CPUID leaves.
3733	*
3734	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3735	*
3736	* @returns Pointer to the extended CPUID leaves (read-only).
3737	* @param pVM The VM handle.
3738	* @remark Intended for PATM.
3739	*/
3740	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3741	{
3742	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3743	}
3744
3745
3746	/**
3747	* Gets a pointer to the array of centaur CPUID leaves.
3748	*
3749	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3750	*
3751	* @returns Pointer to the centaur CPUID leaves (read-only).
3752	* @param pVM The VM handle.
3753	* @remark Intended for PATM.
3754	*/
3755	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3756	{
3757	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3758	}
3759
3760
3761	/**
3762	* Gets a pointer to the default CPUID leaf.
3763	*
3764	* @returns Pointer to the default CPUID leaf (read-only).
3765	* @param pVM The VM handle.
3766	* @remark Intended for PATM.
3767	*/
3768	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3769	{
3770	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3771	}
3772
3773
3774	/**
3775	* Transforms the guest CPU state to raw-ring mode.
3776	*
3777	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3778	*
3779	* @returns VBox status. (recompiler failure)
3780	* @param pVCpu The VMCPU handle.
3781	* @param pCtxCore The context core (for trap usage).
3782	* @see @ref pg_raw
3783	*/
3784	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3785	{
3786	PVM pVM = pVCpu->CTX_SUFF(pVM);
3787
3788	Assert(!pVCpu->cpum.s.fRawEntered);
3789	Assert(!pVCpu->cpum.s.fRemEntered);
3790	if (!pCtxCore)
3791	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3792
3793	/*
3794	* Are we in Ring-0?
3795	*/
3796	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3797	&& !pCtxCore->eflags.Bits.u1VM)
3798	{
3799	/*
3800	* Enter execution mode.
3801	*/
3802	PATMRawEnter(pVM, pCtxCore);
3803
3804	/*
3805	* Set CPL to Ring-1.
3806	*/
3807	pCtxCore->ss \|= 1;
3808	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3809	pCtxCore->cs \|= 1;
3810	}
3811	else
3812	{
3813	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3814	("ring-1 code not supported\n"));
3815	/*
3816	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3817	*/
3818	PATMRawEnter(pVM, pCtxCore);
3819	}
3820
3821	/*
3822	* Invalidate the hidden registers.
3823	*/
3824	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3825
3826	/*
3827	* Assert sanity.
3828	*/
3829	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3830	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3831	\|\| pCtxCore->eflags.Bits.u1VM,
3832	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3833	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3834
3835	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3836
3837	pVCpu->cpum.s.fRawEntered = true;
3838	return VINF_SUCCESS;
3839	}
3840
3841
3842	/**
3843	* Transforms the guest CPU state from raw-ring mode to correct values.
3844	*
3845	* This function will change any selector registers with DPL=1 to DPL=0.
3846	*
3847	* @returns Adjusted rc.
3848	* @param pVCpu The VMCPU handle.
3849	* @param rc Raw mode return code
3850	* @param pCtxCore The context core (for trap usage).
3851	* @see @ref pg_raw
3852	*/
3853	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3854	{
3855	PVM pVM = pVCpu->CTX_SUFF(pVM);
3856
3857	/*
3858	* Don't leave if we've already left (in GC).
3859	*/
3860	Assert(pVCpu->cpum.s.fRawEntered);
3861	Assert(!pVCpu->cpum.s.fRemEntered);
3862	if (!pVCpu->cpum.s.fRawEntered)
3863	return rc;
3864	pVCpu->cpum.s.fRawEntered = false;
3865
3866	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3867	if (!pCtxCore)
3868	pCtxCore = CPUMCTX2CORE(pCtx);
3869	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3870	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3871	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3872
3873	/*
3874	* Are we executing in raw ring-1?
3875	*/
3876	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3877	&& !pCtxCore->eflags.Bits.u1VM)
3878	{
3879	/*
3880	* Leave execution mode.
3881	*/
3882	PATMRawLeave(pVM, pCtxCore, rc);
3883	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3884	/** @todo See what happens if we remove this. */
3885	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3886	pCtxCore->ds &= ~X86_SEL_RPL;
3887	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3888	pCtxCore->es &= ~X86_SEL_RPL;
3889	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3890	pCtxCore->fs &= ~X86_SEL_RPL;
3891	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3892	pCtxCore->gs &= ~X86_SEL_RPL;
3893
3894	/*
3895	* Ring-1 selector => Ring-0.
3896	*/
3897	pCtxCore->ss &= ~X86_SEL_RPL;
3898	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3899	pCtxCore->cs &= ~X86_SEL_RPL;
3900	}
3901	else
3902	{
3903	/*
3904	* PATM is taking care of the IOPL and IF flags for us.
3905	*/
3906	PATMRawLeave(pVM, pCtxCore, rc);
3907	if (!pCtxCore->eflags.Bits.u1VM)
3908	{
3909	/** @todo See what happens if we remove this. */
3910	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3911	pCtxCore->ds &= ~X86_SEL_RPL;
3912	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3913	pCtxCore->es &= ~X86_SEL_RPL;
3914	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3915	pCtxCore->fs &= ~X86_SEL_RPL;
3916	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3917	pCtxCore->gs &= ~X86_SEL_RPL;
3918	}
3919	}
3920
3921	return rc;
3922	}
3923
3924
3925	/**
3926	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3927	*
3928	* Only REM should ever call this function!
3929	*
3930	* @returns The changed flags.
3931	* @param pVCpu The VMCPU handle.
3932	* @param puCpl Where to return the current privilege level (CPL).
3933	*/
3934	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3935	{
3936	Assert(!pVCpu->cpum.s.fRawEntered);
3937	Assert(!pVCpu->cpum.s.fRemEntered);
3938
3939	/*
3940	* Get the CPL first.
3941	*/
3942	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3943
3944	/*
3945	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3946	*/
3947	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3948	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3949
3950	/** @todo change the switcher to use the fChanged flags. */
3951	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3952	{
3953	fFlags \|= CPUM_CHANGED_FPU_REM;
3954	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3955	}
3956
3957	pVCpu->cpum.s.fRemEntered = true;
3958	return fFlags;
3959	}
3960
3961
3962	/**
3963	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3964	*
3965	* @param pVCpu The virtual CPU handle.
3966	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3967	* registers.
3968	*/
3969	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3970	{
3971	Assert(!pVCpu->cpum.s.fRawEntered);
3972	Assert(pVCpu->cpum.s.fRemEntered);
3973
3974	if (fNoOutOfSyncSels)
3975	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3976	else
3977	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3978
3979	pVCpu->cpum.s.fRemEntered = false;
3980	}
3981

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 35368

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