VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 49828

Last change on this file since 49828 was 49538, checked in by vboxsync, 11 years ago

VMM/CPUM: typo
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1/* $Id: CPUM.cpp 49538 2013-11-18 16:21:40Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/assert.h>
58#include <iprt/asm-amd64-x86.h>
59#include <iprt/string.h>
60#include <iprt/mp.h>
61#include <iprt/cpuset.h>
62#include "internal/pgm.h"
63
64
65/*******************************************************************************
66* Defined Constants And Macros *
67*******************************************************************************/
68/** The current saved state version. */
69#define CPUM_SAVED_STATE_VERSION 14
70/** The current saved state version before using SSMR3PutStruct. */
71#define CPUM_SAVED_STATE_VERSION_MEM 13
72/** The saved state version before introducing the MSR size field. */
73#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
74/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
75 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
76#define CPUM_SAVED_STATE_VERSION_VER3_2 11
77/** The saved state version of 3.0 and 3.1 trunk before the teleportation
78 * changes. */
79#define CPUM_SAVED_STATE_VERSION_VER3_0 10
80/** The saved state version for the 2.1 trunk before the MSR changes. */
81#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
82/** The saved state version of 2.0, used for backwards compatibility. */
83#define CPUM_SAVED_STATE_VERSION_VER2_0 8
84/** The saved state version of 1.6, used for backwards compatibility. */
85#define CPUM_SAVED_STATE_VERSION_VER1_6 6
86
87
88/**
89 * This was used in the saved state up to the early life of version 14.
90 *
91 * It indicates that we may have some out-of-sync hidden segement registers.
92 * It is only relevant for raw-mode.
93 */
94#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
95
96
97/*******************************************************************************
98* Structures and Typedefs *
99*******************************************************************************/
100
101/**
102 * What kind of cpu info dump to perform.
103 */
104typedef enum CPUMDUMPTYPE
105{
106 CPUMDUMPTYPE_TERSE,
107 CPUMDUMPTYPE_DEFAULT,
108 CPUMDUMPTYPE_VERBOSE
109} CPUMDUMPTYPE;
110/** Pointer to a cpu info dump type. */
111typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
112
113
114/*******************************************************************************
115* Internal Functions *
116*******************************************************************************/
117static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
118static int cpumR3CpuIdInit(PVM pVM);
119static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
130
131
132/*******************************************************************************
133* Global Variables *
134*******************************************************************************/
135/** Saved state field descriptors for CPUMCTX. */
136static const SSMFIELD g_aCpumCtxFields[] =
137{
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
173 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
174 SSMFIELD_ENTRY( CPUMCTX, rdi),
175 SSMFIELD_ENTRY( CPUMCTX, rsi),
176 SSMFIELD_ENTRY( CPUMCTX, rbp),
177 SSMFIELD_ENTRY( CPUMCTX, rax),
178 SSMFIELD_ENTRY( CPUMCTX, rbx),
179 SSMFIELD_ENTRY( CPUMCTX, rdx),
180 SSMFIELD_ENTRY( CPUMCTX, rcx),
181 SSMFIELD_ENTRY( CPUMCTX, rsp),
182 SSMFIELD_ENTRY( CPUMCTX, rflags),
183 SSMFIELD_ENTRY( CPUMCTX, rip),
184 SSMFIELD_ENTRY( CPUMCTX, r8),
185 SSMFIELD_ENTRY( CPUMCTX, r9),
186 SSMFIELD_ENTRY( CPUMCTX, r10),
187 SSMFIELD_ENTRY( CPUMCTX, r11),
188 SSMFIELD_ENTRY( CPUMCTX, r12),
189 SSMFIELD_ENTRY( CPUMCTX, r13),
190 SSMFIELD_ENTRY( CPUMCTX, r14),
191 SSMFIELD_ENTRY( CPUMCTX, r15),
192 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
193 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
194 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
195 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
196 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
197 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
198 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, cr0),
229 SSMFIELD_ENTRY( CPUMCTX, cr2),
230 SSMFIELD_ENTRY( CPUMCTX, cr3),
231 SSMFIELD_ENTRY( CPUMCTX, cr4),
232 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
237 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
239 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
241 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
244 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
245 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
246 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
248 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
250 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
251 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
252 /* msrApicBase is not included here, it resides in the APIC device state. */
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
265 SSMFIELD_ENTRY_TERM()
266};
267
268/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
269 * registeres changed. */
270static const SSMFIELD g_aCpumCtxFieldsMem[] =
271{
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
306 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
307 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
308 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
309 SSMFIELD_ENTRY( CPUMCTX, rdi),
310 SSMFIELD_ENTRY( CPUMCTX, rsi),
311 SSMFIELD_ENTRY( CPUMCTX, rbp),
312 SSMFIELD_ENTRY( CPUMCTX, rax),
313 SSMFIELD_ENTRY( CPUMCTX, rbx),
314 SSMFIELD_ENTRY( CPUMCTX, rdx),
315 SSMFIELD_ENTRY( CPUMCTX, rcx),
316 SSMFIELD_ENTRY( CPUMCTX, rsp),
317 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
318 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
319 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
321 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
323 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
325 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
327 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
328 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
329 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
330 SSMFIELD_ENTRY( CPUMCTX, rflags),
331 SSMFIELD_ENTRY( CPUMCTX, rip),
332 SSMFIELD_ENTRY( CPUMCTX, r8),
333 SSMFIELD_ENTRY( CPUMCTX, r9),
334 SSMFIELD_ENTRY( CPUMCTX, r10),
335 SSMFIELD_ENTRY( CPUMCTX, r11),
336 SSMFIELD_ENTRY( CPUMCTX, r12),
337 SSMFIELD_ENTRY( CPUMCTX, r13),
338 SSMFIELD_ENTRY( CPUMCTX, r14),
339 SSMFIELD_ENTRY( CPUMCTX, r15),
340 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
356 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
357 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
358 SSMFIELD_ENTRY( CPUMCTX, cr0),
359 SSMFIELD_ENTRY( CPUMCTX, cr2),
360 SSMFIELD_ENTRY( CPUMCTX, cr3),
361 SSMFIELD_ENTRY( CPUMCTX, cr4),
362 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
364 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
365 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
366 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
367 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
368 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
369 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
370 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
371 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
372 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
374 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
375 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
377 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
379 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
381 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
382 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
383 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
384 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
386 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
387 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
388 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
389 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
393 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
394 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
395 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
396 SSMFIELD_ENTRY_TERM()
397};
398
399/** Saved state field descriptors for CPUMCTX_VER1_6. */
400static const SSMFIELD g_aCpumCtxFieldsV16[] =
401{
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
436 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
437 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
438 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
439 SSMFIELD_ENTRY( CPUMCTX, rdi),
440 SSMFIELD_ENTRY( CPUMCTX, rsi),
441 SSMFIELD_ENTRY( CPUMCTX, rbp),
442 SSMFIELD_ENTRY( CPUMCTX, rax),
443 SSMFIELD_ENTRY( CPUMCTX, rbx),
444 SSMFIELD_ENTRY( CPUMCTX, rdx),
445 SSMFIELD_ENTRY( CPUMCTX, rcx),
446 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
447 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
448 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
450 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
451 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
453 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
455 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
457 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
458 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
459 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
460 SSMFIELD_ENTRY( CPUMCTX, rflags),
461 SSMFIELD_ENTRY( CPUMCTX, rip),
462 SSMFIELD_ENTRY( CPUMCTX, r8),
463 SSMFIELD_ENTRY( CPUMCTX, r9),
464 SSMFIELD_ENTRY( CPUMCTX, r10),
465 SSMFIELD_ENTRY( CPUMCTX, r11),
466 SSMFIELD_ENTRY( CPUMCTX, r12),
467 SSMFIELD_ENTRY( CPUMCTX, r13),
468 SSMFIELD_ENTRY( CPUMCTX, r14),
469 SSMFIELD_ENTRY( CPUMCTX, r15),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
485 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
486 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
487 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
488 SSMFIELD_ENTRY( CPUMCTX, cr0),
489 SSMFIELD_ENTRY( CPUMCTX, cr2),
490 SSMFIELD_ENTRY( CPUMCTX, cr3),
491 SSMFIELD_ENTRY( CPUMCTX, cr4),
492 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
493 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
495 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
496 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
497 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
498 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
499 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
500 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
501 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
502 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
503 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
504 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
505 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
506 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
507 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
509 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
510 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
512 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
514 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
515 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
516 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
517 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
519 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
520 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
521 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
522 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
523 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
524 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
528 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
531 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
532 SSMFIELD_ENTRY_TERM()
533};
534
535
536/**
537 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
538 *
539 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error
540 * pointers (last instruction pointer, last data pointer, last opcode)
541 * except when the ES bit (Exception Summary) in x87 FSW (FPU Status
542 * Word) is set. Thus if we don't clear these registers there is
543 * potential, local FPU leakage from a process using the FPU to
544 * another.
545 *
546 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
547 *
548 * @param pVM Pointer to the VM.
549 */
550static void cpumR3CheckLeakyFpu(PVM pVM)
551{
552 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
553 uint32_t const u32Family = u32CpuVersion >> 8;
554 if ( u32Family >= 6 /* K7 and higher */
555 && ASMIsAmdCpu())
556 {
557 uint32_t cExt = ASMCpuId_EAX(0x80000000);
558 if (ASMIsValidExtRange(cExt))
559 {
560 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
561 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
562 {
563 for (VMCPUID i = 0; i < pVM->cCpus; i++)
564 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
565 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
566 }
567 }
568 }
569}
570
571
572/**
573 * Initializes the CPUM.
574 *
575 * @returns VBox status code.
576 * @param pVM Pointer to the VM.
577 */
578VMMR3DECL(int) CPUMR3Init(PVM pVM)
579{
580 LogFlow(("CPUMR3Init\n"));
581
582 /*
583 * Assert alignment and sizes.
584 */
585 AssertCompileMemberAlignment(VM, cpum.s, 32);
586 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
587 AssertCompileSizeAlignment(CPUMCTX, 64);
588 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
589 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
590 AssertCompileMemberAlignment(VM, cpum, 64);
591 AssertCompileMemberAlignment(VM, aCpus, 64);
592 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
593 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
594
595 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
596 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
597 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
598
599 /* Calculate the offset from CPUMCPU to CPUM. */
600 for (VMCPUID i = 0; i < pVM->cCpus; i++)
601 {
602 PVMCPU pVCpu = &pVM->aCpus[i];
603
604 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
605 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
606 }
607
608 /*
609 * Check that the CPU supports the minimum features we require.
610 */
611 if (!ASMHasCpuId())
612 {
613 Log(("The CPU doesn't support CPUID!\n"));
614 return VERR_UNSUPPORTED_CPU;
615 }
616 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
617 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
618
619 /* Setup the CR4 AND and OR masks used in the switcher */
620 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
621 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
622 {
623 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
624 /* No FXSAVE implies no SSE */
625 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
626 pVM->cpum.s.CR4.OrMask = 0;
627 }
628 else
629 {
630 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
631 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
632 }
633
634 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
635 {
636 Log(("The CPU doesn't support MMX!\n"));
637 return VERR_UNSUPPORTED_CPU;
638 }
639 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
640 {
641 Log(("The CPU doesn't support TSC!\n"));
642 return VERR_UNSUPPORTED_CPU;
643 }
644 /* Bogus on AMD? */
645 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
646 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
647
648 /*
649 * Detect the host CPU vendor.
650 * (The guest CPU vendor is re-detected later on.)
651 */
652 uint32_t uEAX, uEBX, uECX, uEDX;
653 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
654 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
655 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
656
657 /*
658 * Setup hypervisor startup values.
659 */
660
661 /*
662 * Register saved state data item.
663 */
664 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
665 NULL, cpumR3LiveExec, NULL,
666 NULL, cpumR3SaveExec, NULL,
667 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
668 if (RT_FAILURE(rc))
669 return rc;
670
671 /*
672 * Register info handlers and registers with the debugger facility.
673 */
674 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
675 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
676 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
677 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
678 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
679 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
680
681 rc = cpumR3DbgInit(pVM);
682 if (RT_FAILURE(rc))
683 return rc;
684
685 /*
686 * Check if we need to workaround partial/leaky FPU handling.
687 */
688 cpumR3CheckLeakyFpu(pVM);
689
690 /*
691 * Initialize the Guest CPUID state.
692 */
693 rc = cpumR3CpuIdInit(pVM);
694 if (RT_FAILURE(rc))
695 return rc;
696 CPUMR3Reset(pVM);
697 return VINF_SUCCESS;
698}
699
700
701/**
702 * Detect the CPU vendor give n the
703 *
704 * @returns The vendor.
705 * @param uEAX EAX from CPUID(0).
706 * @param uEBX EBX from CPUID(0).
707 * @param uECX ECX from CPUID(0).
708 * @param uEDX EDX from CPUID(0).
709 */
710static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
711{
712 if (ASMIsValidStdRange(uEAX))
713 {
714 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
715 return CPUMCPUVENDOR_AMD;
716
717 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
718 return CPUMCPUVENDOR_INTEL;
719
720 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
721 return CPUMCPUVENDOR_VIA;
722
723 /** @todo detect the other buggers... */
724 }
725
726 return CPUMCPUVENDOR_UNKNOWN;
727}
728
729
730/**
731 * Fetches overrides for a CPUID leaf.
732 *
733 * @returns VBox status code.
734 * @param pLeaf The leaf to load the overrides into.
735 * @param pCfgNode The CFGM node containing the overrides
736 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
737 * @param iLeaf The CPUID leaf number.
738 */
739static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
740{
741 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
742 if (pLeafNode)
743 {
744 uint32_t u32;
745 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
746 if (RT_SUCCESS(rc))
747 pLeaf->eax = u32;
748 else
749 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
750
751 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
752 if (RT_SUCCESS(rc))
753 pLeaf->ebx = u32;
754 else
755 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
756
757 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
758 if (RT_SUCCESS(rc))
759 pLeaf->ecx = u32;
760 else
761 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
762
763 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
764 if (RT_SUCCESS(rc))
765 pLeaf->edx = u32;
766 else
767 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
768
769 }
770 return VINF_SUCCESS;
771}
772
773
774/**
775 * Load the overrides for a set of CPUID leaves.
776 *
777 * @returns VBox status code.
778 * @param paLeaves The leaf array.
779 * @param cLeaves The number of leaves.
780 * @param uStart The start leaf number.
781 * @param pCfgNode The CFGM node containing the overrides
782 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
783 */
784static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
785{
786 for (uint32_t i = 0; i < cLeaves; i++)
787 {
788 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
789 if (RT_FAILURE(rc))
790 return rc;
791 }
792
793 return VINF_SUCCESS;
794}
795
796/**
797 * Init a set of host CPUID leaves.
798 *
799 * @returns VBox status code.
800 * @param paLeaves The leaf array.
801 * @param cLeaves The number of leaves.
802 * @param uStart The start leaf number.
803 * @param pCfgNode The /CPUM/HostCPUID/ node.
804 */
805static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
806{
807 /* Using the ECX variant for all of them can't hurt... */
808 for (uint32_t i = 0; i < cLeaves; i++)
809 ASMCpuIdExSlow(uStart + i, 0, 0, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
810
811 /* Load CPUID leaf override; we currently don't care if the user
812 specifies features the host CPU doesn't support. */
813 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
814}
815
816
817/**
818 * Initializes the emulated CPU's cpuid information.
819 *
820 * @returns VBox status code.
821 * @param pVM Pointer to the VM.
822 */
823static int cpumR3CpuIdInit(PVM pVM)
824{
825 PCPUM pCPUM = &pVM->cpum.s;
826 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
827 uint32_t i;
828 int rc;
829
830#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
831 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
832 { \
833 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
834 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
835 }
836#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
837 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
838 { \
839 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
840 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
841 }
842
843 /*
844 * Read the configuration.
845 */
846 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
847 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
848 * completely overridden by VirtualBox custom strings. Some
849 * CPUID information is withheld, like the cache info. */
850 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
851 AssertRCReturn(rc, rc);
852
853 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
854 * When non-zero CPUID features that could cause portability issues will be
855 * stripped. The higher the value the more features gets stripped. Higher
856 * values should only be used when older CPUs are involved since it may
857 * harm performance and maybe also cause problems with specific guests. */
858 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
859 AssertRCReturn(rc, rc);
860
861 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
862
863 /*
864 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
865 * been overridden).
866 */
867 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
868 * Overrides the host CPUID leaf values used for calculating the guest CPUID
869 * leaves. This can be used to preserve the CPUID values when moving a VM to a
870 * different machine. Another use is restricting (or extending) the feature set
871 * exposed to the guest. */
872 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
873 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
874 AssertRCReturn(rc, rc);
875 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
876 AssertRCReturn(rc, rc);
877 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
878 AssertRCReturn(rc, rc);
879
880 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
881 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
882
883 /*
884 * Determine the default leaf.
885 *
886 * Intel returns values of the highest standard function, while AMD
887 * returns zeros. VIA on the other hand seems to returning nothing or
888 * perhaps some random garbage, we don't try to duplicate this behavior.
889 */
890 ASMCpuIdExSlow(pCPUM->aGuestCpuIdStd[0].eax + 10, 0, 0, 0, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
891 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
892 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
893
894 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
895 * Expose CMPXCHG16B to the guest if supported by the host.
896 */
897 bool fCmpXchg16b;
898 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
899
900 /** @cfgm{/CPUM/MONITOR, boolean, true}
901 * Expose MONITOR/MWAIT instructions to the guest.
902 */
903 bool fMonitor;
904 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true); AssertRCReturn(rc, rc);
905
906 /* Cpuid 1 & 0x80000001:
907 * Only report features we can support.
908 *
909 * Note! When enabling new features the Synthetic CPU and Portable CPUID
910 * options may require adjusting (i.e. stripping what was enabled).
911 */
912 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
913 | X86_CPUID_FEATURE_EDX_VME
914 | X86_CPUID_FEATURE_EDX_DE
915 | X86_CPUID_FEATURE_EDX_PSE
916 | X86_CPUID_FEATURE_EDX_TSC
917 | X86_CPUID_FEATURE_EDX_MSR
918 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
919 | X86_CPUID_FEATURE_EDX_MCE
920 | X86_CPUID_FEATURE_EDX_CX8
921 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
922 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
923 //| X86_CPUID_FEATURE_EDX_SEP
924 | X86_CPUID_FEATURE_EDX_MTRR
925 | X86_CPUID_FEATURE_EDX_PGE
926 | X86_CPUID_FEATURE_EDX_MCA
927 | X86_CPUID_FEATURE_EDX_CMOV
928 | X86_CPUID_FEATURE_EDX_PAT
929 | X86_CPUID_FEATURE_EDX_PSE36
930 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
931 | X86_CPUID_FEATURE_EDX_CLFSH
932 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
933 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
934 | X86_CPUID_FEATURE_EDX_MMX
935 | X86_CPUID_FEATURE_EDX_FXSR
936 | X86_CPUID_FEATURE_EDX_SSE
937 | X86_CPUID_FEATURE_EDX_SSE2
938 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
939 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
940 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
941 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
942 | 0;
943 pCPUM->aGuestCpuIdStd[1].ecx &= 0
944 | X86_CPUID_FEATURE_ECX_SSE3
945 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
946 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
947 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
948 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
949 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
950 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
951 | X86_CPUID_FEATURE_ECX_SSSE3
952 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
953 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
954 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
955 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
956 /* ECX Bit 21 - x2APIC support - not yet. */
957 // | X86_CPUID_FEATURE_ECX_X2APIC
958 /* ECX Bit 23 - POPCNT instruction. */
959 //| X86_CPUID_FEATURE_ECX_POPCNT
960 | 0;
961 if (pCPUM->u8PortableCpuIdLevel > 0)
962 {
963 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
964 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
965 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
966 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
967 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
968 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
969 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
970 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
971
972 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
973 | X86_CPUID_FEATURE_EDX_PSN
974 | X86_CPUID_FEATURE_EDX_DS
975 | X86_CPUID_FEATURE_EDX_ACPI
976 | X86_CPUID_FEATURE_EDX_SS
977 | X86_CPUID_FEATURE_EDX_TM
978 | X86_CPUID_FEATURE_EDX_PBE
979 )));
980 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
981 | X86_CPUID_FEATURE_ECX_DTES64
982 | X86_CPUID_FEATURE_ECX_CPLDS
983 | X86_CPUID_FEATURE_ECX_VMX
984 | X86_CPUID_FEATURE_ECX_SMX
985 | X86_CPUID_FEATURE_ECX_EST
986 | X86_CPUID_FEATURE_ECX_TM2
987 | X86_CPUID_FEATURE_ECX_CNTXID
988 | X86_CPUID_FEATURE_ECX_FMA
989 | X86_CPUID_FEATURE_ECX_CX16
990 | X86_CPUID_FEATURE_ECX_TPRUPDATE
991 | X86_CPUID_FEATURE_ECX_PDCM
992 | X86_CPUID_FEATURE_ECX_DCA
993 | X86_CPUID_FEATURE_ECX_MOVBE
994 | X86_CPUID_FEATURE_ECX_AES
995 | X86_CPUID_FEATURE_ECX_POPCNT
996 | X86_CPUID_FEATURE_ECX_XSAVE
997 | X86_CPUID_FEATURE_ECX_OSXSAVE
998 | X86_CPUID_FEATURE_ECX_AVX
999 )));
1000 }
1001
1002 /* Cpuid 0x80000001:
1003 * Only report features we can support.
1004 *
1005 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1006 * options may require adjusting (i.e. stripping what was enabled).
1007 *
1008 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
1009 */
1010 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1011 | X86_CPUID_AMD_FEATURE_EDX_VME
1012 | X86_CPUID_AMD_FEATURE_EDX_DE
1013 | X86_CPUID_AMD_FEATURE_EDX_PSE
1014 | X86_CPUID_AMD_FEATURE_EDX_TSC
1015 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1016 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
1017 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1018 | X86_CPUID_AMD_FEATURE_EDX_CX8
1019 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1020 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1021 //| X86_CPUID_EXT_FEATURE_EDX_SEP
1022 | X86_CPUID_AMD_FEATURE_EDX_MTRR
1023 | X86_CPUID_AMD_FEATURE_EDX_PGE
1024 | X86_CPUID_AMD_FEATURE_EDX_MCA
1025 | X86_CPUID_AMD_FEATURE_EDX_CMOV
1026 | X86_CPUID_AMD_FEATURE_EDX_PAT
1027 | X86_CPUID_AMD_FEATURE_EDX_PSE36
1028 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
1029 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1030 | X86_CPUID_AMD_FEATURE_EDX_MMX
1031 | X86_CPUID_AMD_FEATURE_EDX_FXSR
1032 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
1033 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1034 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1035 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1036 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1037 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
1038 | 0;
1039 pCPUM->aGuestCpuIdExt[1].ecx &= 0
1040 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1041 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
1042 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
1043 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1044 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1045 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1046 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1047 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1048 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1049 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1050 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1051 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1052 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1053 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1054 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1055 | 0;
1056 if (pCPUM->u8PortableCpuIdLevel > 0)
1057 {
1058 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1059 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1060 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1061 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1062 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1063 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1064 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1065
1066 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1067 | X86_CPUID_AMD_FEATURE_ECX_SVM
1068 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1069 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1070 | X86_CPUID_AMD_FEATURE_ECX_ABM
1071 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1072 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1073 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1074 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1075 | X86_CPUID_AMD_FEATURE_ECX_IBS
1076 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1077 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1078 | X86_CPUID_AMD_FEATURE_ECX_WDT
1079 | UINT32_C(0xffffc000)
1080 )));
1081 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1082 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1083 | RT_BIT(18)
1084 | RT_BIT(19)
1085 | RT_BIT(21)
1086 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1087 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1088 | RT_BIT(28)
1089 )));
1090 }
1091
1092 /*
1093 * Apply the Synthetic CPU modifications. (TODO: move this up)
1094 */
1095 if (pCPUM->fSyntheticCpu)
1096 {
1097 static const char s_szVendor[13] = "VirtualBox ";
1098 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1099
1100 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1101
1102 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1103 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1104
1105 /* 0: Vendor */
1106 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1107 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1108 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1109
1110 /* 1.eax: Version information. family : model : stepping */
1111 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1112
1113 /* Leaves 2 - 4 are Intel only - zero them out */
1114 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1115 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1116 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1117
1118 /* Leaf 5 = monitor/mwait */
1119
1120 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1121 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1122 /* AMD only - set to zero. */
1123 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1124
1125 /* 0x800000001: shared feature bits are set dynamically. */
1126 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1127
1128 /* 0x800000002-4: Processor Name String Identifier. */
1129 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1130 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1131 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1132 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1133 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1134 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1135 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1136 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1137 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1138 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1139 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1140 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1141
1142 /* 0x800000005-7 - reserved -> zero */
1143 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1144 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1145 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1146
1147 /* 0x800000008: only the max virtual and physical address size. */
1148 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1149 }
1150
1151 /*
1152 * Hide HTT, multicode, SMP, whatever.
1153 * (APIC-ID := 0 and #LogCpus := 0)
1154 */
1155 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1156#ifdef VBOX_WITH_MULTI_CORE
1157 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1158 && pVM->cCpus > 1)
1159 {
1160 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1161 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1162 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1163 }
1164#endif
1165
1166 /* Cpuid 2:
1167 * Intel: Cache and TLB information
1168 * AMD: Reserved
1169 * VIA: Reserved
1170 * Safe to expose; restrict the number of calls to 1 for the portable case.
1171 */
1172 if ( pCPUM->u8PortableCpuIdLevel > 0
1173 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1174 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1175 {
1176 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1177 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1178 }
1179
1180 /* Cpuid 3:
1181 * Intel: EAX, EBX - reserved (transmeta uses these)
1182 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1183 * AMD: Reserved
1184 * VIA: Reserved
1185 * Safe to expose
1186 */
1187 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1188 {
1189 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1190 if (pCPUM->u8PortableCpuIdLevel > 0)
1191 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1192 }
1193
1194 /* Cpuid 4:
1195 * Intel: Deterministic Cache Parameters Leaf
1196 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1197 * AMD: Reserved
1198 * VIA: Reserved
1199 * Safe to expose, except for EAX:
1200 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1201 * Bits 31-26: Maximum number of processor cores in this physical package**
1202 * Note: These SMP values are constant regardless of ECX
1203 */
1204 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1205 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1206#ifdef VBOX_WITH_MULTI_CORE
1207 if ( pVM->cCpus > 1
1208 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1209 {
1210 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1211 /* One logical processor with possibly multiple cores. */
1212 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1213 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1214 }
1215#endif
1216
1217 /* Cpuid 5: Monitor/mwait Leaf
1218 * Intel: ECX, EDX - reserved
1219 * EAX, EBX - Smallest and largest monitor line size
1220 * AMD: EDX - reserved
1221 * EAX, EBX - Smallest and largest monitor line size
1222 * ECX - extensions (ignored for now)
1223 * VIA: Reserved
1224 * Safe to expose
1225 */
1226 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1227 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1228
1229 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1230 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1231 * Expose MWAIT extended features to the guest. For now we expose
1232 * just MWAIT break on interrupt feature (bit 1).
1233 */
1234 bool fMWaitExtensions;
1235 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1236 if (fMWaitExtensions)
1237 {
1238 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1239 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
1240 it shall be part of our power management virtualization model */
1241#if 0
1242 /* MWAIT sub C-states */
1243 pCPUM->aGuestCpuIdStd[5].edx =
1244 (0 << 0) /* 0 in C0 */ |
1245 (2 << 4) /* 2 in C1 */ |
1246 (2 << 8) /* 2 in C2 */ |
1247 (2 << 12) /* 2 in C3 */ |
1248 (0 << 16) /* 0 in C4 */
1249 ;
1250#endif
1251 }
1252 else
1253 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1254
1255 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1256 * Safe to pass on to the guest.
1257 *
1258 * Intel: 0x800000005 reserved
1259 * 0x800000006 L2 cache information
1260 * AMD: 0x800000005 L1 cache information
1261 * 0x800000006 L2/L3 cache information
1262 * VIA: 0x800000005 TLB and L1 cache information
1263 * 0x800000006 L2 cache information
1264 */
1265
1266 /* Cpuid 0x800000007:
1267 * Intel: Reserved
1268 * AMD: EAX, EBX, ECX - reserved
1269 * EDX: Advanced Power Management Information
1270 * VIA: Reserved
1271 */
1272 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1273 {
1274 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1275
1276 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1277
1278 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1279 {
1280 /* Only expose the TSC invariant capability bit to the guest. */
1281 pCPUM->aGuestCpuIdExt[7].edx &= 0
1282 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1283 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1284 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1285 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1286 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1287 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1288 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1289 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1290#if 0
1291 /*
1292 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1293 * Linux kernels blindly assume that the AMD performance counters work
1294 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1295 * bit for them though.)
1296 */
1297 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1298#endif
1299 | 0;
1300 }
1301 else
1302 pCPUM->aGuestCpuIdExt[7].edx = 0;
1303 }
1304
1305 /* Cpuid 0x800000008:
1306 * Intel: EAX: Virtual/Physical address Size
1307 * EBX, ECX, EDX - reserved
1308 * AMD: EBX, EDX - reserved
1309 * EAX: Virtual/Physical/Guest address Size
1310 * ECX: Number of cores + APICIdCoreIdSize
1311 * VIA: EAX: Virtual/Physical address Size
1312 * EBX, ECX, EDX - reserved
1313 */
1314 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1315 {
1316 /* Only expose the virtual and physical address sizes to the guest. */
1317 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1318 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1319 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1320 * NC (0-7) Number of cores; 0 equals 1 core */
1321 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1322#ifdef VBOX_WITH_MULTI_CORE
1323 if ( pVM->cCpus > 1
1324 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1325 {
1326 /* Legacy method to determine the number of cores. */
1327 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1328 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1329 }
1330#endif
1331 }
1332
1333 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1334 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1335 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1336 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1337 */
1338 bool fNt4LeafLimit;
1339 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1340 if (fNt4LeafLimit && pCPUM->aGuestCpuIdStd[0].eax > 3)
1341 pCPUM->aGuestCpuIdStd[0].eax = 3;
1342
1343 /*
1344 * Limit it the number of entries and fill the remaining with the defaults.
1345 *
1346 * The limits are masking off stuff about power saving and similar, this
1347 * is perhaps a bit crudely done as there is probably some relatively harmless
1348 * info too in these leaves (like words about having a constant TSC).
1349 */
1350 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1351 pCPUM->aGuestCpuIdStd[0].eax = 5;
1352 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1353 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1354
1355 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1356 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1357 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1358 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1359 : 0;
1360 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1361 i++)
1362 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1363
1364 /*
1365 * Centaur stuff (VIA).
1366 *
1367 * The important part here (we think) is to make sure the 0xc0000000
1368 * function returns 0xc0000001. As for the features, we don't currently
1369 * let on about any of those... 0xc0000002 seems to be some
1370 * temperature/hz/++ stuff, include it as well (static).
1371 */
1372 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1373 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1374 {
1375 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1376 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1377 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1378 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1379 i++)
1380 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1381 }
1382 else
1383 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1384 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1385
1386 /*
1387 * Hypervisor identification.
1388 *
1389 * We only return minimal information, primarily ensuring that the
1390 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1391 * Currently we do not support any hypervisor-specific interface.
1392 */
1393 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1394 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1395 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1396 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1397 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1398 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1399
1400 /*
1401 * Mini CPU selection support for making Mac OS X happy.
1402 */
1403 if (pCPUM->enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1404 {
1405 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
1406 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
1407 * probably going to be a temporary hack, so don't depend on this.
1408 * The 1st byte of the value is the stepping, the 2nd byte value is the model
1409 * number and the 3rd byte value is the family, and the 4th value must be zero.
1410 */
1411 uint32_t uMaxIntelFamilyModelStep;
1412 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
1413 AssertRCReturn(rc, rc);
1414 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pCPUM->aGuestCpuIdStd[1].eax),
1415 ASMGetCpuModelIntel(pCPUM->aGuestCpuIdStd[1].eax),
1416 ASMGetCpuFamily(pCPUM->aGuestCpuIdStd[1].eax),
1417 0);
1418 if (uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1419 {
1420 uint32_t uNew = pCPUM->aGuestCpuIdStd[1].eax & UINT32_C(0xf0003000);
1421 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1422 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1423 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1424 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1425 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1426 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1427 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1428 pCPUM->aGuestCpuIdStd[1].eax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1429 pCPUM->aGuestCpuIdStd[1].eax = uNew;
1430 }
1431 }
1432
1433 /*
1434 * Load CPUID overrides from configuration.
1435 * Note: Kind of redundant now, but allows unchanged overrides
1436 */
1437 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1438 * Overrides the CPUID leaf values. */
1439 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1440 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1441 AssertRCReturn(rc, rc);
1442 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1443 AssertRCReturn(rc, rc);
1444 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1445 AssertRCReturn(rc, rc);
1446
1447 /*
1448 * Check if PAE was explicitely enabled by the user.
1449 */
1450 bool fEnable;
1451 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1452 if (fEnable)
1453 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1454
1455 /*
1456 * We don't normally enable NX for raw-mode, so give the user a chance to
1457 * force it on.
1458 */
1459 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1460 if (fEnable)
1461 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1462
1463 /*
1464 * We don't enable the Hypervisor Present bit by default, but it may
1465 * be needed by some guests.
1466 */
1467 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1468 if (fEnable)
1469 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1470
1471#undef PORTABLE_DISABLE_FEATURE_BIT
1472#undef PORTABLE_CLEAR_BITS_WHEN
1473
1474 return VINF_SUCCESS;
1475}
1476
1477
1478/**
1479 * Applies relocations to data and code managed by this
1480 * component. This function will be called at init and
1481 * whenever the VMM need to relocate it self inside the GC.
1482 *
1483 * The CPUM will update the addresses used by the switcher.
1484 *
1485 * @param pVM The VM.
1486 */
1487VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1488{
1489 LogFlow(("CPUMR3Relocate\n"));
1490
1491 /* Recheck the guest DRx values in raw-mode. */
1492 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1493 CPUMRecalcHyperDRx(&pVM->aCpus[iCpu], UINT8_MAX, false);
1494}
1495
1496
1497/**
1498 * Apply late CPUM property changes based on the fHWVirtEx setting
1499 *
1500 * @param pVM Pointer to the VM.
1501 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1502 */
1503VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1504{
1505 /*
1506 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1507 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1508 * of processors from (cpuid(4).eax >> 26) + 1.
1509 *
1510 * Note: this code is obsolete, but let's keep it here for reference.
1511 * Purpose is valid when we artificially cap the max std id to less than 4.
1512 */
1513 if (!fHWVirtExEnabled)
1514 {
1515 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1516 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1517 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1518 }
1519}
1520
1521/**
1522 * Terminates the CPUM.
1523 *
1524 * Termination means cleaning up and freeing all resources,
1525 * the VM it self is at this point powered off or suspended.
1526 *
1527 * @returns VBox status code.
1528 * @param pVM Pointer to the VM.
1529 */
1530VMMR3DECL(int) CPUMR3Term(PVM pVM)
1531{
1532#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1533 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1534 {
1535 PVMCPU pVCpu = &pVM->aCpus[i];
1536 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1537
1538 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1539 pVCpu->cpum.s.uMagic = 0;
1540 pCtx->dr[5] = 0;
1541 }
1542#else
1543 NOREF(pVM);
1544#endif
1545 return VINF_SUCCESS;
1546}
1547
1548
1549/**
1550 * Resets a virtual CPU.
1551 *
1552 * Used by CPUMR3Reset and CPU hot plugging.
1553 *
1554 * @param pVCpu Pointer to the VMCPU.
1555 */
1556VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1557{
1558 /** @todo anything different for VCPU > 0? */
1559 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1560
1561 /*
1562 * Initialize everything to ZERO first.
1563 */
1564 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1565 memset(pCtx, 0, sizeof(*pCtx));
1566 pVCpu->cpum.s.fUseFlags = fUseFlags;
1567
1568 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1569 pCtx->eip = 0x0000fff0;
1570 pCtx->edx = 0x00000600; /* P6 processor */
1571 pCtx->eflags.Bits.u1Reserved0 = 1;
1572
1573 pCtx->cs.Sel = 0xf000;
1574 pCtx->cs.ValidSel = 0xf000;
1575 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1576 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1577 pCtx->cs.u32Limit = 0x0000ffff;
1578 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1579 pCtx->cs.Attr.n.u1Present = 1;
1580 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1581
1582 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1583 pCtx->ds.u32Limit = 0x0000ffff;
1584 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1585 pCtx->ds.Attr.n.u1Present = 1;
1586 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1587
1588 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1589 pCtx->es.u32Limit = 0x0000ffff;
1590 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1591 pCtx->es.Attr.n.u1Present = 1;
1592 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1593
1594 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1595 pCtx->fs.u32Limit = 0x0000ffff;
1596 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1597 pCtx->fs.Attr.n.u1Present = 1;
1598 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1599
1600 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1601 pCtx->gs.u32Limit = 0x0000ffff;
1602 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1603 pCtx->gs.Attr.n.u1Present = 1;
1604 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1605
1606 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1607 pCtx->ss.u32Limit = 0x0000ffff;
1608 pCtx->ss.Attr.n.u1Present = 1;
1609 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1610 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1611
1612 pCtx->idtr.cbIdt = 0xffff;
1613 pCtx->gdtr.cbGdt = 0xffff;
1614
1615 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1616 pCtx->ldtr.u32Limit = 0xffff;
1617 pCtx->ldtr.Attr.n.u1Present = 1;
1618 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1619
1620 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1621 pCtx->tr.u32Limit = 0xffff;
1622 pCtx->tr.Attr.n.u1Present = 1;
1623 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1624
1625 pCtx->dr[6] = X86_DR6_INIT_VAL;
1626 pCtx->dr[7] = X86_DR7_INIT_VAL;
1627
1628 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1629 pCtx->fpu.FCW = 0x37f;
1630
1631 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1632 IA-32 Processor States Following Power-up, Reset, or INIT */
1633 pCtx->fpu.MXCSR = 0x1F80;
1634 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1635 supports all bits, since a zero value here should be read as 0xffbf. */
1636
1637 /* Init PAT MSR */
1638 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1639
1640 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1641 * The Intel docs don't mention it. */
1642 Assert(!pCtx->msrEFER);
1643
1644 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1645 * called from each EMT while we're getting called by CPUMR3Reset()
1646 * iteratively on the same thread. Fix later. */
1647#if 0
1648 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1649 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1650#endif
1651
1652
1653 /* C-state control. Guesses. */
1654 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1655
1656
1657 /*
1658 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1659 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1660 */
1661 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1662}
1663
1664
1665/**
1666 * Resets the CPU.
1667 *
1668 * @returns VINF_SUCCESS.
1669 * @param pVM Pointer to the VM.
1670 */
1671VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1672{
1673 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1674 {
1675 CPUMR3ResetCpu(&pVM->aCpus[i]);
1676
1677#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1678 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1679
1680 /* Magic marker for searching in crash dumps. */
1681 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1682 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1683 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1684#endif
1685 }
1686}
1687
1688
1689/**
1690 * Called both in pass 0 and the final pass.
1691 *
1692 * @param pVM Pointer to the VM.
1693 * @param pSSM The saved state handle.
1694 */
1695static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1696{
1697 /*
1698 * Save all the CPU ID leaves here so we can check them for compatibility
1699 * upon loading.
1700 */
1701 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1702 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1703
1704 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1705 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1706
1707 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1708 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1709
1710 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1711
1712 /*
1713 * Save a good portion of the raw CPU IDs as well as they may come in
1714 * handy when validating features for raw mode.
1715 */
1716 CPUMCPUID aRawStd[16];
1717 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1718 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1719 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1720 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1721
1722 CPUMCPUID aRawExt[32];
1723 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1724 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1725 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1726 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1727}
1728
1729
1730/**
1731 * Loads the CPU ID leaves saved by pass 0.
1732 *
1733 * @returns VBox status code.
1734 * @param pVM Pointer to the VM.
1735 * @param pSSM The saved state handle.
1736 * @param uVersion The format version.
1737 */
1738static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1739{
1740 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1741
1742 /*
1743 * Define a bunch of macros for simplifying the code.
1744 */
1745 /* Generic expression + failure message. */
1746#define CPUID_CHECK_RET(expr, fmt) \
1747 do { \
1748 if (!(expr)) \
1749 { \
1750 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1751 if (fStrictCpuIdChecks) \
1752 { \
1753 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1754 RTStrFree(pszMsg); \
1755 return rcCpuid; \
1756 } \
1757 LogRel(("CPUM: %s\n", pszMsg)); \
1758 RTStrFree(pszMsg); \
1759 } \
1760 } while (0)
1761#define CPUID_CHECK_WRN(expr, fmt) \
1762 do { \
1763 if (!(expr)) \
1764 LogRel(fmt); \
1765 } while (0)
1766
1767 /* For comparing two values and bitch if they differs. */
1768#define CPUID_CHECK2_RET(what, host, saved) \
1769 do { \
1770 if ((host) != (saved)) \
1771 { \
1772 if (fStrictCpuIdChecks) \
1773 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1774 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1775 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1776 } \
1777 } while (0)
1778#define CPUID_CHECK2_WRN(what, host, saved) \
1779 do { \
1780 if ((host) != (saved)) \
1781 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1782 } while (0)
1783
1784 /* For checking raw cpu features (raw mode). */
1785#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1786 do { \
1787 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1788 { \
1789 if (fStrictCpuIdChecks) \
1790 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1791 N_(#bit " mismatch: host=%d saved=%d"), \
1792 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1793 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1794 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1795 } \
1796 } while (0)
1797#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1798 do { \
1799 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1800 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1801 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1802 } while (0)
1803#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1804
1805 /* For checking guest features. */
1806#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1807 do { \
1808 if ( (aGuestCpuId##set [1].reg & bit) \
1809 && !(aHostRaw##set [1].reg & bit) \
1810 && !(aHostOverride##set [1].reg & bit) \
1811 && !(aGuestOverride##set [1].reg & bit) \
1812 ) \
1813 { \
1814 if (fStrictCpuIdChecks) \
1815 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1816 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1817 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1818 } \
1819 } while (0)
1820#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1821 do { \
1822 if ( (aGuestCpuId##set [1].reg & bit) \
1823 && !(aHostRaw##set [1].reg & bit) \
1824 && !(aHostOverride##set [1].reg & bit) \
1825 && !(aGuestOverride##set [1].reg & bit) \
1826 ) \
1827 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1828 } while (0)
1829#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1830 do { \
1831 if ( (aGuestCpuId##set [1].reg & bit) \
1832 && !(aHostRaw##set [1].reg & bit) \
1833 && !(aHostOverride##set [1].reg & bit) \
1834 && !(aGuestOverride##set [1].reg & bit) \
1835 ) \
1836 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1837 } while (0)
1838#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1839
1840 /* For checking guest features if AMD guest CPU. */
1841#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1842 do { \
1843 if ( (aGuestCpuId##set [1].reg & bit) \
1844 && fGuestAmd \
1845 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1846 && !(aHostOverride##set [1].reg & bit) \
1847 && !(aGuestOverride##set [1].reg & bit) \
1848 ) \
1849 { \
1850 if (fStrictCpuIdChecks) \
1851 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1852 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1853 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1854 } \
1855 } while (0)
1856#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1857 do { \
1858 if ( (aGuestCpuId##set [1].reg & bit) \
1859 && fGuestAmd \
1860 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1861 && !(aHostOverride##set [1].reg & bit) \
1862 && !(aGuestOverride##set [1].reg & bit) \
1863 ) \
1864 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1865 } while (0)
1866#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1867 do { \
1868 if ( (aGuestCpuId##set [1].reg & bit) \
1869 && fGuestAmd \
1870 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1871 && !(aHostOverride##set [1].reg & bit) \
1872 && !(aGuestOverride##set [1].reg & bit) \
1873 ) \
1874 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1875 } while (0)
1876#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1877
1878 /* For checking AMD features which have a corresponding bit in the standard
1879 range. (Intel defines very few bits in the extended feature sets.) */
1880#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1881 do { \
1882 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1883 && !(fHostAmd \
1884 ? aHostRawExt[1].reg & (ExtBit) \
1885 : aHostRawStd[1].reg & (StdBit)) \
1886 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1887 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1888 ) \
1889 { \
1890 if (fStrictCpuIdChecks) \
1891 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1892 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1893 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1894 } \
1895 } while (0)
1896#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1897 do { \
1898 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1899 && !(fHostAmd \
1900 ? aHostRawExt[1].reg & (ExtBit) \
1901 : aHostRawStd[1].reg & (StdBit)) \
1902 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1903 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1904 ) \
1905 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1906 } while (0)
1907#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1908 do { \
1909 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1910 && !(fHostAmd \
1911 ? aHostRawExt[1].reg & (ExtBit) \
1912 : aHostRawStd[1].reg & (StdBit)) \
1913 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1914 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1915 ) \
1916 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1917 } while (0)
1918#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1919
1920 /*
1921 * Load them into stack buffers first.
1922 */
1923 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1924 uint32_t cGuestCpuIdStd;
1925 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1926 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1927 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1928 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1929
1930 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1931 uint32_t cGuestCpuIdExt;
1932 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1933 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1934 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1935 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1936
1937 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1938 uint32_t cGuestCpuIdCentaur;
1939 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1940 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1941 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1942 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1943
1944 CPUMCPUID GuestCpuIdDef;
1945 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1946 AssertRCReturn(rc, rc);
1947
1948 CPUMCPUID aRawStd[16];
1949 uint32_t cRawStd;
1950 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1951 if (cRawStd > RT_ELEMENTS(aRawStd))
1952 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1953 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1954
1955 CPUMCPUID aRawExt[32];
1956 uint32_t cRawExt;
1957 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1958 if (cRawExt > RT_ELEMENTS(aRawExt))
1959 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1960 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1961 AssertRCReturn(rc, rc);
1962
1963 /*
1964 * Note that we support restoring less than the current amount of standard
1965 * leaves because we've been allowed more is newer version of VBox.
1966 *
1967 * So, pad new entries with the default.
1968 */
1969 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1970 aGuestCpuIdStd[i] = GuestCpuIdDef;
1971
1972 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1973 aGuestCpuIdExt[i] = GuestCpuIdDef;
1974
1975 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1976 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1977
1978 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1979 ASMCpuIdExSlow(i, 0, 0, 0, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1980
1981 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1982 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0, &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1983
1984 /*
1985 * Get the raw CPU IDs for the current host.
1986 */
1987 CPUMCPUID aHostRawStd[16];
1988 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1989 ASMCpuIdExSlow(i, 0, 0, 0, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1990
1991 CPUMCPUID aHostRawExt[32];
1992 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1993 ASMCpuIdExSlow(i | UINT32_C(0x80000000), 0, 0, 0,
1994 &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1995
1996 /*
1997 * Get the host and guest overrides so we don't reject the state because
1998 * some feature was enabled thru these interfaces.
1999 * Note! We currently only need the feature leaves, so skip rest.
2000 */
2001 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
2002 CPUMCPUID aGuestOverrideStd[2];
2003 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
2004 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
2005
2006 CPUMCPUID aGuestOverrideExt[2];
2007 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
2008 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
2009
2010 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
2011 CPUMCPUID aHostOverrideStd[2];
2012 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
2013 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
2014
2015 CPUMCPUID aHostOverrideExt[2];
2016 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
2017 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
2018
2019 /*
2020 * This can be skipped.
2021 */
2022 bool fStrictCpuIdChecks;
2023 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
2024
2025
2026
2027 /*
2028 * For raw-mode we'll require that the CPUs are very similar since we don't
2029 * intercept CPUID instructions for user mode applications.
2030 */
2031 if (!HMIsEnabled(pVM))
2032 {
2033 /* CPUID(0) */
2034 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
2035 && aHostRawStd[0].ecx == aRawStd[0].ecx
2036 && aHostRawStd[0].edx == aRawStd[0].edx,
2037 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2038 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
2039 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
2040 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
2041 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
2042 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2043
2044 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
2045
2046 /* CPUID(1).eax */
2047 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
2048 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
2049 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
2050
2051 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
2052 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
2053 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
2054
2055 /* CPUID(1).ecx */
2056 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
2057 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
2058 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
2059 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2060 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
2061 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
2062 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
2063 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
2064 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
2065 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
2066 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
2067 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2068 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
2069 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
2070 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
2071 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
2072 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2073 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2074 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
2075 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
2076 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
2077 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2078 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2079 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2080 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2081 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2082 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2083 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2084 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2085 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2086 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2087 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2088
2089 /* CPUID(1).edx */
2090 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2091 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2092 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2093 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2094 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2095 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2096 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2097 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2098 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2099 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2100 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2101 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2102 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2103 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2104 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2105 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2106 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2107 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2108 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2109 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2110 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2111 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2112 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2113 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2114 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2115 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2116 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2117 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2118 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2119 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2120 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2121 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2122
2123 /* CPUID(2) - config, mostly about caches. ignore. */
2124 /* CPUID(3) - processor serial number. ignore. */
2125 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2126 /* CPUID(5) - mwait/monitor config. ignore. */
2127 /* CPUID(6) - power management. ignore. */
2128 /* CPUID(7) - ???. ignore. */
2129 /* CPUID(8) - ???. ignore. */
2130 /* CPUID(9) - DCA. ignore for now. */
2131 /* CPUID(a) - PeMo info. ignore for now. */
2132 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2133
2134 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2135 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2136 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2137 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2138 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2139 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2140 {
2141 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2142 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2143 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2144 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2145 }
2146
2147 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2148 Note! Intel have/is marking many of the fields here as reserved. We
2149 will verify them as if it's an AMD CPU. */
2150 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2151 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2152 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2153 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2154 {
2155 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2156 && aHostRawExt[0].ecx == aRawExt[0].ecx
2157 && aHostRawExt[0].edx == aRawExt[0].edx,
2158 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2159 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2160 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2161 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2162
2163 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2164 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2165 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2166 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2167 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2168 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2169
2170 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2171 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2172 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2173 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2174
2175 /* CPUID(0x80000001).ecx */
2176 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2177 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2178 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2179 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2180 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2181 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2182 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2183 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2184 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2185 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2186 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2187 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2188 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2189 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2190 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2191 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2192 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2193 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2194 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2195 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2196 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2197 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2198 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2199 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2200 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2201 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2202 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2203 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2204 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2205 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2206 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2207 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2208
2209 /* CPUID(0x80000001).edx */
2210 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2211 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2212 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2213 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2214 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2215 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2216 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2217 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2218 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2219 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2220 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2221 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2222 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2223 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2224 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2225 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2226 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2227 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2228 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2229 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2230 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2231 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2232 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2233 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2234 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2235 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2236 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2237 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2238 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2239 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2240 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2241 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2242
2243 /** @todo verify the rest as well. */
2244 }
2245 }
2246
2247
2248
2249 /*
2250 * Verify that we can support the features already exposed to the guest on
2251 * this host.
2252 *
2253 * Most of the features we're emulating requires intercepting instruction
2254 * and doing it the slow way, so there is no need to warn when they aren't
2255 * present in the host CPU. Thus we use IGN instead of EMU on these.
2256 *
2257 * Trailing comments:
2258 * "EMU" - Possible to emulate, could be lots of work and very slow.
2259 * "EMU?" - Can this be emulated?
2260 */
2261 /* CPUID(1).ecx */
2262 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2263 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2264 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2265 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2266 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2267 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2268 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2269 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2270 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2271 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2272 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2273 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2274 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2275 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2276 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2277 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2278 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2279 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2280 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2281 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2282 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2283 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2284 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2285 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2286 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2287 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2288 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2289 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2290 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2291 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2292 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2293 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2294
2295 /* CPUID(1).edx */
2296 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2297 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2298 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2299 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2300 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2301 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2302 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2303 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2304 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2305 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2306 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2307 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2308 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2309 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2310 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2311 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2312 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2313 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2314 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2315 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2316 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2317 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2318 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2319 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2320 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2321 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2322 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2323 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2324 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2325 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2326 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2327 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2328
2329 /* CPUID(0x80000000). */
2330 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2331 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2332 {
2333 /** @todo deal with no 0x80000001 on the host. */
2334 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2335 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2336
2337 /* CPUID(0x80000001).ecx */
2338 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2339 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2340 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2341 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2342 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2343 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2344 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2345 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2346 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2347 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2348 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2349 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2350 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2351 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2352 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2353 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2354 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2355 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2356 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2357 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2358 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2359 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2360 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2361 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2362 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2363 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2364 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2365 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2366 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2367 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2368 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2369 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2370
2371 /* CPUID(0x80000001).edx */
2372 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2373 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2374 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2375 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2376 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2377 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2378 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2379 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2380 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2381 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2382 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2383 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2384 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2385 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2386 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2387 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2388 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2389 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2390 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2391 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2392 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2393 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2394 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2395 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2396 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2397 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2398 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2399 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2400 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2401 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2402 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2403 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2404 }
2405
2406 /*
2407 * We're good, commit the CPU ID leaves.
2408 */
2409 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2410 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2411 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2412 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2413
2414#undef CPUID_CHECK_RET
2415#undef CPUID_CHECK_WRN
2416#undef CPUID_CHECK2_RET
2417#undef CPUID_CHECK2_WRN
2418#undef CPUID_RAW_FEATURE_RET
2419#undef CPUID_RAW_FEATURE_WRN
2420#undef CPUID_RAW_FEATURE_IGN
2421#undef CPUID_GST_FEATURE_RET
2422#undef CPUID_GST_FEATURE_WRN
2423#undef CPUID_GST_FEATURE_EMU
2424#undef CPUID_GST_FEATURE_IGN
2425#undef CPUID_GST_FEATURE2_RET
2426#undef CPUID_GST_FEATURE2_WRN
2427#undef CPUID_GST_FEATURE2_EMU
2428#undef CPUID_GST_FEATURE2_IGN
2429#undef CPUID_GST_AMD_FEATURE_RET
2430#undef CPUID_GST_AMD_FEATURE_WRN
2431#undef CPUID_GST_AMD_FEATURE_EMU
2432#undef CPUID_GST_AMD_FEATURE_IGN
2433
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/**
2439 * Pass 0 live exec callback.
2440 *
2441 * @returns VINF_SSM_DONT_CALL_AGAIN.
2442 * @param pVM Pointer to the VM.
2443 * @param pSSM The saved state handle.
2444 * @param uPass The pass (0).
2445 */
2446static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2447{
2448 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2449 cpumR3SaveCpuId(pVM, pSSM);
2450 return VINF_SSM_DONT_CALL_AGAIN;
2451}
2452
2453
2454/**
2455 * Execute state save operation.
2456 *
2457 * @returns VBox status code.
2458 * @param pVM Pointer to the VM.
2459 * @param pSSM SSM operation handle.
2460 */
2461static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2462{
2463 /*
2464 * Save.
2465 */
2466 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2467 {
2468 PVMCPU pVCpu = &pVM->aCpus[i];
2469 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2470 }
2471
2472 SSMR3PutU32(pSSM, pVM->cCpus);
2473 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2474 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2475 {
2476 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2477
2478 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2479 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2480 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2481 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2482 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2483 }
2484
2485 cpumR3SaveCpuId(pVM, pSSM);
2486 return VINF_SUCCESS;
2487}
2488
2489
2490/**
2491 * @copydoc FNSSMINTLOADPREP
2492 */
2493static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2494{
2495 NOREF(pSSM);
2496 pVM->cpum.s.fPendingRestore = true;
2497 return VINF_SUCCESS;
2498}
2499
2500
2501/**
2502 * @copydoc FNSSMINTLOADEXEC
2503 */
2504static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2505{
2506 /*
2507 * Validate version.
2508 */
2509 if ( uVersion != CPUM_SAVED_STATE_VERSION
2510 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2511 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2512 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2513 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2514 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2515 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2516 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2517 {
2518 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2519 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2520 }
2521
2522 if (uPass == SSM_PASS_FINAL)
2523 {
2524 /*
2525 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2526 * really old SSM file versions.)
2527 */
2528 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2529 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2530 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2531 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2532
2533 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2534 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2535 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2536 paCpumCtxFields = g_aCpumCtxFieldsV16;
2537 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2538 paCpumCtxFields = g_aCpumCtxFieldsMem;
2539
2540 /*
2541 * Restore.
2542 */
2543 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2544 {
2545 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2546 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2547 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2548 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2549 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2550 pVCpu->cpum.s.Hyper.rsp = uRSP;
2551 }
2552
2553 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2554 {
2555 uint32_t cCpus;
2556 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2557 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2558 VERR_SSM_UNEXPECTED_DATA);
2559 }
2560 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2561 || pVM->cCpus == 1,
2562 ("cCpus=%u\n", pVM->cCpus),
2563 VERR_SSM_UNEXPECTED_DATA);
2564
2565 uint32_t cbMsrs = 0;
2566 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2567 {
2568 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2569 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2570 VERR_SSM_UNEXPECTED_DATA);
2571 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2572 VERR_SSM_UNEXPECTED_DATA);
2573 }
2574
2575 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2576 {
2577 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2578 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2579 paCpumCtxFields, NULL);
2580 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2581 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2582 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2583 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2584 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2585 {
2586 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2587 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2588 }
2589
2590 /* REM and other may have cleared must-be-one fields in DR6 and
2591 DR7, fix these. */
2592 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2593 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
2594 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2595 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
2596 }
2597
2598 /* Older states does not have the internal selector register flags
2599 and valid selector value. Supply those. */
2600 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2601 {
2602 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2603 {
2604 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2605 bool const fValid = HMIsEnabled(pVM)
2606 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2607 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2608 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2609 if (fValid)
2610 {
2611 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2612 {
2613 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2614 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2615 }
2616
2617 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2618 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2619 }
2620 else
2621 {
2622 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2623 {
2624 paSelReg[iSelReg].fFlags = 0;
2625 paSelReg[iSelReg].ValidSel = 0;
2626 }
2627
2628 /* This might not be 104% correct, but I think it's close
2629 enough for all practical purposes... (REM always loaded
2630 LDTR registers.) */
2631 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2632 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2633 }
2634 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2635 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2636 }
2637 }
2638
2639 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2640 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2641 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2642 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2643 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2644
2645 /*
2646 * A quick sanity check.
2647 */
2648 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2649 {
2650 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2651 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2652 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2653 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2654 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2655 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2656 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2657 }
2658 }
2659
2660 pVM->cpum.s.fPendingRestore = false;
2661
2662 /*
2663 * Guest CPUIDs.
2664 */
2665 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2666 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2667
2668 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2669 * actually required. */
2670
2671 /*
2672 * Restore the CPUID leaves.
2673 *
2674 * Note that we support restoring less than the current amount of standard
2675 * leaves because we've been allowed more is newer version of VBox.
2676 */
2677 uint32_t cElements;
2678 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2679 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2680 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2681 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2682
2683 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2684 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2685 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2686 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2687
2688 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2689 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2690 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2691 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2692
2693 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2694
2695 /*
2696 * Check that the basic cpuid id information is unchanged.
2697 */
2698 /** @todo we should check the 64 bits capabilities too! */
2699 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2700 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2701 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2702 uint32_t au32CpuIdSaved[8];
2703 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2704 if (RT_SUCCESS(rc))
2705 {
2706 /* Ignore CPU stepping. */
2707 au32CpuId[4] &= 0xfffffff0;
2708 au32CpuIdSaved[4] &= 0xfffffff0;
2709
2710 /* Ignore APIC ID (AMD specs). */
2711 au32CpuId[5] &= ~0xff000000;
2712 au32CpuIdSaved[5] &= ~0xff000000;
2713
2714 /* Ignore the number of Logical CPUs (AMD specs). */
2715 au32CpuId[5] &= ~0x00ff0000;
2716 au32CpuIdSaved[5] &= ~0x00ff0000;
2717
2718 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2719 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2720 | X86_CPUID_FEATURE_ECX_VMX
2721 | X86_CPUID_FEATURE_ECX_SMX
2722 | X86_CPUID_FEATURE_ECX_EST
2723 | X86_CPUID_FEATURE_ECX_TM2
2724 | X86_CPUID_FEATURE_ECX_CNTXID
2725 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2726 | X86_CPUID_FEATURE_ECX_PDCM
2727 | X86_CPUID_FEATURE_ECX_DCA
2728 | X86_CPUID_FEATURE_ECX_X2APIC
2729 );
2730 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2731 | X86_CPUID_FEATURE_ECX_VMX
2732 | X86_CPUID_FEATURE_ECX_SMX
2733 | X86_CPUID_FEATURE_ECX_EST
2734 | X86_CPUID_FEATURE_ECX_TM2
2735 | X86_CPUID_FEATURE_ECX_CNTXID
2736 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2737 | X86_CPUID_FEATURE_ECX_PDCM
2738 | X86_CPUID_FEATURE_ECX_DCA
2739 | X86_CPUID_FEATURE_ECX_X2APIC
2740 );
2741
2742 /* Make sure we don't forget to update the masks when enabling
2743 * features in the future.
2744 */
2745 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2746 ( X86_CPUID_FEATURE_ECX_DTES64
2747 | X86_CPUID_FEATURE_ECX_VMX
2748 | X86_CPUID_FEATURE_ECX_SMX
2749 | X86_CPUID_FEATURE_ECX_EST
2750 | X86_CPUID_FEATURE_ECX_TM2
2751 | X86_CPUID_FEATURE_ECX_CNTXID
2752 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2753 | X86_CPUID_FEATURE_ECX_PDCM
2754 | X86_CPUID_FEATURE_ECX_DCA
2755 | X86_CPUID_FEATURE_ECX_X2APIC
2756 )));
2757 /* do the compare */
2758 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2759 {
2760 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2761 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2762 "Saved=%.*Rhxs\n"
2763 "Real =%.*Rhxs\n",
2764 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2765 sizeof(au32CpuId), au32CpuId));
2766 else
2767 {
2768 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2769 "Saved=%.*Rhxs\n"
2770 "Real =%.*Rhxs\n",
2771 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2772 sizeof(au32CpuId), au32CpuId));
2773 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2774 }
2775 }
2776 }
2777
2778 return rc;
2779}
2780
2781
2782/**
2783 * @copydoc FNSSMINTLOADPREP
2784 */
2785static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2786{
2787 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2788 return VINF_SUCCESS;
2789
2790 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2791 if (pVM->cpum.s.fPendingRestore)
2792 {
2793 LogRel(("CPUM: Missing state!\n"));
2794 return VERR_INTERNAL_ERROR_2;
2795 }
2796
2797 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2798 {
2799 /* Notify PGM of the NXE states in case they've changed. */
2800 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2801
2802 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
2803 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
2804 }
2805 return VINF_SUCCESS;
2806}
2807
2808
2809/**
2810 * Checks if the CPUM state restore is still pending.
2811 *
2812 * @returns true / false.
2813 * @param pVM Pointer to the VM.
2814 */
2815VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2816{
2817 return pVM->cpum.s.fPendingRestore;
2818}
2819
2820
2821/**
2822 * Formats the EFLAGS value into mnemonics.
2823 *
2824 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2825 * @param efl The EFLAGS value.
2826 */
2827static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2828{
2829 /*
2830 * Format the flags.
2831 */
2832 static const struct
2833 {
2834 const char *pszSet; const char *pszClear; uint32_t fFlag;
2835 } s_aFlags[] =
2836 {
2837 { "vip",NULL, X86_EFL_VIP },
2838 { "vif",NULL, X86_EFL_VIF },
2839 { "ac", NULL, X86_EFL_AC },
2840 { "vm", NULL, X86_EFL_VM },
2841 { "rf", NULL, X86_EFL_RF },
2842 { "nt", NULL, X86_EFL_NT },
2843 { "ov", "nv", X86_EFL_OF },
2844 { "dn", "up", X86_EFL_DF },
2845 { "ei", "di", X86_EFL_IF },
2846 { "tf", NULL, X86_EFL_TF },
2847 { "nt", "pl", X86_EFL_SF },
2848 { "nz", "zr", X86_EFL_ZF },
2849 { "ac", "na", X86_EFL_AF },
2850 { "po", "pe", X86_EFL_PF },
2851 { "cy", "nc", X86_EFL_CF },
2852 };
2853 char *psz = pszEFlags;
2854 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2855 {
2856 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2857 if (pszAdd)
2858 {
2859 strcpy(psz, pszAdd);
2860 psz += strlen(pszAdd);
2861 *psz++ = ' ';
2862 }
2863 }
2864 psz[-1] = '\0';
2865}
2866
2867
2868/**
2869 * Formats a full register dump.
2870 *
2871 * @param pVM Pointer to the VM.
2872 * @param pCtx The context to format.
2873 * @param pCtxCore The context core to format.
2874 * @param pHlp Output functions.
2875 * @param enmType The dump type.
2876 * @param pszPrefix Register name prefix.
2877 */
2878static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2879 const char *pszPrefix)
2880{
2881 NOREF(pVM);
2882
2883 /*
2884 * Format the EFLAGS.
2885 */
2886 uint32_t efl = pCtxCore->eflags.u32;
2887 char szEFlags[80];
2888 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2889
2890 /*
2891 * Format the registers.
2892 */
2893 switch (enmType)
2894 {
2895 case CPUMDUMPTYPE_TERSE:
2896 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2897 pHlp->pfnPrintf(pHlp,
2898 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2899 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2900 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2901 "%sr14=%016RX64 %sr15=%016RX64\n"
2902 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2903 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2904 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2905 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2906 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2907 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2908 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2909 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2910 else
2911 pHlp->pfnPrintf(pHlp,
2912 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2913 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2914 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2915 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2916 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2917 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2918 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2919 break;
2920
2921 case CPUMDUMPTYPE_DEFAULT:
2922 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2923 pHlp->pfnPrintf(pHlp,
2924 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2925 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2926 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2927 "%sr14=%016RX64 %sr15=%016RX64\n"
2928 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2929 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2930 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2931 ,
2932 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2933 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2934 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2935 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2936 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2937 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2938 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2939 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2940 else
2941 pHlp->pfnPrintf(pHlp,
2942 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2943 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2944 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2945 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2946 ,
2947 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2948 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2949 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2950 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2951 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2952 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2953 break;
2954
2955 case CPUMDUMPTYPE_VERBOSE:
2956 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2957 pHlp->pfnPrintf(pHlp,
2958 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2959 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2960 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2961 "%sr14=%016RX64 %sr15=%016RX64\n"
2962 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2963 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2964 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2965 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2966 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2967 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2968 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2969 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2970 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2971 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2972 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2973 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2974 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2975 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2976 ,
2977 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2978 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2979 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2980 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2981 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2982 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2983 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2984 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2985 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2986 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2987 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2988 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2989 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2990 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2991 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2992 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2993 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2994 else
2995 pHlp->pfnPrintf(pHlp,
2996 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2997 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2998 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2999 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3000 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3001 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3002 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3003 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3004 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3005 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3006 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3007 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3008 ,
3009 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3010 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3011 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3012 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3013 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3014 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3015 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3016 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3017 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3018 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3019 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3020 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3021
3022 pHlp->pfnPrintf(pHlp,
3023 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3024 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3025 ,
3026 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
3027 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
3028 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
3029 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
3030 );
3031 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
3032 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
3033 {
3034 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
3035 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
3036 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
3037 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
3038 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
3039 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
3040 /** @todo This isn't entirenly correct and needs more work! */
3041 pHlp->pfnPrintf(pHlp,
3042 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
3043 pszPrefix, iST, pszPrefix, iFPR,
3044 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
3045 uTag, chSign, iInteger, u64Fraction, uExponent);
3046 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
3047 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3048 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
3049 else
3050 pHlp->pfnPrintf(pHlp, "\n");
3051 }
3052 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
3053 pHlp->pfnPrintf(pHlp,
3054 iXMM & 1
3055 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3056 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3057 pszPrefix, iXMM, iXMM < 10 ? " " : "",
3058 pCtx->fpu.aXMM[iXMM].au32[3],
3059 pCtx->fpu.aXMM[iXMM].au32[2],
3060 pCtx->fpu.aXMM[iXMM].au32[1],
3061 pCtx->fpu.aXMM[iXMM].au32[0]);
3062 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
3063 if (pCtx->fpu.au32RsrvdRest[i])
3064 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
3065 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
3066
3067 pHlp->pfnPrintf(pHlp,
3068 "%sEFER =%016RX64\n"
3069 "%sPAT =%016RX64\n"
3070 "%sSTAR =%016RX64\n"
3071 "%sCSTAR =%016RX64\n"
3072 "%sLSTAR =%016RX64\n"
3073 "%sSFMASK =%016RX64\n"
3074 "%sKERNELGSBASE =%016RX64\n",
3075 pszPrefix, pCtx->msrEFER,
3076 pszPrefix, pCtx->msrPAT,
3077 pszPrefix, pCtx->msrSTAR,
3078 pszPrefix, pCtx->msrCSTAR,
3079 pszPrefix, pCtx->msrLSTAR,
3080 pszPrefix, pCtx->msrSFMASK,
3081 pszPrefix, pCtx->msrKERNELGSBASE);
3082 break;
3083 }
3084}
3085
3086
3087/**
3088 * Display all cpu states and any other cpum info.
3089 *
3090 * @param pVM Pointer to the VM.
3091 * @param pHlp The info helper functions.
3092 * @param pszArgs Arguments, ignored.
3093 */
3094static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3095{
3096 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3097 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3098 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3099 cpumR3InfoHost(pVM, pHlp, pszArgs);
3100}
3101
3102
3103/**
3104 * Parses the info argument.
3105 *
3106 * The argument starts with 'verbose', 'terse' or 'default' and then
3107 * continues with the comment string.
3108 *
3109 * @param pszArgs The pointer to the argument string.
3110 * @param penmType Where to store the dump type request.
3111 * @param ppszComment Where to store the pointer to the comment string.
3112 */
3113static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3114{
3115 if (!pszArgs)
3116 {
3117 *penmType = CPUMDUMPTYPE_DEFAULT;
3118 *ppszComment = "";
3119 }
3120 else
3121 {
3122 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3123 {
3124 pszArgs += 7;
3125 *penmType = CPUMDUMPTYPE_VERBOSE;
3126 }
3127 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3128 {
3129 pszArgs += 5;
3130 *penmType = CPUMDUMPTYPE_TERSE;
3131 }
3132 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3133 {
3134 pszArgs += 7;
3135 *penmType = CPUMDUMPTYPE_DEFAULT;
3136 }
3137 else
3138 *penmType = CPUMDUMPTYPE_DEFAULT;
3139 *ppszComment = RTStrStripL(pszArgs);
3140 }
3141}
3142
3143
3144/**
3145 * Display the guest cpu state.
3146 *
3147 * @param pVM Pointer to the VM.
3148 * @param pHlp The info helper functions.
3149 * @param pszArgs Arguments, ignored.
3150 */
3151static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3152{
3153 CPUMDUMPTYPE enmType;
3154 const char *pszComment;
3155 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3156
3157 /* @todo SMP support! */
3158 PVMCPU pVCpu = VMMGetCpu(pVM);
3159 if (!pVCpu)
3160 pVCpu = &pVM->aCpus[0];
3161
3162 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3163
3164 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3165 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3166}
3167
3168
3169/**
3170 * Display the current guest instruction
3171 *
3172 * @param pVM Pointer to the VM.
3173 * @param pHlp The info helper functions.
3174 * @param pszArgs Arguments, ignored.
3175 */
3176static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3177{
3178 NOREF(pszArgs);
3179
3180 /** @todo SMP support! */
3181 PVMCPU pVCpu = VMMGetCpu(pVM);
3182 if (!pVCpu)
3183 pVCpu = &pVM->aCpus[0];
3184
3185 char szInstruction[256];
3186 szInstruction[0] = '\0';
3187 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3188 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3189}
3190
3191
3192/**
3193 * Display the hypervisor cpu state.
3194 *
3195 * @param pVM Pointer to the VM.
3196 * @param pHlp The info helper functions.
3197 * @param pszArgs Arguments, ignored.
3198 */
3199static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3200{
3201 CPUMDUMPTYPE enmType;
3202 const char *pszComment;
3203 /* @todo SMP */
3204 PVMCPU pVCpu = &pVM->aCpus[0];
3205
3206 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3207 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3208 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3209 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3210}
3211
3212
3213/**
3214 * Display the host cpu state.
3215 *
3216 * @param pVM Pointer to the VM.
3217 * @param pHlp The info helper functions.
3218 * @param pszArgs Arguments, ignored.
3219 */
3220static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3221{
3222 CPUMDUMPTYPE enmType;
3223 const char *pszComment;
3224 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3225 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3226
3227 /*
3228 * Format the EFLAGS.
3229 */
3230 /* @todo SMP */
3231 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3232#if HC_ARCH_BITS == 32
3233 uint32_t efl = pCtx->eflags.u32;
3234#else
3235 uint64_t efl = pCtx->rflags;
3236#endif
3237 char szEFlags[80];
3238 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3239
3240 /*
3241 * Format the registers.
3242 */
3243#if HC_ARCH_BITS == 32
3244# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3245 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3246# endif
3247 {
3248 pHlp->pfnPrintf(pHlp,
3249 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3250 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3251 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3252 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3253 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3254 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3255 ,
3256 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3257 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3258 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3259 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3260 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3261 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3262 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3263 }
3264# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3265 else
3266# endif
3267#endif
3268#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3269 {
3270 pHlp->pfnPrintf(pHlp,
3271 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3272 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3273 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3274 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3275 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3276 "r14=%016RX64 r15=%016RX64\n"
3277 "iopl=%d %31s\n"
3278 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3279 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3280 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3281 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3282 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3283 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3284 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3285 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3286 ,
3287 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3288 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3289 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3290 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3291 pCtx->r11, pCtx->r12, pCtx->r13,
3292 pCtx->r14, pCtx->r15,
3293 X86_EFL_GET_IOPL(efl), szEFlags,
3294 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3295 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3296 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3297 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3298 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3299 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3300 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3301 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3302 }
3303#endif
3304}
3305
3306
3307/**
3308 * Get L1 cache / TLS associativity.
3309 */
3310static const char *getCacheAss(unsigned u, char *pszBuf)
3311{
3312 if (u == 0)
3313 return "res0 ";
3314 if (u == 1)
3315 return "direct";
3316 if (u == 255)
3317 return "fully";
3318 if (u >= 256)
3319 return "???";
3320
3321 RTStrPrintf(pszBuf, 16, "%d way", u);
3322 return pszBuf;
3323}
3324
3325
3326/**
3327 * Get L2 cache associativity.
3328 */
3329const char *getL2CacheAss(unsigned u)
3330{
3331 switch (u)
3332 {
3333 case 0: return "off ";
3334 case 1: return "direct";
3335 case 2: return "2 way ";
3336 case 3: return "res3 ";
3337 case 4: return "4 way ";
3338 case 5: return "res5 ";
3339 case 6: return "8 way ";
3340 case 7: return "res7 ";
3341 case 8: return "16 way";
3342 case 9: return "res9 ";
3343 case 10: return "res10 ";
3344 case 11: return "res11 ";
3345 case 12: return "res12 ";
3346 case 13: return "res13 ";
3347 case 14: return "res14 ";
3348 case 15: return "fully ";
3349 default: return "????";
3350 }
3351}
3352
3353
3354/**
3355 * Display the guest CpuId leaves.
3356 *
3357 * @param pVM Pointer to the VM.
3358 * @param pHlp The info helper functions.
3359 * @param pszArgs "terse", "default" or "verbose".
3360 */
3361static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3362{
3363 /*
3364 * Parse the argument.
3365 */
3366 unsigned iVerbosity = 1;
3367 if (pszArgs)
3368 {
3369 pszArgs = RTStrStripL(pszArgs);
3370 if (!strcmp(pszArgs, "terse"))
3371 iVerbosity--;
3372 else if (!strcmp(pszArgs, "verbose"))
3373 iVerbosity++;
3374 }
3375
3376 /*
3377 * Start cracking.
3378 */
3379 CPUMCPUID Host;
3380 CPUMCPUID Guest;
3381 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3382
3383 uint32_t cStdHstMax;
3384 uint32_t dummy;
3385 ASMCpuIdExSlow(0, 0, 0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
3386
3387 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd), cStdHstMax);
3388
3389 pHlp->pfnPrintf(pHlp,
3390 " RAW Standard CPUIDs\n"
3391 " Function eax ebx ecx edx\n");
3392 for (unsigned i = 0; i <= cStdLstMax ; i++)
3393 {
3394 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3395 {
3396 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3397 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3398
3399 pHlp->pfnPrintf(pHlp,
3400 "Gst: %08x %08x %08x %08x %08x%s\n"
3401 "Hst: %08x %08x %08x %08x\n",
3402 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3403 i <= cStdMax ? "" : "*",
3404 Host.eax, Host.ebx, Host.ecx, Host.edx);
3405 }
3406 else
3407 {
3408 ASMCpuIdExSlow(i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3409
3410 pHlp->pfnPrintf(pHlp,
3411 "Hst: %08x %08x %08x %08x %08x\n",
3412 i, Host.eax, Host.ebx, Host.ecx, Host.edx);
3413 }
3414 }
3415
3416 /*
3417 * If verbose, decode it.
3418 */
3419 if (iVerbosity)
3420 {
3421 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3422 pHlp->pfnPrintf(pHlp,
3423 "Name: %.04s%.04s%.04s\n"
3424 "Supports: 0-%x\n",
3425 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3426 }
3427
3428 /*
3429 * Get Features.
3430 */
3431 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3432 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3433 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3434 if (cStdMax >= 1 && iVerbosity)
3435 {
3436 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3437
3438 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3439 uint32_t uEAX = Guest.eax;
3440
3441 pHlp->pfnPrintf(pHlp,
3442 "Family: %d \tExtended: %d \tEffective: %d\n"
3443 "Model: %d \tExtended: %d \tEffective: %d\n"
3444 "Stepping: %d\n"
3445 "Type: %d (%s)\n"
3446 "APIC ID: %#04x\n"
3447 "Logical CPUs: %d\n"
3448 "CLFLUSH Size: %d\n"
3449 "Brand ID: %#04x\n",
3450 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3451 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3452 ASMGetCpuStepping(uEAX),
3453 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3454 (Guest.ebx >> 24) & 0xff,
3455 (Guest.ebx >> 16) & 0xff,
3456 (Guest.ebx >> 8) & 0xff,
3457 (Guest.ebx >> 0) & 0xff);
3458 if (iVerbosity == 1)
3459 {
3460 uint32_t uEDX = Guest.edx;
3461 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3462 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3463 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3464 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3465 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3466 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3467 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3468 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3469 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3470 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3471 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3472 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3473 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3474 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3475 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3476 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3477 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3478 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3479 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3480 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3481 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3482 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3483 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3484 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3485 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3486 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3487 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3488 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3489 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3490 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3491 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3492 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3493 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3494 pHlp->pfnPrintf(pHlp, "\n");
3495
3496 uint32_t uECX = Guest.ecx;
3497 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3498 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3499 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3500 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3501 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3502 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3503 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3504 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3505 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3506 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3507 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3508 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3509 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3510 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3511 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3512 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3513 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3514 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3515 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3516 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3517 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3518 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3519 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3520 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3521 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3522 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3523 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3524 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3525 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3526 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3527 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3528 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3529 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3530 pHlp->pfnPrintf(pHlp, "\n");
3531 }
3532 else
3533 {
3534 ASMCpuIdExSlow(1, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3535
3536 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3537 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3538 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3539 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3540
3541 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3542 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3543 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3544 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3545 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3546 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3547 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3548 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3549 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3550 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3551 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3552 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3553 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3554 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3555 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3556 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3557 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3558 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3559 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3560 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3561 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3562 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3563 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3564 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3565 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3566 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3567 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3568 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3569 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3570 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3571 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3572 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3573 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3574
3575 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3576 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3577 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3578 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3579 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3580 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3581 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3582 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3583 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3584 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3585 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3586 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3587 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3588 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3589 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3590 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3591 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3592 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3593 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3594 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3595 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3596 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3597 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3598 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3599 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3600 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3601 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3602 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3603 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3604 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3605 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3606 }
3607 }
3608 if (cStdMax >= 2 && iVerbosity)
3609 {
3610 /** @todo */
3611 }
3612
3613 /*
3614 * Extended.
3615 * Implemented after AMD specs.
3616 */
3617 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3618
3619 pHlp->pfnPrintf(pHlp,
3620 "\n"
3621 " RAW Extended CPUIDs\n"
3622 " Function eax ebx ecx edx\n");
3623 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3624 {
3625 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3626 ASMCpuIdExSlow(0x80000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3627
3628 pHlp->pfnPrintf(pHlp,
3629 "Gst: %08x %08x %08x %08x %08x%s\n"
3630 "Hst: %08x %08x %08x %08x\n",
3631 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3632 i <= cExtMax ? "" : "*",
3633 Host.eax, Host.ebx, Host.ecx, Host.edx);
3634 }
3635
3636 /*
3637 * Understandable output
3638 */
3639 if (iVerbosity)
3640 {
3641 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3642 pHlp->pfnPrintf(pHlp,
3643 "Ext Name: %.4s%.4s%.4s\n"
3644 "Ext Supports: 0x80000000-%#010x\n",
3645 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3646 }
3647
3648 if (iVerbosity && cExtMax >= 1)
3649 {
3650 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3651 uint32_t uEAX = Guest.eax;
3652 pHlp->pfnPrintf(pHlp,
3653 "Family: %d \tExtended: %d \tEffective: %d\n"
3654 "Model: %d \tExtended: %d \tEffective: %d\n"
3655 "Stepping: %d\n"
3656 "Brand ID: %#05x\n",
3657 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3658 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3659 ASMGetCpuStepping(uEAX),
3660 Guest.ebx & 0xfff);
3661
3662 if (iVerbosity == 1)
3663 {
3664 uint32_t uEDX = Guest.edx;
3665 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3666 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3667 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3668 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3669 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3670 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3671 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3672 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3673 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3674 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3675 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3676 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3677 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3678 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3679 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3680 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3681 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3682 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3683 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3684 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3685 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3686 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3687 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3688 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3689 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3690 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3691 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3692 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3693 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3694 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3695 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3696 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3697 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3698 pHlp->pfnPrintf(pHlp, "\n");
3699
3700 uint32_t uECX = Guest.ecx;
3701 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3702 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3703 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3704 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3705 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3706 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3707 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3708 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3709 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3710 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3711 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3712 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3713 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3714 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3715 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3716 for (unsigned iBit = 5; iBit < 32; iBit++)
3717 if (uECX & RT_BIT(iBit))
3718 pHlp->pfnPrintf(pHlp, " %d", iBit);
3719 pHlp->pfnPrintf(pHlp, "\n");
3720 }
3721 else
3722 {
3723 ASMCpuIdExSlow(0x80000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3724
3725 uint32_t uEdxGst = Guest.edx;
3726 uint32_t uEdxHst = Host.edx;
3727 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3728 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3729 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3730 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3731 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3732 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3733 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3734 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3735 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3736 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3737 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3738 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3739 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3740 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3741 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3742 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3743 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3744 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3745 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3746 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3747 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3748 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3749 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3750 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3751 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3752 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3753 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3754 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3755 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3756 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3757 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3758 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3759 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3760
3761 uint32_t uEcxGst = Guest.ecx;
3762 uint32_t uEcxHst = Host.ecx;
3763 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3764 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3765 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3766 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3767 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3768 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3769 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3770 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3771 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3772 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3773 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3774 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3775 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3776 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3777 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3778 }
3779 }
3780
3781 if (iVerbosity && cExtMax >= 2)
3782 {
3783 char szString[4*4*3+1] = {0};
3784 uint32_t *pu32 = (uint32_t *)szString;
3785 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3786 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3787 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3788 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3789 if (cExtMax >= 3)
3790 {
3791 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3792 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3793 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3794 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3795 }
3796 if (cExtMax >= 4)
3797 {
3798 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3799 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3800 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3801 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3802 }
3803 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3804 }
3805
3806 if (iVerbosity && cExtMax >= 5)
3807 {
3808 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3809 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3810 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3811 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3812 char sz1[32];
3813 char sz2[32];
3814
3815 pHlp->pfnPrintf(pHlp,
3816 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3817 "TLB 2/4M Data: %s %3d entries\n",
3818 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3819 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3820 pHlp->pfnPrintf(pHlp,
3821 "TLB 4K Instr/Uni: %s %3d entries\n"
3822 "TLB 4K Data: %s %3d entries\n",
3823 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3824 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3825 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3826 "L1 Instr Cache Lines Per Tag: %d\n"
3827 "L1 Instr Cache Associativity: %s\n"
3828 "L1 Instr Cache Size: %d KB\n",
3829 (uEDX >> 0) & 0xff,
3830 (uEDX >> 8) & 0xff,
3831 getCacheAss((uEDX >> 16) & 0xff, sz1),
3832 (uEDX >> 24) & 0xff);
3833 pHlp->pfnPrintf(pHlp,
3834 "L1 Data Cache Line Size: %d bytes\n"
3835 "L1 Data Cache Lines Per Tag: %d\n"
3836 "L1 Data Cache Associativity: %s\n"
3837 "L1 Data Cache Size: %d KB\n",
3838 (uECX >> 0) & 0xff,
3839 (uECX >> 8) & 0xff,
3840 getCacheAss((uECX >> 16) & 0xff, sz1),
3841 (uECX >> 24) & 0xff);
3842 }
3843
3844 if (iVerbosity && cExtMax >= 6)
3845 {
3846 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3847 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3848 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3849
3850 pHlp->pfnPrintf(pHlp,
3851 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3852 "L2 TLB 2/4M Data: %s %4d entries\n",
3853 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3854 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3855 pHlp->pfnPrintf(pHlp,
3856 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3857 "L2 TLB 4K Data: %s %4d entries\n",
3858 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3859 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3860 pHlp->pfnPrintf(pHlp,
3861 "L2 Cache Line Size: %d bytes\n"
3862 "L2 Cache Lines Per Tag: %d\n"
3863 "L2 Cache Associativity: %s\n"
3864 "L2 Cache Size: %d KB\n",
3865 (uEDX >> 0) & 0xff,
3866 (uEDX >> 8) & 0xf,
3867 getL2CacheAss((uEDX >> 12) & 0xf),
3868 (uEDX >> 16) & 0xffff);
3869 }
3870
3871 if (iVerbosity && cExtMax >= 7)
3872 {
3873 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3874
3875 pHlp->pfnPrintf(pHlp, "APM Features: ");
3876 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3877 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3878 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3879 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3880 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3881 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3882 for (unsigned iBit = 6; iBit < 32; iBit++)
3883 if (uEDX & RT_BIT(iBit))
3884 pHlp->pfnPrintf(pHlp, " %d", iBit);
3885 pHlp->pfnPrintf(pHlp, "\n");
3886 }
3887
3888 if (iVerbosity && cExtMax >= 8)
3889 {
3890 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3891 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3892
3893 pHlp->pfnPrintf(pHlp,
3894 "Physical Address Width: %d bits\n"
3895 "Virtual Address Width: %d bits\n"
3896 "Guest Physical Address Width: %d bits\n",
3897 (uEAX >> 0) & 0xff,
3898 (uEAX >> 8) & 0xff,
3899 (uEAX >> 16) & 0xff);
3900 pHlp->pfnPrintf(pHlp,
3901 "Physical Core Count: %d\n",
3902 (uECX >> 0) & 0xff);
3903 }
3904
3905
3906 /*
3907 * Centaur.
3908 */
3909 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3910
3911 pHlp->pfnPrintf(pHlp,
3912 "\n"
3913 " RAW Centaur CPUIDs\n"
3914 " Function eax ebx ecx edx\n");
3915 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3916 {
3917 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3918 ASMCpuIdExSlow(0xc0000000 | i, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3919
3920 pHlp->pfnPrintf(pHlp,
3921 "Gst: %08x %08x %08x %08x %08x%s\n"
3922 "Hst: %08x %08x %08x %08x\n",
3923 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3924 i <= cCentaurMax ? "" : "*",
3925 Host.eax, Host.ebx, Host.ecx, Host.edx);
3926 }
3927
3928 /*
3929 * Understandable output
3930 */
3931 if (iVerbosity)
3932 {
3933 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3934 pHlp->pfnPrintf(pHlp,
3935 "Centaur Supports: 0xc0000000-%#010x\n",
3936 Guest.eax);
3937 }
3938
3939 if (iVerbosity && cCentaurMax >= 1)
3940 {
3941 ASMCpuIdExSlow(0xc0000001, 0, 0, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3942 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdCentaur[1].edx;
3943 uint32_t uEdxHst = Host.edx;
3944
3945 if (iVerbosity == 1)
3946 {
3947 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3948 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3949 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3950 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3951 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3952 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3953 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3954 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3955 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3956 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3957 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3958 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3959 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3960 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3961 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3962 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3963 for (unsigned iBit = 14; iBit < 32; iBit++)
3964 if (uEdxGst & RT_BIT(iBit))
3965 pHlp->pfnPrintf(pHlp, " %d", iBit);
3966 pHlp->pfnPrintf(pHlp, "\n");
3967 }
3968 else
3969 {
3970 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3971 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3972 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3973 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3974 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3975 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3976 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3977 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3978 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3979 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3980 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3981 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3982 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3983 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3984 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3985 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3986 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3987 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3988 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3989 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3990 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3991 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3992 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3993 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3994 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3995 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3996 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3997 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3998 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3999 for (unsigned iBit = 27; iBit < 32; iBit++)
4000 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
4001 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
4002 pHlp->pfnPrintf(pHlp, "\n");
4003 }
4004 }
4005}
4006
4007
4008/**
4009 * Structure used when disassembling and instructions in DBGF.
4010 * This is used so the reader function can get the stuff it needs.
4011 */
4012typedef struct CPUMDISASSTATE
4013{
4014 /** Pointer to the CPU structure. */
4015 PDISCPUSTATE pCpu;
4016 /** Pointer to the VM. */
4017 PVM pVM;
4018 /** Pointer to the VMCPU. */
4019 PVMCPU pVCpu;
4020 /** Pointer to the first byte in the segment. */
4021 RTGCUINTPTR GCPtrSegBase;
4022 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
4023 RTGCUINTPTR GCPtrSegEnd;
4024 /** The size of the segment minus 1. */
4025 RTGCUINTPTR cbSegLimit;
4026 /** Pointer to the current page - R3 Ptr. */
4027 void const *pvPageR3;
4028 /** Pointer to the current page - GC Ptr. */
4029 RTGCPTR pvPageGC;
4030 /** The lock information that PGMPhysReleasePageMappingLock needs. */
4031 PGMPAGEMAPLOCK PageMapLock;
4032 /** Whether the PageMapLock is valid or not. */
4033 bool fLocked;
4034 /** 64 bits mode or not. */
4035 bool f64Bits;
4036} CPUMDISASSTATE, *PCPUMDISASSTATE;
4037
4038
4039/**
4040 * @callback_method_impl{FNDISREADBYTES}
4041 */
4042static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4043{
4044 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4045 for (;;)
4046 {
4047 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4048
4049 /*
4050 * Need to update the page translation?
4051 */
4052 if ( !pState->pvPageR3
4053 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4054 {
4055 int rc = VINF_SUCCESS;
4056
4057 /* translate the address */
4058 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4059 if ( !HMIsEnabled(pState->pVM)
4060 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4061 {
4062 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4063 if (!pState->pvPageR3)
4064 rc = VERR_INVALID_POINTER;
4065 }
4066 else
4067 {
4068 /* Release mapping lock previously acquired. */
4069 if (pState->fLocked)
4070 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4071 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4072 pState->fLocked = RT_SUCCESS_NP(rc);
4073 }
4074 if (RT_FAILURE(rc))
4075 {
4076 pState->pvPageR3 = NULL;
4077 return rc;
4078 }
4079 }
4080
4081 /*
4082 * Check the segment limit.
4083 */
4084 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4085 return VERR_OUT_OF_SELECTOR_BOUNDS;
4086
4087 /*
4088 * Calc how much we can read.
4089 */
4090 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4091 if (!pState->f64Bits)
4092 {
4093 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4094 if (cb > cbSeg && cbSeg)
4095 cb = cbSeg;
4096 }
4097 if (cb > cbMaxRead)
4098 cb = cbMaxRead;
4099
4100 /*
4101 * Read and advance or exit.
4102 */
4103 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4104 offInstr += (uint8_t)cb;
4105 if (cb >= cbMinRead)
4106 {
4107 pDis->cbCachedInstr = offInstr;
4108 return VINF_SUCCESS;
4109 }
4110 cbMinRead -= (uint8_t)cb;
4111 cbMaxRead -= (uint8_t)cb;
4112 }
4113}
4114
4115
4116/**
4117 * Disassemble an instruction and return the information in the provided structure.
4118 *
4119 * @returns VBox status code.
4120 * @param pVM Pointer to the VM.
4121 * @param pVCpu Pointer to the VMCPU.
4122 * @param pCtx Pointer to the guest CPU context.
4123 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4124 * @param pCpu Disassembly state.
4125 * @param pszPrefix String prefix for logging (debug only).
4126 *
4127 */
4128VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4129{
4130 CPUMDISASSTATE State;
4131 int rc;
4132
4133 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4134 State.pCpu = pCpu;
4135 State.pvPageGC = 0;
4136 State.pvPageR3 = NULL;
4137 State.pVM = pVM;
4138 State.pVCpu = pVCpu;
4139 State.fLocked = false;
4140 State.f64Bits = false;
4141
4142 /*
4143 * Get selector information.
4144 */
4145 DISCPUMODE enmDisCpuMode;
4146 if ( (pCtx->cr0 & X86_CR0_PE)
4147 && pCtx->eflags.Bits.u1VM == 0)
4148 {
4149 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4150 {
4151# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4152 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4153# endif
4154 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4155 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4156 }
4157 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4158 State.GCPtrSegBase = pCtx->cs.u64Base;
4159 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4160 State.cbSegLimit = pCtx->cs.u32Limit;
4161 enmDisCpuMode = (State.f64Bits)
4162 ? DISCPUMODE_64BIT
4163 : pCtx->cs.Attr.n.u1DefBig
4164 ? DISCPUMODE_32BIT
4165 : DISCPUMODE_16BIT;
4166 }
4167 else
4168 {
4169 /* real or V86 mode */
4170 enmDisCpuMode = DISCPUMODE_16BIT;
4171 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4172 State.GCPtrSegEnd = 0xFFFFFFFF;
4173 State.cbSegLimit = 0xFFFFFFFF;
4174 }
4175
4176 /*
4177 * Disassemble the instruction.
4178 */
4179 uint32_t cbInstr;
4180#ifndef LOG_ENABLED
4181 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4182 if (RT_SUCCESS(rc))
4183 {
4184#else
4185 char szOutput[160];
4186 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4187 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4188 if (RT_SUCCESS(rc))
4189 {
4190 /* log it */
4191 if (pszPrefix)
4192 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4193 else
4194 Log(("%s", szOutput));
4195#endif
4196 rc = VINF_SUCCESS;
4197 }
4198 else
4199 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4200
4201 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4202 if (State.fLocked)
4203 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4204
4205 return rc;
4206}
4207
4208
4209
4210/**
4211 * API for controlling a few of the CPU features found in CR4.
4212 *
4213 * Currently only X86_CR4_TSD is accepted as input.
4214 *
4215 * @returns VBox status code.
4216 *
4217 * @param pVM Pointer to the VM.
4218 * @param fOr The CR4 OR mask.
4219 * @param fAnd The CR4 AND mask.
4220 */
4221VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4222{
4223 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4224 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4225
4226 pVM->cpum.s.CR4.OrMask &= fAnd;
4227 pVM->cpum.s.CR4.OrMask |= fOr;
4228
4229 return VINF_SUCCESS;
4230}
4231
4232
4233/**
4234 * Gets a pointer to the array of standard CPUID leaves.
4235 *
4236 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4237 *
4238 * @returns Pointer to the standard CPUID leaves (read-only).
4239 * @param pVM Pointer to the VM.
4240 * @remark Intended for PATM.
4241 */
4242VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4243{
4244 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4245}
4246
4247
4248/**
4249 * Gets a pointer to the array of extended CPUID leaves.
4250 *
4251 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4252 *
4253 * @returns Pointer to the extended CPUID leaves (read-only).
4254 * @param pVM Pointer to the VM.
4255 * @remark Intended for PATM.
4256 */
4257VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4258{
4259 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4260}
4261
4262
4263/**
4264 * Gets a pointer to the array of centaur CPUID leaves.
4265 *
4266 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4267 *
4268 * @returns Pointer to the centaur CPUID leaves (read-only).
4269 * @param pVM Pointer to the VM.
4270 * @remark Intended for PATM.
4271 */
4272VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4273{
4274 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4275}
4276
4277
4278/**
4279 * Gets a pointer to the default CPUID leaf.
4280 *
4281 * @returns Pointer to the default CPUID leaf (read-only).
4282 * @param pVM Pointer to the VM.
4283 * @remark Intended for PATM.
4284 */
4285VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4286{
4287 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4288}
4289
4290
4291/**
4292 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4293 *
4294 * Only REM should ever call this function!
4295 *
4296 * @returns The changed flags.
4297 * @param pVCpu Pointer to the VMCPU.
4298 * @param puCpl Where to return the current privilege level (CPL).
4299 */
4300VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4301{
4302 Assert(!pVCpu->cpum.s.fRawEntered);
4303 Assert(!pVCpu->cpum.s.fRemEntered);
4304
4305 /*
4306 * Get the CPL first.
4307 */
4308 *puCpl = CPUMGetGuestCPL(pVCpu);
4309
4310 /*
4311 * Get and reset the flags.
4312 */
4313 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4314 pVCpu->cpum.s.fChanged = 0;
4315
4316 /** @todo change the switcher to use the fChanged flags. */
4317 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4318 {
4319 fFlags |= CPUM_CHANGED_FPU_REM;
4320 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4321 }
4322
4323 pVCpu->cpum.s.fRemEntered = true;
4324 return fFlags;
4325}
4326
4327
4328/**
4329 * Leaves REM.
4330 *
4331 * @param pVCpu Pointer to the VMCPU.
4332 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4333 * registers.
4334 */
4335VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4336{
4337 Assert(!pVCpu->cpum.s.fRawEntered);
4338 Assert(pVCpu->cpum.s.fRemEntered);
4339
4340 pVCpu->cpum.s.fRemEntered = false;
4341}
4342
4343
4344/**
4345 * Called when the ring-3 init phase completes.
4346 *
4347 * @returns VBox status code.
4348 * @param pVM Pointer to the VM.
4349 */
4350VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4351{
4352 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4353 {
4354 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4355 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4356 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4357 }
4358 return VINF_SUCCESS;
4359}
4360
4361/**
4362 * Called when the ring-0 init phases comleted.
4363 *
4364 * @param pVM Pointer to the VM.
4365 */
4366VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4367{
4368 /*
4369 * Log the cpuid.
4370 */
4371 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4372 RTCPUSET OnlineSet;
4373 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4374 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4375 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4376 RTCPUID cCores = RTMpGetCoreCount();
4377 if (cCores)
4378 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
4379 LogRel(("************************* CPUID dump ************************\n"));
4380 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4381 LogRel(("\n"));
4382 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4383 RTLogRelSetBuffering(fOldBuffered);
4384 LogRel(("******************** End of CPUID dump **********************\n"));
4385}
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