CPUM.cpp@ 79373

Last change on this file since 79373 was 79353, checked in by vboxsync, 6 years ago
VMM/CPUM: Nested VMX: bugref:9180 Todo about exposing VMX VMWRITE-all feature to the guest. In theory, we could do this without VMCS shadowing but it's of no real use to the guest hypervisor.
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1	/* $Id: CPUM.cpp 79353 2019-06-26 09:44:40Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
339	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
340	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
341	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
342
343	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
344	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
345	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
346	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
347	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
348	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
349	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
350	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
351	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
352	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
353	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1[8]),
354
355	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
356	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
357	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
358	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
359	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
360	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
361	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
362	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
363
364	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
365	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
366	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
367	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
369	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
370	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
371	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
373	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
374	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
378	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
379	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
380	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
381	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
382	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
383
384	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
385	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
386	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
387	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
388	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
389	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
390	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
391	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
392	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
393
394	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
395	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
396	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
397	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
398	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
399	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
400	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
401	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
402	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
403	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
404	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
405	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
406	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
407	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
408	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
409	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
410	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
411	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
412	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
413	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
414	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
415	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
416	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
417	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
418
419	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
420	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
421
422	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
423	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
424	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
425	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
426	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
427	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
428	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
429	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
430	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
431	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
432	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
433	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
434	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
435	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
436	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
437	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
438	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
439	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
440	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
441	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
442	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
443	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
444	SSMFIELD_ENTRY( VMXVVMCS, u64XssBitmap),
445	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsBitmap),
446	SSMFIELD_ENTRY( VMXVVMCS, u64SpptPtr),
447	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
448	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
449
450	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
451	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
452
453	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
454	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
455	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
456	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
457	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
458	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
459	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
460	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
461	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
462	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
463	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
464	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
465
466	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
467	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
468	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
469	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
470
471	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
472	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
473	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
474	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
475	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
476	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
477	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
478	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
479	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved4),
480
481	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
482	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
483	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
484	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
485	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
486	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
487	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved5),
488
489	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
490	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
491	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
492	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
493	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
494	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
495	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
496	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
497	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
498	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
503	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
504	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpt),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
509	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved6),
510
511	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
512	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
513	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
514	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
515	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
519	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
520	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
521	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
522	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
523	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved7),
524	SSMFIELD_ENTRY_TERM()
525	};
526
527	/** Saved state field descriptors for CPUMCTX. */
528	static const SSMFIELD g_aCpumX87Fields[] =
529	{
530	SSMFIELD_ENTRY( X86FXSTATE, FCW),
531	SSMFIELD_ENTRY( X86FXSTATE, FSW),
532	SSMFIELD_ENTRY( X86FXSTATE, FTW),
533	SSMFIELD_ENTRY( X86FXSTATE, FOP),
534	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
535	SSMFIELD_ENTRY( X86FXSTATE, CS),
536	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
537	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
538	SSMFIELD_ENTRY( X86FXSTATE, DS),
539	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
540	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
541	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
542	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
543	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
544	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
545	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
546	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
547	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
548	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
549	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
550	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
551	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
552	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
553	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
554	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
555	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
556	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
557	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
558	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
559	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
560	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
561	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
562	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
564	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
565	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
566	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
567	SSMFIELD_ENTRY_TERM()
568	};
569
570	/** Saved state field descriptors for X86XSAVEHDR. */
571	static const SSMFIELD g_aCpumXSaveHdrFields[] =
572	{
573	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
574	SSMFIELD_ENTRY_TERM()
575	};
576
577	/** Saved state field descriptors for X86XSAVEYMMHI. */
578	static const SSMFIELD g_aCpumYmmHiFields[] =
579	{
580	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
581	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
582	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
583	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
584	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
585	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
586	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
587	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
588	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
589	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
590	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
591	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
592	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
594	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
595	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
596	SSMFIELD_ENTRY_TERM()
597	};
598
599	/** Saved state field descriptors for X86XSAVEBNDREGS. */
600	static const SSMFIELD g_aCpumBndRegsFields[] =
601	{
602	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
603	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
604	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
605	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
606	SSMFIELD_ENTRY_TERM()
607	};
608
609	/** Saved state field descriptors for X86XSAVEBNDCFG. */
610	static const SSMFIELD g_aCpumBndCfgFields[] =
611	{
612	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
613	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
614	SSMFIELD_ENTRY_TERM()
615	};
616
617	#if 0 /** @todo */
618	/** Saved state field descriptors for X86XSAVEOPMASK. */
619	static const SSMFIELD g_aCpumOpmaskFields[] =
620	{
621	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
622	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
623	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
624	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
625	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
626	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
627	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
628	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
629	SSMFIELD_ENTRY_TERM()
630	};
631	#endif
632
633	/** Saved state field descriptors for X86XSAVEZMMHI256. */
634	static const SSMFIELD g_aCpumZmmHi256Fields[] =
635	{
636	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
637	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
638	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
639	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
640	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
641	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
642	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
643	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
644	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
645	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
646	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
647	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
648	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
650	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
651	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
652	SSMFIELD_ENTRY_TERM()
653	};
654
655	/** Saved state field descriptors for X86XSAVEZMM16HI. */
656	static const SSMFIELD g_aCpumZmm16HiFields[] =
657	{
658	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
659	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
660	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
661	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
662	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
663	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
664	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
665	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
666	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
667	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
668	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
669	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
670	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
672	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
673	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
674	SSMFIELD_ENTRY_TERM()
675	};
676
677
678
679	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
680	* registeres changed. */
681	static const SSMFIELD g_aCpumX87FieldsMem[] =
682	{
683	SSMFIELD_ENTRY( X86FXSTATE, FCW),
684	SSMFIELD_ENTRY( X86FXSTATE, FSW),
685	SSMFIELD_ENTRY( X86FXSTATE, FTW),
686	SSMFIELD_ENTRY( X86FXSTATE, FOP),
687	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
688	SSMFIELD_ENTRY( X86FXSTATE, CS),
689	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
690	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
691	SSMFIELD_ENTRY( X86FXSTATE, DS),
692	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
693	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
694	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
695	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
696	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
697	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
698	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
699	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
700	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
701	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
702	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
703	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
704	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
705	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
706	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
707	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
708	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
709	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
710	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
711	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
712	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
713	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
714	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
715	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
717	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
718	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
719	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
720	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
721	};
722
723	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
724	* registeres changed. */
725	static const SSMFIELD g_aCpumCtxFieldsMem[] =
726	{
727	SSMFIELD_ENTRY( CPUMCTX, rdi),
728	SSMFIELD_ENTRY( CPUMCTX, rsi),
729	SSMFIELD_ENTRY( CPUMCTX, rbp),
730	SSMFIELD_ENTRY( CPUMCTX, rax),
731	SSMFIELD_ENTRY( CPUMCTX, rbx),
732	SSMFIELD_ENTRY( CPUMCTX, rdx),
733	SSMFIELD_ENTRY( CPUMCTX, rcx),
734	SSMFIELD_ENTRY( CPUMCTX, rsp),
735	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
736	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
737	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
738	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
739	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
740	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
741	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
742	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
743	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
744	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
745	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
746	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
747	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
748	SSMFIELD_ENTRY( CPUMCTX, rflags),
749	SSMFIELD_ENTRY( CPUMCTX, rip),
750	SSMFIELD_ENTRY( CPUMCTX, r8),
751	SSMFIELD_ENTRY( CPUMCTX, r9),
752	SSMFIELD_ENTRY( CPUMCTX, r10),
753	SSMFIELD_ENTRY( CPUMCTX, r11),
754	SSMFIELD_ENTRY( CPUMCTX, r12),
755	SSMFIELD_ENTRY( CPUMCTX, r13),
756	SSMFIELD_ENTRY( CPUMCTX, r14),
757	SSMFIELD_ENTRY( CPUMCTX, r15),
758	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
759	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
760	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
761	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
762	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
763	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
764	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
765	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
766	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
767	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
768	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
769	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
770	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
771	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
772	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
773	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
774	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
775	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
776	SSMFIELD_ENTRY( CPUMCTX, cr0),
777	SSMFIELD_ENTRY( CPUMCTX, cr2),
778	SSMFIELD_ENTRY( CPUMCTX, cr3),
779	SSMFIELD_ENTRY( CPUMCTX, cr4),
780	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
781	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
782	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
783	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
784	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
785	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
786	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
787	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
788	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
789	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
790	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
791	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
792	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
793	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
794	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
795	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
796	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
797	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
798	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
799	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
800	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
801	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
802	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
803	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
804	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
805	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
806	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
807	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
808	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
809	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
810	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
811	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
812	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
813	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
814	SSMFIELD_ENTRY_TERM()
815	};
816
817	/** Saved state field descriptors for CPUMCTX_VER1_6. */
818	static const SSMFIELD g_aCpumX87FieldsV16[] =
819	{
820	SSMFIELD_ENTRY( X86FXSTATE, FCW),
821	SSMFIELD_ENTRY( X86FXSTATE, FSW),
822	SSMFIELD_ENTRY( X86FXSTATE, FTW),
823	SSMFIELD_ENTRY( X86FXSTATE, FOP),
824	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
825	SSMFIELD_ENTRY( X86FXSTATE, CS),
826	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
827	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
828	SSMFIELD_ENTRY( X86FXSTATE, DS),
829	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
830	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
831	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
832	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
833	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
834	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
835	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
836	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
837	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
838	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
839	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
840	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
841	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
842	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
843	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
844	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
845	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
846	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
847	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
848	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
849	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
850	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
851	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
852	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
854	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
855	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
856	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
857	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
858	SSMFIELD_ENTRY_TERM()
859	};
860
861	/** Saved state field descriptors for CPUMCTX_VER1_6. */
862	static const SSMFIELD g_aCpumCtxFieldsV16[] =
863	{
864	SSMFIELD_ENTRY( CPUMCTX, rdi),
865	SSMFIELD_ENTRY( CPUMCTX, rsi),
866	SSMFIELD_ENTRY( CPUMCTX, rbp),
867	SSMFIELD_ENTRY( CPUMCTX, rax),
868	SSMFIELD_ENTRY( CPUMCTX, rbx),
869	SSMFIELD_ENTRY( CPUMCTX, rdx),
870	SSMFIELD_ENTRY( CPUMCTX, rcx),
871	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
872	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
873	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
874	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
875	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
876	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
877	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
878	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
879	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
880	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
881	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
882	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
883	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
884	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
885	SSMFIELD_ENTRY( CPUMCTX, rflags),
886	SSMFIELD_ENTRY( CPUMCTX, rip),
887	SSMFIELD_ENTRY( CPUMCTX, r8),
888	SSMFIELD_ENTRY( CPUMCTX, r9),
889	SSMFIELD_ENTRY( CPUMCTX, r10),
890	SSMFIELD_ENTRY( CPUMCTX, r11),
891	SSMFIELD_ENTRY( CPUMCTX, r12),
892	SSMFIELD_ENTRY( CPUMCTX, r13),
893	SSMFIELD_ENTRY( CPUMCTX, r14),
894	SSMFIELD_ENTRY( CPUMCTX, r15),
895	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
896	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
897	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
898	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
899	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
900	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
901	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
902	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
903	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
904	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
905	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
906	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
907	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
908	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
909	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
910	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
911	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
912	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
913	SSMFIELD_ENTRY( CPUMCTX, cr0),
914	SSMFIELD_ENTRY( CPUMCTX, cr2),
915	SSMFIELD_ENTRY( CPUMCTX, cr3),
916	SSMFIELD_ENTRY( CPUMCTX, cr4),
917	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
918	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
919	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
920	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
921	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
922	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
923	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
924	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
925	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
926	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
927	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
928	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
929	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
930	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
931	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
932	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
933	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
934	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
935	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
936	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
937	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
938	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
939	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
940	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
941	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
942	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
943	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
944	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
945	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
946	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
947	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
948	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
949	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
950	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
951	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
952	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
953	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
954	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
955	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
956	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
957	SSMFIELD_ENTRY_TERM()
958	};
959
960
961	/**
962	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
963	*
964	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
965	* (last instruction pointer, last data pointer, last opcode) except when the ES
966	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
967	* clear these registers there is potential, local FPU leakage from a process
968	* using the FPU to another.
969	*
970	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
971	*
972	* @param pVM The cross context VM structure.
973	*/
974	static void cpumR3CheckLeakyFpu(PVM pVM)
975	{
976	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
977	uint32_t const u32Family = u32CpuVersion >> 8;
978	if ( u32Family >= 6 /* K7 and higher */
979	&& ASMIsAmdCpu())
980	{
981	uint32_t cExt = ASMCpuId_EAX(0x80000000);
982	if (ASMIsValidExtRange(cExt))
983	{
984	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
985	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
986	{
987	for (VMCPUID i = 0; i < pVM->cCpus; i++)
988	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
989	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
990	}
991	}
992	}
993	}
994
995
996	/**
997	* Frees memory allocated for the SVM hardware virtualization state.
998	*
999	* @param pVM The cross context VM structure.
1000	*/
1001	static void cpumR3FreeSvmHwVirtState(PVM pVM)
1002	{
1003	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1004	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1005	{
1006	PVMCPU pVCpu = &pVM->aCpus[i];
1007	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
1008	{
1009	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
1010	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
1011	}
1012	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
1013
1014	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
1015	{
1016	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
1017	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
1018	}
1019
1020	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
1021	{
1022	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
1023	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
1024	}
1025	}
1026	}
1027
1028
1029	/**
1030	* Allocates memory for the SVM hardware virtualization state.
1031	*
1032	* @returns VBox status code.
1033	* @param pVM The cross context VM structure.
1034	*/
1035	static int cpumR3AllocSvmHwVirtState(PVM pVM)
1036	{
1037	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1038
1039	int rc = VINF_SUCCESS;
1040	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
1041	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
1042	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1043	{
1044	PVMCPU pVCpu = &pVM->aCpus[i];
1045	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1046
1047	/*
1048	* Allocate the nested-guest VMCB.
1049	*/
1050	SUPPAGE SupNstGstVmcbPage;
1051	RT_ZERO(SupNstGstVmcbPage);
1052	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
1053	Assert(SVM_VMCB_PAGES == 1);
1054	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1055	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
1056	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
1057	if (RT_FAILURE(rc))
1058	{
1059	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1060	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
1061	break;
1062	}
1063	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
1064
1065	/*
1066	* Allocate the MSRPM (MSR Permission bitmap).
1067	*/
1068	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1069	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
1070	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
1071	if (RT_FAILURE(rc))
1072	{
1073	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1074	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
1075	SVM_MSRPM_PAGES));
1076	break;
1077	}
1078
1079	/*
1080	* Allocate the IOPM (IO Permission bitmap).
1081	*/
1082	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1083	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
1084	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
1085	if (RT_FAILURE(rc))
1086	{
1087	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1088	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
1089	SVM_IOPM_PAGES));
1090	break;
1091	}
1092	}
1093
1094	/* On any failure, cleanup. */
1095	if (RT_FAILURE(rc))
1096	cpumR3FreeSvmHwVirtState(pVM);
1097
1098	return rc;
1099	}
1100
1101
1102	/**
1103	* Resets per-VCPU SVM hardware virtualization state.
1104	*
1105	* @param pVCpu The cross context virtual CPU structure.
1106	*/
1107	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1108	{
1109	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1110	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1111	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1112
1113	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1114	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1115	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1116	}
1117
1118
1119	/**
1120	* Frees memory allocated for the VMX hardware virtualization state.
1121	*
1122	* @param pVM The cross context VM structure.
1123	*/
1124	static void cpumR3FreeVmxHwVirtState(PVM pVM)
1125	{
1126	Assert(pVM->cpum.s.GuestFeatures.fVmx);
1127	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1128	{
1129	PVMCPU pVCpu = &pVM->aCpus[i];
1130	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1131
1132	if (pCtx->hwvirt.vmx.pVmcsR3)
1133	{
1134	SUPR3ContFree(pCtx->hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
1135	pCtx->hwvirt.vmx.pVmcsR3 = NULL;
1136	}
1137	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1138	{
1139	SUPR3ContFree(pCtx->hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
1140	pCtx->hwvirt.vmx.pShadowVmcsR3 = NULL;
1141	}
1142	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1143	{
1144	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1145	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = NULL;
1146	}
1147	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1148	{
1149	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1150	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
1151	}
1152	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1153	{
1154	SUPR3ContFree(pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1155	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = NULL;
1156	}
1157	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1158	{
1159	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1160	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = NULL;
1161	}
1162	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1163	{
1164	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1165	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = NULL;
1166	}
1167	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1168	{
1169	SUPR3ContFree(pCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
1170	pCtx->hwvirt.vmx.pvMsrBitmapR3 = NULL;
1171	}
1172	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1173	{
1174	SUPR3ContFree(pCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1175	pCtx->hwvirt.vmx.pvIoBitmapR3 = NULL;
1176	}
1177	}
1178	}
1179
1180
1181	/**
1182	* Allocates memory for the VMX hardware virtualization state.
1183	*
1184	* @returns VBox status code.
1185	* @param pVM The cross context VM structure.
1186	*/
1187	static int cpumR3AllocVmxHwVirtState(PVM pVM)
1188	{
1189	int rc = VINF_SUCCESS;
1190	uint32_t const cPages = VMX_V_VMCS_PAGES
1191	+ VMX_V_SHADOW_VMCS_PAGES
1192	+ VMX_V_VIRT_APIC_PAGES
1193	+ (2 * VMX_V_VMREAD_VMWRITE_BITMAP_PAGES)
1194	+ (3 * VMX_V_AUTOMSR_AREA_PAGES)
1195	+ VMX_V_MSR_BITMAP_PAGES
1196	+ (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1197	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n", pVM->cCpus * cPages));
1198	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1199	{
1200	PVMCPU pVCpu = &pVM->aCpus[i];
1201	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1202	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1203
1204	/*
1205	* Allocate the nested-guest current VMCS.
1206	*/
1207	pCtx->hwvirt.vmx.pVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1208	&pCtx->hwvirt.vmx.pVmcsR0,
1209	&pCtx->hwvirt.vmx.HCPhysVmcs);
1210	if (pCtx->hwvirt.vmx.pVmcsR3)
1211	{ /* likely */ }
1212	else
1213	{
1214	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1215	break;
1216	}
1217
1218	/*
1219	* Allocate the nested-guest shadow VMCS.
1220	*/
1221	pCtx->hwvirt.vmx.pShadowVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1222	&pCtx->hwvirt.vmx.pShadowVmcsR0,
1223	&pCtx->hwvirt.vmx.HCPhysShadowVmcs);
1224	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1225	{ /* likely */ }
1226	else
1227	{
1228	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1229	break;
1230	}
1231
1232	/*
1233	* Allocate the VMREAD-bitmap.
1234	*/
1235	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1236	&pCtx->hwvirt.vmx.pvVmreadBitmapR0,
1237	&pCtx->hwvirt.vmx.HCPhysVmreadBitmap);
1238	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1239	{ /* likely */ }
1240	else
1241	{
1242	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1243	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1244	break;
1245	}
1246
1247	/*
1248	* Allocatge the VMWRITE-bitmap.
1249	*/
1250	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1251	&pCtx->hwvirt.vmx.pvVmwriteBitmapR0,
1252	&pCtx->hwvirt.vmx.HCPhysVmwriteBitmap);
1253	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1254	{ /* likely */ }
1255	else
1256	{
1257	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1258	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1259	break;
1260	}
1261
1262	/*
1263	* Allocate the VM-entry MSR-load area.
1264	*/
1265	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1266	&pCtx->hwvirt.vmx.pEntryMsrLoadAreaR0,
1267	&pCtx->hwvirt.vmx.HCPhysEntryMsrLoadArea);
1268	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1269	{ /* likely */ }
1270	else
1271	{
1272	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-entry MSR-load area\n", pVCpu->idCpu,
1273	VMX_V_AUTOMSR_AREA_PAGES));
1274	break;
1275	}
1276
1277	/*
1278	* Allocate the VM-exit MSR-store area.
1279	*/
1280	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1281	&pCtx->hwvirt.vmx.pExitMsrStoreAreaR0,
1282	&pCtx->hwvirt.vmx.HCPhysExitMsrStoreArea);
1283	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1284	{ /* likely */ }
1285	else
1286	{
1287	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-store area\n", pVCpu->idCpu,
1288	VMX_V_AUTOMSR_AREA_PAGES));
1289	break;
1290	}
1291
1292	/*
1293	* Allocate the VM-exit MSR-load area.
1294	*/
1295	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1296	&pCtx->hwvirt.vmx.pExitMsrLoadAreaR0,
1297	&pCtx->hwvirt.vmx.HCPhysExitMsrLoadArea);
1298	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1299	{ /* likely */ }
1300	else
1301	{
1302	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-load area\n", pVCpu->idCpu,
1303	VMX_V_AUTOMSR_AREA_PAGES));
1304	break;
1305	}
1306
1307	/*
1308	* Allocate the MSR bitmap.
1309	*/
1310	pCtx->hwvirt.vmx.pvMsrBitmapR3 = SUPR3ContAlloc(VMX_V_MSR_BITMAP_PAGES,
1311	&pCtx->hwvirt.vmx.pvMsrBitmapR0,
1312	&pCtx->hwvirt.vmx.HCPhysMsrBitmap);
1313	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1314	{ /* likely */ }
1315	else
1316	{
1317	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1318	VMX_V_MSR_BITMAP_PAGES));
1319	break;
1320	}
1321
1322	/*
1323	* Allocate the I/O bitmaps (A and B).
1324	*/
1325	pCtx->hwvirt.vmx.pvIoBitmapR3 = SUPR3ContAlloc(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES,
1326	&pCtx->hwvirt.vmx.pvIoBitmapR0,
1327	&pCtx->hwvirt.vmx.HCPhysIoBitmap);
1328	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1329	{ /* likely */ }
1330	else
1331	{
1332	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1333	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1334	break;
1335	}
1336
1337	/*
1338	* Zero out all allocated pages (should compress well for saved-state).
1339	*/
1340	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1341	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1342	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmreadBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1343	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1344	memset(pCtx->hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1345	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1346	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1347	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvMsrBitmap), 0, VMX_V_MSR_BITMAP_SIZE);
1348	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap), 0, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1349	}
1350
1351	/* On any failure, cleanup. */
1352	if (RT_FAILURE(rc))
1353	cpumR3FreeVmxHwVirtState(pVM);
1354
1355	return rc;
1356	}
1357
1358
1359	/**
1360	* Resets per-VCPU VMX hardware virtualization state.
1361	*
1362	* @param pVCpu The cross context virtual CPU structure.
1363	*/
1364	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1365	{
1366	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1367	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1368	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1369	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1370
1371	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1372	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1373	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1374	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1375	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1376	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1377	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1378	/* Don't reset diagnostics here. */
1379	}
1380
1381
1382	/**
1383	* Displays the host and guest VMX features.
1384	*
1385	* @param pVM The cross context VM structure.
1386	* @param pHlp The info helper functions.
1387	* @param pszArgs "terse", "default" or "verbose".
1388	*/
1389	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1390	{
1391	RT_NOREF(pszArgs);
1392	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1393	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1394	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1395	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1396	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1397	{
1398	#define VMXFEATDUMP(a_szDesc, a_Var) \
1399	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1400
1401	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1402	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1403	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1404	/* Basic. */
1405	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1406	/* Pin-based controls. */
1407	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1408	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1409	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1410	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1411	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1412	/* Processor-based controls. */
1413	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1414	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1415	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1416	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1417	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1418	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1419	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1420	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1421	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1422	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1423	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1424	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1425	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1426	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1427	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1428	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1429	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1430	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1431	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1432	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1433	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1434	/* Secondary processor-based controls. */
1435	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1436	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1437	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1438	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1439	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1440	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1441	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1442	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1443	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1444	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1445	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1446	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1447	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1448	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1449	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1450	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1451	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1452	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1453	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1454	/* VM-entry controls. */
1455	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1456	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1457	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1458	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1459	/* VM-exit controls. */
1460	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1461	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1462	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1463	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1464	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1465	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1466	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1467	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1468	/* Miscellaneous data. */
1469	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1470	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1471	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1472	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1473	#undef VMXFEATDUMP
1474	}
1475	else
1476	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1477	}
1478
1479
1480	/**
1481	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1482	* or NEM) is allowed.
1483	*
1484	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1485	* otherwise.
1486	* @param pVM The cross context VM structure.
1487	*/
1488	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1489	{
1490	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1491	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1492	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1493	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1494	return true;
1495	#else
1496	NOREF(pVM);
1497	#endif
1498	return false;
1499	}
1500
1501
1502	/**
1503	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1504	*
1505	* @param pVM The cross context VM structure.
1506	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1507	* and no hardware-assisted nested-guest execution is
1508	* possible for this VM.
1509	* @param pGuestFeatures The guest features to use (only VMX features are
1510	* accessed).
1511	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1512	*
1513	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1514	*/
1515	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1516	{
1517	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1518
1519	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1520	Assert(pGuestFeatures->fVmx);
1521
1522	/*
1523	* We don't support the following MSRs yet:
1524	* - True Pin-based VM-execution controls.
1525	* - True Processor-based VM-execution controls.
1526	* - True VM-entry VM-execution controls.
1527	* - True VM-exit VM-execution controls.
1528	*/
1529
1530	/* Feature control. */
1531	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1532
1533	/* Basic information. */
1534	{
1535	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1536	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1537	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1538	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1539	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1540	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1541	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1542	pGuestVmxMsrs->u64Basic = u64Basic;
1543	}
1544
1545	/* Pin-based VM-execution controls. */
1546	{
1547	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1548	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1549	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1550	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1551	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1552	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1553	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1554	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1555	fAllowed0, fAllowed1, fFeatures));
1556	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1557	}
1558
1559	/* Processor-based VM-execution controls. */
1560	{
1561	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1562	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1563	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1564	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1565	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1566	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1567	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1568	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1569	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1570	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1571	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1572	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1573	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1574	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1575	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1576	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1577	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1578	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1579	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1580	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1581	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1582	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1583	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1584	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1585	fAllowed1, fFeatures));
1586	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1587	}
1588
1589	/* Secondary processor-based VM-execution controls. */
1590	if (pGuestFeatures->fVmxSecondaryExecCtls)
1591	{
1592	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1593	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1594	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1595	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1596	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1597	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1598	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1599	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1600	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1601	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1602	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1603	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1604	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1605	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1606	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1607	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1608	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1609	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1610	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1611	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1612	uint32_t const fAllowed0 = 0;
1613	uint32_t const fAllowed1 = fFeatures;
1614	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1615	}
1616
1617	/* VM-exit controls. */
1618	{
1619	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1620	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1621	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1622	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1623	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1624	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1625	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1626	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1627	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1628	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1629	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1630	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1631	fAllowed1, fFeatures));
1632	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1633	}
1634
1635	/* VM-entry controls. */
1636	{
1637	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1638	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1639	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1640	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1641	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1642	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1643	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1644	fAllowed1, fFeatures));
1645	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1646	}
1647
1648	/* Miscellaneous data. */
1649	{
1650	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1651
1652	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1653	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1654	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1655	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1656	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1657	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1658	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1659	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1660	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1661	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1662	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1663	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1664	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1665	}
1666
1667	/* CR0 Fixed-0. */
1668	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1669
1670	/* CR0 Fixed-1. */
1671	{
1672	/*
1673	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1674	* This is different from CR4 fixed-1 bits which are reported as per the
1675	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1676	*/
1677	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1678	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1679	}
1680
1681	/* CR4 Fixed-0. */
1682	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1683
1684	/* CR4 Fixed-1. */
1685	{
1686	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1687	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1688	}
1689
1690	/* VMCS Enumeration. */
1691	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1692
1693	/* VPID and EPT Capabilities. */
1694	{
1695	/*
1696	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1697	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1698	* when INVVPID instruction is supported just to be more compatible with guest
1699	* hypervisors that may make assumptions by only looking at this MSR even though they
1700	* are technically supposed to refer to bit 37 of MSR_IA32_VMX_PROC_CTLS2 first.
1701	*
1702	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1703	* See Intel spec. 30.3 "VMX Instructions".
1704	*/
1705	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1706	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1707	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & 1)
1708	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & 1)
1709	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & 1);
1710	}
1711
1712	/* VM Functions. */
1713	if (pGuestFeatures->fVmxVmFunc)
1714	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1715	}
1716
1717
1718	/**
1719	* Checks whether the given guest CPU VMX features are compatible with the provided
1720	* base features.
1721	*
1722	* @returns @c true if compatible, @c false otherwise.
1723	* @param pVM The cross context VM structure.
1724	* @param pBase The base VMX CPU features.
1725	* @param pGst The guest VMX CPU features.
1726	*
1727	* @remarks Only VMX feature bits are examined.
1728	*/
1729	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1730	{
1731	if (cpumR3IsHwAssistNstGstExecAllowed(pVM))
1732	{
1733	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1734	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1735	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1736	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1737	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1738	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1739	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1740	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1741	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1742	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1743	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1744	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1745	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1746	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1747	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1748	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1749	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1750	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1751	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1752	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1753	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1754	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1755	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1756	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1757	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1758	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1759	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1760	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1761	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1762	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1763	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1764	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1765
1766	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1767	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1768	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1769	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1770	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1771	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1772	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1773	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1774	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1775	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1776	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1777	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1778	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1779	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1780	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1781	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1782	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1783	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1784	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1785	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1786	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1787	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1788	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1789	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1790	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1791	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1792	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1793	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1794	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1795	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1796	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1797	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1798
1799	if ((fBase \| fGst) != fBase)
1800	{
1801	LogRel(("CPUM: Host VMX features are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64\n",
1802	fBase, fGst));
1803	return false;
1804	}
1805	return true;
1806	}
1807	return true;
1808	}
1809
1810
1811	/**
1812	* Initializes VMX guest features and MSRs.
1813	*
1814	* @param pVM The cross context VM structure.
1815	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1816	* and no hardware-assisted nested-guest execution is
1817	* possible for this VM.
1818	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1819	*/
1820	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1821	{
1822	Assert(pVM);
1823	Assert(pGuestVmxMsrs);
1824
1825	/*
1826	* Initialize the set of VMX features we emulate.
1827	*
1828	* Note! Some bits might be reported as 1 always if they fall under the
1829	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1830	*/
1831	CPUMFEATURES EmuFeat;
1832	RT_ZERO(EmuFeat);
1833	EmuFeat.fVmx = 1;
1834	EmuFeat.fVmxInsOutInfo = 0;
1835	EmuFeat.fVmxExtIntExit = 1;
1836	EmuFeat.fVmxNmiExit = 1;
1837	EmuFeat.fVmxVirtNmi = 0;
1838	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1839	EmuFeat.fVmxPostedInt = 0;
1840	EmuFeat.fVmxIntWindowExit = 1;
1841	EmuFeat.fVmxTscOffsetting = 1;
1842	EmuFeat.fVmxHltExit = 1;
1843	EmuFeat.fVmxInvlpgExit = 1;
1844	EmuFeat.fVmxMwaitExit = 1;
1845	EmuFeat.fVmxRdpmcExit = 1;
1846	EmuFeat.fVmxRdtscExit = 1;
1847	EmuFeat.fVmxCr3LoadExit = 1;
1848	EmuFeat.fVmxCr3StoreExit = 1;
1849	EmuFeat.fVmxCr8LoadExit = 1;
1850	EmuFeat.fVmxCr8StoreExit = 1;
1851	EmuFeat.fVmxUseTprShadow = 0;
1852	EmuFeat.fVmxNmiWindowExit = 0;
1853	EmuFeat.fVmxMovDRxExit = 1;
1854	EmuFeat.fVmxUncondIoExit = 1;
1855	EmuFeat.fVmxUseIoBitmaps = 1;
1856	EmuFeat.fVmxMonitorTrapFlag = 0;
1857	EmuFeat.fVmxUseMsrBitmaps = 1;
1858	EmuFeat.fVmxMonitorExit = 1;
1859	EmuFeat.fVmxPauseExit = 1;
1860	EmuFeat.fVmxSecondaryExecCtls = 1;
1861	EmuFeat.fVmxVirtApicAccess = 0;
1862	EmuFeat.fVmxEpt = 0;
1863	EmuFeat.fVmxDescTableExit = 1;
1864	EmuFeat.fVmxRdtscp = 1;
1865	EmuFeat.fVmxVirtX2ApicMode = 0;
1866	EmuFeat.fVmxVpid = 0; /** @todo NSTVMX: enable this. */
1867	EmuFeat.fVmxWbinvdExit = 1;
1868	EmuFeat.fVmxUnrestrictedGuest = 0;
1869	EmuFeat.fVmxApicRegVirt = 0;
1870	EmuFeat.fVmxVirtIntDelivery = 0;
1871	EmuFeat.fVmxPauseLoopExit = 0;
1872	EmuFeat.fVmxRdrandExit = 0;
1873	EmuFeat.fVmxInvpcid = 1;
1874	EmuFeat.fVmxVmFunc = 0;
1875	EmuFeat.fVmxVmcsShadowing = 0;
1876	EmuFeat.fVmxRdseedExit = 0;
1877	EmuFeat.fVmxPml = 0;
1878	EmuFeat.fVmxEptXcptVe = 0;
1879	EmuFeat.fVmxXsavesXrstors = 0;
1880	EmuFeat.fVmxUseTscScaling = 0;
1881	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1882	EmuFeat.fVmxIa32eModeGuest = 1;
1883	EmuFeat.fVmxEntryLoadEferMsr = 1;
1884	EmuFeat.fVmxEntryLoadPatMsr = 0;
1885	EmuFeat.fVmxExitSaveDebugCtls = 1;
1886	EmuFeat.fVmxHostAddrSpaceSize = 1;
1887	EmuFeat.fVmxExitAckExtInt = 0;
1888	EmuFeat.fVmxExitSavePatMsr = 0;
1889	EmuFeat.fVmxExitLoadPatMsr = 0;
1890	EmuFeat.fVmxExitSaveEferMsr = 1;
1891	EmuFeat.fVmxExitLoadEferMsr = 1;
1892	EmuFeat.fVmxSavePreemptTimer = 0;
1893	EmuFeat.fVmxExitSaveEferLma = 1;
1894	EmuFeat.fVmxIntelPt = 0;
1895	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1896	EmuFeat.fVmxEntryInjectSoftInt = 0;
1897
1898	/*
1899	* Merge guest features.
1900	*
1901	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1902	* by the hardware, hence we merge our emulated features with the host features below.
1903	*/
1904	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1905	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1906	Assert(pBaseFeat->fVmx);
1907	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1908	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1909	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1910	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1911	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1912	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1913	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1914	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1915	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1916	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1917	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1918	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1919	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1920	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1921	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1922	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1923	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1924	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1925	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1926	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1927	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1928	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1929	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1930	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1931	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1932	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1933	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1934	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1935	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1936	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1937	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1938	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1939	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1940	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1941	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1942	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1943	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1944	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1945	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1946	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1947	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1948	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1949	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1950	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1951	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1952	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1953	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1954	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1955	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1956	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1957	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1958	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1959	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1960	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1961	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1962	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1963	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1964	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1965	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1966	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1967	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1968	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1969	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1970
1971	/* Paranoia. */
1972	if (!pGuestFeat->fVmxSecondaryExecCtls)
1973	{
1974	Assert(!pGuestFeat->fVmxVirtApicAccess);
1975	Assert(!pGuestFeat->fVmxEpt);
1976	Assert(!pGuestFeat->fVmxDescTableExit);
1977	Assert(!pGuestFeat->fVmxRdtscp);
1978	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1979	Assert(!pGuestFeat->fVmxVpid);
1980	Assert(!pGuestFeat->fVmxWbinvdExit);
1981	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1982	Assert(!pGuestFeat->fVmxApicRegVirt);
1983	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1984	Assert(!pGuestFeat->fVmxPauseLoopExit);
1985	Assert(!pGuestFeat->fVmxRdrandExit);
1986	Assert(!pGuestFeat->fVmxInvpcid);
1987	Assert(!pGuestFeat->fVmxVmFunc);
1988	Assert(!pGuestFeat->fVmxVmcsShadowing);
1989	Assert(!pGuestFeat->fVmxRdseedExit);
1990	Assert(!pGuestFeat->fVmxPml);
1991	Assert(!pGuestFeat->fVmxEptXcptVe);
1992	Assert(!pGuestFeat->fVmxXsavesXrstors);
1993	Assert(!pGuestFeat->fVmxUseTscScaling);
1994	}
1995	if (pGuestFeat->fVmxUnrestrictedGuest)
1996	{
1997	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1998	Assert(pGuestFeat->fVmxExitSaveEferLma);
1999	}
2000
2001	/*
2002	* Finally initialize the VMX guest MSRs.
2003	*/
2004	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2005	}
2006
2007
2008	/**
2009	* Gets the host hardware-virtualization MSRs.
2010	*
2011	* @returns VBox status code.
2012	* @param pMsrs Where to store the MSRs.
2013	*/
2014	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2015	{
2016	Assert(pMsrs);
2017
2018	uint32_t fCaps = 0;
2019	int rc = SUPR3QueryVTCaps(&fCaps);
2020	if (RT_SUCCESS(rc))
2021	{
2022	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2023	{
2024	SUPHWVIRTMSRS HwvirtMsrs;
2025	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2026	if (RT_SUCCESS(rc))
2027	{
2028	if (fCaps & SUPVTCAPS_VT_X)
2029	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2030	else
2031	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2032	return VINF_SUCCESS;
2033	}
2034
2035	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2036	return rc;
2037	}
2038	else
2039	{
2040	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2041	return VERR_INTERNAL_ERROR_5;
2042	}
2043	}
2044	else
2045	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2046
2047	return VINF_SUCCESS;
2048	}
2049
2050
2051	/**
2052	* Initializes the CPUM.
2053	*
2054	* @returns VBox status code.
2055	* @param pVM The cross context VM structure.
2056	*/
2057	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2058	{
2059	LogFlow(("CPUMR3Init\n"));
2060
2061	/*
2062	* Assert alignment, sizes and tables.
2063	*/
2064	AssertCompileMemberAlignment(VM, cpum.s, 32);
2065	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2066	AssertCompileSizeAlignment(CPUMCTX, 64);
2067	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2068	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2069	AssertCompileMemberAlignment(VM, cpum, 64);
2070	AssertCompileMemberAlignment(VM, aCpus, 64);
2071	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2072	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
2073	#ifdef VBOX_STRICT
2074	int rc2 = cpumR3MsrStrictInitChecks();
2075	AssertRCReturn(rc2, rc2);
2076	#endif
2077
2078	/*
2079	* Initialize offsets.
2080	*/
2081
2082	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
2083	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
2084	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
2085
2086
2087	/* Calculate the offset from CPUMCPU to CPUM. */
2088	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2089	{
2090	PVMCPU pVCpu = &pVM->aCpus[i];
2091
2092	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
2093	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
2094	}
2095
2096	/*
2097	* Gather info about the host CPU.
2098	*/
2099	if (!ASMHasCpuId())
2100	{
2101	LogRel(("The CPU doesn't support CPUID!\n"));
2102	return VERR_UNSUPPORTED_CPU;
2103	}
2104
2105	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2106
2107	CPUMMSRS HostMsrs;
2108	RT_ZERO(HostMsrs);
2109	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2110	AssertLogRelRCReturn(rc, rc);
2111
2112	PCPUMCPUIDLEAF paLeaves;
2113	uint32_t cLeaves;
2114	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
2115	AssertLogRelRCReturn(rc, rc);
2116
2117	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
2118	RTMemFree(paLeaves);
2119	AssertLogRelRCReturn(rc, rc);
2120	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2121
2122	/*
2123	* Check that the CPU supports the minimum features we require.
2124	*/
2125	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2126	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2127	if (!pVM->cpum.s.HostFeatures.fMmx)
2128	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2129	if (!pVM->cpum.s.HostFeatures.fTsc)
2130	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2131
2132	/*
2133	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2134	*/
2135	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2136	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2137
2138	/*
2139	* Figure out which XSAVE/XRSTOR features are available on the host.
2140	*/
2141	uint64_t fXcr0Host = 0;
2142	uint64_t fXStateHostMask = 0;
2143	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2144	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2145	{
2146	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2147	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2148	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2149	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2150	}
2151	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2152	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
2153	fXStateHostMask = 0;
2154	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2155	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2156
2157	/*
2158	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
2159	*/
2160	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2161	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2162	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
2163
2164	uint8_t *pbXStates;
2165	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
2166	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
2167	AssertLogRelRCReturn(rc, rc);
2168
2169	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2170	{
2171	PVMCPU pVCpu = &pVM->aCpus[i];
2172
2173	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2174	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2175	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
2176	pbXStates += cbMaxXState;
2177
2178	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2179	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2180	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
2181	pbXStates += cbMaxXState;
2182
2183	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2184	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2185	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
2186	pbXStates += cbMaxXState;
2187
2188	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2189	}
2190
2191	/*
2192	* Register saved state data item.
2193	*/
2194	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2195	NULL, cpumR3LiveExec, NULL,
2196	NULL, cpumR3SaveExec, NULL,
2197	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2198	if (RT_FAILURE(rc))
2199	return rc;
2200
2201	/*
2202	* Register info handlers and registers with the debugger facility.
2203	*/
2204	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2205	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2206	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2207	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2208	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2209	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2210	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2211	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2212	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2213	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2214	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2215	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2216	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2217	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2218	&cpumR3InfoVmxFeatures);
2219
2220	rc = cpumR3DbgInit(pVM);
2221	if (RT_FAILURE(rc))
2222	return rc;
2223
2224	/*
2225	* Check if we need to workaround partial/leaky FPU handling.
2226	*/
2227	cpumR3CheckLeakyFpu(pVM);
2228
2229	/*
2230	* Initialize the Guest CPUID and MSR states.
2231	*/
2232	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2233	if (RT_FAILURE(rc))
2234	return rc;
2235
2236	/*
2237	* Allocate memory required by the guest hardware-virtualization structures.
2238	* This must be done after initializing CPUID/MSR features as we access the
2239	* the VMX/SVM guest features below.
2240	*/
2241	if (pVM->cpum.s.GuestFeatures.fVmx)
2242	rc = cpumR3AllocVmxHwVirtState(pVM);
2243	else if (pVM->cpum.s.GuestFeatures.fSvm)
2244	rc = cpumR3AllocSvmHwVirtState(pVM);
2245	else
2246	Assert(pVM->aCpus[0].cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2247	if (RT_FAILURE(rc))
2248	return rc;
2249
2250	/*
2251	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
2252	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
2253	* of processors from (cpuid(4).eax >> 26) + 1.
2254	*
2255	* Note: this code is obsolete, but let's keep it here for reference.
2256	* Purpose is valid when we artificially cap the max std id to less than 4.
2257	*
2258	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
2259	* after VMINITCOMPLETED_HM.
2260	*/
2261	if (VM_IS_RAW_MODE_ENABLED(pVM))
2262	{
2263	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
2264	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
2265	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
2266	}
2267
2268	CPUMR3Reset(pVM);
2269	return VINF_SUCCESS;
2270	}
2271
2272
2273	/**
2274	* Applies relocations to data and code managed by this
2275	* component. This function will be called at init and
2276	* whenever the VMM need to relocate it self inside the GC.
2277	*
2278	* The CPUM will update the addresses used by the switcher.
2279	*
2280	* @param pVM The cross context VM structure.
2281	*/
2282	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2283	{
2284	LogFlow(("CPUMR3Relocate\n"));
2285
2286	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
2287	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
2288
2289	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2290	{
2291	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2292	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
2293	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
2294	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
2295
2296	/* Recheck the guest DRx values in raw-mode. */
2297	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
2298	}
2299	}
2300
2301
2302	/**
2303	* Terminates the CPUM.
2304	*
2305	* Termination means cleaning up and freeing all resources,
2306	* the VM it self is at this point powered off or suspended.
2307	*
2308	* @returns VBox status code.
2309	* @param pVM The cross context VM structure.
2310	*/
2311	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2312	{
2313	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2314	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2315	{
2316	PVMCPU pVCpu = &pVM->aCpus[i];
2317	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2318
2319	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2320	pVCpu->cpum.s.uMagic = 0;
2321	pCtx->dr[5] = 0;
2322	}
2323	#endif
2324
2325	if (pVM->cpum.s.GuestFeatures.fVmx)
2326	cpumR3FreeVmxHwVirtState(pVM);
2327	else if (pVM->cpum.s.GuestFeatures.fSvm)
2328	cpumR3FreeSvmHwVirtState(pVM);
2329	return VINF_SUCCESS;
2330	}
2331
2332
2333	/**
2334	* Resets a virtual CPU.
2335	*
2336	* Used by CPUMR3Reset and CPU hot plugging.
2337	*
2338	* @param pVM The cross context VM structure.
2339	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2340	* being reset. This may differ from the current EMT.
2341	*/
2342	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2343	{
2344	/** @todo anything different for VCPU > 0? */
2345	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2346
2347	/*
2348	* Initialize everything to ZERO first.
2349	*/
2350	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2351
2352	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
2353	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
2354	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
2355
2356	pVCpu->cpum.s.fUseFlags = fUseFlags;
2357
2358	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2359	pCtx->eip = 0x0000fff0;
2360	pCtx->edx = 0x00000600; /* P6 processor */
2361	pCtx->eflags.Bits.u1Reserved0 = 1;
2362
2363	pCtx->cs.Sel = 0xf000;
2364	pCtx->cs.ValidSel = 0xf000;
2365	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2366	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2367	pCtx->cs.u32Limit = 0x0000ffff;
2368	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2369	pCtx->cs.Attr.n.u1Present = 1;
2370	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2371
2372	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2373	pCtx->ds.u32Limit = 0x0000ffff;
2374	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2375	pCtx->ds.Attr.n.u1Present = 1;
2376	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2377
2378	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2379	pCtx->es.u32Limit = 0x0000ffff;
2380	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2381	pCtx->es.Attr.n.u1Present = 1;
2382	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2383
2384	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2385	pCtx->fs.u32Limit = 0x0000ffff;
2386	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2387	pCtx->fs.Attr.n.u1Present = 1;
2388	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2389
2390	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2391	pCtx->gs.u32Limit = 0x0000ffff;
2392	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2393	pCtx->gs.Attr.n.u1Present = 1;
2394	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2395
2396	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2397	pCtx->ss.u32Limit = 0x0000ffff;
2398	pCtx->ss.Attr.n.u1Present = 1;
2399	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2400	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2401
2402	pCtx->idtr.cbIdt = 0xffff;
2403	pCtx->gdtr.cbGdt = 0xffff;
2404
2405	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2406	pCtx->ldtr.u32Limit = 0xffff;
2407	pCtx->ldtr.Attr.n.u1Present = 1;
2408	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2409
2410	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2411	pCtx->tr.u32Limit = 0xffff;
2412	pCtx->tr.Attr.n.u1Present = 1;
2413	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2414
2415	pCtx->dr[6] = X86_DR6_INIT_VAL;
2416	pCtx->dr[7] = X86_DR7_INIT_VAL;
2417
2418	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
2419	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2420	pFpuCtx->FCW = 0x37f;
2421
2422	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2423	IA-32 Processor States Following Power-up, Reset, or INIT */
2424	pFpuCtx->MXCSR = 0x1F80;
2425	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2426
2427	pCtx->aXcr[0] = XSAVE_C_X87;
2428	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2429	{
2430	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2431	as we don't know what happened before. (Bother optimize later?) */
2432	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2433	}
2434
2435	/*
2436	* MSRs.
2437	*/
2438	/* Init PAT MSR */
2439	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2440
2441	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2442	* The Intel docs don't mention it. */
2443	Assert(!pCtx->msrEFER);
2444
2445	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2446	is supposed to be here, just trying provide useful/sensible values. */
2447	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2448	if (pRange)
2449	{
2450	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2451	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2452	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2453	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2454	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2455	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2456	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2457	}
2458
2459	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2460
2461	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2462	* called from each EMT while we're getting called by CPUMR3Reset()
2463	* iteratively on the same thread. Fix later. */
2464	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2465	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2466	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2467	#endif
2468
2469
2470	/* C-state control. Guesses. */
2471	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2472	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2473	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2474	* functionality. The default value must be different due to incompatible write mask.
2475	*/
2476	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2477	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2478	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2479	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2480
2481	/*
2482	* Hardware virtualization state.
2483	*/
2484	CPUMSetGuestGif(pCtx, true);
2485	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2486	if (pVM->cpum.s.GuestFeatures.fVmx)
2487	cpumR3ResetVmxHwVirtState(pVCpu);
2488	else if (pVM->cpum.s.GuestFeatures.fSvm)
2489	cpumR3ResetSvmHwVirtState(pVCpu);
2490	}
2491
2492
2493	/**
2494	* Resets the CPU.
2495	*
2496	* @returns VINF_SUCCESS.
2497	* @param pVM The cross context VM structure.
2498	*/
2499	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2500	{
2501	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2502	{
2503	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
2504
2505	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2506	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
2507
2508	/* Magic marker for searching in crash dumps. */
2509	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
2510	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2511	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2512	#endif
2513	}
2514	}
2515
2516
2517
2518
2519	/**
2520	* Pass 0 live exec callback.
2521	*
2522	* @returns VINF_SSM_DONT_CALL_AGAIN.
2523	* @param pVM The cross context VM structure.
2524	* @param pSSM The saved state handle.
2525	* @param uPass The pass (0).
2526	*/
2527	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2528	{
2529	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2530	cpumR3SaveCpuId(pVM, pSSM);
2531	return VINF_SSM_DONT_CALL_AGAIN;
2532	}
2533
2534
2535	/**
2536	* Execute state save operation.
2537	*
2538	* @returns VBox status code.
2539	* @param pVM The cross context VM structure.
2540	* @param pSSM SSM operation handle.
2541	*/
2542	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2543	{
2544	/*
2545	* Save.
2546	*/
2547	SSMR3PutU32(pSSM, pVM->cCpus);
2548	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2549	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2550	{
2551	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2552
2553	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2554
2555	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2556	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2557	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2558	if (pGstCtx->fXStateMask != 0)
2559	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2560	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2561	{
2562	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2563	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2564	}
2565	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2566	{
2567	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2568	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2569	}
2570	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2571	{
2572	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2573	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2574	}
2575	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2576	{
2577	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2578	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2579	}
2580	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2581	{
2582	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2583	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2584	}
2585	if (pVM->cpum.s.GuestFeatures.fSvm)
2586	{
2587	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2588	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2589	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2590	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2591	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2592	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2593	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2594	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2595	g_aSvmHwvirtHostState, NULL /* pvUser */);
2596	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2597	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2598	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2599	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2600	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2601	}
2602	if (pVM->cpum.s.GuestFeatures.fVmx)
2603	{
2604	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2605	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2606	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2607	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2608	SSMR3PutU32(pSSM, (uint32_t)pGstCtx->hwvirt.vmx.enmDiag);
2609	SSMR3PutU32(pSSM, (uint32_t)pGstCtx->hwvirt.vmx.enmAbort);
2610	SSMR3PutU32(pSSM, pGstCtx->hwvirt.vmx.uAbortAux);
2611	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2612	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2613	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2614	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2615	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2616	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2617	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2618	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2619	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2620	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2621	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2622	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2623	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2624	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2625	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2626	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2627	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2628	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2629	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2630	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2631	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2632	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2633	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2634	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2635	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2636	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2637	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2638	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2639	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2640	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2641	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2642	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2643	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2644	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2645	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2646	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2647	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2648	}
2649	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2650	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2651	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2652	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2653	}
2654
2655	cpumR3SaveCpuId(pVM, pSSM);
2656	return VINF_SUCCESS;
2657	}
2658
2659
2660	/**
2661	* @callback_method_impl{FNSSMINTLOADPREP}
2662	*/
2663	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2664	{
2665	NOREF(pSSM);
2666	pVM->cpum.s.fPendingRestore = true;
2667	return VINF_SUCCESS;
2668	}
2669
2670
2671	/**
2672	* @callback_method_impl{FNSSMINTLOADEXEC}
2673	*/
2674	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2675	{
2676	int rc; /* Only for AssertRCReturn use. */
2677
2678	/*
2679	* Validate version.
2680	*/
2681	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
2682	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2683	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2684	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2685	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2686	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2687	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2688	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2689	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2690	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2691	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2692	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2693	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2694	{
2695	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2696	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2697	}
2698
2699	if (uPass == SSM_PASS_FINAL)
2700	{
2701	/*
2702	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2703	* really old SSM file versions.)
2704	*/
2705	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2706	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2707	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2708	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2709
2710	/*
2711	* Figure x86 and ctx field definitions to use for older states.
2712	*/
2713	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2714	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2715	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2716	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2717	{
2718	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2719	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2720	}
2721	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2722	{
2723	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2724	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2725	}
2726
2727	/*
2728	* The hyper state used to preceed the CPU count. Starting with
2729	* XSAVE it was moved down till after we've got the count.
2730	*/
2731	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2732	{
2733	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2734	{
2735	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2736	X86FXSTATE Ign;
2737	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2738	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2739	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2740	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
2741	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2742	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2743	pVCpu->cpum.s.Hyper.rsp = uRSP;
2744	}
2745	}
2746
2747	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2748	{
2749	uint32_t cCpus;
2750	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2751	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2752	VERR_SSM_UNEXPECTED_DATA);
2753	}
2754	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2755	\|\| pVM->cCpus == 1,
2756	("cCpus=%u\n", pVM->cCpus),
2757	VERR_SSM_UNEXPECTED_DATA);
2758
2759	uint32_t cbMsrs = 0;
2760	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2761	{
2762	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2763	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2764	VERR_SSM_UNEXPECTED_DATA);
2765	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2766	VERR_SSM_UNEXPECTED_DATA);
2767	}
2768
2769	/*
2770	* Do the per-CPU restoring.
2771	*/
2772	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2773	{
2774	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2775	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2776
2777	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2778	{
2779	/*
2780	* The XSAVE saved state layout moved the hyper state down here.
2781	*/
2782	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2783	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2784	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2785	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2786	pVCpu->cpum.s.Hyper.rsp = uRSP;
2787	AssertRCReturn(rc, rc);
2788
2789	/*
2790	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2791	*/
2792	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2793	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2794	AssertRCReturn(rc, rc);
2795
2796	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2797	if (pGstCtx->fXStateMask != 0)
2798	{
2799	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2800	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2801	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2802	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2803	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2804	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2805	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2806	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2807	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2808	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2809	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2810	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2811	}
2812
2813	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2814	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2815	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2816	{
2817	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2818	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2819	VERR_CPUM_INVALID_XCR0);
2820	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2821	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2822	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2823	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2824	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2825	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2826	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2827	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2828	}
2829
2830	/* Check that the XCR1 is zero, as we don't implement it yet. */
2831	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2832
2833	/*
2834	* Restore the individual extended state components we support.
2835	*/
2836	if (pGstCtx->fXStateMask != 0)
2837	{
2838	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2839	0, g_aCpumXSaveHdrFields, NULL);
2840	AssertRCReturn(rc, rc);
2841	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2842	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2843	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2844	VERR_CPUM_INVALID_XSAVE_HDR);
2845	}
2846	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2847	{
2848	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2849	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2850	}
2851	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2852	{
2853	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2854	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2855	}
2856	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2857	{
2858	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2859	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2860	}
2861	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2862	{
2863	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2864	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2865	}
2866	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2867	{
2868	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2869	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2870	}
2871	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2872	{
2873	if (pVM->cpum.s.GuestFeatures.fSvm)
2874	{
2875	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2876	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2877	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2878	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2879	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2880	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2881	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2882	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2883	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2884	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2885	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2886	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2887	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2888	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2889	}
2890	}
2891	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM)
2892	{
2893	if (pVM->cpum.s.GuestFeatures.fVmx)
2894	{
2895	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2896	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2897	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2898	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2899	SSMR3GetU32(pSSM, (uint32_t *)&pGstCtx->hwvirt.vmx.enmDiag);
2900	SSMR3GetU32(pSSM, (uint32_t *)&pGstCtx->hwvirt.vmx.enmAbort);
2901	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.vmx.uAbortAux);
2902	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2903	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2904	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2905	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2906	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2907	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2908	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2909	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2910	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2911	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2912	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2913	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2914	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2915	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2916	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2917	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2918	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2919	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2920	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2921	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2922	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2923	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2924	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2925	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2926	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2927	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2928	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2929	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2930	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2931	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2932	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2933	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2934	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2935	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2936	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2937	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2938	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2939	}
2940	}
2941	}
2942	else
2943	{
2944	/*
2945	* Pre XSAVE saved state.
2946	*/
2947	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2948	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2949	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2950	}
2951
2952	/*
2953	* Restore a couple of flags and the MSRs.
2954	*/
2955	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2956	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2957
2958	rc = VINF_SUCCESS;
2959	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2960	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2961	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2962	{
2963	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2964	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2965	}
2966	AssertRCReturn(rc, rc);
2967
2968	/* REM and other may have cleared must-be-one fields in DR6 and
2969	DR7, fix these. */
2970	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2971	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2972	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2973	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2974	}
2975
2976	/* Older states does not have the internal selector register flags
2977	and valid selector value. Supply those. */
2978	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2979	{
2980	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2981	{
2982	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2983	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2984	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2985	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2986	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2987	if (fValid)
2988	{
2989	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2990	{
2991	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2992	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2993	}
2994
2995	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2996	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2997	}
2998	else
2999	{
3000	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3001	{
3002	paSelReg[iSelReg].fFlags = 0;
3003	paSelReg[iSelReg].ValidSel = 0;
3004	}
3005
3006	/* This might not be 104% correct, but I think it's close
3007	enough for all practical purposes... (REM always loaded
3008	LDTR registers.) */
3009	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3010	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3011	}
3012	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
3013	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
3014	}
3015	}
3016
3017	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
3018	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3019	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3020	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3021	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3022
3023	/*
3024	* A quick sanity check.
3025	*/
3026	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3027	{
3028	PVMCPU pVCpu = &pVM->aCpus[iCpu];
3029	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3030	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3031	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3032	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3033	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3034	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3035	}
3036	}
3037
3038	pVM->cpum.s.fPendingRestore = false;
3039
3040	/*
3041	* Guest CPUIDs (and VMX MSR features).
3042	*/
3043	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3044	{
3045	CPUMMSRS GuestMsrs;
3046	RT_ZERO(GuestMsrs);
3047
3048	CPUMFEATURES BaseFeatures;
3049	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3050	if (fVmxGstFeat)
3051	{
3052	/*
3053	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3054	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3055	* here so we can compare them for compatibility after exploding guest features.
3056	*/
3057	BaseFeatures = pVM->cpum.s.GuestFeatures;
3058
3059	/* Use the VMX MSR features from the saved state while exploding guest features. */
3060	GuestMsrs.hwvirt.vmx = pVM->aCpus[0].cpum.s.Guest.hwvirt.vmx.Msrs;
3061	}
3062
3063	/* Load CPUID and explode guest features. */
3064	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3065	if (fVmxGstFeat)
3066	{
3067	/*
3068	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3069	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3070	* VMX features presented to the guest.
3071	*/
3072	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3073	if (!fIsCompat)
3074	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3075	}
3076	return rc;
3077	}
3078	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3079	}
3080
3081
3082	/**
3083	* @callback_method_impl{FNSSMINTLOADDONE}
3084	*/
3085	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3086	{
3087	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3088	return VINF_SUCCESS;
3089
3090	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3091	if (pVM->cpum.s.fPendingRestore)
3092	{
3093	LogRel(("CPUM: Missing state!\n"));
3094	return VERR_INTERNAL_ERROR_2;
3095	}
3096
3097	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3098	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3099	{
3100	PVMCPU pVCpu = &pVM->aCpus[idCpu];
3101
3102	/* Notify PGM of the NXE states in case they've changed. */
3103	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3104
3105	/* During init. this is done in CPUMR3InitCompleted(). */
3106	if (fSupportsLongMode)
3107	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3108	}
3109	return VINF_SUCCESS;
3110	}
3111
3112
3113	/**
3114	* Checks if the CPUM state restore is still pending.
3115	*
3116	* @returns true / false.
3117	* @param pVM The cross context VM structure.
3118	*/
3119	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3120	{
3121	return pVM->cpum.s.fPendingRestore;
3122	}
3123
3124
3125	/**
3126	* Formats the EFLAGS value into mnemonics.
3127	*
3128	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3129	* @param efl The EFLAGS value.
3130	*/
3131	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3132	{
3133	/*
3134	* Format the flags.
3135	*/
3136	static const struct
3137	{
3138	const char pszSet; const char pszClear; uint32_t fFlag;
3139	} s_aFlags[] =
3140	{
3141	{ "vip",NULL, X86_EFL_VIP },
3142	{ "vif",NULL, X86_EFL_VIF },
3143	{ "ac", NULL, X86_EFL_AC },
3144	{ "vm", NULL, X86_EFL_VM },
3145	{ "rf", NULL, X86_EFL_RF },
3146	{ "nt", NULL, X86_EFL_NT },
3147	{ "ov", "nv", X86_EFL_OF },
3148	{ "dn", "up", X86_EFL_DF },
3149	{ "ei", "di", X86_EFL_IF },
3150	{ "tf", NULL, X86_EFL_TF },
3151	{ "nt", "pl", X86_EFL_SF },
3152	{ "nz", "zr", X86_EFL_ZF },
3153	{ "ac", "na", X86_EFL_AF },
3154	{ "po", "pe", X86_EFL_PF },
3155	{ "cy", "nc", X86_EFL_CF },
3156	};
3157	char *psz = pszEFlags;
3158	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3159	{
3160	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3161	if (pszAdd)
3162	{
3163	strcpy(psz, pszAdd);
3164	psz += strlen(pszAdd);
3165	*psz++ = ' ';
3166	}
3167	}
3168	psz[-1] = '\0';
3169	}
3170
3171
3172	/**
3173	* Formats a full register dump.
3174	*
3175	* @param pVM The cross context VM structure.
3176	* @param pCtx The context to format.
3177	* @param pCtxCore The context core to format.
3178	* @param pHlp Output functions.
3179	* @param enmType The dump type.
3180	* @param pszPrefix Register name prefix.
3181	*/
3182	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3183	const char *pszPrefix)
3184	{
3185	NOREF(pVM);
3186
3187	/*
3188	* Format the EFLAGS.
3189	*/
3190	uint32_t efl = pCtxCore->eflags.u32;
3191	char szEFlags[80];
3192	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3193
3194	/*
3195	* Format the registers.
3196	*/
3197	switch (enmType)
3198	{
3199	case CPUMDUMPTYPE_TERSE:
3200	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3201	pHlp->pfnPrintf(pHlp,
3202	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3203	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3204	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3205	"%sr14=%016RX64 %sr15=%016RX64\n"
3206	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3207	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3208	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3209	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3210	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3211	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3212	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3213	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3214	else
3215	pHlp->pfnPrintf(pHlp,
3216	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3217	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3218	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3219	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3220	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3221	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3222	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3223	break;
3224
3225	case CPUMDUMPTYPE_DEFAULT:
3226	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3227	pHlp->pfnPrintf(pHlp,
3228	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3229	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3230	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3231	"%sr14=%016RX64 %sr15=%016RX64\n"
3232	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3233	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3234	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3235	,
3236	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3237	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3238	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3239	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3240	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3241	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3242	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3243	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3244	else
3245	pHlp->pfnPrintf(pHlp,
3246	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3247	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3248	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3249	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3250	,
3251	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3252	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3253	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3254	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3255	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3256	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3257	break;
3258
3259	case CPUMDUMPTYPE_VERBOSE:
3260	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3261	pHlp->pfnPrintf(pHlp,
3262	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3263	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3264	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3265	"%sr14=%016RX64 %sr15=%016RX64\n"
3266	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3267	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3268	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3269	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3270	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3271	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3272	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3273	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3274	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3275	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3276	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3277	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3278	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3279	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3280	,
3281	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3282	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3283	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3284	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3285	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3286	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3287	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3288	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3289	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3290	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3291	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3292	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3293	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3294	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3295	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3296	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3297	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3298	else
3299	pHlp->pfnPrintf(pHlp,
3300	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3301	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3302	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3303	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3304	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3305	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3306	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3307	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3308	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3309	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3310	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3311	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3312	,
3313	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3314	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3315	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3316	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3317	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3318	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3319	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3320	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3321	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3322	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3323	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3324	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3325
3326	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3327	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3328	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3329	if (pCtx->CTX_SUFF(pXState))
3330	{
3331	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
3332	pHlp->pfnPrintf(pHlp,
3333	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3334	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3335	,
3336	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3337	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3338	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3339	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3340	);
3341	/*
3342	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3343	* not (FP)R0-7 as Intel SDM suggests.
3344	*/
3345	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3346	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3347	{
3348	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3349	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3350	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3351	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3352	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3353	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3354	iExponent -= 16383; /* subtract bias */
3355	/** @todo This isn't entirenly correct and needs more work! */
3356	pHlp->pfnPrintf(pHlp,
3357	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3358	pszPrefix, iST, pszPrefix, iFPR,
3359	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3360	uTag, chSign, iInteger, u64Fraction, iExponent);
3361	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3362	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3363	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3364	else
3365	pHlp->pfnPrintf(pHlp, "\n");
3366	}
3367
3368	/* XMM/YMM/ZMM registers. */
3369	if (pCtx->fXStateMask & XSAVE_C_YMM)
3370	{
3371	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3372	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3373	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3374	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3375	pszPrefix, i, i < 10 ? " " : "",
3376	pYmmHiCtx->aYmmHi[i].au32[3],
3377	pYmmHiCtx->aYmmHi[i].au32[2],
3378	pYmmHiCtx->aYmmHi[i].au32[1],
3379	pYmmHiCtx->aYmmHi[i].au32[0],
3380	pFpuCtx->aXMM[i].au32[3],
3381	pFpuCtx->aXMM[i].au32[2],
3382	pFpuCtx->aXMM[i].au32[1],
3383	pFpuCtx->aXMM[i].au32[0]);
3384	else
3385	{
3386	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3387	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3388	pHlp->pfnPrintf(pHlp,
3389	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3390	pszPrefix, i, i < 10 ? " " : "",
3391	pZmmHi256->aHi256Regs[i].au32[7],
3392	pZmmHi256->aHi256Regs[i].au32[6],
3393	pZmmHi256->aHi256Regs[i].au32[5],
3394	pZmmHi256->aHi256Regs[i].au32[4],
3395	pZmmHi256->aHi256Regs[i].au32[3],
3396	pZmmHi256->aHi256Regs[i].au32[2],
3397	pZmmHi256->aHi256Regs[i].au32[1],
3398	pZmmHi256->aHi256Regs[i].au32[0],
3399	pYmmHiCtx->aYmmHi[i].au32[3],
3400	pYmmHiCtx->aYmmHi[i].au32[2],
3401	pYmmHiCtx->aYmmHi[i].au32[1],
3402	pYmmHiCtx->aYmmHi[i].au32[0],
3403	pFpuCtx->aXMM[i].au32[3],
3404	pFpuCtx->aXMM[i].au32[2],
3405	pFpuCtx->aXMM[i].au32[1],
3406	pFpuCtx->aXMM[i].au32[0]);
3407
3408	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3409	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3410	pHlp->pfnPrintf(pHlp,
3411	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3412	pszPrefix, i + 16,
3413	pZmm16Hi->aRegs[i].au32[15],
3414	pZmm16Hi->aRegs[i].au32[14],
3415	pZmm16Hi->aRegs[i].au32[13],
3416	pZmm16Hi->aRegs[i].au32[12],
3417	pZmm16Hi->aRegs[i].au32[11],
3418	pZmm16Hi->aRegs[i].au32[10],
3419	pZmm16Hi->aRegs[i].au32[9],
3420	pZmm16Hi->aRegs[i].au32[8],
3421	pZmm16Hi->aRegs[i].au32[7],
3422	pZmm16Hi->aRegs[i].au32[6],
3423	pZmm16Hi->aRegs[i].au32[5],
3424	pZmm16Hi->aRegs[i].au32[4],
3425	pZmm16Hi->aRegs[i].au32[3],
3426	pZmm16Hi->aRegs[i].au32[2],
3427	pZmm16Hi->aRegs[i].au32[1],
3428	pZmm16Hi->aRegs[i].au32[0]);
3429	}
3430	}
3431	else
3432	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3433	pHlp->pfnPrintf(pHlp,
3434	i & 1
3435	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3436	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3437	pszPrefix, i, i < 10 ? " " : "",
3438	pFpuCtx->aXMM[i].au32[3],
3439	pFpuCtx->aXMM[i].au32[2],
3440	pFpuCtx->aXMM[i].au32[1],
3441	pFpuCtx->aXMM[i].au32[0]);
3442
3443	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3444	{
3445	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3446	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3447	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3448	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3449	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3450	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3451	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3452	}
3453
3454	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3455	{
3456	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3457	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3458	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3459	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3460	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3461	}
3462
3463	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3464	{
3465	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3466	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3467	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3468	}
3469
3470	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3471	if (pFpuCtx->au32RsrvdRest[i])
3472	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3473	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3474	}
3475
3476	pHlp->pfnPrintf(pHlp,
3477	"%sEFER =%016RX64\n"
3478	"%sPAT =%016RX64\n"
3479	"%sSTAR =%016RX64\n"
3480	"%sCSTAR =%016RX64\n"
3481	"%sLSTAR =%016RX64\n"
3482	"%sSFMASK =%016RX64\n"
3483	"%sKERNELGSBASE =%016RX64\n",
3484	pszPrefix, pCtx->msrEFER,
3485	pszPrefix, pCtx->msrPAT,
3486	pszPrefix, pCtx->msrSTAR,
3487	pszPrefix, pCtx->msrCSTAR,
3488	pszPrefix, pCtx->msrLSTAR,
3489	pszPrefix, pCtx->msrSFMASK,
3490	pszPrefix, pCtx->msrKERNELGSBASE);
3491	break;
3492	}
3493	}
3494
3495
3496	/**
3497	* Display all cpu states and any other cpum info.
3498	*
3499	* @param pVM The cross context VM structure.
3500	* @param pHlp The info helper functions.
3501	* @param pszArgs Arguments, ignored.
3502	*/
3503	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3504	{
3505	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3506	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3507	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3508	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3509	cpumR3InfoHost(pVM, pHlp, pszArgs);
3510	}
3511
3512
3513	/**
3514	* Parses the info argument.
3515	*
3516	* The argument starts with 'verbose', 'terse' or 'default' and then
3517	* continues with the comment string.
3518	*
3519	* @param pszArgs The pointer to the argument string.
3520	* @param penmType Where to store the dump type request.
3521	* @param ppszComment Where to store the pointer to the comment string.
3522	*/
3523	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3524	{
3525	if (!pszArgs)
3526	{
3527	*penmType = CPUMDUMPTYPE_DEFAULT;
3528	*ppszComment = "";
3529	}
3530	else
3531	{
3532	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3533	{
3534	pszArgs += 7;
3535	*penmType = CPUMDUMPTYPE_VERBOSE;
3536	}
3537	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3538	{
3539	pszArgs += 5;
3540	*penmType = CPUMDUMPTYPE_TERSE;
3541	}
3542	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3543	{
3544	pszArgs += 7;
3545	*penmType = CPUMDUMPTYPE_DEFAULT;
3546	}
3547	else
3548	*penmType = CPUMDUMPTYPE_DEFAULT;
3549	*ppszComment = RTStrStripL(pszArgs);
3550	}
3551	}
3552
3553
3554	/**
3555	* Display the guest cpu state.
3556	*
3557	* @param pVM The cross context VM structure.
3558	* @param pHlp The info helper functions.
3559	* @param pszArgs Arguments.
3560	*/
3561	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3562	{
3563	CPUMDUMPTYPE enmType;
3564	const char *pszComment;
3565	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3566
3567	PVMCPU pVCpu = VMMGetCpu(pVM);
3568	if (!pVCpu)
3569	pVCpu = &pVM->aCpus[0];
3570
3571	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3572
3573	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3574	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3575	}
3576
3577
3578	/**
3579	* Displays an SVM VMCB control area.
3580	*
3581	* @param pHlp The info helper functions.
3582	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3583	* @param pszPrefix Caller specified string prefix.
3584	*/
3585	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3586	{
3587	AssertReturnVoid(pHlp);
3588	AssertReturnVoid(pVmcbCtrl);
3589
3590	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3591	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3592	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3593	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3594	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3595	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3596	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3597	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3598	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3599	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3600	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3601	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3602	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3603	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3604	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3605	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3606	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3607	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3608	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3609	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3610	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3611	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3612	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3613	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3614	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3615	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3616	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3617	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3618	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3619	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3620	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3621	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3622	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3623	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3624	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3625	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3626	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3627	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3628	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3629	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3630	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3631	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3632	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3633	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3634	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3635	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3636	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3637	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3638	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3639	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3640	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3641	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3642	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3643	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3644	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3645	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3646	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3647	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3648	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3649	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3650	}
3651
3652
3653	/**
3654	* Helper for dumping the SVM VMCB selector registers.
3655	*
3656	* @param pHlp The info helper functions.
3657	* @param pSel Pointer to the SVM selector register.
3658	* @param pszName Name of the selector.
3659	* @param pszPrefix Caller specified string prefix.
3660	*/
3661	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3662	{
3663	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3664	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3665	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3666	}
3667
3668
3669	/**
3670	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3671	*
3672	* @param pHlp The info helper functions.
3673	* @param pXdtr Pointer to the descriptor table register.
3674	* @param pszName Name of the descriptor table register.
3675	* @param pszPrefix Caller specified string prefix.
3676	*/
3677	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3678	{
3679	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3680	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3681	}
3682
3683
3684	/**
3685	* Displays an SVM VMCB state-save area.
3686	*
3687	* @param pHlp The info helper functions.
3688	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3689	* @param pszPrefix Caller specified string prefix.
3690	*/
3691	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3692	{
3693	AssertReturnVoid(pHlp);
3694	AssertReturnVoid(pVmcbStateSave);
3695
3696	char szEFlags[80];
3697	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3698
3699	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3700	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3701	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3702	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3703	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3704	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3705	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3706	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3707	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3708	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3709	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3710	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3711	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3712	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3713	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3714	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3715	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3716	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3717	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3718	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3719	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3720	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3721	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3722	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3723	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3724	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3725	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3726	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3727	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3728	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3729	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3730	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3731	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3732	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3733	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3734	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3735	}
3736
3737
3738	/**
3739	* Displays a virtual-VMCS.
3740	*
3741	* @param pHlp The info helper functions.
3742	* @param pVmcs Pointer to a virtual VMCS.
3743	* @param pszPrefix Caller specified string prefix.
3744	*/
3745	static void cpumR3InfoVmxVmcs(PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3746	{
3747	AssertReturnVoid(pHlp);
3748	AssertReturnVoid(pVmcs);
3749
3750	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3751	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3752	do { \
3753	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3754	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3755	} while (0)
3756
3757	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3758	do { \
3759	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3760	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3761	} while (0)
3762
3763	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3764	do { \
3765	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3766	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3767	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3768	} while (0)
3769
3770	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3771	do { \
3772	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3773	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3774	} while (0)
3775
3776	/* Header. */
3777	{
3778	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3779	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3780	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, HMGetVmxAbortDesc(pVmcs->enmVmxAbort));
3781	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, HMGetVmxVmcsStateDesc(pVmcs->fVmcsState));
3782	}
3783
3784	/* Control fields. */
3785	{
3786	/* 16-bit. */
3787	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3788	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3789	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3790	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3791
3792	/* 32-bit. */
3793	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3794	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3795	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3796	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3797	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3798	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3799	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3800	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3801	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3802	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3803	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3804	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3805	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3806	{
3807	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3808	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3809	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3810	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxEntryIntInfoTypeDesc(uType));
3811	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3812	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3813	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3814	}
3815	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3816	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3817	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3818	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3819	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3820
3821	/* 64-bit. */
3822	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3823	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3824	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3825	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3826	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3827	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3828	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3829	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3830	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3831	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3832	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3833	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3834	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3835	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3836	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3837	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3838	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3839	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3840	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3841	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3842	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3843	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3844	pHlp->pfnPrintf(pHlp, " %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u);
3845	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsBitmap.u);
3846	pHlp->pfnPrintf(pHlp, " %sSPPT ptr = %#RX64\n", pszPrefix, pVmcs->u64SpptPtr.u);
3847	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3848
3849	/* Natural width. */
3850	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3851	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3852	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3853	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3854	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3855	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3856	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3857	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3858	}
3859
3860	/* Guest state. */
3861	{
3862	char szEFlags[80];
3863	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3864	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3865
3866	/* 16-bit. */
3867	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "cs", pszPrefix);
3868	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "ss", pszPrefix);
3869	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "es", pszPrefix);
3870	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "ds", pszPrefix);
3871	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "fs", pszPrefix);
3872	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "gs", pszPrefix);
3873	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "ldtr", pszPrefix);
3874	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "tr", pszPrefix);
3875	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3876	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3877	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3878	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3879
3880	/* 32-bit. */
3881	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3882	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3883	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3884	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3885	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3886
3887	/* 64-bit. */
3888	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3889	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3890	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3891	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3892	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3893	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3894	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3895	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3896	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3897	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3898	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3899
3900	/* Natural width. */
3901	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3902	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3903	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3904	pHlp->pfnPrintf(pHlp, " %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3905	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3906	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3907	pHlp->pfnPrintf(pHlp, " %srflags = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3908	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpt.u);
3909	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3910	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3911	}
3912
3913	/* Host state. */
3914	{
3915	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3916
3917	/* 16-bit. */
3918	pHlp->pfnPrintf(pHlp, " %scs = %#RX16\n", pszPrefix, pVmcs->HostCs);
3919	pHlp->pfnPrintf(pHlp, " %sss = %#RX16\n", pszPrefix, pVmcs->HostSs);
3920	pHlp->pfnPrintf(pHlp, " %sds = %#RX16\n", pszPrefix, pVmcs->HostDs);
3921	pHlp->pfnPrintf(pHlp, " %ses = %#RX16\n", pszPrefix, pVmcs->HostEs);
3922	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "fs", pszPrefix);
3923	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "gs", pszPrefix);
3924	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "tr", pszPrefix);
3925	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3926	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3927
3928	/* 32-bit. */
3929	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3930
3931	/* 64-bit. */
3932	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3933	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3934	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3935
3936	/* Natural width. */
3937	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3938	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3939	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3940	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3941	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3942	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3943	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3944	}
3945
3946	/* Read-only fields. */
3947	{
3948	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3949
3950	/* 16-bit (none currently). */
3951
3952	/* 32-bit. */
3953	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3954	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3955	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3956	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3957	{
3958	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3959	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3960	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3961	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxExitIntInfoTypeDesc(uType));
3962	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3963	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3964	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3965	}
3966	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3967	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3968	{
3969	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3970	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3971	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3972	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxIdtVectoringInfoTypeDesc(uType));
3973	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3974	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3975	}
3976	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3977	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u bytes\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3978	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3979
3980	/* 64-bit. */
3981	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3982
3983	/* Natural width. */
3984	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3985	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3986	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3987	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3988	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3989	}
3990
3991	#undef CPUMVMX_DUMP_HOST_XDTR
3992	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3993	#undef CPUMVMX_DUMP_GUEST_SEGREG
3994	#undef CPUMVMX_DUMP_GUEST_XDTR
3995	}
3996
3997
3998	/**
3999	* Display the guest's hardware-virtualization cpu state.
4000	*
4001	* @param pVM The cross context VM structure.
4002	* @param pHlp The info helper functions.
4003	* @param pszArgs Arguments, ignored.
4004	*/
4005	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4006	{
4007	RT_NOREF(pszArgs);
4008
4009	PVMCPU pVCpu = VMMGetCpu(pVM);
4010	if (!pVCpu)
4011	pVCpu = &pVM->aCpus[0];
4012
4013	/*
4014	* Figure out what to dump.
4015	*
4016	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
4017	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
4018	* dump hwvirt. state when the guest CPU is executing a nested-guest.
4019	*/
4020	/** @todo perhaps make this configurable through pszArgs, depending on how much
4021	* noise we wish to accept when nested hwvirt. isn't used. */
4022	#define CPUMHWVIRTDUMP_NONE (0)
4023	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
4024	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
4025	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
4026	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
4027
4028	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4029	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
4030	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4031	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4032	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
4033	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
4034	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
4035	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
4036	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
4037
4038	/*
4039	* Dump it.
4040	*/
4041	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4042
4043	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
4044	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
4045
4046	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
4047	":" : "");
4048	if (fDumpState & CPUMHWVIRTDUMP_SVM)
4049	{
4050	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4051
4052	char szEFlags[80];
4053	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4054	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4055	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4056	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4057	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
4058	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4059	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
4060	pHlp->pfnPrintf(pHlp, " HostState:\n");
4061	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4062	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4063	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4064	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4065	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4066	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4067	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4068	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4069	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
4070	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4071	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4072	pSel = &pCtx->hwvirt.svm.HostState.cs;
4073	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4074	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4075	pSel = &pCtx->hwvirt.svm.HostState.ss;
4076	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4077	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4078	pSel = &pCtx->hwvirt.svm.HostState.ds;
4079	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4080	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4081	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4082	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4083	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4084	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4085	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4086	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4087	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4088	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
4089	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
4090	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
4091	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
4092	}
4093
4094	if (fDumpState & CPUMHWVIRTDUMP_VMX)
4095	{
4096	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4097	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4098	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4099	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4100	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, HMGetVmxAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4101	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4102	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4103	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4104	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4105	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4106	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4107	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4108	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4109	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4110	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4111	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4112	cpumR3InfoVmxVmcs(pHlp, pCtx->hwvirt.vmx.pVmcsR3, " " /* pszPrefix */);
4113	}
4114
4115	#undef CPUMHWVIRTDUMP_NONE
4116	#undef CPUMHWVIRTDUMP_COMMON
4117	#undef CPUMHWVIRTDUMP_SVM
4118	#undef CPUMHWVIRTDUMP_VMX
4119	#undef CPUMHWVIRTDUMP_LAST
4120	#undef CPUMHWVIRTDUMP_ALL
4121	}
4122
4123	/**
4124	* Display the current guest instruction
4125	*
4126	* @param pVM The cross context VM structure.
4127	* @param pHlp The info helper functions.
4128	* @param pszArgs Arguments, ignored.
4129	*/
4130	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4131	{
4132	NOREF(pszArgs);
4133
4134	PVMCPU pVCpu = VMMGetCpu(pVM);
4135	if (!pVCpu)
4136	pVCpu = &pVM->aCpus[0];
4137
4138	char szInstruction[256];
4139	szInstruction[0] = '\0';
4140	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4141	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4142	}
4143
4144
4145	/**
4146	* Display the hypervisor cpu state.
4147	*
4148	* @param pVM The cross context VM structure.
4149	* @param pHlp The info helper functions.
4150	* @param pszArgs Arguments, ignored.
4151	*/
4152	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4153	{
4154	PVMCPU pVCpu = VMMGetCpu(pVM);
4155	if (!pVCpu)
4156	pVCpu = &pVM->aCpus[0];
4157
4158	CPUMDUMPTYPE enmType;
4159	const char *pszComment;
4160	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4161	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4162	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
4163	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4164	}
4165
4166
4167	/**
4168	* Display the host cpu state.
4169	*
4170	* @param pVM The cross context VM structure.
4171	* @param pHlp The info helper functions.
4172	* @param pszArgs Arguments, ignored.
4173	*/
4174	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4175	{
4176	CPUMDUMPTYPE enmType;
4177	const char *pszComment;
4178	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4179	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4180
4181	PVMCPU pVCpu = VMMGetCpu(pVM);
4182	if (!pVCpu)
4183	pVCpu = &pVM->aCpus[0];
4184	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4185
4186	/*
4187	* Format the EFLAGS.
4188	*/
4189	#if HC_ARCH_BITS == 32
4190	uint32_t efl = pCtx->eflags.u32;
4191	#else
4192	uint64_t efl = pCtx->rflags;
4193	#endif
4194	char szEFlags[80];
4195	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4196
4197	/*
4198	* Format the registers.
4199	*/
4200	#if HC_ARCH_BITS == 32
4201	pHlp->pfnPrintf(pHlp,
4202	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
4203	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
4204	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
4205	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
4206	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
4207	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4208	,
4209	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
4210	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
4211	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4212	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
4213	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
4214	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
4215	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
4216	#else
4217	pHlp->pfnPrintf(pHlp,
4218	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4219	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4220	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4221	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4222	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4223	"r14=%016RX64 r15=%016RX64\n"
4224	"iopl=%d %31s\n"
4225	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4226	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4227	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4228	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4229	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4230	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4231	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4232	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4233	,
4234	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4235	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4236	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4237	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4238	pCtx->r11, pCtx->r12, pCtx->r13,
4239	pCtx->r14, pCtx->r15,
4240	X86_EFL_GET_IOPL(efl), szEFlags,
4241	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4242	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4243	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4244	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4245	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4246	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4247	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4248	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4249	#endif
4250	}
4251
4252	/**
4253	* Structure used when disassembling and instructions in DBGF.
4254	* This is used so the reader function can get the stuff it needs.
4255	*/
4256	typedef struct CPUMDISASSTATE
4257	{
4258	/** Pointer to the CPU structure. */
4259	PDISCPUSTATE pCpu;
4260	/** Pointer to the VM. */
4261	PVM pVM;
4262	/** Pointer to the VMCPU. */
4263	PVMCPU pVCpu;
4264	/** Pointer to the first byte in the segment. */
4265	RTGCUINTPTR GCPtrSegBase;
4266	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4267	RTGCUINTPTR GCPtrSegEnd;
4268	/** The size of the segment minus 1. */
4269	RTGCUINTPTR cbSegLimit;
4270	/** Pointer to the current page - R3 Ptr. */
4271	void const *pvPageR3;
4272	/** Pointer to the current page - GC Ptr. */
4273	RTGCPTR pvPageGC;
4274	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4275	PGMPAGEMAPLOCK PageMapLock;
4276	/** Whether the PageMapLock is valid or not. */
4277	bool fLocked;
4278	/** 64 bits mode or not. */
4279	bool f64Bits;
4280	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4281
4282
4283	/**
4284	* @callback_method_impl{FNDISREADBYTES}
4285	*/
4286	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4287	{
4288	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4289	for (;;)
4290	{
4291	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4292
4293	/*
4294	* Need to update the page translation?
4295	*/
4296	if ( !pState->pvPageR3
4297	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4298	{
4299	int rc = VINF_SUCCESS;
4300
4301	/* translate the address */
4302	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4303	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
4304	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4305	{
4306	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4307	if (!pState->pvPageR3)
4308	rc = VERR_INVALID_POINTER;
4309	}
4310	else
4311	{
4312	/* Release mapping lock previously acquired. */
4313	if (pState->fLocked)
4314	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4315	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4316	pState->fLocked = RT_SUCCESS_NP(rc);
4317	}
4318	if (RT_FAILURE(rc))
4319	{
4320	pState->pvPageR3 = NULL;
4321	return rc;
4322	}
4323	}
4324
4325	/*
4326	* Check the segment limit.
4327	*/
4328	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4329	return VERR_OUT_OF_SELECTOR_BOUNDS;
4330
4331	/*
4332	* Calc how much we can read.
4333	*/
4334	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4335	if (!pState->f64Bits)
4336	{
4337	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4338	if (cb > cbSeg && cbSeg)
4339	cb = cbSeg;
4340	}
4341	if (cb > cbMaxRead)
4342	cb = cbMaxRead;
4343
4344	/*
4345	* Read and advance or exit.
4346	*/
4347	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4348	offInstr += (uint8_t)cb;
4349	if (cb >= cbMinRead)
4350	{
4351	pDis->cbCachedInstr = offInstr;
4352	return VINF_SUCCESS;
4353	}
4354	cbMinRead -= (uint8_t)cb;
4355	cbMaxRead -= (uint8_t)cb;
4356	}
4357	}
4358
4359
4360	/**
4361	* Disassemble an instruction and return the information in the provided structure.
4362	*
4363	* @returns VBox status code.
4364	* @param pVM The cross context VM structure.
4365	* @param pVCpu The cross context virtual CPU structure.
4366	* @param pCtx Pointer to the guest CPU context.
4367	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4368	* @param pCpu Disassembly state.
4369	* @param pszPrefix String prefix for logging (debug only).
4370	*
4371	*/
4372	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4373	const char *pszPrefix)
4374	{
4375	CPUMDISASSTATE State;
4376	int rc;
4377
4378	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4379	State.pCpu = pCpu;
4380	State.pvPageGC = 0;
4381	State.pvPageR3 = NULL;
4382	State.pVM = pVM;
4383	State.pVCpu = pVCpu;
4384	State.fLocked = false;
4385	State.f64Bits = false;
4386
4387	/*
4388	* Get selector information.
4389	*/
4390	DISCPUMODE enmDisCpuMode;
4391	if ( (pCtx->cr0 & X86_CR0_PE)
4392	&& pCtx->eflags.Bits.u1VM == 0)
4393	{
4394	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4395	{
4396	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4397	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4398	# endif
4399	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4400	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4401	}
4402	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4403	State.GCPtrSegBase = pCtx->cs.u64Base;
4404	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4405	State.cbSegLimit = pCtx->cs.u32Limit;
4406	enmDisCpuMode = (State.f64Bits)
4407	? DISCPUMODE_64BIT
4408	: pCtx->cs.Attr.n.u1DefBig
4409	? DISCPUMODE_32BIT
4410	: DISCPUMODE_16BIT;
4411	}
4412	else
4413	{
4414	/* real or V86 mode */
4415	enmDisCpuMode = DISCPUMODE_16BIT;
4416	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4417	State.GCPtrSegEnd = 0xFFFFFFFF;
4418	State.cbSegLimit = 0xFFFFFFFF;
4419	}
4420
4421	/*
4422	* Disassemble the instruction.
4423	*/
4424	uint32_t cbInstr;
4425	#ifndef LOG_ENABLED
4426	RT_NOREF_PV(pszPrefix);
4427	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4428	if (RT_SUCCESS(rc))
4429	{
4430	#else
4431	char szOutput[160];
4432	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4433	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4434	if (RT_SUCCESS(rc))
4435	{
4436	/* log it */
4437	if (pszPrefix)
4438	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4439	else
4440	Log(("%s", szOutput));
4441	#endif
4442	rc = VINF_SUCCESS;
4443	}
4444	else
4445	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4446
4447	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4448	if (State.fLocked)
4449	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4450
4451	return rc;
4452	}
4453
4454
4455
4456	/**
4457	* API for controlling a few of the CPU features found in CR4.
4458	*
4459	* Currently only X86_CR4_TSD is accepted as input.
4460	*
4461	* @returns VBox status code.
4462	*
4463	* @param pVM The cross context VM structure.
4464	* @param fOr The CR4 OR mask.
4465	* @param fAnd The CR4 AND mask.
4466	*/
4467	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4468	{
4469	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4470	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4471
4472	pVM->cpum.s.CR4.OrMask &= fAnd;
4473	pVM->cpum.s.CR4.OrMask \|= fOr;
4474
4475	return VINF_SUCCESS;
4476	}
4477
4478
4479	/**
4480	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4481	*
4482	* Only REM should ever call this function!
4483	*
4484	* @returns The changed flags.
4485	* @param pVCpu The cross context virtual CPU structure.
4486	* @param puCpl Where to return the current privilege level (CPL).
4487	*/
4488	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4489	{
4490	Assert(!pVCpu->cpum.s.fRawEntered);
4491	Assert(!pVCpu->cpum.s.fRemEntered);
4492
4493	/*
4494	* Get the CPL first.
4495	*/
4496	*puCpl = CPUMGetGuestCPL(pVCpu);
4497
4498	/*
4499	* Get and reset the flags.
4500	*/
4501	uint32_t fFlags = pVCpu->cpum.s.fChanged;
4502	pVCpu->cpum.s.fChanged = 0;
4503
4504	/** @todo change the switcher to use the fChanged flags. */
4505	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4506	{
4507	fFlags \|= CPUM_CHANGED_FPU_REM;
4508	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4509	}
4510
4511	pVCpu->cpum.s.fRemEntered = true;
4512	return fFlags;
4513	}
4514
4515
4516	/**
4517	* Leaves REM.
4518	*
4519	* @param pVCpu The cross context virtual CPU structure.
4520	* @param fNoOutOfSyncSels This is @c false if there are out of sync
4521	* registers.
4522	*/
4523	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4524	{
4525	Assert(!pVCpu->cpum.s.fRawEntered);
4526	Assert(pVCpu->cpum.s.fRemEntered);
4527
4528	RT_NOREF_PV(fNoOutOfSyncSels);
4529
4530	pVCpu->cpum.s.fRemEntered = false;
4531	}
4532
4533
4534	/**
4535	* Called when the ring-3 init phase completes.
4536	*
4537	* @returns VBox status code.
4538	* @param pVM The cross context VM structure.
4539	* @param enmWhat Which init phase.
4540	*/
4541	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4542	{
4543	switch (enmWhat)
4544	{
4545	case VMINITCOMPLETED_RING3:
4546	{
4547	/*
4548	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4549	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4550	*/
4551	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4552	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4553	{
4554	PVMCPU pVCpu = &pVM->aCpus[i];
4555	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4556	if (fSupportsLongMode)
4557	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4558	}
4559
4560	/* Register statistic counters for MSRs. */
4561	cpumR3MsrRegStats(pVM);
4562	break;
4563	}
4564
4565	default:
4566	break;
4567	}
4568	return VINF_SUCCESS;
4569	}
4570
4571
4572	/**
4573	* Called when the ring-0 init phases completed.
4574	*
4575	* @param pVM The cross context VM structure.
4576	*/
4577	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4578	{
4579	/*
4580	* Enable log buffering as we're going to log a lot of lines.
4581	*/
4582	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4583
4584	/*
4585	* Log the cpuid.
4586	*/
4587	RTCPUSET OnlineSet;
4588	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4589	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4590	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4591	RTCPUID cCores = RTMpGetCoreCount();
4592	if (cCores)
4593	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4594	LogRel(("*********************** CPUID dump **********************\n"));
4595	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4596	LogRel(("\n"));
4597	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4598	LogRel(("****************** End of CPUID dump ********************\n"));
4599
4600	/*
4601	* Log VT-x extended features.
4602	*
4603	* SVM features are currently all covered under CPUID so there is nothing
4604	* to do here for SVM.
4605	*/
4606	if (pVM->cpum.s.HostFeatures.fVmx)
4607	{
4608	LogRel(("********************* VT-x features *********************\n"));
4609	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4610	LogRel(("\n"));
4611	LogRel(("***************** End of VT-x features ******************\n"));
4612	}
4613
4614	/*
4615	* Restore the log buffering state to what it was previously.
4616	*/
4617	RTLogRelSetBuffering(fOldBuffered);
4618	}
4619

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 79373

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