CPUM.cpp@ 96962

Last change on this file since 96962 was 96902, checked in by vboxsync, 2 years ago
VMM: Nested SVM: bugref:7243 VM reset and init. nits for nested SVM, don't rely on order of usage assumptions.
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1	/* $Id: CPUM.cpp 96902 2022-09-27 14:30:57Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
31	* also responsible for lazy FPU handling and some of the context loading
32	* in raw mode.
33	*
34	* There are three CPU contexts, the most important one is the guest one (GC).
35	* When running in raw-mode (RC) there is a special hyper context for the VMM
36	* part that floats around inside the guest address space. When running in
37	* raw-mode, CPUM also maintains a host context for saving and restoring
38	* registers across world switches. This latter is done in cooperation with the
39	* world switcher (@see pg_vmm).
40	*
41	* @see grp_cpum
42	*
43	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44	*
45	* TODO: proper write up, currently just some notes.
46	*
47	* The ring-0 FPU handling per OS:
48	*
49	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
50	* convention (Visual C++ doesn't seem to have a way to disable
51	* generating such code either), so CR0.TS/EM are always zero from what I
52	* can tell. We are also forced to always load/save the guest XMM0-XMM15
53	* registers when entering/leaving guest context. Interrupt handlers
54	* using FPU/SSE will offically have call save and restore functions
55	* exported by the kernel, if the really really have to use the state.
56	*
57	* - 32-bit windows does lazy FPU handling, I think, probably including
58	* lazying saving. The Windows Internals book states that it's a bad
59	* idea to use the FPU in kernel space. However, it looks like it will
60	* restore the FPU state of the current thread in case of a kernel \#NM.
61	* Interrupt handlers should be same as for 64-bit.
62	*
63	* - Darwin allows taking \#NM in kernel space, restoring current thread's
64	* state if I read the code correctly. It saves the FPU state of the
65	* outgoing thread, and uses CR0.TS to lazily load the state of the
66	* incoming one. No idea yet how the FPU is treated by interrupt
67	* handlers, i.e. whether they are allowed to disable the state or
68	* something.
69	*
70	* - Linux also allows \#NM in kernel space (don't know since when), and
71	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72	* loads the incoming unless configured to agressivly load it. Interrupt
73	* handlers can ask whether they're allowed to use the FPU, and may
74	* freely trash the state if Linux thinks it has saved the thread's state
75	* already. This is a problem.
76	*
77	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78	* context. When switching threads, the kernel will save the state of
79	* the outgoing thread and lazy load the incoming one using CR0.TS.
80	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
81	* to do stuff, HAT are among the users. The routines there will
82	* manually clear CR0.TS and save the XMM registers they use only if
83	* CR0.TS was zero upon entry. They will skip it when not, because as
84	* mentioned above, the FPU state is saved when switching away from a
85	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86	* preserve. This is a problem if we restore CR0.TS to 1 after loading
87	* the guest state.
88	*
89	* - FreeBSD - no idea yet.
90	*
91	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93	* FPU states.
94	*
95	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96	* saving and restoring the host and guest states. The motivation for this
97	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98	*
99	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100	* state and only restore it once we've restore the host FPU state. This has the
101	* accidental side effect of triggering Solaris to preserve XMM registers in
102	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104	*
105	*
106	* @section sec_cpum_logging Logging Level Assignments.
107	*
108	* Following log level assignments:
109	* - Log6 is used for FPU state management.
110	* - Log7 is used for FPU state actualization.
111	*
112	*/
113
114
115	/*********************************************************************************************************************************
116	* Header Files *
117	*********************************************************************************************************************************/
118	#define LOG_GROUP LOG_GROUP_CPUM
119	#define CPUM_WITH_NONCONST_HOST_FEATURES
120	#include <VBox/vmm/cpum.h>
121	#include <VBox/vmm/cpumdis.h>
122	#include <VBox/vmm/cpumctx-v1_6.h>
123	#include <VBox/vmm/pgm.h>
124	#include <VBox/vmm/apic.h>
125	#include <VBox/vmm/mm.h>
126	#include <VBox/vmm/em.h>
127	#include <VBox/vmm/iem.h>
128	#include <VBox/vmm/selm.h>
129	#include <VBox/vmm/dbgf.h>
130	#include <VBox/vmm/hm.h>
131	#include <VBox/vmm/hmvmxinline.h>
132	#include <VBox/vmm/ssm.h>
133	#include "CPUMInternal.h"
134	#include <VBox/vmm/vm.h>
135
136	#include <VBox/param.h>
137	#include <VBox/dis.h>
138	#include <VBox/err.h>
139	#include <VBox/log.h>
140	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
141	# include <iprt/asm-amd64-x86.h>
142	#endif
143	#include <iprt/assert.h>
144	#include <iprt/cpuset.h>
145	#include <iprt/mem.h>
146	#include <iprt/mp.h>
147	#include <iprt/string.h>
148
149
150	/*********************************************************************************************************************************
151	* Defined Constants And Macros *
152	*********************************************************************************************************************************/
153	/**
154	* This was used in the saved state up to the early life of version 14.
155	*
156	* It indicates that we may have some out-of-sync hidden segement registers.
157	* It is only relevant for raw-mode.
158	*/
159	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
160
161
162	/*********************************************************************************************************************************
163	* Structures and Typedefs *
164	*********************************************************************************************************************************/
165
166	/**
167	* What kind of cpu info dump to perform.
168	*/
169	typedef enum CPUMDUMPTYPE
170	{
171	CPUMDUMPTYPE_TERSE,
172	CPUMDUMPTYPE_DEFAULT,
173	CPUMDUMPTYPE_VERBOSE
174	} CPUMDUMPTYPE;
175	/** Pointer to a cpu info dump type. */
176	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
177
178
179	/*********************************************************************************************************************************
180	* Internal Functions *
181	*********************************************************************************************************************************/
182	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
183	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
184	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
185	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
186	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
187	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
188	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
189	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
190	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
191	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
192	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
193
194
195	/*********************************************************************************************************************************
196	* Global Variables *
197	*********************************************************************************************************************************/
198	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
199	/** Host CPU features. */
200	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
201	#endif
202
203	/** Saved state field descriptors for CPUMCTX. */
204	static const SSMFIELD g_aCpumCtxFields[] =
205	{
206	SSMFIELD_ENTRY( CPUMCTX, rdi),
207	SSMFIELD_ENTRY( CPUMCTX, rsi),
208	SSMFIELD_ENTRY( CPUMCTX, rbp),
209	SSMFIELD_ENTRY( CPUMCTX, rax),
210	SSMFIELD_ENTRY( CPUMCTX, rbx),
211	SSMFIELD_ENTRY( CPUMCTX, rdx),
212	SSMFIELD_ENTRY( CPUMCTX, rcx),
213	SSMFIELD_ENTRY( CPUMCTX, rsp),
214	SSMFIELD_ENTRY( CPUMCTX, rflags),
215	SSMFIELD_ENTRY( CPUMCTX, rip),
216	SSMFIELD_ENTRY( CPUMCTX, r8),
217	SSMFIELD_ENTRY( CPUMCTX, r9),
218	SSMFIELD_ENTRY( CPUMCTX, r10),
219	SSMFIELD_ENTRY( CPUMCTX, r11),
220	SSMFIELD_ENTRY( CPUMCTX, r12),
221	SSMFIELD_ENTRY( CPUMCTX, r13),
222	SSMFIELD_ENTRY( CPUMCTX, r14),
223	SSMFIELD_ENTRY( CPUMCTX, r15),
224	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
243	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
244	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
245	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
246	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
247	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
248	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
249	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
250	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
251	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
252	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
253	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
254	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
255	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
256	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
257	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
258	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
259	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
260	SSMFIELD_ENTRY( CPUMCTX, cr0),
261	SSMFIELD_ENTRY( CPUMCTX, cr2),
262	SSMFIELD_ENTRY( CPUMCTX, cr3),
263	SSMFIELD_ENTRY( CPUMCTX, cr4),
264	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
265	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
266	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
267	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
268	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
269	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
270	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
271	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
272	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
273	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
274	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
275	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
276	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
277	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
278	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
279	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
280	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
281	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
282	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
283	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
284	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
285	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
286	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
287	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
288	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
289	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
290	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
291	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
292	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
293	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
294	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
295	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
296	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
297	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
298	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
299	SSMFIELD_ENTRY_TERM()
300	};
301
302	/** Saved state field descriptors for SVM nested hardware-virtualization
303	* Host State. */
304	static const SSMFIELD g_aSvmHwvirtHostState[] =
305	{
306	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
324	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
325	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
326	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
327	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
328	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
329	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
330	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
331	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
332	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
333	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
334	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
335	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
336	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
337	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
338	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
339	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
340	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
341	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
342	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
343	SSMFIELD_ENTRY_TERM()
344	};
345
346	/** Saved state field descriptors for VMX nested hardware-virtualization
347	* VMCS. */
348	static const SSMFIELD g_aVmxHwvirtVmcs[] =
349	{
350	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
351	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
352	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
353	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
354	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
355
356	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
357
358	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
359	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
360	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
361	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
362	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
363	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
364	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
365	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
366	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
367
368	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
369	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
370
371	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
372	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
373	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
374	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
375	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
376	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
377	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
378
379	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
380	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
381	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
382	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
383
384	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
385	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
386	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
387	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
388	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
389	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
390	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
391	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
392	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
393	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
394	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
395	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
396	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
397	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
398	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
399	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
400	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
401	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
402	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
403
404	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
405	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
406	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
407	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
408	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
409	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
410	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
411	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
412	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
413	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
414	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
415	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
416	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
417	SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
418	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
419	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
420	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
421	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
422	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
423	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
424	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
425	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
426	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
427	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
428	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
429	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
430	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
431	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
432	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
433
434	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
435	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
436	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
437	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
438	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
439	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
440	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
441	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
442	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
443
444	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
445	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
446	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
447	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
448	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
449	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
450	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
451	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
452
453	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
454	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
455
456	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
457	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
458	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
459	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
460	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
461
462	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
463	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
464	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
465	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
466	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
467	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
468	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
469	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
470	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
471	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
472	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
473	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
474	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
475	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
476	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
477	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
478
479	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
480	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
481	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
482	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
483	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
484	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
485	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
486	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
487	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
488	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
489	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
490
491	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
492	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
493	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
494	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
495	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
496	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
497	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
498	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
499	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
500	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
501	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
502	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
503	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
504	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
505	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
506	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
507	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
508	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
509	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
510	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
511	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
512	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
513	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
514	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
515
516	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
517	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
518	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
519	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
520	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
521	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
527	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
528	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
529
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
532	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
533	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
534	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
535	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
536	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
537	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
538	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
539	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
540	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
541	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
542	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
543	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
544	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
545	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
546	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
547	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
548	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
549	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
550	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
551	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
552	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
553	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
554
555	SSMFIELD_ENTRY_TERM()
556	};
557
558	/** Saved state field descriptors for CPUMCTX. */
559	static const SSMFIELD g_aCpumX87Fields[] =
560	{
561	SSMFIELD_ENTRY( X86FXSTATE, FCW),
562	SSMFIELD_ENTRY( X86FXSTATE, FSW),
563	SSMFIELD_ENTRY( X86FXSTATE, FTW),
564	SSMFIELD_ENTRY( X86FXSTATE, FOP),
565	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
566	SSMFIELD_ENTRY( X86FXSTATE, CS),
567	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
568	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
569	SSMFIELD_ENTRY( X86FXSTATE, DS),
570	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
571	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
572	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
573	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
574	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
575	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
576	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
577	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
578	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
579	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
580	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
581	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
582	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
583	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
584	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
585	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
586	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
587	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
588	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
589	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
590	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
591	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
592	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
593	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
594	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
595	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
596	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
597	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
598	SSMFIELD_ENTRY_TERM()
599	};
600
601	/** Saved state field descriptors for X86XSAVEHDR. */
602	static const SSMFIELD g_aCpumXSaveHdrFields[] =
603	{
604	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
605	SSMFIELD_ENTRY_TERM()
606	};
607
608	/** Saved state field descriptors for X86XSAVEYMMHI. */
609	static const SSMFIELD g_aCpumYmmHiFields[] =
610	{
611	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
612	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
613	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
614	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
615	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
616	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
617	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
618	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
619	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
620	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
621	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
622	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
623	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
624	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
625	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
626	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
627	SSMFIELD_ENTRY_TERM()
628	};
629
630	/** Saved state field descriptors for X86XSAVEBNDREGS. */
631	static const SSMFIELD g_aCpumBndRegsFields[] =
632	{
633	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
634	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
635	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
636	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
637	SSMFIELD_ENTRY_TERM()
638	};
639
640	/** Saved state field descriptors for X86XSAVEBNDCFG. */
641	static const SSMFIELD g_aCpumBndCfgFields[] =
642	{
643	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
644	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
645	SSMFIELD_ENTRY_TERM()
646	};
647
648	#if 0 /** @todo */
649	/** Saved state field descriptors for X86XSAVEOPMASK. */
650	static const SSMFIELD g_aCpumOpmaskFields[] =
651	{
652	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
653	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
654	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
655	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
656	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
657	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
658	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
659	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
660	SSMFIELD_ENTRY_TERM()
661	};
662	#endif
663
664	/** Saved state field descriptors for X86XSAVEZMMHI256. */
665	static const SSMFIELD g_aCpumZmmHi256Fields[] =
666	{
667	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
668	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
669	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
670	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
671	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
672	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
673	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
674	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
675	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
676	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
677	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
678	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
679	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
680	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
681	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
682	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
683	SSMFIELD_ENTRY_TERM()
684	};
685
686	/** Saved state field descriptors for X86XSAVEZMM16HI. */
687	static const SSMFIELD g_aCpumZmm16HiFields[] =
688	{
689	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
690	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
691	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
692	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
693	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
694	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
695	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
696	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
697	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
698	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
699	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
700	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
701	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
702	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
703	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
704	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
705	SSMFIELD_ENTRY_TERM()
706	};
707
708
709
710	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
711	* registeres changed. */
712	static const SSMFIELD g_aCpumX87FieldsMem[] =
713	{
714	SSMFIELD_ENTRY( X86FXSTATE, FCW),
715	SSMFIELD_ENTRY( X86FXSTATE, FSW),
716	SSMFIELD_ENTRY( X86FXSTATE, FTW),
717	SSMFIELD_ENTRY( X86FXSTATE, FOP),
718	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
719	SSMFIELD_ENTRY( X86FXSTATE, CS),
720	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
721	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
722	SSMFIELD_ENTRY( X86FXSTATE, DS),
723	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
724	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
725	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
726	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
727	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
728	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
729	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
730	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
731	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
732	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
733	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
734	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
735	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
736	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
737	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
738	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
739	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
740	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
741	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
742	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
743	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
744	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
745	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
746	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
747	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
748	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
749	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
750	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
751	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
752	};
753
754	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
755	* registeres changed. */
756	static const SSMFIELD g_aCpumCtxFieldsMem[] =
757	{
758	SSMFIELD_ENTRY( CPUMCTX, rdi),
759	SSMFIELD_ENTRY( CPUMCTX, rsi),
760	SSMFIELD_ENTRY( CPUMCTX, rbp),
761	SSMFIELD_ENTRY( CPUMCTX, rax),
762	SSMFIELD_ENTRY( CPUMCTX, rbx),
763	SSMFIELD_ENTRY( CPUMCTX, rdx),
764	SSMFIELD_ENTRY( CPUMCTX, rcx),
765	SSMFIELD_ENTRY( CPUMCTX, rsp),
766	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
767	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
768	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
769	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
770	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
771	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
772	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
773	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
774	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
775	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
776	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
777	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
778	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
779	SSMFIELD_ENTRY( CPUMCTX, rflags),
780	SSMFIELD_ENTRY( CPUMCTX, rip),
781	SSMFIELD_ENTRY( CPUMCTX, r8),
782	SSMFIELD_ENTRY( CPUMCTX, r9),
783	SSMFIELD_ENTRY( CPUMCTX, r10),
784	SSMFIELD_ENTRY( CPUMCTX, r11),
785	SSMFIELD_ENTRY( CPUMCTX, r12),
786	SSMFIELD_ENTRY( CPUMCTX, r13),
787	SSMFIELD_ENTRY( CPUMCTX, r14),
788	SSMFIELD_ENTRY( CPUMCTX, r15),
789	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
790	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
791	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
792	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
793	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
794	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
795	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
796	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
797	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
798	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
799	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
800	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
801	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
802	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
803	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
804	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
805	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
806	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
807	SSMFIELD_ENTRY( CPUMCTX, cr0),
808	SSMFIELD_ENTRY( CPUMCTX, cr2),
809	SSMFIELD_ENTRY( CPUMCTX, cr3),
810	SSMFIELD_ENTRY( CPUMCTX, cr4),
811	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
812	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
813	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
814	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
815	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
816	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
817	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
818	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
819	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
820	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
821	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
822	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
823	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
824	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
825	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
826	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
827	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
828	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
829	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
830	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
831	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
832	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
833	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
834	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
835	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
836	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
837	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
838	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
839	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
840	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
841	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
842	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
843	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
844	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
845	SSMFIELD_ENTRY_TERM()
846	};
847
848	/** Saved state field descriptors for CPUMCTX_VER1_6. */
849	static const SSMFIELD g_aCpumX87FieldsV16[] =
850	{
851	SSMFIELD_ENTRY( X86FXSTATE, FCW),
852	SSMFIELD_ENTRY( X86FXSTATE, FSW),
853	SSMFIELD_ENTRY( X86FXSTATE, FTW),
854	SSMFIELD_ENTRY( X86FXSTATE, FOP),
855	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
856	SSMFIELD_ENTRY( X86FXSTATE, CS),
857	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
858	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
859	SSMFIELD_ENTRY( X86FXSTATE, DS),
860	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
861	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
862	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
863	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
864	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
865	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
866	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
867	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
868	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
869	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
870	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
871	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
872	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
873	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
874	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
875	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
876	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
877	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
878	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
879	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
880	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
881	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
882	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
883	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
884	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
885	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
886	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
887	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
888	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
889	SSMFIELD_ENTRY_TERM()
890	};
891
892	/** Saved state field descriptors for CPUMCTX_VER1_6. */
893	static const SSMFIELD g_aCpumCtxFieldsV16[] =
894	{
895	SSMFIELD_ENTRY( CPUMCTX, rdi),
896	SSMFIELD_ENTRY( CPUMCTX, rsi),
897	SSMFIELD_ENTRY( CPUMCTX, rbp),
898	SSMFIELD_ENTRY( CPUMCTX, rax),
899	SSMFIELD_ENTRY( CPUMCTX, rbx),
900	SSMFIELD_ENTRY( CPUMCTX, rdx),
901	SSMFIELD_ENTRY( CPUMCTX, rcx),
902	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
903	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
904	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
905	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
906	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
907	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
908	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
909	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
910	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
911	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
912	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
913	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
914	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
915	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
916	SSMFIELD_ENTRY( CPUMCTX, rflags),
917	SSMFIELD_ENTRY( CPUMCTX, rip),
918	SSMFIELD_ENTRY( CPUMCTX, r8),
919	SSMFIELD_ENTRY( CPUMCTX, r9),
920	SSMFIELD_ENTRY( CPUMCTX, r10),
921	SSMFIELD_ENTRY( CPUMCTX, r11),
922	SSMFIELD_ENTRY( CPUMCTX, r12),
923	SSMFIELD_ENTRY( CPUMCTX, r13),
924	SSMFIELD_ENTRY( CPUMCTX, r14),
925	SSMFIELD_ENTRY( CPUMCTX, r15),
926	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
927	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
928	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
929	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
930	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
931	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
932	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
933	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
934	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
935	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
936	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
937	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
938	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
939	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
940	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
941	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
942	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
943	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
944	SSMFIELD_ENTRY( CPUMCTX, cr0),
945	SSMFIELD_ENTRY( CPUMCTX, cr2),
946	SSMFIELD_ENTRY( CPUMCTX, cr3),
947	SSMFIELD_ENTRY( CPUMCTX, cr4),
948	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
949	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
950	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
951	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
952	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
953	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
954	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
955	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
956	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
957	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
958	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
959	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
960	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
961	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
962	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
963	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
964	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
965	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
966	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
967	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
968	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
969	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
970	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
971	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
972	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
973	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
974	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
975	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
976	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
977	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
978	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
979	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
980	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
981	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
982	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
983	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
984	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
985	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
986	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
987	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
988	SSMFIELD_ENTRY_TERM()
989	};
990
991
992	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
993	/**
994	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
995	*
996	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
997	* (last instruction pointer, last data pointer, last opcode) except when the ES
998	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
999	* clear these registers there is potential, local FPU leakage from a process
1000	* using the FPU to another.
1001	*
1002	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
1003	*
1004	* @param pVM The cross context VM structure.
1005	*/
1006	static void cpumR3CheckLeakyFpu(PVM pVM)
1007	{
1008	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1009	uint32_t const u32Family = u32CpuVersion >> 8;
1010	if ( u32Family >= 6 /* K7 and higher */
1011	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
1012	{
1013	uint32_t cExt = ASMCpuId_EAX(0x80000000);
1014	if (RTX86IsValidExtRange(cExt))
1015	{
1016	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1017	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1018	{
1019	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1020	{
1021	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1022	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1023	}
1024	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1025	}
1026	}
1027	}
1028	}
1029	#endif
1030
1031
1032	/**
1033	* Initialize the SVM hardware virtualization state.
1034	*
1035	* @param pVM The cross context VM structure.
1036	*/
1037	static void cpumR3InitSvmHwVirtState(PVM pVM)
1038	{
1039	LogRel(("CPUM: AMD-V nested-guest init\n"));
1040	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1041	{
1042	PVMCPU pVCpu = pVM->apCpusR3[i];
1043	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1044
1045	/* Initialize that SVM hardware virtualization is available. */
1046	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1047
1048	AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1049	AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1050	AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1051
1052	/* Initialize non-zero values. */
1053	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1054	}
1055	}
1056
1057
1058	/**
1059	* Resets per-VCPU SVM hardware virtualization state.
1060	*
1061	* @param pVCpu The cross context virtual CPU structure.
1062	*/
1063	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1064	{
1065	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1066	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1067
1068	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1069	RT_ZERO(pCtx->hwvirt.svm.HostState);
1070	RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1071	RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1072
1073	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1074	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1075	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1076	pCtx->hwvirt.svm.cPauseFilter = 0;
1077	pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1078	pCtx->hwvirt.svm.fInterceptEvents = false;
1079	}
1080
1081
1082	/**
1083	* Initializes the VMX hardware virtualization state.
1084	*
1085	* @param pVM The cross context VM structure.
1086	*/
1087	static void cpumR3InitVmxHwVirtState(PVM pVM)
1088	{
1089	LogRel(("CPUM: VT-x nested-guest init\n"));
1090	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1091	{
1092	PVMCPU pVCpu = pVM->apCpusR3[i];
1093	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1094
1095	/* Initialize that VMX hardware virtualization is available. */
1096	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1097
1098	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1099	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1100	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1101	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1102	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1103	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1104	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1105	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1106	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1107	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1108	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1109	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1110	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1111	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1112	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1113	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1114	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1115	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1116	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_PAGES * X86_PAGE_SIZE);
1117	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_SIZE);
1118
1119	/* Initialize non-zero values. */
1120	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1121	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1122	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1123	}
1124	}
1125
1126
1127	/**
1128	* Resets per-VCPU VMX hardware virtualization state.
1129	*
1130	* @param pVCpu The cross context virtual CPU structure.
1131	*/
1132	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1133	{
1134	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1135	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1136
1137	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1138	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1139	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1140	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1141	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1142	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1143	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1144	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1145	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1146	RT_ZERO(pCtx->hwvirt.vmx.abVirtApicPage);
1147
1148	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1149	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1150	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1151	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1152	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1153	/* Don't reset diagnostics here. */
1154
1155	pCtx->hwvirt.vmx.fInterceptEvents = false;
1156	pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1157	pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1158	pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1159	pCtx->hwvirt.vmx.uEntryTick = 0;
1160	pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1161	pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1162
1163	/* Stop any VMX-preemption timer. */
1164	CPUMStopGuestVmxPremptTimer(pVCpu);
1165
1166	/* Clear all nested-guest FFs. */
1167	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1168	}
1169
1170
1171	/**
1172	* Displays the host and guest VMX features.
1173	*
1174	* @param pVM The cross context VM structure.
1175	* @param pHlp The info helper functions.
1176	* @param pszArgs "terse", "default" or "verbose".
1177	*/
1178	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1179	{
1180	RT_NOREF(pszArgs);
1181	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1182	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1183	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1184	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1185	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1186	{
1187	#define VMXFEATDUMP(a_szDesc, a_Var) \
1188	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1189
1190	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1191	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1192	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1193	/* Basic. */
1194	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1195
1196	/* Pin-based controls. */
1197	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1198	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1199	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1200	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1201	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1202
1203	/* Processor-based controls. */
1204	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1205	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1206	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1207	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1208	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1209	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1210	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1211	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1212	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1213	VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1214	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1215	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1216	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1217	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1218	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1219	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1220	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1221	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1222	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1223	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1224	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1225	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1226
1227	/* Secondary processor-based controls. */
1228	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1229	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1230	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1231	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1232	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1233	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1234	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1235	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1236	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1237	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1238	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1239	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1240	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1241	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1242	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1243	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1244	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1245	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1246	VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1247	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1248	VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1249	VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1250	VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1251	VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1252	VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1253	VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1254
1255	/* Tertiary processor-based controls. */
1256	VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1257
1258	/* VM-entry controls. */
1259	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1260	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1261	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1262	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1263
1264	/* VM-exit controls. */
1265	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1266	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1267	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1268	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1269	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1270	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1271	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1272	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1273
1274	/* Miscellaneous data. */
1275	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1276	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxPt);
1277	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1278	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1279	#undef VMXFEATDUMP
1280	}
1281	else
1282	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1283	}
1284
1285
1286	/**
1287	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1288	* or NEM) is allowed.
1289	*
1290	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1291	* otherwise.
1292	* @param pVM The cross context VM structure.
1293	*/
1294	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1295	{
1296	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1297	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1298	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1299	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1300	return true;
1301	#else
1302	NOREF(pVM);
1303	#endif
1304	return false;
1305	}
1306
1307
1308	/**
1309	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1310	*
1311	* @param pVM The cross context VM structure.
1312	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1313	* and no hardware-assisted nested-guest execution is
1314	* possible for this VM.
1315	* @param pGuestFeatures The guest features to use (only VMX features are
1316	* accessed).
1317	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1318	*
1319	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1320	*/
1321	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1322	{
1323	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1324
1325	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1326	Assert(pGuestFeatures->fVmx);
1327
1328	/*
1329	* We don't support the following MSRs yet:
1330	* - True Pin-based VM-execution controls.
1331	* - True Processor-based VM-execution controls.
1332	* - True VM-entry VM-execution controls.
1333	* - True VM-exit VM-execution controls.
1334	*/
1335
1336	/* Basic information. */
1337	uint8_t const fTrueVmxMsrs = 1;
1338	{
1339	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1340	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1341	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1342	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1343	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1344	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1345	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1346	pGuestVmxMsrs->u64Basic = u64Basic;
1347	}
1348
1349	/* Pin-based VM-execution controls. */
1350	{
1351	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1352	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1353	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1354	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1355	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1356	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1357	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1358	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1359	fAllowed0, fAllowed1, fFeatures));
1360	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1361
1362	/* True pin-based VM-execution controls. */
1363	if (fTrueVmxMsrs)
1364	{
1365	/* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1366	pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1367	}
1368	}
1369
1370	/* Processor-based VM-execution controls. */
1371	{
1372	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1373	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1374	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1375	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1376	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1377	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1378	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1379	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1380	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1381	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1382	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1383	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1384	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1385	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1386	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1387	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1388	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1389	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1390	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1391	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1392	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1393	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1394	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1395	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1396	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1397	fAllowed1, fFeatures));
1398	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1399
1400	/* True processor-based VM-execution controls. */
1401	if (fTrueVmxMsrs)
1402	{
1403	/* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1404	uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1405	\| VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1406	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1407	pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1408	}
1409	}
1410
1411	/* Secondary processor-based VM-execution controls. */
1412	if (pGuestFeatures->fVmxSecondaryExecCtls)
1413	{
1414	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1415	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1416	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1417	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1418	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1419	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1420	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1421	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1422	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1423	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1424	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1425	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1426	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1427	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1428	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1429	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1430	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1431	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1432	\| (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1433	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1434	\| (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1435	\| (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1436	\| (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1437	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1438	\| (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1439	\| (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT );
1440	uint32_t const fAllowed0 = 0;
1441	uint32_t const fAllowed1 = fFeatures;
1442	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1443	}
1444
1445	/* Tertiary processor-based VM-execution controls. */
1446	if (pGuestFeatures->fVmxTertiaryExecCtls)
1447	{
1448	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1449	}
1450
1451	/* VM-exit controls. */
1452	{
1453	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1454	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1455	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1456	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1457	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1458	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1459	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1460	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1461	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1462	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1463	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1464	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1465	fAllowed1, fFeatures));
1466	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1467
1468	/* True VM-exit controls. */
1469	if (fTrueVmxMsrs)
1470	{
1471	/* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1472	uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1473	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1474	pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1475	}
1476	}
1477
1478	/* VM-entry controls. */
1479	{
1480	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1481	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1482	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1483	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1484	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1485	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1486	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1487	fAllowed1, fFeatures));
1488	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1489
1490	/* True VM-entry controls. */
1491	if (fTrueVmxMsrs)
1492	{
1493	/* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1494	uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1495	\| VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1496	\| VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1497	\| VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1498	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1499	pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1500	}
1501	}
1502
1503	/* Miscellaneous data. */
1504	{
1505	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1506
1507	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1508	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1509	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1510	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1511	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1512	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1513	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1514	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1515	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1516	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1517	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1518	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1519	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1520	}
1521
1522	/* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1523	pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1524
1525	/* CR0 Fixed-1. */
1526	{
1527	/*
1528	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1529	* This is different from CR4 fixed-1 bits which are reported as per the
1530	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1531	*/
1532	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1533	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1534	}
1535
1536	/* CR4 Fixed-0. */
1537	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1538
1539	/* CR4 Fixed-1. */
1540	{
1541	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1542	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1543	}
1544
1545	/* VMCS Enumeration. */
1546	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1547
1548	/* VPID and EPT Capabilities. */
1549	if (pGuestFeatures->fVmxEpt)
1550	{
1551	/*
1552	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1553	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1554	* when INVVPID instruction is supported just to be more compatible with guest
1555	* hypervisors that may make assumptions by only looking at this MSR even though they
1556	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1557	*
1558	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1559	* See Intel spec. 30.3 "VMX Instructions".
1560	*/
1561	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1562	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1563
1564	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1565	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1566	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1567	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1568	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1569	uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G);
1570	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1571	/** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1572	/* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1573	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1574	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1575	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1576	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1577	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1578	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1579	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1580	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1581	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1582	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1583	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1584	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage)
1585	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1586	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1587	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1588	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1589	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1590	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1591	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1592	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1593	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1594	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1595	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1596	}
1597
1598	/* VM Functions. */
1599	if (pGuestFeatures->fVmxVmFunc)
1600	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1601	}
1602
1603
1604	/**
1605	* Checks whether the given guest CPU VMX features are compatible with the provided
1606	* base features.
1607	*
1608	* @returns @c true if compatible, @c false otherwise.
1609	* @param pVM The cross context VM structure.
1610	* @param pBase The base VMX CPU features.
1611	* @param pGst The guest VMX CPU features.
1612	*
1613	* @remarks Only VMX feature bits are examined.
1614	*/
1615	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1616	{
1617	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1618	return false;
1619
1620	#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1621	#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1622	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1623	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1624	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1625	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1626	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1627	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1628	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1629	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1630	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1631	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1632	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1633	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1634	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1635	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1636	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1637	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1638	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1639	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1640	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1641	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1642	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1643	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1644	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1645	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1646	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1647	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1648	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1649	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1650	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1651	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1652	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1653	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1654	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1655	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1656	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1657	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1658	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1659	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1660	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1661	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1662	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1663	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1664	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1665	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1666	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1667	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1668	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1669	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 49) \
1670	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 50) \
1671	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 51) \
1672	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 52) \
1673	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 53) \
1674	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 54) \
1675	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 55) \
1676	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 56) \
1677	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 57) \
1678	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 58) \
1679	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 59) \
1680	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 60) \
1681	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 61) \
1682	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 62) \
1683	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 63))
1684
1685	#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 0) \
1686	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 1) \
1687	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 2) \
1688	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 3) \
1689	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 4) \
1690	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 5) \
1691	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 6) \
1692	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 7))
1693
1694	/* Check first set of feature bits. */
1695	{
1696	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1697	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1698	if ((fBase \| fGst) != fBase)
1699	{
1700	uint64_t const fDiff = fBase ^ fGst;
1701	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1702	fBase, fGst, fDiff));
1703	return false;
1704	}
1705	}
1706
1707	/* Check second set of feature bits. */
1708	{
1709	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1710	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1711	if ((fBase \| fGst) != fBase)
1712	{
1713	uint64_t const fDiff = fBase ^ fGst;
1714	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1715	fBase, fGst, fDiff));
1716	return false;
1717	}
1718	}
1719	#undef CPUM_VMX_FEAT_SHIFT
1720	#undef CPUM_VMX_MAKE_FEATURES_1
1721	#undef CPUM_VMX_MAKE_FEATURES_2
1722
1723	return true;
1724	}
1725
1726
1727	/**
1728	* Initializes VMX guest features and MSRs.
1729	*
1730	* @param pVM The cross context VM structure.
1731	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1732	* and no hardware-assisted nested-guest execution is
1733	* possible for this VM.
1734	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1735	*/
1736	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1737	{
1738	Assert(pVM);
1739	Assert(pGuestVmxMsrs);
1740
1741	/*
1742	* While it would be nice to check this earlier while initializing fNestedVmxEpt
1743	* but we would not have enumearted host features then, so do it at least now.
1744	*/
1745	if ( !pVM->cpum.s.HostFeatures.fNoExecute
1746	&& pVM->cpum.s.fNestedVmxEpt)
1747	{
1748	LogRel(("CPUM: Warning! EPT not exposed to the guest since NX isn't available on the host.\n"));
1749	pVM->cpum.s.fNestedVmxEpt = false;
1750	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1751	}
1752
1753	/*
1754	* Initialize the set of VMX features we emulate.
1755	*
1756	* Note! Some bits might be reported as 1 always if they fall under the
1757	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1758	*/
1759	CPUMFEATURES EmuFeat;
1760	RT_ZERO(EmuFeat);
1761	EmuFeat.fVmx = 1;
1762	EmuFeat.fVmxInsOutInfo = 1;
1763	EmuFeat.fVmxExtIntExit = 1;
1764	EmuFeat.fVmxNmiExit = 1;
1765	EmuFeat.fVmxVirtNmi = 1;
1766	EmuFeat.fVmxPreemptTimer = pVM->cpum.s.fNestedVmxPreemptTimer;
1767	EmuFeat.fVmxPostedInt = 0;
1768	EmuFeat.fVmxIntWindowExit = 1;
1769	EmuFeat.fVmxTscOffsetting = 1;
1770	EmuFeat.fVmxHltExit = 1;
1771	EmuFeat.fVmxInvlpgExit = 1;
1772	EmuFeat.fVmxMwaitExit = 1;
1773	EmuFeat.fVmxRdpmcExit = 1;
1774	EmuFeat.fVmxRdtscExit = 1;
1775	EmuFeat.fVmxCr3LoadExit = 1;
1776	EmuFeat.fVmxCr3StoreExit = 1;
1777	EmuFeat.fVmxTertiaryExecCtls = 0;
1778	EmuFeat.fVmxCr8LoadExit = 1;
1779	EmuFeat.fVmxCr8StoreExit = 1;
1780	EmuFeat.fVmxUseTprShadow = 1;
1781	EmuFeat.fVmxNmiWindowExit = 0;
1782	EmuFeat.fVmxMovDRxExit = 1;
1783	EmuFeat.fVmxUncondIoExit = 1;
1784	EmuFeat.fVmxUseIoBitmaps = 1;
1785	EmuFeat.fVmxMonitorTrapFlag = 0;
1786	EmuFeat.fVmxUseMsrBitmaps = 1;
1787	EmuFeat.fVmxMonitorExit = 1;
1788	EmuFeat.fVmxPauseExit = 1;
1789	EmuFeat.fVmxSecondaryExecCtls = 1;
1790	EmuFeat.fVmxVirtApicAccess = 1;
1791	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1792	EmuFeat.fVmxDescTableExit = 1;
1793	EmuFeat.fVmxRdtscp = 1;
1794	EmuFeat.fVmxVirtX2ApicMode = 0;
1795	EmuFeat.fVmxVpid = 0; /** @todo Consider enabling this when EPT works. */
1796	EmuFeat.fVmxWbinvdExit = 1;
1797	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1798	EmuFeat.fVmxApicRegVirt = 0;
1799	EmuFeat.fVmxVirtIntDelivery = 0;
1800	EmuFeat.fVmxPauseLoopExit = 0;
1801	EmuFeat.fVmxRdrandExit = 0;
1802	EmuFeat.fVmxInvpcid = 1;
1803	EmuFeat.fVmxVmFunc = 0;
1804	EmuFeat.fVmxVmcsShadowing = 0;
1805	EmuFeat.fVmxRdseedExit = 0;
1806	EmuFeat.fVmxPml = 0;
1807	EmuFeat.fVmxEptXcptVe = 0;
1808	EmuFeat.fVmxConcealVmxFromPt = 0;
1809	EmuFeat.fVmxXsavesXrstors = 0;
1810	EmuFeat.fVmxModeBasedExecuteEpt = 0;
1811	EmuFeat.fVmxSppEpt = 0;
1812	EmuFeat.fVmxPtEpt = 0;
1813	EmuFeat.fVmxUseTscScaling = 0;
1814	EmuFeat.fVmxUserWaitPause = 0;
1815	EmuFeat.fVmxEnclvExit = 0;
1816	EmuFeat.fVmxLoadIwKeyExit = 0;
1817	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1818	EmuFeat.fVmxIa32eModeGuest = 1;
1819	EmuFeat.fVmxEntryLoadEferMsr = 1;
1820	EmuFeat.fVmxEntryLoadPatMsr = 0;
1821	EmuFeat.fVmxExitSaveDebugCtls = 1;
1822	EmuFeat.fVmxHostAddrSpaceSize = 1;
1823	EmuFeat.fVmxExitAckExtInt = 1;
1824	EmuFeat.fVmxExitSavePatMsr = 0;
1825	EmuFeat.fVmxExitLoadPatMsr = 0;
1826	EmuFeat.fVmxExitSaveEferMsr = 1;
1827	EmuFeat.fVmxExitLoadEferMsr = 1;
1828	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1829	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1830	EmuFeat.fVmxPt = 0;
1831	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1832	EmuFeat.fVmxEntryInjectSoftInt = 1;
1833
1834	/*
1835	* Merge guest features.
1836	*
1837	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1838	* by the hardware, hence we merge our emulated features with the host features below.
1839	*/
1840	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1841	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1842	Assert(pBaseFeat->fVmx);
1843	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1844	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1845	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1846	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1847	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1848	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1849	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1850	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1851	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1852	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1853	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1854	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1855	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1856	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1857	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1858	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1859	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1860	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1861	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1862	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1863	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1864	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1865	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1866	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1867	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1868	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1869	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1870	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1871	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1872	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1873	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1874	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1875	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1876	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1877	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1878	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1879	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1880	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1881	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1882	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1883	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1884	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1885	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1886	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1887	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1888	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1889	pGuestFeat->fVmxConcealVmxFromPt = (pBaseFeat->fVmxConcealVmxFromPt & EmuFeat.fVmxConcealVmxFromPt );
1890	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1891	pGuestFeat->fVmxModeBasedExecuteEpt = (pBaseFeat->fVmxModeBasedExecuteEpt & EmuFeat.fVmxModeBasedExecuteEpt );
1892	pGuestFeat->fVmxSppEpt = (pBaseFeat->fVmxSppEpt & EmuFeat.fVmxSppEpt );
1893	pGuestFeat->fVmxPtEpt = (pBaseFeat->fVmxPtEpt & EmuFeat.fVmxPtEpt );
1894	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1895	pGuestFeat->fVmxUserWaitPause = (pBaseFeat->fVmxUserWaitPause & EmuFeat.fVmxUserWaitPause );
1896	pGuestFeat->fVmxEnclvExit = (pBaseFeat->fVmxEnclvExit & EmuFeat.fVmxEnclvExit );
1897	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1898	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1899	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1900	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1901	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1902	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1903	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1904	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1905	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1906	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1907	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1908	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1909	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1910	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1911	pGuestFeat->fVmxPt = (pBaseFeat->fVmxPt & EmuFeat.fVmxPt );
1912	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1913	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1914
1915	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1916	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1917	if ( pGuestFeat->fVmxPreemptTimer
1918	&& HMIsSubjectToVmxPreemptTimerErratum())
1919	{
1920	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1921	pGuestFeat->fVmxPreemptTimer = 0;
1922	pGuestFeat->fVmxSavePreemptTimer = 0;
1923	}
1924	#endif
1925
1926	/* Sanity checking. */
1927	if (!pGuestFeat->fVmxSecondaryExecCtls)
1928	{
1929	Assert(!pGuestFeat->fVmxVirtApicAccess);
1930	Assert(!pGuestFeat->fVmxEpt);
1931	Assert(!pGuestFeat->fVmxDescTableExit);
1932	Assert(!pGuestFeat->fVmxRdtscp);
1933	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1934	Assert(!pGuestFeat->fVmxVpid);
1935	Assert(!pGuestFeat->fVmxWbinvdExit);
1936	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1937	Assert(!pGuestFeat->fVmxApicRegVirt);
1938	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1939	Assert(!pGuestFeat->fVmxPauseLoopExit);
1940	Assert(!pGuestFeat->fVmxRdrandExit);
1941	Assert(!pGuestFeat->fVmxInvpcid);
1942	Assert(!pGuestFeat->fVmxVmFunc);
1943	Assert(!pGuestFeat->fVmxVmcsShadowing);
1944	Assert(!pGuestFeat->fVmxRdseedExit);
1945	Assert(!pGuestFeat->fVmxPml);
1946	Assert(!pGuestFeat->fVmxEptXcptVe);
1947	Assert(!pGuestFeat->fVmxConcealVmxFromPt);
1948	Assert(!pGuestFeat->fVmxXsavesXrstors);
1949	Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
1950	Assert(!pGuestFeat->fVmxSppEpt);
1951	Assert(!pGuestFeat->fVmxPtEpt);
1952	Assert(!pGuestFeat->fVmxUseTscScaling);
1953	Assert(!pGuestFeat->fVmxUserWaitPause);
1954	Assert(!pGuestFeat->fVmxEnclvExit);
1955	}
1956	else if (pGuestFeat->fVmxUnrestrictedGuest)
1957	{
1958	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1959	Assert(pGuestFeat->fVmxExitSaveEferLma);
1960	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1961	Assert(pGuestFeat->fVmxEpt);
1962	}
1963
1964	if (!pGuestFeat->fVmxTertiaryExecCtls)
1965	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1966
1967	/*
1968	* Finally initialize the VMX guest MSRs.
1969	*/
1970	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1971	}
1972
1973
1974	/**
1975	* Gets the host hardware-virtualization MSRs.
1976	*
1977	* @returns VBox status code.
1978	* @param pMsrs Where to store the MSRs.
1979	*/
1980	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1981	{
1982	Assert(pMsrs);
1983
1984	uint32_t fCaps = 0;
1985	int rc = SUPR3QueryVTCaps(&fCaps);
1986	if (RT_SUCCESS(rc))
1987	{
1988	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
1989	{
1990	SUPHWVIRTMSRS HwvirtMsrs;
1991	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
1992	if (RT_SUCCESS(rc))
1993	{
1994	if (fCaps & SUPVTCAPS_VT_X)
1995	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
1996	else
1997	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
1998	return VINF_SUCCESS;
1999	}
2000
2001	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2002	return rc;
2003	}
2004
2005	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2006	return VERR_INTERNAL_ERROR_5;
2007	}
2008	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2009	return VINF_SUCCESS;
2010	}
2011
2012
2013	/**
2014	* @callback_method_impl{FNTMTIMERINT,
2015	* Callback that fires when the nested VMX-preemption timer expired.}
2016	*/
2017	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2018	{
2019	RT_NOREF(pVM, hTimer);
2020	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2021	AssertPtr(pVCpu);
2022	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2023	}
2024
2025
2026	/**
2027	* Initializes the CPUM.
2028	*
2029	* @returns VBox status code.
2030	* @param pVM The cross context VM structure.
2031	*/
2032	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2033	{
2034	LogFlow(("CPUMR3Init\n"));
2035
2036	/*
2037	* Assert alignment, sizes and tables.
2038	*/
2039	AssertCompileMemberAlignment(VM, cpum.s, 32);
2040	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2041	AssertCompileSizeAlignment(CPUMCTX, 64);
2042	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2043	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2044	AssertCompileMemberAlignment(VM, cpum, 64);
2045	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2046	#ifdef VBOX_STRICT
2047	int rc2 = cpumR3MsrStrictInitChecks();
2048	AssertRCReturn(rc2, rc2);
2049	#endif
2050
2051	/*
2052	* Gather info about the host CPU.
2053	*/
2054	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2055	if (!ASMHasCpuId())
2056	{
2057	LogRel(("The CPU doesn't support CPUID!\n"));
2058	return VERR_UNSUPPORTED_CPU;
2059	}
2060
2061	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2062	#endif
2063
2064	CPUMMSRS HostMsrs;
2065	RT_ZERO(HostMsrs);
2066	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2067	AssertLogRelRCReturn(rc, rc);
2068
2069	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2070	/* Use the host features detected by CPUMR0ModuleInit if available. */
2071	if (pVM->cpum.s.HostFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2072	g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures;
2073	else
2074	{
2075	PCPUMCPUIDLEAF paLeaves;
2076	uint32_t cLeaves;
2077	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2078	AssertLogRelRCReturn(rc, rc);
2079
2080	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2081	RTMemFree(paLeaves);
2082	AssertLogRelRCReturn(rc, rc);
2083	}
2084	pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2085	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2086	#endif
2087
2088	/*
2089	* Check that the CPU supports the minimum features we require.
2090	*/
2091	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2092	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2093	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2094	if (!pVM->cpum.s.HostFeatures.fMmx)
2095	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2096	if (!pVM->cpum.s.HostFeatures.fTsc)
2097	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2098	#endif
2099
2100	/*
2101	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2102	*/
2103	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2104	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2105
2106	/*
2107	* Figure out which XSAVE/XRSTOR features are available on the host.
2108	*/
2109	uint64_t fXcr0Host = 0;
2110	uint64_t fXStateHostMask = 0;
2111	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2112	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2113	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2114	{
2115	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2116	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2117	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2118	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2119	}
2120	#endif
2121	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2122	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2123	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2124
2125	/*
2126	* Initialize the host XSAVE/XRSTOR mask.
2127	*/
2128	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2129	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2130	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2131	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2132	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2133	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2134	, VERR_CPUM_IPE_2);
2135	#endif
2136
2137	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2138	{
2139	PVMCPU pVCpu = pVM->apCpusR3[i];
2140
2141	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2142	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2143	}
2144
2145	/*
2146	* Register saved state data item.
2147	*/
2148	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2149	NULL, cpumR3LiveExec, NULL,
2150	NULL, cpumR3SaveExec, NULL,
2151	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2152	if (RT_FAILURE(rc))
2153	return rc;
2154
2155	/*
2156	* Register info handlers and registers with the debugger facility.
2157	*/
2158	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2159	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2160	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2161	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2162	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2163	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2164	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2165	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2166	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2167	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2168	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2169	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2170	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2171	&cpumR3CpuIdInfo);
2172	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2173	&cpumR3InfoVmxFeatures);
2174
2175	rc = cpumR3DbgInit(pVM);
2176	if (RT_FAILURE(rc))
2177	return rc;
2178
2179	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2180	/*
2181	* Check if we need to workaround partial/leaky FPU handling.
2182	*/
2183	cpumR3CheckLeakyFpu(pVM);
2184	#endif
2185
2186	/*
2187	* Initialize the Guest CPUID and MSR states.
2188	*/
2189	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2190	if (RT_FAILURE(rc))
2191	return rc;
2192
2193	/*
2194	* Init the VMX/SVM state.
2195	*
2196	* This must be done after initializing CPUID/MSR features as we access the
2197	* the VMX/SVM guest features below.
2198	*
2199	* In the case of nested VT-x, we also need to create the per-VCPU
2200	* VMX preemption timers.
2201	*/
2202	if (pVM->cpum.s.GuestFeatures.fVmx)
2203	cpumR3InitVmxHwVirtState(pVM);
2204	else if (pVM->cpum.s.GuestFeatures.fSvm)
2205	cpumR3InitSvmHwVirtState(pVM);
2206	else
2207	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2208
2209	CPUMR3Reset(pVM);
2210	return VINF_SUCCESS;
2211	}
2212
2213
2214	/**
2215	* Applies relocations to data and code managed by this
2216	* component. This function will be called at init and
2217	* whenever the VMM need to relocate it self inside the GC.
2218	*
2219	* The CPUM will update the addresses used by the switcher.
2220	*
2221	* @param pVM The cross context VM structure.
2222	*/
2223	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2224	{
2225	RT_NOREF(pVM);
2226	}
2227
2228
2229	/**
2230	* Terminates the CPUM.
2231	*
2232	* Termination means cleaning up and freeing all resources,
2233	* the VM it self is at this point powered off or suspended.
2234	*
2235	* @returns VBox status code.
2236	* @param pVM The cross context VM structure.
2237	*/
2238	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2239	{
2240	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2241	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2242	{
2243	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2244	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2245	pVCpu->cpum.s.uMagic = 0;
2246	pvCpu->cpum.s.Guest.dr[5] = 0;
2247	}
2248	#endif
2249
2250	if (pVM->cpum.s.GuestFeatures.fVmx)
2251	{
2252	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2253	{
2254	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2255	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2256	{
2257	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2258	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2259	}
2260	}
2261	}
2262	return VINF_SUCCESS;
2263	}
2264
2265
2266	/**
2267	* Resets a virtual CPU.
2268	*
2269	* Used by CPUMR3Reset and CPU hot plugging.
2270	*
2271	* @param pVM The cross context VM structure.
2272	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2273	* being reset. This may differ from the current EMT.
2274	*/
2275	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2276	{
2277	/** @todo anything different for VCPU > 0? */
2278	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2279
2280	/*
2281	* Initialize everything to ZERO first.
2282	*/
2283	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2284
2285	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2286
2287	pVCpu->cpum.s.fUseFlags = fUseFlags;
2288
2289	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2290	pCtx->eip = 0x0000fff0;
2291	pCtx->edx = 0x00000600; /* P6 processor */
2292	pCtx->eflags.Bits.u1Reserved0 = 1;
2293
2294	pCtx->cs.Sel = 0xf000;
2295	pCtx->cs.ValidSel = 0xf000;
2296	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2297	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2298	pCtx->cs.u32Limit = 0x0000ffff;
2299	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2300	pCtx->cs.Attr.n.u1Present = 1;
2301	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2302
2303	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2304	pCtx->ds.u32Limit = 0x0000ffff;
2305	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2306	pCtx->ds.Attr.n.u1Present = 1;
2307	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2308
2309	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2310	pCtx->es.u32Limit = 0x0000ffff;
2311	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2312	pCtx->es.Attr.n.u1Present = 1;
2313	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2314
2315	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2316	pCtx->fs.u32Limit = 0x0000ffff;
2317	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2318	pCtx->fs.Attr.n.u1Present = 1;
2319	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2320
2321	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2322	pCtx->gs.u32Limit = 0x0000ffff;
2323	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2324	pCtx->gs.Attr.n.u1Present = 1;
2325	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2326
2327	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2328	pCtx->ss.u32Limit = 0x0000ffff;
2329	pCtx->ss.Attr.n.u1Present = 1;
2330	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2331	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2332
2333	pCtx->idtr.cbIdt = 0xffff;
2334	pCtx->gdtr.cbGdt = 0xffff;
2335
2336	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2337	pCtx->ldtr.u32Limit = 0xffff;
2338	pCtx->ldtr.Attr.n.u1Present = 1;
2339	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2340
2341	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2342	pCtx->tr.u32Limit = 0xffff;
2343	pCtx->tr.Attr.n.u1Present = 1;
2344	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2345
2346	pCtx->dr[6] = X86_DR6_INIT_VAL;
2347	pCtx->dr[7] = X86_DR7_INIT_VAL;
2348
2349	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2350	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2351	pFpuCtx->FCW = 0x37f;
2352
2353	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2354	IA-32 Processor States Following Power-up, Reset, or INIT */
2355	pFpuCtx->MXCSR = 0x1F80;
2356	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2357
2358	pCtx->aXcr[0] = XSAVE_C_X87;
2359	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2360	{
2361	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2362	as we don't know what happened before. (Bother optimize later?) */
2363	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2364	}
2365
2366	/*
2367	* MSRs.
2368	*/
2369	/* Init PAT MSR */
2370	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2371
2372	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2373	* The Intel docs don't mention it. */
2374	Assert(!pCtx->msrEFER);
2375
2376	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2377	is supposed to be here, just trying provide useful/sensible values. */
2378	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2379	if (pRange)
2380	{
2381	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2382	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2383	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2384	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2385	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2386	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2387	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2388	}
2389
2390	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2391
2392	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2393	* called from each EMT while we're getting called by CPUMR3Reset()
2394	* iteratively on the same thread. Fix later. */
2395	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2396	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2397	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2398	#endif
2399
2400
2401	/* C-state control. Guesses. */
2402	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2403	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2404	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2405	* functionality. The default value must be different due to incompatible write mask.
2406	*/
2407	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2408	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2409	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2410	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2411
2412	/*
2413	* Hardware virtualization state.
2414	*/
2415	CPUMSetGuestGif(pCtx, true);
2416	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2417	if (pVM->cpum.s.GuestFeatures.fVmx)
2418	cpumR3ResetVmxHwVirtState(pVCpu);
2419	else if (pVM->cpum.s.GuestFeatures.fSvm)
2420	cpumR3ResetSvmHwVirtState(pVCpu);
2421	}
2422
2423
2424	/**
2425	* Resets the CPU.
2426	*
2427	* @returns VINF_SUCCESS.
2428	* @param pVM The cross context VM structure.
2429	*/
2430	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2431	{
2432	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2433	{
2434	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2435	CPUMR3ResetCpu(pVM, pVCpu);
2436
2437	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2438
2439	/* Magic marker for searching in crash dumps. */
2440	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2441	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2442	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2443	#endif
2444	}
2445	}
2446
2447
2448
2449
2450	/**
2451	* Pass 0 live exec callback.
2452	*
2453	* @returns VINF_SSM_DONT_CALL_AGAIN.
2454	* @param pVM The cross context VM structure.
2455	* @param pSSM The saved state handle.
2456	* @param uPass The pass (0).
2457	*/
2458	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2459	{
2460	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2461	cpumR3SaveCpuId(pVM, pSSM);
2462	return VINF_SSM_DONT_CALL_AGAIN;
2463	}
2464
2465
2466	/**
2467	* Execute state save operation.
2468	*
2469	* @returns VBox status code.
2470	* @param pVM The cross context VM structure.
2471	* @param pSSM SSM operation handle.
2472	*/
2473	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2474	{
2475	/*
2476	* Save.
2477	*/
2478	SSMR3PutU32(pSSM, pVM->cCpus);
2479	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2480	CPUMCTX DummyHyperCtx;
2481	RT_ZERO(DummyHyperCtx);
2482	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2483	{
2484	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2485
2486	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2487
2488	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2489	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2490	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2491	if (pGstCtx->fXStateMask != 0)
2492	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2493	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2494	{
2495	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2496	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2497	}
2498	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2499	{
2500	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2501	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2502	}
2503	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2504	{
2505	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2506	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2507	}
2508	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2509	{
2510	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2511	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2512	}
2513	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2514	{
2515	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2516	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2517	}
2518	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2519	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2520	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2521	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2522	if (pVM->cpum.s.GuestFeatures.fSvm)
2523	{
2524	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2525	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2526	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2527	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2528	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2529	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2530	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2531	g_aSvmHwvirtHostState, NULL /* pvUser */);
2532	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2533	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2534	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2535	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2536	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2537	}
2538	if (pVM->cpum.s.GuestFeatures.fVmx)
2539	{
2540	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2541	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2542	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2543	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2544	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2545	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2546	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2547	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2548	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2549	0, g_aVmxHwvirtVmcs, NULL);
2550	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2551	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2552	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2553	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2554	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2555	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2556	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2557	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2558	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2559	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2560	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2561	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2562	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2563	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2564	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2565	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2566	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2567	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2568	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2569	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2570	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2571	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2572	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2573	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2574	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2575	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2576	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2577	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2578	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2579	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2580	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2581	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2582	}
2583	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2584	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2585	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2586	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2587	}
2588
2589	cpumR3SaveCpuId(pVM, pSSM);
2590	return VINF_SUCCESS;
2591	}
2592
2593
2594	/**
2595	* @callback_method_impl{FNSSMINTLOADPREP}
2596	*/
2597	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2598	{
2599	NOREF(pSSM);
2600	pVM->cpum.s.fPendingRestore = true;
2601	return VINF_SUCCESS;
2602	}
2603
2604
2605	/**
2606	* @callback_method_impl{FNSSMINTLOADEXEC}
2607	*/
2608	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2609	{
2610	int rc; /* Only for AssertRCReturn use. */
2611
2612	/*
2613	* Validate version.
2614	*/
2615	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2616	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2617	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2618	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2619	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2620	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2621	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2622	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2623	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2624	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2625	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2626	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2627	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2628	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2629	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2630	{
2631	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2632	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2633	}
2634
2635	if (uPass == SSM_PASS_FINAL)
2636	{
2637	/*
2638	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2639	* really old SSM file versions.)
2640	*/
2641	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2642	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2643	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2644	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2645
2646	/*
2647	* Figure x86 and ctx field definitions to use for older states.
2648	*/
2649	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2650	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2651	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2652	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2653	{
2654	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2655	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2656	}
2657	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2658	{
2659	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2660	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2661	}
2662
2663	/*
2664	* The hyper state used to preceed the CPU count. Starting with
2665	* XSAVE it was moved down till after we've got the count.
2666	*/
2667	CPUMCTX HyperCtxIgnored;
2668	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2669	{
2670	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2671	{
2672	X86FXSTATE Ign;
2673	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2674	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2675	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2676	}
2677	}
2678
2679	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2680	{
2681	uint32_t cCpus;
2682	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2683	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2684	VERR_SSM_UNEXPECTED_DATA);
2685	}
2686	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2687	\|\| pVM->cCpus == 1,
2688	("cCpus=%u\n", pVM->cCpus),
2689	VERR_SSM_UNEXPECTED_DATA);
2690
2691	uint32_t cbMsrs = 0;
2692	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2693	{
2694	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2695	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2696	VERR_SSM_UNEXPECTED_DATA);
2697	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2698	VERR_SSM_UNEXPECTED_DATA);
2699	}
2700
2701	/*
2702	* Do the per-CPU restoring.
2703	*/
2704	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2705	{
2706	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2707	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2708
2709	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2710	{
2711	/*
2712	* The XSAVE saved state layout moved the hyper state down here.
2713	*/
2714	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2715	AssertRCReturn(rc, rc);
2716
2717	/*
2718	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2719	*/
2720	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2721	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2722	AssertRCReturn(rc, rc);
2723
2724	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2725	if (pGstCtx->fXStateMask != 0)
2726	{
2727	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2728	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2729	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2730	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2731	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2732	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2733	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2734	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2735	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2736	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2737	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2738	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2739	}
2740
2741	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2742	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2743	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2744	{
2745	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2746	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2747	VERR_CPUM_INVALID_XCR0);
2748	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2749	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2750	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2751	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2752	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2753	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2754	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2755	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2756	}
2757
2758	/* Check that the XCR1 is zero, as we don't implement it yet. */
2759	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2760
2761	/*
2762	* Restore the individual extended state components we support.
2763	*/
2764	if (pGstCtx->fXStateMask != 0)
2765	{
2766	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2767	0, g_aCpumXSaveHdrFields, NULL);
2768	AssertRCReturn(rc, rc);
2769	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2770	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2771	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2772	VERR_CPUM_INVALID_XSAVE_HDR);
2773	}
2774	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2775	{
2776	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2777	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2778	}
2779	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2780	{
2781	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2782	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2783	}
2784	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2785	{
2786	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2787	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2788	}
2789	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2790	{
2791	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2792	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2793	}
2794	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2795	{
2796	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2797	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2798	}
2799	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2800	{
2801	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2802	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2803	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2804	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2805	}
2806	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2807	{
2808	if (pVM->cpum.s.GuestFeatures.fSvm)
2809	{
2810	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2811	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2812	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2813	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2814	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2815	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2816	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2817	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2818	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2819	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2820	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2821	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2822	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2823	}
2824	}
2825	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2826	{
2827	if (pVM->cpum.s.GuestFeatures.fVmx)
2828	{
2829	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2830	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2831	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2832	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2833	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2834	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2835	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2836	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2837	0, g_aVmxHwvirtVmcs, NULL);
2838	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2839	0, g_aVmxHwvirtVmcs, NULL);
2840	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2841	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2842	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2843	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2844	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2845	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2846	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2847	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2848	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2849	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2850	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2851	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2852	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2853	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2854	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2855	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2856	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2857	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2858	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2859	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2860	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2861	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2862	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2863	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2864	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2865	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2866	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2867	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2868	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2869	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2870	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2871	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2872	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2873	}
2874	}
2875	}
2876	else
2877	{
2878	/*
2879	* Pre XSAVE saved state.
2880	*/
2881	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2882	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2883	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2884	}
2885
2886	/*
2887	* Restore a couple of flags and the MSRs.
2888	*/
2889	uint32_t fIgnoredUsedFlags = 0;
2890	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2891	AssertRCReturn(rc, rc);
2892	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2893
2894	rc = VINF_SUCCESS;
2895	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2896	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2897	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2898	{
2899	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2900	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2901	}
2902	AssertRCReturn(rc, rc);
2903
2904	/* REM and other may have cleared must-be-one fields in DR6 and
2905	DR7, fix these. */
2906	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2907	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2908	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2909	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2910	}
2911
2912	/* Older states does not have the internal selector register flags
2913	and valid selector value. Supply those. */
2914	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2915	{
2916	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2917	{
2918	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2919	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2920	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2921	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2922	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2923	if (fValid)
2924	{
2925	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2926	{
2927	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2928	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2929	}
2930
2931	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2932	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2933	}
2934	else
2935	{
2936	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2937	{
2938	paSelReg[iSelReg].fFlags = 0;
2939	paSelReg[iSelReg].ValidSel = 0;
2940	}
2941
2942	/* This might not be 104% correct, but I think it's close
2943	enough for all practical purposes... (REM always loaded
2944	LDTR registers.) */
2945	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2946	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2947	}
2948	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2949	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2950	}
2951	}
2952
2953	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2954	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2955	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2956	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2957	{
2958	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2959	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2960	}
2961
2962	/*
2963	* A quick sanity check.
2964	*/
2965	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2966	{
2967	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2968	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2969	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2970	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2971	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2972	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2973	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2974	}
2975	}
2976
2977	pVM->cpum.s.fPendingRestore = false;
2978
2979	/*
2980	* Guest CPUIDs (and VMX MSR features).
2981	*/
2982	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2983	{
2984	CPUMMSRS GuestMsrs;
2985	RT_ZERO(GuestMsrs);
2986
2987	CPUMFEATURES BaseFeatures;
2988	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
2989	if (fVmxGstFeat)
2990	{
2991	/*
2992	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
2993	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
2994	* here so we can compare them for compatibility after exploding guest features.
2995	*/
2996	BaseFeatures = pVM->cpum.s.GuestFeatures;
2997
2998	/* Use the VMX MSR features from the saved state while exploding guest features. */
2999	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3000	}
3001
3002	/* Load CPUID and explode guest features. */
3003	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3004	if (fVmxGstFeat)
3005	{
3006	/*
3007	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3008	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3009	* VMX features presented to the guest.
3010	*/
3011	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3012	if (!fIsCompat)
3013	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3014	}
3015	return rc;
3016	}
3017	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3018	}
3019
3020
3021	/**
3022	* @callback_method_impl{FNSSMINTLOADDONE}
3023	*/
3024	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3025	{
3026	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3027	return VINF_SUCCESS;
3028
3029	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3030	if (pVM->cpum.s.fPendingRestore)
3031	{
3032	LogRel(("CPUM: Missing state!\n"));
3033	return VERR_INTERNAL_ERROR_2;
3034	}
3035
3036	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3037	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3038	{
3039	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3040
3041	/* Notify PGM of the NXE states in case they've changed. */
3042	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3043
3044	/* During init. this is done in CPUMR3InitCompleted(). */
3045	if (fSupportsLongMode)
3046	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3047
3048	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3049	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3050	}
3051	return VINF_SUCCESS;
3052	}
3053
3054
3055	/**
3056	* Checks if the CPUM state restore is still pending.
3057	*
3058	* @returns true / false.
3059	* @param pVM The cross context VM structure.
3060	*/
3061	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3062	{
3063	return pVM->cpum.s.fPendingRestore;
3064	}
3065
3066
3067	/**
3068	* Formats the EFLAGS value into mnemonics.
3069	*
3070	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3071	* @param efl The EFLAGS value.
3072	*/
3073	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3074	{
3075	/*
3076	* Format the flags.
3077	*/
3078	static const struct
3079	{
3080	const char pszSet; const char pszClear; uint32_t fFlag;
3081	} s_aFlags[] =
3082	{
3083	{ "vip",NULL, X86_EFL_VIP },
3084	{ "vif",NULL, X86_EFL_VIF },
3085	{ "ac", NULL, X86_EFL_AC },
3086	{ "vm", NULL, X86_EFL_VM },
3087	{ "rf", NULL, X86_EFL_RF },
3088	{ "nt", NULL, X86_EFL_NT },
3089	{ "ov", "nv", X86_EFL_OF },
3090	{ "dn", "up", X86_EFL_DF },
3091	{ "ei", "di", X86_EFL_IF },
3092	{ "tf", NULL, X86_EFL_TF },
3093	{ "nt", "pl", X86_EFL_SF },
3094	{ "nz", "zr", X86_EFL_ZF },
3095	{ "ac", "na", X86_EFL_AF },
3096	{ "po", "pe", X86_EFL_PF },
3097	{ "cy", "nc", X86_EFL_CF },
3098	};
3099	char *psz = pszEFlags;
3100	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3101	{
3102	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3103	if (pszAdd)
3104	{
3105	strcpy(psz, pszAdd);
3106	psz += strlen(pszAdd);
3107	*psz++ = ' ';
3108	}
3109	}
3110	psz[-1] = '\0';
3111	}
3112
3113
3114	/**
3115	* Formats a full register dump.
3116	*
3117	* @param pVM The cross context VM structure.
3118	* @param pCtx The context to format.
3119	* @param pCtxCore The context core to format.
3120	* @param pHlp Output functions.
3121	* @param enmType The dump type.
3122	* @param pszPrefix Register name prefix.
3123	*/
3124	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3125	const char *pszPrefix)
3126	{
3127	NOREF(pVM);
3128
3129	/*
3130	* Format the EFLAGS.
3131	*/
3132	uint32_t efl = pCtxCore->eflags.u32;
3133	char szEFlags[80];
3134	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3135
3136	/*
3137	* Format the registers.
3138	*/
3139	switch (enmType)
3140	{
3141	case CPUMDUMPTYPE_TERSE:
3142	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3143	pHlp->pfnPrintf(pHlp,
3144	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3145	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3146	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3147	"%sr14=%016RX64 %sr15=%016RX64\n"
3148	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3149	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3150	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3151	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3152	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3153	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3154	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3155	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3156	else
3157	pHlp->pfnPrintf(pHlp,
3158	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3159	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3160	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3161	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3162	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3163	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3164	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3165	break;
3166
3167	case CPUMDUMPTYPE_DEFAULT:
3168	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3169	pHlp->pfnPrintf(pHlp,
3170	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3171	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3172	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3173	"%sr14=%016RX64 %sr15=%016RX64\n"
3174	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3175	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3176	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3177	,
3178	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3179	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3180	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3181	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3182	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3183	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3184	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3185	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3186	else
3187	pHlp->pfnPrintf(pHlp,
3188	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3189	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3190	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3191	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3192	,
3193	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3194	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3195	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3196	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3197	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3198	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3199	break;
3200
3201	case CPUMDUMPTYPE_VERBOSE:
3202	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3203	pHlp->pfnPrintf(pHlp,
3204	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3205	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3206	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3207	"%sr14=%016RX64 %sr15=%016RX64\n"
3208	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3209	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3210	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3211	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3212	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3213	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3214	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3215	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3216	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3217	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3218	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3219	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3220	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3221	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3222	,
3223	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3224	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3225	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3226	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3227	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3228	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3229	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3230	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3231	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3232	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3233	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3234	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3235	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3236	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3237	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3238	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3239	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3240	else
3241	pHlp->pfnPrintf(pHlp,
3242	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3243	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3244	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3245	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3246	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3247	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3248	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3249	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3250	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3251	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3252	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3253	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3254	,
3255	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3256	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3257	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3258	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3259	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3260	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3261	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3262	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3263	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3264	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3265	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3266	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3267
3268	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3269	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3270	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3271	{
3272	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3273	pHlp->pfnPrintf(pHlp,
3274	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3275	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3276	,
3277	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3278	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3279	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3280	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3281	);
3282	/*
3283	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3284	* not (FP)R0-7 as Intel SDM suggests.
3285	*/
3286	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3287	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3288	{
3289	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3290	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3291	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3292	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3293	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3294	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3295	iExponent -= 16383; /* subtract bias */
3296	/** @todo This isn't entirenly correct and needs more work! */
3297	pHlp->pfnPrintf(pHlp,
3298	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3299	pszPrefix, iST, pszPrefix, iFPR,
3300	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3301	uTag, chSign, iInteger, u64Fraction, iExponent);
3302	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3303	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3304	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3305	else
3306	pHlp->pfnPrintf(pHlp, "\n");
3307	}
3308
3309	/* XMM/YMM/ZMM registers. */
3310	if (pCtx->fXStateMask & XSAVE_C_YMM)
3311	{
3312	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3313	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3314	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3315	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3316	pszPrefix, i, i < 10 ? " " : "",
3317	pYmmHiCtx->aYmmHi[i].au32[3],
3318	pYmmHiCtx->aYmmHi[i].au32[2],
3319	pYmmHiCtx->aYmmHi[i].au32[1],
3320	pYmmHiCtx->aYmmHi[i].au32[0],
3321	pFpuCtx->aXMM[i].au32[3],
3322	pFpuCtx->aXMM[i].au32[2],
3323	pFpuCtx->aXMM[i].au32[1],
3324	pFpuCtx->aXMM[i].au32[0]);
3325	else
3326	{
3327	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3328	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3329	pHlp->pfnPrintf(pHlp,
3330	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3331	pszPrefix, i, i < 10 ? " " : "",
3332	pZmmHi256->aHi256Regs[i].au32[7],
3333	pZmmHi256->aHi256Regs[i].au32[6],
3334	pZmmHi256->aHi256Regs[i].au32[5],
3335	pZmmHi256->aHi256Regs[i].au32[4],
3336	pZmmHi256->aHi256Regs[i].au32[3],
3337	pZmmHi256->aHi256Regs[i].au32[2],
3338	pZmmHi256->aHi256Regs[i].au32[1],
3339	pZmmHi256->aHi256Regs[i].au32[0],
3340	pYmmHiCtx->aYmmHi[i].au32[3],
3341	pYmmHiCtx->aYmmHi[i].au32[2],
3342	pYmmHiCtx->aYmmHi[i].au32[1],
3343	pYmmHiCtx->aYmmHi[i].au32[0],
3344	pFpuCtx->aXMM[i].au32[3],
3345	pFpuCtx->aXMM[i].au32[2],
3346	pFpuCtx->aXMM[i].au32[1],
3347	pFpuCtx->aXMM[i].au32[0]);
3348
3349	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3350	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3351	pHlp->pfnPrintf(pHlp,
3352	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3353	pszPrefix, i + 16,
3354	pZmm16Hi->aRegs[i].au32[15],
3355	pZmm16Hi->aRegs[i].au32[14],
3356	pZmm16Hi->aRegs[i].au32[13],
3357	pZmm16Hi->aRegs[i].au32[12],
3358	pZmm16Hi->aRegs[i].au32[11],
3359	pZmm16Hi->aRegs[i].au32[10],
3360	pZmm16Hi->aRegs[i].au32[9],
3361	pZmm16Hi->aRegs[i].au32[8],
3362	pZmm16Hi->aRegs[i].au32[7],
3363	pZmm16Hi->aRegs[i].au32[6],
3364	pZmm16Hi->aRegs[i].au32[5],
3365	pZmm16Hi->aRegs[i].au32[4],
3366	pZmm16Hi->aRegs[i].au32[3],
3367	pZmm16Hi->aRegs[i].au32[2],
3368	pZmm16Hi->aRegs[i].au32[1],
3369	pZmm16Hi->aRegs[i].au32[0]);
3370	}
3371	}
3372	else
3373	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3374	pHlp->pfnPrintf(pHlp,
3375	i & 1
3376	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3377	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3378	pszPrefix, i, i < 10 ? " " : "",
3379	pFpuCtx->aXMM[i].au32[3],
3380	pFpuCtx->aXMM[i].au32[2],
3381	pFpuCtx->aXMM[i].au32[1],
3382	pFpuCtx->aXMM[i].au32[0]);
3383
3384	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3385	{
3386	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3387	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3388	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3389	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3390	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3391	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3392	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3393	}
3394
3395	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3396	{
3397	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3398	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3399	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3400	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3401	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3402	}
3403
3404	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3405	{
3406	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3407	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3408	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3409	}
3410
3411	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3412	if (pFpuCtx->au32RsrvdRest[i])
3413	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3414	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3415	}
3416
3417	pHlp->pfnPrintf(pHlp,
3418	"%sEFER =%016RX64\n"
3419	"%sPAT =%016RX64\n"
3420	"%sSTAR =%016RX64\n"
3421	"%sCSTAR =%016RX64\n"
3422	"%sLSTAR =%016RX64\n"
3423	"%sSFMASK =%016RX64\n"
3424	"%sKERNELGSBASE =%016RX64\n",
3425	pszPrefix, pCtx->msrEFER,
3426	pszPrefix, pCtx->msrPAT,
3427	pszPrefix, pCtx->msrSTAR,
3428	pszPrefix, pCtx->msrCSTAR,
3429	pszPrefix, pCtx->msrLSTAR,
3430	pszPrefix, pCtx->msrSFMASK,
3431	pszPrefix, pCtx->msrKERNELGSBASE);
3432
3433	if (CPUMIsGuestInPAEModeEx(pCtx))
3434	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3435	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3436	break;
3437	}
3438	}
3439
3440
3441	/**
3442	* Display all cpu states and any other cpum info.
3443	*
3444	* @param pVM The cross context VM structure.
3445	* @param pHlp The info helper functions.
3446	* @param pszArgs Arguments, ignored.
3447	*/
3448	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3449	{
3450	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3451	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3452	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3453	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3454	cpumR3InfoHost(pVM, pHlp, pszArgs);
3455	}
3456
3457
3458	/**
3459	* Parses the info argument.
3460	*
3461	* The argument starts with 'verbose', 'terse' or 'default' and then
3462	* continues with the comment string.
3463	*
3464	* @param pszArgs The pointer to the argument string.
3465	* @param penmType Where to store the dump type request.
3466	* @param ppszComment Where to store the pointer to the comment string.
3467	*/
3468	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3469	{
3470	if (!pszArgs)
3471	{
3472	*penmType = CPUMDUMPTYPE_DEFAULT;
3473	*ppszComment = "";
3474	}
3475	else
3476	{
3477	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3478	{
3479	pszArgs += 7;
3480	*penmType = CPUMDUMPTYPE_VERBOSE;
3481	}
3482	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3483	{
3484	pszArgs += 5;
3485	*penmType = CPUMDUMPTYPE_TERSE;
3486	}
3487	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3488	{
3489	pszArgs += 7;
3490	*penmType = CPUMDUMPTYPE_DEFAULT;
3491	}
3492	else
3493	*penmType = CPUMDUMPTYPE_DEFAULT;
3494	*ppszComment = RTStrStripL(pszArgs);
3495	}
3496	}
3497
3498
3499	/**
3500	* Display the guest cpu state.
3501	*
3502	* @param pVM The cross context VM structure.
3503	* @param pHlp The info helper functions.
3504	* @param pszArgs Arguments.
3505	*/
3506	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3507	{
3508	CPUMDUMPTYPE enmType;
3509	const char *pszComment;
3510	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3511
3512	PVMCPU pVCpu = VMMGetCpu(pVM);
3513	if (!pVCpu)
3514	pVCpu = pVM->apCpusR3[0];
3515
3516	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3517
3518	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3519	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3520	}
3521
3522
3523	/**
3524	* Displays an SVM VMCB control area.
3525	*
3526	* @param pHlp The info helper functions.
3527	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3528	* @param pszPrefix Caller specified string prefix.
3529	*/
3530	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3531	{
3532	AssertReturnVoid(pHlp);
3533	AssertReturnVoid(pVmcbCtrl);
3534
3535	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3536	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3537	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3538	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3539	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3540	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3541	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3542	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3543	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3544	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3545	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3546	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3547	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3548	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3549	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3550	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3551	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3552	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3553	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3554	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3555	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3556	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3557	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3558	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3559	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3560	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3561	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3562	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3563	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3564	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3565	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3566	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3567	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3568	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3569	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3570	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3571	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3572	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3573	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3574	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3575	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3576	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3577	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3578	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3579	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3580	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3581	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3582	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3583	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3584	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3585	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3586	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3587	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3588	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3589	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3590	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3591	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3592	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3593	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3594	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3595	}
3596
3597
3598	/**
3599	* Helper for dumping the SVM VMCB selector registers.
3600	*
3601	* @param pHlp The info helper functions.
3602	* @param pSel Pointer to the SVM selector register.
3603	* @param pszName Name of the selector.
3604	* @param pszPrefix Caller specified string prefix.
3605	*/
3606	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3607	{
3608	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3609	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3610	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3611	}
3612
3613
3614	/**
3615	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3616	*
3617	* @param pHlp The info helper functions.
3618	* @param pXdtr Pointer to the descriptor table register.
3619	* @param pszName Name of the descriptor table register.
3620	* @param pszPrefix Caller specified string prefix.
3621	*/
3622	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3623	{
3624	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3625	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3626	}
3627
3628
3629	/**
3630	* Displays an SVM VMCB state-save area.
3631	*
3632	* @param pHlp The info helper functions.
3633	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3634	* @param pszPrefix Caller specified string prefix.
3635	*/
3636	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3637	{
3638	AssertReturnVoid(pHlp);
3639	AssertReturnVoid(pVmcbStateSave);
3640
3641	char szEFlags[80];
3642	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3643
3644	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3645	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3646	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3647	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3648	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3649	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3650	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3651	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3652	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3653	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3654	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3655	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3656	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3657	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3658	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3659	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3660	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3661	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3662	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3663	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3664	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3665	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3666	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3667	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3668	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3669	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3670	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3671	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3672	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3673	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3674	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3675	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3676	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3677	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3678	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3679	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3680	}
3681
3682
3683	/**
3684	* Displays a virtual-VMCS.
3685	*
3686	* @param pVCpu The cross context virtual CPU structure.
3687	* @param pHlp The info helper functions.
3688	* @param pVmcs Pointer to a virtual VMCS.
3689	* @param pszPrefix Caller specified string prefix.
3690	*/
3691	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3692	{
3693	AssertReturnVoid(pHlp);
3694	AssertReturnVoid(pVmcs);
3695
3696	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3697	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3698	do { \
3699	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3700	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3701	} while (0)
3702
3703	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3704	do { \
3705	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3706	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3707	} while (0)
3708
3709	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3710	do { \
3711	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3712	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3713	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3714	} while (0)
3715
3716	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3717	do { \
3718	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3719	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3720	} while (0)
3721
3722	/* Header. */
3723	{
3724	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3725	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3726	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3727	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3728	}
3729
3730	/* Control fields. */
3731	{
3732	/* 16-bit. */
3733	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3734	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3735	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3736	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3737
3738	/* 32-bit. */
3739	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3740	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3741	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3742	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3743	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3744	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3745	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3746	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3747	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3748	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3749	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3750	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3751	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3752	{
3753	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3754	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3755	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3756	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3757	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3758	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3759	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3760	}
3761	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3762	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3763	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3764	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3765	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3766
3767	/* 64-bit. */
3768	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3769	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3770	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3771	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3772	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3773	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3774	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3775	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3776	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3777	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3778	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3779	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3780	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3781	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3782	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3783	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3784	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3785	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3786	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3787	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3788	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3789	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3790	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3791	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3792	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3793	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3794	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3795	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3796
3797	/* Natural width. */
3798	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3799	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3800	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3801	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3802	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3803	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3804	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3805	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3806	}
3807
3808	/* Guest state. */
3809	{
3810	char szEFlags[80];
3811	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3812	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3813
3814	/* 16-bit. */
3815	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3816	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3817	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3818	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3819	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3820	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3821	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3822	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3823	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3824	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3825	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3826	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3827
3828	/* 32-bit. */
3829	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3830	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3831	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3832	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3833	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3834
3835	/* 64-bit. */
3836	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3837	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3838	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3839	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3840	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3841	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3842	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3843	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3844	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3845	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3846	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3847	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3848
3849	/* Natural width. */
3850	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3851	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3852	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3853	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3854	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3855	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3856	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3857	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3858	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3859	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3860	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3861	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3862	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3863	}
3864
3865	/* Host state. */
3866	{
3867	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3868
3869	/* 16-bit. */
3870	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3871	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3872	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3873	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3874	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3875	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3876	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3877	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3878	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3879
3880	/* 32-bit. */
3881	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3882
3883	/* 64-bit. */
3884	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3885	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3886	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3887	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3888
3889	/* Natural width. */
3890	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3891	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3892	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3893	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3894	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3895	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3896	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3897	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3898	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3899	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3900
3901	}
3902
3903	/* Read-only fields. */
3904	{
3905	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3906
3907	/* 16-bit (none currently). */
3908
3909	/* 32-bit. */
3910	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3911	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3912	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3913	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3914	{
3915	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3916	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3917	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3918	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3919	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3920	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3921	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3922	}
3923	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3924	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3925	{
3926	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3927	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3928	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3929	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3930	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3931	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3932	}
3933	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3934	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3935	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3936
3937	/* 64-bit. */
3938	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3939
3940	/* Natural width. */
3941	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3942	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3943	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3944	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3945	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3946	}
3947
3948	#ifdef DEBUG_ramshankar
3949	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3950	{
3951	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3952	Assert(pvPage);
3953	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3954	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3955	if (RT_SUCCESS(rc))
3956	{
3957	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3958	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3959	pHlp->pfnPrintf(pHlp, "\n");
3960	}
3961	RTMemTmpFree(pvPage);
3962	}
3963	#else
3964	NOREF(pVCpu);
3965	#endif
3966
3967	#undef CPUMVMX_DUMP_HOST_XDTR
3968	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3969	#undef CPUMVMX_DUMP_GUEST_SEGREG
3970	#undef CPUMVMX_DUMP_GUEST_XDTR
3971	}
3972
3973
3974	/**
3975	* Display the guest's hardware-virtualization cpu state.
3976	*
3977	* @param pVM The cross context VM structure.
3978	* @param pHlp The info helper functions.
3979	* @param pszArgs Arguments, ignored.
3980	*/
3981	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3982	{
3983	RT_NOREF(pszArgs);
3984
3985	PVMCPU pVCpu = VMMGetCpu(pVM);
3986	if (!pVCpu)
3987	pVCpu = pVM->apCpusR3[0];
3988
3989	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3990	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
3991	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
3992
3993	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3994	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3995	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
3996
3997	if (fSvm)
3998	{
3999	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4000	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4001
4002	char szEFlags[80];
4003	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4004	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4005	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4006	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4007	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4008	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4009	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4010	pHlp->pfnPrintf(pHlp, " HostState:\n");
4011	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4012	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4013	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4014	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4015	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4016	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4017	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4018	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4019	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4020	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4021	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4022	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4023	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4024	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4025	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4026	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4027	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4028	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4029	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4030	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4031	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4032	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4033	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4034	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4035	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4036	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4037	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4038	}
4039	else if (fVmx)
4040	{
4041	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4042	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4043	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4044	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4045	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4046	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4047	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4048	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4049	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4050	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4051	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4052	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4053	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4054	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4055	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4056	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4057	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4058	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4059	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4060	}
4061	else
4062	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4063
4064	#undef CPUMHWVIRTDUMP_NONE
4065	#undef CPUMHWVIRTDUMP_COMMON
4066	#undef CPUMHWVIRTDUMP_SVM
4067	#undef CPUMHWVIRTDUMP_VMX
4068	#undef CPUMHWVIRTDUMP_LAST
4069	#undef CPUMHWVIRTDUMP_ALL
4070	}
4071
4072	/**
4073	* Display the current guest instruction
4074	*
4075	* @param pVM The cross context VM structure.
4076	* @param pHlp The info helper functions.
4077	* @param pszArgs Arguments, ignored.
4078	*/
4079	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4080	{
4081	NOREF(pszArgs);
4082
4083	PVMCPU pVCpu = VMMGetCpu(pVM);
4084	if (!pVCpu)
4085	pVCpu = pVM->apCpusR3[0];
4086
4087	char szInstruction[256];
4088	szInstruction[0] = '\0';
4089	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4090	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4091	}
4092
4093
4094	/**
4095	* Display the hypervisor cpu state.
4096	*
4097	* @param pVM The cross context VM structure.
4098	* @param pHlp The info helper functions.
4099	* @param pszArgs Arguments, ignored.
4100	*/
4101	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4102	{
4103	PVMCPU pVCpu = VMMGetCpu(pVM);
4104	if (!pVCpu)
4105	pVCpu = pVM->apCpusR3[0];
4106
4107	CPUMDUMPTYPE enmType;
4108	const char *pszComment;
4109	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4110	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4111
4112	pHlp->pfnPrintf(pHlp,
4113	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4114	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4115	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4116	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4117	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4118	}
4119
4120
4121	/**
4122	* Display the host cpu state.
4123	*
4124	* @param pVM The cross context VM structure.
4125	* @param pHlp The info helper functions.
4126	* @param pszArgs Arguments, ignored.
4127	*/
4128	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4129	{
4130	CPUMDUMPTYPE enmType;
4131	const char *pszComment;
4132	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4133	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4134
4135	PVMCPU pVCpu = VMMGetCpu(pVM);
4136	if (!pVCpu)
4137	pVCpu = pVM->apCpusR3[0];
4138	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4139
4140	/*
4141	* Format the EFLAGS.
4142	*/
4143	uint64_t efl = pCtx->rflags;
4144	char szEFlags[80];
4145	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4146
4147	/*
4148	* Format the registers.
4149	*/
4150	pHlp->pfnPrintf(pHlp,
4151	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4152	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4153	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4154	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4155	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4156	"r14=%016RX64 r15=%016RX64\n"
4157	"iopl=%d %31s\n"
4158	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4159	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4160	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4161	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4162	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4163	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4164	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4165	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4166	,
4167	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4168	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4169	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4170	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4171	pCtx->r11, pCtx->r12, pCtx->r13,
4172	pCtx->r14, pCtx->r15,
4173	X86_EFL_GET_IOPL(efl), szEFlags,
4174	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4175	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4176	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4177	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4178	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4179	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4180	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4181	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4182	}
4183
4184	/**
4185	* Structure used when disassembling and instructions in DBGF.
4186	* This is used so the reader function can get the stuff it needs.
4187	*/
4188	typedef struct CPUMDISASSTATE
4189	{
4190	/** Pointer to the CPU structure. */
4191	PDISCPUSTATE pCpu;
4192	/** Pointer to the VM. */
4193	PVM pVM;
4194	/** Pointer to the VMCPU. */
4195	PVMCPU pVCpu;
4196	/** Pointer to the first byte in the segment. */
4197	RTGCUINTPTR GCPtrSegBase;
4198	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4199	RTGCUINTPTR GCPtrSegEnd;
4200	/** The size of the segment minus 1. */
4201	RTGCUINTPTR cbSegLimit;
4202	/** Pointer to the current page - R3 Ptr. */
4203	void const *pvPageR3;
4204	/** Pointer to the current page - GC Ptr. */
4205	RTGCPTR pvPageGC;
4206	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4207	PGMPAGEMAPLOCK PageMapLock;
4208	/** Whether the PageMapLock is valid or not. */
4209	bool fLocked;
4210	/** 64 bits mode or not. */
4211	bool f64Bits;
4212	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4213
4214
4215	/**
4216	* @callback_method_impl{FNDISREADBYTES}
4217	*/
4218	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4219	{
4220	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4221	for (;;)
4222	{
4223	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4224
4225	/*
4226	* Need to update the page translation?
4227	*/
4228	if ( !pState->pvPageR3
4229	\|\| (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
4230	{
4231	/* translate the address */
4232	pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
4233
4234	/* Release mapping lock previously acquired. */
4235	if (pState->fLocked)
4236	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4237	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4238	if (RT_SUCCESS(rc))
4239	pState->fLocked = true;
4240	else
4241	{
4242	pState->fLocked = false;
4243	pState->pvPageR3 = NULL;
4244	return rc;
4245	}
4246	}
4247
4248	/*
4249	* Check the segment limit.
4250	*/
4251	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4252	return VERR_OUT_OF_SELECTOR_BOUNDS;
4253
4254	/*
4255	* Calc how much we can read.
4256	*/
4257	uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
4258	if (!pState->f64Bits)
4259	{
4260	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4261	if (cb > cbSeg && cbSeg)
4262	cb = cbSeg;
4263	}
4264	if (cb > cbMaxRead)
4265	cb = cbMaxRead;
4266
4267	/*
4268	* Read and advance or exit.
4269	*/
4270	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
4271	offInstr += (uint8_t)cb;
4272	if (cb >= cbMinRead)
4273	{
4274	pDis->cbCachedInstr = offInstr;
4275	return VINF_SUCCESS;
4276	}
4277	cbMinRead -= (uint8_t)cb;
4278	cbMaxRead -= (uint8_t)cb;
4279	}
4280	}
4281
4282
4283	/**
4284	* Disassemble an instruction and return the information in the provided structure.
4285	*
4286	* @returns VBox status code.
4287	* @param pVM The cross context VM structure.
4288	* @param pVCpu The cross context virtual CPU structure.
4289	* @param pCtx Pointer to the guest CPU context.
4290	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4291	* @param pCpu Disassembly state.
4292	* @param pszPrefix String prefix for logging (debug only).
4293	*
4294	*/
4295	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4296	const char *pszPrefix)
4297	{
4298	CPUMDISASSTATE State;
4299	int rc;
4300
4301	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4302	State.pCpu = pCpu;
4303	State.pvPageGC = 0;
4304	State.pvPageR3 = NULL;
4305	State.pVM = pVM;
4306	State.pVCpu = pVCpu;
4307	State.fLocked = false;
4308	State.f64Bits = false;
4309
4310	/*
4311	* Get selector information.
4312	*/
4313	DISCPUMODE enmDisCpuMode;
4314	if ( (pCtx->cr0 & X86_CR0_PE)
4315	&& pCtx->eflags.Bits.u1VM == 0)
4316	{
4317	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4318	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4319	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4320	State.GCPtrSegBase = pCtx->cs.u64Base;
4321	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4322	State.cbSegLimit = pCtx->cs.u32Limit;
4323	enmDisCpuMode = (State.f64Bits)
4324	? DISCPUMODE_64BIT
4325	: pCtx->cs.Attr.n.u1DefBig
4326	? DISCPUMODE_32BIT
4327	: DISCPUMODE_16BIT;
4328	}
4329	else
4330	{
4331	/* real or V86 mode */
4332	enmDisCpuMode = DISCPUMODE_16BIT;
4333	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4334	State.GCPtrSegEnd = 0xFFFFFFFF;
4335	State.cbSegLimit = 0xFFFFFFFF;
4336	}
4337
4338	/*
4339	* Disassemble the instruction.
4340	*/
4341	uint32_t cbInstr;
4342	#ifndef LOG_ENABLED
4343	RT_NOREF_PV(pszPrefix);
4344	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4345	if (RT_SUCCESS(rc))
4346	{
4347	#else
4348	char szOutput[160];
4349	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4350	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4351	if (RT_SUCCESS(rc))
4352	{
4353	/* log it */
4354	if (pszPrefix)
4355	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4356	else
4357	Log(("%s", szOutput));
4358	#endif
4359	rc = VINF_SUCCESS;
4360	}
4361	else
4362	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4363
4364	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4365	if (State.fLocked)
4366	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4367
4368	return rc;
4369	}
4370
4371
4372
4373	/**
4374	* API for controlling a few of the CPU features found in CR4.
4375	*
4376	* Currently only X86_CR4_TSD is accepted as input.
4377	*
4378	* @returns VBox status code.
4379	*
4380	* @param pVM The cross context VM structure.
4381	* @param fOr The CR4 OR mask.
4382	* @param fAnd The CR4 AND mask.
4383	*/
4384	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4385	{
4386	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4387	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4388
4389	pVM->cpum.s.CR4.OrMask &= fAnd;
4390	pVM->cpum.s.CR4.OrMask \|= fOr;
4391
4392	return VINF_SUCCESS;
4393	}
4394
4395
4396	/**
4397	* Called when the ring-3 init phase completes.
4398	*
4399	* @returns VBox status code.
4400	* @param pVM The cross context VM structure.
4401	* @param enmWhat Which init phase.
4402	*/
4403	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4404	{
4405	switch (enmWhat)
4406	{
4407	case VMINITCOMPLETED_RING3:
4408	{
4409	/*
4410	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4411	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4412	*/
4413	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4414	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4415	{
4416	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4417
4418	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4419	if (fSupportsLongMode)
4420	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4421	}
4422
4423	/* Register statistic counters for MSRs. */
4424	cpumR3MsrRegStats(pVM);
4425
4426	/* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
4427	CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
4428	cpumR3CpuIdRing3InitDone(pVM);
4429
4430	/* Create VMX-preemption timer for nested guests if required. Must be
4431	done here as CPUM is initialized before TM. */
4432	if (pVM->cpum.s.GuestFeatures.fVmx)
4433	{
4434	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4435	{
4436	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4437	char szName[32];
4438	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4439	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4440	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4441	AssertLogRelRCReturn(rc, rc);
4442	}
4443	}
4444	break;
4445	}
4446
4447	default:
4448	break;
4449	}
4450	return VINF_SUCCESS;
4451	}
4452
4453
4454	/**
4455	* Called when the ring-0 init phases completed.
4456	*
4457	* @param pVM The cross context VM structure.
4458	*/
4459	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4460	{
4461	/*
4462	* Enable log buffering as we're going to log a lot of lines.
4463	*/
4464	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4465
4466	/*
4467	* Log the cpuid.
4468	*/
4469	RTCPUSET OnlineSet;
4470	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4471	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4472	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4473	RTCPUID cCores = RTMpGetCoreCount();
4474	if (cCores)
4475	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4476	LogRel(("*********************** CPUID dump **********************\n"));
4477	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4478	LogRel(("\n"));
4479	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4480	LogRel(("****************** End of CPUID dump ********************\n"));
4481
4482	/*
4483	* Log VT-x extended features.
4484	*
4485	* SVM features are currently all covered under CPUID so there is nothing
4486	* to do here for SVM.
4487	*/
4488	if (pVM->cpum.s.HostFeatures.fVmx)
4489	{
4490	LogRel(("********************* VT-x features *********************\n"));
4491	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4492	LogRel(("\n"));
4493	LogRel(("***************** End of VT-x features ******************\n"));
4494	}
4495
4496	/*
4497	* Restore the log buffering state to what it was previously.
4498	*/
4499	RTLogRelSetBuffering(fOldBuffered);
4500	}
4501
4502
4503	/**
4504	* Marks the guest debug state as active.
4505	*
4506	* @returns nothing.
4507	* @param pVCpu The cross context virtual CPU structure.
4508	*
4509	* @note This is used solely by NEM (hence the name) to set the correct flags here
4510	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4511	* The specific NEM backends have to make sure to load the correct values.
4512	*/
4513	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4514	{
4515	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4516	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4517	}
4518
4519
4520	/**
4521	* Marks the hyper debug state as active.
4522	*
4523	* @returns nothing.
4524	* @param pVCpu The cross context virtual CPU structure.
4525	*
4526	* @note This is used solely by NEM (hence the name) to set the correct flags here
4527	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4528	* The specific NEM backends have to make sure to load the correct values.
4529	*/
4530	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4531	{
4532	/*
4533	* Make sure the hypervisor values are up to date.
4534	*/
4535	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4536
4537	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4538	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4539	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 96962

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