CPUM.cpp@ 101932

Last change on this file since 101932 was 101932, checked in by vboxsync, 13 months ago
VMM/CPUM: Nested VMX: Updated cpumR3AreVmxCpuFeaturesCompatible() for newly added VMX features fields.
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1	/* $Id: CPUM.cpp 101932 2023-11-07 11:36:26Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
31	* also responsible for lazy FPU handling and some of the context loading
32	* in raw mode.
33	*
34	* There are three CPU contexts, the most important one is the guest one (GC).
35	* When running in raw-mode (RC) there is a special hyper context for the VMM
36	* part that floats around inside the guest address space. When running in
37	* raw-mode, CPUM also maintains a host context for saving and restoring
38	* registers across world switches. This latter is done in cooperation with the
39	* world switcher (@see pg_vmm).
40	*
41	* @see grp_cpum
42	*
43	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44	*
45	* TODO: proper write up, currently just some notes.
46	*
47	* The ring-0 FPU handling per OS:
48	*
49	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
50	* convention (Visual C++ doesn't seem to have a way to disable
51	* generating such code either), so CR0.TS/EM are always zero from what I
52	* can tell. We are also forced to always load/save the guest XMM0-XMM15
53	* registers when entering/leaving guest context. Interrupt handlers
54	* using FPU/SSE will offically have call save and restore functions
55	* exported by the kernel, if the really really have to use the state.
56	*
57	* - 32-bit windows does lazy FPU handling, I think, probably including
58	* lazying saving. The Windows Internals book states that it's a bad
59	* idea to use the FPU in kernel space. However, it looks like it will
60	* restore the FPU state of the current thread in case of a kernel \#NM.
61	* Interrupt handlers should be same as for 64-bit.
62	*
63	* - Darwin allows taking \#NM in kernel space, restoring current thread's
64	* state if I read the code correctly. It saves the FPU state of the
65	* outgoing thread, and uses CR0.TS to lazily load the state of the
66	* incoming one. No idea yet how the FPU is treated by interrupt
67	* handlers, i.e. whether they are allowed to disable the state or
68	* something.
69	*
70	* - Linux also allows \#NM in kernel space (don't know since when), and
71	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72	* loads the incoming unless configured to agressivly load it. Interrupt
73	* handlers can ask whether they're allowed to use the FPU, and may
74	* freely trash the state if Linux thinks it has saved the thread's state
75	* already. This is a problem.
76	*
77	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78	* context. When switching threads, the kernel will save the state of
79	* the outgoing thread and lazy load the incoming one using CR0.TS.
80	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
81	* to do stuff, HAT are among the users. The routines there will
82	* manually clear CR0.TS and save the XMM registers they use only if
83	* CR0.TS was zero upon entry. They will skip it when not, because as
84	* mentioned above, the FPU state is saved when switching away from a
85	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86	* preserve. This is a problem if we restore CR0.TS to 1 after loading
87	* the guest state.
88	*
89	* - FreeBSD - no idea yet.
90	*
91	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93	* FPU states.
94	*
95	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96	* saving and restoring the host and guest states. The motivation for this
97	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98	*
99	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100	* state and only restore it once we've restore the host FPU state. This has the
101	* accidental side effect of triggering Solaris to preserve XMM registers in
102	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104	*
105	*
106	* @section sec_cpum_logging Logging Level Assignments.
107	*
108	* Following log level assignments:
109	* - Log6 is used for FPU state management.
110	* - Log7 is used for FPU state actualization.
111	*
112	*/
113
114
115	/*********************************************************************************************************************************
116	* Header Files *
117	*********************************************************************************************************************************/
118	#define LOG_GROUP LOG_GROUP_CPUM
119	#define CPUM_WITH_NONCONST_HOST_FEATURES
120	#include <VBox/vmm/cpum.h>
121	#include <VBox/vmm/cpumdis.h>
122	#include <VBox/vmm/cpumctx-v1_6.h>
123	#include <VBox/vmm/pgm.h>
124	#include <VBox/vmm/apic.h>
125	#include <VBox/vmm/mm.h>
126	#include <VBox/vmm/em.h>
127	#include <VBox/vmm/iem.h>
128	#include <VBox/vmm/selm.h>
129	#include <VBox/vmm/dbgf.h>
130	#include <VBox/vmm/hm.h>
131	#include <VBox/vmm/hmvmxinline.h>
132	#include <VBox/vmm/ssm.h>
133	#include "CPUMInternal.h"
134	#include <VBox/vmm/vm.h>
135
136	#include <VBox/param.h>
137	#include <VBox/dis.h>
138	#include <VBox/err.h>
139	#include <VBox/log.h>
140	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
141	# include <iprt/asm-amd64-x86.h>
142	#endif
143	#include <iprt/assert.h>
144	#include <iprt/cpuset.h>
145	#include <iprt/mem.h>
146	#include <iprt/mp.h>
147	#include <iprt/rand.h>
148	#include <iprt/string.h>
149
150
151	/*********************************************************************************************************************************
152	* Defined Constants And Macros *
153	*********************************************************************************************************************************/
154	/**
155	* This was used in the saved state up to the early life of version 14.
156	*
157	* It indicates that we may have some out-of-sync hidden segement registers.
158	* It is only relevant for raw-mode.
159	*/
160	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
161
162
163	/** For saved state only: Block injection of non-maskable interrupts to the guest.
164	* @note This flag was moved to CPUMCTX::eflags.uBoth in v7.0.4. */
165	#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
166
167
168	/*********************************************************************************************************************************
169	* Structures and Typedefs *
170	*********************************************************************************************************************************/
171
172	/**
173	* What kind of cpu info dump to perform.
174	*/
175	typedef enum CPUMDUMPTYPE
176	{
177	CPUMDUMPTYPE_TERSE,
178	CPUMDUMPTYPE_DEFAULT,
179	CPUMDUMPTYPE_VERBOSE
180	} CPUMDUMPTYPE;
181	/** Pointer to a cpu info dump type. */
182	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
183
184
185	/*********************************************************************************************************************************
186	* Internal Functions *
187	*********************************************************************************************************************************/
188	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
189	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
190	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
191	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
192	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
193	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
194	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
195	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
196	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
197	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
198	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
199
200
201	/*********************************************************************************************************************************
202	* Global Variables *
203	*********************************************************************************************************************************/
204	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
205	/** Host CPU features. */
206	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
207	#endif
208
209	/** Saved state field descriptors for CPUMCTX. */
210	static const SSMFIELD g_aCpumCtxFields[] =
211	{
212	SSMFIELD_ENTRY( CPUMCTX, rdi),
213	SSMFIELD_ENTRY( CPUMCTX, rsi),
214	SSMFIELD_ENTRY( CPUMCTX, rbp),
215	SSMFIELD_ENTRY( CPUMCTX, rax),
216	SSMFIELD_ENTRY( CPUMCTX, rbx),
217	SSMFIELD_ENTRY( CPUMCTX, rdx),
218	SSMFIELD_ENTRY( CPUMCTX, rcx),
219	SSMFIELD_ENTRY( CPUMCTX, rsp),
220	SSMFIELD_ENTRY( CPUMCTX, rflags),
221	SSMFIELD_ENTRY( CPUMCTX, rip),
222	SSMFIELD_ENTRY( CPUMCTX, r8),
223	SSMFIELD_ENTRY( CPUMCTX, r9),
224	SSMFIELD_ENTRY( CPUMCTX, r10),
225	SSMFIELD_ENTRY( CPUMCTX, r11),
226	SSMFIELD_ENTRY( CPUMCTX, r12),
227	SSMFIELD_ENTRY( CPUMCTX, r13),
228	SSMFIELD_ENTRY( CPUMCTX, r14),
229	SSMFIELD_ENTRY( CPUMCTX, r15),
230	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
243	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
244	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
245	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
246	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
247	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
248	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
249	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
250	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
251	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
252	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
253	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
254	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
255	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
256	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
257	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
258	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
259	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
260	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
261	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
262	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
263	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
264	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
265	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
266	SSMFIELD_ENTRY( CPUMCTX, cr0),
267	SSMFIELD_ENTRY( CPUMCTX, cr2),
268	SSMFIELD_ENTRY( CPUMCTX, cr3),
269	SSMFIELD_ENTRY( CPUMCTX, cr4),
270	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
271	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
272	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
273	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
274	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
275	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
276	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
277	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
278	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
279	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
280	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
281	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
282	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
283	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
284	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
285	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
286	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
287	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
288	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
289	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
290	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
291	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
292	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
293	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
294	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
295	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
296	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
297	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
298	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
299	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
300	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
301	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
302	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
303	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
304	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
305	SSMFIELD_ENTRY_TERM()
306	};
307
308	/** Saved state field descriptors for SVM nested hardware-virtualization
309	* Host State. */
310	static const SSMFIELD g_aSvmHwvirtHostState[] =
311	{
312	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
324	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
325	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
326	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
327	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
328	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
329	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
330	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
331	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
332	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
333	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
334	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
335	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
336	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
337	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
338	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
339	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
340	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
341	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
342	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
343	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
344	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
345	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
346	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
347	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
348	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
349	SSMFIELD_ENTRY_TERM()
350	};
351
352	/** Saved state field descriptors for VMX nested hardware-virtualization
353	* VMCS. */
354	static const SSMFIELD g_aVmxHwvirtVmcs[] =
355	{
356	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
357	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
358	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
360	SSMFIELD_ENTRY_VER( VMXVVMCS, u32RestoreProcCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4),
361	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
362
363	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
364
365	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
366	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
367	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
368	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
369	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
370	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
371	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
372	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
373	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
374
375	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
376	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
377
378	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
379	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
380	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
381	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
382	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
383	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
384	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
385
386	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
387	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
388	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
389	SSMFIELD_ENTRY_VER( VMXVVMCS, u16HlatPrefixSize, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
390	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
391
392	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
393	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
394	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
395	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
396	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
397	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
398	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
399	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
400	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
401	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
402	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
403	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
404	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
405	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
406	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
407	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
408	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
409	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
410	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
411
412	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
413	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
414	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
415	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
416	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
417	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
418	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
419	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
420	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
421	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
422	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
423	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
424	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
425	SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
426	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
427	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
428	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
429	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
430	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
431	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
432	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
433	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
434	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
435	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
436	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
437	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
438	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
439	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
440	SSMFIELD_ENTRY_VER( VMXVVMCS, u64PconfigExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
441	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HlatPtr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
442	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ExitCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
443	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
444
445	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
446	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
447	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
448	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
449	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
450	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
451	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
452	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
453	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
454
455	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
456	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
457	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
458	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
459	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
460	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
461	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
462	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
463
464	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
465	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
466
467	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
468	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
469	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
470	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
471	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
472
473	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
474	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
475	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
476	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
477	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
478	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
479	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
480	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
481	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
482	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
483	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
484	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
485	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
486	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
487	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
488	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
489
490	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
491	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
492	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
493	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
494	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
495	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
496	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
497	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
498	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
499	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
500	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
501
502	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
503	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
504	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
505	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
506	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
507	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
508	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
509	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
510	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
511	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
512	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
513	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
514	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
515	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
516	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
517	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
518	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
519	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
520	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
521	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
522	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
523	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
524	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
525	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
526
527	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
532	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
533	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
534	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
535	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
536	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
537	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
538	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
539	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
540
541	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
542	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
543	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
544	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
545	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
546	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
547	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
548	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
549	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
550	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
551	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
552	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
553	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
554	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
555	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
556	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
557	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
558	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
559	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
560	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
561	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
562	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
563	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
564	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
565
566	SSMFIELD_ENTRY_TERM()
567	};
568
569	/** Saved state field descriptors for CPUMCTX. */
570	static const SSMFIELD g_aCpumX87Fields[] =
571	{
572	SSMFIELD_ENTRY( X86FXSTATE, FCW),
573	SSMFIELD_ENTRY( X86FXSTATE, FSW),
574	SSMFIELD_ENTRY( X86FXSTATE, FTW),
575	SSMFIELD_ENTRY( X86FXSTATE, FOP),
576	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
577	SSMFIELD_ENTRY( X86FXSTATE, CS),
578	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
579	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
580	SSMFIELD_ENTRY( X86FXSTATE, DS),
581	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
582	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
583	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
584	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
585	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
586	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
587	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
588	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
589	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
590	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
591	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
592	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
593	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
594	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
595	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
596	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
597	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
598	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
599	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
600	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
601	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
602	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
603	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
604	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
605	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
606	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
607	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
608	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
609	SSMFIELD_ENTRY_TERM()
610	};
611
612	/** Saved state field descriptors for X86XSAVEHDR. */
613	static const SSMFIELD g_aCpumXSaveHdrFields[] =
614	{
615	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
616	SSMFIELD_ENTRY_TERM()
617	};
618
619	/** Saved state field descriptors for X86XSAVEYMMHI. */
620	static const SSMFIELD g_aCpumYmmHiFields[] =
621	{
622	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
623	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
624	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
625	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
626	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
627	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
628	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
629	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
630	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
631	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
632	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
633	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
634	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
635	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
636	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
637	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
638	SSMFIELD_ENTRY_TERM()
639	};
640
641	/** Saved state field descriptors for X86XSAVEBNDREGS. */
642	static const SSMFIELD g_aCpumBndRegsFields[] =
643	{
644	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
645	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
646	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
647	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
648	SSMFIELD_ENTRY_TERM()
649	};
650
651	/** Saved state field descriptors for X86XSAVEBNDCFG. */
652	static const SSMFIELD g_aCpumBndCfgFields[] =
653	{
654	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
655	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
656	SSMFIELD_ENTRY_TERM()
657	};
658
659	#if 0 /** @todo */
660	/** Saved state field descriptors for X86XSAVEOPMASK. */
661	static const SSMFIELD g_aCpumOpmaskFields[] =
662	{
663	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
664	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
665	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
666	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
667	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
668	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
669	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
670	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
671	SSMFIELD_ENTRY_TERM()
672	};
673	#endif
674
675	/** Saved state field descriptors for X86XSAVEZMMHI256. */
676	static const SSMFIELD g_aCpumZmmHi256Fields[] =
677	{
678	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
679	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
680	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
681	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
682	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
683	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
684	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
685	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
686	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
687	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
688	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
689	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
690	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
691	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
692	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
693	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
694	SSMFIELD_ENTRY_TERM()
695	};
696
697	/** Saved state field descriptors for X86XSAVEZMM16HI. */
698	static const SSMFIELD g_aCpumZmm16HiFields[] =
699	{
700	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
701	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
702	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
703	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
704	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
705	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
706	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
707	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
708	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
709	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
710	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
711	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
712	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
713	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
714	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
715	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
716	SSMFIELD_ENTRY_TERM()
717	};
718
719
720
721	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
722	* registeres changed. */
723	static const SSMFIELD g_aCpumX87FieldsMem[] =
724	{
725	SSMFIELD_ENTRY( X86FXSTATE, FCW),
726	SSMFIELD_ENTRY( X86FXSTATE, FSW),
727	SSMFIELD_ENTRY( X86FXSTATE, FTW),
728	SSMFIELD_ENTRY( X86FXSTATE, FOP),
729	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
730	SSMFIELD_ENTRY( X86FXSTATE, CS),
731	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
732	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
733	SSMFIELD_ENTRY( X86FXSTATE, DS),
734	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
735	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
736	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
737	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
738	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
739	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
740	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
741	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
742	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
743	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
744	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
745	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
746	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
747	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
748	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
749	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
750	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
751	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
752	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
753	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
754	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
755	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
756	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
757	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
758	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
759	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
760	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
761	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
762	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
763	};
764
765	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
766	* registeres changed. */
767	static const SSMFIELD g_aCpumCtxFieldsMem[] =
768	{
769	SSMFIELD_ENTRY( CPUMCTX, rdi),
770	SSMFIELD_ENTRY( CPUMCTX, rsi),
771	SSMFIELD_ENTRY( CPUMCTX, rbp),
772	SSMFIELD_ENTRY( CPUMCTX, rax),
773	SSMFIELD_ENTRY( CPUMCTX, rbx),
774	SSMFIELD_ENTRY( CPUMCTX, rdx),
775	SSMFIELD_ENTRY( CPUMCTX, rcx),
776	SSMFIELD_ENTRY( CPUMCTX, rsp),
777	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
778	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
779	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
780	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
781	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
782	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
783	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
784	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
785	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
786	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
787	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
788	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
789	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
790	SSMFIELD_ENTRY( CPUMCTX, rflags),
791	SSMFIELD_ENTRY( CPUMCTX, rip),
792	SSMFIELD_ENTRY( CPUMCTX, r8),
793	SSMFIELD_ENTRY( CPUMCTX, r9),
794	SSMFIELD_ENTRY( CPUMCTX, r10),
795	SSMFIELD_ENTRY( CPUMCTX, r11),
796	SSMFIELD_ENTRY( CPUMCTX, r12),
797	SSMFIELD_ENTRY( CPUMCTX, r13),
798	SSMFIELD_ENTRY( CPUMCTX, r14),
799	SSMFIELD_ENTRY( CPUMCTX, r15),
800	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
801	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
802	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
803	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
804	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
805	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
806	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
807	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
808	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
809	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
810	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
811	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
812	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
813	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
814	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
815	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
816	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
817	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
818	SSMFIELD_ENTRY( CPUMCTX, cr0),
819	SSMFIELD_ENTRY( CPUMCTX, cr2),
820	SSMFIELD_ENTRY( CPUMCTX, cr3),
821	SSMFIELD_ENTRY( CPUMCTX, cr4),
822	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
823	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
824	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
825	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
826	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
827	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
828	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
829	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
830	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
831	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
832	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
833	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
834	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
835	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
836	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
837	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
838	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
839	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
840	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
841	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
842	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
843	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
844	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
845	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
846	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
847	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
848	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
849	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
850	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
851	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
852	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
853	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
854	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
855	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
856	SSMFIELD_ENTRY_TERM()
857	};
858
859	/** Saved state field descriptors for CPUMCTX_VER1_6. */
860	static const SSMFIELD g_aCpumX87FieldsV16[] =
861	{
862	SSMFIELD_ENTRY( X86FXSTATE, FCW),
863	SSMFIELD_ENTRY( X86FXSTATE, FSW),
864	SSMFIELD_ENTRY( X86FXSTATE, FTW),
865	SSMFIELD_ENTRY( X86FXSTATE, FOP),
866	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
867	SSMFIELD_ENTRY( X86FXSTATE, CS),
868	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
869	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
870	SSMFIELD_ENTRY( X86FXSTATE, DS),
871	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
872	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
873	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
874	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
875	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
876	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
877	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
878	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
879	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
880	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
881	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
882	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
883	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
884	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
885	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
886	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
887	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
888	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
889	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
890	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
891	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
892	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
893	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
894	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
895	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
896	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
897	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
898	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
899	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
900	SSMFIELD_ENTRY_TERM()
901	};
902
903	/** Saved state field descriptors for CPUMCTX_VER1_6. */
904	static const SSMFIELD g_aCpumCtxFieldsV16[] =
905	{
906	SSMFIELD_ENTRY( CPUMCTX, rdi),
907	SSMFIELD_ENTRY( CPUMCTX, rsi),
908	SSMFIELD_ENTRY( CPUMCTX, rbp),
909	SSMFIELD_ENTRY( CPUMCTX, rax),
910	SSMFIELD_ENTRY( CPUMCTX, rbx),
911	SSMFIELD_ENTRY( CPUMCTX, rdx),
912	SSMFIELD_ENTRY( CPUMCTX, rcx),
913	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
914	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
915	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
916	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
917	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
918	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
919	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
920	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
921	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
922	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
923	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
924	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
925	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
926	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
927	SSMFIELD_ENTRY( CPUMCTX, rflags),
928	SSMFIELD_ENTRY( CPUMCTX, rip),
929	SSMFIELD_ENTRY( CPUMCTX, r8),
930	SSMFIELD_ENTRY( CPUMCTX, r9),
931	SSMFIELD_ENTRY( CPUMCTX, r10),
932	SSMFIELD_ENTRY( CPUMCTX, r11),
933	SSMFIELD_ENTRY( CPUMCTX, r12),
934	SSMFIELD_ENTRY( CPUMCTX, r13),
935	SSMFIELD_ENTRY( CPUMCTX, r14),
936	SSMFIELD_ENTRY( CPUMCTX, r15),
937	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
938	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
939	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
940	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
941	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
942	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
943	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
944	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
945	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
946	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
947	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
948	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
949	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
950	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
951	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
952	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
953	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
954	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
955	SSMFIELD_ENTRY( CPUMCTX, cr0),
956	SSMFIELD_ENTRY( CPUMCTX, cr2),
957	SSMFIELD_ENTRY( CPUMCTX, cr3),
958	SSMFIELD_ENTRY( CPUMCTX, cr4),
959	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
960	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
961	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
962	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
963	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
964	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
965	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
966	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
967	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
968	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
969	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
970	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
971	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
972	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
973	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
974	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
975	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
976	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
977	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
978	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
979	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
980	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
981	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
982	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
983	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
984	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
985	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
986	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
987	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
988	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
989	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
990	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
991	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
992	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
993	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
994	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
995	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
996	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
997	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
998	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
999	SSMFIELD_ENTRY_TERM()
1000	};
1001
1002
1003	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1004	/**
1005	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
1006	*
1007	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
1008	* (last instruction pointer, last data pointer, last opcode) except when the ES
1009	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
1010	* clear these registers there is potential, local FPU leakage from a process
1011	* using the FPU to another.
1012	*
1013	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
1014	*
1015	* @param pVM The cross context VM structure.
1016	*/
1017	static void cpumR3CheckLeakyFpu(PVM pVM)
1018	{
1019	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1020	uint32_t const u32Family = u32CpuVersion >> 8;
1021	if ( u32Family >= 6 /* K7 and higher */
1022	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
1023	{
1024	uint32_t cExt = ASMCpuId_EAX(0x80000000);
1025	if (RTX86IsValidExtRange(cExt))
1026	{
1027	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1028	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1029	{
1030	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1031	{
1032	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1033	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1034	}
1035	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1036	}
1037	}
1038	}
1039	}
1040	#endif
1041
1042
1043	/**
1044	* Initialize the SVM hardware virtualization state.
1045	*
1046	* @param pVM The cross context VM structure.
1047	*/
1048	static void cpumR3InitSvmHwVirtState(PVM pVM)
1049	{
1050	LogRel(("CPUM: AMD-V nested-guest init\n"));
1051	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1052	{
1053	PVMCPU pVCpu = pVM->apCpusR3[i];
1054	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1055
1056	/* Initialize that SVM hardware virtualization is available. */
1057	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1058
1059	AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1060	AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1061	AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1062
1063	/* Initialize non-zero values. */
1064	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1065	}
1066	}
1067
1068
1069	/**
1070	* Resets per-VCPU SVM hardware virtualization state.
1071	*
1072	* @param pVCpu The cross context virtual CPU structure.
1073	*/
1074	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1075	{
1076	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1077	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1078
1079	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1080	RT_ZERO(pCtx->hwvirt.svm.HostState);
1081	RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1082	RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1083
1084	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1085	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1086	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1087	pCtx->hwvirt.svm.cPauseFilter = 0;
1088	pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1089	pCtx->hwvirt.svm.fInterceptEvents = false;
1090	}
1091
1092
1093	/**
1094	* Initializes the VMX hardware virtualization state.
1095	*
1096	* @param pVM The cross context VM structure.
1097	*/
1098	static void cpumR3InitVmxHwVirtState(PVM pVM)
1099	{
1100	LogRel(("CPUM: VT-x nested-guest init\n"));
1101	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1102	{
1103	PVMCPU pVCpu = pVM->apCpusR3[i];
1104	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1105
1106	/* Initialize that VMX hardware virtualization is available. */
1107	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1108
1109	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1110	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1111	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1112	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1113	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1114	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1115	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1116	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1117	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1118	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1119	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1120	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1121	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1122	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1123	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1124	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1125	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1126	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1127
1128	/* Initialize non-zero values. */
1129	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1130	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1131	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1132	}
1133	}
1134
1135
1136	/**
1137	* Resets per-VCPU VMX hardware virtualization state.
1138	*
1139	* @param pVCpu The cross context virtual CPU structure.
1140	*/
1141	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1142	{
1143	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1144	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1145
1146	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1147	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1148	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1149	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1150	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1151	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1152	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1153	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1154	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1155
1156	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1157	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1158	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1159	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1160	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1161	/* Don't reset diagnostics here. */
1162
1163	pCtx->hwvirt.vmx.fInterceptEvents = false;
1164	pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1165	pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1166	pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1167	pCtx->hwvirt.vmx.uEntryTick = 0;
1168	pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1169	pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1170
1171	/* Stop any VMX-preemption timer. */
1172	CPUMStopGuestVmxPremptTimer(pVCpu);
1173
1174	/* Clear all nested-guest FFs. */
1175	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1176	}
1177
1178
1179	/**
1180	* Displays the host and guest VMX features.
1181	*
1182	* @param pVM The cross context VM structure.
1183	* @param pHlp The info helper functions.
1184	* @param pszArgs "terse", "default" or "verbose".
1185	*/
1186	static DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1187	{
1188	RT_NOREF(pszArgs);
1189	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1190	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1191	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1192	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1193	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1194	{
1195	#define VMXFEATDUMP(a_szDesc, a_Var) \
1196	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1197
1198	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1199	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1200	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1201	/* Basic. */
1202	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1203
1204	/* Pin-based controls. */
1205	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1206	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1207	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1208	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1209	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1210
1211	/* Processor-based controls. */
1212	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1213	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1214	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1215	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1216	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1217	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1218	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1219	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1220	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1221	VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1222	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1223	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1224	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1225	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1226	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1227	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1228	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1229	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1230	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1231	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1232	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1233	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1234
1235	/* Secondary processor-based controls. */
1236	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1237	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1238	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1239	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1240	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1241	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1242	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1243	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1244	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1245	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1246	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1247	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1248	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1249	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1250	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1251	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1252	VMXFEATDUMP("PML - Page-Modification Log ", fVmxPml);
1253	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1254	VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1255	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1256	VMXFEATDUMP("PasidTranslate - PASID translation ", fVmxPasidTranslate);
1257	VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1258	VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1259	VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1260	VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1261	VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1262	VMXFEATDUMP("Pconfig - Enable PCONFIG ", fVmxPconfig);
1263	VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1264	VMXFEATDUMP("BusLockDetect - VMM Bus-Lock detection ", fVmxBusLockDetect);
1265	VMXFEATDUMP("InstrTimeout - Instruction timeout ", fVmxInstrTimeout);
1266
1267	/* Tertiary processor-based controls. */
1268	VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1269	VMXFEATDUMP("HLAT - Hypervisor-managed linear-address translation ", fVmxHlat);
1270	VMXFEATDUMP("EptPagingWrite - EPT paging-write ", fVmxEptPagingWrite);
1271	VMXFEATDUMP("GstPagingVerify - Guest-paging verification ", fVmxGstPagingVerify);
1272	VMXFEATDUMP("IpiVirt - IPI virtualization ", fVmxIpiVirt);
1273	VMXFEATDUMP("VirtSpecCtrl - Virtualize IA32_SPEC_CTRL ", fVmxVirtSpecCtrl);
1274
1275	/* VM-entry controls. */
1276	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1277	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1278	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1279	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1280
1281	/* VM-exit controls. */
1282	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1283	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1284	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1285	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1286	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1287	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1288	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1289	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1290	VMXFEATDUMP("SecondaryExitCtls - Secondary VM-exit controls ", fVmxSecondaryExitCtls);
1291
1292	/* Miscellaneous data. */
1293	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1294	VMXFEATDUMP("IntelPt - Intel Processor Trace in VMX operation ", fVmxPt);
1295	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1296	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1297	#undef VMXFEATDUMP
1298	}
1299	else
1300	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1301	}
1302
1303
1304	/**
1305	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1306	* or NEM) is allowed.
1307	*
1308	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1309	* otherwise.
1310	* @param pVM The cross context VM structure.
1311	*/
1312	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1313	{
1314	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1315	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1316	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1317	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1318	return true;
1319	#else
1320	NOREF(pVM);
1321	#endif
1322	return false;
1323	}
1324
1325
1326	/**
1327	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1328	*
1329	* @param pVM The cross context VM structure.
1330	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1331	* and no hardware-assisted nested-guest execution is
1332	* possible for this VM.
1333	* @param pGuestFeatures The guest features to use (only VMX features are
1334	* accessed).
1335	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1336	*
1337	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1338	*/
1339	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1340	{
1341	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1342
1343	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1344	Assert(pGuestFeatures->fVmx);
1345
1346	/* Basic information. */
1347	uint8_t const fTrueVmxMsrs = 1;
1348	{
1349	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1350	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1351	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1352	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1353	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1354	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1355	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1356	pGuestVmxMsrs->u64Basic = u64Basic;
1357	}
1358
1359	/* Pin-based VM-execution controls. */
1360	{
1361	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1362	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1363	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1364	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1365	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1366	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1367	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1368	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1369	fAllowed0, fAllowed1, fFeatures));
1370	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1371
1372	/* True pin-based VM-execution controls. */
1373	if (fTrueVmxMsrs)
1374	{
1375	/* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1376	pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1377	}
1378	}
1379
1380	/* Processor-based VM-execution controls. */
1381	{
1382	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1383	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1384	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1385	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1386	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1387	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1388	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1389	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1390	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1391	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1392	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1393	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1394	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1395	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1396	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1397	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1398	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1399	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1400	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1401	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1402	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1403	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1404	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1405	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1406	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1407	fAllowed1, fFeatures));
1408	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1409
1410	/* True processor-based VM-execution controls. */
1411	if (fTrueVmxMsrs)
1412	{
1413	/* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1414	uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1415	\| VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1416	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1417	pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1418	}
1419	}
1420
1421	/* Secondary processor-based VM-execution controls. */
1422	if (pGuestFeatures->fVmxSecondaryExecCtls)
1423	{
1424	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1425	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1426	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1427	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1428	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1429	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1430	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1431	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1432	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1433	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1434	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1435	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1436	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1437	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1438	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1439	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1440	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1441	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1442	\| (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1443	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1444	\| (pGuestFeatures->fVmxPasidTranslate << VMX_BF_PROC_CTLS2_PASID_TRANSLATE_SHIFT )
1445	\| (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1446	\| (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1447	\| (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1448	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1449	\| (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1450	\| (pGuestFeatures->fVmxPconfig << VMX_BF_PROC_CTLS2_PCONFIG_SHIFT )
1451	\| (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT )
1452	\| (pGuestFeatures->fVmxBusLockDetect << VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_SHIFT )
1453	\| (pGuestFeatures->fVmxInstrTimeout << VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_SHIFT );
1454	uint32_t const fAllowed0 = 0;
1455	uint32_t const fAllowed1 = fFeatures;
1456	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1457	}
1458
1459	/* Tertiary processor-based VM-execution controls. */
1460	if (pGuestFeatures->fVmxTertiaryExecCtls)
1461	{
1462	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT)
1463	\| (pGuestFeatures->fVmxHlat << VMX_BF_PROC_CTLS3_HLAT_SHIFT)
1464	\| (pGuestFeatures->fVmxEptPagingWrite << VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_SHIFT)
1465	\| (pGuestFeatures->fVmxGstPagingVerify << VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_SHIFT)
1466	\| (pGuestFeatures->fVmxIpiVirt << VMX_BF_PROC_CTLS3_IPI_VIRT_SHIFT)
1467	\| (pGuestFeatures->fVmxVirtSpecCtrl << VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_SHIFT);
1468	}
1469
1470	/* VM-exit controls. */
1471	{
1472	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1473	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1474	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1475	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1476	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1477	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1478	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1479	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT )
1480	\| (pGuestFeatures->fVmxSecondaryExitCtls << VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_SHIFT );
1481	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1482	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1483	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1484	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1485	fAllowed1, fFeatures));
1486	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1487
1488	/* True VM-exit controls. */
1489	if (fTrueVmxMsrs)
1490	{
1491	/* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1492	uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1493	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1494	pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1495	}
1496	}
1497
1498	/* VM-entry controls. */
1499	{
1500	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1501	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1502	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1503	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1504	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1505	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1506	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1507	fAllowed1, fFeatures));
1508	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1509
1510	/* True VM-entry controls. */
1511	if (fTrueVmxMsrs)
1512	{
1513	/* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1514	uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1515	\| VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1516	\| VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1517	\| VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1518	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1519	pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1520	}
1521	}
1522
1523	/* Miscellaneous data. */
1524	{
1525	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1526
1527	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1528	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1529	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1530	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1531	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1532	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1533	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1534	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1535	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1536	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1537	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1538	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1539	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1540	}
1541
1542	/* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1543	pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1544
1545	/* CR0 Fixed-1. */
1546	{
1547	/*
1548	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1549	* This is different from CR4 fixed-1 bits which are reported as per the
1550	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1551	*/
1552	pGuestVmxMsrs->u64Cr0Fixed1 = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1553
1554	/* Make sure the CR0 MB1 bits are not clear. */
1555	Assert((pGuestVmxMsrs->u64Cr0Fixed1 & pGuestVmxMsrs->u64Cr0Fixed0) == pGuestVmxMsrs->u64Cr0Fixed0);
1556	}
1557
1558	/* CR4 Fixed-0. */
1559	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1560
1561	/* CR4 Fixed-1. */
1562	{
1563	pGuestVmxMsrs->u64Cr4Fixed1 = CPUMGetGuestCR4ValidMask(pVM) & pHostVmxMsrs->u64Cr4Fixed1;
1564
1565	/* Make sure the CR4 MB1 bits are not clear. */
1566	Assert((pGuestVmxMsrs->u64Cr4Fixed1 & pGuestVmxMsrs->u64Cr4Fixed0) == pGuestVmxMsrs->u64Cr4Fixed0);
1567
1568	/* Make sure bits that must always be set are set. */
1569	Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_PAE);
1570	Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_VMXE);
1571	}
1572
1573	/* VMCS Enumeration. */
1574	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1575
1576	/* VPID and EPT Capabilities. */
1577	if (pGuestFeatures->fVmxEpt)
1578	{
1579	/*
1580	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1581	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1582	* when INVVPID instruction is supported just to be more compatible with guest
1583	* hypervisors that may make assumptions by only looking at this MSR even though they
1584	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1585	*
1586	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1587	* See Intel spec. 30.3 "VMX Instructions".
1588	*/
1589	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1590	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1591
1592	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1593	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1594	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1595	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1596	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1597	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1598	/** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1599	/* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1600	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1601	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1602	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1603	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1604	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1605	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1606	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1607	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1608	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1609	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1610	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1611	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1612	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1613	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1614	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1615	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1616	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1617	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1618	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1619	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1620	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1621	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1622	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1623	}
1624
1625	/* VM Functions. */
1626	if (pGuestFeatures->fVmxVmFunc)
1627	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1628	}
1629
1630
1631	/**
1632	* Checks whether the given guest CPU VMX features are compatible with the provided
1633	* base features.
1634	*
1635	* @returns @c true if compatible, @c false otherwise.
1636	* @param pVM The cross context VM structure.
1637	* @param pBase The base VMX CPU features.
1638	* @param pGst The guest VMX CPU features.
1639	*
1640	* @remarks Only VMX feature bits are examined.
1641	*/
1642	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1643	{
1644	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1645	return false;
1646
1647	#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1648	#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1649	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1650	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1651	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1652	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1653	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1654	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1655	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1656	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1657	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1658	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1659	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1660	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1661	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1662	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1663	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1664	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1665	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1666	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1667	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1668	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1669	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1670	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1671	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1672	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1673	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1674	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1675	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1676	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1677	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1678	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1679	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1680	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1681	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1682	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1683	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1684	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1685	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1686	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1687	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1688	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1689	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1690	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1691	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1692	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1693	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1694	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1695	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1696	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPasidTranslate , 49) \
1697	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 50) \
1698	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 51) \
1699	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 52) \
1700	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 53) \
1701	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 54) \
1702	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPconfig , 55) \
1703	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 56) \
1704	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxBusLockDetect , 57) \
1705	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInstrTimeout , 58) \
1706	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 59) \
1707	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHlat , 60) \
1708	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptPagingWrite , 61) \
1709	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxGstPagingVerify , 62) \
1710	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIpiVirt , 63))
1711
1712	#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtSpecCtrl , 0) \
1713	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 1) \
1714	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 2) \
1715	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 3) \
1716	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 4) \
1717	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 5) \
1718	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 6) \
1719	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 7) \
1720	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 8) \
1721	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 9) \
1722	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 10) \
1723	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 12) \
1724	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 13) \
1725	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExitCtls , 14) \
1726	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 15) \
1727	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 16) \
1728	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 17) \
1729	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 18))
1730
1731	/* Check first set of feature bits. */
1732	{
1733	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1734	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1735	if ((fBase \| fGst) != fBase)
1736	{
1737	uint64_t const fDiff = fBase ^ fGst;
1738	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1739	fBase, fGst, fDiff));
1740	return false;
1741	}
1742	}
1743
1744	/* Check second set of feature bits. */
1745	{
1746	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1747	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1748	if ((fBase \| fGst) != fBase)
1749	{
1750	uint64_t const fDiff = fBase ^ fGst;
1751	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1752	fBase, fGst, fDiff));
1753	return false;
1754	}
1755	}
1756	#undef CPUM_VMX_FEAT_SHIFT
1757	#undef CPUM_VMX_MAKE_FEATURES_1
1758	#undef CPUM_VMX_MAKE_FEATURES_2
1759
1760	return true;
1761	}
1762
1763
1764	/**
1765	* Initializes VMX guest features and MSRs.
1766	*
1767	* @param pVM The cross context VM structure.
1768	* @param pCpumCfg The CPUM CFGM configuration node.
1769	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1770	* and no hardware-assisted nested-guest execution is
1771	* possible for this VM.
1772	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1773	*/
1774	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1775	{
1776	Assert(pVM);
1777	Assert(pCpumCfg);
1778	Assert(pGuestVmxMsrs);
1779
1780	/*
1781	* Query VMX features from CFGM.
1782	*/
1783	bool fVmxPreemptTimer;
1784	bool fVmxEpt;
1785	bool fVmxUnrestrictedGuest;
1786	{
1787	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
1788	* Whether to expose the VMX-preemption timer feature to the guest (if also
1789	* supported by the host hardware). When disabled will prevent exposing the
1790	* VMX-preemption timer feature to the guest even if the host supports it.
1791	*
1792	* @todo Currently disabled, see @bugref{9180#c108}.
1793	*/
1794	int rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &fVmxPreemptTimer, false);
1795	AssertLogRelRCReturnVoid(rc);
1796
1797	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1798	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
1799	* Whether to expose the EPT feature to the guest. The default is true.
1800	* When disabled will automatically prevent exposing features that rely
1801	* on it. This is dependent upon nested paging being enabled for the VM.
1802	*/
1803	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &fVmxEpt, true);
1804	AssertLogRelRCReturnVoid(rc);
1805
1806	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
1807	* Whether to expose the Unrestricted Guest feature to the guest. The
1808	* default is the same a /CPUM/Nested/VmxEpt. When disabled will
1809	* automatically prevent exposing features that rely on it.
1810	*/
1811	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &fVmxUnrestrictedGuest, fVmxEpt);
1812	AssertLogRelRCReturnVoid(rc);
1813	#else
1814	fVmxEpt = fVmxUnrestrictedGuest = false;
1815	#endif
1816	}
1817
1818	if (fVmxEpt)
1819	{
1820	const char *pszWhy = NULL;
1821	if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1822	pszWhy = "execution engine is neither HM nor IEM";
1823	else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1824	pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1825	else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.fNoExecute)
1826	pszWhy = "NX is not available on the host";
1827	if (pszWhy)
1828	{
1829	LogRel(("CPUM: Warning! EPT not exposed to the guest because %s\n", pszWhy));
1830	fVmxEpt = false;
1831	}
1832	}
1833	else if (fVmxUnrestrictedGuest)
1834	{
1835	LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1836	fVmxUnrestrictedGuest = false;
1837	}
1838
1839	/*
1840	* Initialize the set of VMX features we emulate.
1841	*
1842	* Note! Some bits might be reported as 1 always if they fall under the
1843	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1844	*/
1845	CPUMFEATURES EmuFeat;
1846	RT_ZERO(EmuFeat);
1847	EmuFeat.fVmx = 1;
1848	EmuFeat.fVmxInsOutInfo = 1;
1849	EmuFeat.fVmxExtIntExit = 1;
1850	EmuFeat.fVmxNmiExit = 1;
1851	EmuFeat.fVmxVirtNmi = 1;
1852	EmuFeat.fVmxPreemptTimer = fVmxPreemptTimer;
1853	EmuFeat.fVmxPostedInt = 0;
1854	EmuFeat.fVmxIntWindowExit = 1;
1855	EmuFeat.fVmxTscOffsetting = 1;
1856	EmuFeat.fVmxHltExit = 1;
1857	EmuFeat.fVmxInvlpgExit = 1;
1858	EmuFeat.fVmxMwaitExit = 1;
1859	EmuFeat.fVmxRdpmcExit = 1;
1860	EmuFeat.fVmxRdtscExit = 1;
1861	EmuFeat.fVmxCr3LoadExit = 1;
1862	EmuFeat.fVmxCr3StoreExit = 1;
1863	EmuFeat.fVmxTertiaryExecCtls = 0;
1864	EmuFeat.fVmxCr8LoadExit = 1;
1865	EmuFeat.fVmxCr8StoreExit = 1;
1866	EmuFeat.fVmxUseTprShadow = 1;
1867	EmuFeat.fVmxNmiWindowExit = 1;
1868	EmuFeat.fVmxMovDRxExit = 1;
1869	EmuFeat.fVmxUncondIoExit = 1;
1870	EmuFeat.fVmxUseIoBitmaps = 1;
1871	EmuFeat.fVmxMonitorTrapFlag = 0;
1872	EmuFeat.fVmxUseMsrBitmaps = 1;
1873	EmuFeat.fVmxMonitorExit = 1;
1874	EmuFeat.fVmxPauseExit = 1;
1875	EmuFeat.fVmxSecondaryExecCtls = 1;
1876	EmuFeat.fVmxVirtApicAccess = 1;
1877	EmuFeat.fVmxEpt = fVmxEpt;
1878	EmuFeat.fVmxDescTableExit = 1;
1879	EmuFeat.fVmxRdtscp = 1;
1880	EmuFeat.fVmxVirtX2ApicMode = 0;
1881	EmuFeat.fVmxVpid = 1;
1882	EmuFeat.fVmxWbinvdExit = 1;
1883	EmuFeat.fVmxUnrestrictedGuest = fVmxUnrestrictedGuest;
1884	EmuFeat.fVmxApicRegVirt = 0;
1885	EmuFeat.fVmxVirtIntDelivery = 0;
1886	EmuFeat.fVmxPauseLoopExit = 1;
1887	EmuFeat.fVmxRdrandExit = 0;
1888	EmuFeat.fVmxInvpcid = 1;
1889	EmuFeat.fVmxVmFunc = 0;
1890	EmuFeat.fVmxVmcsShadowing = 0;
1891	EmuFeat.fVmxRdseedExit = 0;
1892	EmuFeat.fVmxPml = 0;
1893	EmuFeat.fVmxEptXcptVe = 0;
1894	EmuFeat.fVmxConcealVmxFromPt = 0;
1895	EmuFeat.fVmxXsavesXrstors = 0;
1896	EmuFeat.fVmxPasidTranslate = 0;
1897	EmuFeat.fVmxModeBasedExecuteEpt = 0;
1898	EmuFeat.fVmxSppEpt = 0;
1899	EmuFeat.fVmxPtEpt = 0;
1900	EmuFeat.fVmxUseTscScaling = 0;
1901	EmuFeat.fVmxUserWaitPause = 0;
1902	EmuFeat.fVmxPconfig = 0;
1903	EmuFeat.fVmxEnclvExit = 0;
1904	EmuFeat.fVmxBusLockDetect = 0;
1905	EmuFeat.fVmxInstrTimeout = 0;
1906	EmuFeat.fVmxLoadIwKeyExit = 0;
1907	EmuFeat.fVmxHlat = 0;
1908	EmuFeat.fVmxEptPagingWrite = 0;
1909	EmuFeat.fVmxGstPagingVerify = 0;
1910	EmuFeat.fVmxIpiVirt = 0;
1911	EmuFeat.fVmxVirtSpecCtrl = 0;
1912	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1913	EmuFeat.fVmxIa32eModeGuest = 1;
1914	EmuFeat.fVmxEntryLoadEferMsr = 1;
1915	EmuFeat.fVmxEntryLoadPatMsr = 1;
1916	EmuFeat.fVmxExitSaveDebugCtls = 1;
1917	EmuFeat.fVmxHostAddrSpaceSize = 1;
1918	EmuFeat.fVmxExitAckExtInt = 1;
1919	EmuFeat.fVmxExitSavePatMsr = 1;
1920	EmuFeat.fVmxExitLoadPatMsr = 1;
1921	EmuFeat.fVmxExitSaveEferMsr = 1;
1922	EmuFeat.fVmxExitLoadEferMsr = 1;
1923	EmuFeat.fVmxSavePreemptTimer = 0 & fVmxPreemptTimer; /* Cannot be enabled if VMX-preemption timer is disabled. */
1924	EmuFeat.fVmxSecondaryExitCtls = 0;
1925	EmuFeat.fVmxExitSaveEferLma = 1 \| fVmxUnrestrictedGuest; /* Cannot be disabled if unrestricted guest is enabled. */
1926	EmuFeat.fVmxPt = 0;
1927	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1928	EmuFeat.fVmxEntryInjectSoftInt = 1;
1929
1930	/*
1931	* Merge guest features.
1932	*
1933	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1934	* by the hardware, hence we merge our emulated features with the host features below.
1935	*/
1936	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1937	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1938	Assert(pBaseFeat->fVmx);
1939	#define CPUMVMX_SET_GST_FEAT(a_Feat) \
1940	do { \
1941	pGuestFeat->a_Feat = (pBaseFeat->a_Feat & EmuFeat.a_Feat); \
1942	} while (0)
1943
1944	CPUMVMX_SET_GST_FEAT(fVmxInsOutInfo);
1945	CPUMVMX_SET_GST_FEAT(fVmxExtIntExit);
1946	CPUMVMX_SET_GST_FEAT(fVmxNmiExit);
1947	CPUMVMX_SET_GST_FEAT(fVmxVirtNmi);
1948	CPUMVMX_SET_GST_FEAT(fVmxPreemptTimer);
1949	CPUMVMX_SET_GST_FEAT(fVmxPostedInt);
1950	CPUMVMX_SET_GST_FEAT(fVmxIntWindowExit);
1951	CPUMVMX_SET_GST_FEAT(fVmxTscOffsetting);
1952	CPUMVMX_SET_GST_FEAT(fVmxHltExit);
1953	CPUMVMX_SET_GST_FEAT(fVmxInvlpgExit);
1954	CPUMVMX_SET_GST_FEAT(fVmxMwaitExit);
1955	CPUMVMX_SET_GST_FEAT(fVmxRdpmcExit);
1956	CPUMVMX_SET_GST_FEAT(fVmxRdtscExit);
1957	CPUMVMX_SET_GST_FEAT(fVmxCr3LoadExit);
1958	CPUMVMX_SET_GST_FEAT(fVmxCr3StoreExit);
1959	CPUMVMX_SET_GST_FEAT(fVmxTertiaryExecCtls);
1960	CPUMVMX_SET_GST_FEAT(fVmxCr8LoadExit);
1961	CPUMVMX_SET_GST_FEAT(fVmxCr8StoreExit);
1962	CPUMVMX_SET_GST_FEAT(fVmxUseTprShadow);
1963	CPUMVMX_SET_GST_FEAT(fVmxNmiWindowExit);
1964	CPUMVMX_SET_GST_FEAT(fVmxMovDRxExit);
1965	CPUMVMX_SET_GST_FEAT(fVmxUncondIoExit);
1966	CPUMVMX_SET_GST_FEAT(fVmxUseIoBitmaps);
1967	CPUMVMX_SET_GST_FEAT(fVmxMonitorTrapFlag);
1968	CPUMVMX_SET_GST_FEAT(fVmxUseMsrBitmaps);
1969	CPUMVMX_SET_GST_FEAT(fVmxMonitorExit);
1970	CPUMVMX_SET_GST_FEAT(fVmxPauseExit);
1971	CPUMVMX_SET_GST_FEAT(fVmxSecondaryExecCtls);
1972	CPUMVMX_SET_GST_FEAT(fVmxVirtApicAccess);
1973	CPUMVMX_SET_GST_FEAT(fVmxEpt);
1974	CPUMVMX_SET_GST_FEAT(fVmxDescTableExit);
1975	CPUMVMX_SET_GST_FEAT(fVmxRdtscp);
1976	CPUMVMX_SET_GST_FEAT(fVmxVirtX2ApicMode);
1977	CPUMVMX_SET_GST_FEAT(fVmxVpid);
1978	CPUMVMX_SET_GST_FEAT(fVmxWbinvdExit);
1979	CPUMVMX_SET_GST_FEAT(fVmxUnrestrictedGuest);
1980	CPUMVMX_SET_GST_FEAT(fVmxApicRegVirt);
1981	CPUMVMX_SET_GST_FEAT(fVmxVirtIntDelivery);
1982	CPUMVMX_SET_GST_FEAT(fVmxPauseLoopExit);
1983	CPUMVMX_SET_GST_FEAT(fVmxRdrandExit);
1984	CPUMVMX_SET_GST_FEAT(fVmxInvpcid);
1985	CPUMVMX_SET_GST_FEAT(fVmxVmFunc);
1986	CPUMVMX_SET_GST_FEAT(fVmxVmcsShadowing);
1987	CPUMVMX_SET_GST_FEAT(fVmxRdseedExit);
1988	CPUMVMX_SET_GST_FEAT(fVmxPml);
1989	CPUMVMX_SET_GST_FEAT(fVmxEptXcptVe);
1990	CPUMVMX_SET_GST_FEAT(fVmxConcealVmxFromPt);
1991	CPUMVMX_SET_GST_FEAT(fVmxXsavesXrstors);
1992	CPUMVMX_SET_GST_FEAT(fVmxPasidTranslate);
1993	CPUMVMX_SET_GST_FEAT(fVmxModeBasedExecuteEpt);
1994	CPUMVMX_SET_GST_FEAT(fVmxSppEpt);
1995	CPUMVMX_SET_GST_FEAT(fVmxPtEpt);
1996	CPUMVMX_SET_GST_FEAT(fVmxUseTscScaling);
1997	CPUMVMX_SET_GST_FEAT(fVmxUserWaitPause);
1998	CPUMVMX_SET_GST_FEAT(fVmxPconfig);
1999	CPUMVMX_SET_GST_FEAT(fVmxEnclvExit);
2000	CPUMVMX_SET_GST_FEAT(fVmxBusLockDetect);
2001	CPUMVMX_SET_GST_FEAT(fVmxInstrTimeout);
2002	CPUMVMX_SET_GST_FEAT(fVmxLoadIwKeyExit);
2003	CPUMVMX_SET_GST_FEAT(fVmxHlat);
2004	CPUMVMX_SET_GST_FEAT(fVmxEptPagingWrite);
2005	CPUMVMX_SET_GST_FEAT(fVmxGstPagingVerify);
2006	CPUMVMX_SET_GST_FEAT(fVmxIpiVirt);
2007	CPUMVMX_SET_GST_FEAT(fVmxVirtSpecCtrl);
2008	CPUMVMX_SET_GST_FEAT(fVmxEntryLoadDebugCtls);
2009	CPUMVMX_SET_GST_FEAT(fVmxIa32eModeGuest);
2010	CPUMVMX_SET_GST_FEAT(fVmxEntryLoadEferMsr);
2011	CPUMVMX_SET_GST_FEAT(fVmxEntryLoadPatMsr);
2012	CPUMVMX_SET_GST_FEAT(fVmxExitSaveDebugCtls);
2013	CPUMVMX_SET_GST_FEAT(fVmxHostAddrSpaceSize);
2014	CPUMVMX_SET_GST_FEAT(fVmxExitAckExtInt);
2015	CPUMVMX_SET_GST_FEAT(fVmxExitSavePatMsr);
2016	CPUMVMX_SET_GST_FEAT(fVmxExitLoadPatMsr);
2017	CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferMsr);
2018	CPUMVMX_SET_GST_FEAT(fVmxExitLoadEferMsr);
2019	CPUMVMX_SET_GST_FEAT(fVmxSavePreemptTimer);
2020	CPUMVMX_SET_GST_FEAT(fVmxSecondaryExitCtls);
2021	CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferLma);
2022	CPUMVMX_SET_GST_FEAT(fVmxPt);
2023	CPUMVMX_SET_GST_FEAT(fVmxVmwriteAll);
2024	CPUMVMX_SET_GST_FEAT(fVmxEntryInjectSoftInt);
2025
2026	#undef CPUMVMX_SET_GST_FEAT
2027
2028	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2029	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
2030	if ( pGuestFeat->fVmxPreemptTimer
2031	&& HMIsSubjectToVmxPreemptTimerErratum())
2032	{
2033	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum\n"));
2034	pGuestFeat->fVmxPreemptTimer = 0;
2035	pGuestFeat->fVmxSavePreemptTimer = 0;
2036	}
2037	#endif
2038
2039	/* Sanity checking. */
2040	if (!pGuestFeat->fVmxSecondaryExecCtls)
2041	{
2042	Assert(!pGuestFeat->fVmxVirtApicAccess);
2043	Assert(!pGuestFeat->fVmxEpt);
2044	Assert(!pGuestFeat->fVmxDescTableExit);
2045	Assert(!pGuestFeat->fVmxRdtscp);
2046	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
2047	Assert(!pGuestFeat->fVmxVpid);
2048	Assert(!pGuestFeat->fVmxWbinvdExit);
2049	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
2050	Assert(!pGuestFeat->fVmxApicRegVirt);
2051	Assert(!pGuestFeat->fVmxVirtIntDelivery);
2052	Assert(!pGuestFeat->fVmxPauseLoopExit);
2053	Assert(!pGuestFeat->fVmxRdrandExit);
2054	Assert(!pGuestFeat->fVmxInvpcid);
2055	Assert(!pGuestFeat->fVmxVmFunc);
2056	Assert(!pGuestFeat->fVmxVmcsShadowing);
2057	Assert(!pGuestFeat->fVmxRdseedExit);
2058	Assert(!pGuestFeat->fVmxPml);
2059	Assert(!pGuestFeat->fVmxEptXcptVe);
2060	Assert(!pGuestFeat->fVmxConcealVmxFromPt);
2061	Assert(!pGuestFeat->fVmxXsavesXrstors);
2062	Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
2063	Assert(!pGuestFeat->fVmxSppEpt);
2064	Assert(!pGuestFeat->fVmxPtEpt);
2065	Assert(!pGuestFeat->fVmxUseTscScaling);
2066	Assert(!pGuestFeat->fVmxUserWaitPause);
2067	Assert(!pGuestFeat->fVmxEnclvExit);
2068	}
2069	else if (pGuestFeat->fVmxUnrestrictedGuest)
2070	{
2071	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2072	Assert(pGuestFeat->fVmxExitSaveEferLma);
2073	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
2074	Assert(pGuestFeat->fVmxEpt);
2075	}
2076
2077	if (!pGuestFeat->fVmxTertiaryExecCtls)
2078	{
2079	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
2080	Assert(!pGuestFeat->fVmxHlat);
2081	Assert(!pGuestFeat->fVmxEptPagingWrite);
2082	Assert(!pGuestFeat->fVmxGstPagingVerify);
2083	Assert(!pGuestFeat->fVmxIpiVirt);
2084	Assert(!pGuestFeat->fVmxVirtSpecCtrl);
2085	}
2086
2087	/*
2088	* Finally initialize the VMX guest MSRs.
2089	*/
2090	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2091	}
2092
2093
2094	/**
2095	* Gets the host hardware-virtualization MSRs.
2096	*
2097	* @returns VBox status code.
2098	* @param pMsrs Where to store the MSRs.
2099	*/
2100	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2101	{
2102	Assert(pMsrs);
2103
2104	uint32_t fCaps = 0;
2105	int rc = SUPR3QueryVTCaps(&fCaps);
2106	if (RT_SUCCESS(rc))
2107	{
2108	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2109	{
2110	SUPHWVIRTMSRS HwvirtMsrs;
2111	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2112	if (RT_SUCCESS(rc))
2113	{
2114	if (fCaps & SUPVTCAPS_VT_X)
2115	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2116	else
2117	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2118	return VINF_SUCCESS;
2119	}
2120
2121	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2122	return rc;
2123	}
2124
2125	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2126	return VERR_INTERNAL_ERROR_5;
2127	}
2128
2129	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2130	return VINF_SUCCESS;
2131	}
2132
2133
2134	/**
2135	* @callback_method_impl{FNTMTIMERINT,
2136	* Callback that fires when the nested VMX-preemption timer expired.}
2137	*/
2138	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2139	{
2140	RT_NOREF(pVM, hTimer);
2141	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2142	AssertPtr(pVCpu);
2143	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2144	}
2145
2146
2147	/**
2148	* Initializes the CPUM.
2149	*
2150	* @returns VBox status code.
2151	* @param pVM The cross context VM structure.
2152	*/
2153	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2154	{
2155	LogFlow(("CPUMR3Init\n"));
2156
2157	/*
2158	* Assert alignment, sizes and tables.
2159	*/
2160	AssertCompileMemberAlignment(VM, cpum.s, 32);
2161	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2162	AssertCompileSizeAlignment(CPUMCTX, 64);
2163	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2164	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2165	AssertCompileMemberAlignment(VM, cpum, 64);
2166	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2167	#ifdef VBOX_STRICT
2168	int rc2 = cpumR3MsrStrictInitChecks();
2169	AssertRCReturn(rc2, rc2);
2170	#endif
2171
2172	/*
2173	* Gather info about the host CPU.
2174	*/
2175	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2176	if (!ASMHasCpuId())
2177	{
2178	LogRel(("The CPU doesn't support CPUID!\n"));
2179	return VERR_UNSUPPORTED_CPU;
2180	}
2181
2182	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2183	#endif
2184
2185	CPUMMSRS HostMsrs;
2186	RT_ZERO(HostMsrs);
2187	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2188	AssertLogRelRCReturn(rc, rc);
2189
2190	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2191	/* Use the host features detected by CPUMR0ModuleInit if available. */
2192	if (pVM->cpum.s.HostFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2193	g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures;
2194	else
2195	{
2196	PCPUMCPUIDLEAF paLeaves;
2197	uint32_t cLeaves;
2198	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2199	AssertLogRelRCReturn(rc, rc);
2200
2201	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2202	RTMemFree(paLeaves);
2203	AssertLogRelRCReturn(rc, rc);
2204	}
2205	pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2206	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2207	#endif
2208
2209	/*
2210	* Check that the CPU supports the minimum features we require.
2211	*/
2212	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2213	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2214	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2215	if (!pVM->cpum.s.HostFeatures.fMmx)
2216	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2217	if (!pVM->cpum.s.HostFeatures.fTsc)
2218	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2219	#endif
2220
2221	/*
2222	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2223	*/
2224	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2225	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2226
2227	/*
2228	* Figure out which XSAVE/XRSTOR features are available on the host.
2229	*/
2230	uint64_t fXcr0Host = 0;
2231	uint64_t fXStateHostMask = 0;
2232	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2233	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2234	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2235	{
2236	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2237	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2238	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2239	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2240	}
2241	#endif
2242	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2243	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2244	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2245
2246	/*
2247	* Initialize the host XSAVE/XRSTOR mask.
2248	*/
2249	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2250	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2251	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2252	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2253	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2254	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2255	, VERR_CPUM_IPE_2);
2256	#endif
2257
2258	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2259	{
2260	PVMCPU pVCpu = pVM->apCpusR3[i];
2261
2262	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2263	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2264	}
2265
2266	/*
2267	* Register saved state data item.
2268	*/
2269	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2270	NULL, cpumR3LiveExec, NULL,
2271	NULL, cpumR3SaveExec, NULL,
2272	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2273	if (RT_FAILURE(rc))
2274	return rc;
2275
2276	/*
2277	* Register info handlers and registers with the debugger facility.
2278	*/
2279	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2280	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2281	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2282	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2283	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2284	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2285	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2286	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2287	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2288	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2289	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2290	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2291	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2292	&cpumR3CpuIdInfo);
2293	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2294	&cpumR3InfoVmxFeatures);
2295
2296	rc = cpumR3DbgInit(pVM);
2297	if (RT_FAILURE(rc))
2298	return rc;
2299
2300	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2301	/*
2302	* Check if we need to workaround partial/leaky FPU handling.
2303	*/
2304	cpumR3CheckLeakyFpu(pVM);
2305	#endif
2306
2307	/*
2308	* Initialize the Guest CPUID and MSR states.
2309	*/
2310	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2311	if (RT_FAILURE(rc))
2312	return rc;
2313
2314	/*
2315	* Generate the RFLAGS cookie.
2316	*/
2317	pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 \| CPUMX86EFLAGS_INT_MASK_64);
2318
2319	/*
2320	* Init the VMX/SVM state.
2321	*
2322	* This must be done after initializing CPUID/MSR features as we access the
2323	* the VMX/SVM guest features below.
2324	*
2325	* In the case of nested VT-x, we also need to create the per-VCPU
2326	* VMX preemption timers.
2327	*/
2328	if (pVM->cpum.s.GuestFeatures.fVmx)
2329	cpumR3InitVmxHwVirtState(pVM);
2330	else if (pVM->cpum.s.GuestFeatures.fSvm)
2331	cpumR3InitSvmHwVirtState(pVM);
2332	else
2333	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2334
2335	/*
2336	* Initialize the general guest CPU state.
2337	*/
2338	CPUMR3Reset(pVM);
2339
2340	return VINF_SUCCESS;
2341	}
2342
2343
2344	/**
2345	* Applies relocations to data and code managed by this
2346	* component. This function will be called at init and
2347	* whenever the VMM need to relocate it self inside the GC.
2348	*
2349	* The CPUM will update the addresses used by the switcher.
2350	*
2351	* @param pVM The cross context VM structure.
2352	*/
2353	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2354	{
2355	RT_NOREF(pVM);
2356	}
2357
2358
2359	/**
2360	* Terminates the CPUM.
2361	*
2362	* Termination means cleaning up and freeing all resources,
2363	* the VM it self is at this point powered off or suspended.
2364	*
2365	* @returns VBox status code.
2366	* @param pVM The cross context VM structure.
2367	*/
2368	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2369	{
2370	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2371	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2372	{
2373	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2374	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2375	pVCpu->cpum.s.uMagic = 0;
2376	pvCpu->cpum.s.Guest.dr[5] = 0;
2377	}
2378	#endif
2379
2380	if (pVM->cpum.s.GuestFeatures.fVmx)
2381	{
2382	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2383	{
2384	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2385	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2386	{
2387	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2388	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2389	}
2390	}
2391	}
2392	return VINF_SUCCESS;
2393	}
2394
2395
2396	/**
2397	* Resets a virtual CPU.
2398	*
2399	* Used by CPUMR3Reset and CPU hot plugging.
2400	*
2401	* @param pVM The cross context VM structure.
2402	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2403	* being reset. This may differ from the current EMT.
2404	*/
2405	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2406	{
2407	/** @todo anything different for VCPU > 0? */
2408	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2409
2410	/*
2411	* Initialize everything to ZERO first.
2412	*/
2413	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2414
2415	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2416
2417	pVCpu->cpum.s.fUseFlags = fUseFlags;
2418
2419	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2420	pCtx->eip = 0x0000fff0;
2421	pCtx->edx = 0x00000600; /* P6 processor */
2422
2423	Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK \| X86_EFL_RAZ_LO_MASK \| X86_EFL_RA1_MASK)) == 0);
2424	pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie \| X86_EFL_RA1_MASK;
2425
2426	pCtx->cs.Sel = 0xf000;
2427	pCtx->cs.ValidSel = 0xf000;
2428	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2429	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2430	pCtx->cs.u32Limit = 0x0000ffff;
2431	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2432	pCtx->cs.Attr.n.u1Present = 1;
2433	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2434
2435	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2436	pCtx->ds.u32Limit = 0x0000ffff;
2437	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2438	pCtx->ds.Attr.n.u1Present = 1;
2439	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2440
2441	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2442	pCtx->es.u32Limit = 0x0000ffff;
2443	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2444	pCtx->es.Attr.n.u1Present = 1;
2445	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2446
2447	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2448	pCtx->fs.u32Limit = 0x0000ffff;
2449	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2450	pCtx->fs.Attr.n.u1Present = 1;
2451	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2452
2453	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2454	pCtx->gs.u32Limit = 0x0000ffff;
2455	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2456	pCtx->gs.Attr.n.u1Present = 1;
2457	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2458
2459	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2460	pCtx->ss.u32Limit = 0x0000ffff;
2461	pCtx->ss.Attr.n.u1Present = 1;
2462	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2463	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2464
2465	pCtx->idtr.cbIdt = 0xffff;
2466	pCtx->gdtr.cbGdt = 0xffff;
2467
2468	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2469	pCtx->ldtr.u32Limit = 0xffff;
2470	pCtx->ldtr.Attr.n.u1Present = 1;
2471	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2472
2473	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2474	pCtx->tr.u32Limit = 0xffff;
2475	pCtx->tr.Attr.n.u1Present = 1;
2476	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2477
2478	pCtx->dr[6] = X86_DR6_INIT_VAL;
2479	pCtx->dr[7] = X86_DR7_INIT_VAL;
2480
2481	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2482	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2483	pFpuCtx->FCW = 0x37f;
2484
2485	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2486	IA-32 Processor States Following Power-up, Reset, or INIT */
2487	pFpuCtx->MXCSR = 0x1F80;
2488	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2489
2490	pCtx->aXcr[0] = XSAVE_C_X87;
2491	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2492	{
2493	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2494	as we don't know what happened before. (Bother optimize later?) */
2495	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2496	}
2497
2498	/*
2499	* MSRs.
2500	*/
2501	/* Init PAT MSR */
2502	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2503
2504	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2505	* The Intel docs don't mention it. */
2506	Assert(!pCtx->msrEFER);
2507
2508	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2509	is supposed to be here, just trying provide useful/sensible values. */
2510	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2511	if (pRange)
2512	{
2513	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2514	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2515	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2516	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2517	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2518	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2519	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2520	}
2521
2522	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2523
2524	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2525	* called from each EMT while we're getting called by CPUMR3Reset()
2526	* iteratively on the same thread. Fix later. */
2527	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2528	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2529	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2530	#endif
2531
2532
2533	/* C-state control. Guesses. */
2534	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2535	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2536	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2537	* functionality. The default value must be different due to incompatible write mask.
2538	*/
2539	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2540	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2541	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2542	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2543
2544	/*
2545	* Hardware virtualization state.
2546	*/
2547	CPUMSetGuestGif(pCtx, true);
2548	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2549	if (pVM->cpum.s.GuestFeatures.fVmx)
2550	cpumR3ResetVmxHwVirtState(pVCpu);
2551	else if (pVM->cpum.s.GuestFeatures.fSvm)
2552	cpumR3ResetSvmHwVirtState(pVCpu);
2553	}
2554
2555
2556	/**
2557	* Resets the CPU.
2558	*
2559	* @param pVM The cross context VM structure.
2560	*/
2561	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2562	{
2563	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2564	{
2565	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2566	CPUMR3ResetCpu(pVM, pVCpu);
2567
2568	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2569
2570	/* Magic marker for searching in crash dumps. */
2571	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2572	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2573	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2574	#endif
2575	}
2576	}
2577
2578
2579
2580
2581	/**
2582	* Pass 0 live exec callback.
2583	*
2584	* @returns VINF_SSM_DONT_CALL_AGAIN.
2585	* @param pVM The cross context VM structure.
2586	* @param pSSM The saved state handle.
2587	* @param uPass The pass (0).
2588	*/
2589	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2590	{
2591	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2592	cpumR3SaveCpuId(pVM, pSSM);
2593	return VINF_SSM_DONT_CALL_AGAIN;
2594	}
2595
2596
2597	/**
2598	* Execute state save operation.
2599	*
2600	* @returns VBox status code.
2601	* @param pVM The cross context VM structure.
2602	* @param pSSM SSM operation handle.
2603	*/
2604	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2605	{
2606	/*
2607	* Save.
2608	*/
2609	SSMR3PutU32(pSSM, pVM->cCpus);
2610	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2611	CPUMCTX DummyHyperCtx;
2612	RT_ZERO(DummyHyperCtx);
2613	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2614	{
2615	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
2616	PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
2617
2618	/** @todo ditch this the next time we change the saved state. */
2619	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2620
2621	uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth;
2622	pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */
2623	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2624	pGstCtx->rflags.uBoth = fSavedRFlags;
2625
2626	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2627	if (pGstCtx->fXStateMask != 0)
2628	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2629	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2630	{
2631	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2632	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2633	}
2634	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2635	{
2636	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2637	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2638	}
2639	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2640	{
2641	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2642	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2643	}
2644	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2645	{
2646	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2647	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2648	}
2649	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2650	{
2651	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2652	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2653	}
2654	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2655	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2656	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2657	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2658	if (pVM->cpum.s.GuestFeatures.fSvm)
2659	{
2660	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2661	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2662	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2663	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2664	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2665	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2666	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2667	g_aSvmHwvirtHostState, NULL /* pvUser */);
2668	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2669	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2670	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2671	/* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2672	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2673	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2674	}
2675	if (pVM->cpum.s.GuestFeatures.fVmx)
2676	{
2677	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2678	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2679	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2680	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2681	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2682	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2683	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2684	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2685	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2686	0, g_aVmxHwvirtVmcs, NULL);
2687	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2688	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2689	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2690	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2691	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2692	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2693	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2694	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2695	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2696	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2697	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2698	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2699	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2700	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2701	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2702	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2703	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2704	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2705	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2706	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2707	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2708	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2709	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2710	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2711	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2712	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2713	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2714	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2715	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2716	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2717	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2718	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2719	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2720	}
2721	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2722	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2723	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2724	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2725	}
2726
2727	cpumR3SaveCpuId(pVM, pSSM);
2728	return VINF_SUCCESS;
2729	}
2730
2731
2732	/**
2733	* @callback_method_impl{FNSSMINTLOADPREP}
2734	*/
2735	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2736	{
2737	NOREF(pSSM);
2738	pVM->cpum.s.fPendingRestore = true;
2739	return VINF_SUCCESS;
2740	}
2741
2742
2743	/**
2744	* @callback_method_impl{FNSSMINTLOADEXEC}
2745	*/
2746	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2747	{
2748	int rc; /* Only for AssertRCReturn use. */
2749
2750	/*
2751	* Validate version.
2752	*/
2753	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
2754	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3
2755	&& uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2756	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2757	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2758	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2759	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2760	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2761	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2762	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2763	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2764	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2765	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2766	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2767	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2768	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2769	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2770	{
2771	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2772	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2773	}
2774
2775	if (uPass == SSM_PASS_FINAL)
2776	{
2777	/*
2778	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2779	* really old SSM file versions.)
2780	*/
2781	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2782	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2783	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2784	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2785
2786	/*
2787	* Figure x86 and ctx field definitions to use for older states.
2788	*/
2789	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2790	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2791	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2792	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2793	{
2794	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2795	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2796	}
2797	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2798	{
2799	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2800	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2801	}
2802
2803	/*
2804	* The hyper state used to preceed the CPU count. Starting with
2805	* XSAVE it was moved down till after we've got the count.
2806	*/
2807	CPUMCTX HyperCtxIgnored;
2808	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2809	{
2810	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2811	{
2812	X86FXSTATE Ign;
2813	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2814	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2815	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2816	}
2817	}
2818
2819	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2820	{
2821	uint32_t cCpus;
2822	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2823	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2824	VERR_SSM_UNEXPECTED_DATA);
2825	}
2826	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2827	\|\| pVM->cCpus == 1,
2828	("cCpus=%u\n", pVM->cCpus),
2829	VERR_SSM_UNEXPECTED_DATA);
2830
2831	uint32_t cbMsrs = 0;
2832	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2833	{
2834	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2835	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2836	VERR_SSM_UNEXPECTED_DATA);
2837	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2838	VERR_SSM_UNEXPECTED_DATA);
2839	}
2840
2841	/*
2842	* Do the per-CPU restoring.
2843	*/
2844	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2845	{
2846	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2847	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2848
2849	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2850	{
2851	/*
2852	* The XSAVE saved state layout moved the hyper state down here.
2853	*/
2854	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2855	AssertRCReturn(rc, rc);
2856
2857	/*
2858	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2859	*/
2860	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2861	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2862	AssertRCReturn(rc, rc);
2863
2864	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2865	if (pGstCtx->fXStateMask != 0)
2866	{
2867	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2868	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2869	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2870	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2871	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2872	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2873	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2874	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2875	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2876	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2877	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2878	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2879	}
2880
2881	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2882	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2883	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2884	{
2885	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2886	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2887	VERR_CPUM_INVALID_XCR0);
2888	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2889	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2890	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2891	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2892	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2893	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2894	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2895	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2896	}
2897
2898	/* Check that the XCR1 is zero, as we don't implement it yet. */
2899	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2900
2901	/*
2902	* Restore the individual extended state components we support.
2903	*/
2904	if (pGstCtx->fXStateMask != 0)
2905	{
2906	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2907	0, g_aCpumXSaveHdrFields, NULL);
2908	AssertRCReturn(rc, rc);
2909	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2910	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2911	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2912	VERR_CPUM_INVALID_XSAVE_HDR);
2913	}
2914	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2915	{
2916	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2917	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2918	}
2919	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2920	{
2921	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2922	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2923	}
2924	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2925	{
2926	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2927	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2928	}
2929	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2930	{
2931	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2932	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2933	}
2934	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2935	{
2936	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2937	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2938	}
2939	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2940	{
2941	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2942	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2943	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2944	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2945	}
2946	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2947	{
2948	if (pVM->cpum.s.GuestFeatures.fSvm)
2949	{
2950	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2951	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2952	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2953	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2954	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2955	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2956	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2957	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2958	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2959	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2960	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2961
2962	uint32_t fSavedLocalFFs = 0;
2963	rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
2964	AssertRCReturn(rc, rc);
2965	Assert(fSavedLocalFFs == 0 \|\| fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
2966	pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
2967
2968	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2969	}
2970	}
2971	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2972	{
2973	if (pVM->cpum.s.GuestFeatures.fVmx)
2974	{
2975	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2976	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2977	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2978	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2979	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2980	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2981	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2982	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2983	0, g_aVmxHwvirtVmcs, NULL);
2984	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2985	0, g_aVmxHwvirtVmcs, NULL);
2986	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2987	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2988	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2989	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2990	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2991	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2992	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2993	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2994	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2995	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2996	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2997	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2998	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2999	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
3000	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
3001	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
3002	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
3003	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
3004	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
3005	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
3006	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
3007	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
3008	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
3009	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
3010	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
3011	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
3012	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
3013	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
3014	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
3015	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
3016	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
3017	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
3018	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
3019	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3)
3020	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
3021	}
3022	}
3023	}
3024	else
3025	{
3026	/*
3027	* Pre XSAVE saved state.
3028	*/
3029	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
3030	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
3031	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
3032	}
3033
3034	/*
3035	* Restore a couple of flags and the MSRs.
3036	*/
3037	uint32_t fIgnoredUsedFlags = 0;
3038	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
3039	AssertRCReturn(rc, rc);
3040	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
3041
3042	rc = VINF_SUCCESS;
3043	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
3044	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
3045	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
3046	{
3047	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
3048	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
3049	}
3050	AssertRCReturn(rc, rc);
3051
3052	/* Deal with the reusing of reserved RFLAGS bits. */
3053	pGstCtx->rflags.uBoth \|= pVM->cpum.s.fReservedRFlagsCookie;
3054
3055	/* REM and other may have cleared must-be-one fields in DR6 and
3056	DR7, fix these. */
3057	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
3058	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
3059	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
3060	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
3061	}
3062
3063	/* Older states does not have the internal selector register flags
3064	and valid selector value. Supply those. */
3065	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3066	{
3067	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3068	{
3069	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3070	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
3071	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3072	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
3073	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
3074	if (fValid)
3075	{
3076	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3077	{
3078	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
3079	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
3080	}
3081
3082	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3083	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3084	}
3085	else
3086	{
3087	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3088	{
3089	paSelReg[iSelReg].fFlags = 0;
3090	paSelReg[iSelReg].ValidSel = 0;
3091	}
3092
3093	/* This might not be 104% correct, but I think it's close
3094	enough for all practical purposes... (REM always loaded
3095	LDTR registers.) */
3096	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3097	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3098	}
3099	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
3100	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
3101	}
3102	}
3103
3104	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
3105	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3106	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3107	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3108	{
3109	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3110	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3111	}
3112
3113	/*
3114	* A quick sanity check.
3115	*/
3116	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3117	{
3118	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3119	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3120	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3121	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3122	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3123	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3124	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3125	}
3126	}
3127
3128	pVM->cpum.s.fPendingRestore = false;
3129
3130	/*
3131	* Guest CPUIDs (and VMX MSR features).
3132	*/
3133	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3134	{
3135	CPUMMSRS GuestMsrs;
3136	RT_ZERO(GuestMsrs);
3137
3138	CPUMFEATURES BaseFeatures;
3139	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3140	if (fVmxGstFeat)
3141	{
3142	/*
3143	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3144	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3145	* here so we can compare them for compatibility after exploding guest features.
3146	*/
3147	BaseFeatures = pVM->cpum.s.GuestFeatures;
3148
3149	/* Use the VMX MSR features from the saved state while exploding guest features. */
3150	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3151	}
3152
3153	/* Load CPUID and explode guest features. */
3154	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3155	if (fVmxGstFeat)
3156	{
3157	/*
3158	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3159	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3160	* VMX features presented to the guest.
3161	*/
3162	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3163	if (!fIsCompat)
3164	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3165	}
3166	return rc;
3167	}
3168	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3169	}
3170
3171
3172	/**
3173	* @callback_method_impl{FNSSMINTLOADDONE}
3174	*/
3175	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3176	{
3177	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3178	return VINF_SUCCESS;
3179
3180	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3181	if (pVM->cpum.s.fPendingRestore)
3182	{
3183	LogRel(("CPUM: Missing state!\n"));
3184	return VERR_INTERNAL_ERROR_2;
3185	}
3186
3187	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3188	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3189	{
3190	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3191
3192	/* Notify PGM of the NXE states in case they've changed. */
3193	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3194
3195	/* During init. this is done in CPUMR3InitCompleted(). */
3196	if (fSupportsLongMode)
3197	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3198
3199	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3200	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3201	}
3202	return VINF_SUCCESS;
3203	}
3204
3205
3206	/**
3207	* Checks if the CPUM state restore is still pending.
3208	*
3209	* @returns true / false.
3210	* @param pVM The cross context VM structure.
3211	*/
3212	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3213	{
3214	return pVM->cpum.s.fPendingRestore;
3215	}
3216
3217
3218	/**
3219	* Formats the EFLAGS value into mnemonics.
3220	*
3221	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3222	* @param efl The EFLAGS value with both guest hardware and VBox
3223	* internal bits included.
3224	*/
3225	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3226	{
3227	/*
3228	* Format the flags.
3229	*/
3230	static const struct
3231	{
3232	const char pszSet; const char pszClear; uint32_t fFlag;
3233	} s_aFlags[] =
3234	{
3235	{ "vip",NULL, X86_EFL_VIP },
3236	{ "vif",NULL, X86_EFL_VIF },
3237	{ "ac", NULL, X86_EFL_AC },
3238	{ "vm", NULL, X86_EFL_VM },
3239	{ "rf", NULL, X86_EFL_RF },
3240	{ "nt", NULL, X86_EFL_NT },
3241	{ "ov", "nv", X86_EFL_OF },
3242	{ "dn", "up", X86_EFL_DF },
3243	{ "ei", "di", X86_EFL_IF },
3244	{ "tf", NULL, X86_EFL_TF },
3245	{ "nt", "pl", X86_EFL_SF },
3246	{ "nz", "zr", X86_EFL_ZF },
3247	{ "ac", "na", X86_EFL_AF },
3248	{ "po", "pe", X86_EFL_PF },
3249	{ "cy", "nc", X86_EFL_CF },
3250	{ "inh-ss", NULL, CPUMCTX_INHIBIT_SHADOW_SS },
3251	{ "inh-sti", NULL, CPUMCTX_INHIBIT_SHADOW_STI },
3252	{ "inh-nmi", NULL, CPUMCTX_INHIBIT_NMI },
3253	};
3254	char *psz = pszEFlags;
3255	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3256	{
3257	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3258	if (pszAdd)
3259	{
3260	strcpy(psz, pszAdd);
3261	psz += strlen(pszAdd);
3262	*psz++ = ' ';
3263	}
3264	}
3265	psz[-1] = '\0';
3266	}
3267
3268
3269	/**
3270	* Formats a full register dump.
3271	*
3272	* @param pVM The cross context VM structure.
3273	* @param pVCpu The cross context virtual CPU structure.
3274	* @param pHlp Output functions.
3275	* @param enmType The dump type.
3276	* @param pszPrefix Register name prefix.
3277	*/
3278	static void cpumR3InfoOne(PVM pVM, PCVMCPU pVCpu, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
3279	{
3280	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3281
3282	/*
3283	* Format the EFLAGS.
3284	*/
3285	char szEFlags[80];
3286	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->eflags.uBoth);
3287
3288	/*
3289	* Format the registers.
3290	*/
3291	uint32_t const efl = pCtx->eflags.u;
3292	switch (enmType)
3293	{
3294	case CPUMDUMPTYPE_TERSE:
3295	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3296	pHlp->pfnPrintf(pHlp,
3297	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3298	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3299	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3300	"%sr14=%016RX64 %sr15=%016RX64\n"
3301	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3302	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3303	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3304	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3305	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3306	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3307	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3308	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3309	else
3310	pHlp->pfnPrintf(pHlp,
3311	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3312	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3313	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3314	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3315	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3316	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3317	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3318	break;
3319
3320	case CPUMDUMPTYPE_DEFAULT:
3321	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3322	pHlp->pfnPrintf(pHlp,
3323	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3324	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3325	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3326	"%sr14=%016RX64 %sr15=%016RX64\n"
3327	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3328	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3329	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3330	,
3331	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3332	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3333	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3334	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3335	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3336	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3337	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3338	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3339	else
3340	pHlp->pfnPrintf(pHlp,
3341	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3342	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3343	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3344	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3345	,
3346	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3347	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3348	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3349	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3350	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3351	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3352	break;
3353
3354	case CPUMDUMPTYPE_VERBOSE:
3355	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3356	pHlp->pfnPrintf(pHlp,
3357	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3358	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3359	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3360	"%sr14=%016RX64 %sr15=%016RX64\n"
3361	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3362	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3363	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3364	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3365	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3366	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3367	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3368	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3369	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3370	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3371	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3372	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3373	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3374	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3375	,
3376	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3377	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3378	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3379	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3380	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3381	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3382	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3383	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3384	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3385	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3386	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3387	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3388	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3389	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3390	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3391	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3392	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3393	else
3394	pHlp->pfnPrintf(pHlp,
3395	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3396	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3397	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3398	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3399	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3400	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3401	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3402	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3403	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3404	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3405	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3406	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3407	,
3408	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3409	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3410	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3411	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3412	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3413	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3414	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3415	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3416	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3417	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3418	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3419	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3420
3421	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3422	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3423	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3424	{
3425	PCX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3426	pHlp->pfnPrintf(pHlp,
3427	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3428	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3429	,
3430	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3431	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3432	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3433	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3434	);
3435	/*
3436	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3437	* not (FP)R0-7 as Intel SDM suggests.
3438	*/
3439	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3440	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3441	{
3442	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3443	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3444	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3445	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3446	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3447	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3448	iExponent -= 16383; /* subtract bias */
3449	/** @todo This isn't entirenly correct and needs more work! */
3450	pHlp->pfnPrintf(pHlp,
3451	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3452	pszPrefix, iST, pszPrefix, iFPR,
3453	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3454	uTag, chSign, iInteger, u64Fraction, iExponent);
3455	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3456	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3457	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3458	else
3459	pHlp->pfnPrintf(pHlp, "\n");
3460	}
3461
3462	/* XMM/YMM/ZMM registers. */
3463	if (pCtx->fXStateMask & XSAVE_C_YMM)
3464	{
3465	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3466	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3467	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3468	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3469	pszPrefix, i, i < 10 ? " " : "",
3470	pYmmHiCtx->aYmmHi[i].au32[3],
3471	pYmmHiCtx->aYmmHi[i].au32[2],
3472	pYmmHiCtx->aYmmHi[i].au32[1],
3473	pYmmHiCtx->aYmmHi[i].au32[0],
3474	pFpuCtx->aXMM[i].au32[3],
3475	pFpuCtx->aXMM[i].au32[2],
3476	pFpuCtx->aXMM[i].au32[1],
3477	pFpuCtx->aXMM[i].au32[0]);
3478	else
3479	{
3480	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3481	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3482	pHlp->pfnPrintf(pHlp,
3483	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3484	pszPrefix, i, i < 10 ? " " : "",
3485	pZmmHi256->aHi256Regs[i].au32[7],
3486	pZmmHi256->aHi256Regs[i].au32[6],
3487	pZmmHi256->aHi256Regs[i].au32[5],
3488	pZmmHi256->aHi256Regs[i].au32[4],
3489	pZmmHi256->aHi256Regs[i].au32[3],
3490	pZmmHi256->aHi256Regs[i].au32[2],
3491	pZmmHi256->aHi256Regs[i].au32[1],
3492	pZmmHi256->aHi256Regs[i].au32[0],
3493	pYmmHiCtx->aYmmHi[i].au32[3],
3494	pYmmHiCtx->aYmmHi[i].au32[2],
3495	pYmmHiCtx->aYmmHi[i].au32[1],
3496	pYmmHiCtx->aYmmHi[i].au32[0],
3497	pFpuCtx->aXMM[i].au32[3],
3498	pFpuCtx->aXMM[i].au32[2],
3499	pFpuCtx->aXMM[i].au32[1],
3500	pFpuCtx->aXMM[i].au32[0]);
3501
3502	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3503	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3504	pHlp->pfnPrintf(pHlp,
3505	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3506	pszPrefix, i + 16,
3507	pZmm16Hi->aRegs[i].au32[15],
3508	pZmm16Hi->aRegs[i].au32[14],
3509	pZmm16Hi->aRegs[i].au32[13],
3510	pZmm16Hi->aRegs[i].au32[12],
3511	pZmm16Hi->aRegs[i].au32[11],
3512	pZmm16Hi->aRegs[i].au32[10],
3513	pZmm16Hi->aRegs[i].au32[9],
3514	pZmm16Hi->aRegs[i].au32[8],
3515	pZmm16Hi->aRegs[i].au32[7],
3516	pZmm16Hi->aRegs[i].au32[6],
3517	pZmm16Hi->aRegs[i].au32[5],
3518	pZmm16Hi->aRegs[i].au32[4],
3519	pZmm16Hi->aRegs[i].au32[3],
3520	pZmm16Hi->aRegs[i].au32[2],
3521	pZmm16Hi->aRegs[i].au32[1],
3522	pZmm16Hi->aRegs[i].au32[0]);
3523	}
3524	}
3525	else
3526	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3527	pHlp->pfnPrintf(pHlp,
3528	i & 1
3529	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3530	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3531	pszPrefix, i, i < 10 ? " " : "",
3532	pFpuCtx->aXMM[i].au32[3],
3533	pFpuCtx->aXMM[i].au32[2],
3534	pFpuCtx->aXMM[i].au32[1],
3535	pFpuCtx->aXMM[i].au32[0]);
3536
3537	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3538	{
3539	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3540	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3541	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3542	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3543	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3544	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3545	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3546	}
3547
3548	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3549	{
3550	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3551	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3552	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3553	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3554	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3555	}
3556
3557	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3558	{
3559	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3560	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3561	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3562	}
3563
3564	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3565	if (pFpuCtx->au32RsrvdRest[i])
3566	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3567	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3568	}
3569
3570	pHlp->pfnPrintf(pHlp,
3571	"%sEFER =%016RX64\n"
3572	"%sPAT =%016RX64\n"
3573	"%sSTAR =%016RX64\n"
3574	"%sCSTAR =%016RX64\n"
3575	"%sLSTAR =%016RX64\n"
3576	"%sSFMASK =%016RX64\n"
3577	"%sKERNELGSBASE =%016RX64\n",
3578	pszPrefix, pCtx->msrEFER,
3579	pszPrefix, pCtx->msrPAT,
3580	pszPrefix, pCtx->msrSTAR,
3581	pszPrefix, pCtx->msrCSTAR,
3582	pszPrefix, pCtx->msrLSTAR,
3583	pszPrefix, pCtx->msrSFMASK,
3584	pszPrefix, pCtx->msrKERNELGSBASE);
3585
3586	if (CPUMIsGuestInPAEModeEx(pCtx))
3587	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3588	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3589
3590	/*
3591	* MTRRs.
3592	*/
3593	if (pVM->cpum.s.GuestFeatures.fMtrr)
3594	{
3595	pHlp->pfnPrintf(pHlp,
3596	"%sMTRR_CAP =%016RX64\n"
3597	"%sMTRR_DEF_TYPE =%016RX64\n"
3598	"%sMTRR_FIX64K_00000 =%016RX64\n"
3599	"%sMTRR_FIX16K_80000 =%016RX64\n"
3600	"%sMTRR_FIX16K_A0000 =%016RX64\n"
3601	"%sMTRR_FIX4K_C0000 =%016RX64\n"
3602	"%sMTRR_FIX4K_C8000 =%016RX64\n"
3603	"%sMTRR_FIX4K_D0000 =%016RX64\n"
3604	"%sMTRR_FIX4K_D8000 =%016RX64\n"
3605	"%sMTRR_FIX4K_E0000 =%016RX64\n"
3606	"%sMTRR_FIX4K_E8000 =%016RX64\n"
3607	"%sMTRR_FIX4K_F0000 =%016RX64\n"
3608	"%sMTRR_FIX4K_F8000 =%016RX64\n",
3609	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrCap,
3610	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType,
3611	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000,
3612	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000,
3613	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000,
3614	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000,
3615	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000,
3616	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000,
3617	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000,
3618	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000,
3619	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000,
3620	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000,
3621	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000);
3622
3623	for (uint8_t iRange = 0; iRange < RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs); iRange++)
3624	{
3625	PCX86MTRRVAR pMtrrVar = &pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[iRange];
3626	bool const fIsValid = RT_BOOL(pMtrrVar->MtrrPhysMask & MSR_IA32_MTRR_PHYSMASK_VALID);
3627	if (fIsValid)
3628	{
3629	uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3630	RTGCPHYS const GCPhysMask = pMtrrVar->MtrrPhysMask & X86_PAGE_BASE_MASK;
3631	RTGCPHYS const GCPhysFirst = pMtrrVar->MtrrPhysBase & X86_PAGE_BASE_MASK;
3632	RTGCPHYS const GCPhysLast = (GCPhysFirst \| ~GCPhysMask) & ~fInvPhysMask;
3633	Assert((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask));
3634	Assert(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask));
3635	pHlp->pfnPrintf(pHlp,
3636	"%sMTRR_PHYSBASE[%2u] =%016RX64 First=%016RX64\n"
3637	"%sMTRR_PHYSMASK[%2u] =%016RX64 Last =%016RX64\n",
3638	pszPrefix, iRange, pMtrrVar->MtrrPhysBase, GCPhysFirst,
3639	pszPrefix, iRange, pMtrrVar->MtrrPhysMask, GCPhysLast);
3640	}
3641	else
3642	pHlp->pfnPrintf(pHlp,
3643	"%sMTRR_PHYSBASE[%2u] =%016RX64\n"
3644	"%sMTRR_PHYSMASK[%2u] =%016RX64\n",
3645	pszPrefix, iRange, pMtrrVar->MtrrPhysBase,
3646	pszPrefix, iRange, pMtrrVar->MtrrPhysMask);
3647	}
3648	}
3649	break;
3650	}
3651	}
3652
3653
3654	/**
3655	* Display all cpu states and any other cpum info.
3656	*
3657	* @param pVM The cross context VM structure.
3658	* @param pHlp The info helper functions.
3659	* @param pszArgs Arguments, ignored.
3660	*/
3661	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3662	{
3663	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3664	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3665	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3666	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3667	cpumR3InfoHost(pVM, pHlp, pszArgs);
3668	}
3669
3670
3671	/**
3672	* Parses the info argument.
3673	*
3674	* The argument starts with 'verbose', 'terse' or 'default' and then
3675	* continues with the comment string.
3676	*
3677	* @param pszArgs The pointer to the argument string.
3678	* @param penmType Where to store the dump type request.
3679	* @param ppszComment Where to store the pointer to the comment string.
3680	*/
3681	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3682	{
3683	if (!pszArgs)
3684	{
3685	*penmType = CPUMDUMPTYPE_DEFAULT;
3686	*ppszComment = "";
3687	}
3688	else
3689	{
3690	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3691	{
3692	pszArgs += 7;
3693	*penmType = CPUMDUMPTYPE_VERBOSE;
3694	}
3695	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3696	{
3697	pszArgs += 5;
3698	*penmType = CPUMDUMPTYPE_TERSE;
3699	}
3700	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3701	{
3702	pszArgs += 7;
3703	*penmType = CPUMDUMPTYPE_DEFAULT;
3704	}
3705	else
3706	*penmType = CPUMDUMPTYPE_DEFAULT;
3707	*ppszComment = RTStrStripL(pszArgs);
3708	}
3709	}
3710
3711
3712	/**
3713	* Display the guest cpu state.
3714	*
3715	* @param pVM The cross context VM structure.
3716	* @param pHlp The info helper functions.
3717	* @param pszArgs Arguments.
3718	*/
3719	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3720	{
3721	CPUMDUMPTYPE enmType;
3722	const char *pszComment;
3723	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3724
3725	PCVMCPU pVCpu = VMMGetCpu(pVM);
3726	if (!pVCpu)
3727	pVCpu = pVM->apCpusR3[0];
3728
3729	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3730
3731	cpumR3InfoOne(pVM, pVCpu, pHlp, enmType, "");
3732	}
3733
3734
3735	/**
3736	* Displays an SVM VMCB control area.
3737	*
3738	* @param pHlp The info helper functions.
3739	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3740	* @param pszPrefix Caller specified string prefix.
3741	*/
3742	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3743	{
3744	AssertReturnVoid(pHlp);
3745	AssertReturnVoid(pVmcbCtrl);
3746
3747	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3748	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3749	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3750	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3751	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3752	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3753	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3754	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3755	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3756	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3757	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3758	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3759	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3760	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3761	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3762	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3763	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3764	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3765	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3766	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3767	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3768	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3769	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3770	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3771	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3772	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3773	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3774	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3775	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3776	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3777	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3778	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3779	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3780	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3781	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3782	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3783	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3784	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3785	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3786	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3787	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3788	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3789	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3790	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3791	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3792	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3793	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3794	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3795	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3796	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3797	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3798	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3799	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3800	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3801	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3802	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3803	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3804	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3805	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3806	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3807	}
3808
3809
3810	/**
3811	* Helper for dumping the SVM VMCB selector registers.
3812	*
3813	* @param pHlp The info helper functions.
3814	* @param pSel Pointer to the SVM selector register.
3815	* @param pszName Name of the selector.
3816	* @param pszPrefix Caller specified string prefix.
3817	*/
3818	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3819	{
3820	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3821	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3822	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3823	}
3824
3825
3826	/**
3827	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3828	*
3829	* @param pHlp The info helper functions.
3830	* @param pXdtr Pointer to the descriptor table register.
3831	* @param pszName Name of the descriptor table register.
3832	* @param pszPrefix Caller specified string prefix.
3833	*/
3834	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3835	{
3836	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3837	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3838	}
3839
3840
3841	/**
3842	* Displays an SVM VMCB state-save area.
3843	*
3844	* @param pHlp The info helper functions.
3845	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3846	* @param pszPrefix Caller specified string prefix.
3847	*/
3848	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3849	{
3850	AssertReturnVoid(pHlp);
3851	AssertReturnVoid(pVmcbStateSave);
3852
3853	char szEFlags[80];
3854	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3855
3856	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3857	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3858	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3859	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3860	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3861	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3862	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3863	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3864	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3865	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3866	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3867	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3868	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3869	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3870	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3871	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3872	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3873	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3874	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3875	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3876	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3877	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3878	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3879	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3880	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3881	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3882	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3883	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3884	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3885	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3886	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3887	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3888	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3889	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3890	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3891	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3892	}
3893
3894
3895	/**
3896	* Displays a virtual-VMCS.
3897	*
3898	* @param pVCpu The cross context virtual CPU structure.
3899	* @param pHlp The info helper functions.
3900	* @param pVmcs Pointer to a virtual VMCS.
3901	* @param pszPrefix Caller specified string prefix.
3902	*/
3903	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3904	{
3905	AssertReturnVoid(pHlp);
3906	AssertReturnVoid(pVmcs);
3907
3908	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3909	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3910	do { \
3911	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3912	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3913	} while (0)
3914
3915	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3916	do { \
3917	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3918	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3919	} while (0)
3920
3921	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3922	do { \
3923	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3924	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3925	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3926	} while (0)
3927
3928	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3929	do { \
3930	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3931	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3932	} while (0)
3933
3934	/* Header. */
3935	{
3936	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3937	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3938	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3939	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3940	}
3941
3942	/* Control fields. */
3943	{
3944	/* 16-bit. */
3945	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3946	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3947	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3948	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3949	pHlp->pfnPrintf(pHlp, " %sHLAT prefix size = %#RX16\n", pszPrefix, pVmcs->u16HlatPrefixSize);
3950
3951	/* 32-bit. */
3952	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3953	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3954	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3955	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3956	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3957	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3958	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3959	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3960	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3961	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3962	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3963	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3964	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3965	{
3966	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3967	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3968	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3969	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3970	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3971	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3972	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3973	}
3974	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3975	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3976	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3977	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3978	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3979
3980	/* 64-bit. */
3981	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3982	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3983	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3984	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3985	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3986	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3987	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3988	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3989	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3990	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3991	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3992	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3993	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3994	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3995	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3996	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3997	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3998	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3999	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
4000	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
4001	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
4002	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
4003	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
4004	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
4005	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
4006	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
4007	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
4008	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
4009	pHlp->pfnPrintf(pHlp, " %sPCONFIG-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64PconfigExitBitmap.u);
4010	pHlp->pfnPrintf(pHlp, " %sHLAT ptr = %#RX64\n", pszPrefix, pVmcs->u64HlatPtr.u);
4011	pHlp->pfnPrintf(pHlp, " %sSecondary VM-exit controls = %#RX64\n", pszPrefix, pVmcs->u64ExitCtls2.u);
4012
4013	/* Natural width. */
4014	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
4015	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
4016	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
4017	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
4018	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
4019	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
4020	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
4021	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
4022	}
4023
4024	/* Guest state. */
4025	{
4026	char szEFlags[80];
4027	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
4028	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
4029
4030	/* 16-bit. */
4031	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
4032	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
4033	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
4034	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
4035	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
4036	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
4037	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
4038	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
4039	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4040	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4041	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
4042	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
4043
4044	/* 32-bit. */
4045	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
4046	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
4047	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
4048	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
4049	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
4050
4051	/* 64-bit. */
4052	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
4053	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
4054	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
4055	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
4056	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
4057	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
4058	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
4059	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
4060	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
4061	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
4062	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
4063	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
4064
4065	/* Natural width. */
4066	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
4067	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
4068	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
4069	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
4070	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
4071	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
4072	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
4073	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
4074	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
4075	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
4076	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
4077	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
4078	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
4079	}
4080
4081	/* Host state. */
4082	{
4083	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
4084
4085	/* 16-bit. */
4086	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
4087	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
4088	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
4089	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
4090	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
4091	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
4092	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
4093	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4094	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4095
4096	/* 32-bit. */
4097	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
4098
4099	/* 64-bit. */
4100	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
4101	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
4102	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
4103	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
4104
4105	/* Natural width. */
4106	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
4107	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
4108	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
4109	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
4110	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
4111	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
4112	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
4113	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
4114	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
4115	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
4116	}
4117
4118	/* Read-only fields. */
4119	{
4120	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
4121
4122	/* 16-bit (none currently). */
4123
4124	/* 32-bit. */
4125	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
4126	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
4127	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
4128	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
4129	{
4130	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
4131	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
4132	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
4133	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
4134	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
4135	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4136	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4137	}
4138	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
4139	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
4140	{
4141	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
4142	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
4143	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
4144	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
4145	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
4146	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
4147	}
4148	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
4149	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
4150	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
4151
4152	/* 64-bit. */
4153	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
4154
4155	/* Natural width. */
4156	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
4157	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
4158	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
4159	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
4160	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
4161	}
4162
4163	#ifdef DEBUG_ramshankar
4164	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4165	{
4166	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
4167	Assert(pvPage);
4168	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4169	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
4170	if (RT_SUCCESS(rc))
4171	{
4172	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
4173	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4174	pHlp->pfnPrintf(pHlp, "\n");
4175	}
4176	RTMemTmpFree(pvPage);
4177	}
4178	#else
4179	NOREF(pVCpu);
4180	#endif
4181
4182	#undef CPUMVMX_DUMP_HOST_XDTR
4183	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4184	#undef CPUMVMX_DUMP_GUEST_SEGREG
4185	#undef CPUMVMX_DUMP_GUEST_XDTR
4186	}
4187
4188
4189	/**
4190	* Display the guest's hardware-virtualization cpu state.
4191	*
4192	* @param pVM The cross context VM structure.
4193	* @param pHlp The info helper functions.
4194	* @param pszArgs Arguments, ignored.
4195	*/
4196	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4197	{
4198	RT_NOREF(pszArgs);
4199
4200	PVMCPU pVCpu = VMMGetCpu(pVM);
4201	if (!pVCpu)
4202	pVCpu = pVM->apCpusR3[0];
4203
4204	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4205	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4206	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4207
4208	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4209	pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4210	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4211
4212	if (fSvm)
4213	{
4214	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4215	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4216
4217	char szEFlags[80];
4218	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4219	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4220	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4221	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4222	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4223	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4224	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4225	pHlp->pfnPrintf(pHlp, " HostState:\n");
4226	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4227	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4228	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4229	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4230	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4231	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4232	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4233	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4234	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4235	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4236	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4237	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4238	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4239	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4240	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4241	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4242	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4243	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4244	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4245	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4246	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4247	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4248	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4249	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4250	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4251	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4252	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4253	}
4254	else if (fVmx)
4255	{
4256	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4257	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4258	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4259	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4260	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4261	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4262	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4263	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4264	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4265	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4266	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4267	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4268	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4269	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4270	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4271	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4272	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4273	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4274	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4275	}
4276	else
4277	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4278
4279	#undef CPUMHWVIRTDUMP_NONE
4280	#undef CPUMHWVIRTDUMP_COMMON
4281	#undef CPUMHWVIRTDUMP_SVM
4282	#undef CPUMHWVIRTDUMP_VMX
4283	#undef CPUMHWVIRTDUMP_LAST
4284	#undef CPUMHWVIRTDUMP_ALL
4285	}
4286
4287	/**
4288	* Display the current guest instruction
4289	*
4290	* @param pVM The cross context VM structure.
4291	* @param pHlp The info helper functions.
4292	* @param pszArgs Arguments, ignored.
4293	*/
4294	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4295	{
4296	NOREF(pszArgs);
4297
4298	PVMCPU pVCpu = VMMGetCpu(pVM);
4299	if (!pVCpu)
4300	pVCpu = pVM->apCpusR3[0];
4301
4302	char szInstruction[256];
4303	szInstruction[0] = '\0';
4304	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4305	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4306	}
4307
4308
4309	/**
4310	* Display the hypervisor cpu state.
4311	*
4312	* @param pVM The cross context VM structure.
4313	* @param pHlp The info helper functions.
4314	* @param pszArgs Arguments, ignored.
4315	*/
4316	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4317	{
4318	PVMCPU pVCpu = VMMGetCpu(pVM);
4319	if (!pVCpu)
4320	pVCpu = pVM->apCpusR3[0];
4321
4322	CPUMDUMPTYPE enmType;
4323	const char *pszComment;
4324	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4325	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4326
4327	pHlp->pfnPrintf(pHlp,
4328	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4329	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4330	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4331	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4332	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4333	}
4334
4335
4336	/**
4337	* Display the host cpu state.
4338	*
4339	* @param pVM The cross context VM structure.
4340	* @param pHlp The info helper functions.
4341	* @param pszArgs Arguments, ignored.
4342	*/
4343	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4344	{
4345	CPUMDUMPTYPE enmType;
4346	const char *pszComment;
4347	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4348	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4349
4350	PVMCPU pVCpu = VMMGetCpu(pVM);
4351	if (!pVCpu)
4352	pVCpu = pVM->apCpusR3[0];
4353	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4354
4355	/*
4356	* Format the EFLAGS.
4357	*/
4358	uint64_t efl = pCtx->rflags;
4359	char szEFlags[80];
4360	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4361
4362	/*
4363	* Format the registers.
4364	*/
4365	pHlp->pfnPrintf(pHlp,
4366	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4367	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4368	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4369	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4370	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4371	"r14=%016RX64 r15=%016RX64\n"
4372	"iopl=%d %31s\n"
4373	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4374	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4375	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4376	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4377	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4378	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4379	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4380	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4381	,
4382	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4383	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4384	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4385	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4386	pCtx->r11, pCtx->r12, pCtx->r13,
4387	pCtx->r14, pCtx->r15,
4388	X86_EFL_GET_IOPL(efl), szEFlags,
4389	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4390	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4391	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4392	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4393	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4394	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4395	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4396	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4397	}
4398
4399	/**
4400	* Structure used when disassembling and instructions in DBGF.
4401	* This is used so the reader function can get the stuff it needs.
4402	*/
4403	typedef struct CPUMDISASSTATE
4404	{
4405	/** Pointer to the CPU structure. */
4406	PDISSTATE pDis;
4407	/** Pointer to the VM. */
4408	PVM pVM;
4409	/** Pointer to the VMCPU. */
4410	PVMCPU pVCpu;
4411	/** Pointer to the first byte in the segment. */
4412	RTGCUINTPTR GCPtrSegBase;
4413	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4414	RTGCUINTPTR GCPtrSegEnd;
4415	/** The size of the segment minus 1. */
4416	RTGCUINTPTR cbSegLimit;
4417	/** Pointer to the current page - R3 Ptr. */
4418	void const *pvPageR3;
4419	/** Pointer to the current page - GC Ptr. */
4420	RTGCPTR pvPageGC;
4421	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4422	PGMPAGEMAPLOCK PageMapLock;
4423	/** Whether the PageMapLock is valid or not. */
4424	bool fLocked;
4425	/** 64 bits mode or not. */
4426	bool f64Bits;
4427	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4428
4429
4430	/**
4431	* @callback_method_impl{FNDISREADBYTES}
4432	*/
4433	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4434	{
4435	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4436	for (;;)
4437	{
4438	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4439
4440	/*
4441	* Need to update the page translation?
4442	*/
4443	if ( !pState->pvPageR3
4444	\|\| (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
4445	{
4446	/* translate the address */
4447	pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
4448
4449	/* Release mapping lock previously acquired. */
4450	if (pState->fLocked)
4451	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4452	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4453	if (RT_SUCCESS(rc))
4454	pState->fLocked = true;
4455	else
4456	{
4457	pState->fLocked = false;
4458	pState->pvPageR3 = NULL;
4459	return rc;
4460	}
4461	}
4462
4463	/*
4464	* Check the segment limit.
4465	*/
4466	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4467	return VERR_OUT_OF_SELECTOR_BOUNDS;
4468
4469	/*
4470	* Calc how much we can read.
4471	*/
4472	uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
4473	if (!pState->f64Bits)
4474	{
4475	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4476	if (cb > cbSeg && cbSeg)
4477	cb = cbSeg;
4478	}
4479	if (cb > cbMaxRead)
4480	cb = cbMaxRead;
4481
4482	/*
4483	* Read and advance or exit.
4484	*/
4485	memcpy(&pDis->Instr.ab[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
4486	offInstr += (uint8_t)cb;
4487	if (cb >= cbMinRead)
4488	{
4489	pDis->cbCachedInstr = offInstr;
4490	return VINF_SUCCESS;
4491	}
4492	cbMinRead -= (uint8_t)cb;
4493	cbMaxRead -= (uint8_t)cb;
4494	}
4495	}
4496
4497
4498	/**
4499	* Disassemble an instruction and return the information in the provided structure.
4500	*
4501	* @returns VBox status code.
4502	* @param pVM The cross context VM structure.
4503	* @param pVCpu The cross context virtual CPU structure.
4504	* @param pCtx Pointer to the guest CPU context.
4505	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4506	* @param pDis Disassembly state.
4507	* @param pszPrefix String prefix for logging (debug only).
4508	*
4509	*/
4510	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISSTATE pDis,
4511	const char *pszPrefix)
4512	{
4513	CPUMDISASSTATE State;
4514	int rc;
4515
4516	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4517	State.pDis = pDis;
4518	State.pvPageGC = 0;
4519	State.pvPageR3 = NULL;
4520	State.pVM = pVM;
4521	State.pVCpu = pVCpu;
4522	State.fLocked = false;
4523	State.f64Bits = false;
4524
4525	/*
4526	* Get selector information.
4527	*/
4528	DISCPUMODE enmDisCpuMode;
4529	if ( (pCtx->cr0 & X86_CR0_PE)
4530	&& pCtx->eflags.Bits.u1VM == 0)
4531	{
4532	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4533	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4534	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4535	State.GCPtrSegBase = pCtx->cs.u64Base;
4536	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4537	State.cbSegLimit = pCtx->cs.u32Limit;
4538	enmDisCpuMode = (State.f64Bits)
4539	? DISCPUMODE_64BIT
4540	: pCtx->cs.Attr.n.u1DefBig
4541	? DISCPUMODE_32BIT
4542	: DISCPUMODE_16BIT;
4543	}
4544	else
4545	{
4546	/* real or V86 mode */
4547	enmDisCpuMode = DISCPUMODE_16BIT;
4548	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4549	State.GCPtrSegEnd = 0xFFFFFFFF;
4550	State.cbSegLimit = 0xFFFFFFFF;
4551	}
4552
4553	/*
4554	* Disassemble the instruction.
4555	*/
4556	uint32_t cbInstr;
4557	#ifndef LOG_ENABLED
4558	RT_NOREF_PV(pszPrefix);
4559	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pDis, &cbInstr);
4560	if (RT_SUCCESS(rc))
4561	{
4562	#else
4563	char szOutput[160];
4564	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4565	pDis, &cbInstr, szOutput, sizeof(szOutput));
4566	if (RT_SUCCESS(rc))
4567	{
4568	/* log it */
4569	if (pszPrefix)
4570	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4571	else
4572	Log(("%s", szOutput));
4573	#endif
4574	rc = VINF_SUCCESS;
4575	}
4576	else
4577	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4578
4579	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4580	if (State.fLocked)
4581	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4582
4583	return rc;
4584	}
4585
4586
4587
4588	/**
4589	* API for controlling a few of the CPU features found in CR4.
4590	*
4591	* Currently only X86_CR4_TSD is accepted as input.
4592	*
4593	* @returns VBox status code.
4594	*
4595	* @param pVM The cross context VM structure.
4596	* @param fOr The CR4 OR mask.
4597	* @param fAnd The CR4 AND mask.
4598	*/
4599	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4600	{
4601	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4602	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4603
4604	pVM->cpum.s.CR4.OrMask &= fAnd;
4605	pVM->cpum.s.CR4.OrMask \|= fOr;
4606
4607	return VINF_SUCCESS;
4608	}
4609
4610
4611	/**
4612	* Called when the ring-3 init phase completes.
4613	*
4614	* @returns VBox status code.
4615	* @param pVM The cross context VM structure.
4616	* @param enmWhat Which init phase.
4617	*/
4618	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4619	{
4620	switch (enmWhat)
4621	{
4622	case VMINITCOMPLETED_RING3:
4623	{
4624	/*
4625	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4626	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4627	*/
4628	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4629	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4630	{
4631	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4632
4633	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4634	if (fSupportsLongMode)
4635	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4636	}
4637
4638	/* Register statistic counters for MSRs. */
4639	cpumR3MsrRegStats(pVM);
4640
4641	/* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
4642	CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
4643	cpumR3CpuIdRing3InitDone(pVM);
4644
4645	/* Create VMX-preemption timer for nested guests if required. Must be
4646	done here as CPUM is initialized before TM. */
4647	if (pVM->cpum.s.GuestFeatures.fVmx)
4648	{
4649	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4650	{
4651	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4652	char szName[32];
4653	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4654	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4655	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4656	AssertLogRelRCReturn(rc, rc);
4657	}
4658	}
4659
4660	/*
4661	* Initialize MTRRs.
4662	*/
4663	if (pVM->cpum.s.fMtrrRead)
4664	{
4665	uint64_t cbRam;
4666	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4667	AssertReturn(cbRam > _1M, VERR_CPUM_IPE_1);
4668	RTGCPHYS const GCPhysFirst = _1M;
4669	RTGCPHYS const GCPhysLast = cbRam - 1;
4670	RTGCPHYS const GCPhysLength = GCPhysLast - GCPhysFirst;
4671	uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
4672	RTGCPHYS const GCPhysMask = (~(GCPhysLength - 1) & ~fInvPhysMask) & X86_PAGE_BASE_MASK;
4673	uint64_t const uMtrrPhysMask = GCPhysMask \| MSR_IA32_MTRR_PHYSMASK_VALID;
4674	#ifdef VBOX_STRICT
4675	/* Paranoia. */
4676	Assert(GCPhysLast == ((GCPhysFirst \| ~GCPhysMask) & ~fInvPhysMask));
4677	Assert((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask));
4678	Assert(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask));
4679	#endif
4680	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4681	{
4682	PCPUMCTXMSRS pCtxMsrs = &pVM->apCpusR3[idCpu]->cpum.s.GuestMsrs;
4683	pCtxMsrs->msr.MtrrFix64K_00000 = 0x0606060606060606;
4684	pCtxMsrs->msr.MtrrFix16K_80000 = 0x0606060606060606;
4685	pCtxMsrs->msr.MtrrFix16K_A0000 = 0;
4686	pCtxMsrs->msr.MtrrFix4K_C0000 = 0x0505050505050505;
4687	pCtxMsrs->msr.MtrrFix4K_C8000 = 0x0505050505050505;
4688	pCtxMsrs->msr.MtrrFix4K_D0000 = 0x0505050505050505;
4689	pCtxMsrs->msr.MtrrFix4K_D8000 = 0x0505050505050505;
4690	pCtxMsrs->msr.MtrrFix4K_E0000 = 0x0505050505050505;
4691	pCtxMsrs->msr.MtrrFix4K_E8000 = 0x0505050505050505;
4692	pCtxMsrs->msr.MtrrFix4K_F0000 = 0x0505050505050505;
4693	pCtxMsrs->msr.MtrrFix4K_F8000 = 0x0505050505050505;
4694	pCtxMsrs->msr.aMtrrVarMsrs[0].MtrrPhysBase = GCPhysFirst \| X86_MTRR_MT_WB;
4695	pCtxMsrs->msr.aMtrrVarMsrs[0].MtrrPhysMask = uMtrrPhysMask;
4696	}
4697	LogRel(("CPUM: Initialized MTRRs (MtrrPhysMask=%RGp GCPhysLast=%RGp)\n", uMtrrPhysMask, GCPhysLast));
4698	}
4699	break;
4700	}
4701
4702	default:
4703	break;
4704	}
4705	return VINF_SUCCESS;
4706	}
4707
4708
4709	/**
4710	* Called when the ring-0 init phases completed.
4711	*
4712	* @param pVM The cross context VM structure.
4713	*/
4714	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4715	{
4716	/*
4717	* Enable log buffering as we're going to log a lot of lines.
4718	*/
4719	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4720
4721	/*
4722	* Log the cpuid.
4723	*/
4724	RTCPUSET OnlineSet;
4725	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4726	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4727	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4728	RTCPUID cCores = RTMpGetCoreCount();
4729	if (cCores)
4730	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4731	LogRel(("*********************** CPUID dump **********************\n"));
4732	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4733	LogRel(("\n"));
4734	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4735	LogRel(("****************** End of CPUID dump ********************\n"));
4736
4737	/*
4738	* Log VT-x extended features.
4739	*
4740	* SVM features are currently all covered under CPUID so there is nothing
4741	* to do here for SVM.
4742	*/
4743	if (pVM->cpum.s.HostFeatures.fVmx)
4744	{
4745	LogRel(("********************* VT-x features *********************\n"));
4746	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4747	LogRel(("\n"));
4748	LogRel(("***************** End of VT-x features ******************\n"));
4749	}
4750
4751	/*
4752	* Restore the log buffering state to what it was previously.
4753	*/
4754	RTLogRelSetBuffering(fOldBuffered);
4755	}
4756
4757
4758	/**
4759	* Marks the guest debug state as active.
4760	*
4761	* @param pVCpu The cross context virtual CPU structure.
4762	*
4763	* @note This is used solely by NEM (hence the name) to set the correct flags here
4764	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4765	* The specific NEM backends have to make sure to load the correct values.
4766	*/
4767	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4768	{
4769	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4770	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4771	}
4772
4773
4774	/**
4775	* Marks the hyper debug state as active.
4776	*
4777	* @param pVCpu The cross context virtual CPU structure.
4778	*
4779	* @note This is used solely by NEM (hence the name) to set the correct flags here
4780	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4781	* The specific NEM backends have to make sure to load the correct values.
4782	*/
4783	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4784	{
4785	/*
4786	* Make sure the hypervisor values are up to date.
4787	*/
4788	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4789
4790	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4791	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4792	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 101932

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