CPUM.cpp@ 107650

Last change on this file since 107650 was 107650, checked in by vboxsync, 8 days ago
VMM/CPUM,++: Made the HostFeatures match the host when targeting x86 guests on arm64 hosts. Merged and deduplicated code targeting x86 & amd64. jiraref:VBP-1470
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 279.4 KB

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1	/* $Id: CPUM.cpp 107650 2025-01-10 13:42:28Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
31	* also responsible for lazy FPU handling and some of the context loading
32	* in raw mode.
33	*
34	* There are three CPU contexts, the most important one is the guest one (GC).
35	* When running in raw-mode (RC) there is a special hyper context for the VMM
36	* part that floats around inside the guest address space. When running in
37	* raw-mode, CPUM also maintains a host context for saving and restoring
38	* registers across world switches. This latter is done in cooperation with the
39	* world switcher (@see pg_vmm).
40	*
41	* @see grp_cpum
42	*
43	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44	*
45	* TODO: proper write up, currently just some notes.
46	*
47	* The ring-0 FPU handling per OS:
48	*
49	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
50	* convention (Visual C++ doesn't seem to have a way to disable
51	* generating such code either), so CR0.TS/EM are always zero from what I
52	* can tell. We are also forced to always load/save the guest XMM0-XMM15
53	* registers when entering/leaving guest context. Interrupt handlers
54	* using FPU/SSE will offically have call save and restore functions
55	* exported by the kernel, if the really really have to use the state.
56	*
57	* - 32-bit windows does lazy FPU handling, I think, probably including
58	* lazying saving. The Windows Internals book states that it's a bad
59	* idea to use the FPU in kernel space. However, it looks like it will
60	* restore the FPU state of the current thread in case of a kernel \#NM.
61	* Interrupt handlers should be same as for 64-bit.
62	*
63	* - Darwin allows taking \#NM in kernel space, restoring current thread's
64	* state if I read the code correctly. It saves the FPU state of the
65	* outgoing thread, and uses CR0.TS to lazily load the state of the
66	* incoming one. No idea yet how the FPU is treated by interrupt
67	* handlers, i.e. whether they are allowed to disable the state or
68	* something.
69	*
70	* - Linux also allows \#NM in kernel space (don't know since when), and
71	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72	* loads the incoming unless configured to agressivly load it. Interrupt
73	* handlers can ask whether they're allowed to use the FPU, and may
74	* freely trash the state if Linux thinks it has saved the thread's state
75	* already. This is a problem.
76	*
77	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78	* context. When switching threads, the kernel will save the state of
79	* the outgoing thread and lazy load the incoming one using CR0.TS.
80	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
81	* to do stuff, HAT are among the users. The routines there will
82	* manually clear CR0.TS and save the XMM registers they use only if
83	* CR0.TS was zero upon entry. They will skip it when not, because as
84	* mentioned above, the FPU state is saved when switching away from a
85	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86	* preserve. This is a problem if we restore CR0.TS to 1 after loading
87	* the guest state.
88	*
89	* - FreeBSD - no idea yet.
90	*
91	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93	* FPU states.
94	*
95	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96	* saving and restoring the host and guest states. The motivation for this
97	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98	*
99	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100	* state and only restore it once we've restore the host FPU state. This has the
101	* accidental side effect of triggering Solaris to preserve XMM registers in
102	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104	*
105	*
106	* @section sec_cpum_logging Logging Level Assignments.
107	*
108	* Following log level assignments:
109	* - Log6 is used for FPU state management.
110	* - Log7 is used for FPU state actualization.
111	*
112	*/
113
114
115	/*********************************************************************************************************************************
116	* Header Files *
117	*********************************************************************************************************************************/
118	#define LOG_GROUP LOG_GROUP_CPUM
119	#define CPUM_WITH_NONCONST_HOST_FEATURES
120	#include <VBox/vmm/cpum.h>
121	#include <VBox/vmm/cpumdis.h>
122	#include <VBox/vmm/cpumctx-v1_6.h>
123	#include <VBox/vmm/pgm.h>
124	#include <VBox/vmm/pdmapic.h>
125	#include <VBox/vmm/mm.h>
126	#include <VBox/vmm/em.h>
127	#include <VBox/vmm/iem.h>
128	#include <VBox/vmm/selm.h>
129	#include <VBox/vmm/dbgf.h>
130	#include <VBox/vmm/hm.h>
131	#include <VBox/vmm/hmvmxinline.h>
132	#include <VBox/vmm/ssm.h>
133	#include "CPUMInternal.h"
134	#include <VBox/vmm/vm.h>
135	#include <VBox/vmm/vmcc.h>
136
137	#include <VBox/param.h>
138	#include <VBox/dis.h>
139	#include <VBox/err.h>
140	#include <VBox/log.h>
141	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
142	# include <iprt/asm-amd64-x86.h>
143	#endif
144	#include <iprt/assert.h>
145	#include <iprt/cpuset.h>
146	#include <iprt/mem.h>
147	#include <iprt/mp.h>
148	#include <iprt/rand.h>
149	#include <iprt/string.h>
150
151
152	/*********************************************************************************************************************************
153	* Defined Constants And Macros *
154	*********************************************************************************************************************************/
155	/**
156	* This was used in the saved state up to the early life of version 14.
157	*
158	* It indicates that we may have some out-of-sync hidden segement registers.
159	* It is only relevant for raw-mode.
160	*/
161	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
162
163
164	/** For saved state only: Block injection of non-maskable interrupts to the guest.
165	* @note This flag was moved to CPUMCTX::eflags.uBoth in v7.0.4. */
166	#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
167
168
169	/*********************************************************************************************************************************
170	* Structures and Typedefs *
171	*********************************************************************************************************************************/
172
173	/**
174	* What kind of cpu info dump to perform.
175	*/
176	typedef enum CPUMDUMPTYPE
177	{
178	CPUMDUMPTYPE_TERSE,
179	CPUMDUMPTYPE_DEFAULT,
180	CPUMDUMPTYPE_VERBOSE
181	} CPUMDUMPTYPE;
182	/** Pointer to a cpu info dump type. */
183	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
184
185	/**
186	* Map of variable-range MTRRs.
187	*/
188	typedef struct CPUMMTRRMAP
189	{
190	/** The index of the next available MTRR. */
191	uint8_t idxMtrr;
192	/** The number of usable MTRRs. */
193	uint8_t cMtrrs;
194	/** Alignment padding. */
195	uint16_t uAlign;
196	/** The number of bytes to map via these MTRRs (not including UC regions). */
197	uint64_t cbToMap;
198	/** The number of bytes mapped via these MTRRs (not including UC regions). */
199	uint64_t cbMapped;
200	/** The variable-range MTRRs. */
201	X86MTRRVAR aMtrrs[CPUMCTX_MAX_MTRRVAR_COUNT];
202	} CPUMMTRRMAP;
203	/** Pointer to a CPUM variable-range MTRR structure. */
204	typedef CPUMMTRRMAP *PCPUMMTRRMAP;
205	/** Pointer to a const CPUM variable-range MTRR structure. */
206	typedef CPUMMTRRMAP const *PCCPUMMTRRMAP;
207
208
209	/*********************************************************************************************************************************
210	* Internal Functions *
211	*********************************************************************************************************************************/
212	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
213	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
214	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
215	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
216	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
217	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
218	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
219	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
220	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
221	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
222	#ifdef RT_ARCH_AMD64
223	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
224	#endif
225
226
227	/*********************************************************************************************************************************
228	* Global Variables *
229	*********************************************************************************************************************************/
230	/** Host CPU features. */
231	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
232
233	/** Saved state field descriptors for CPUMCTX. */
234	static const SSMFIELD g_aCpumCtxFields[] =
235	{
236	SSMFIELD_ENTRY( CPUMCTX, rdi),
237	SSMFIELD_ENTRY( CPUMCTX, rsi),
238	SSMFIELD_ENTRY( CPUMCTX, rbp),
239	SSMFIELD_ENTRY( CPUMCTX, rax),
240	SSMFIELD_ENTRY( CPUMCTX, rbx),
241	SSMFIELD_ENTRY( CPUMCTX, rdx),
242	SSMFIELD_ENTRY( CPUMCTX, rcx),
243	SSMFIELD_ENTRY( CPUMCTX, rsp),
244	SSMFIELD_ENTRY( CPUMCTX, rflags),
245	SSMFIELD_ENTRY( CPUMCTX, rip),
246	SSMFIELD_ENTRY( CPUMCTX, r8),
247	SSMFIELD_ENTRY( CPUMCTX, r9),
248	SSMFIELD_ENTRY( CPUMCTX, r10),
249	SSMFIELD_ENTRY( CPUMCTX, r11),
250	SSMFIELD_ENTRY( CPUMCTX, r12),
251	SSMFIELD_ENTRY( CPUMCTX, r13),
252	SSMFIELD_ENTRY( CPUMCTX, r14),
253	SSMFIELD_ENTRY( CPUMCTX, r15),
254	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
255	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
256	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
257	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
258	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
259	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
260	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
261	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
262	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
263	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
264	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
265	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
266	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
278	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
279	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
280	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
281	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
282	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
283	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
284	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
285	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
286	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
287	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
288	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
289	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
290	SSMFIELD_ENTRY( CPUMCTX, cr0),
291	SSMFIELD_ENTRY( CPUMCTX, cr2),
292	SSMFIELD_ENTRY( CPUMCTX, cr3),
293	SSMFIELD_ENTRY( CPUMCTX, cr4),
294	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
295	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
296	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
297	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
298	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
299	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
300	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
301	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
302	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
303	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
304	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
305	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
306	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
307	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
308	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
309	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
310	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
311	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
312	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
313	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
314	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
315	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
316	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
317	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
318	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
319	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
320	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
321	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
322	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
323	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
324	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
325	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
326	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
327	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
328	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
329	SSMFIELD_ENTRY_TERM()
330	};
331
332	/** Saved state field descriptors for SVM nested hardware-virtualization
333	* Host State. */
334	static const SSMFIELD g_aSvmHwvirtHostState[] =
335	{
336	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
337	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
338	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
339	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
340	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
341	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
342	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
343	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
344	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
345	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
346	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
347	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
348	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
349	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
350	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
351	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
352	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
353	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
354	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
355	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
356	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
357	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
358	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
359	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
360	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
361	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
362	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
363	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
364	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
365	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
366	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
367	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
368	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
369	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
370	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
371	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
372	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
373	SSMFIELD_ENTRY_TERM()
374	};
375
376	/** Saved state field descriptors for VMX nested hardware-virtualization
377	* VMCS. */
378	static const SSMFIELD g_aVmxHwvirtVmcs[] =
379	{
380	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
381	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
382	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
383	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
384	SSMFIELD_ENTRY_VER( VMXVVMCS, u32RestoreProcCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4),
385	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
386
387	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
388
389	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
390	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
391	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
392	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
393	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
394	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
395	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
396	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
397	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
398
399	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
400	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
401
402	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
403	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
404	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
405	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
406	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
407	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
408	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
409
410	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
411	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
412	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
413	SSMFIELD_ENTRY_VER( VMXVVMCS, u16HlatPrefixSize, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
414	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
415
416	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
417	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
418	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
419	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
420	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
421	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
422	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
423	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
424	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
425	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
426	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
427	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
428	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
429	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
430	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
431	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
432	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
433	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
434	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
435
436	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
437	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
438	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
439	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
440	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
441	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
442	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
443	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
444	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
445	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
446	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
447	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
448	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
449	SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
450	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
451	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
452	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
453	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
454	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
455	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
456	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
457	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
458	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
459	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
460	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
461	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
462	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
463	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
464	SSMFIELD_ENTRY_VER( VMXVVMCS, u64PconfigExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
465	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HlatPtr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
466	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ExitCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
467	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
468
469	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
470	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
471	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
472	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
473	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
474	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
475	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
476	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
477	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
478
479	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
480	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
481	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
482	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
483	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
484	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
485	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
486	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
487
488	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
489	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
490
491	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
492	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
493	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
494	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
495	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
496
497	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
498	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
499	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
500	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
501	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
502	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
503	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
504	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
505	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
506	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
507	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
508	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
509	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
510	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
511	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
512	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
513
514	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
515	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
516	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
517	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
518	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
519	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
520	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
521	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
522	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
523	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
524	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
525
526	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
527	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
528	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
529	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
530	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
531	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
532	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
533	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
534	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
535	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
536	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
537	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
538	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
539	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
540	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
541	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
542	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
543	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
544	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
545	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
546	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
547	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
548	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
549	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
550
551	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
552	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
553	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
554	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
555	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
556	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
557	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
558	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
559	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
560	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
561	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
562	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
563	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
564
565	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
566	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
567	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
568	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
569	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
570	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
571	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
572	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
573	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
574	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
575	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
576	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
577	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
578	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
579	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
580	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
581	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
582	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
583	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
584	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
585	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
586	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
587	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
588	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
589
590	SSMFIELD_ENTRY_TERM()
591	};
592
593	/** Saved state field descriptors for CPUMCTX. */
594	static const SSMFIELD g_aCpumX87Fields[] =
595	{
596	SSMFIELD_ENTRY( X86FXSTATE, FCW),
597	SSMFIELD_ENTRY( X86FXSTATE, FSW),
598	SSMFIELD_ENTRY( X86FXSTATE, FTW),
599	SSMFIELD_ENTRY( X86FXSTATE, FOP),
600	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
601	SSMFIELD_ENTRY( X86FXSTATE, CS),
602	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
603	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
604	SSMFIELD_ENTRY( X86FXSTATE, DS),
605	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
606	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
607	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
608	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
609	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
610	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
611	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
612	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
613	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
614	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
615	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
616	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
617	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
618	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
619	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
620	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
621	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
622	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
623	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
624	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
625	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
626	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
627	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
628	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
629	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
630	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
631	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
632	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
633	SSMFIELD_ENTRY_TERM()
634	};
635
636	/** Saved state field descriptors for X86XSAVEHDR. */
637	static const SSMFIELD g_aCpumXSaveHdrFields[] =
638	{
639	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
640	SSMFIELD_ENTRY_TERM()
641	};
642
643	/** Saved state field descriptors for X86XSAVEYMMHI. */
644	static const SSMFIELD g_aCpumYmmHiFields[] =
645	{
646	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
647	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
648	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
649	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
650	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
651	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
652	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
653	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
654	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
655	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
656	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
657	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
658	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
659	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
660	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
661	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
662	SSMFIELD_ENTRY_TERM()
663	};
664
665	/** Saved state field descriptors for X86XSAVEBNDREGS. */
666	static const SSMFIELD g_aCpumBndRegsFields[] =
667	{
668	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
669	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
670	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
671	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
672	SSMFIELD_ENTRY_TERM()
673	};
674
675	/** Saved state field descriptors for X86XSAVEBNDCFG. */
676	static const SSMFIELD g_aCpumBndCfgFields[] =
677	{
678	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
679	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
680	SSMFIELD_ENTRY_TERM()
681	};
682
683	#if 0 /** @todo */
684	/** Saved state field descriptors for X86XSAVEOPMASK. */
685	static const SSMFIELD g_aCpumOpmaskFields[] =
686	{
687	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
688	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
689	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
690	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
691	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
692	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
693	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
694	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
695	SSMFIELD_ENTRY_TERM()
696	};
697	#endif
698
699	/** Saved state field descriptors for X86XSAVEZMMHI256. */
700	static const SSMFIELD g_aCpumZmmHi256Fields[] =
701	{
702	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
703	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
704	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
705	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
706	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
707	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
708	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
709	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
710	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
711	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
712	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
713	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
714	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
715	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
716	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
717	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
718	SSMFIELD_ENTRY_TERM()
719	};
720
721	/** Saved state field descriptors for X86XSAVEZMM16HI. */
722	static const SSMFIELD g_aCpumZmm16HiFields[] =
723	{
724	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
725	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
726	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
727	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
728	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
729	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
730	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
731	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
732	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
733	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
734	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
735	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
736	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
737	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
738	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
739	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
740	SSMFIELD_ENTRY_TERM()
741	};
742
743
744
745	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
746	* registeres changed. */
747	static const SSMFIELD g_aCpumX87FieldsMem[] =
748	{
749	SSMFIELD_ENTRY( X86FXSTATE, FCW),
750	SSMFIELD_ENTRY( X86FXSTATE, FSW),
751	SSMFIELD_ENTRY( X86FXSTATE, FTW),
752	SSMFIELD_ENTRY( X86FXSTATE, FOP),
753	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
754	SSMFIELD_ENTRY( X86FXSTATE, CS),
755	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
756	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
757	SSMFIELD_ENTRY( X86FXSTATE, DS),
758	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
759	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
760	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
761	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
762	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
763	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
764	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
765	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
766	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
767	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
768	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
769	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
770	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
771	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
772	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
773	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
774	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
775	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
776	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
777	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
778	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
779	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
780	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
781	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
782	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
783	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
784	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
785	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
786	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
787	};
788
789	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
790	* registeres changed. */
791	static const SSMFIELD g_aCpumCtxFieldsMem[] =
792	{
793	SSMFIELD_ENTRY( CPUMCTX, rdi),
794	SSMFIELD_ENTRY( CPUMCTX, rsi),
795	SSMFIELD_ENTRY( CPUMCTX, rbp),
796	SSMFIELD_ENTRY( CPUMCTX, rax),
797	SSMFIELD_ENTRY( CPUMCTX, rbx),
798	SSMFIELD_ENTRY( CPUMCTX, rdx),
799	SSMFIELD_ENTRY( CPUMCTX, rcx),
800	SSMFIELD_ENTRY( CPUMCTX, rsp),
801	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
802	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
803	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
804	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
805	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
806	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
807	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
808	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
809	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
810	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
811	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
812	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
813	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
814	SSMFIELD_ENTRY( CPUMCTX, rflags),
815	SSMFIELD_ENTRY( CPUMCTX, rip),
816	SSMFIELD_ENTRY( CPUMCTX, r8),
817	SSMFIELD_ENTRY( CPUMCTX, r9),
818	SSMFIELD_ENTRY( CPUMCTX, r10),
819	SSMFIELD_ENTRY( CPUMCTX, r11),
820	SSMFIELD_ENTRY( CPUMCTX, r12),
821	SSMFIELD_ENTRY( CPUMCTX, r13),
822	SSMFIELD_ENTRY( CPUMCTX, r14),
823	SSMFIELD_ENTRY( CPUMCTX, r15),
824	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
825	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
826	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
827	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
828	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
829	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
830	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
831	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
832	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
833	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
834	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
835	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
836	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
837	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
838	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
839	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
840	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
841	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
842	SSMFIELD_ENTRY( CPUMCTX, cr0),
843	SSMFIELD_ENTRY( CPUMCTX, cr2),
844	SSMFIELD_ENTRY( CPUMCTX, cr3),
845	SSMFIELD_ENTRY( CPUMCTX, cr4),
846	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
847	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
848	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
849	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
850	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
851	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
852	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
853	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
854	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
855	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
856	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
857	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
858	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
859	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
860	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
861	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
862	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
863	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
864	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
865	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
866	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
867	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
868	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
869	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
870	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
871	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
872	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
873	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
874	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
875	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
876	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
877	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
878	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
879	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
880	SSMFIELD_ENTRY_TERM()
881	};
882
883	/** Saved state field descriptors for CPUMCTX_VER1_6. */
884	static const SSMFIELD g_aCpumX87FieldsV16[] =
885	{
886	SSMFIELD_ENTRY( X86FXSTATE, FCW),
887	SSMFIELD_ENTRY( X86FXSTATE, FSW),
888	SSMFIELD_ENTRY( X86FXSTATE, FTW),
889	SSMFIELD_ENTRY( X86FXSTATE, FOP),
890	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
891	SSMFIELD_ENTRY( X86FXSTATE, CS),
892	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
893	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
894	SSMFIELD_ENTRY( X86FXSTATE, DS),
895	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
896	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
897	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
898	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
899	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
900	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
901	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
902	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
903	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
904	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
905	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
906	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
907	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
908	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
909	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
910	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
911	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
912	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
913	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
914	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
915	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
916	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
917	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
918	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
919	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
920	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
921	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
922	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
923	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
924	SSMFIELD_ENTRY_TERM()
925	};
926
927	/** Saved state field descriptors for CPUMCTX_VER1_6. */
928	static const SSMFIELD g_aCpumCtxFieldsV16[] =
929	{
930	SSMFIELD_ENTRY( CPUMCTX, rdi),
931	SSMFIELD_ENTRY( CPUMCTX, rsi),
932	SSMFIELD_ENTRY( CPUMCTX, rbp),
933	SSMFIELD_ENTRY( CPUMCTX, rax),
934	SSMFIELD_ENTRY( CPUMCTX, rbx),
935	SSMFIELD_ENTRY( CPUMCTX, rdx),
936	SSMFIELD_ENTRY( CPUMCTX, rcx),
937	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
938	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
939	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
940	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
941	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
942	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
943	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
944	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
945	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
946	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
947	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
948	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
949	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
950	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
951	SSMFIELD_ENTRY( CPUMCTX, rflags),
952	SSMFIELD_ENTRY( CPUMCTX, rip),
953	SSMFIELD_ENTRY( CPUMCTX, r8),
954	SSMFIELD_ENTRY( CPUMCTX, r9),
955	SSMFIELD_ENTRY( CPUMCTX, r10),
956	SSMFIELD_ENTRY( CPUMCTX, r11),
957	SSMFIELD_ENTRY( CPUMCTX, r12),
958	SSMFIELD_ENTRY( CPUMCTX, r13),
959	SSMFIELD_ENTRY( CPUMCTX, r14),
960	SSMFIELD_ENTRY( CPUMCTX, r15),
961	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
962	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
963	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
964	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
965	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
966	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
967	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
968	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
969	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
970	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
971	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
972	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
973	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
974	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
975	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
976	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
977	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
978	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
979	SSMFIELD_ENTRY( CPUMCTX, cr0),
980	SSMFIELD_ENTRY( CPUMCTX, cr2),
981	SSMFIELD_ENTRY( CPUMCTX, cr3),
982	SSMFIELD_ENTRY( CPUMCTX, cr4),
983	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
984	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
985	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
986	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
987	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
988	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
989	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
990	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
991	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
992	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
993	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
994	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
995	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
996	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
997	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
998	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
999	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
1000	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
1001	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
1002	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
1003	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
1004	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
1005	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
1006	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
1007	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
1008	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
1009	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
1010	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
1011	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
1012	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
1013	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
1014	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
1015	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
1016	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
1017	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
1018	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
1019	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
1020	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
1021	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
1022	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
1023	SSMFIELD_ENTRY_TERM()
1024	};
1025
1026
1027	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1028	/**
1029	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
1030	*
1031	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
1032	* (last instruction pointer, last data pointer, last opcode) except when the ES
1033	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
1034	* clear these registers there is potential, local FPU leakage from a process
1035	* using the FPU to another.
1036	*
1037	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
1038	*
1039	* @param pVM The cross context VM structure.
1040	*/
1041	static void cpumR3CheckLeakyFpu(PVM pVM)
1042	{
1043	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1044	uint32_t const u32Family = u32CpuVersion >> 8;
1045	if ( u32Family >= 6 /* K7 and higher */
1046	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
1047	{
1048	uint32_t cExt = ASMCpuId_EAX(0x80000000);
1049	if (RTX86IsValidExtRange(cExt))
1050	{
1051	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1052	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1053	{
1054	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1055	{
1056	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1057	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1058	}
1059	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1060	}
1061	}
1062	}
1063	}
1064	#endif
1065
1066
1067	/**
1068	* Initialize the SVM hardware virtualization state.
1069	*
1070	* @param pVM The cross context VM structure.
1071	*/
1072	static void cpumR3InitSvmHwVirtState(PVM pVM)
1073	{
1074	LogRel(("CPUM: AMD-V nested-guest init\n"));
1075	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1076	{
1077	PVMCPU pVCpu = pVM->apCpusR3[i];
1078	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1079
1080	/* Initialize that SVM hardware virtualization is available. */
1081	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1082
1083	AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1084	AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1085	AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1086
1087	/* Initialize non-zero values. */
1088	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1089	}
1090	}
1091
1092
1093	/**
1094	* Resets per-VCPU SVM hardware virtualization state.
1095	*
1096	* @param pVCpu The cross context virtual CPU structure.
1097	*/
1098	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1099	{
1100	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1101	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1102
1103	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1104	RT_ZERO(pCtx->hwvirt.svm.HostState);
1105	RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1106	RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1107
1108	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1109	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1110	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1111	pCtx->hwvirt.svm.cPauseFilter = 0;
1112	pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1113	pCtx->hwvirt.svm.fInterceptEvents = false;
1114	}
1115
1116
1117	/**
1118	* Initializes the VMX hardware virtualization state.
1119	*
1120	* @param pVM The cross context VM structure.
1121	*/
1122	static void cpumR3InitVmxHwVirtState(PVM pVM)
1123	{
1124	LogRel(("CPUM: VT-x nested-guest init\n"));
1125	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1126	{
1127	PVMCPU pVCpu = pVM->apCpusR3[i];
1128	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1129
1130	/* Initialize that VMX hardware virtualization is available. */
1131	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1132
1133	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1134	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1135	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1136	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1137	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1138	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1139	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1140	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1141	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1142	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1143	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1144	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1145	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1146	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1147	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1148	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1149	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1150	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1151
1152	/* Initialize non-zero values. */
1153	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1154	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1155	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1156	}
1157	}
1158
1159
1160	/**
1161	* Resets per-VCPU VMX hardware virtualization state.
1162	*
1163	* @param pVCpu The cross context virtual CPU structure.
1164	*/
1165	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1166	{
1167	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1168	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1169
1170	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1171	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1172	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1173	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1174	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1175	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1176	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1177	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1178	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1179
1180	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1181	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1182	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1183	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1184	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1185	/* Don't reset diagnostics here. */
1186
1187	pCtx->hwvirt.vmx.fInterceptEvents = false;
1188	pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1189	pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1190	pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1191	pCtx->hwvirt.vmx.uEntryTick = 0;
1192	pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1193	pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1194
1195	/* Stop any VMX-preemption timer. */
1196	CPUMStopGuestVmxPremptTimer(pVCpu);
1197
1198	/* Clear all nested-guest FFs. */
1199	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1200	}
1201
1202
1203	/**
1204	* Displays the host and guest VMX features.
1205	*
1206	* @param pVM The cross context VM structure.
1207	* @param pHlp The info helper functions.
1208	* @param pszArgs "terse", "default" or "verbose".
1209	*/
1210	static DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1211	{
1212	RT_NOREF(pszArgs);
1213	#ifdef RT_ARCH_AMD64
1214	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures.s;
1215	#else
1216	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.GuestFeatures;
1217	#endif
1218	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1219	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1220	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1221	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1222	{
1223	#ifdef RT_ARCH_AMD64
1224	# define VMXFEATDUMP(a_szDesc, a_Var) \
1225	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1226	#else
1227	# define VMXFEATDUMP(a_szDesc, a_Var) \
1228	pHlp->pfnPrintf(pHlp, " %s = %u\n", a_szDesc, pGuestFeatures->a_Var)
1229	#endif
1230
1231	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1232	#ifdef RT_ARCH_AMD64
1233	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1234	#else
1235	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest\n");
1236	#endif
1237	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1238	/* Basic. */
1239	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1240
1241	/* Pin-based controls. */
1242	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1243	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1244	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1245	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1246	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1247
1248	/* Processor-based controls. */
1249	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1250	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1251	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1252	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1253	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1254	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1255	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1256	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1257	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1258	VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1259	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1260	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1261	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1262	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1263	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1264	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1265	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1266	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1267	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1268	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1269	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1270	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1271
1272	/* Secondary processor-based controls. */
1273	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1274	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1275	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1276	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1277	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1278	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1279	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1280	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1281	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1282	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1283	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1284	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1285	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1286	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1287	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1288	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1289	VMXFEATDUMP("PML - Page-Modification Log ", fVmxPml);
1290	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1291	VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1292	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1293	VMXFEATDUMP("PasidTranslate - PASID translation ", fVmxPasidTranslate);
1294	VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1295	VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1296	VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1297	VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1298	VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1299	VMXFEATDUMP("Pconfig - Enable PCONFIG ", fVmxPconfig);
1300	VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1301	VMXFEATDUMP("BusLockDetect - VMM Bus-Lock detection ", fVmxBusLockDetect);
1302	VMXFEATDUMP("InstrTimeout - Instruction timeout ", fVmxInstrTimeout);
1303
1304	/* Tertiary processor-based controls. */
1305	VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1306	VMXFEATDUMP("HLAT - Hypervisor-managed linear-address translation ", fVmxHlat);
1307	VMXFEATDUMP("EptPagingWrite - EPT paging-write ", fVmxEptPagingWrite);
1308	VMXFEATDUMP("GstPagingVerify - Guest-paging verification ", fVmxGstPagingVerify);
1309	VMXFEATDUMP("IpiVirt - IPI virtualization ", fVmxIpiVirt);
1310	VMXFEATDUMP("VirtSpecCtrl - Virtualize IA32_SPEC_CTRL ", fVmxVirtSpecCtrl);
1311
1312	/* VM-entry controls. */
1313	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1314	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1315	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1316	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1317
1318	/* VM-exit controls. */
1319	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1320	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1321	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1322	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1323	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1324	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1325	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1326	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1327	VMXFEATDUMP("SecondaryExitCtls - Secondary VM-exit controls ", fVmxSecondaryExitCtls);
1328
1329	/* Miscellaneous data. */
1330	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1331	VMXFEATDUMP("IntelPt - Intel Processor Trace in VMX operation ", fVmxPt);
1332	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1333	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1334	#undef VMXFEATDUMP
1335	}
1336	else
1337	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1338	}
1339
1340
1341	/**
1342	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1343	* or NEM) is allowed.
1344	*
1345	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1346	* otherwise.
1347	* @param pVM The cross context VM structure.
1348	*/
1349	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1350	{
1351	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1352	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1353	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1354	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1355	return true;
1356	#else
1357	NOREF(pVM);
1358	#endif
1359	return false;
1360	}
1361
1362
1363	/**
1364	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1365	*
1366	* @param pVM The cross context VM structure.
1367	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1368	* and no hardware-assisted nested-guest execution is
1369	* possible for this VM.
1370	* @param pGuestFeatures The guest features to use (only VMX features are
1371	* accessed).
1372	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1373	*
1374	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1375	*/
1376	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1377	{
1378	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1379
1380	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1381	Assert(pGuestFeatures->fVmx);
1382
1383	/* Basic information. */
1384	uint8_t const fTrueVmxMsrs = 1;
1385	{
1386	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1387	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1388	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1389	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1390	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1391	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1392	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1393	pGuestVmxMsrs->u64Basic = u64Basic;
1394	}
1395
1396	/* Pin-based VM-execution controls. */
1397	{
1398	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1399	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1400	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1401	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1402	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1403	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1404	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1405	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1406	fAllowed0, fAllowed1, fFeatures));
1407	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1408
1409	/* True pin-based VM-execution controls. */
1410	if (fTrueVmxMsrs)
1411	{
1412	/* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1413	pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1414	}
1415	}
1416
1417	/* Processor-based VM-execution controls. */
1418	{
1419	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1420	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1421	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1422	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1423	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1424	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1425	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1426	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1427	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1428	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1429	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1430	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1431	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1432	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1433	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1434	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1435	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1436	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1437	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1438	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1439	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1440	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1441	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1442	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1443	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1444	fAllowed1, fFeatures));
1445	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1446
1447	/* True processor-based VM-execution controls. */
1448	if (fTrueVmxMsrs)
1449	{
1450	/* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1451	uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1452	\| VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1453	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1454	pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1455	}
1456	}
1457
1458	/* Secondary processor-based VM-execution controls. */
1459	if (pGuestFeatures->fVmxSecondaryExecCtls)
1460	{
1461	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1462	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1463	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1464	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1465	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1466	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1467	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1468	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1469	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1470	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1471	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1472	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1473	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1474	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1475	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1476	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1477	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1478	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1479	\| (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1480	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1481	\| (pGuestFeatures->fVmxPasidTranslate << VMX_BF_PROC_CTLS2_PASID_TRANSLATE_SHIFT )
1482	\| (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1483	\| (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1484	\| (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1485	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1486	\| (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1487	\| (pGuestFeatures->fVmxPconfig << VMX_BF_PROC_CTLS2_PCONFIG_SHIFT )
1488	\| (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT )
1489	\| (pGuestFeatures->fVmxBusLockDetect << VMX_BF_PROC_CTLS2_BUSLOCK_DETECT_SHIFT )
1490	\| (pGuestFeatures->fVmxInstrTimeout << VMX_BF_PROC_CTLS2_INSTR_TIMEOUT_SHIFT );
1491	uint32_t const fAllowed0 = 0;
1492	uint32_t const fAllowed1 = fFeatures;
1493	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1494	}
1495
1496	/* Tertiary processor-based VM-execution controls. */
1497	if (pGuestFeatures->fVmxTertiaryExecCtls)
1498	{
1499	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT)
1500	\| (pGuestFeatures->fVmxHlat << VMX_BF_PROC_CTLS3_HLAT_SHIFT)
1501	\| (pGuestFeatures->fVmxEptPagingWrite << VMX_BF_PROC_CTLS3_EPT_PAGING_WRITE_SHIFT)
1502	\| (pGuestFeatures->fVmxGstPagingVerify << VMX_BF_PROC_CTLS3_GST_PAGING_VERIFY_SHIFT)
1503	\| (pGuestFeatures->fVmxIpiVirt << VMX_BF_PROC_CTLS3_IPI_VIRT_SHIFT)
1504	\| (pGuestFeatures->fVmxVirtSpecCtrl << VMX_BF_PROC_CTLS3_VIRT_SPEC_CTRL_SHIFT);
1505	}
1506
1507	/* VM-exit controls. */
1508	{
1509	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1510	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1511	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1512	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1513	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1514	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1515	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1516	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT )
1517	\| (pGuestFeatures->fVmxSecondaryExitCtls << VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_SHIFT );
1518	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1519	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1520	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1521	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1522	fAllowed1, fFeatures));
1523	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1524
1525	/* True VM-exit controls. */
1526	if (fTrueVmxMsrs)
1527	{
1528	/* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1529	uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1530	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1531	pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1532	}
1533	}
1534
1535	/* VM-entry controls. */
1536	{
1537	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1538	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1539	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1540	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1541	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1542	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1543	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1544	fAllowed1, fFeatures));
1545	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1546
1547	/* True VM-entry controls. */
1548	if (fTrueVmxMsrs)
1549	{
1550	/* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1551	uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1552	\| VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1553	\| VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1554	\| VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1555	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1556	pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1557	}
1558	}
1559
1560	/* Miscellaneous data. */
1561	{
1562	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1563
1564	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1565	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1566	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1567	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1568	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1569	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1570	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1571	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1572	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1573	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1574	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1575	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1576	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1577	}
1578
1579	/* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1580	pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1581
1582	/* CR0 Fixed-1. */
1583	{
1584	/*
1585	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1586	* This is different from CR4 fixed-1 bits which are reported as per the
1587	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1588	*/
1589	pGuestVmxMsrs->u64Cr0Fixed1 = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1590
1591	/* Make sure the CR0 MB1 bits are not clear. */
1592	Assert((pGuestVmxMsrs->u64Cr0Fixed1 & pGuestVmxMsrs->u64Cr0Fixed0) == pGuestVmxMsrs->u64Cr0Fixed0);
1593	}
1594
1595	/* CR4 Fixed-0. */
1596	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1597
1598	/* CR4 Fixed-1. */
1599	{
1600	pGuestVmxMsrs->u64Cr4Fixed1 = CPUMGetGuestCR4ValidMask(pVM) & pHostVmxMsrs->u64Cr4Fixed1;
1601
1602	/* Make sure the CR4 MB1 bits are not clear. */
1603	Assert((pGuestVmxMsrs->u64Cr4Fixed1 & pGuestVmxMsrs->u64Cr4Fixed0) == pGuestVmxMsrs->u64Cr4Fixed0);
1604
1605	/* Make sure bits that must always be set are set. */
1606	Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_PAE);
1607	Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_VMXE);
1608	}
1609
1610	/* VMCS Enumeration. */
1611	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1612
1613	/* VPID and EPT Capabilities. */
1614	if (pGuestFeatures->fVmxEpt)
1615	{
1616	/*
1617	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1618	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1619	* when INVVPID instruction is supported just to be more compatible with guest
1620	* hypervisors that may make assumptions by only looking at this MSR even though they
1621	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1622	*
1623	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1624	* See Intel spec. 30.3 "VMX Instructions".
1625	*/
1626	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1627	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1628
1629	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1630	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1631	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1632	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1633	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1634	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1635	/** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1636	/* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1637	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1638	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1639	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1640	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1641	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1642	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1643	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1644	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1645	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1646	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1647	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1648	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1649	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1650	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1651	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1652	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1653	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1654	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1655	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1656	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1657	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1658	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1659	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1660	}
1661
1662	/* VM Functions. */
1663	if (pGuestFeatures->fVmxVmFunc)
1664	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1665	}
1666
1667
1668	/**
1669	* Checks whether the given guest CPU VMX features are compatible with the provided
1670	* base features.
1671	*
1672	* @returns @c true if compatible, @c false otherwise.
1673	* @param pVM The cross context VM structure.
1674	* @param pBase The base VMX CPU features.
1675	* @param pGst The guest VMX CPU features.
1676	*
1677	* @remarks Only VMX feature bits are examined.
1678	*/
1679	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1680	{
1681	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1682	return false;
1683
1684	#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1685	#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1686	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1687	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1688	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1689	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1690	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1691	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1692	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1693	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1694	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1695	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1696	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1697	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1698	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1699	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1700	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1701	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1702	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1703	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1704	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1705	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1706	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1707	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1708	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1709	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1710	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1711	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1712	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1713	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1714	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1715	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1716	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1717	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1718	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1719	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1720	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1721	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1722	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1723	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1724	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1725	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1726	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1727	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1728	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1729	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1730	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1731	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1732	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1733	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPasidTranslate , 49) \
1734	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 50) \
1735	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 51) \
1736	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 52) \
1737	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 53) \
1738	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 54) \
1739	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPconfig , 55) \
1740	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 56) \
1741	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxBusLockDetect , 57) \
1742	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInstrTimeout , 58) \
1743	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 59) \
1744	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHlat , 60) \
1745	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptPagingWrite , 61) \
1746	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxGstPagingVerify , 62) \
1747	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIpiVirt , 63))
1748
1749	#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtSpecCtrl , 0) \
1750	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 1) \
1751	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 2) \
1752	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 3) \
1753	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 4) \
1754	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 5) \
1755	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 6) \
1756	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 7) \
1757	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 8) \
1758	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 9) \
1759	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 10) \
1760	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 12) \
1761	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 13) \
1762	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExitCtls , 14) \
1763	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 15) \
1764	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 16) \
1765	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 17) \
1766	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 18))
1767
1768	/* Check first set of feature bits. */
1769	{
1770	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1771	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1772	if ((fBase \| fGst) != fBase)
1773	{
1774	uint64_t const fDiff = fBase ^ fGst;
1775	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1776	fBase, fGst, fDiff));
1777	return false;
1778	}
1779	}
1780
1781	/* Check second set of feature bits. */
1782	{
1783	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1784	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1785	if ((fBase \| fGst) != fBase)
1786	{
1787	uint64_t const fDiff = fBase ^ fGst;
1788	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1789	fBase, fGst, fDiff));
1790	return false;
1791	}
1792	}
1793	#undef CPUM_VMX_FEAT_SHIFT
1794	#undef CPUM_VMX_MAKE_FEATURES_1
1795	#undef CPUM_VMX_MAKE_FEATURES_2
1796
1797	return true;
1798	}
1799
1800
1801	/**
1802	* Initializes VMX guest features and MSRs.
1803	*
1804	* @param pVM The cross context VM structure.
1805	* @param pCpumCfg The CPUM CFGM configuration node.
1806	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1807	* and no hardware-assisted nested-guest execution is
1808	* possible for this VM.
1809	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1810	*/
1811	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1812	{
1813	Assert(pVM);
1814	Assert(pCpumCfg);
1815	Assert(pGuestVmxMsrs);
1816
1817	/*
1818	* Query VMX features from CFGM.
1819	*/
1820	bool fVmxPreemptTimer;
1821	bool fVmxEpt;
1822	bool fVmxUnrestrictedGuest;
1823	{
1824	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
1825	* Whether to expose the VMX-preemption timer feature to the guest (if also
1826	* supported by the host hardware). When disabled will prevent exposing the
1827	* VMX-preemption timer feature to the guest even if the host supports it.
1828	*
1829	* @todo Currently disabled, see @bugref{9180#c108}.
1830	*/
1831	int rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &fVmxPreemptTimer, false);
1832	AssertLogRelRCReturnVoid(rc);
1833
1834	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1835	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
1836	* Whether to expose the EPT feature to the guest. The default is true.
1837	* When disabled will automatically prevent exposing features that rely
1838	* on it. This is dependent upon nested paging being enabled for the VM.
1839	*/
1840	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &fVmxEpt, true);
1841	AssertLogRelRCReturnVoid(rc);
1842
1843	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
1844	* Whether to expose the Unrestricted Guest feature to the guest. The
1845	* default is the same a /CPUM/Nested/VmxEpt. When disabled will
1846	* automatically prevent exposing features that rely on it.
1847	*/
1848	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &fVmxUnrestrictedGuest, fVmxEpt);
1849	AssertLogRelRCReturnVoid(rc);
1850	#else
1851	fVmxEpt = fVmxUnrestrictedGuest = false;
1852	#endif
1853	}
1854
1855	if (fVmxEpt)
1856	{
1857	const char *pszWhy = NULL;
1858	if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1859	pszWhy = "execution engine is neither HM nor IEM";
1860	#ifdef RT_ARCH_AMD64
1861	else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1862	pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1863	else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.s.fNoExecute)
1864	pszWhy = "NX is not available on the host";
1865	#endif
1866	if (pszWhy)
1867	{
1868	LogRel(("CPUM: Warning! EPT not exposed to the guest because %s\n", pszWhy));
1869	fVmxEpt = false;
1870	}
1871	}
1872	else if (fVmxUnrestrictedGuest)
1873	{
1874	LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1875	fVmxUnrestrictedGuest = false;
1876	}
1877
1878	/*
1879	* Initialize the set of VMX features we emulate.
1880	*
1881	* Note! Some bits might be reported as 1 always if they fall under the
1882	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1883	*/
1884	CPUMFEATURES EmuFeat;
1885	RT_ZERO(EmuFeat);
1886	EmuFeat.fVmx = 1;
1887	EmuFeat.fVmxInsOutInfo = 1;
1888	EmuFeat.fVmxExtIntExit = 1;
1889	EmuFeat.fVmxNmiExit = 1;
1890	EmuFeat.fVmxVirtNmi = 1;
1891	EmuFeat.fVmxPreemptTimer = fVmxPreemptTimer;
1892	EmuFeat.fVmxPostedInt = 0;
1893	EmuFeat.fVmxIntWindowExit = 1;
1894	EmuFeat.fVmxTscOffsetting = 1;
1895	EmuFeat.fVmxHltExit = 1;
1896	EmuFeat.fVmxInvlpgExit = 1;
1897	EmuFeat.fVmxMwaitExit = 1;
1898	EmuFeat.fVmxRdpmcExit = 1;
1899	EmuFeat.fVmxRdtscExit = 1;
1900	EmuFeat.fVmxCr3LoadExit = 1;
1901	EmuFeat.fVmxCr3StoreExit = 1;
1902	EmuFeat.fVmxTertiaryExecCtls = 0;
1903	EmuFeat.fVmxCr8LoadExit = 1;
1904	EmuFeat.fVmxCr8StoreExit = 1;
1905	EmuFeat.fVmxUseTprShadow = 1;
1906	EmuFeat.fVmxNmiWindowExit = 1;
1907	EmuFeat.fVmxMovDRxExit = 1;
1908	EmuFeat.fVmxUncondIoExit = 1;
1909	EmuFeat.fVmxUseIoBitmaps = 1;
1910	EmuFeat.fVmxMonitorTrapFlag = 0;
1911	EmuFeat.fVmxUseMsrBitmaps = 1;
1912	EmuFeat.fVmxMonitorExit = 1;
1913	EmuFeat.fVmxPauseExit = 1;
1914	EmuFeat.fVmxSecondaryExecCtls = 1;
1915	EmuFeat.fVmxVirtApicAccess = 1;
1916	EmuFeat.fVmxEpt = fVmxEpt;
1917	EmuFeat.fVmxDescTableExit = 1;
1918	EmuFeat.fVmxRdtscp = 1;
1919	EmuFeat.fVmxVirtX2ApicMode = 0;
1920	EmuFeat.fVmxVpid = 1;
1921	EmuFeat.fVmxWbinvdExit = 1;
1922	EmuFeat.fVmxUnrestrictedGuest = fVmxUnrestrictedGuest;
1923	EmuFeat.fVmxApicRegVirt = 0;
1924	EmuFeat.fVmxVirtIntDelivery = 0;
1925	EmuFeat.fVmxPauseLoopExit = 1;
1926	EmuFeat.fVmxRdrandExit = 1;
1927	EmuFeat.fVmxInvpcid = 1;
1928	EmuFeat.fVmxVmFunc = 0;
1929	EmuFeat.fVmxVmcsShadowing = 0;
1930	EmuFeat.fVmxRdseedExit = 1;
1931	EmuFeat.fVmxPml = 0;
1932	EmuFeat.fVmxEptXcptVe = 0;
1933	EmuFeat.fVmxConcealVmxFromPt = 0;
1934	EmuFeat.fVmxXsavesXrstors = 0;
1935	EmuFeat.fVmxPasidTranslate = 0;
1936	EmuFeat.fVmxModeBasedExecuteEpt = 0;
1937	EmuFeat.fVmxSppEpt = 0;
1938	EmuFeat.fVmxPtEpt = 0;
1939	EmuFeat.fVmxUseTscScaling = 0;
1940	EmuFeat.fVmxUserWaitPause = 0;
1941	EmuFeat.fVmxPconfig = 0;
1942	EmuFeat.fVmxEnclvExit = 0;
1943	EmuFeat.fVmxBusLockDetect = 0;
1944	EmuFeat.fVmxInstrTimeout = 0;
1945	EmuFeat.fVmxLoadIwKeyExit = 0;
1946	EmuFeat.fVmxHlat = 0;
1947	EmuFeat.fVmxEptPagingWrite = 0;
1948	EmuFeat.fVmxGstPagingVerify = 0;
1949	EmuFeat.fVmxIpiVirt = 0;
1950	EmuFeat.fVmxVirtSpecCtrl = 0;
1951	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1952	EmuFeat.fVmxIa32eModeGuest = 1;
1953	EmuFeat.fVmxEntryLoadEferMsr = 1;
1954	EmuFeat.fVmxEntryLoadPatMsr = 1;
1955	EmuFeat.fVmxExitSaveDebugCtls = 1;
1956	EmuFeat.fVmxHostAddrSpaceSize = 1;
1957	EmuFeat.fVmxExitAckExtInt = 1;
1958	EmuFeat.fVmxExitSavePatMsr = 1;
1959	EmuFeat.fVmxExitLoadPatMsr = 1;
1960	EmuFeat.fVmxExitSaveEferMsr = 1;
1961	EmuFeat.fVmxExitLoadEferMsr = 1;
1962	EmuFeat.fVmxSavePreemptTimer = 0 & fVmxPreemptTimer; /* Cannot be enabled if VMX-preemption timer is disabled. */
1963	EmuFeat.fVmxSecondaryExitCtls = 0;
1964	EmuFeat.fVmxExitSaveEferLma = 1 \| fVmxUnrestrictedGuest; /* Cannot be disabled if unrestricted guest is enabled. */
1965	EmuFeat.fVmxPt = 0;
1966	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1967	EmuFeat.fVmxEntryInjectSoftInt = 1;
1968
1969	/*
1970	* Merge guest features.
1971	*
1972	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1973	* by the hardware, hence we merge our emulated features with the host features below.
1974	*/
1975	#ifdef RT_ARCH_AMD64
1976	PCCPUMFEATURES const pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures.s : &EmuFeat;
1977	#else
1978	PCCPUMFEATURES const pBaseFeat = &EmuFeat;
1979	#endif
1980	PCPUMFEATURES const pGuestFeat = &pVM->cpum.s.GuestFeatures;
1981	Assert(pBaseFeat->fVmx);
1982	#define CPUMVMX_SET_GST_FEAT(a_Feat) \
1983	do { \
1984	pGuestFeat->a_Feat = (pBaseFeat->a_Feat & EmuFeat.a_Feat); \
1985	} while (0)
1986
1987	CPUMVMX_SET_GST_FEAT(fVmxInsOutInfo);
1988	CPUMVMX_SET_GST_FEAT(fVmxExtIntExit);
1989	CPUMVMX_SET_GST_FEAT(fVmxNmiExit);
1990	CPUMVMX_SET_GST_FEAT(fVmxVirtNmi);
1991	CPUMVMX_SET_GST_FEAT(fVmxPreemptTimer);
1992	CPUMVMX_SET_GST_FEAT(fVmxPostedInt);
1993	CPUMVMX_SET_GST_FEAT(fVmxIntWindowExit);
1994	CPUMVMX_SET_GST_FEAT(fVmxTscOffsetting);
1995	CPUMVMX_SET_GST_FEAT(fVmxHltExit);
1996	CPUMVMX_SET_GST_FEAT(fVmxInvlpgExit);
1997	CPUMVMX_SET_GST_FEAT(fVmxMwaitExit);
1998	CPUMVMX_SET_GST_FEAT(fVmxRdpmcExit);
1999	CPUMVMX_SET_GST_FEAT(fVmxRdtscExit);
2000	CPUMVMX_SET_GST_FEAT(fVmxCr3LoadExit);
2001	CPUMVMX_SET_GST_FEAT(fVmxCr3StoreExit);
2002	CPUMVMX_SET_GST_FEAT(fVmxTertiaryExecCtls);
2003	CPUMVMX_SET_GST_FEAT(fVmxCr8LoadExit);
2004	CPUMVMX_SET_GST_FEAT(fVmxCr8StoreExit);
2005	CPUMVMX_SET_GST_FEAT(fVmxUseTprShadow);
2006	CPUMVMX_SET_GST_FEAT(fVmxNmiWindowExit);
2007	CPUMVMX_SET_GST_FEAT(fVmxMovDRxExit);
2008	CPUMVMX_SET_GST_FEAT(fVmxUncondIoExit);
2009	CPUMVMX_SET_GST_FEAT(fVmxUseIoBitmaps);
2010	CPUMVMX_SET_GST_FEAT(fVmxMonitorTrapFlag);
2011	CPUMVMX_SET_GST_FEAT(fVmxUseMsrBitmaps);
2012	CPUMVMX_SET_GST_FEAT(fVmxMonitorExit);
2013	CPUMVMX_SET_GST_FEAT(fVmxPauseExit);
2014	CPUMVMX_SET_GST_FEAT(fVmxSecondaryExecCtls);
2015	CPUMVMX_SET_GST_FEAT(fVmxVirtApicAccess);
2016	CPUMVMX_SET_GST_FEAT(fVmxEpt);
2017	CPUMVMX_SET_GST_FEAT(fVmxDescTableExit);
2018	CPUMVMX_SET_GST_FEAT(fVmxRdtscp);
2019	CPUMVMX_SET_GST_FEAT(fVmxVirtX2ApicMode);
2020	CPUMVMX_SET_GST_FEAT(fVmxVpid);
2021	CPUMVMX_SET_GST_FEAT(fVmxWbinvdExit);
2022	CPUMVMX_SET_GST_FEAT(fVmxUnrestrictedGuest);
2023	CPUMVMX_SET_GST_FEAT(fVmxApicRegVirt);
2024	CPUMVMX_SET_GST_FEAT(fVmxVirtIntDelivery);
2025	CPUMVMX_SET_GST_FEAT(fVmxPauseLoopExit);
2026	CPUMVMX_SET_GST_FEAT(fVmxRdrandExit);
2027	CPUMVMX_SET_GST_FEAT(fVmxInvpcid);
2028	CPUMVMX_SET_GST_FEAT(fVmxVmFunc);
2029	CPUMVMX_SET_GST_FEAT(fVmxVmcsShadowing);
2030	CPUMVMX_SET_GST_FEAT(fVmxRdseedExit);
2031	CPUMVMX_SET_GST_FEAT(fVmxPml);
2032	CPUMVMX_SET_GST_FEAT(fVmxEptXcptVe);
2033	CPUMVMX_SET_GST_FEAT(fVmxConcealVmxFromPt);
2034	CPUMVMX_SET_GST_FEAT(fVmxXsavesXrstors);
2035	CPUMVMX_SET_GST_FEAT(fVmxPasidTranslate);
2036	CPUMVMX_SET_GST_FEAT(fVmxModeBasedExecuteEpt);
2037	CPUMVMX_SET_GST_FEAT(fVmxSppEpt);
2038	CPUMVMX_SET_GST_FEAT(fVmxPtEpt);
2039	CPUMVMX_SET_GST_FEAT(fVmxUseTscScaling);
2040	CPUMVMX_SET_GST_FEAT(fVmxUserWaitPause);
2041	CPUMVMX_SET_GST_FEAT(fVmxPconfig);
2042	CPUMVMX_SET_GST_FEAT(fVmxEnclvExit);
2043	CPUMVMX_SET_GST_FEAT(fVmxBusLockDetect);
2044	CPUMVMX_SET_GST_FEAT(fVmxInstrTimeout);
2045	CPUMVMX_SET_GST_FEAT(fVmxLoadIwKeyExit);
2046	CPUMVMX_SET_GST_FEAT(fVmxHlat);
2047	CPUMVMX_SET_GST_FEAT(fVmxEptPagingWrite);
2048	CPUMVMX_SET_GST_FEAT(fVmxGstPagingVerify);
2049	CPUMVMX_SET_GST_FEAT(fVmxIpiVirt);
2050	CPUMVMX_SET_GST_FEAT(fVmxVirtSpecCtrl);
2051	CPUMVMX_SET_GST_FEAT(fVmxEntryLoadDebugCtls);
2052	CPUMVMX_SET_GST_FEAT(fVmxIa32eModeGuest);
2053	CPUMVMX_SET_GST_FEAT(fVmxEntryLoadEferMsr);
2054	CPUMVMX_SET_GST_FEAT(fVmxEntryLoadPatMsr);
2055	CPUMVMX_SET_GST_FEAT(fVmxExitSaveDebugCtls);
2056	CPUMVMX_SET_GST_FEAT(fVmxHostAddrSpaceSize);
2057	CPUMVMX_SET_GST_FEAT(fVmxExitAckExtInt);
2058	CPUMVMX_SET_GST_FEAT(fVmxExitSavePatMsr);
2059	CPUMVMX_SET_GST_FEAT(fVmxExitLoadPatMsr);
2060	CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferMsr);
2061	CPUMVMX_SET_GST_FEAT(fVmxExitLoadEferMsr);
2062	CPUMVMX_SET_GST_FEAT(fVmxSavePreemptTimer);
2063	CPUMVMX_SET_GST_FEAT(fVmxSecondaryExitCtls);
2064	CPUMVMX_SET_GST_FEAT(fVmxExitSaveEferLma);
2065	CPUMVMX_SET_GST_FEAT(fVmxPt);
2066	CPUMVMX_SET_GST_FEAT(fVmxVmwriteAll);
2067	CPUMVMX_SET_GST_FEAT(fVmxEntryInjectSoftInt);
2068
2069	#undef CPUMVMX_SET_GST_FEAT
2070
2071	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2072	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
2073	if ( pGuestFeat->fVmxPreemptTimer
2074	&& HMIsSubjectToVmxPreemptTimerErratum())
2075	{
2076	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum\n"));
2077	pGuestFeat->fVmxPreemptTimer = 0;
2078	pGuestFeat->fVmxSavePreemptTimer = 0;
2079	}
2080	#endif
2081
2082	/* Sanity checking. */
2083	if (!pGuestFeat->fVmxSecondaryExecCtls)
2084	{
2085	Assert(!pGuestFeat->fVmxVirtApicAccess);
2086	Assert(!pGuestFeat->fVmxEpt);
2087	Assert(!pGuestFeat->fVmxDescTableExit);
2088	Assert(!pGuestFeat->fVmxRdtscp);
2089	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
2090	Assert(!pGuestFeat->fVmxVpid);
2091	Assert(!pGuestFeat->fVmxWbinvdExit);
2092	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
2093	Assert(!pGuestFeat->fVmxApicRegVirt);
2094	Assert(!pGuestFeat->fVmxVirtIntDelivery);
2095	Assert(!pGuestFeat->fVmxPauseLoopExit);
2096	Assert(!pGuestFeat->fVmxRdrandExit);
2097	Assert(!pGuestFeat->fVmxInvpcid);
2098	Assert(!pGuestFeat->fVmxVmFunc);
2099	Assert(!pGuestFeat->fVmxVmcsShadowing);
2100	Assert(!pGuestFeat->fVmxRdseedExit);
2101	Assert(!pGuestFeat->fVmxPml);
2102	Assert(!pGuestFeat->fVmxEptXcptVe);
2103	Assert(!pGuestFeat->fVmxConcealVmxFromPt);
2104	Assert(!pGuestFeat->fVmxXsavesXrstors);
2105	Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
2106	Assert(!pGuestFeat->fVmxSppEpt);
2107	Assert(!pGuestFeat->fVmxPtEpt);
2108	Assert(!pGuestFeat->fVmxUseTscScaling);
2109	Assert(!pGuestFeat->fVmxUserWaitPause);
2110	Assert(!pGuestFeat->fVmxEnclvExit);
2111	}
2112	else if (pGuestFeat->fVmxUnrestrictedGuest)
2113	{
2114	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2115	Assert(pGuestFeat->fVmxExitSaveEferLma);
2116	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
2117	Assert(pGuestFeat->fVmxEpt);
2118	}
2119
2120	if (!pGuestFeat->fVmxTertiaryExecCtls)
2121	{
2122	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
2123	Assert(!pGuestFeat->fVmxHlat);
2124	Assert(!pGuestFeat->fVmxEptPagingWrite);
2125	Assert(!pGuestFeat->fVmxGstPagingVerify);
2126	Assert(!pGuestFeat->fVmxIpiVirt);
2127	Assert(!pGuestFeat->fVmxVirtSpecCtrl);
2128	}
2129
2130	/*
2131	* Finally initialize the VMX guest MSRs.
2132	*/
2133	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2134	}
2135
2136
2137	/**
2138	* Gets the host hardware-virtualization MSRs.
2139	*
2140	* @returns VBox status code.
2141	* @param pMsrs Where to store the MSRs.
2142	*/
2143	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2144	{
2145	Assert(pMsrs);
2146
2147	uint32_t fCaps = 0;
2148	int rc = SUPR3QueryVTCaps(&fCaps);
2149	if (RT_SUCCESS(rc))
2150	{
2151	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2152	{
2153	SUPHWVIRTMSRS HwvirtMsrs;
2154	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2155	if (RT_SUCCESS(rc))
2156	{
2157	if (fCaps & SUPVTCAPS_VT_X)
2158	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2159	else
2160	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2161	return VINF_SUCCESS;
2162	}
2163
2164	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2165	return rc;
2166	}
2167
2168	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2169	return VERR_INTERNAL_ERROR_5;
2170	}
2171
2172	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2173	return VINF_SUCCESS;
2174	}
2175
2176
2177	/**
2178	* @callback_method_impl{FNTMTIMERINT,
2179	* Callback that fires when the nested VMX-preemption timer expired.}
2180	*/
2181	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2182	{
2183	RT_NOREF(pVM, hTimer);
2184	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2185	AssertPtr(pVCpu);
2186	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2187	}
2188
2189
2190	/**
2191	* Initializes the CPUM.
2192	*
2193	* @returns VBox status code.
2194	* @param pVM The cross context VM structure.
2195	*/
2196	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2197	{
2198	LogFlow(("CPUMR3Init\n"));
2199
2200	/*
2201	* Assert alignment, sizes and tables.
2202	*/
2203	AssertCompileMemberAlignment(VM, cpum.s, 32);
2204	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2205	AssertCompileSizeAlignment(CPUMCTX, 64);
2206	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2207	#ifdef RT_ARCH_AMD64
2208	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2209	#endif
2210	AssertCompileMemberAlignment(VM, cpum, 64);
2211	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2212	#ifdef VBOX_STRICT
2213	int rc2 = cpumR3MsrStrictInitChecks();
2214	AssertRCReturn(rc2, rc2);
2215	#endif
2216
2217	/*
2218	* Gather info about the host CPU.
2219	*/
2220	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2221	if (!ASMHasCpuId())
2222	{
2223	LogRel(("The CPU doesn't support CPUID!\n"));
2224	return VERR_UNSUPPORTED_CPU;
2225	}
2226
2227	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2228	#endif
2229
2230	CPUMMSRS HostMsrs;
2231	RT_ZERO(HostMsrs);
2232	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2233	AssertLogRelRCReturn(rc, rc);
2234
2235	/* Use the host features detected by CPUMR0ModuleInit if available. */
2236	if (pVM->cpum.s.HostFeatures.Common.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2237	g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures.s;
2238	else
2239	{
2240	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2241	PCPUMCPUIDLEAF paLeaves;
2242	uint32_t cLeaves;
2243	rc = CPUMCpuIdCollectLeavesFromX86Host(&paLeaves, &cLeaves);
2244	AssertLogRelRCReturn(rc, rc);
2245
2246	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2247	RTMemFree(paLeaves);
2248	AssertLogRelRCReturn(rc, rc);
2249
2250	#elif defined(RT_ARCH_ARM64)
2251	CPUMARMV8IDREGS IdRegs = {0};
2252	rc = CPUMCpuIdCollectIdRegistersFromArmV8Host(&IdRegs);
2253	AssertLogRelRCReturn(rc, rc);
2254
2255	rc = cpumCpuIdExplodeFeaturesArmV8(&IdRegs, &g_CpumHostFeatures.s);
2256	AssertLogRelRCReturn(rc, rc);
2257
2258	#else
2259	# error port me
2260	#endif
2261	AssertLogRelRCReturn(rc, rc);
2262	pVM->cpum.s.HostFeatures.s = g_CpumHostFeatures.s;
2263	}
2264	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.Common.enmCpuVendor; /* a bit bogus for mismatching host/guest */
2265
2266	#if 0 /** @todo fix */
2267	/** @todo we shouldn't be using the x86/AMD64 CPUMFEATURES for HostFeatures,
2268	* but it's too much work to fix that now. So, instead we just set
2269	* the bits we think are important for CPUMR3CpuId... This must
2270	* correspond to what IEM can emulate on ARM64. */
2271	pVM->cpum.s.HostFeatures.fCmpXchg8b = true;
2272	pVM->cpum.s.HostFeatures.fCmpXchg16b = true;
2273	pVM->cpum.s.HostFeatures.fPopCnt = true;
2274	pVM->cpum.s.HostFeatures.fAbm = true;
2275	pVM->cpum.s.HostFeatures.fBmi1 = true;
2276	pVM->cpum.s.HostFeatures.fBmi2 = true;
2277	pVM->cpum.s.HostFeatures.fAdx = true;
2278	pVM->cpum.s.HostFeatures.fSse = true;
2279	pVM->cpum.s.HostFeatures.fSse2 = true;
2280	pVM->cpum.s.HostFeatures.fSse3 = true;
2281	pVM->cpum.s.HostFeatures.fSse41 = true;
2282	pVM->cpum.s.HostFeatures.fSse42 = true;
2283	pVM->cpum.s.HostFeatures.fLahfSahf = true;
2284	pVM->cpum.s.HostFeatures.fMovBe = true;
2285	pVM->cpum.s.HostFeatures.fXSaveRstor = true;
2286	pVM->cpum.s.HostFeatures.fOpSysXSaveRstor = true;
2287	/** @todo r=aeichner Keep AVX/AVX2 disabled for now, too many missing instruction emulations. */
2288	# if 1
2289	pVM->cpum.s.HostFeatures.cbMaxExtendedState = RT_UOFFSETOF(X86XSAVEAREA, u.YmmHi);
2290	# else
2291	pVM->cpum.s.HostFeatures.cbMaxExtendedState = RT_UOFFSETOF(X86XSAVEAREA, u.YmmHi) + sizeof(X86XSAVEYMMHI);
2292	pVM->cpum.s.HostFeatures.fAvx = false;
2293	pVM->cpum.s.HostFeatures.fAvx2 = false;
2294	# endif
2295
2296	/* We must strongly discourage the guest from doing unnecessary stuff with the
2297	page tables to avoid exploits, as that's expensive and doesn't apply to us. */
2298	pVM->cpum.s.HostFeatures.fArchRdclNo = true;
2299	pVM->cpum.s.HostFeatures.fArchIbrsAll = true;
2300	//pVM->cpum.s.HostFeatures.fArchRsbOverride = true;
2301	pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = true;
2302	pVM->cpum.s.HostFeatures.fArchMdsNo = true;
2303	VMCC_FOR_EACH_VMCPU_STMT(pVM, pVCpu->cpum.s.GuestMsrs.msr.ArchCaps = MSR_IA32_ARCH_CAP_F_RDCL_NO
2304	\| MSR_IA32_ARCH_CAP_F_IBRS_ALL
2305	//\| MSR_IA32_ARCH_CAP_F_RSBO
2306	\| MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D
2307	\| MSR_IA32_ARCH_CAP_F_SSB_NO
2308	\| MSR_IA32_ARCH_CAP_F_MDS_NO
2309	\| MSR_IA32_ARCH_CAP_F_IF_PSCHANGE_MC_NO
2310	//\| MSR_IA32_ARCH_CAP_F_TSX_CTRL
2311	//\| MSR_IA32_ARCH_CAP_F_TAA_NO
2312	//\| MSR_IA32_ARCH_CAP_F_MISC_PACKAGE_CTRLS
2313	//\| MSR_IA32_ARCH_CAP_F_ENERGY_FILTERING_CTL
2314	//\| MSR_IA32_ARCH_CAP_F_DOITM
2315	\| MSR_IA32_ARCH_CAP_F_SBDR_SSDP_NO
2316	\| MSR_IA32_ARCH_CAP_F_FBSDP_NO
2317	\| MSR_IA32_ARCH_CAP_F_PSDP_NO
2318	//\| MSR_IA32_ARCH_CAP_F_FB_CLEAR
2319	//\| MSR_IA32_ARCH_CAP_F_FB_CLEAR_CTRL
2320	//\| MSR_IA32_ARCH_CAP_F_RRSBA
2321	\| MSR_IA32_ARCH_CAP_F_BHI_NO
2322	//\| MSR_IA32_ARCH_CAP_F_XAPIC_DISABLE_STATUS
2323	//\| MSR_IA32_ARCH_CAP_F_OVERCLOCKING_STATUS
2324	\| MSR_IA32_ARCH_CAP_F_PBRSB_NO
2325	//\| MSR_IA32_ARCH_CAP_F_GDS_CTRL
2326	\| MSR_IA32_ARCH_CAP_F_GDS_NO
2327	\| MSR_IA32_ARCH_CAP_F_RFDS_NO
2328	//\| MSR_IA32_ARCH_CAP_F_RFDS_CLEAR
2329	);
2330	#endif
2331
2332	/*
2333	* Check that the CPU supports the minimum features we require.
2334	*/
2335	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2336	if (!pVM->cpum.s.HostFeatures.s.fFxSaveRstor)
2337	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2338	if (!pVM->cpum.s.HostFeatures.s.fMmx)
2339	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2340	if (!pVM->cpum.s.HostFeatures.s.fTsc)
2341	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2342	#endif
2343
2344	/*
2345	* Figure out which XSAVE/XRSTOR features are available on the host.
2346	*/
2347	uint64_t fXcr0Host = 0;
2348	uint64_t fXStateHostMask = 0;
2349	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2350	if ( pVM->cpum.s.HostFeatures.s.fXSaveRstor
2351	&& pVM->cpum.s.HostFeatures.s.fOpSysXSaveRstor)
2352	{
2353	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2354	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2355	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2356	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2357	}
2358	#elif defined(RT_ARCH_ARM64)
2359	/** @todo r=aeichner Keep AVX/AVX2 disabled for now, too many missing instruction emulations. */
2360	fXStateHostMask = XSAVE_C_X87 \| XSAVE_C_SSE /\| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI/;
2361	#endif
2362	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2363	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2364	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2365
2366	/*
2367	* Initialize the host XSAVE/XRSTOR mask.
2368	*/
2369	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2370	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.s.cbMaxExtendedState;
2371	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2372	AssertLogRelReturn( pVM->cpum.s.HostFeatures.s.cbMaxExtendedState >= sizeof(X86FXSTATE)
2373	&& pVM->cpum.s.HostFeatures.s.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.abXState)
2374	&& pVM->cpum.s.HostFeatures.s.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.abXState)
2375	, VERR_CPUM_IPE_2);
2376	#endif
2377
2378	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2379	{
2380	PVMCPU pVCpu = pVM->apCpusR3[i];
2381	RT_NOREF(pVCpu);
2382
2383	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2384	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2385	#endif
2386	#ifdef VBOX_VMM_TARGET_X86
2387	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2388	#endif
2389	}
2390
2391	/*
2392	* Register saved state data item.
2393	*/
2394	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2395	NULL, cpumR3LiveExec, NULL,
2396	NULL, cpumR3SaveExec, NULL,
2397	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2398	if (RT_FAILURE(rc))
2399	return rc;
2400
2401	/*
2402	* Register info handlers and registers with the debugger facility.
2403	*/
2404	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2405	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2406	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2407	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2408	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2409	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2410	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2411	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2412	#ifdef RT_ARCH_AMD64
2413	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2414	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2415	#endif
2416	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2417	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2418	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2419	&cpumR3CpuIdInfo);
2420	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2421	&cpumR3InfoVmxFeatures);
2422
2423	rc = cpumR3DbgInit(pVM);
2424	if (RT_FAILURE(rc))
2425	return rc;
2426
2427	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2428	/*
2429	* Check if we need to workaround partial/leaky FPU handling.
2430	*/
2431	cpumR3CheckLeakyFpu(pVM);
2432	#endif
2433
2434	/*
2435	* Initialize the Guest CPUID and MSR states.
2436	*/
2437	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2438	if (RT_FAILURE(rc))
2439	return rc;
2440
2441	/*
2442	* Generate the RFLAGS cookie.
2443	*/
2444	pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 \| CPUMX86EFLAGS_INT_MASK_64);
2445
2446	/*
2447	* Init the VMX/SVM state.
2448	*
2449	* This must be done after initializing CPUID/MSR features as we access the
2450	* the VMX/SVM guest features below.
2451	*
2452	* In the case of nested VT-x, we also need to create the per-VCPU
2453	* VMX preemption timers.
2454	*/
2455	if (pVM->cpum.s.GuestFeatures.fVmx)
2456	cpumR3InitVmxHwVirtState(pVM);
2457	else if (pVM->cpum.s.GuestFeatures.fSvm)
2458	cpumR3InitSvmHwVirtState(pVM);
2459	else
2460	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2461
2462	/*
2463	* Initialize the general guest CPU state.
2464	*/
2465	CPUMR3Reset(pVM);
2466
2467	return VINF_SUCCESS;
2468	}
2469
2470
2471	/**
2472	* Applies relocations to data and code managed by this
2473	* component. This function will be called at init and
2474	* whenever the VMM need to relocate it self inside the GC.
2475	*
2476	* The CPUM will update the addresses used by the switcher.
2477	*
2478	* @param pVM The cross context VM structure.
2479	*/
2480	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2481	{
2482	RT_NOREF(pVM);
2483	}
2484
2485
2486	/**
2487	* Terminates the CPUM.
2488	*
2489	* Termination means cleaning up and freeing all resources,
2490	* the VM it self is at this point powered off or suspended.
2491	*
2492	* @returns VBox status code.
2493	* @param pVM The cross context VM structure.
2494	*/
2495	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2496	{
2497	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2498	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2499	{
2500	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2501	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2502	pVCpu->cpum.s.uMagic = 0;
2503	pvCpu->cpum.s.Guest.dr[5] = 0;
2504	}
2505	#endif
2506
2507	if (pVM->cpum.s.GuestFeatures.fVmx)
2508	{
2509	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2510	{
2511	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2512	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2513	{
2514	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2515	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2516	}
2517	}
2518	}
2519	return VINF_SUCCESS;
2520	}
2521
2522
2523	/**
2524	* Resets a virtual CPU.
2525	*
2526	* Used by CPUMR3Reset and CPU hot plugging.
2527	*
2528	* @param pVM The cross context VM structure.
2529	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2530	* being reset. This may differ from the current EMT.
2531	*/
2532	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2533	{
2534	/** @todo anything different for VCPU > 0? */
2535	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2536
2537	/*
2538	* Initialize everything to ZERO first.
2539	*/
2540	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2541
2542	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2543
2544	pVCpu->cpum.s.fUseFlags = fUseFlags;
2545
2546	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2547	pCtx->eip = 0x0000fff0;
2548	pCtx->edx = 0x00000600; /* P6 processor */
2549
2550	Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK \| X86_EFL_RAZ_LO_MASK \| X86_EFL_RA1_MASK)) == 0);
2551	pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie \| X86_EFL_RA1_MASK;
2552
2553	pCtx->cs.Sel = 0xf000;
2554	pCtx->cs.ValidSel = 0xf000;
2555	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2556	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2557	pCtx->cs.u32Limit = 0x0000ffff;
2558	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2559	pCtx->cs.Attr.n.u1Present = 1;
2560	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2561
2562	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2563	pCtx->ds.u32Limit = 0x0000ffff;
2564	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2565	pCtx->ds.Attr.n.u1Present = 1;
2566	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2567
2568	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2569	pCtx->es.u32Limit = 0x0000ffff;
2570	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2571	pCtx->es.Attr.n.u1Present = 1;
2572	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2573
2574	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2575	pCtx->fs.u32Limit = 0x0000ffff;
2576	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2577	pCtx->fs.Attr.n.u1Present = 1;
2578	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2579
2580	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2581	pCtx->gs.u32Limit = 0x0000ffff;
2582	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2583	pCtx->gs.Attr.n.u1Present = 1;
2584	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2585
2586	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2587	pCtx->ss.u32Limit = 0x0000ffff;
2588	pCtx->ss.Attr.n.u1Present = 1;
2589	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2590	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2591
2592	pCtx->idtr.cbIdt = 0xffff;
2593	pCtx->gdtr.cbGdt = 0xffff;
2594
2595	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2596	pCtx->ldtr.u32Limit = 0xffff;
2597	pCtx->ldtr.Attr.n.u1Present = 1;
2598	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2599
2600	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2601	pCtx->tr.u32Limit = 0xffff;
2602	pCtx->tr.Attr.n.u1Present = 1;
2603	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2604
2605	pCtx->dr[6] = X86_DR6_INIT_VAL;
2606	pCtx->dr[7] = X86_DR7_INIT_VAL;
2607
2608	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2609	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2610	pFpuCtx->FCW = 0x37f;
2611
2612	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2613	IA-32 Processor States Following Power-up, Reset, or INIT */
2614	pFpuCtx->MXCSR = 0x1F80;
2615	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2616
2617	pCtx->aXcr[0] = XSAVE_C_X87;
2618	#ifdef RT_ARCH_AMD64 /** @todo x86-on-ARM64: recheck this! */
2619	if (pVM->cpum.s.HostFeatures.s.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2620	#endif
2621	{
2622	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2623	as we don't know what happened before. (Bother optimize later?) */
2624	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2625	}
2626
2627	/*
2628	* MSRs.
2629	*/
2630	/* Init PAT MSR */
2631	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2632
2633	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2634	* The Intel docs don't mention it. */
2635	Assert(!pCtx->msrEFER);
2636
2637	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2638	is supposed to be here, just trying provide useful/sensible values. */
2639	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2640	if (pRange)
2641	{
2642	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2643	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2644	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2645	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2646	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2647	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2648	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2649	}
2650
2651	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2652
2653	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2654	* called from each EMT while we're getting called by CPUMR3Reset()
2655	* iteratively on the same thread. Fix later. */
2656	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2657	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2658	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2659	#endif
2660
2661
2662	/* C-state control. Guesses. */
2663	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2664	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2665	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2666	* functionality. The default value must be different due to incompatible write mask.
2667	*/
2668	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2669	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2670	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2671	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2672
2673	/*
2674	* Hardware virtualization state.
2675	*/
2676	CPUMSetGuestGif(pCtx, true);
2677	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2678	if (pVM->cpum.s.GuestFeatures.fVmx)
2679	cpumR3ResetVmxHwVirtState(pVCpu);
2680	else if (pVM->cpum.s.GuestFeatures.fSvm)
2681	cpumR3ResetSvmHwVirtState(pVCpu);
2682	}
2683
2684
2685	/**
2686	* Resets the CPU.
2687	*
2688	* @param pVM The cross context VM structure.
2689	*/
2690	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2691	{
2692	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2693	{
2694	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2695	CPUMR3ResetCpu(pVM, pVCpu);
2696
2697	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2698
2699	/* Magic marker for searching in crash dumps. */
2700	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2701	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2702	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2703	#endif
2704	}
2705	}
2706
2707
2708
2709
2710	/**
2711	* Pass 0 live exec callback.
2712	*
2713	* @returns VINF_SSM_DONT_CALL_AGAIN.
2714	* @param pVM The cross context VM structure.
2715	* @param pSSM The saved state handle.
2716	* @param uPass The pass (0).
2717	*/
2718	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2719	{
2720	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2721	cpumR3SaveCpuId(pVM, pSSM);
2722	return VINF_SSM_DONT_CALL_AGAIN;
2723	}
2724
2725
2726	/**
2727	* Execute state save operation.
2728	*
2729	* @returns VBox status code.
2730	* @param pVM The cross context VM structure.
2731	* @param pSSM SSM operation handle.
2732	*/
2733	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2734	{
2735	/*
2736	* Save.
2737	*/
2738	SSMR3PutU32(pSSM, pVM->cCpus);
2739	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2740	CPUMCTX DummyHyperCtx;
2741	RT_ZERO(DummyHyperCtx);
2742	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2743	{
2744	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
2745	PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
2746
2747	/** @todo ditch this the next time we change the saved state. */
2748	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2749
2750	uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth;
2751	pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */
2752	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2753	pGstCtx->rflags.uBoth = fSavedRFlags;
2754
2755	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2756	if (pGstCtx->fXStateMask != 0)
2757	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2758	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2759	{
2760	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2761	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2762	}
2763	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2764	{
2765	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2766	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2767	}
2768	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2769	{
2770	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2771	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2772	}
2773	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2774	{
2775	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2776	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2777	}
2778	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2779	{
2780	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2781	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2782	}
2783	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2784	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2785	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2786	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2787	if (pVM->cpum.s.GuestFeatures.fSvm)
2788	{
2789	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2790	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2791	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2792	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2793	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2794	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2795	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2796	g_aSvmHwvirtHostState, NULL /* pvUser */);
2797	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2798	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2799	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2800	/* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2801	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2802	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2803	}
2804	if (pVM->cpum.s.GuestFeatures.fVmx)
2805	{
2806	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2807	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2808	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2809	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2810	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2811	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2812	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2813	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2814	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2815	0, g_aVmxHwvirtVmcs, NULL);
2816	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2817	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2818	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2819	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2820	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2821	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2822	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2823	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2824	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2825	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2826	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2827	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2828	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2829	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2830	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2831	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2832	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2833	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2834	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2835	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2836	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2837	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2838	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2839	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2840	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2841	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2842	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2843	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2844	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2845	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2846	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2847	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2848	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2849	}
2850	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2851	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2852	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2853	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2854	}
2855
2856	cpumR3SaveCpuId(pVM, pSSM);
2857	return VINF_SUCCESS;
2858	}
2859
2860
2861	/**
2862	* @callback_method_impl{FNSSMINTLOADPREP}
2863	*/
2864	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2865	{
2866	NOREF(pSSM);
2867	pVM->cpum.s.fPendingRestore = true;
2868	return VINF_SUCCESS;
2869	}
2870
2871
2872	/**
2873	* @callback_method_impl{FNSSMINTLOADEXEC}
2874	*/
2875	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2876	{
2877	int rc; /* Only for AssertRCReturn use. */
2878
2879	/*
2880	* Validate version.
2881	*/
2882	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
2883	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3
2884	&& uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2885	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2886	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2887	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2888	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2889	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2890	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2891	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2892	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2893	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2894	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2895	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2896	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2897	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2898	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2899	{
2900	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2901	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2902	}
2903
2904	if (uPass == SSM_PASS_FINAL)
2905	{
2906	/*
2907	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2908	* really old SSM file versions.)
2909	*/
2910	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2911	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2912	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2913	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2914
2915	/*
2916	* Figure x86 and ctx field definitions to use for older states.
2917	*/
2918	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2919	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2920	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2921	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2922	{
2923	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2924	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2925	}
2926	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2927	{
2928	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2929	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2930	}
2931
2932	/*
2933	* The hyper state used to preceed the CPU count. Starting with
2934	* XSAVE it was moved down till after we've got the count.
2935	*/
2936	CPUMCTX HyperCtxIgnored;
2937	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2938	{
2939	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2940	{
2941	X86FXSTATE Ign;
2942	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2943	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2944	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2945	}
2946	}
2947
2948	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2949	{
2950	uint32_t cCpus;
2951	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2952	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2953	VERR_SSM_UNEXPECTED_DATA);
2954	}
2955	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2956	\|\| pVM->cCpus == 1,
2957	("cCpus=%u\n", pVM->cCpus),
2958	VERR_SSM_UNEXPECTED_DATA);
2959
2960	uint32_t cbMsrs = 0;
2961	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2962	{
2963	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2964	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2965	VERR_SSM_UNEXPECTED_DATA);
2966	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2967	VERR_SSM_UNEXPECTED_DATA);
2968	}
2969
2970	/*
2971	* Do the per-CPU restoring.
2972	*/
2973	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2974	{
2975	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2976	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2977
2978	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2979	{
2980	/*
2981	* The XSAVE saved state layout moved the hyper state down here.
2982	*/
2983	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2984	AssertRCReturn(rc, rc);
2985
2986	/*
2987	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2988	*/
2989	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2990	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2991	AssertRCReturn(rc, rc);
2992
2993	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2994	if (pGstCtx->fXStateMask != 0)
2995	{
2996	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2997	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2998	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2999	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
3000	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
3001	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
3002	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
3003	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
3004	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
3005	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
3006	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
3007	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
3008	}
3009
3010	/* Check that the XCR0 mask is valid (invalid results in #GP). */
3011	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
3012	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
3013	{
3014	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
3015	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
3016	VERR_CPUM_INVALID_XCR0);
3017	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
3018	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
3019	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
3020	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
3021	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
3022	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
3023	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
3024	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
3025	}
3026
3027	/* Check that the XCR1 is zero, as we don't implement it yet. */
3028	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3029
3030	/*
3031	* Restore the individual extended state components we support.
3032	*/
3033	if (pGstCtx->fXStateMask != 0)
3034	{
3035	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
3036	0, g_aCpumXSaveHdrFields, NULL);
3037	AssertRCReturn(rc, rc);
3038	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
3039	("bmXState=%#RX64 fXStateMask=%#RX64\n",
3040	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
3041	VERR_CPUM_INVALID_XSAVE_HDR);
3042	}
3043	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
3044	{
3045	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
3046	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
3047	}
3048	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
3049	{
3050	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
3051	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
3052	}
3053	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
3054	{
3055	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
3056	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
3057	}
3058	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
3059	{
3060	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
3061	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
3062	}
3063	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
3064	{
3065	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
3066	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
3067	}
3068	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
3069	{
3070	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
3071	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
3072	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
3073	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
3074	}
3075	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
3076	{
3077	if (pVM->cpum.s.GuestFeatures.fSvm)
3078	{
3079	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
3080	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
3081	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
3082	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
3083	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
3084	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
3085	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
3086	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
3087	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
3088	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
3089	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
3090
3091	uint32_t fSavedLocalFFs = 0;
3092	rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
3093	AssertRCReturn(rc, rc);
3094	Assert(fSavedLocalFFs == 0 \|\| fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
3095	pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
3096
3097	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
3098	}
3099	}
3100	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
3101	{
3102	if (pVM->cpum.s.GuestFeatures.fVmx)
3103	{
3104	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
3105	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
3106	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
3107	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
3108	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
3109	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
3110	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
3111	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
3112	0, g_aVmxHwvirtVmcs, NULL);
3113	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
3114	0, g_aVmxHwvirtVmcs, NULL);
3115	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
3116	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
3117	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
3118	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
3119	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
3120	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
3121	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
3122	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
3123	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
3124	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
3125	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
3126	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
3127	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
3128	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
3129	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
3130	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
3131	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
3132	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
3133	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
3134	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
3135	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
3136	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
3137	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
3138	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
3139	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
3140	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
3141	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
3142	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
3143	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
3144	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
3145	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
3146	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
3147	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
3148	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3)
3149	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
3150	}
3151	}
3152	}
3153	else
3154	{
3155	/*
3156	* Pre XSAVE saved state.
3157	*/
3158	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
3159	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
3160	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
3161	}
3162
3163	/*
3164	* Restore a couple of flags and the MSRs.
3165	*/
3166	uint32_t fIgnoredUsedFlags = 0;
3167	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
3168	AssertRCReturn(rc, rc);
3169	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
3170
3171	rc = VINF_SUCCESS;
3172	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
3173	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
3174	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
3175	{
3176	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
3177	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
3178	}
3179	AssertRCReturn(rc, rc);
3180
3181	/* Deal with the reusing of reserved RFLAGS bits. */
3182	pGstCtx->rflags.uBoth \|= pVM->cpum.s.fReservedRFlagsCookie;
3183
3184	/* REM and other may have cleared must-be-one fields in DR6 and
3185	DR7, fix these. */
3186	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
3187	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
3188	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
3189	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
3190	}
3191
3192	/* Older states does not have the internal selector register flags
3193	and valid selector value. Supply those. */
3194	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3195	{
3196	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3197	{
3198	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3199	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
3200	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3201	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
3202	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
3203	if (fValid)
3204	{
3205	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3206	{
3207	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
3208	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
3209	}
3210
3211	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3212	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3213	}
3214	else
3215	{
3216	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3217	{
3218	paSelReg[iSelReg].fFlags = 0;
3219	paSelReg[iSelReg].ValidSel = 0;
3220	}
3221
3222	/* This might not be 104% correct, but I think it's close
3223	enough for all practical purposes... (REM always loaded
3224	LDTR registers.) */
3225	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3226	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3227	}
3228	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
3229	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
3230	}
3231	}
3232
3233	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
3234	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3235	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3236	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3237	{
3238	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3239	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3240	}
3241
3242	/*
3243	* A quick sanity check.
3244	*/
3245	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3246	{
3247	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3248	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3249	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3250	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3251	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3252	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3253	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3254	}
3255	}
3256
3257	pVM->cpum.s.fPendingRestore = false;
3258
3259	/*
3260	* Guest CPUIDs (and VMX MSR features).
3261	*/
3262	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3263	{
3264	CPUMMSRS GuestMsrs;
3265	RT_ZERO(GuestMsrs);
3266
3267	CPUMFEATURES BaseFeatures;
3268	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3269	if (fVmxGstFeat)
3270	{
3271	/*
3272	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3273	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3274	* here so we can compare them for compatibility after exploding guest features.
3275	*/
3276	BaseFeatures = pVM->cpum.s.GuestFeatures;
3277
3278	/* Use the VMX MSR features from the saved state while exploding guest features. */
3279	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3280	}
3281
3282	/* Load CPUID and explode guest features. */
3283	rc = cpumR3LoadCpuIdX86(pVM, pSSM, uVersion, &GuestMsrs);
3284	if (fVmxGstFeat)
3285	{
3286	/*
3287	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3288	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3289	* VMX features presented to the guest.
3290	*/
3291	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3292	if (!fIsCompat)
3293	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3294	}
3295	return rc;
3296	}
3297	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3298	}
3299
3300
3301	/**
3302	* @callback_method_impl{FNSSMINTLOADDONE}
3303	*/
3304	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3305	{
3306	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3307	return VINF_SUCCESS;
3308
3309	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3310	if (pVM->cpum.s.fPendingRestore)
3311	{
3312	LogRel(("CPUM: Missing state!\n"));
3313	return VERR_INTERNAL_ERROR_2;
3314	}
3315
3316	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3317	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3318	{
3319	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3320
3321	/* Notify PGM of the NXE states in case they've changed. */
3322	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3323
3324	/* During init. this is done in CPUMR3InitCompleted(). */
3325	if (fSupportsLongMode)
3326	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3327
3328	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3329	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3330	}
3331	return VINF_SUCCESS;
3332	}
3333
3334
3335	/**
3336	* Checks if the CPUM state restore is still pending.
3337	*
3338	* @returns true / false.
3339	* @param pVM The cross context VM structure.
3340	*/
3341	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3342	{
3343	return pVM->cpum.s.fPendingRestore;
3344	}
3345
3346
3347	/**
3348	* Gets the variable-range MTRR physical address mask given an address range.
3349	*
3350	* @returns The MTRR physical address mask.
3351	* @param pVM The cross context VM structure.
3352	* @param GCPhysFirst The first guest-physical address of the memory range
3353	* (inclusive).
3354	* @param GCPhysLast The last guest-physical address of the memory range
3355	* (inclusive).
3356	*/
3357	static uint64_t cpumR3GetVarMtrrMask(PVM pVM, RTGCPHYS GCPhysFirst, RTGCPHYS GCPhysLast)
3358	{
3359	RTGCPHYS const GCPhysLength = GCPhysLast - GCPhysFirst;
3360	uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3361	RTGCPHYS const GCPhysMask = (~(GCPhysLength - 1) & ~fInvPhysMask) & X86_PAGE_BASE_MASK;
3362	#ifdef VBOX_STRICT
3363	AssertMsg(GCPhysLast == ((GCPhysFirst \| ~GCPhysMask) & ~fInvPhysMask),
3364	("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
3365	AssertMsg(((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask)),
3366	("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
3367	AssertMsg(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask),
3368	("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp\n", GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask));
3369
3370	uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
3371	AssertMsg(cbRange >= _4K, ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
3372	GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
3373	AssertMsg(RT_IS_POWER_OF_TWO(cbRange), ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
3374	GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
3375	AssertMsg(GCPhysFirst == 0 \|\| cbRange <= GCPhysFirst, ("last=%RGp first=%RGp mask=%RGp inv_mask=%RGp cb=%RU64\n",
3376	GCPhysLast, GCPhysFirst, GCPhysMask, fInvPhysMask, cbRange));
3377	#endif
3378	return GCPhysMask;
3379	}
3380
3381
3382	/**
3383	* Gets the first and last guest-physical address for the given variable-range
3384	* MTRR.
3385	*
3386	* @param pVM The cross context VM structure.
3387	* @param pMtrrVar The variable-range MTRR.
3388	* @param pGCPhysFirst Where to store the first guest-physical address of the
3389	* memory range (inclusive).
3390	* @param pGCPhysLast Where to store the last guest-physical address of the
3391	* memory range (inclusive).
3392	*/
3393	static void cpumR3GetVarMtrrAddrs(PVM pVM, PCX86MTRRVAR pMtrrVar, PRTGCPHYS pGCPhysFirst, PRTGCPHYS pGCPhysLast)
3394	{
3395	Assert(pMtrrVar);
3396	Assert(pGCPhysFirst);
3397	Assert(pGCPhysLast);
3398	uint64_t const fInvPhysMask = ~(RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U);
3399	RTGCPHYS const GCPhysMask = pMtrrVar->MtrrPhysMask & X86_PAGE_BASE_MASK;
3400	RTGCPHYS const GCPhysFirst = pMtrrVar->MtrrPhysBase & X86_PAGE_BASE_MASK;
3401	RTGCPHYS const GCPhysLast = (GCPhysFirst \| ~GCPhysMask) & ~fInvPhysMask;
3402	Assert((GCPhysLast & GCPhysMask) == (GCPhysFirst & GCPhysMask));
3403	Assert(((GCPhysLast + 1) & GCPhysMask) != (GCPhysFirst & GCPhysMask));
3404	*pGCPhysFirst = GCPhysFirst;
3405	*pGCPhysLast = GCPhysLast;
3406	}
3407
3408
3409	/**
3410	* Gets the previous power of two for a given value.
3411	*
3412	* @returns Previous power of two.
3413	* @param uVal The value (must not be zero).
3414	*/
3415	static uint64_t cpumR3GetPrevPowerOfTwo(uint64_t uVal)
3416	{
3417	Assert(uVal > 1);
3418	uint8_t const cBits = sizeof(uVal) << 3;
3419	return RT_BIT_64(cBits - 1 - ASMCountLeadingZerosU64(uVal));
3420	}
3421
3422
3423	/**
3424	* Gets the next power of two for a given value.
3425	*
3426	* @returns Next power of two.
3427	* @param uVal The value (must not be zero).
3428	*/
3429	static uint64_t cpumR3GetNextPowerOfTwo(uint64_t uVal)
3430	{
3431	Assert(uVal > 1);
3432	uint8_t const cBits = sizeof(uVal) << 3;
3433	return RT_BIT_64(cBits - ASMCountLeadingZerosU64(uVal));
3434	}
3435
3436
3437	/**
3438	* Gets the MTRR memory type description.
3439	*
3440	* @returns The MTRR memory type description.
3441	* @param fType The MTRR memory type.
3442	*/
3443	static const char *cpumR3GetVarMtrrMemType(uint8_t fType)
3444	{
3445	switch (fType)
3446	{
3447	case X86_MTRR_MT_UC: return "UC";
3448	case X86_MTRR_MT_WC: return "WC";
3449	case X86_MTRR_MT_WT: return "WT";
3450	case X86_MTRR_MT_WP: return "WP";
3451	case X86_MTRR_MT_WB: return "WB";
3452	default: return "--";
3453	}
3454	}
3455
3456
3457	/**
3458	* Adds a memory region to the given MTRR map.
3459	*
3460	* @returns VBox status code.
3461	* @retval VINF_SUCCESS when the map could accommodate a memory region being
3462	* added.
3463	* @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
3464	* memory region.
3465	*
3466	* @param pVM The cross context VM structure.
3467	* @param pMtrrMap The variable-range MTRR map to add to.
3468	* @param GCPhysFirst The first guest-physical address in the memory region.
3469	* @param GCPhysLast The last guest-physical address in the memory region.
3470	* @param fType The MTRR memory type of the memory region being added.
3471	*/
3472	static int cpumR3MtrrMapAddRegion(PVM pVM, PCPUMMTRRMAP pMtrrMap, RTGCPHYS GCPhysFirst, RTGCPHYS GCPhysLast, uint8_t fType)
3473	{
3474	Assert(fType < 7 && fType != 2 && fType != 3);
3475	if (pMtrrMap->idxMtrr < pMtrrMap->cMtrrs)
3476	{
3477	/*
3478	* We must ensure the physical-address does not exceed the maximum guest-physical address width.
3479	* Otherwise, the MTRR physical mask computation gets totally busted rather than returning 0 to
3480	* indicate such mapping is impossible.
3481	*/
3482	RTGCPHYS const GCPhysLastMax = RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth) - 1U;
3483	if (GCPhysLast <= GCPhysLastMax)
3484	{
3485	pMtrrMap->aMtrrs[pMtrrMap->idxMtrr].MtrrPhysBase = GCPhysFirst \| fType;
3486	pMtrrMap->aMtrrs[pMtrrMap->idxMtrr].MtrrPhysMask = cpumR3GetVarMtrrMask(pVM, GCPhysFirst, GCPhysLast)
3487	\| MSR_IA32_MTRR_PHYSMASK_VALID;
3488	++pMtrrMap->idxMtrr;
3489
3490	uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
3491	if (fType != X86_MTRR_MT_UC)
3492	pMtrrMap->cbMapped += cbRange;
3493	else
3494	{
3495	Assert(pMtrrMap->cbMapped >= cbRange);
3496	pMtrrMap->cbMapped -= cbRange;
3497	}
3498	return VINF_SUCCESS;
3499	}
3500	}
3501	return VERR_OUT_OF_RESOURCES;
3502	}
3503
3504
3505	/**
3506	* Adds an MTRR to the given MTRR map.
3507	*
3508	* @returns VBox status code.
3509	* @retval VINF_SUCCESS when the map could accommodate the MTRR being added.
3510	* @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
3511	* MTRR.
3512	*
3513	* @param pVM The cross context VM structure.
3514	* @param pMtrrMap The variable-range MTRR map to add to.
3515	* @param pVarMtrr The variable-range MTRR to add from.
3516	*/
3517	static int cpumR3MtrrMapAddMtrr(PVM pVM, PCPUMMTRRMAP pMtrrMap, PCX86MTRRVAR pVarMtrr)
3518	{
3519	RTGCPHYS GCPhysFirst;
3520	RTGCPHYS GCPhysLast;
3521	cpumR3GetVarMtrrAddrs(pVM, pVarMtrr, &GCPhysFirst, &GCPhysLast);
3522	uint8_t const fType = pVarMtrr->MtrrPhysBase & MSR_IA32_MTRR_PHYSBASE_MT_MASK;
3523	return cpumR3MtrrMapAddRegion(pVM, pMtrrMap, GCPhysFirst, GCPhysLast, fType);
3524	}
3525
3526
3527	/**
3528	* Adds a source MTRR map to the given destination MTRR map.
3529	*
3530	* @returns VBox status code.
3531	* @retval VINF_SUCCESS when the map could fully accommodate the map being added.
3532	* @retval VERR_OUT_OF_RESOURCES when the map ran out of room while adding the
3533	* specified map.
3534	*
3535	* @param pVM The cross context VM structure.
3536	* @param pMtrrMapDst The variable-range MTRR map to add to (destination).
3537	* @param pMtrrMapSrc The variable-range MTRR map to add from (source).
3538	*/
3539	static int cpumR3MtrrMapAddMap(PVM pVM, PCPUMMTRRMAP pMtrrMapDst, PCCPUMMTRRMAP pMtrrMapSrc)
3540	{
3541	Assert(pMtrrMapDst);
3542	Assert(pMtrrMapSrc);
3543	for (uint8_t i = 0 ; i < pMtrrMapSrc->idxMtrr; i++)
3544	{
3545	int const rc = cpumR3MtrrMapAddMtrr(pVM, pMtrrMapDst, &pMtrrMapSrc->aMtrrs[i]);
3546	if (RT_FAILURE(rc))
3547	return rc;
3548	}
3549	return VINF_SUCCESS;
3550	}
3551
3552
3553	/**
3554	* Maps memory using an additive method using variable-range MTRRs.
3555	*
3556	* The additive method fits as many valid MTRR WB (write-back) sub-regions to map
3557	* the specified memory size. For instance, 3584 MB is mapped as 2048 MB, 1024 MB
3558	* and 512 MB of WB memory, requiring 3 MTRRs.
3559	*
3560	* @returns VBox status code.
3561	* @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3562	* given number of MTRRs.
3563	* @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3564	* mapped within the given number of MTRRs.
3565	*
3566	* @param pVM The cross context VM structure.
3567	* @param GCPhysRegionFirst The guest-physical address in the region being
3568	* mapped.
3569	* @param cb The number of bytes being mapped.
3570	* @param pMtrrMap The variable-range MTRR map to populate.
3571	*/
3572	static int cpumR3MapMtrrsAdditive(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3573	{
3574	Assert(pMtrrMap);
3575	Assert(pMtrrMap->cMtrrs > 1);
3576	Assert(cb >= _4K);
3577	Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3578
3579	uint64_t cbLeft = cb;
3580	uint64_t offRegion = GCPhysRegionFirst;
3581	while (cbLeft > 0)
3582	{
3583	uint64_t const cbRegion = !RT_IS_POWER_OF_TWO(cbLeft) ? cpumR3GetPrevPowerOfTwo(cbLeft) : cbLeft;
3584
3585	Log3(("CPUM: MTRR: Add[%u]: %' Rhcb (%RU64 bytes)\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3586	int const rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion, offRegion + cbRegion - 1, X86_MTRR_MT_WB);
3587	if (RT_FAILURE(rc))
3588	return rc;
3589
3590	cbLeft -= RT_MIN(cbRegion, cbLeft);
3591	offRegion += cbRegion;
3592	}
3593	return VINF_SUCCESS;
3594	}
3595
3596
3597	/**
3598	* Maps memory using a subtractive method using variable-range MTRRs.
3599	*
3600	* The subtractive method rounds up the memory region using WB (write-back) memory
3601	* type and then "subtracts" sub-regions using UC (uncacheable) memory type. For
3602	* instance, 3584 MB is mapped as 4096 MB of WB minus 512 MB of UC, requiring 2
3603	* MTRRs.
3604	*
3605	* @returns VBox status code.
3606	* @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3607	* given number of MTRRs.
3608	* @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3609	* mapped within the given number of MTRRs.
3610	*
3611	* @param pVM The cross context VM structure.
3612	* @param GCPhysRegionFirst The guest-physical address in the region being
3613	* mapped.
3614	* @param cb The number of bytes being mapped.
3615	* @param pMtrrMap The variable-range MTRR map to populate.
3616	*/
3617	static int cpumR3MapMtrrsSubtractive(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3618	{
3619	Assert(pMtrrMap);
3620	Assert(pMtrrMap->cMtrrs > 1);
3621	Assert(cb >= _4K);
3622	Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3623
3624	uint64_t const cbRegion = !RT_IS_POWER_OF_TWO(cb) ? cpumR3GetNextPowerOfTwo(cb) : cb;
3625	Assert(cbRegion >= cb);
3626
3627	Log3(("CPUM: MTRR: Sub[%u]: %' Rhcb (%RU64 bytes) [WB]\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3628	int rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, GCPhysRegionFirst, GCPhysRegionFirst + cbRegion - 1, X86_MTRR_MT_WB);
3629	if (RT_FAILURE(rc))
3630	return rc;
3631
3632	uint64_t cbLeft = cbRegion - cb;
3633	RTGCPHYS offRegion = GCPhysRegionFirst + cbRegion;
3634	while (cbLeft > 0)
3635	{
3636	uint64_t const cbSubRegion = cpumR3GetPrevPowerOfTwo(cbLeft);
3637
3638	Log3(("CPUM: MTRR: Sub[%u]: %' Rhcb (%RU64 bytes) [UC]\n", pMtrrMap->idxMtrr, cbSubRegion, cbSubRegion));
3639	rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion - cbSubRegion, offRegion - 1, X86_MTRR_MT_UC);
3640	if (RT_FAILURE(rc))
3641	return rc;
3642
3643	cbLeft -= RT_MIN(cbSubRegion, cbLeft);
3644	offRegion -= cbSubRegion;
3645	}
3646	return rc;
3647	}
3648
3649
3650	/**
3651	* Optimally maps RAM when it's not necessarily aligned to a power of two using
3652	* variable-range MTRRs.
3653	*
3654	* @returns VBox status code.
3655	* @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3656	* given number of MTRRs.
3657	* @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3658	* mapped within the given number of MTRRs.
3659	*
3660	* @param pVM The cross context VM structure.
3661	* @param GCPhysRegionFirst The guest-physical address in the region being
3662	* mapped.
3663	* @param cb The number of bytes being mapped.
3664	* @param pMtrrMap The variable-range MTRR map to populate.
3665	*/
3666	static int cpumR3MapMtrrsOptimal(PVM pVM, RTGCPHYS GCPhysRegionFirst, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3667	{
3668	Assert(pMtrrMap);
3669	Assert(pMtrrMap->cMtrrs > 1);
3670	Assert(cb >= _4K);
3671	Assert(!(GCPhysRegionFirst & X86_PAGE_4K_OFFSET_MASK));
3672
3673	/*
3674	* Additive method.
3675	*/
3676	CPUMMTRRMAP MtrrMapAdd;
3677	RT_ZERO(MtrrMapAdd);
3678	MtrrMapAdd.cMtrrs = pMtrrMap->cMtrrs;
3679	MtrrMapAdd.cbToMap = cb;
3680	int rcAdd;
3681	{
3682	rcAdd = cpumR3MapMtrrsAdditive(pVM, GCPhysRegionFirst, cb, &MtrrMapAdd);
3683	if (RT_SUCCESS(rcAdd))
3684	{
3685	Assert(MtrrMapAdd.idxMtrr > 0);
3686	Assert(MtrrMapAdd.idxMtrr <= MtrrMapAdd.cMtrrs);
3687	Assert(MtrrMapAdd.cbMapped == MtrrMapAdd.cbToMap);
3688	Log3(("CPUM: MTRR: Mapped %u regions using additive method\n", MtrrMapAdd.idxMtrr));
3689
3690	/*
3691	* If we were able to map memory using 2 or fewer MTRRs, don't bother with trying
3692	* to map using the subtractive method as that requires at least 2 MTRRs anyway.
3693	*/
3694	if (MtrrMapAdd.idxMtrr <= 2)
3695	return cpumR3MtrrMapAddMap(pVM, pMtrrMap, &MtrrMapAdd);
3696	}
3697	else
3698	Log3(("CPUM: MTRR: Partially mapped %u regions using additive method\n", MtrrMapAdd.idxMtrr));
3699	}
3700
3701	/*
3702	* Subtractive method.
3703	*/
3704	CPUMMTRRMAP MtrrMapSub;
3705	RT_ZERO(MtrrMapSub);
3706	MtrrMapSub.cMtrrs = pMtrrMap->cMtrrs;
3707	MtrrMapSub.cbToMap = cb;
3708	int rcSub;
3709	{
3710	rcSub = cpumR3MapMtrrsSubtractive(pVM, GCPhysRegionFirst, cb, &MtrrMapSub);
3711	if (RT_SUCCESS(rcSub))
3712	{
3713	Assert(MtrrMapSub.idxMtrr > 0);
3714	Assert(MtrrMapSub.idxMtrr <= MtrrMapSub.cMtrrs);
3715	Assert(MtrrMapSub.cbMapped == MtrrMapSub.cbToMap);
3716	Log3(("CPUM: MTRR: Mapped %u regions using subtractive method\n", MtrrMapSub.idxMtrr));
3717	}
3718	else
3719	Log3(("CPUM: MTRR: Partially mapped %u regions using subtractive method\n", MtrrMapAdd.idxMtrr));
3720	}
3721
3722	/*
3723	* Pick whichever method requires fewer MTRRs to map the memory.
3724	*/
3725	PCCPUMMTRRMAP pMtrrMapOptimal;
3726	if ( RT_SUCCESS(rcAdd)
3727	&& RT_SUCCESS(rcSub))
3728	{
3729	Assert(MtrrMapAdd.cbMapped == MtrrMapSub.cbMapped);
3730	if (MtrrMapSub.idxMtrr < MtrrMapAdd.idxMtrr)
3731	pMtrrMapOptimal = &MtrrMapSub;
3732	else
3733	pMtrrMapOptimal = &MtrrMapAdd;
3734	}
3735	else if (RT_SUCCESS(rcAdd))
3736	pMtrrMapOptimal = &MtrrMapAdd;
3737	else if (RT_SUCCESS(rcSub))
3738	pMtrrMapOptimal = &MtrrMapSub;
3739	else
3740	{
3741	/*
3742	* If both methods fail, use the additive method as it gives partially mapped
3743	* memory as opposed to memory that isn't present.
3744	*/
3745	pMtrrMapOptimal = &MtrrMapAdd;
3746	}
3747
3748	int const rc = cpumR3MtrrMapAddMap(pVM, pMtrrMap, pMtrrMapOptimal);
3749	if ( RT_SUCCESS(rc)
3750	&& pMtrrMapOptimal->cbMapped == pMtrrMapOptimal->cbToMap) /* Required to distinguish full vs overflow state. */
3751	return VINF_SUCCESS;
3752	return VERR_OUT_OF_RESOURCES;
3753	}
3754
3755
3756	/**
3757	* Maps RAM above 4GB using variable-range MTRRs.
3758	*
3759	* @returns VBox status code.
3760	* @retval VINF_SUCCESS when the requested memory could be fully mapped within the
3761	* given number of MTRRs.
3762	* @retval VERR_OUT_OF_RESOURCES when the requested memory could not be fully
3763	* mapped within the given number of MTRRs.
3764	*
3765	* @param pVM The cross context VM structure.
3766	* @param cb The number of bytes above 4GB to map.
3767	* @param pMtrrMap The variable-range MTRR map to populate.
3768	*/
3769	static int cpumR3MapMtrrsAbove4GB(PVM pVM, uint64_t cb, PCPUMMTRRMAP pMtrrMap)
3770	{
3771	Assert(pMtrrMap);
3772	Assert(pMtrrMap->cMtrrs > 1);
3773	Assert(cb >= _4K);
3774
3775	/*
3776	* Map regions at incremental powers of two offsets and sizes.
3777	* Note: We cannot map an 8GB region in a 4GB offset.
3778	*/
3779	uint64_t cbLeft = cb;
3780	uint64_t offRegion = _4G;
3781	while (cbLeft > offRegion)
3782	{
3783	uint64_t const cbRegion = offRegion;
3784
3785	Log3(("CPUM: MTRR: [%u]: %' Rhcb (%RU64 bytes)\n", pMtrrMap->idxMtrr, cbRegion, cbRegion));
3786	int const rc = cpumR3MtrrMapAddRegion(pVM, pMtrrMap, offRegion, offRegion + cbRegion - 1, X86_MTRR_MT_WB);
3787	if (RT_FAILURE(rc))
3788	return rc;
3789
3790	offRegion <<= 1;
3791	cbLeft -= RT_MIN(cbRegion, cbLeft);
3792	}
3793
3794	/*
3795	* Optimally try and map any remaining memory that is smaller than
3796	* the last power of two offset (size) above.
3797	*/
3798	if (cbLeft > 0)
3799	{
3800	Assert(pMtrrMap->cMtrrs - pMtrrMap->idxMtrr > 0);
3801	return cpumR3MapMtrrsOptimal(pVM, offRegion, cbLeft, pMtrrMap);
3802	}
3803	return VINF_SUCCESS;
3804	}
3805
3806
3807	/**
3808	* Maps guest RAM via MTRRs.
3809	*
3810	* @returns VBox status code.
3811	* @param pVM The cross context VM structure.
3812	*/
3813	static int cpumR3MapMtrrs(PVM pVM)
3814	{
3815	/*
3816	* The RAM size configured for the VM does NOT include the RAM hole!
3817	* We cannot make ANY assumptions about the RAM size or the RAM hole size
3818	* of the VM since it is configurable by the user. Hence, we must check for
3819	* atypical sizes.
3820	*/
3821	uint64_t cbRam;
3822	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
3823	if (RT_FAILURE(rc))
3824	{
3825	LogRel(("CPUM: Cannot map RAM via MTRRs since the RAM size is not configured for the VM\n"));
3826	return VINF_SUCCESS;
3827	}
3828	if (!(cbRam & ~X86_PAGE_4K_BASE_MASK))
3829	{ /* likely */ }
3830	else
3831	{
3832	LogRel(("CPUM: WARNING! RAM size %u bytes is not 4K aligned, using %u bytes\n", cbRam, cbRam & X86_PAGE_4K_BASE_MASK));
3833	cbRam &= X86_PAGE_4K_BASE_MASK;
3834	}
3835
3836	/*
3837	* Map the RAM below 1MB.
3838	*/
3839	if (cbRam >= _1M)
3840	{
3841	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3842	{
3843	PCPUMCTXMSRS pCtxMsrs = &pVM->apCpusR3[idCpu]->cpum.s.GuestMsrs;
3844	pCtxMsrs->msr.MtrrFix64K_00000 = 0x0606060606060606;
3845	pCtxMsrs->msr.MtrrFix16K_80000 = 0x0606060606060606;
3846	pCtxMsrs->msr.MtrrFix16K_A0000 = 0;
3847	pCtxMsrs->msr.MtrrFix4K_C0000 = 0x0505050505050505;
3848	pCtxMsrs->msr.MtrrFix4K_C8000 = 0x0505050505050505;
3849	pCtxMsrs->msr.MtrrFix4K_D0000 = 0x0505050505050505;
3850	pCtxMsrs->msr.MtrrFix4K_D8000 = 0x0505050505050505;
3851	pCtxMsrs->msr.MtrrFix4K_E0000 = 0x0505050505050505;
3852	pCtxMsrs->msr.MtrrFix4K_E8000 = 0x0505050505050505;
3853	pCtxMsrs->msr.MtrrFix4K_F0000 = 0x0505050505050505;
3854	pCtxMsrs->msr.MtrrFix4K_F8000 = 0x0505050505050505;
3855	}
3856	LogRel(("CPUM: Mapped %' Rhcb (%RU64 bytes) of RAM using fixed-range MTRRs\n", _1M, _1M));
3857	}
3858	else
3859	{
3860	LogRel(("CPUM: WARNING! Cannot map RAM via MTRRs since the RAM size is below 1 MiB\n"));
3861	return VINF_SUCCESS;
3862	}
3863
3864	if (cbRam > _1M + _4K)
3865	{ /* likely */ }
3866	else
3867	{
3868	LogRel(("CPUM: WARNING! Cannot map RAM above 1M via MTRRs since the RAM size above 1M is below 4K\n"));
3869	return VINF_SUCCESS;
3870	}
3871
3872	/*
3873	* Check if there is at least 1 MTRR available in addition to MTRRs reserved
3874	* for use by software for mapping guest memory, see @bugref{10498#c34}.
3875	*
3876	* Intel Pentium Pro Processor's BIOS Writers Guide and our EFI code reserves
3877	* 2 MTRRs for use by software and thus we reserve the same here.
3878	*/
3879	uint8_t const cMtrrsMax = pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr.MtrrCap & MSR_IA32_MTRR_CAP_VCNT_MASK;
3880	uint8_t const cMtrrsRsvd = 2;
3881	if (cMtrrsMax < cMtrrsRsvd + 1)
3882	{
3883	LogRel(("CPUM: WARNING! Variable-range MTRRs (%u) insufficient to map RAM since %u of them are reserved for software\n",
3884	cMtrrsMax, cMtrrsRsvd));
3885	return VINF_SUCCESS;
3886	}
3887
3888	CPUMMTRRMAP MtrrMap;
3889	RT_ZERO(MtrrMap);
3890	uint8_t const cMtrrsMappable = cMtrrsMax - cMtrrsRsvd;
3891	Assert(cMtrrsMappable > 0); /* Paranoia. */
3892	AssertLogRelMsgReturn(cMtrrsMappable <= RT_ELEMENTS(MtrrMap.aMtrrs),
3893	("Mappable variable-range MTRRs (%u) exceed MTRRs available (%u)\n", cMtrrsMappable,
3894	RT_ELEMENTS(MtrrMap.aMtrrs)),
3895	VERR_CPUM_IPE_1);
3896	MtrrMap.cMtrrs = cMtrrsMappable;
3897	MtrrMap.cbToMap = cbRam;
3898
3899	/*
3900	* Get the RAM hole size configured for the VM.
3901	* Since MM has already validated it, we only debug assert the same constraints here.
3902	*
3903	* Although it is not required by the MTRR mapping code that the RAM hole size be a
3904	* power of 2, it is highly recommended to keep it this way in order to drastically
3905	* reduce the number of MTRRs used.
3906	*/
3907	uint32_t const cbRamHole = MMR3PhysGet4GBRamHoleSize(pVM);
3908	AssertMsg(cbRamHole <= 4032U * _1M, ("RAM hole size (%RU32 bytes) is too large\n", cbRamHole));
3909	AssertMsg(cbRamHole > 16 * _1M, ("RAM hole size (%RU32 bytes) is too small\n", cbRamHole));
3910	AssertMsg(!(cbRamHole & (_4M - 1)), ("RAM hole size (%RU32 bytes) must be 4MB aligned\n", cbRamHole));
3911
3912	/*
3913	* Paranoia.
3914	* Ensure the maximum physical-address width can accommodate the specified RAM size.
3915	*/
3916	RTGCPHYS const GCPhysEndMax = RT_BIT_64(pVM->cpum.s.GuestFeatures.cMaxPhysAddrWidth);
3917	RTGCPHYS const GCPhysEnd = cbRam + cbRamHole;
3918	if (GCPhysEnd <= GCPhysEndMax)
3919	{ /* likely */ }
3920	else
3921	{
3922	LogRel(("CPUM: WARNING! Cannot fully map RAM of %' Rhcb (%RU64 bytes) as it exceeds maximum physical-address (%#RX64)\n",
3923	GCPhysEnd, GCPhysEnd, GCPhysEndMax - 1));
3924	}
3925
3926	/*
3927	* Map the RAM (and RAM hole) below 4GB.
3928	*/
3929	uint64_t const cbBelow4GB = RT_MIN(cbRam, (uint64_t)_4G - cbRamHole);
3930	rc = cpumR3MapMtrrsOptimal(pVM, 0 /* GCPhysFirst */, cbBelow4GB, &MtrrMap);
3931	if (RT_SUCCESS(rc))
3932	{
3933	Assert(MtrrMap.idxMtrr > 0);
3934	Assert(MtrrMap.idxMtrr <= MtrrMap.cMtrrs);
3935	Assert(MtrrMap.cbMapped == cbBelow4GB);
3936
3937	/*
3938	* Map the RAM above 4GB.
3939	*/
3940	uint64_t const cbAbove4GB = cbRam + cbRamHole > _4G ? cbRam + cbRamHole - _4G : 0;
3941	if (cbAbove4GB)
3942	{
3943	rc = cpumR3MapMtrrsAbove4GB(pVM, cbAbove4GB, &MtrrMap);
3944	if (RT_SUCCESS(rc))
3945	Assert(MtrrMap.cbMapped == MtrrMap.cbToMap);
3946	}
3947	LogRel(("CPUM: Mapped %' Rhcb (%RU64 bytes) of RAM using %u variable-range MTRRs\n", MtrrMap.cbMapped, MtrrMap.cbMapped,
3948	MtrrMap.idxMtrr));
3949	}
3950
3951	/*
3952	* Check if we ran out of MTRRs while mapping the memory.
3953	*/
3954	if (MtrrMap.cbMapped < cbRam)
3955	{
3956	Assert(rc == VERR_OUT_OF_RESOURCES);
3957	Assert(MtrrMap.idxMtrr == cMtrrsMappable);
3958	Assert(MtrrMap.idxMtrr == MtrrMap.cMtrrs);
3959	uint64_t const cbLost = cbRam - MtrrMap.cbMapped;
3960	LogRel(("CPUM: WARNING! Could not map %' Rhcb (%RU64 bytes) of RAM using %u variable-range MTRRs\n", cbLost, cbLost,
3961	MtrrMap.cMtrrs));
3962	}
3963
3964	/*
3965	* Copy mapped MTRRs to all VCPUs.
3966	*/
3967	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3968	{
3969	PCPUMCTXMSRS pCtxMsrs = &pVM->apCpusR3[idCpu]->cpum.s.GuestMsrs;
3970	Assert(sizeof(pCtxMsrs->msr.aMtrrVarMsrs) == sizeof(MtrrMap.aMtrrs));
3971	memcpy(&pCtxMsrs->msr.aMtrrVarMsrs[0], &MtrrMap.aMtrrs[0], sizeof(MtrrMap.aMtrrs));
3972	}
3973
3974	return VINF_SUCCESS;
3975	}
3976
3977
3978	/**
3979	* Formats the EFLAGS value into mnemonics.
3980	*
3981	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3982	* @param efl The EFLAGS value with both guest hardware and VBox
3983	* internal bits included.
3984	*/
3985	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3986	{
3987	/*
3988	* Format the flags.
3989	*/
3990	static const struct
3991	{
3992	const char pszSet; const char pszClear; uint32_t fFlag;
3993	} s_aFlags[] =
3994	{
3995	{ "vip",NULL, X86_EFL_VIP },
3996	{ "vif",NULL, X86_EFL_VIF },
3997	{ "ac", NULL, X86_EFL_AC },
3998	{ "vm", NULL, X86_EFL_VM },
3999	{ "rf", NULL, X86_EFL_RF },
4000	{ "nt", NULL, X86_EFL_NT },
4001	{ "ov", "nv", X86_EFL_OF },
4002	{ "dn", "up", X86_EFL_DF },
4003	{ "ei", "di", X86_EFL_IF },
4004	{ "tf", NULL, X86_EFL_TF },
4005	{ "nt", "pl", X86_EFL_SF },
4006	{ "nz", "zr", X86_EFL_ZF },
4007	{ "ac", "na", X86_EFL_AF },
4008	{ "po", "pe", X86_EFL_PF },
4009	{ "cy", "nc", X86_EFL_CF },
4010	{ "inh-ss", NULL, CPUMCTX_INHIBIT_SHADOW_SS },
4011	{ "inh-sti", NULL, CPUMCTX_INHIBIT_SHADOW_STI },
4012	{ "inh-nmi", NULL, CPUMCTX_INHIBIT_NMI },
4013	};
4014	char *psz = pszEFlags;
4015	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
4016	{
4017	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
4018	if (pszAdd)
4019	{
4020	strcpy(psz, pszAdd);
4021	psz += strlen(pszAdd);
4022	*psz++ = ' ';
4023	}
4024	}
4025	psz[-1] = '\0';
4026	}
4027
4028
4029	/**
4030	* Formats a full register dump.
4031	*
4032	* @param pVM The cross context VM structure.
4033	* @param pVCpu The cross context virtual CPU structure.
4034	* @param pHlp Output functions.
4035	* @param enmType The dump type.
4036	* @param pszPrefix Register name prefix.
4037	*/
4038	static void cpumR3InfoOne(PVM pVM, PCVMCPU pVCpu, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
4039	{
4040	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4041
4042	/*
4043	* Format the EFLAGS.
4044	*/
4045	char szEFlags[80];
4046	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->eflags.uBoth);
4047
4048	/*
4049	* Format the registers.
4050	*/
4051	uint32_t const efl = pCtx->eflags.u;
4052	switch (enmType)
4053	{
4054	case CPUMDUMPTYPE_TERSE:
4055	if (CPUMIsGuestIn64BitCodeEx(pCtx))
4056	pHlp->pfnPrintf(pHlp,
4057	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
4058	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
4059	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
4060	"%sr14=%016RX64 %sr15=%016RX64\n"
4061	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
4062	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
4063	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
4064	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
4065	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
4066	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4067	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
4068	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
4069	else
4070	pHlp->pfnPrintf(pHlp,
4071	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
4072	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
4073	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
4074	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
4075	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4076	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
4077	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
4078	break;
4079
4080	case CPUMDUMPTYPE_DEFAULT:
4081	if (CPUMIsGuestIn64BitCodeEx(pCtx))
4082	pHlp->pfnPrintf(pHlp,
4083	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
4084	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
4085	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
4086	"%sr14=%016RX64 %sr15=%016RX64\n"
4087	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
4088	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
4089	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
4090	,
4091	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
4092	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
4093	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
4094	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4095	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
4096	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
4097	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4098	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
4099	else
4100	pHlp->pfnPrintf(pHlp,
4101	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
4102	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
4103	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
4104	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
4105	,
4106	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
4107	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4108	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
4109	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
4110	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4111	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
4112	break;
4113
4114	case CPUMDUMPTYPE_VERBOSE:
4115	if (CPUMIsGuestIn64BitCodeEx(pCtx))
4116	pHlp->pfnPrintf(pHlp,
4117	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
4118	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
4119	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
4120	"%sr14=%016RX64 %sr15=%016RX64\n"
4121	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
4122	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4123	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4124	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4125	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4126	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4127	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
4128	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
4129	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
4130	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
4131	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
4132	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4133	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4134	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
4135	,
4136	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
4137	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
4138	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
4139	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4140	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
4141	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
4142	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
4143	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
4144	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
4145	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
4146	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4147	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
4148	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
4149	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
4150	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
4151	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
4152	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
4153	else
4154	pHlp->pfnPrintf(pHlp,
4155	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
4156	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
4157	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
4158	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
4159	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
4160	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
4161	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
4162	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
4163	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
4164	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4165	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
4166	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
4167	,
4168	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
4169	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
4170	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
4171	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
4172	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
4173	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
4174	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
4175	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
4176	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
4177	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
4178	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
4179	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
4180
4181	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
4182	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
4183	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
4184	{
4185	PCX86FXSTATE pFpuCtx = &pCtx->XState.x87;
4186	pHlp->pfnPrintf(pHlp,
4187	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
4188	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
4189	,
4190	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
4191	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
4192	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
4193	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
4194	);
4195	/*
4196	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
4197	* not (FP)R0-7 as Intel SDM suggests.
4198	*/
4199	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
4200	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
4201	{
4202	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
4203	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
4204	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
4205	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
4206	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
4207	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
4208	iExponent -= 16383; /* subtract bias */
4209	/** @todo This isn't entirenly correct and needs more work! */
4210	pHlp->pfnPrintf(pHlp,
4211	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
4212	pszPrefix, iST, pszPrefix, iFPR,
4213	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
4214	uTag, chSign, iInteger, u64Fraction, iExponent);
4215	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
4216	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
4217	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
4218	else
4219	pHlp->pfnPrintf(pHlp, "\n");
4220	}
4221
4222	/* XMM/YMM/ZMM registers. */
4223	if (pCtx->fXStateMask & XSAVE_C_YMM)
4224	{
4225	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
4226	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
4227	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
4228	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
4229	pszPrefix, i, i < 10 ? " " : "",
4230	pYmmHiCtx->aYmmHi[i].au32[3],
4231	pYmmHiCtx->aYmmHi[i].au32[2],
4232	pYmmHiCtx->aYmmHi[i].au32[1],
4233	pYmmHiCtx->aYmmHi[i].au32[0],
4234	pFpuCtx->aXMM[i].au32[3],
4235	pFpuCtx->aXMM[i].au32[2],
4236	pFpuCtx->aXMM[i].au32[1],
4237	pFpuCtx->aXMM[i].au32[0]);
4238	else
4239	{
4240	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
4241	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
4242	pHlp->pfnPrintf(pHlp,
4243	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
4244	pszPrefix, i, i < 10 ? " " : "",
4245	pZmmHi256->aHi256Regs[i].au32[7],
4246	pZmmHi256->aHi256Regs[i].au32[6],
4247	pZmmHi256->aHi256Regs[i].au32[5],
4248	pZmmHi256->aHi256Regs[i].au32[4],
4249	pZmmHi256->aHi256Regs[i].au32[3],
4250	pZmmHi256->aHi256Regs[i].au32[2],
4251	pZmmHi256->aHi256Regs[i].au32[1],
4252	pZmmHi256->aHi256Regs[i].au32[0],
4253	pYmmHiCtx->aYmmHi[i].au32[3],
4254	pYmmHiCtx->aYmmHi[i].au32[2],
4255	pYmmHiCtx->aYmmHi[i].au32[1],
4256	pYmmHiCtx->aYmmHi[i].au32[0],
4257	pFpuCtx->aXMM[i].au32[3],
4258	pFpuCtx->aXMM[i].au32[2],
4259	pFpuCtx->aXMM[i].au32[1],
4260	pFpuCtx->aXMM[i].au32[0]);
4261
4262	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
4263	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
4264	pHlp->pfnPrintf(pHlp,
4265	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
4266	pszPrefix, i + 16,
4267	pZmm16Hi->aRegs[i].au32[15],
4268	pZmm16Hi->aRegs[i].au32[14],
4269	pZmm16Hi->aRegs[i].au32[13],
4270	pZmm16Hi->aRegs[i].au32[12],
4271	pZmm16Hi->aRegs[i].au32[11],
4272	pZmm16Hi->aRegs[i].au32[10],
4273	pZmm16Hi->aRegs[i].au32[9],
4274	pZmm16Hi->aRegs[i].au32[8],
4275	pZmm16Hi->aRegs[i].au32[7],
4276	pZmm16Hi->aRegs[i].au32[6],
4277	pZmm16Hi->aRegs[i].au32[5],
4278	pZmm16Hi->aRegs[i].au32[4],
4279	pZmm16Hi->aRegs[i].au32[3],
4280	pZmm16Hi->aRegs[i].au32[2],
4281	pZmm16Hi->aRegs[i].au32[1],
4282	pZmm16Hi->aRegs[i].au32[0]);
4283	}
4284	}
4285	else
4286	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
4287	pHlp->pfnPrintf(pHlp,
4288	i & 1
4289	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
4290	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
4291	pszPrefix, i, i < 10 ? " " : "",
4292	pFpuCtx->aXMM[i].au32[3],
4293	pFpuCtx->aXMM[i].au32[2],
4294	pFpuCtx->aXMM[i].au32[1],
4295	pFpuCtx->aXMM[i].au32[0]);
4296
4297	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
4298	{
4299	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
4300	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
4301	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
4302	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
4303	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
4304	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
4305	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
4306	}
4307
4308	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
4309	{
4310	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
4311	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
4312	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
4313	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
4314	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
4315	}
4316
4317	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
4318	{
4319	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
4320	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
4321	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
4322	}
4323
4324	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
4325	if (pFpuCtx->au32RsrvdRest[i])
4326	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
4327	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
4328	}
4329
4330	pHlp->pfnPrintf(pHlp,
4331	"%sEFER =%016RX64\n"
4332	"%sPAT =%016RX64\n"
4333	"%sSTAR =%016RX64\n"
4334	"%sCSTAR =%016RX64\n"
4335	"%sLSTAR =%016RX64\n"
4336	"%sSFMASK =%016RX64\n"
4337	"%sKERNELGSBASE =%016RX64\n",
4338	pszPrefix, pCtx->msrEFER,
4339	pszPrefix, pCtx->msrPAT,
4340	pszPrefix, pCtx->msrSTAR,
4341	pszPrefix, pCtx->msrCSTAR,
4342	pszPrefix, pCtx->msrLSTAR,
4343	pszPrefix, pCtx->msrSFMASK,
4344	pszPrefix, pCtx->msrKERNELGSBASE);
4345
4346	if (CPUMIsGuestInPAEModeEx(pCtx))
4347	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
4348	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
4349
4350	/*
4351	* MTRRs.
4352	*/
4353	if (pVM->cpum.s.GuestFeatures.fMtrr)
4354	{
4355	pHlp->pfnPrintf(pHlp,
4356	"%sMTRR_CAP =%016RX64\n"
4357	"%sMTRR_DEF_TYPE =%016RX64\n"
4358	"%sMTRR_FIX64K_00000 =%016RX64\n"
4359	"%sMTRR_FIX16K_80000 =%016RX64\n"
4360	"%sMTRR_FIX16K_A0000 =%016RX64\n"
4361	"%sMTRR_FIX4K_C0000 =%016RX64\n"
4362	"%sMTRR_FIX4K_C8000 =%016RX64\n"
4363	"%sMTRR_FIX4K_D0000 =%016RX64\n"
4364	"%sMTRR_FIX4K_D8000 =%016RX64\n"
4365	"%sMTRR_FIX4K_E0000 =%016RX64\n"
4366	"%sMTRR_FIX4K_E8000 =%016RX64\n"
4367	"%sMTRR_FIX4K_F0000 =%016RX64\n"
4368	"%sMTRR_FIX4K_F8000 =%016RX64\n",
4369	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrCap,
4370	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrDefType,
4371	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix64K_00000,
4372	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_80000,
4373	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix16K_A0000,
4374	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C0000,
4375	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_C8000,
4376	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D0000,
4377	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_D8000,
4378	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E0000,
4379	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_E8000,
4380	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F0000,
4381	pszPrefix, pVCpu->cpum.s.GuestMsrs.msr.MtrrFix4K_F8000);
4382
4383	for (uint8_t iRange = 0; iRange < RT_ELEMENTS(pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs); iRange++)
4384	{
4385	PCX86MTRRVAR pMtrrVar = &pVCpu->cpum.s.GuestMsrs.msr.aMtrrVarMsrs[iRange];
4386	bool const fIsValid = RT_BOOL(pMtrrVar->MtrrPhysMask & MSR_IA32_MTRR_PHYSMASK_VALID);
4387	if (fIsValid)
4388	{
4389	RTGCPHYS GCPhysFirst;
4390	RTGCPHYS GCPhysLast;
4391	cpumR3GetVarMtrrAddrs(pVM, pMtrrVar, &GCPhysFirst, &GCPhysLast);
4392	uint8_t const fType = pMtrrVar->MtrrPhysBase & MSR_IA32_MTRR_PHYSBASE_MT_MASK;
4393	const char *pszType = cpumR3GetVarMtrrMemType(fType);
4394	uint64_t const cbRange = GCPhysLast - GCPhysFirst + 1;
4395	pHlp->pfnPrintf(pHlp,
4396	"%sMTRR_PHYSBASE[%2u] =%016RX64 First=%016RX64 %6RU64 MB [%s]\n"
4397	"%sMTRR_PHYSMASK[%2u] =%016RX64 Last =%016RX64 %6RU64 MB [%RU64 MB]\n",
4398	pszPrefix, iRange, pMtrrVar->MtrrPhysBase, GCPhysFirst, GCPhysFirst / _1M, pszType,
4399	pszPrefix, iRange, pMtrrVar->MtrrPhysMask, GCPhysLast, GCPhysLast / _1M, cbRange / (uint64_t)_1M);
4400	}
4401	else
4402	pHlp->pfnPrintf(pHlp,
4403	"%sMTRR_PHYSBASE[%2u] =%016RX64\n"
4404	"%sMTRR_PHYSMASK[%2u] =%016RX64\n",
4405	pszPrefix, iRange, pMtrrVar->MtrrPhysBase,
4406	pszPrefix, iRange, pMtrrVar->MtrrPhysMask);
4407	}
4408	}
4409	break;
4410	}
4411	}
4412
4413
4414	/**
4415	* Display all cpu states and any other cpum info.
4416	*
4417	* @param pVM The cross context VM structure.
4418	* @param pHlp The info helper functions.
4419	* @param pszArgs Arguments, ignored.
4420	*/
4421	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4422	{
4423	cpumR3InfoGuest(pVM, pHlp, pszArgs);
4424	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
4425	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
4426	cpumR3InfoHyper(pVM, pHlp, pszArgs);
4427	#ifdef RT_ARCH_AMD64
4428	cpumR3InfoHost(pVM, pHlp, pszArgs);
4429	#endif
4430	}
4431
4432
4433	/**
4434	* Parses the info argument.
4435	*
4436	* The argument starts with 'verbose', 'terse' or 'default' and then
4437	* continues with the comment string.
4438	*
4439	* @param pszArgs The pointer to the argument string.
4440	* @param penmType Where to store the dump type request.
4441	* @param ppszComment Where to store the pointer to the comment string.
4442	*/
4443	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
4444	{
4445	if (!pszArgs)
4446	{
4447	*penmType = CPUMDUMPTYPE_DEFAULT;
4448	*ppszComment = "";
4449	}
4450	else
4451	{
4452	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
4453	{
4454	pszArgs += 7;
4455	*penmType = CPUMDUMPTYPE_VERBOSE;
4456	}
4457	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
4458	{
4459	pszArgs += 5;
4460	*penmType = CPUMDUMPTYPE_TERSE;
4461	}
4462	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
4463	{
4464	pszArgs += 7;
4465	*penmType = CPUMDUMPTYPE_DEFAULT;
4466	}
4467	else
4468	*penmType = CPUMDUMPTYPE_DEFAULT;
4469	*ppszComment = RTStrStripL(pszArgs);
4470	}
4471	}
4472
4473
4474	/**
4475	* Display the guest cpu state.
4476	*
4477	* @param pVM The cross context VM structure.
4478	* @param pHlp The info helper functions.
4479	* @param pszArgs Arguments.
4480	*/
4481	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4482	{
4483	CPUMDUMPTYPE enmType;
4484	const char *pszComment;
4485	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4486
4487	PCVMCPU pVCpu = VMMGetCpu(pVM);
4488	if (!pVCpu)
4489	pVCpu = pVM->apCpusR3[0];
4490
4491	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
4492
4493	cpumR3InfoOne(pVM, pVCpu, pHlp, enmType, "");
4494	}
4495
4496
4497	/**
4498	* Displays an SVM VMCB control area.
4499	*
4500	* @param pHlp The info helper functions.
4501	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
4502	* @param pszPrefix Caller specified string prefix.
4503	*/
4504	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
4505	{
4506	AssertReturnVoid(pHlp);
4507	AssertReturnVoid(pVmcbCtrl);
4508
4509	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
4510	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
4511	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
4512	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
4513	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
4514	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
4515	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
4516	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
4517	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
4518	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
4519	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
4520	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
4521	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
4522	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
4523	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
4524	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
4525	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
4526	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
4527	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
4528	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
4529	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
4530	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
4531	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
4532	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
4533	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
4534	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
4535	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
4536	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
4537	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
4538	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
4539	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
4540	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
4541	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
4542	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
4543	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
4544	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
4545	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
4546	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
4547	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
4548	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
4549	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
4550	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
4551	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
4552	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
4553	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
4554	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
4555	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
4556	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
4557	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
4558	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
4559	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
4560	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
4561	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
4562	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
4563	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
4564	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
4565	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
4566	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
4567	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
4568	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
4569	}
4570
4571
4572	/**
4573	* Helper for dumping the SVM VMCB selector registers.
4574	*
4575	* @param pHlp The info helper functions.
4576	* @param pSel Pointer to the SVM selector register.
4577	* @param pszName Name of the selector.
4578	* @param pszPrefix Caller specified string prefix.
4579	*/
4580	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
4581	{
4582	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
4583	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
4584	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
4585	}
4586
4587
4588	/**
4589	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
4590	*
4591	* @param pHlp The info helper functions.
4592	* @param pXdtr Pointer to the descriptor table register.
4593	* @param pszName Name of the descriptor table register.
4594	* @param pszPrefix Caller specified string prefix.
4595	*/
4596	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
4597	{
4598	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
4599	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
4600	}
4601
4602
4603	/**
4604	* Displays an SVM VMCB state-save area.
4605	*
4606	* @param pHlp The info helper functions.
4607	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
4608	* @param pszPrefix Caller specified string prefix.
4609	*/
4610	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
4611	{
4612	AssertReturnVoid(pHlp);
4613	AssertReturnVoid(pVmcbStateSave);
4614
4615	char szEFlags[80];
4616	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
4617
4618	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
4619	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
4620	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
4621	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
4622	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
4623	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
4624	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
4625	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
4626	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
4627	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
4628	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
4629	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
4630	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
4631	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
4632	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
4633	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
4634	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
4635	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
4636	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
4637	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
4638	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
4639	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
4640	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
4641	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
4642	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
4643	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
4644	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
4645	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
4646	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
4647	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
4648	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
4649	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
4650	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
4651	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
4652	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
4653	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
4654	}
4655
4656
4657	/**
4658	* Displays a virtual-VMCS.
4659	*
4660	* @param pVCpu The cross context virtual CPU structure.
4661	* @param pHlp The info helper functions.
4662	* @param pVmcs Pointer to a virtual VMCS.
4663	* @param pszPrefix Caller specified string prefix.
4664	*/
4665	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
4666	{
4667	AssertReturnVoid(pHlp);
4668	AssertReturnVoid(pVmcs);
4669
4670	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
4671	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4672	do { \
4673	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
4674	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
4675	} while (0)
4676
4677	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4678	do { \
4679	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
4680	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
4681	} while (0)
4682
4683	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4684	do { \
4685	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
4686	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
4687	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
4688	} while (0)
4689
4690	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
4691	do { \
4692	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
4693	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
4694	} while (0)
4695
4696	/* Header. */
4697	{
4698	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
4699	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
4700	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
4701	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
4702	}
4703
4704	/* Control fields. */
4705	{
4706	/* 16-bit. */
4707	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
4708	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
4709	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
4710	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
4711	pHlp->pfnPrintf(pHlp, " %sHLAT prefix size = %#RX16\n", pszPrefix, pVmcs->u16HlatPrefixSize);
4712
4713	/* 32-bit. */
4714	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
4715	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
4716	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
4717	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
4718	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
4719	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
4720	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
4721	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
4722	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
4723	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
4724	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
4725	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
4726	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
4727	{
4728	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
4729	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
4730	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
4731	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
4732	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
4733	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4734	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4735	}
4736	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
4737	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
4738	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
4739	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
4740	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
4741
4742	/* 64-bit. */
4743	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
4744	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
4745	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
4746	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
4747	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
4748	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
4749	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
4750	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
4751	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
4752	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
4753	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
4754	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
4755	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
4756	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
4757	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
4758	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
4759	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
4760	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
4761	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
4762	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
4763	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
4764	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
4765	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
4766	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
4767	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
4768	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
4769	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
4770	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
4771	pHlp->pfnPrintf(pHlp, " %sPCONFIG-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64PconfigExitBitmap.u);
4772	pHlp->pfnPrintf(pHlp, " %sHLAT ptr = %#RX64\n", pszPrefix, pVmcs->u64HlatPtr.u);
4773	pHlp->pfnPrintf(pHlp, " %sSecondary VM-exit controls = %#RX64\n", pszPrefix, pVmcs->u64ExitCtls2.u);
4774
4775	/* Natural width. */
4776	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
4777	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
4778	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
4779	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
4780	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
4781	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
4782	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
4783	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
4784	}
4785
4786	/* Guest state. */
4787	{
4788	char szEFlags[80];
4789	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
4790	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
4791
4792	/* 16-bit. */
4793	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
4794	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
4795	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
4796	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
4797	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
4798	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
4799	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
4800	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
4801	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4802	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4803	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
4804	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
4805
4806	/* 32-bit. */
4807	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
4808	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
4809	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
4810	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
4811	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
4812
4813	/* 64-bit. */
4814	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
4815	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
4816	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
4817	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
4818	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
4819	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
4820	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
4821	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
4822	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
4823	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
4824	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
4825	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
4826
4827	/* Natural width. */
4828	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
4829	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
4830	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
4831	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
4832	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
4833	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
4834	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
4835	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
4836	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
4837	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
4838	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
4839	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
4840	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
4841	}
4842
4843	/* Host state. */
4844	{
4845	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
4846
4847	/* 16-bit. */
4848	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
4849	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
4850	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
4851	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
4852	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
4853	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
4854	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
4855	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4856	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4857
4858	/* 32-bit. */
4859	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
4860
4861	/* 64-bit. */
4862	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
4863	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
4864	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
4865	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
4866
4867	/* Natural width. */
4868	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
4869	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
4870	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
4871	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
4872	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
4873	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
4874	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
4875	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
4876	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
4877	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
4878	}
4879
4880	/* Read-only fields. */
4881	{
4882	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
4883
4884	/* 16-bit (none currently). */
4885
4886	/* 32-bit. */
4887	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
4888	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
4889	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
4890	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
4891	{
4892	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
4893	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
4894	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
4895	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
4896	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
4897	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4898	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4899	}
4900	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
4901	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
4902	{
4903	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
4904	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
4905	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
4906	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
4907	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
4908	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
4909	}
4910	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
4911	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
4912	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
4913
4914	/* 64-bit. */
4915	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
4916
4917	/* Natural width. */
4918	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
4919	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
4920	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
4921	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
4922	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
4923	}
4924
4925	#ifdef DEBUG_ramshankar
4926	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4927	{
4928	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
4929	Assert(pvPage);
4930	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4931	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
4932	if (RT_SUCCESS(rc))
4933	{
4934	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
4935	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4936	pHlp->pfnPrintf(pHlp, "\n");
4937	}
4938	RTMemTmpFree(pvPage);
4939	}
4940	#else
4941	NOREF(pVCpu);
4942	#endif
4943
4944	#undef CPUMVMX_DUMP_HOST_XDTR
4945	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4946	#undef CPUMVMX_DUMP_GUEST_SEGREG
4947	#undef CPUMVMX_DUMP_GUEST_XDTR
4948	}
4949
4950
4951	/**
4952	* Display the guest's hardware-virtualization cpu state.
4953	*
4954	* @param pVM The cross context VM structure.
4955	* @param pHlp The info helper functions.
4956	* @param pszArgs Arguments, ignored.
4957	*/
4958	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4959	{
4960	RT_NOREF(pszArgs);
4961
4962	PVMCPU pVCpu = VMMGetCpu(pVM);
4963	if (!pVCpu)
4964	pVCpu = pVM->apCpusR3[0];
4965
4966	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4967	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4968	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4969
4970	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4971	pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4972	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4973
4974	if (fSvm)
4975	{
4976	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4977	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4978
4979	char szEFlags[80];
4980	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4981	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4982	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4983	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4984	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4985	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4986	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4987	pHlp->pfnPrintf(pHlp, " HostState:\n");
4988	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4989	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4990	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4991	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4992	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4993	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4994	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4995	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4996	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4997	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4998	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4999	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
5000	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
5001	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
5002	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
5003	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
5004	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
5005	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
5006	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
5007	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
5008	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
5009	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
5010	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
5011	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
5012	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
5013	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
5014	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
5015	}
5016	else if (fVmx)
5017	{
5018	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
5019	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
5020	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
5021	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
5022	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
5023	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
5024	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
5025	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
5026	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
5027	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
5028	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
5029	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
5030	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
5031	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
5032	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
5033	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
5034	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
5035	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
5036	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
5037	}
5038	else
5039	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
5040
5041	#undef CPUMHWVIRTDUMP_NONE
5042	#undef CPUMHWVIRTDUMP_COMMON
5043	#undef CPUMHWVIRTDUMP_SVM
5044	#undef CPUMHWVIRTDUMP_VMX
5045	#undef CPUMHWVIRTDUMP_LAST
5046	#undef CPUMHWVIRTDUMP_ALL
5047	}
5048
5049	/**
5050	* Display the current guest instruction
5051	*
5052	* @param pVM The cross context VM structure.
5053	* @param pHlp The info helper functions.
5054	* @param pszArgs Arguments, ignored.
5055	*/
5056	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5057	{
5058	NOREF(pszArgs);
5059
5060	PVMCPU pVCpu = VMMGetCpu(pVM);
5061	if (!pVCpu)
5062	pVCpu = pVM->apCpusR3[0];
5063
5064	char szInstruction[256];
5065	szInstruction[0] = '\0';
5066	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
5067	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
5068	}
5069
5070
5071	/**
5072	* Display the hypervisor cpu state.
5073	*
5074	* @param pVM The cross context VM structure.
5075	* @param pHlp The info helper functions.
5076	* @param pszArgs Arguments, ignored.
5077	*/
5078	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5079	{
5080	PVMCPU pVCpu = VMMGetCpu(pVM);
5081	if (!pVCpu)
5082	pVCpu = pVM->apCpusR3[0];
5083
5084	CPUMDUMPTYPE enmType;
5085	const char *pszComment;
5086	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
5087	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
5088
5089	pHlp->pfnPrintf(pHlp,
5090	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
5091	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
5092	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
5093	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
5094	}
5095
5096
5097	#ifdef RT_ARCH_AMD64
5098	/**
5099	* Display the host cpu state.
5100	*
5101	* @param pVM The cross context VM structure.
5102	* @param pHlp The info helper functions.
5103	* @param pszArgs Arguments, ignored.
5104	*/
5105	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
5106	{
5107	CPUMDUMPTYPE enmType;
5108	const char *pszComment;
5109	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
5110	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
5111
5112	PVMCPU pVCpu = VMMGetCpu(pVM);
5113	if (!pVCpu)
5114	pVCpu = pVM->apCpusR3[0];
5115	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
5116
5117	/*
5118	* Format the EFLAGS.
5119	*/
5120	uint64_t efl = pCtx->rflags;
5121	char szEFlags[80];
5122	cpumR3InfoFormatFlags(&szEFlags[0], efl);
5123
5124	/*
5125	* Format the registers.
5126	*/
5127	pHlp->pfnPrintf(pHlp,
5128	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
5129	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
5130	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
5131	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
5132	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
5133	"r14=%016RX64 r15=%016RX64\n"
5134	"iopl=%d %31s\n"
5135	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
5136	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
5137	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
5138	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
5139	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
5140	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
5141	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
5142	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
5143	,
5144	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
5145	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
5146	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
5147	/pCtx->r8, pCtx->r9,/ pCtx->r10,
5148	pCtx->r11, pCtx->r12, pCtx->r13,
5149	pCtx->r14, pCtx->r15,
5150	X86_EFL_GET_IOPL(efl), szEFlags,
5151	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
5152	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
5153	pCtx->cr4, pCtx->ldtr, pCtx->tr,
5154	pCtx->dr0, pCtx->dr1, pCtx->dr2,
5155	pCtx->dr3, pCtx->dr6, pCtx->dr7,
5156	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
5157	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
5158	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
5159	}
5160	#endif /* RT_ARCH_AMD64 */
5161
5162
5163	/**
5164	* Structure used when disassembling and instructions in DBGF.
5165	* This is used so the reader function can get the stuff it needs.
5166	*/
5167	typedef struct CPUMDISASSTATE
5168	{
5169	/** Pointer to the CPU structure. */
5170	PDISSTATE pDis;
5171	/** Pointer to the VM. */
5172	PVM pVM;
5173	/** Pointer to the VMCPU. */
5174	PVMCPU pVCpu;
5175	/** Pointer to the first byte in the segment. */
5176	RTGCUINTPTR GCPtrSegBase;
5177	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
5178	RTGCUINTPTR GCPtrSegEnd;
5179	/** The size of the segment minus 1. */
5180	RTGCUINTPTR cbSegLimit;
5181	/** Pointer to the current page - R3 Ptr. */
5182	void const *pvPageR3;
5183	/** Pointer to the current page - GC Ptr. */
5184	RTGCPTR pvPageGC;
5185	/** The lock information that PGMPhysReleasePageMappingLock needs. */
5186	PGMPAGEMAPLOCK PageMapLock;
5187	/** Whether the PageMapLock is valid or not. */
5188	bool fLocked;
5189	/** 64 bits mode or not. */
5190	bool f64Bits;
5191	} CPUMDISASSTATE, *PCPUMDISASSTATE;
5192
5193
5194	/**
5195	* @callback_method_impl{FNDISREADBYTES}
5196	*/
5197	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
5198	{
5199	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
5200	for (;;)
5201	{
5202	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
5203
5204	/*
5205	* Need to update the page translation?
5206	*/
5207	if ( !pState->pvPageR3
5208	\|\| (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
5209	{
5210	/* translate the address */
5211	pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
5212
5213	/* Release mapping lock previously acquired. */
5214	if (pState->fLocked)
5215	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
5216	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
5217	if (RT_SUCCESS(rc))
5218	pState->fLocked = true;
5219	else
5220	{
5221	pState->fLocked = false;
5222	pState->pvPageR3 = NULL;
5223	return rc;
5224	}
5225	}
5226
5227	/*
5228	* Check the segment limit.
5229	*/
5230	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
5231	return VERR_OUT_OF_SELECTOR_BOUNDS;
5232
5233	/*
5234	* Calc how much we can read.
5235	*/
5236	uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
5237	if (!pState->f64Bits)
5238	{
5239	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
5240	if (cb > cbSeg && cbSeg)
5241	cb = cbSeg;
5242	}
5243	if (cb > cbMaxRead)
5244	cb = cbMaxRead;
5245
5246	/*
5247	* Read and advance or exit.
5248	*/
5249	memcpy(&pDis->Instr.ab[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
5250	offInstr += (uint8_t)cb;
5251	if (cb >= cbMinRead)
5252	{
5253	pDis->cbCachedInstr = offInstr;
5254	return VINF_SUCCESS;
5255	}
5256	cbMinRead -= (uint8_t)cb;
5257	cbMaxRead -= (uint8_t)cb;
5258	}
5259	}
5260
5261
5262	/**
5263	* Disassemble an instruction and return the information in the provided structure.
5264	*
5265	* @returns VBox status code.
5266	* @param pVM The cross context VM structure.
5267	* @param pVCpu The cross context virtual CPU structure.
5268	* @param pCtx Pointer to the guest CPU context.
5269	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
5270	* @param pDis Disassembly state.
5271	* @param pszPrefix String prefix for logging (debug only).
5272	*
5273	*/
5274	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISSTATE pDis,
5275	const char *pszPrefix)
5276	{
5277	CPUMDISASSTATE State;
5278	int rc;
5279
5280	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
5281	State.pDis = pDis;
5282	State.pvPageGC = 0;
5283	State.pvPageR3 = NULL;
5284	State.pVM = pVM;
5285	State.pVCpu = pVCpu;
5286	State.fLocked = false;
5287	State.f64Bits = false;
5288
5289	/*
5290	* Get selector information.
5291	*/
5292	DISCPUMODE enmDisCpuMode;
5293	if ( (pCtx->cr0 & X86_CR0_PE)
5294	&& pCtx->eflags.Bits.u1VM == 0)
5295	{
5296	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
5297	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
5298	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
5299	State.GCPtrSegBase = pCtx->cs.u64Base;
5300	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
5301	State.cbSegLimit = pCtx->cs.u32Limit;
5302	enmDisCpuMode = (State.f64Bits)
5303	? DISCPUMODE_64BIT
5304	: pCtx->cs.Attr.n.u1DefBig
5305	? DISCPUMODE_32BIT
5306	: DISCPUMODE_16BIT;
5307	}
5308	else
5309	{
5310	/* real or V86 mode */
5311	enmDisCpuMode = DISCPUMODE_16BIT;
5312	State.GCPtrSegBase = pCtx->cs.Sel * 16;
5313	State.GCPtrSegEnd = 0xFFFFFFFF;
5314	State.cbSegLimit = 0xFFFFFFFF;
5315	}
5316
5317	/*
5318	* Disassemble the instruction.
5319	*/
5320	uint32_t cbInstr;
5321	#ifndef LOG_ENABLED
5322	RT_NOREF_PV(pszPrefix);
5323	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pDis, &cbInstr);
5324	if (RT_SUCCESS(rc))
5325	{
5326	#else
5327	char szOutput[160];
5328	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
5329	pDis, &cbInstr, szOutput, sizeof(szOutput));
5330	if (RT_SUCCESS(rc))
5331	{
5332	/* log it */
5333	if (pszPrefix)
5334	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
5335	else
5336	Log(("%s", szOutput));
5337	#endif
5338	rc = VINF_SUCCESS;
5339	}
5340	else
5341	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
5342
5343	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
5344	if (State.fLocked)
5345	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
5346
5347	return rc;
5348	}
5349
5350
5351	/**
5352	* Called when the ring-3 init phase completes.
5353	*
5354	* @returns VBox status code.
5355	* @param pVM The cross context VM structure.
5356	* @param enmWhat Which init phase.
5357	*/
5358	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
5359	{
5360	switch (enmWhat)
5361	{
5362	case VMINITCOMPLETED_RING3:
5363	{
5364	/*
5365	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
5366	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
5367	*/
5368	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
5369	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5370	{
5371	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5372
5373	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
5374	if (fSupportsLongMode)
5375	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
5376	}
5377
5378	/* Register statistic counters for MSRs. */
5379	cpumR3MsrRegStats(pVM);
5380
5381	/* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
5382	CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
5383	cpumR3CpuIdRing3InitDone(pVM);
5384
5385	/* Create VMX-preemption timer for nested guests if required. Must be
5386	done here as CPUM is initialized before TM. */
5387	if (pVM->cpum.s.GuestFeatures.fVmx)
5388	{
5389	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
5390	{
5391	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
5392	char szName[32];
5393	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
5394	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
5395	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
5396	AssertLogRelRCReturn(rc, rc);
5397	}
5398	}
5399
5400	/*
5401	* Map guest RAM via MTRRs.
5402	*/
5403	if (pVM->cpum.s.fMtrrRead)
5404	{
5405	int const rc = cpumR3MapMtrrs(pVM);
5406	if (RT_SUCCESS(rc))
5407	{ /* likely */ }
5408	else
5409	return rc;
5410	}
5411	break;
5412	}
5413
5414	default:
5415	break;
5416	}
5417	return VINF_SUCCESS;
5418	}
5419
5420
5421	/**
5422	* Called when the ring-0 init phases completed.
5423	*
5424	* @param pVM The cross context VM structure.
5425	*/
5426	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
5427	{
5428	/*
5429	* Enable log buffering as we're going to log a lot of lines.
5430	*/
5431	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
5432
5433	/*
5434	* Log the cpuid.
5435	*/
5436	RTCPUSET OnlineSet;
5437	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
5438	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
5439	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
5440	RTCPUID cCores = RTMpGetCoreCount();
5441	if (cCores)
5442	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
5443	LogRel(("*********************** CPUID dump **********************\n"));
5444	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
5445	LogRel(("\n"));
5446	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
5447	LogRel(("****************** End of CPUID dump ********************\n"));
5448
5449	#ifdef RT_ARCH_AMD64
5450	/*
5451	* Log VT-x extended features.
5452	*
5453	* SVM features are currently all covered under CPUID so there is nothing
5454	* to do here for SVM.
5455	*/
5456	if (pVM->cpum.s.HostFeatures.s.fVmx)
5457	{
5458	LogRel(("********************* VT-x features *********************\n"));
5459	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
5460	LogRel(("\n"));
5461	LogRel(("***************** End of VT-x features ******************\n"));
5462	}
5463	#endif
5464
5465	/*
5466	* Restore the log buffering state to what it was previously.
5467	*/
5468	RTLogRelSetBuffering(fOldBuffered);
5469	}
5470
5471
5472	/**
5473	* Marks the guest debug state as active.
5474	*
5475	* @param pVCpu The cross context virtual CPU structure.
5476	*
5477	* @note This is used solely by NEM (hence the name) to set the correct flags here
5478	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
5479	* The specific NEM backends have to make sure to load the correct values.
5480	*/
5481	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
5482	{
5483	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
5484	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
5485	}
5486
5487
5488	/**
5489	* Marks the hyper debug state as active.
5490	*
5491	* @param pVCpu The cross context virtual CPU structure.
5492	*
5493	* @note This is used solely by NEM (hence the name) to set the correct flags here
5494	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
5495	* The specific NEM backends have to make sure to load the correct values.
5496	*/
5497	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
5498	{
5499	/*
5500	* Make sure the hypervisor values are up to date.
5501	*/
5502	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
5503
5504	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
5505	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
5506	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 107650

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