CPUM.cpp@ 39913

Last change on this file since 39913 was 39405, checked in by vboxsync, 13 years ago
VMM: Don't use generic IPE status codes, use specific ones. Part 2.
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1	/* $Id: CPUM.cpp 39405 2011-11-23 19:30:29Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/cpumdis.h>
40	#include <VBox/vmm/pgm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/selm.h>
43	#include <VBox/vmm/dbgf.h>
44	#include <VBox/vmm/patm.h>
45	#include <VBox/vmm/hwaccm.h>
46	#include <VBox/vmm/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vmm/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include "internal/pgm.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The current saved state version. */
66	#define CPUM_SAVED_STATE_VERSION 12
67	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
68	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
69	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatibility. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detect the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers and registers with the debugger facility.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	rc = cpumR3DbgInit(pVM);
232	if (RT_FAILURE(rc))
233	return rc;
234
235	/*
236	* Initialize the Guest CPUID state.
237	*/
238	rc = cpumR3CpuIdInit(pVM);
239	if (RT_FAILURE(rc))
240	return rc;
241	CPUMR3Reset(pVM);
242	return VINF_SUCCESS;
243	}
244
245
246	/**
247	* Detect the CPU vendor give n the
248	*
249	* @returns The vendor.
250	* @param uEAX EAX from CPUID(0).
251	* @param uEBX EBX from CPUID(0).
252	* @param uECX ECX from CPUID(0).
253	* @param uEDX EDX from CPUID(0).
254	*/
255	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
256	{
257	if ( uEAX >= 1
258	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
259	&& uECX == X86_CPUID_VENDOR_AMD_ECX
260	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
261	return CPUMCPUVENDOR_AMD;
262
263	if ( uEAX >= 1
264	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
265	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
266	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
267	return CPUMCPUVENDOR_INTEL;
268
269	/** @todo detect the other buggers... */
270	return CPUMCPUVENDOR_UNKNOWN;
271	}
272
273
274	/**
275	* Fetches overrides for a CPUID leaf.
276	*
277	* @returns VBox status code.
278	* @param pLeaf The leaf to load the overrides into.
279	* @param pCfgNode The CFGM node containing the overrides
280	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
281	* @param iLeaf The CPUID leaf number.
282	*/
283	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
284	{
285	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
286	if (pLeafNode)
287	{
288	uint32_t u32;
289	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
290	if (RT_SUCCESS(rc))
291	pLeaf->eax = u32;
292	else
293	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
294
295	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
296	if (RT_SUCCESS(rc))
297	pLeaf->ebx = u32;
298	else
299	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
300
301	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
302	if (RT_SUCCESS(rc))
303	pLeaf->ecx = u32;
304	else
305	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
306
307	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
308	if (RT_SUCCESS(rc))
309	pLeaf->edx = u32;
310	else
311	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
312
313	}
314	return VINF_SUCCESS;
315	}
316
317
318	/**
319	* Load the overrides for a set of CPUID leaves.
320	*
321	* @returns VBox status code.
322	* @param paLeaves The leaf array.
323	* @param cLeaves The number of leaves.
324	* @param uStart The start leaf number.
325	* @param pCfgNode The CFGM node containing the overrides
326	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
327	*/
328	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
329	{
330	for (uint32_t i = 0; i < cLeaves; i++)
331	{
332	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
333	if (RT_FAILURE(rc))
334	return rc;
335	}
336
337	return VINF_SUCCESS;
338	}
339
340	/**
341	* Init a set of host CPUID leaves.
342	*
343	* @returns VBox status code.
344	* @param paLeaves The leaf array.
345	* @param cLeaves The number of leaves.
346	* @param uStart The start leaf number.
347	* @param pCfgNode The /CPUM/HostCPUID/ node.
348	*/
349	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
350	{
351	/* Using the ECX variant for all of them can't hurt... */
352	for (uint32_t i = 0; i < cLeaves; i++)
353	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
354
355	/* Load CPUID leaf override; we currently don't care if the user
356	specifies features the host CPU doesn't support. */
357	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
358	}
359
360
361	/**
362	* Initializes the emulated CPU's cpuid information.
363	*
364	* @returns VBox status code.
365	* @param pVM The VM to operate on.
366	*/
367	static int cpumR3CpuIdInit(PVM pVM)
368	{
369	PCPUM pCPUM = &pVM->cpum.s;
370	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
371	uint32_t i;
372	int rc;
373
374	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
375	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
376	{ \
377	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
378	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
379	}
380	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
381	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
382	{ \
383	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
384	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
385	}
386
387	/*
388	* Read the configuration.
389	*/
390	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
391	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
392	* completely overridden by VirtualBox custom strings. Some
393	* CPUID information is withheld, like the cache info. */
394	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
395	AssertRCReturn(rc, rc);
396
397	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
398	* When non-zero CPUID features that could cause portability issues will be
399	* stripped. The higher the value the more features gets stripped. Higher
400	* values should only be used when older CPUs are involved since it may
401	* harm performance and maybe also cause problems with specific guests. */
402	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
403	AssertRCReturn(rc, rc);
404
405	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
406
407	/*
408	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
409	* been overridden).
410	*/
411	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
412	* Overrides the host CPUID leaf values used for calculating the guest CPUID
413	* leaves. This can be used to preserve the CPUID values when moving a VM
414	* to a different machine. Another use is restricting (or extending) the
415	* feature set exposed to the guest. */
416	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
417	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
418	AssertRCReturn(rc, rc);
419	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
420	AssertRCReturn(rc, rc);
421	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
422	AssertRCReturn(rc, rc);
423
424	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
425	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
426
427	/*
428	* Determine the default leaf.
429	*
430	* Intel returns values of the highest standard function, while AMD
431	* returns zeros. VIA on the other hand seems to returning nothing or
432	* perhaps some random garbage, we don't try to duplicate this behavior.
433	*/
434	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
435	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
436	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
437
438
439	/* Cpuid 1 & 0x80000001:
440	* Only report features we can support.
441	*
442	* Note! When enabling new features the Synthetic CPU and Portable CPUID
443	* options may require adjusting (i.e. stripping what was enabled).
444	*/
445	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
446	\| X86_CPUID_FEATURE_EDX_VME
447	\| X86_CPUID_FEATURE_EDX_DE
448	\| X86_CPUID_FEATURE_EDX_PSE
449	\| X86_CPUID_FEATURE_EDX_TSC
450	\| X86_CPUID_FEATURE_EDX_MSR
451	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
452	\| X86_CPUID_FEATURE_EDX_MCE
453	\| X86_CPUID_FEATURE_EDX_CX8
454	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
455	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
456	//\| X86_CPUID_FEATURE_EDX_SEP
457	\| X86_CPUID_FEATURE_EDX_MTRR
458	\| X86_CPUID_FEATURE_EDX_PGE
459	\| X86_CPUID_FEATURE_EDX_MCA
460	\| X86_CPUID_FEATURE_EDX_CMOV
461	\| X86_CPUID_FEATURE_EDX_PAT
462	\| X86_CPUID_FEATURE_EDX_PSE36
463	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
464	\| X86_CPUID_FEATURE_EDX_CLFSH
465	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
466	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
467	\| X86_CPUID_FEATURE_EDX_MMX
468	\| X86_CPUID_FEATURE_EDX_FXSR
469	\| X86_CPUID_FEATURE_EDX_SSE
470	\| X86_CPUID_FEATURE_EDX_SSE2
471	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
472	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
473	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
474	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
475	\| 0;
476	pCPUM->aGuestCpuIdStd[1].ecx &= 0
477	\| X86_CPUID_FEATURE_ECX_SSE3
478	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
479	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
480	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
481	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
482	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
483	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
484	\| X86_CPUID_FEATURE_ECX_SSSE3
485	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
486	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
487	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
488	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
489	/* ECX Bit 21 - x2APIC support - not yet. */
490	// \| X86_CPUID_FEATURE_ECX_X2APIC
491	/* ECX Bit 23 - POPCNT instruction. */
492	//\| X86_CPUID_FEATURE_ECX_POPCNT
493	\| 0;
494	if (pCPUM->u8PortableCpuIdLevel > 0)
495	{
496	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
497	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
498	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
499	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
500	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
501	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
502	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
503
504	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
505	\| X86_CPUID_FEATURE_EDX_PSN
506	\| X86_CPUID_FEATURE_EDX_DS
507	\| X86_CPUID_FEATURE_EDX_ACPI
508	\| X86_CPUID_FEATURE_EDX_SS
509	\| X86_CPUID_FEATURE_EDX_TM
510	\| X86_CPUID_FEATURE_EDX_PBE
511	)));
512	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
513	\| X86_CPUID_FEATURE_ECX_DTES64
514	\| X86_CPUID_FEATURE_ECX_CPLDS
515	\| X86_CPUID_FEATURE_ECX_VMX
516	\| X86_CPUID_FEATURE_ECX_SMX
517	\| X86_CPUID_FEATURE_ECX_EST
518	\| X86_CPUID_FEATURE_ECX_TM2
519	\| X86_CPUID_FEATURE_ECX_CNTXID
520	\| X86_CPUID_FEATURE_ECX_FMA
521	\| X86_CPUID_FEATURE_ECX_CX16
522	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
523	\| X86_CPUID_FEATURE_ECX_PDCM
524	\| X86_CPUID_FEATURE_ECX_DCA
525	\| X86_CPUID_FEATURE_ECX_MOVBE
526	\| X86_CPUID_FEATURE_ECX_AES
527	\| X86_CPUID_FEATURE_ECX_POPCNT
528	\| X86_CPUID_FEATURE_ECX_XSAVE
529	\| X86_CPUID_FEATURE_ECX_OSXSAVE
530	\| X86_CPUID_FEATURE_ECX_AVX
531	)));
532	}
533
534	/* Cpuid 0x80000001:
535	* Only report features we can support.
536	*
537	* Note! When enabling new features the Synthetic CPU and Portable CPUID
538	* options may require adjusting (i.e. stripping what was enabled).
539	*
540	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
541	*/
542	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
543	\| X86_CPUID_AMD_FEATURE_EDX_VME
544	\| X86_CPUID_AMD_FEATURE_EDX_DE
545	\| X86_CPUID_AMD_FEATURE_EDX_PSE
546	\| X86_CPUID_AMD_FEATURE_EDX_TSC
547	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
548	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
549	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
550	\| X86_CPUID_AMD_FEATURE_EDX_CX8
551	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
552	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
553	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
554	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
555	\| X86_CPUID_AMD_FEATURE_EDX_PGE
556	\| X86_CPUID_AMD_FEATURE_EDX_MCA
557	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
558	\| X86_CPUID_AMD_FEATURE_EDX_PAT
559	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
560	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
561	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
562	\| X86_CPUID_AMD_FEATURE_EDX_MMX
563	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
564	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
565	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
566	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
567	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
568	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
569	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
570	\| 0;
571	pCPUM->aGuestCpuIdExt[1].ecx &= 0
572	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
573	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
574	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
575	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
576	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
577	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
578	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
579	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
580	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
581	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
582	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
583	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
584	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
585	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
586	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
587	\| 0;
588	if (pCPUM->u8PortableCpuIdLevel > 0)
589	{
590	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
591	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
592	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
593	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
594	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
595	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
596	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
597
598	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
599	\| X86_CPUID_AMD_FEATURE_ECX_SVM
600	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
601	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
602	\| X86_CPUID_AMD_FEATURE_ECX_ABM
603	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
604	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
605	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
606	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
607	\| X86_CPUID_AMD_FEATURE_ECX_IBS
608	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
609	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
610	\| X86_CPUID_AMD_FEATURE_ECX_WDT
611	\| UINT32_C(0xffffc000)
612	)));
613	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
614	\| X86_CPUID_AMD_FEATURE_EDX_SEP
615	\| RT_BIT(18)
616	\| RT_BIT(19)
617	\| RT_BIT(21)
618	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
619	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
620	\| RT_BIT(28)
621	)));
622	}
623
624	/*
625	* Apply the Synthetic CPU modifications. (TODO: move this up)
626	*/
627	if (pCPUM->fSyntheticCpu)
628	{
629	static const char s_szVendor[13] = "VirtualBox ";
630	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
631
632	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
633
634	/* Limit the nr of standard leaves; 5 for monitor/mwait */
635	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
636
637	/* 0: Vendor */
638	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
639	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
640	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
641
642	/* 1.eax: Version information. family : model : stepping */
643	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
644
645	/* Leaves 2 - 4 are Intel only - zero them out */
646	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
647	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
648	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
649
650	/* Leaf 5 = monitor/mwait */
651
652	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
653	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
654	/* AMD only - set to zero. */
655	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
656
657	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
658	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
659
660	/* 0x800000002-4: Processor Name String Identifier. */
661	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
662	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
663	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
664	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
665	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
666	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
667	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
668	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
669	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
670	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
671	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
672	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
673
674	/* 0x800000005-7 - reserved -> zero */
675	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
676	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
677	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
678
679	/* 0x800000008: only the max virtual and physical address size. */
680	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
681	}
682
683	/*
684	* Hide HTT, multicode, SMP, whatever.
685	* (APIC-ID := 0 and #LogCpus := 0)
686	*/
687	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
688	#ifdef VBOX_WITH_MULTI_CORE
689	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
690	&& pVM->cCpus > 1)
691	{
692	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
693	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
694	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
695	}
696	#endif
697
698	/* Cpuid 2:
699	* Intel: Cache and TLB information
700	* AMD: Reserved
701	* Safe to expose; restrict the number of calls to 1 for the portable case.
702	*/
703	if ( pCPUM->u8PortableCpuIdLevel > 0
704	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
705	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
706	{
707	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
708	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
709	}
710
711	/* Cpuid 3:
712	* Intel: EAX, EBX - reserved (transmeta uses these)
713	* ECX, EDX - Processor Serial Number if available, otherwise reserved
714	* AMD: Reserved
715	* Safe to expose
716	*/
717	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
718	{
719	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
720	if (pCPUM->u8PortableCpuIdLevel > 0)
721	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
722	}
723
724	/* Cpuid 4:
725	* Intel: Deterministic Cache Parameters Leaf
726	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
727	* AMD: Reserved
728	* Safe to expose, except for EAX:
729	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
730	* Bits 31-26: Maximum number of processor cores in this physical package**
731	* Note: These SMP values are constant regardless of ECX
732	*/
733	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
734	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
735	#ifdef VBOX_WITH_MULTI_CORE
736	if ( pVM->cCpus > 1
737	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
738	{
739	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
740	/* One logical processor with possibly multiple cores. */
741	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
742	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
743	}
744	#endif
745
746	/* Cpuid 5: Monitor/mwait Leaf
747	* Intel: ECX, EDX - reserved
748	* EAX, EBX - Smallest and largest monitor line size
749	* AMD: EDX - reserved
750	* EAX, EBX - Smallest and largest monitor line size
751	* ECX - extensions (ignored for now)
752	* Safe to expose
753	*/
754	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
755	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
756
757	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
758	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
759	* Expose MWAIT extended features to the guest. For now we expose
760	* just MWAIT break on interrupt feature (bit 1).
761	*/
762	bool fMWaitExtensions;
763	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
764	if (fMWaitExtensions)
765	{
766	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
767	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
768	it shall be part of our power management virtualization model */
769	#if 0
770	/* MWAIT sub C-states */
771	pCPUM->aGuestCpuIdStd[5].edx =
772	(0 << 0) /* 0 in C0 */ \|
773	(2 << 4) /* 2 in C1 */ \|
774	(2 << 8) /* 2 in C2 */ \|
775	(2 << 12) /* 2 in C3 */ \|
776	(0 << 16) /* 0 in C4 */
777	;
778	#endif
779	}
780	else
781	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
782
783	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
784	* Safe to pass on to the guest.
785	*
786	* Intel: 0x800000005 reserved
787	* 0x800000006 L2 cache information
788	* AMD: 0x800000005 L1 cache information
789	* 0x800000006 L2/L3 cache information
790	*/
791
792	/* Cpuid 0x800000007:
793	* AMD: EAX, EBX, ECX - reserved
794	* EDX: Advanced Power Management Information
795	* Intel: Reserved
796	*/
797	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
798	{
799	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
800
801	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
802
803	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
804	{
805	/* Only expose the TSC invariant capability bit to the guest. */
806	pCPUM->aGuestCpuIdExt[7].edx &= 0
807	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
808	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
809	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
810	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
811	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
812	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
813	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
814	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
815	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
816	* Linux kernels blindly assume that the AMD performance counters work
817	* if this is set for 64 bits guests. (Can't really find a CPUID feature
818	* bit for them though.) */
819	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
820	#endif
821	\| 0;
822	}
823	else
824	pCPUM->aGuestCpuIdExt[7].edx = 0;
825	}
826
827	/* Cpuid 0x800000008:
828	* AMD: EBX, EDX - reserved
829	* EAX: Virtual/Physical/Guest address Size
830	* ECX: Number of cores + APICIdCoreIdSize
831	* Intel: EAX: Virtual/Physical address Size
832	* EBX, ECX, EDX - reserved
833	*/
834	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
835	{
836	/* Only expose the virtual and physical address sizes to the guest. */
837	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
838	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
839	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
840	* NC (0-7) Number of cores; 0 equals 1 core */
841	pCPUM->aGuestCpuIdExt[8].ecx = 0;
842	#ifdef VBOX_WITH_MULTI_CORE
843	if ( pVM->cCpus > 1
844	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
845	{
846	/* Legacy method to determine the number of cores. */
847	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
848	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
849	}
850	#endif
851	}
852
853	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
854	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
855	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
856	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
857	*/
858	bool fNt4LeafLimit;
859	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
860	if (fNt4LeafLimit)
861	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
862
863	/*
864	* Limit it the number of entries and fill the remaining with the defaults.
865	*
866	* The limits are masking off stuff about power saving and similar, this
867	* is perhaps a bit crudely done as there is probably some relatively harmless
868	* info too in these leaves (like words about having a constant TSC).
869	*/
870	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
871	pCPUM->aGuestCpuIdStd[0].eax = 5;
872	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
873	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
874
875	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
876	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
877	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
878	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
879	: 0;
880	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
881	i++)
882	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
883
884	/*
885	* Centaur stuff (VIA).
886	*
887	* The important part here (we think) is to make sure the 0xc0000000
888	* function returns 0xc0000001. As for the features, we don't currently
889	* let on about any of those... 0xc0000002 seems to be some
890	* temperature/hz/++ stuff, include it as well (static).
891	*/
892	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
893	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
894	{
895	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
896	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
897	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
898	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
899	i++)
900	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
901	}
902	else
903	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
904	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
905
906
907	/*
908	* Load CPUID overrides from configuration.
909	* Note: Kind of redundant now, but allows unchanged overrides
910	*/
911	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
912	* Overrides the CPUID leaf values. */
913	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
914	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
915	AssertRCReturn(rc, rc);
916	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
917	AssertRCReturn(rc, rc);
918	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
919	AssertRCReturn(rc, rc);
920
921	/*
922	* Check if PAE was explicitely enabled by the user.
923	*/
924	bool fEnable;
925	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
926	if (fEnable)
927	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
928
929	/*
930	* We don't normally enable NX for raw-mode, so give the user a chance to
931	* force it on.
932	*/
933	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
934	if (fEnable)
935	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
936
937	/*
938	* We don't enable the Hypervisor Present bit by default, but it may
939	* be needed by some guests.
940	*/
941	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
942	if (fEnable)
943	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
944	/*
945	* Log the cpuid and we're good.
946	*/
947	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
948	RTCPUSET OnlineSet;
949	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
950	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
951	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
952	LogRel(("*********************** CPUID dump **********************\n"));
953	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
954	LogRel(("\n"));
955	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
956	RTLogRelSetBuffering(fOldBuffered);
957	LogRel(("****************** End of CPUID dump ********************\n"));
958
959	#undef PORTABLE_DISABLE_FEATURE_BIT
960	#undef PORTABLE_CLEAR_BITS_WHEN
961
962	return VINF_SUCCESS;
963	}
964
965
966	/**
967	* Applies relocations to data and code managed by this
968	* component. This function will be called at init and
969	* whenever the VMM need to relocate it self inside the GC.
970	*
971	* The CPUM will update the addresses used by the switcher.
972	*
973	* @param pVM The VM.
974	*/
975	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
976	{
977	LogFlow(("CPUMR3Relocate\n"));
978	for (VMCPUID i = 0; i < pVM->cCpus; i++)
979	{
980	/*
981	* Switcher pointers.
982	*/
983	PVMCPU pVCpu = &pVM->aCpus[i];
984	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
985	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
986
987	}
988	}
989
990
991	/**
992	* Apply late CPUM property changes based on the fHWVirtEx setting
993	*
994	* @param pVM The VM to operate on.
995	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
996	*/
997	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
998	{
999	/*
1000	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1001	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1002	* of processors from (cpuid(4).eax >> 26) + 1.
1003	*
1004	* Note: this code is obsolete, but let's keep it here for reference.
1005	* Purpose is valid when we artificially cap the max std id to less than 4.
1006	*/
1007	if (!fHWVirtExEnabled)
1008	{
1009	Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1010	\|\| pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1011	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1012	}
1013	}
1014
1015	/**
1016	* Terminates the CPUM.
1017	*
1018	* Termination means cleaning up and freeing all resources,
1019	* the VM it self is at this point powered off or suspended.
1020	*
1021	* @returns VBox status code.
1022	* @param pVM The VM to operate on.
1023	*/
1024	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1025	{
1026	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1027	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1028	{
1029	PVMCPU pVCpu = &pVM->aCpus[i];
1030	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1031
1032	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1033	pVCpu->cpum.s.uMagic = 0;
1034	pCtx->dr[5] = 0;
1035	}
1036	#else
1037	NOREF(pVM);
1038	#endif
1039	return VINF_SUCCESS;
1040	}
1041
1042
1043	/**
1044	* Resets a virtual CPU.
1045	*
1046	* Used by CPUMR3Reset and CPU hot plugging.
1047	*
1048	* @param pVCpu The virtual CPU handle.
1049	*/
1050	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1051	{
1052	/** @todo anything different for VCPU > 0? */
1053	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1054
1055	/*
1056	* Initialize everything to ZERO first.
1057	*/
1058	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1059	memset(pCtx, 0, sizeof(*pCtx));
1060	pVCpu->cpum.s.fUseFlags = fUseFlags;
1061
1062	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1063	pCtx->eip = 0x0000fff0;
1064	pCtx->edx = 0x00000600; /* P6 processor */
1065	pCtx->eflags.Bits.u1Reserved0 = 1;
1066
1067	pCtx->cs = 0xf000;
1068	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1069	pCtx->csHid.u32Limit = 0x0000ffff;
1070	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1071	pCtx->csHid.Attr.n.u1Present = 1;
1072	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1073
1074	pCtx->dsHid.u32Limit = 0x0000ffff;
1075	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1076	pCtx->dsHid.Attr.n.u1Present = 1;
1077	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1078
1079	pCtx->esHid.u32Limit = 0x0000ffff;
1080	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1081	pCtx->esHid.Attr.n.u1Present = 1;
1082	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1083
1084	pCtx->fsHid.u32Limit = 0x0000ffff;
1085	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1086	pCtx->fsHid.Attr.n.u1Present = 1;
1087	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1088
1089	pCtx->gsHid.u32Limit = 0x0000ffff;
1090	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1091	pCtx->gsHid.Attr.n.u1Present = 1;
1092	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1093
1094	pCtx->ssHid.u32Limit = 0x0000ffff;
1095	pCtx->ssHid.Attr.n.u1Present = 1;
1096	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1097	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1098
1099	pCtx->idtr.cbIdt = 0xffff;
1100	pCtx->gdtr.cbGdt = 0xffff;
1101
1102	pCtx->ldtrHid.u32Limit = 0xffff;
1103	pCtx->ldtrHid.Attr.n.u1Present = 1;
1104	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1105
1106	pCtx->trHid.u32Limit = 0xffff;
1107	pCtx->trHid.Attr.n.u1Present = 1;
1108	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1109
1110	pCtx->dr[6] = X86_DR6_INIT_VAL;
1111	pCtx->dr[7] = X86_DR7_INIT_VAL;
1112
1113	pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1114	pCtx->fpu.FCW = 0x37f;
1115
1116	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
1117	pCtx->fpu.MXCSR = 0x1F80;
1118
1119	/* Init PAT MSR */
1120	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1121
1122	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1123	* The Intel docs don't mention it.
1124	*/
1125	pCtx->msrEFER = 0;
1126	}
1127
1128
1129	/**
1130	* Resets the CPU.
1131	*
1132	* @returns VINF_SUCCESS.
1133	* @param pVM The VM handle.
1134	*/
1135	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1136	{
1137	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1138	{
1139	CPUMR3ResetCpu(&pVM->aCpus[i]);
1140
1141	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1142	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1143
1144	/* Magic marker for searching in crash dumps. */
1145	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1146	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1147	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1148	#endif
1149	}
1150	}
1151
1152
1153	/**
1154	* Called both in pass 0 and the final pass.
1155	*
1156	* @param pVM The VM handle.
1157	* @param pSSM The saved state handle.
1158	*/
1159	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1160	{
1161	/*
1162	* Save all the CPU ID leaves here so we can check them for compatibility
1163	* upon loading.
1164	*/
1165	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1166	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1167
1168	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1169	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1170
1171	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1172	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1173
1174	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1175
1176	/*
1177	* Save a good portion of the raw CPU IDs as well as they may come in
1178	* handy when validating features for raw mode.
1179	*/
1180	CPUMCPUID aRawStd[16];
1181	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1182	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1183	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1184	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1185
1186	CPUMCPUID aRawExt[32];
1187	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1188	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1189	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1190	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1191	}
1192
1193
1194	/**
1195	* Loads the CPU ID leaves saved by pass 0.
1196	*
1197	* @returns VBox status code.
1198	* @param pVM The VM handle.
1199	* @param pSSM The saved state handle.
1200	* @param uVersion The format version.
1201	*/
1202	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1203	{
1204	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1205
1206	/*
1207	* Define a bunch of macros for simplifying the code.
1208	*/
1209	/* Generic expression + failure message. */
1210	#define CPUID_CHECK_RET(expr, fmt) \
1211	do { \
1212	if (!(expr)) \
1213	{ \
1214	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
1215	if (fStrictCpuIdChecks) \
1216	{ \
1217	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1218	RTStrFree(pszMsg); \
1219	return rcCpuid; \
1220	} \
1221	LogRel(("CPUM: %s\n", pszMsg)); \
1222	RTStrFree(pszMsg); \
1223	} \
1224	} while (0)
1225	#define CPUID_CHECK_WRN(expr, fmt) \
1226	do { \
1227	if (!(expr)) \
1228	LogRel(fmt); \
1229	} while (0)
1230
1231	/* For comparing two values and bitch if they differs. */
1232	#define CPUID_CHECK2_RET(what, host, saved) \
1233	do { \
1234	if ((host) != (saved)) \
1235	{ \
1236	if (fStrictCpuIdChecks) \
1237	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1238	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1239	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1240	} \
1241	} while (0)
1242	#define CPUID_CHECK2_WRN(what, host, saved) \
1243	do { \
1244	if ((host) != (saved)) \
1245	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1246	} while (0)
1247
1248	/* For checking raw cpu features (raw mode). */
1249	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1250	do { \
1251	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1252	{ \
1253	if (fStrictCpuIdChecks) \
1254	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1255	N_(#bit " mismatch: host=%d saved=%d"), \
1256	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1257	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1258	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1259	} \
1260	} while (0)
1261	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1262	do { \
1263	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1264	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1265	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1266	} while (0)
1267	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1268
1269	/* For checking guest features. */
1270	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1271	do { \
1272	if ( (aGuestCpuId##set [1].reg & bit) \
1273	&& !(aHostRaw##set [1].reg & bit) \
1274	&& !(aHostOverride##set [1].reg & bit) \
1275	&& !(aGuestOverride##set [1].reg & bit) \
1276	) \
1277	{ \
1278	if (fStrictCpuIdChecks) \
1279	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1280	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1281	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1282	} \
1283	} while (0)
1284	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1285	do { \
1286	if ( (aGuestCpuId##set [1].reg & bit) \
1287	&& !(aHostRaw##set [1].reg & bit) \
1288	&& !(aHostOverride##set [1].reg & bit) \
1289	&& !(aGuestOverride##set [1].reg & bit) \
1290	) \
1291	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1292	} while (0)
1293	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1294	do { \
1295	if ( (aGuestCpuId##set [1].reg & bit) \
1296	&& !(aHostRaw##set [1].reg & bit) \
1297	&& !(aHostOverride##set [1].reg & bit) \
1298	&& !(aGuestOverride##set [1].reg & bit) \
1299	) \
1300	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1301	} while (0)
1302	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1303
1304	/* For checking guest features if AMD guest CPU. */
1305	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1306	do { \
1307	if ( (aGuestCpuId##set [1].reg & bit) \
1308	&& fGuestAmd \
1309	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1310	&& !(aHostOverride##set [1].reg & bit) \
1311	&& !(aGuestOverride##set [1].reg & bit) \
1312	) \
1313	{ \
1314	if (fStrictCpuIdChecks) \
1315	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1316	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1317	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1318	} \
1319	} while (0)
1320	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1321	do { \
1322	if ( (aGuestCpuId##set [1].reg & bit) \
1323	&& fGuestAmd \
1324	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1325	&& !(aHostOverride##set [1].reg & bit) \
1326	&& !(aGuestOverride##set [1].reg & bit) \
1327	) \
1328	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1329	} while (0)
1330	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1331	do { \
1332	if ( (aGuestCpuId##set [1].reg & bit) \
1333	&& fGuestAmd \
1334	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1335	&& !(aHostOverride##set [1].reg & bit) \
1336	&& !(aGuestOverride##set [1].reg & bit) \
1337	) \
1338	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1339	} while (0)
1340	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1341
1342	/* For checking AMD features which have a corresponding bit in the standard
1343	range. (Intel defines very few bits in the extended feature sets.) */
1344	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1345	do { \
1346	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1347	&& !(fHostAmd \
1348	? aHostRawExt[1].reg & (ExtBit) \
1349	: aHostRawStd[1].reg & (StdBit)) \
1350	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1351	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1352	) \
1353	{ \
1354	if (fStrictCpuIdChecks) \
1355	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1356	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1357	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1358	} \
1359	} while (0)
1360	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1361	do { \
1362	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1363	&& !(fHostAmd \
1364	? aHostRawExt[1].reg & (ExtBit) \
1365	: aHostRawStd[1].reg & (StdBit)) \
1366	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1367	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1368	) \
1369	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1370	} while (0)
1371	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1372	do { \
1373	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1374	&& !(fHostAmd \
1375	? aHostRawExt[1].reg & (ExtBit) \
1376	: aHostRawStd[1].reg & (StdBit)) \
1377	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1378	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1379	) \
1380	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1381	} while (0)
1382	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1383
1384	/*
1385	* Load them into stack buffers first.
1386	*/
1387	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1388	uint32_t cGuestCpuIdStd;
1389	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1390	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1391	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1392	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1393
1394	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1395	uint32_t cGuestCpuIdExt;
1396	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1397	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1398	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1399	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1400
1401	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1402	uint32_t cGuestCpuIdCentaur;
1403	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1404	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1405	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1406	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1407
1408	CPUMCPUID GuestCpuIdDef;
1409	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1410	AssertRCReturn(rc, rc);
1411
1412	CPUMCPUID aRawStd[16];
1413	uint32_t cRawStd;
1414	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1415	if (cRawStd > RT_ELEMENTS(aRawStd))
1416	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1417	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1418
1419	CPUMCPUID aRawExt[32];
1420	uint32_t cRawExt;
1421	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1422	if (cRawExt > RT_ELEMENTS(aRawExt))
1423	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1424	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1425	AssertRCReturn(rc, rc);
1426
1427	/*
1428	* Note that we support restoring less than the current amount of standard
1429	* leaves because we've been allowed more is newer version of VBox.
1430	*
1431	* So, pad new entries with the default.
1432	*/
1433	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1434	aGuestCpuIdStd[i] = GuestCpuIdDef;
1435
1436	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1437	aGuestCpuIdExt[i] = GuestCpuIdDef;
1438
1439	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1440	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1441
1442	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1443	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1444
1445	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1446	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1447
1448	/*
1449	* Get the raw CPU IDs for the current host.
1450	*/
1451	CPUMCPUID aHostRawStd[16];
1452	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1453	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1454
1455	CPUMCPUID aHostRawExt[32];
1456	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1457	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1458
1459	/*
1460	* Get the host and guest overrides so we don't reject the state because
1461	* some feature was enabled thru these interfaces.
1462	* Note! We currently only need the feature leaves, so skip rest.
1463	*/
1464	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1465	CPUMCPUID aGuestOverrideStd[2];
1466	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1467	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1468
1469	CPUMCPUID aGuestOverrideExt[2];
1470	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1471	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1472
1473	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1474	CPUMCPUID aHostOverrideStd[2];
1475	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1476	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1477
1478	CPUMCPUID aHostOverrideExt[2];
1479	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1480	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1481
1482	/*
1483	* This can be skipped.
1484	*/
1485	bool fStrictCpuIdChecks;
1486	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1487
1488
1489
1490	/*
1491	* For raw-mode we'll require that the CPUs are very similar since we don't
1492	* intercept CPUID instructions for user mode applications.
1493	*/
1494	if (!HWACCMIsEnabled(pVM))
1495	{
1496	/* CPUID(0) */
1497	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1498	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1499	&& aHostRawStd[0].edx == aRawStd[0].edx,
1500	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1501	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1502	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1503	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1504	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1505	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1506
1507	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1508
1509	/* CPUID(1).eax */
1510	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1511	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1512	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1513
1514	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1515	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1516	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1517
1518	/* CPUID(1).ecx */
1519	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1520	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1521	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1522	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1523	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1524	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1525	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1526	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1527	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1528	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1529	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1530	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1531	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1532	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1533	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1534	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1535	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1536	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1537	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1538	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1539	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1540	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1541	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1542	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1543	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1544	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1545	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1546	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1547	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1548	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1549	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1550	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1551
1552	/* CPUID(1).edx */
1553	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1554	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1555	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1556	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1557	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1558	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1559	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1560	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1561	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1562	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1563	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1564	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1565	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1566	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1567	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1568	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1569	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1570	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1571	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1572	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1573	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1574	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1575	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1576	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1577	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1578	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1579	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1580	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1581	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1582	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1583	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1584	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1585
1586	/* CPUID(2) - config, mostly about caches. ignore. */
1587	/* CPUID(3) - processor serial number. ignore. */
1588	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1589	/* CPUID(5) - mwait/monitor config. ignore. */
1590	/* CPUID(6) - power management. ignore. */
1591	/* CPUID(7) - ???. ignore. */
1592	/* CPUID(8) - ???. ignore. */
1593	/* CPUID(9) - DCA. ignore for now. */
1594	/* CPUID(a) - PeMo info. ignore for now. */
1595	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1596
1597	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1598	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1599	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1600	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1601	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1602	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1603	{
1604	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1605	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1606	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1607	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1608	}
1609
1610	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1611	Note! Intel have/is marking many of the fields here as reserved. We
1612	will verify them as if it's an AMD CPU. */
1613	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1614	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1615	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1616	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1617	{
1618	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1619	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1620	&& aHostRawExt[0].edx == aRawExt[0].edx,
1621	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1622	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1623	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1624	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1625
1626	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1627	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1628	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1629	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1630	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1631	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1632
1633	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1634	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1635	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1636	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1637
1638	/* CPUID(0x80000001).ecx */
1639	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1640	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1641	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1642	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1643	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1644	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1645	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1646	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1647	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1648	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1649	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1650	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1651	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1652	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1653	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1654	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1655	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1656	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1657	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1658	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1659	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1660	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1661	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1662	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1663	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1664	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1665	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1666	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1667	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1668	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1669	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1670	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1671
1672	/* CPUID(0x80000001).edx */
1673	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1674	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1675	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1676	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1677	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1678	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1679	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1680	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1681	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1682	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1683	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1684	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1685	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1686	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1687	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1688	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1689	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1690	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1691	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1692	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1693	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1694	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1695	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1696	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1697	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1698	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1699	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1700	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1701	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1702	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1703	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1704	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1705
1706	/** @todo verify the rest as well. */
1707	}
1708	}
1709
1710
1711
1712	/*
1713	* Verify that we can support the features already exposed to the guest on
1714	* this host.
1715	*
1716	* Most of the features we're emulating requires intercepting instruction
1717	* and doing it the slow way, so there is no need to warn when they aren't
1718	* present in the host CPU. Thus we use IGN instead of EMU on these.
1719	*
1720	* Trailing comments:
1721	* "EMU" - Possible to emulate, could be lots of work and very slow.
1722	* "EMU?" - Can this be emulated?
1723	*/
1724	/* CPUID(1).ecx */
1725	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1726	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1727	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1728	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1729	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1730	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1731	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1732	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1733	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1734	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1735	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1736	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1739	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1740	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1741	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1742	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1743	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1744	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1745	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1746	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1747	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1748	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1749	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1750	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1751	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1752	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1753	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1754	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1755	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1756	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1757
1758	/* CPUID(1).edx */
1759	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1760	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1761	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1762	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1763	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1764	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1765	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1766	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1767	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1768	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1769	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1770	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1771	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1772	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1773	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1774	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1775	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1776	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1777	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1778	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1779	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1780	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1781	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1782	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1783	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1784	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1785	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1786	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1787	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1788	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1789	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1790	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1791
1792	/* CPUID(0x80000000). */
1793	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1794	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1795	{
1796	/** @todo deal with no 0x80000001 on the host. */
1797	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1798	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1799
1800	/* CPUID(0x80000001).ecx */
1801	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1802	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1803	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1804	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1805	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1806	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1807	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1808	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1809	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1810	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1811	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1812	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1813	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1814	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1815	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1816	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1817	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1818	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1819	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1820	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1821	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1822	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1823	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1824	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1825	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1826	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1827	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1828	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1829	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1831	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1832	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1833
1834	/* CPUID(0x80000001).edx */
1835	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1836	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1837	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1838	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1839	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1840	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1841	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1842	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1843	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1844	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1845	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1846	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1847	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1848	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1849	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1850	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1851	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1852	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1853	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1854	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1855	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1856	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1857	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1858	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1859	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1860	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1861	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1862	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1863	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1864	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1865	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1866	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1867	}
1868
1869	/*
1870	* We're good, commit the CPU ID leaves.
1871	*/
1872	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1873	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1874	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1875	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1876
1877	#undef CPUID_CHECK_RET
1878	#undef CPUID_CHECK_WRN
1879	#undef CPUID_CHECK2_RET
1880	#undef CPUID_CHECK2_WRN
1881	#undef CPUID_RAW_FEATURE_RET
1882	#undef CPUID_RAW_FEATURE_WRN
1883	#undef CPUID_RAW_FEATURE_IGN
1884	#undef CPUID_GST_FEATURE_RET
1885	#undef CPUID_GST_FEATURE_WRN
1886	#undef CPUID_GST_FEATURE_EMU
1887	#undef CPUID_GST_FEATURE_IGN
1888	#undef CPUID_GST_FEATURE2_RET
1889	#undef CPUID_GST_FEATURE2_WRN
1890	#undef CPUID_GST_FEATURE2_EMU
1891	#undef CPUID_GST_FEATURE2_IGN
1892	#undef CPUID_GST_AMD_FEATURE_RET
1893	#undef CPUID_GST_AMD_FEATURE_WRN
1894	#undef CPUID_GST_AMD_FEATURE_EMU
1895	#undef CPUID_GST_AMD_FEATURE_IGN
1896
1897	return VINF_SUCCESS;
1898	}
1899
1900
1901	/**
1902	* Pass 0 live exec callback.
1903	*
1904	* @returns VINF_SSM_DONT_CALL_AGAIN.
1905	* @param pVM The VM handle.
1906	* @param pSSM The saved state handle.
1907	* @param uPass The pass (0).
1908	*/
1909	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1910	{
1911	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1912	cpumR3SaveCpuId(pVM, pSSM);
1913	return VINF_SSM_DONT_CALL_AGAIN;
1914	}
1915
1916
1917	/**
1918	* Execute state save operation.
1919	*
1920	* @returns VBox status code.
1921	* @param pVM VM Handle.
1922	* @param pSSM SSM operation handle.
1923	*/
1924	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1925	{
1926	/*
1927	* Save.
1928	*/
1929	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1930	{
1931	PVMCPU pVCpu = &pVM->aCpus[i];
1932
1933	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1934	}
1935
1936	SSMR3PutU32(pSSM, pVM->cCpus);
1937	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1938	{
1939	PVMCPU pVCpu = &pVM->aCpus[i];
1940
1941	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1942	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1943	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1944	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1945	}
1946
1947	cpumR3SaveCpuId(pVM, pSSM);
1948	return VINF_SUCCESS;
1949	}
1950
1951
1952	/**
1953	* Load a version 1.6 CPUMCTX structure.
1954	*
1955	* @returns VBox status code.
1956	* @param pVM VM Handle.
1957	* @param pCpumctx16 Version 1.6 CPUMCTX
1958	*/
1959	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1960	{
1961	#define CPUMCTX16_LOADREG(RegName) \
1962	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1963
1964	#define CPUMCTX16_LOADDRXREG(RegName) \
1965	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1966
1967	#define CPUMCTX16_LOADHIDREG(RegName) \
1968	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1969	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1970	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1971
1972	#define CPUMCTX16_LOADSEGREG(RegName) \
1973	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1974	CPUMCTX16_LOADHIDREG(RegName);
1975
1976	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1977
1978	CPUMCTX16_LOADREG(rax);
1979	CPUMCTX16_LOADREG(rbx);
1980	CPUMCTX16_LOADREG(rcx);
1981	CPUMCTX16_LOADREG(rdx);
1982	CPUMCTX16_LOADREG(rdi);
1983	CPUMCTX16_LOADREG(rsi);
1984	CPUMCTX16_LOADREG(rbp);
1985	CPUMCTX16_LOADREG(esp);
1986	CPUMCTX16_LOADREG(rip);
1987	CPUMCTX16_LOADREG(rflags);
1988
1989	CPUMCTX16_LOADSEGREG(cs);
1990	CPUMCTX16_LOADSEGREG(ds);
1991	CPUMCTX16_LOADSEGREG(es);
1992	CPUMCTX16_LOADSEGREG(fs);
1993	CPUMCTX16_LOADSEGREG(gs);
1994	CPUMCTX16_LOADSEGREG(ss);
1995
1996	CPUMCTX16_LOADREG(r8);
1997	CPUMCTX16_LOADREG(r9);
1998	CPUMCTX16_LOADREG(r10);
1999	CPUMCTX16_LOADREG(r11);
2000	CPUMCTX16_LOADREG(r12);
2001	CPUMCTX16_LOADREG(r13);
2002	CPUMCTX16_LOADREG(r14);
2003	CPUMCTX16_LOADREG(r15);
2004
2005	CPUMCTX16_LOADREG(cr0);
2006	CPUMCTX16_LOADREG(cr2);
2007	CPUMCTX16_LOADREG(cr3);
2008	CPUMCTX16_LOADREG(cr4);
2009
2010	CPUMCTX16_LOADDRXREG(0);
2011	CPUMCTX16_LOADDRXREG(1);
2012	CPUMCTX16_LOADDRXREG(2);
2013	CPUMCTX16_LOADDRXREG(3);
2014	CPUMCTX16_LOADDRXREG(4);
2015	CPUMCTX16_LOADDRXREG(5);
2016	CPUMCTX16_LOADDRXREG(6);
2017	CPUMCTX16_LOADDRXREG(7);
2018
2019	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2020	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2021	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2022	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2023
2024	CPUMCTX16_LOADREG(ldtr);
2025	CPUMCTX16_LOADREG(tr);
2026
2027	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2028
2029	CPUMCTX16_LOADREG(msrEFER);
2030	CPUMCTX16_LOADREG(msrSTAR);
2031	CPUMCTX16_LOADREG(msrPAT);
2032	CPUMCTX16_LOADREG(msrLSTAR);
2033	CPUMCTX16_LOADREG(msrCSTAR);
2034	CPUMCTX16_LOADREG(msrSFMASK);
2035	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2036
2037	CPUMCTX16_LOADHIDREG(ldtr);
2038	CPUMCTX16_LOADHIDREG(tr);
2039
2040	#undef CPUMCTX16_LOADSEGREG
2041	#undef CPUMCTX16_LOADHIDREG
2042	#undef CPUMCTX16_LOADDRXREG
2043	#undef CPUMCTX16_LOADREG
2044	}
2045
2046
2047	/**
2048	* @copydoc FNSSMINTLOADPREP
2049	*/
2050	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2051	{
2052	NOREF(pSSM);
2053	pVM->cpum.s.fPendingRestore = true;
2054	return VINF_SUCCESS;
2055	}
2056
2057
2058	/**
2059	* @copydoc FNSSMINTLOADEXEC
2060	*/
2061	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2062	{
2063	/*
2064	* Validate version.
2065	*/
2066	if ( uVersion != CPUM_SAVED_STATE_VERSION
2067	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2068	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2069	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2070	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2071	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2072	{
2073	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2074	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2075	}
2076
2077	if (uPass == SSM_PASS_FINAL)
2078	{
2079	/*
2080	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2081	* really old SSM file versions.)
2082	*/
2083	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2084	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2085	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2086	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2087
2088	/*
2089	* Restore.
2090	*/
2091	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2092	{
2093	PVMCPU pVCpu = &pVM->aCpus[i];
2094	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2095	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2096
2097	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2098	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2099	pVCpu->cpum.s.Hyper.esp = uESP;
2100	}
2101
2102	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2103	{
2104	CPUMCTX_VER1_6 cpumctx16;
2105	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2106	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2107
2108	/* Save the old cpumctx state into the new one. */
2109	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2110
2111	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2112	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2113	}
2114	else
2115	{
2116	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2117	{
2118	uint32_t cCpus;
2119	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2120	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2121	VERR_SSM_UNEXPECTED_DATA);
2122	}
2123	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2124	\|\| pVM->cCpus == 1,
2125	("cCpus=%u\n", pVM->cCpus),
2126	VERR_SSM_UNEXPECTED_DATA);
2127
2128	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2129	{
2130	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2131	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2132	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2133	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2134	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2135	}
2136	}
2137
2138	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2139	raw-mode guest, so we have to do it ourselves. */
2140	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2141	&& !HWACCMIsEnabled(pVM))
2142	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2143	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2144	}
2145
2146	pVM->cpum.s.fPendingRestore = false;
2147
2148	/*
2149	* Guest CPUIDs.
2150	*/
2151	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2152	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2153
2154	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2155	* actually required. */
2156
2157	/*
2158	* Restore the CPUID leaves.
2159	*
2160	* Note that we support restoring less than the current amount of standard
2161	* leaves because we've been allowed more is newer version of VBox.
2162	*/
2163	uint32_t cElements;
2164	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2165	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2166	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2167	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2168
2169	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2170	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2171	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2172	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2173
2174	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2175	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2176	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2177	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2178
2179	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2180
2181	/*
2182	* Check that the basic cpuid id information is unchanged.
2183	*/
2184	/** @todo we should check the 64 bits capabilities too! */
2185	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2186	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2187	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2188	uint32_t au32CpuIdSaved[8];
2189	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2190	if (RT_SUCCESS(rc))
2191	{
2192	/* Ignore CPU stepping. */
2193	au32CpuId[4] &= 0xfffffff0;
2194	au32CpuIdSaved[4] &= 0xfffffff0;
2195
2196	/* Ignore APIC ID (AMD specs). */
2197	au32CpuId[5] &= ~0xff000000;
2198	au32CpuIdSaved[5] &= ~0xff000000;
2199
2200	/* Ignore the number of Logical CPUs (AMD specs). */
2201	au32CpuId[5] &= ~0x00ff0000;
2202	au32CpuIdSaved[5] &= ~0x00ff0000;
2203
2204	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2205	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2206	\| X86_CPUID_FEATURE_ECX_VMX
2207	\| X86_CPUID_FEATURE_ECX_SMX
2208	\| X86_CPUID_FEATURE_ECX_EST
2209	\| X86_CPUID_FEATURE_ECX_TM2
2210	\| X86_CPUID_FEATURE_ECX_CNTXID
2211	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2212	\| X86_CPUID_FEATURE_ECX_PDCM
2213	\| X86_CPUID_FEATURE_ECX_DCA
2214	\| X86_CPUID_FEATURE_ECX_X2APIC
2215	);
2216	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2217	\| X86_CPUID_FEATURE_ECX_VMX
2218	\| X86_CPUID_FEATURE_ECX_SMX
2219	\| X86_CPUID_FEATURE_ECX_EST
2220	\| X86_CPUID_FEATURE_ECX_TM2
2221	\| X86_CPUID_FEATURE_ECX_CNTXID
2222	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2223	\| X86_CPUID_FEATURE_ECX_PDCM
2224	\| X86_CPUID_FEATURE_ECX_DCA
2225	\| X86_CPUID_FEATURE_ECX_X2APIC
2226	);
2227
2228	/* Make sure we don't forget to update the masks when enabling
2229	* features in the future.
2230	*/
2231	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2232	( X86_CPUID_FEATURE_ECX_DTES64
2233	\| X86_CPUID_FEATURE_ECX_VMX
2234	\| X86_CPUID_FEATURE_ECX_SMX
2235	\| X86_CPUID_FEATURE_ECX_EST
2236	\| X86_CPUID_FEATURE_ECX_TM2
2237	\| X86_CPUID_FEATURE_ECX_CNTXID
2238	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2239	\| X86_CPUID_FEATURE_ECX_PDCM
2240	\| X86_CPUID_FEATURE_ECX_DCA
2241	\| X86_CPUID_FEATURE_ECX_X2APIC
2242	)));
2243	/* do the compare */
2244	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2245	{
2246	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2247	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2248	"Saved=%.*Rhxs\n"
2249	"Real =%.*Rhxs\n",
2250	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2251	sizeof(au32CpuId), au32CpuId));
2252	else
2253	{
2254	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2255	"Saved=%.*Rhxs\n"
2256	"Real =%.*Rhxs\n",
2257	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2258	sizeof(au32CpuId), au32CpuId));
2259	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2260	}
2261	}
2262	}
2263
2264	return rc;
2265	}
2266
2267
2268	/**
2269	* @copydoc FNSSMINTLOADPREP
2270	*/
2271	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2272	{
2273	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2274	return VINF_SUCCESS;
2275
2276	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2277	if (pVM->cpum.s.fPendingRestore)
2278	{
2279	LogRel(("CPUM: Missing state!\n"));
2280	return VERR_INTERNAL_ERROR_2;
2281	}
2282
2283	/* Notify PGM of the NXE states in case they've changed. */
2284	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2285	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2286	return VINF_SUCCESS;
2287	}
2288
2289
2290	/**
2291	* Checks if the CPUM state restore is still pending.
2292	*
2293	* @returns true / false.
2294	* @param pVM The VM handle.
2295	*/
2296	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2297	{
2298	return pVM->cpum.s.fPendingRestore;
2299	}
2300
2301
2302	/**
2303	* Formats the EFLAGS value into mnemonics.
2304	*
2305	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2306	* @param efl The EFLAGS value.
2307	*/
2308	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2309	{
2310	/*
2311	* Format the flags.
2312	*/
2313	static const struct
2314	{
2315	const char pszSet; const char pszClear; uint32_t fFlag;
2316	} s_aFlags[] =
2317	{
2318	{ "vip",NULL, X86_EFL_VIP },
2319	{ "vif",NULL, X86_EFL_VIF },
2320	{ "ac", NULL, X86_EFL_AC },
2321	{ "vm", NULL, X86_EFL_VM },
2322	{ "rf", NULL, X86_EFL_RF },
2323	{ "nt", NULL, X86_EFL_NT },
2324	{ "ov", "nv", X86_EFL_OF },
2325	{ "dn", "up", X86_EFL_DF },
2326	{ "ei", "di", X86_EFL_IF },
2327	{ "tf", NULL, X86_EFL_TF },
2328	{ "nt", "pl", X86_EFL_SF },
2329	{ "nz", "zr", X86_EFL_ZF },
2330	{ "ac", "na", X86_EFL_AF },
2331	{ "po", "pe", X86_EFL_PF },
2332	{ "cy", "nc", X86_EFL_CF },
2333	};
2334	char *psz = pszEFlags;
2335	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2336	{
2337	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2338	if (pszAdd)
2339	{
2340	strcpy(psz, pszAdd);
2341	psz += strlen(pszAdd);
2342	*psz++ = ' ';
2343	}
2344	}
2345	psz[-1] = '\0';
2346	}
2347
2348
2349	/**
2350	* Formats a full register dump.
2351	*
2352	* @param pVM VM Handle.
2353	* @param pCtx The context to format.
2354	* @param pCtxCore The context core to format.
2355	* @param pHlp Output functions.
2356	* @param enmType The dump type.
2357	* @param pszPrefix Register name prefix.
2358	*/
2359	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2360	const char *pszPrefix)
2361	{
2362	NOREF(pVM);
2363
2364	/*
2365	* Format the EFLAGS.
2366	*/
2367	uint32_t efl = pCtxCore->eflags.u32;
2368	char szEFlags[80];
2369	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2370
2371	/*
2372	* Format the registers.
2373	*/
2374	switch (enmType)
2375	{
2376	case CPUMDUMPTYPE_TERSE:
2377	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2378	pHlp->pfnPrintf(pHlp,
2379	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2380	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2381	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2382	"%sr14=%016RX64 %sr15=%016RX64\n"
2383	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2384	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2385	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2386	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2387	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2388	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2389	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2390	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2391	else
2392	pHlp->pfnPrintf(pHlp,
2393	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2394	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2395	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2396	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2397	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2398	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2399	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2400	break;
2401
2402	case CPUMDUMPTYPE_DEFAULT:
2403	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2404	pHlp->pfnPrintf(pHlp,
2405	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2406	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2407	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2408	"%sr14=%016RX64 %sr15=%016RX64\n"
2409	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2410	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2411	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2412	,
2413	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2414	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2415	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2416	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2417	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2418	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2419	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2420	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2421	else
2422	pHlp->pfnPrintf(pHlp,
2423	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2424	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2425	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2426	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2427	,
2428	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2429	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2430	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2431	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2432	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2433	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2434	break;
2435
2436	case CPUMDUMPTYPE_VERBOSE:
2437	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2438	pHlp->pfnPrintf(pHlp,
2439	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2440	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2441	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2442	"%sr14=%016RX64 %sr15=%016RX64\n"
2443	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2444	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2445	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2446	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2447	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2448	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2449	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2450	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2451	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2452	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2453	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2454	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2455	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2456	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2457	,
2458	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2459	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2460	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2461	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2462	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2463	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2464	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2465	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2466	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2467	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2468	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2469	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2470	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2471	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2472	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2473	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2474	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2475	else
2476	pHlp->pfnPrintf(pHlp,
2477	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2478	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2479	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2480	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2481	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2482	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2483	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2484	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2485	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2486	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2487	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2488	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2489	,
2490	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2491	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2492	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2493	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2494	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2495	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2496	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2497	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2498	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2499	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2500	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2501	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2502
2503	pHlp->pfnPrintf(pHlp,
2504	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2505	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2506	,
2507	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2508	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2509	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2510	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2511	);
2512	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2513	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2514	{
2515	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2516	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2517	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2518	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2519	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2520	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2521	/** @todo This isn't entirenly correct and needs more work! */
2522	pHlp->pfnPrintf(pHlp,
2523	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2524	pszPrefix, iST, pszPrefix, iFPR,
2525	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2526	uTag, chSign, iInteger, u64Fraction, uExponent);
2527	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2528	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2529	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2530	else
2531	pHlp->pfnPrintf(pHlp, "\n");
2532	}
2533	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2534	pHlp->pfnPrintf(pHlp,
2535	iXMM & 1
2536	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2537	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2538	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2539	pCtx->fpu.aXMM[iXMM].au32[3],
2540	pCtx->fpu.aXMM[iXMM].au32[2],
2541	pCtx->fpu.aXMM[iXMM].au32[1],
2542	pCtx->fpu.aXMM[iXMM].au32[0]);
2543	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2544	if (pCtx->fpu.au32RsrvdRest[i])
2545	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2546	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2547
2548	pHlp->pfnPrintf(pHlp,
2549	"%sEFER =%016RX64\n"
2550	"%sPAT =%016RX64\n"
2551	"%sSTAR =%016RX64\n"
2552	"%sCSTAR =%016RX64\n"
2553	"%sLSTAR =%016RX64\n"
2554	"%sSFMASK =%016RX64\n"
2555	"%sKERNELGSBASE =%016RX64\n",
2556	pszPrefix, pCtx->msrEFER,
2557	pszPrefix, pCtx->msrPAT,
2558	pszPrefix, pCtx->msrSTAR,
2559	pszPrefix, pCtx->msrCSTAR,
2560	pszPrefix, pCtx->msrLSTAR,
2561	pszPrefix, pCtx->msrSFMASK,
2562	pszPrefix, pCtx->msrKERNELGSBASE);
2563	break;
2564	}
2565	}
2566
2567
2568	/**
2569	* Display all cpu states and any other cpum info.
2570	*
2571	* @param pVM VM Handle.
2572	* @param pHlp The info helper functions.
2573	* @param pszArgs Arguments, ignored.
2574	*/
2575	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2576	{
2577	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2578	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2579	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2580	cpumR3InfoHost(pVM, pHlp, pszArgs);
2581	}
2582
2583
2584	/**
2585	* Parses the info argument.
2586	*
2587	* The argument starts with 'verbose', 'terse' or 'default' and then
2588	* continues with the comment string.
2589	*
2590	* @param pszArgs The pointer to the argument string.
2591	* @param penmType Where to store the dump type request.
2592	* @param ppszComment Where to store the pointer to the comment string.
2593	*/
2594	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2595	{
2596	if (!pszArgs)
2597	{
2598	*penmType = CPUMDUMPTYPE_DEFAULT;
2599	*ppszComment = "";
2600	}
2601	else
2602	{
2603	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2604	{
2605	pszArgs += 5;
2606	*penmType = CPUMDUMPTYPE_VERBOSE;
2607	}
2608	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2609	{
2610	pszArgs += 5;
2611	*penmType = CPUMDUMPTYPE_TERSE;
2612	}
2613	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2614	{
2615	pszArgs += 7;
2616	*penmType = CPUMDUMPTYPE_DEFAULT;
2617	}
2618	else
2619	*penmType = CPUMDUMPTYPE_DEFAULT;
2620	*ppszComment = RTStrStripL(pszArgs);
2621	}
2622	}
2623
2624
2625	/**
2626	* Display the guest cpu state.
2627	*
2628	* @param pVM VM Handle.
2629	* @param pHlp The info helper functions.
2630	* @param pszArgs Arguments, ignored.
2631	*/
2632	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2633	{
2634	CPUMDUMPTYPE enmType;
2635	const char *pszComment;
2636	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2637
2638	/* @todo SMP support! */
2639	PVMCPU pVCpu = VMMGetCpu(pVM);
2640	if (!pVCpu)
2641	pVCpu = &pVM->aCpus[0];
2642
2643	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2644
2645	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2646	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2647	}
2648
2649
2650	/**
2651	* Display the current guest instruction
2652	*
2653	* @param pVM VM Handle.
2654	* @param pHlp The info helper functions.
2655	* @param pszArgs Arguments, ignored.
2656	*/
2657	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2658	{
2659	NOREF(pszArgs);
2660
2661	/** @todo SMP support! */
2662	PVMCPU pVCpu = VMMGetCpu(pVM);
2663	if (!pVCpu)
2664	pVCpu = &pVM->aCpus[0];
2665
2666	char szInstruction[256];
2667	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2668	if (RT_SUCCESS(rc))
2669	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2670	}
2671
2672
2673	/**
2674	* Display the hypervisor cpu state.
2675	*
2676	* @param pVM VM Handle.
2677	* @param pHlp The info helper functions.
2678	* @param pszArgs Arguments, ignored.
2679	*/
2680	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2681	{
2682	CPUMDUMPTYPE enmType;
2683	const char *pszComment;
2684	/* @todo SMP */
2685	PVMCPU pVCpu = &pVM->aCpus[0];
2686
2687	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2688	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2689	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2690	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2691	}
2692
2693
2694	/**
2695	* Display the host cpu state.
2696	*
2697	* @param pVM VM Handle.
2698	* @param pHlp The info helper functions.
2699	* @param pszArgs Arguments, ignored.
2700	*/
2701	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2702	{
2703	CPUMDUMPTYPE enmType;
2704	const char *pszComment;
2705	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2706	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2707
2708	/*
2709	* Format the EFLAGS.
2710	*/
2711	/* @todo SMP */
2712	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2713	#if HC_ARCH_BITS == 32
2714	uint32_t efl = pCtx->eflags.u32;
2715	#else
2716	uint64_t efl = pCtx->rflags;
2717	#endif
2718	char szEFlags[80];
2719	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2720
2721	/*
2722	* Format the registers.
2723	*/
2724	#if HC_ARCH_BITS == 32
2725	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2726	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2727	# endif
2728	{
2729	pHlp->pfnPrintf(pHlp,
2730	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2731	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2732	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2733	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2734	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2735	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2736	,
2737	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2738	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2739	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2740	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2741	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2742	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2743	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2744	}
2745	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2746	else
2747	# endif
2748	#endif
2749	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2750	{
2751	pHlp->pfnPrintf(pHlp,
2752	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2753	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2754	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2755	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2756	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2757	"r14=%016RX64 r15=%016RX64\n"
2758	"iopl=%d %31s\n"
2759	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2760	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2761	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2762	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2763	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2764	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2765	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2766	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2767	,
2768	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2769	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2770	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2771	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2772	pCtx->r11, pCtx->r12, pCtx->r13,
2773	pCtx->r14, pCtx->r15,
2774	X86_EFL_GET_IOPL(efl), szEFlags,
2775	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2776	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2777	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2778	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2779	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2780	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2781	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2782	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2783	}
2784	#endif
2785	}
2786
2787
2788	/**
2789	* Get L1 cache / TLS associativity.
2790	*/
2791	static const char getCacheAss(unsigned u, char pszBuf)
2792	{
2793	if (u == 0)
2794	return "res0 ";
2795	if (u == 1)
2796	return "direct";
2797	if (u == 255)
2798	return "fully";
2799	if (u >= 256)
2800	return "???";
2801
2802	RTStrPrintf(pszBuf, 16, "%d way", u);
2803	return pszBuf;
2804	}
2805
2806
2807	/**
2808	* Get L2 cache associativity.
2809	*/
2810	const char *getL2CacheAss(unsigned u)
2811	{
2812	switch (u)
2813	{
2814	case 0: return "off ";
2815	case 1: return "direct";
2816	case 2: return "2 way ";
2817	case 3: return "res3 ";
2818	case 4: return "4 way ";
2819	case 5: return "res5 ";
2820	case 6: return "8 way ";
2821	case 7: return "res7 ";
2822	case 8: return "16 way";
2823	case 9: return "res9 ";
2824	case 10: return "res10 ";
2825	case 11: return "res11 ";
2826	case 12: return "res12 ";
2827	case 13: return "res13 ";
2828	case 14: return "res14 ";
2829	case 15: return "fully ";
2830	default: return "????";
2831	}
2832	}
2833
2834
2835	/**
2836	* Display the guest CpuId leaves.
2837	*
2838	* @param pVM VM Handle.
2839	* @param pHlp The info helper functions.
2840	* @param pszArgs "terse", "default" or "verbose".
2841	*/
2842	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2843	{
2844	/*
2845	* Parse the argument.
2846	*/
2847	unsigned iVerbosity = 1;
2848	if (pszArgs)
2849	{
2850	pszArgs = RTStrStripL(pszArgs);
2851	if (!strcmp(pszArgs, "terse"))
2852	iVerbosity--;
2853	else if (!strcmp(pszArgs, "verbose"))
2854	iVerbosity++;
2855	}
2856
2857	/*
2858	* Start cracking.
2859	*/
2860	CPUMCPUID Host;
2861	CPUMCPUID Guest;
2862	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2863
2864	pHlp->pfnPrintf(pHlp,
2865	" RAW Standard CPUIDs\n"
2866	" Function eax ebx ecx edx\n");
2867	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2868	{
2869	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2870	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2871
2872	pHlp->pfnPrintf(pHlp,
2873	"Gst: %08x %08x %08x %08x %08x%s\n"
2874	"Hst: %08x %08x %08x %08x\n",
2875	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2876	i <= cStdMax ? "" : "*",
2877	Host.eax, Host.ebx, Host.ecx, Host.edx);
2878	}
2879
2880	/*
2881	* If verbose, decode it.
2882	*/
2883	if (iVerbosity)
2884	{
2885	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2886	pHlp->pfnPrintf(pHlp,
2887	"Name: %.04s%.04s%.04s\n"
2888	"Supports: 0-%x\n",
2889	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2890	}
2891
2892	/*
2893	* Get Features.
2894	*/
2895	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2896	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2897	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2898	if (cStdMax >= 1 && iVerbosity)
2899	{
2900	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2901
2902	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2903	uint32_t uEAX = Guest.eax;
2904
2905	pHlp->pfnPrintf(pHlp,
2906	"Family: %d \tExtended: %d \tEffective: %d\n"
2907	"Model: %d \tExtended: %d \tEffective: %d\n"
2908	"Stepping: %d\n"
2909	"Type: %d (%s)\n"
2910	"APIC ID: %#04x\n"
2911	"Logical CPUs: %d\n"
2912	"CLFLUSH Size: %d\n"
2913	"Brand ID: %#04x\n",
2914	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2915	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2916	ASMGetCpuStepping(uEAX),
2917	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2918	(Guest.ebx >> 24) & 0xff,
2919	(Guest.ebx >> 16) & 0xff,
2920	(Guest.ebx >> 8) & 0xff,
2921	(Guest.ebx >> 0) & 0xff);
2922	if (iVerbosity == 1)
2923	{
2924	uint32_t uEDX = Guest.edx;
2925	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2926	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2927	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2928	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2929	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2930	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2931	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2932	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2933	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2934	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2935	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2936	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2937	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2938	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2939	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2940	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2941	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2942	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2943	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2944	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2945	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2946	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2947	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2948	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2949	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2950	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2951	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2952	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2953	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2954	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2955	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2956	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2957	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2958	pHlp->pfnPrintf(pHlp, "\n");
2959
2960	uint32_t uECX = Guest.ecx;
2961	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2962	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2963	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2964	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2965	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2966	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2967	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2968	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2969	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2970	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2971	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2972	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2973	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2974	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2975	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2976	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2977	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2978	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2979	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
2980	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2981	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
2982	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
2983	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2984	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2985	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2986	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
2987	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2988	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2989	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2990	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2991	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2992	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2993	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2994	pHlp->pfnPrintf(pHlp, "\n");
2995	}
2996	else
2997	{
2998	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2999
3000	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3001	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3002	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3003	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3004
3005	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3006	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3007	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3008	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3009	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3010	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3011	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3012	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3013	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3014	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3015	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3016	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3017	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3018	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3019	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3020	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3021	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3022	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3023	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3024	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3025	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3026	pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3027	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3028	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3029	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3030	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3031	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3032	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3033	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3034	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3035	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3036	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3037	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3038
3039	pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3040	pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3041	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3042	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3043	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3044	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3045	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3046	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3047	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3048	pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3049	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3050	pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3051	pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3052	pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3053	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3054	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3055	pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3056	pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3057	pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3058	pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3059	pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3060	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3061	pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3062	pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3063	pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3064	pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3065	pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3066	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3067	pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3068	pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3069	pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3070	}
3071	}
3072	if (cStdMax >= 2 && iVerbosity)
3073	{
3074	/** @todo */
3075	}
3076
3077	/*
3078	* Extended.
3079	* Implemented after AMD specs.
3080	*/
3081	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3082
3083	pHlp->pfnPrintf(pHlp,
3084	"\n"
3085	" RAW Extended CPUIDs\n"
3086	" Function eax ebx ecx edx\n");
3087	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3088	{
3089	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3090	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3091
3092	pHlp->pfnPrintf(pHlp,
3093	"Gst: %08x %08x %08x %08x %08x%s\n"
3094	"Hst: %08x %08x %08x %08x\n",
3095	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3096	i <= cExtMax ? "" : "*",
3097	Host.eax, Host.ebx, Host.ecx, Host.edx);
3098	}
3099
3100	/*
3101	* Understandable output
3102	*/
3103	if (iVerbosity)
3104	{
3105	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3106	pHlp->pfnPrintf(pHlp,
3107	"Ext Name: %.4s%.4s%.4s\n"
3108	"Ext Supports: 0x80000000-%#010x\n",
3109	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3110	}
3111
3112	if (iVerbosity && cExtMax >= 1)
3113	{
3114	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3115	uint32_t uEAX = Guest.eax;
3116	pHlp->pfnPrintf(pHlp,
3117	"Family: %d \tExtended: %d \tEffective: %d\n"
3118	"Model: %d \tExtended: %d \tEffective: %d\n"
3119	"Stepping: %d\n"
3120	"Brand ID: %#05x\n",
3121	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3122	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3123	ASMGetCpuStepping(uEAX),
3124	Guest.ebx & 0xfff);
3125
3126	if (iVerbosity == 1)
3127	{
3128	uint32_t uEDX = Guest.edx;
3129	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3130	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3131	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3132	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3133	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3134	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3135	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3136	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3137	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3138	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3139	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3140	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3141	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3142	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3143	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3144	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3145	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3146	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3147	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3148	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3149	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3150	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3151	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3152	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3153	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3154	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3155	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3156	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3157	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3158	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3159	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3160	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3161	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3162	pHlp->pfnPrintf(pHlp, "\n");
3163
3164	uint32_t uECX = Guest.ecx;
3165	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3166	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3167	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3168	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3169	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3170	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3171	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3172	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3173	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3174	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3175	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3176	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3177	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3178	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3179	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3180	for (unsigned iBit = 5; iBit < 32; iBit++)
3181	if (uECX & RT_BIT(iBit))
3182	pHlp->pfnPrintf(pHlp, " %d", iBit);
3183	pHlp->pfnPrintf(pHlp, "\n");
3184	}
3185	else
3186	{
3187	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3188
3189	uint32_t uEdxGst = Guest.edx;
3190	uint32_t uEdxHst = Host.edx;
3191	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3192	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3193	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3194	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3195	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3196	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3197	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3198	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3199	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3200	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3201	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3202	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3203	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3204	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3205	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3206	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3207	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3208	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3209	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3210	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3211	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3212	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3213	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3214	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3215	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3216	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3217	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3218	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3219	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3220	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3221	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3222	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3223	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3224
3225	uint32_t uEcxGst = Guest.ecx;
3226	uint32_t uEcxHst = Host.ecx;
3227	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3228	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3229	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3230	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3231	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3232	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3233	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3234	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3235	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3236	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3237	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3238	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3239	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3240	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3241	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3242	}
3243	}
3244
3245	if (iVerbosity && cExtMax >= 2)
3246	{
3247	char szString[443+1] = {0};
3248	uint32_t pu32 = (uint32_t )szString;
3249	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3250	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3251	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3252	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3253	if (cExtMax >= 3)
3254	{
3255	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3256	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3257	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3258	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3259	}
3260	if (cExtMax >= 4)
3261	{
3262	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3263	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3264	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3265	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3266	}
3267	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3268	}
3269
3270	if (iVerbosity && cExtMax >= 5)
3271	{
3272	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3273	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3274	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3275	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3276	char sz1[32];
3277	char sz2[32];
3278
3279	pHlp->pfnPrintf(pHlp,
3280	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3281	"TLB 2/4M Data: %s %3d entries\n",
3282	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3283	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3284	pHlp->pfnPrintf(pHlp,
3285	"TLB 4K Instr/Uni: %s %3d entries\n"
3286	"TLB 4K Data: %s %3d entries\n",
3287	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3288	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3289	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3290	"L1 Instr Cache Lines Per Tag: %d\n"
3291	"L1 Instr Cache Associativity: %s\n"
3292	"L1 Instr Cache Size: %d KB\n",
3293	(uEDX >> 0) & 0xff,
3294	(uEDX >> 8) & 0xff,
3295	getCacheAss((uEDX >> 16) & 0xff, sz1),
3296	(uEDX >> 24) & 0xff);
3297	pHlp->pfnPrintf(pHlp,
3298	"L1 Data Cache Line Size: %d bytes\n"
3299	"L1 Data Cache Lines Per Tag: %d\n"
3300	"L1 Data Cache Associativity: %s\n"
3301	"L1 Data Cache Size: %d KB\n",
3302	(uECX >> 0) & 0xff,
3303	(uECX >> 8) & 0xff,
3304	getCacheAss((uECX >> 16) & 0xff, sz1),
3305	(uECX >> 24) & 0xff);
3306	}
3307
3308	if (iVerbosity && cExtMax >= 6)
3309	{
3310	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3311	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3312	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3313
3314	pHlp->pfnPrintf(pHlp,
3315	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3316	"L2 TLB 2/4M Data: %s %4d entries\n",
3317	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3318	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3319	pHlp->pfnPrintf(pHlp,
3320	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3321	"L2 TLB 4K Data: %s %4d entries\n",
3322	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3323	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3324	pHlp->pfnPrintf(pHlp,
3325	"L2 Cache Line Size: %d bytes\n"
3326	"L2 Cache Lines Per Tag: %d\n"
3327	"L2 Cache Associativity: %s\n"
3328	"L2 Cache Size: %d KB\n",
3329	(uEDX >> 0) & 0xff,
3330	(uEDX >> 8) & 0xf,
3331	getL2CacheAss((uEDX >> 12) & 0xf),
3332	(uEDX >> 16) & 0xffff);
3333	}
3334
3335	if (iVerbosity && cExtMax >= 7)
3336	{
3337	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3338
3339	pHlp->pfnPrintf(pHlp, "APM Features: ");
3340	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3341	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3342	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3343	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3344	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3345	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3346	for (unsigned iBit = 6; iBit < 32; iBit++)
3347	if (uEDX & RT_BIT(iBit))
3348	pHlp->pfnPrintf(pHlp, " %d", iBit);
3349	pHlp->pfnPrintf(pHlp, "\n");
3350	}
3351
3352	if (iVerbosity && cExtMax >= 8)
3353	{
3354	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3355	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3356
3357	pHlp->pfnPrintf(pHlp,
3358	"Physical Address Width: %d bits\n"
3359	"Virtual Address Width: %d bits\n"
3360	"Guest Physical Address Width: %d bits\n",
3361	(uEAX >> 0) & 0xff,
3362	(uEAX >> 8) & 0xff,
3363	(uEAX >> 16) & 0xff);
3364	pHlp->pfnPrintf(pHlp,
3365	"Physical Core Count: %d\n",
3366	(uECX >> 0) & 0xff);
3367	}
3368
3369
3370	/*
3371	* Centaur.
3372	*/
3373	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3374
3375	pHlp->pfnPrintf(pHlp,
3376	"\n"
3377	" RAW Centaur CPUIDs\n"
3378	" Function eax ebx ecx edx\n");
3379	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3380	{
3381	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3382	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3383
3384	pHlp->pfnPrintf(pHlp,
3385	"Gst: %08x %08x %08x %08x %08x%s\n"
3386	"Hst: %08x %08x %08x %08x\n",
3387	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3388	i <= cCentaurMax ? "" : "*",
3389	Host.eax, Host.ebx, Host.ecx, Host.edx);
3390	}
3391
3392	/*
3393	* Understandable output
3394	*/
3395	if (iVerbosity)
3396	{
3397	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3398	pHlp->pfnPrintf(pHlp,
3399	"Centaur Supports: 0xc0000000-%#010x\n",
3400	Guest.eax);
3401	}
3402
3403	if (iVerbosity && cCentaurMax >= 1)
3404	{
3405	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3406	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3407	uint32_t uEdxHst = Host.edx;
3408
3409	if (iVerbosity == 1)
3410	{
3411	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3412	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3413	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3414	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3415	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3416	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3417	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3418	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3419	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3420	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3421	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3422	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3423	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3424	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3425	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3426	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3427	for (unsigned iBit = 14; iBit < 32; iBit++)
3428	if (uEdxGst & RT_BIT(iBit))
3429	pHlp->pfnPrintf(pHlp, " %d", iBit);
3430	pHlp->pfnPrintf(pHlp, "\n");
3431	}
3432	else
3433	{
3434	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3435	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3436	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3437	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3438	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3439	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3440	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3441	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3442	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3443	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3444	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3445	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3446	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3447	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3448	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3449	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3450	for (unsigned iBit = 14; iBit < 32; iBit++)
3451	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3452	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3453	pHlp->pfnPrintf(pHlp, "\n");
3454	}
3455	}
3456	}
3457
3458
3459	/**
3460	* Structure used when disassembling and instructions in DBGF.
3461	* This is used so the reader function can get the stuff it needs.
3462	*/
3463	typedef struct CPUMDISASSTATE
3464	{
3465	/** Pointer to the CPU structure. */
3466	PDISCPUSTATE pCpu;
3467	/** The VM handle. */
3468	PVM pVM;
3469	/** The VMCPU handle. */
3470	PVMCPU pVCpu;
3471	/** Pointer to the first byte in the segment. */
3472	RTGCUINTPTR GCPtrSegBase;
3473	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3474	RTGCUINTPTR GCPtrSegEnd;
3475	/** The size of the segment minus 1. */
3476	RTGCUINTPTR cbSegLimit;
3477	/** Pointer to the current page - R3 Ptr. */
3478	void const *pvPageR3;
3479	/** Pointer to the current page - GC Ptr. */
3480	RTGCPTR pvPageGC;
3481	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3482	PGMPAGEMAPLOCK PageMapLock;
3483	/** Whether the PageMapLock is valid or not. */
3484	bool fLocked;
3485	/** 64 bits mode or not. */
3486	bool f64Bits;
3487	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3488
3489
3490	/**
3491	* Instruction reader.
3492	*
3493	* @returns VBox status code.
3494	* @param PtrSrc Address to read from.
3495	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3496	* @param pu8Dst Where to store the bytes.
3497	* @param cbRead Number of bytes to read.
3498	* @param uDisCpu Pointer to the disassembler cpu state.
3499	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3500	*/
3501	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3502	{
3503	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3504	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3505	Assert(cbRead > 0);
3506	for (;;)
3507	{
3508	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3509
3510	/* Need to update the page translation? */
3511	if ( !pState->pvPageR3
3512	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3513	{
3514	int rc = VINF_SUCCESS;
3515
3516	/* translate the address */
3517	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3518	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3519	&& !HWACCMIsEnabled(pState->pVM))
3520	{
3521	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3522	if (!pState->pvPageR3)
3523	rc = VERR_INVALID_POINTER;
3524	}
3525	else
3526	{
3527	/* Release mapping lock previously acquired. */
3528	if (pState->fLocked)
3529	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3530	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3531	pState->fLocked = RT_SUCCESS_NP(rc);
3532	}
3533	if (RT_FAILURE(rc))
3534	{
3535	pState->pvPageR3 = NULL;
3536	return rc;
3537	}
3538	}
3539
3540	/* check the segment limit */
3541	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3542	return VERR_OUT_OF_SELECTOR_BOUNDS;
3543
3544	/* calc how much we can read */
3545	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3546	if (!pState->f64Bits)
3547	{
3548	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3549	if (cb > cbSeg && cbSeg)
3550	cb = cbSeg;
3551	}
3552	if (cb > cbRead)
3553	cb = cbRead;
3554
3555	/* read and advance */
3556	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3557	cbRead -= cb;
3558	if (!cbRead)
3559	return VINF_SUCCESS;
3560	pu8Dst += cb;
3561	PtrSrc += cb;
3562	}
3563	}
3564
3565
3566	/**
3567	* Disassemble an instruction and return the information in the provided structure.
3568	*
3569	* @returns VBox status code.
3570	* @param pVM VM Handle
3571	* @param pVCpu VMCPU Handle
3572	* @param pCtx CPU context
3573	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3574	* @param pCpu Disassembly state
3575	* @param pszPrefix String prefix for logging (debug only)
3576	*
3577	*/
3578	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3579	{
3580	CPUMDISASSTATE State;
3581	int rc;
3582
3583	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3584	State.pCpu = pCpu;
3585	State.pvPageGC = 0;
3586	State.pvPageR3 = NULL;
3587	State.pVM = pVM;
3588	State.pVCpu = pVCpu;
3589	State.fLocked = false;
3590	State.f64Bits = false;
3591
3592	/*
3593	* Get selector information.
3594	*/
3595	if ( (pCtx->cr0 & X86_CR0_PE)
3596	&& pCtx->eflags.Bits.u1VM == 0)
3597	{
3598	if (CPUMAreHiddenSelRegsValid(pVCpu))
3599	{
3600	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3601	State.GCPtrSegBase = pCtx->csHid.u64Base;
3602	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3603	State.cbSegLimit = pCtx->csHid.u32Limit;
3604	pCpu->mode = (State.f64Bits)
3605	? CPUMODE_64BIT
3606	: pCtx->csHid.Attr.n.u1DefBig
3607	? CPUMODE_32BIT
3608	: CPUMODE_16BIT;
3609	}
3610	else
3611	{
3612	DBGFSELINFO SelInfo;
3613
3614	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3615	if (RT_FAILURE(rc))
3616	{
3617	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3618	return rc;
3619	}
3620
3621	/*
3622	* Validate the selector.
3623	*/
3624	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3625	if (RT_FAILURE(rc))
3626	{
3627	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3628	return rc;
3629	}
3630	State.GCPtrSegBase = SelInfo.GCPtrBase;
3631	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3632	State.cbSegLimit = SelInfo.cbLimit;
3633	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3634	}
3635	}
3636	else
3637	{
3638	/* real or V86 mode */
3639	pCpu->mode = CPUMODE_16BIT;
3640	State.GCPtrSegBase = pCtx->cs * 16;
3641	State.GCPtrSegEnd = 0xFFFFFFFF;
3642	State.cbSegLimit = 0xFFFFFFFF;
3643	}
3644
3645	/*
3646	* Disassemble the instruction.
3647	*/
3648	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3649	pCpu->apvUserData[0] = &State;
3650
3651	uint32_t cbInstr;
3652	#ifndef LOG_ENABLED
3653	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3654	if (RT_SUCCESS(rc))
3655	{
3656	#else
3657	char szOutput[160];
3658	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3659	if (RT_SUCCESS(rc))
3660	{
3661	/* log it */
3662	if (pszPrefix)
3663	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3664	else
3665	Log(("%s", szOutput));
3666	#endif
3667	rc = VINF_SUCCESS;
3668	}
3669	else
3670	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3671
3672	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3673	if (State.fLocked)
3674	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3675
3676	return rc;
3677	}
3678
3679	#ifdef DEBUG
3680
3681	/**
3682	* Disassemble an instruction and dump it to the log
3683	*
3684	* @returns VBox status code.
3685	* @param pVM VM Handle
3686	* @param pVCpu VMCPU Handle
3687	* @param pCtx CPU context
3688	* @param pc GC instruction pointer
3689	* @param pszPrefix String prefix for logging
3690	*
3691	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3692	*/
3693	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3694	{
3695	DISCPUSTATE Cpu;
3696	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3697	}
3698
3699
3700	/**
3701	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3702	*
3703	* @internal
3704	*/
3705	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3706	{
3707	/** @todo SMP support!! */
3708	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3709	}
3710
3711	#endif /* DEBUG */
3712
3713	/**
3714	* API for controlling a few of the CPU features found in CR4.
3715	*
3716	* Currently only X86_CR4_TSD is accepted as input.
3717	*
3718	* @returns VBox status code.
3719	*
3720	* @param pVM The VM handle.
3721	* @param fOr The CR4 OR mask.
3722	* @param fAnd The CR4 AND mask.
3723	*/
3724	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3725	{
3726	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3727	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3728
3729	pVM->cpum.s.CR4.OrMask &= fAnd;
3730	pVM->cpum.s.CR4.OrMask \|= fOr;
3731
3732	return VINF_SUCCESS;
3733	}
3734
3735
3736	/**
3737	* Gets a pointer to the array of standard CPUID leaves.
3738	*
3739	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3740	*
3741	* @returns Pointer to the standard CPUID leaves (read-only).
3742	* @param pVM The VM handle.
3743	* @remark Intended for PATM.
3744	*/
3745	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3746	{
3747	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3748	}
3749
3750
3751	/**
3752	* Gets a pointer to the array of extended CPUID leaves.
3753	*
3754	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3755	*
3756	* @returns Pointer to the extended CPUID leaves (read-only).
3757	* @param pVM The VM handle.
3758	* @remark Intended for PATM.
3759	*/
3760	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3761	{
3762	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3763	}
3764
3765
3766	/**
3767	* Gets a pointer to the array of centaur CPUID leaves.
3768	*
3769	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3770	*
3771	* @returns Pointer to the centaur CPUID leaves (read-only).
3772	* @param pVM The VM handle.
3773	* @remark Intended for PATM.
3774	*/
3775	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3776	{
3777	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3778	}
3779
3780
3781	/**
3782	* Gets a pointer to the default CPUID leaf.
3783	*
3784	* @returns Pointer to the default CPUID leaf (read-only).
3785	* @param pVM The VM handle.
3786	* @remark Intended for PATM.
3787	*/
3788	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3789	{
3790	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3791	}
3792
3793
3794	/**
3795	* Transforms the guest CPU state to raw-ring mode.
3796	*
3797	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3798	*
3799	* @returns VBox status. (recompiler failure)
3800	* @param pVCpu The VMCPU handle.
3801	* @param pCtxCore The context core (for trap usage).
3802	* @see @ref pg_raw
3803	*/
3804	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3805	{
3806	PVM pVM = pVCpu->CTX_SUFF(pVM);
3807
3808	Assert(!pVCpu->cpum.s.fRawEntered);
3809	Assert(!pVCpu->cpum.s.fRemEntered);
3810	if (!pCtxCore)
3811	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3812
3813	/*
3814	* Are we in Ring-0?
3815	*/
3816	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3817	&& !pCtxCore->eflags.Bits.u1VM)
3818	{
3819	/*
3820	* Enter execution mode.
3821	*/
3822	PATMRawEnter(pVM, pCtxCore);
3823
3824	/*
3825	* Set CPL to Ring-1.
3826	*/
3827	pCtxCore->ss \|= 1;
3828	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3829	pCtxCore->cs \|= 1;
3830	}
3831	else
3832	{
3833	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3834	("ring-1 code not supported\n"));
3835	/*
3836	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3837	*/
3838	PATMRawEnter(pVM, pCtxCore);
3839	}
3840
3841	/*
3842	* Invalidate the hidden registers.
3843	*/
3844	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3845
3846	/*
3847	* Assert sanity.
3848	*/
3849	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3850	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3851	\|\| pCtxCore->eflags.Bits.u1VM,
3852	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3853	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3854
3855	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3856
3857	pVCpu->cpum.s.fRawEntered = true;
3858	return VINF_SUCCESS;
3859	}
3860
3861
3862	/**
3863	* Transforms the guest CPU state from raw-ring mode to correct values.
3864	*
3865	* This function will change any selector registers with DPL=1 to DPL=0.
3866	*
3867	* @returns Adjusted rc.
3868	* @param pVCpu The VMCPU handle.
3869	* @param rc Raw mode return code
3870	* @param pCtxCore The context core (for trap usage).
3871	* @see @ref pg_raw
3872	*/
3873	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3874	{
3875	PVM pVM = pVCpu->CTX_SUFF(pVM);
3876
3877	/*
3878	* Don't leave if we've already left (in GC).
3879	*/
3880	Assert(pVCpu->cpum.s.fRawEntered);
3881	Assert(!pVCpu->cpum.s.fRemEntered);
3882	if (!pVCpu->cpum.s.fRawEntered)
3883	return rc;
3884	pVCpu->cpum.s.fRawEntered = false;
3885
3886	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3887	if (!pCtxCore)
3888	pCtxCore = CPUMCTX2CORE(pCtx);
3889	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3890	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3891	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3892
3893	/*
3894	* Are we executing in raw ring-1?
3895	*/
3896	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3897	&& !pCtxCore->eflags.Bits.u1VM)
3898	{
3899	/*
3900	* Leave execution mode.
3901	*/
3902	PATMRawLeave(pVM, pCtxCore, rc);
3903	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3904	/** @todo See what happens if we remove this. */
3905	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3906	pCtxCore->ds &= ~X86_SEL_RPL;
3907	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3908	pCtxCore->es &= ~X86_SEL_RPL;
3909	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3910	pCtxCore->fs &= ~X86_SEL_RPL;
3911	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3912	pCtxCore->gs &= ~X86_SEL_RPL;
3913
3914	/*
3915	* Ring-1 selector => Ring-0.
3916	*/
3917	pCtxCore->ss &= ~X86_SEL_RPL;
3918	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3919	pCtxCore->cs &= ~X86_SEL_RPL;
3920	}
3921	else
3922	{
3923	/*
3924	* PATM is taking care of the IOPL and IF flags for us.
3925	*/
3926	PATMRawLeave(pVM, pCtxCore, rc);
3927	if (!pCtxCore->eflags.Bits.u1VM)
3928	{
3929	/** @todo See what happens if we remove this. */
3930	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3931	pCtxCore->ds &= ~X86_SEL_RPL;
3932	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3933	pCtxCore->es &= ~X86_SEL_RPL;
3934	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3935	pCtxCore->fs &= ~X86_SEL_RPL;
3936	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3937	pCtxCore->gs &= ~X86_SEL_RPL;
3938	}
3939	}
3940
3941	return rc;
3942	}
3943
3944
3945	/**
3946	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3947	*
3948	* Only REM should ever call this function!
3949	*
3950	* @returns The changed flags.
3951	* @param pVCpu The VMCPU handle.
3952	* @param puCpl Where to return the current privilege level (CPL).
3953	*/
3954	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3955	{
3956	Assert(!pVCpu->cpum.s.fRawEntered);
3957	Assert(!pVCpu->cpum.s.fRemEntered);
3958
3959	/*
3960	* Get the CPL first.
3961	*/
3962	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3963
3964	/*
3965	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3966	*/
3967	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3968	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3969
3970	/** @todo change the switcher to use the fChanged flags. */
3971	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3972	{
3973	fFlags \|= CPUM_CHANGED_FPU_REM;
3974	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3975	}
3976
3977	pVCpu->cpum.s.fRemEntered = true;
3978	return fFlags;
3979	}
3980
3981
3982	/**
3983	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3984	*
3985	* @param pVCpu The virtual CPU handle.
3986	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3987	* registers.
3988	*/
3989	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3990	{
3991	Assert(!pVCpu->cpum.s.fRawEntered);
3992	Assert(pVCpu->cpum.s.fRemEntered);
3993
3994	if (fNoOutOfSyncSels)
3995	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3996	else
3997	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3998
3999	pVCpu->cpum.s.fRemEntered = false;
4000	}
4001

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 39913

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