CPUM.cpp@ 40082

Last change on this file since 40082 was 40075, checked in by vboxsync, 13 years ago
CPUM.cpp: MXCSR_MASK always was 0xffff not 0 (0xffbf) because of REM.
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1	/* $Id: CPUM.cpp 40075 2012-02-11 02:47:21Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*/
33
34	/*******************************************************************************
35	* Header Files *
36	*******************************************************************************/
37	#define LOG_GROUP LOG_GROUP_CPUM
38	#include <VBox/vmm/cpum.h>
39	#include <VBox/vmm/cpumdis.h>
40	#include <VBox/vmm/pgm.h>
41	#include <VBox/vmm/mm.h>
42	#include <VBox/vmm/selm.h>
43	#include <VBox/vmm/dbgf.h>
44	#include <VBox/vmm/patm.h>
45	#include <VBox/vmm/hwaccm.h>
46	#include <VBox/vmm/ssm.h>
47	#include "CPUMInternal.h"
48	#include <VBox/vmm/vm.h>
49
50	#include <VBox/param.h>
51	#include <VBox/dis.h>
52	#include <VBox/err.h>
53	#include <VBox/log.h>
54	#include <iprt/assert.h>
55	#include <iprt/asm-amd64-x86.h>
56	#include <iprt/string.h>
57	#include <iprt/mp.h>
58	#include <iprt/cpuset.h>
59	#include "internal/pgm.h"
60
61
62	/*******************************************************************************
63	* Defined Constants And Macros *
64	*******************************************************************************/
65	/** The current saved state version. */
66	#define CPUM_SAVED_STATE_VERSION 12
67	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
68	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
69	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
70	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
71	* changes. */
72	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
73	/** The saved state version for the 2.1 trunk before the MSR changes. */
74	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
75	/** The saved state version of 2.0, used for backwards compatibility. */
76	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
77	/** The saved state version of 1.6, used for backwards compatibility. */
78	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
79
80
81	/*******************************************************************************
82	* Structures and Typedefs *
83	*******************************************************************************/
84
85	/**
86	* What kind of cpu info dump to perform.
87	*/
88	typedef enum CPUMDUMPTYPE
89	{
90	CPUMDUMPTYPE_TERSE,
91	CPUMDUMPTYPE_DEFAULT,
92	CPUMDUMPTYPE_VERBOSE
93	} CPUMDUMPTYPE;
94	/** Pointer to a cpu info dump type. */
95	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
96
97
98	/*******************************************************************************
99	* Internal Functions *
100	*******************************************************************************/
101	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
102	static int cpumR3CpuIdInit(PVM pVM);
103	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
104	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
105	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
106	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
107	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
108	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
110	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
111	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
112	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
113	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
114
115
116	/**
117	* Initializes the CPUM.
118	*
119	* @returns VBox status code.
120	* @param pVM The VM to operate on.
121	*/
122	VMMR3DECL(int) CPUMR3Init(PVM pVM)
123	{
124	LogFlow(("CPUMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	*/
129	AssertCompileMemberAlignment(VM, cpum.s, 32);
130	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
131	AssertCompileSizeAlignment(CPUMCTX, 64);
132	AssertCompileSizeAlignment(CPUMCTXMSR, 64);
133	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
134	AssertCompileMemberAlignment(VM, cpum, 64);
135	AssertCompileMemberAlignment(VM, aCpus, 64);
136	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
137	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
138
139	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
140	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
141	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
142
143	/* Calculate the offset from CPUMCPU to CPUM. */
144	for (VMCPUID i = 0; i < pVM->cCpus; i++)
145	{
146	PVMCPU pVCpu = &pVM->aCpus[i];
147
148	/*
149	* Setup any fixed pointers and offsets.
150	*/
151	pVCpu->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVCpu->cpum.s.Hyper);
152	pVCpu->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper));
153
154	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
155	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
156	}
157
158	/*
159	* Check that the CPU supports the minimum features we require.
160	*/
161	if (!ASMHasCpuId())
162	{
163	Log(("The CPU doesn't support CPUID!\n"));
164	return VERR_UNSUPPORTED_CPU;
165	}
166	ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
167	ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
168
169	/* Setup the CR4 AND and OR masks used in the switcher */
170	/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
171	if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
172	{
173	Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
174	/* No FXSAVE implies no SSE */
175	pVM->cpum.s.CR4.AndMask = X86_CR4_PVI \| X86_CR4_VME;
176	pVM->cpum.s.CR4.OrMask = 0;
177	}
178	else
179	{
180	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
181	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
182	}
183
184	if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
185	{
186	Log(("The CPU doesn't support MMX!\n"));
187	return VERR_UNSUPPORTED_CPU;
188	}
189	if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
190	{
191	Log(("The CPU doesn't support TSC!\n"));
192	return VERR_UNSUPPORTED_CPU;
193	}
194	/* Bogus on AMD? */
195	if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
196	Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
197
198	/*
199	* Detect the host CPU vendor.
200	* (The guest CPU vendor is re-detected later on.)
201	*/
202	uint32_t uEAX, uEBX, uECX, uEDX;
203	ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
204	pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
205	pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
206
207	/*
208	* Setup hypervisor startup values.
209	*/
210
211	/*
212	* Register saved state data item.
213	*/
214	int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
215	NULL, cpumR3LiveExec, NULL,
216	NULL, cpumR3SaveExec, NULL,
217	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
218	if (RT_FAILURE(rc))
219	return rc;
220
221	/*
222	* Register info handlers and registers with the debugger facility.
223	*/
224	DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
225	DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
226	DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
227	DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
228	DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
229	DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
230
231	rc = cpumR3DbgInit(pVM);
232	if (RT_FAILURE(rc))
233	return rc;
234
235	/*
236	* Initialize the Guest CPUID state.
237	*/
238	rc = cpumR3CpuIdInit(pVM);
239	if (RT_FAILURE(rc))
240	return rc;
241	CPUMR3Reset(pVM);
242	return VINF_SUCCESS;
243	}
244
245
246	/**
247	* Detect the CPU vendor give n the
248	*
249	* @returns The vendor.
250	* @param uEAX EAX from CPUID(0).
251	* @param uEBX EBX from CPUID(0).
252	* @param uECX ECX from CPUID(0).
253	* @param uEDX EDX from CPUID(0).
254	*/
255	static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
256	{
257	if ( uEAX >= 1
258	&& uEBX == X86_CPUID_VENDOR_AMD_EBX
259	&& uECX == X86_CPUID_VENDOR_AMD_ECX
260	&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
261	return CPUMCPUVENDOR_AMD;
262
263	if ( uEAX >= 1
264	&& uEBX == X86_CPUID_VENDOR_INTEL_EBX
265	&& uECX == X86_CPUID_VENDOR_INTEL_ECX
266	&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
267	return CPUMCPUVENDOR_INTEL;
268
269	/** @todo detect the other buggers... */
270	return CPUMCPUVENDOR_UNKNOWN;
271	}
272
273
274	/**
275	* Fetches overrides for a CPUID leaf.
276	*
277	* @returns VBox status code.
278	* @param pLeaf The leaf to load the overrides into.
279	* @param pCfgNode The CFGM node containing the overrides
280	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
281	* @param iLeaf The CPUID leaf number.
282	*/
283	static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
284	{
285	PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
286	if (pLeafNode)
287	{
288	uint32_t u32;
289	int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
290	if (RT_SUCCESS(rc))
291	pLeaf->eax = u32;
292	else
293	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
294
295	rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
296	if (RT_SUCCESS(rc))
297	pLeaf->ebx = u32;
298	else
299	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
300
301	rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
302	if (RT_SUCCESS(rc))
303	pLeaf->ecx = u32;
304	else
305	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
306
307	rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
308	if (RT_SUCCESS(rc))
309	pLeaf->edx = u32;
310	else
311	AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
312
313	}
314	return VINF_SUCCESS;
315	}
316
317
318	/**
319	* Load the overrides for a set of CPUID leaves.
320	*
321	* @returns VBox status code.
322	* @param paLeaves The leaf array.
323	* @param cLeaves The number of leaves.
324	* @param uStart The start leaf number.
325	* @param pCfgNode The CFGM node containing the overrides
326	* (/CPUM/HostCPUID/ or /CPUM/CPUID/).
327	*/
328	static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
329	{
330	for (uint32_t i = 0; i < cLeaves; i++)
331	{
332	int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
333	if (RT_FAILURE(rc))
334	return rc;
335	}
336
337	return VINF_SUCCESS;
338	}
339
340	/**
341	* Init a set of host CPUID leaves.
342	*
343	* @returns VBox status code.
344	* @param paLeaves The leaf array.
345	* @param cLeaves The number of leaves.
346	* @param uStart The start leaf number.
347	* @param pCfgNode The /CPUM/HostCPUID/ node.
348	*/
349	static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
350	{
351	/* Using the ECX variant for all of them can't hurt... */
352	for (uint32_t i = 0; i < cLeaves; i++)
353	ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
354
355	/* Load CPUID leaf override; we currently don't care if the user
356	specifies features the host CPU doesn't support. */
357	return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
358	}
359
360
361	/**
362	* Initializes the emulated CPU's cpuid information.
363	*
364	* @returns VBox status code.
365	* @param pVM The VM to operate on.
366	*/
367	static int cpumR3CpuIdInit(PVM pVM)
368	{
369	PCPUM pCPUM = &pVM->cpum.s;
370	PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
371	uint32_t i;
372	int rc;
373
374	#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
375	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
376	{ \
377	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
378	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
379	}
380	#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
381	if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
382	{ \
383	LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
384	pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
385	}
386
387	/*
388	* Read the configuration.
389	*/
390	/** @cfgm{CPUM/SyntheticCpu, boolean, false}
391	* Enables the Synthetic CPU. The Vendor ID and Processor Name are
392	* completely overridden by VirtualBox custom strings. Some
393	* CPUID information is withheld, like the cache info. */
394	rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
395	AssertRCReturn(rc, rc);
396
397	/** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
398	* When non-zero CPUID features that could cause portability issues will be
399	* stripped. The higher the value the more features gets stripped. Higher
400	* values should only be used when older CPUs are involved since it may
401	* harm performance and maybe also cause problems with specific guests. */
402	rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
403	AssertRCReturn(rc, rc);
404
405	AssertLogRelReturn(!pCPUM->fSyntheticCpu \|\| !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
406
407	/*
408	* Get the host CPUID leaves and redetect the guest CPU vendor (could've
409	* been overridden).
410	*/
411	/** @cfgm{CPUM/HostCPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
412	* Overrides the host CPUID leaf values used for calculating the guest CPUID
413	* leaves. This can be used to preserve the CPUID values when moving a VM
414	* to a different machine. Another use is restricting (or extending) the
415	* feature set exposed to the guest. */
416	PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
417	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
418	AssertRCReturn(rc, rc);
419	rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
420	AssertRCReturn(rc, rc);
421	rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
422	AssertRCReturn(rc, rc);
423
424	pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
425	pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
426
427	/*
428	* Determine the default leaf.
429	*
430	* Intel returns values of the highest standard function, while AMD
431	* returns zeros. VIA on the other hand seems to returning nothing or
432	* perhaps some random garbage, we don't try to duplicate this behavior.
433	*/
434	ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
435	&pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
436	&pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
437
438
439	/* Cpuid 1 & 0x80000001:
440	* Only report features we can support.
441	*
442	* Note! When enabling new features the Synthetic CPU and Portable CPUID
443	* options may require adjusting (i.e. stripping what was enabled).
444	*/
445	pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
446	\| X86_CPUID_FEATURE_EDX_VME
447	\| X86_CPUID_FEATURE_EDX_DE
448	\| X86_CPUID_FEATURE_EDX_PSE
449	\| X86_CPUID_FEATURE_EDX_TSC
450	\| X86_CPUID_FEATURE_EDX_MSR
451	//\| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
452	\| X86_CPUID_FEATURE_EDX_MCE
453	\| X86_CPUID_FEATURE_EDX_CX8
454	//\| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
455	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
456	//\| X86_CPUID_FEATURE_EDX_SEP
457	\| X86_CPUID_FEATURE_EDX_MTRR
458	\| X86_CPUID_FEATURE_EDX_PGE
459	\| X86_CPUID_FEATURE_EDX_MCA
460	\| X86_CPUID_FEATURE_EDX_CMOV
461	\| X86_CPUID_FEATURE_EDX_PAT
462	\| X86_CPUID_FEATURE_EDX_PSE36
463	//\| X86_CPUID_FEATURE_EDX_PSN - no serial number.
464	\| X86_CPUID_FEATURE_EDX_CLFSH
465	//\| X86_CPUID_FEATURE_EDX_DS - no debug store.
466	//\| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
467	\| X86_CPUID_FEATURE_EDX_MMX
468	\| X86_CPUID_FEATURE_EDX_FXSR
469	\| X86_CPUID_FEATURE_EDX_SSE
470	\| X86_CPUID_FEATURE_EDX_SSE2
471	//\| X86_CPUID_FEATURE_EDX_SS - no self snoop.
472	//\| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
473	//\| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
474	//\| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
475	\| 0;
476	pCPUM->aGuestCpuIdStd[1].ecx &= 0
477	\| X86_CPUID_FEATURE_ECX_SSE3
478	/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
479	\| ((pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
480	//\| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
481	//\| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
482	//\| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
483	//\| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
484	\| X86_CPUID_FEATURE_ECX_SSSE3
485	//\| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
486	//\| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
487	/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
488	//\| X86_CPUID_FEATURE_ECX_TPRUPDATE
489	/* ECX Bit 21 - x2APIC support - not yet. */
490	// \| X86_CPUID_FEATURE_ECX_X2APIC
491	/* ECX Bit 23 - POPCNT instruction. */
492	//\| X86_CPUID_FEATURE_ECX_POPCNT
493	\| 0;
494	if (pCPUM->u8PortableCpuIdLevel > 0)
495	{
496	PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
497	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
498	PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
499	PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
500	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
501	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
502	PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
503
504	Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
505	\| X86_CPUID_FEATURE_EDX_PSN
506	\| X86_CPUID_FEATURE_EDX_DS
507	\| X86_CPUID_FEATURE_EDX_ACPI
508	\| X86_CPUID_FEATURE_EDX_SS
509	\| X86_CPUID_FEATURE_EDX_TM
510	\| X86_CPUID_FEATURE_EDX_PBE
511	)));
512	Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
513	\| X86_CPUID_FEATURE_ECX_DTES64
514	\| X86_CPUID_FEATURE_ECX_CPLDS
515	\| X86_CPUID_FEATURE_ECX_VMX
516	\| X86_CPUID_FEATURE_ECX_SMX
517	\| X86_CPUID_FEATURE_ECX_EST
518	\| X86_CPUID_FEATURE_ECX_TM2
519	\| X86_CPUID_FEATURE_ECX_CNTXID
520	\| X86_CPUID_FEATURE_ECX_FMA
521	\| X86_CPUID_FEATURE_ECX_CX16
522	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
523	\| X86_CPUID_FEATURE_ECX_PDCM
524	\| X86_CPUID_FEATURE_ECX_DCA
525	\| X86_CPUID_FEATURE_ECX_MOVBE
526	\| X86_CPUID_FEATURE_ECX_AES
527	\| X86_CPUID_FEATURE_ECX_POPCNT
528	\| X86_CPUID_FEATURE_ECX_XSAVE
529	\| X86_CPUID_FEATURE_ECX_OSXSAVE
530	\| X86_CPUID_FEATURE_ECX_AVX
531	)));
532	}
533
534	/* Cpuid 0x80000001:
535	* Only report features we can support.
536	*
537	* Note! When enabling new features the Synthetic CPU and Portable CPUID
538	* options may require adjusting (i.e. stripping what was enabled).
539	*
540	* ASSUMES that this is ALWAYS the AMD defined feature set if present.
541	*/
542	pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
543	\| X86_CPUID_AMD_FEATURE_EDX_VME
544	\| X86_CPUID_AMD_FEATURE_EDX_DE
545	\| X86_CPUID_AMD_FEATURE_EDX_PSE
546	\| X86_CPUID_AMD_FEATURE_EDX_TSC
547	\| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
548	//\| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
549	//\| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
550	\| X86_CPUID_AMD_FEATURE_EDX_CX8
551	//\| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
552	/* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
553	//\| X86_CPUID_AMD_FEATURE_EDX_SEP
554	\| X86_CPUID_AMD_FEATURE_EDX_MTRR
555	\| X86_CPUID_AMD_FEATURE_EDX_PGE
556	\| X86_CPUID_AMD_FEATURE_EDX_MCA
557	\| X86_CPUID_AMD_FEATURE_EDX_CMOV
558	\| X86_CPUID_AMD_FEATURE_EDX_PAT
559	\| X86_CPUID_AMD_FEATURE_EDX_PSE36
560	//\| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
561	//\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
562	\| X86_CPUID_AMD_FEATURE_EDX_MMX
563	\| X86_CPUID_AMD_FEATURE_EDX_FXSR
564	\| X86_CPUID_AMD_FEATURE_EDX_FFXSR
565	//\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
566	//\| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
567	//\| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
568	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
569	\| X86_CPUID_AMD_FEATURE_EDX_3DNOW
570	\| 0;
571	pCPUM->aGuestCpuIdExt[1].ecx &= 0
572	//\| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
573	//\| X86_CPUID_AMD_FEATURE_ECX_CMPL
574	//\| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
575	//\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
576	/* Note: This could prevent teleporting from AMD to Intel CPUs! */
577	\| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
578	//\| X86_CPUID_AMD_FEATURE_ECX_ABM
579	//\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
580	//\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
581	//\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
582	//\| X86_CPUID_AMD_FEATURE_ECX_OSVW
583	//\| X86_CPUID_AMD_FEATURE_ECX_IBS
584	//\| X86_CPUID_AMD_FEATURE_ECX_SSE5
585	//\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
586	//\| X86_CPUID_AMD_FEATURE_ECX_WDT
587	\| 0;
588	if (pCPUM->u8PortableCpuIdLevel > 0)
589	{
590	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
591	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
592	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
593	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
594	PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
595	PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
596	PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
597
598	Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
599	\| X86_CPUID_AMD_FEATURE_ECX_SVM
600	\| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
601	\| X86_CPUID_AMD_FEATURE_ECX_CR8L
602	\| X86_CPUID_AMD_FEATURE_ECX_ABM
603	\| X86_CPUID_AMD_FEATURE_ECX_SSE4A
604	\| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
605	\| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
606	\| X86_CPUID_AMD_FEATURE_ECX_OSVW
607	\| X86_CPUID_AMD_FEATURE_ECX_IBS
608	\| X86_CPUID_AMD_FEATURE_ECX_SSE5
609	\| X86_CPUID_AMD_FEATURE_ECX_SKINIT
610	\| X86_CPUID_AMD_FEATURE_ECX_WDT
611	\| UINT32_C(0xffffc000)
612	)));
613	Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
614	\| X86_CPUID_AMD_FEATURE_EDX_SEP
615	\| RT_BIT(18)
616	\| RT_BIT(19)
617	\| RT_BIT(21)
618	\| X86_CPUID_AMD_FEATURE_EDX_AXMMX
619	\| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
620	\| RT_BIT(28)
621	)));
622	}
623
624	/*
625	* Apply the Synthetic CPU modifications. (TODO: move this up)
626	*/
627	if (pCPUM->fSyntheticCpu)
628	{
629	static const char s_szVendor[13] = "VirtualBox ";
630	static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
631
632	pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
633
634	/* Limit the nr of standard leaves; 5 for monitor/mwait */
635	pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
636
637	/* 0: Vendor */
638	pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
639	pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
640	pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
641
642	/* 1.eax: Version information. family : model : stepping */
643	pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
644
645	/* Leaves 2 - 4 are Intel only - zero them out */
646	memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
647	memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
648	memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
649
650	/* Leaf 5 = monitor/mwait */
651
652	/* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
653	pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
654	/* AMD only - set to zero. */
655	pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
656
657	/* 0x800000001: AMD only; shared feature bits are set dynamically. */
658	memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
659
660	/* 0x800000002-4: Processor Name String Identifier. */
661	pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
662	pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
663	pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
664	pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
665	pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
666	pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
667	pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
668	pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
669	pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
670	pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
671	pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
672	pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
673
674	/* 0x800000005-7 - reserved -> zero */
675	memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
676	memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
677	memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
678
679	/* 0x800000008: only the max virtual and physical address size. */
680	pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
681	}
682
683	/*
684	* Hide HTT, multicode, SMP, whatever.
685	* (APIC-ID := 0 and #LogCpus := 0)
686	*/
687	pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
688	#ifdef VBOX_WITH_MULTI_CORE
689	if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
690	&& pVM->cCpus > 1)
691	{
692	/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
693	pCPUM->aGuestCpuIdStd[1].ebx \|= (pVM->cCpus << 16);
694	pCPUM->aGuestCpuIdStd[1].edx \|= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading or multi-core CPUs */
695	}
696	#endif
697
698	/* Cpuid 2:
699	* Intel: Cache and TLB information
700	* AMD: Reserved
701	* Safe to expose; restrict the number of calls to 1 for the portable case.
702	*/
703	if ( pCPUM->u8PortableCpuIdLevel > 0
704	&& pCPUM->aGuestCpuIdStd[0].eax >= 2
705	&& (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
706	{
707	LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
708	pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
709	}
710
711	/* Cpuid 3:
712	* Intel: EAX, EBX - reserved (transmeta uses these)
713	* ECX, EDX - Processor Serial Number if available, otherwise reserved
714	* AMD: Reserved
715	* Safe to expose
716	*/
717	if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
718	{
719	pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
720	if (pCPUM->u8PortableCpuIdLevel > 0)
721	pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
722	}
723
724	/* Cpuid 4:
725	* Intel: Deterministic Cache Parameters Leaf
726	* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
727	* AMD: Reserved
728	* Safe to expose, except for EAX:
729	* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
730	* Bits 31-26: Maximum number of processor cores in this physical package**
731	* Note: These SMP values are constant regardless of ECX
732	*/
733	pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
734	pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
735	#ifdef VBOX_WITH_MULTI_CORE
736	if ( pVM->cCpus > 1
737	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
738	{
739	AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
740	/* One logical processor with possibly multiple cores. */
741	/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
742	pCPUM->aGuestCpuIdStd[4].eax \|= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
743	}
744	#endif
745
746	/* Cpuid 5: Monitor/mwait Leaf
747	* Intel: ECX, EDX - reserved
748	* EAX, EBX - Smallest and largest monitor line size
749	* AMD: EDX - reserved
750	* EAX, EBX - Smallest and largest monitor line size
751	* ECX - extensions (ignored for now)
752	* Safe to expose
753	*/
754	if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
755	pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
756
757	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
758	/** @cfgm{/CPUM/MWaitExtensions, boolean, false}
759	* Expose MWAIT extended features to the guest. For now we expose
760	* just MWAIT break on interrupt feature (bit 1).
761	*/
762	bool fMWaitExtensions;
763	rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
764	if (fMWaitExtensions)
765	{
766	pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT \| X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
767	/* @todo: for now we just expose host's MWAIT C-states, although conceptually
768	it shall be part of our power management virtualization model */
769	#if 0
770	/* MWAIT sub C-states */
771	pCPUM->aGuestCpuIdStd[5].edx =
772	(0 << 0) /* 0 in C0 */ \|
773	(2 << 4) /* 2 in C1 */ \|
774	(2 << 8) /* 2 in C2 */ \|
775	(2 << 12) /* 2 in C3 */ \|
776	(0 << 16) /* 0 in C4 */
777	;
778	#endif
779	}
780	else
781	pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
782
783	/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
784	* Safe to pass on to the guest.
785	*
786	* Intel: 0x800000005 reserved
787	* 0x800000006 L2 cache information
788	* AMD: 0x800000005 L1 cache information
789	* 0x800000006 L2/L3 cache information
790	*/
791
792	/* Cpuid 0x800000007:
793	* AMD: EAX, EBX, ECX - reserved
794	* EDX: Advanced Power Management Information
795	* Intel: Reserved
796	*/
797	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
798	{
799	Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
800
801	pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
802
803	if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
804	{
805	/* Only expose the TSC invariant capability bit to the guest. */
806	pCPUM->aGuestCpuIdExt[7].edx &= 0
807	//\| X86_CPUID_AMD_ADVPOWER_EDX_TS
808	//\| X86_CPUID_AMD_ADVPOWER_EDX_FID
809	//\| X86_CPUID_AMD_ADVPOWER_EDX_VID
810	//\| X86_CPUID_AMD_ADVPOWER_EDX_TTP
811	//\| X86_CPUID_AMD_ADVPOWER_EDX_TM
812	//\| X86_CPUID_AMD_ADVPOWER_EDX_STC
813	//\| X86_CPUID_AMD_ADVPOWER_EDX_MC
814	//\| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
815	#if 0 /* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
816	* Linux kernels blindly assume that the AMD performance counters work
817	* if this is set for 64 bits guests. (Can't really find a CPUID feature
818	* bit for them though.) */
819	\| X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
820	#endif
821	\| 0;
822	}
823	else
824	pCPUM->aGuestCpuIdExt[7].edx = 0;
825	}
826
827	/* Cpuid 0x800000008:
828	* AMD: EBX, EDX - reserved
829	* EAX: Virtual/Physical/Guest address Size
830	* ECX: Number of cores + APICIdCoreIdSize
831	* Intel: EAX: Virtual/Physical address Size
832	* EBX, ECX, EDX - reserved
833	*/
834	if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
835	{
836	/* Only expose the virtual and physical address sizes to the guest. */
837	pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
838	pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
839	/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
840	* NC (0-7) Number of cores; 0 equals 1 core */
841	pCPUM->aGuestCpuIdExt[8].ecx = 0;
842	#ifdef VBOX_WITH_MULTI_CORE
843	if ( pVM->cCpus > 1
844	&& pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
845	{
846	/* Legacy method to determine the number of cores. */
847	pCPUM->aGuestCpuIdExt[1].ecx \|= X86_CPUID_AMD_FEATURE_ECX_CMPL;
848	pCPUM->aGuestCpuIdExt[8].ecx \|= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
849	}
850	#endif
851	}
852
853	/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
854	* Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
855	* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
856	* This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
857	*/
858	bool fNt4LeafLimit;
859	rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
860	if (fNt4LeafLimit)
861	pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
862
863	/*
864	* Limit it the number of entries and fill the remaining with the defaults.
865	*
866	* The limits are masking off stuff about power saving and similar, this
867	* is perhaps a bit crudely done as there is probably some relatively harmless
868	* info too in these leaves (like words about having a constant TSC).
869	*/
870	if (pCPUM->aGuestCpuIdStd[0].eax > 5)
871	pCPUM->aGuestCpuIdStd[0].eax = 5;
872	for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
873	pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
874
875	if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
876	pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
877	for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
878	? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
879	: 0;
880	i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
881	i++)
882	pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
883
884	/*
885	* Centaur stuff (VIA).
886	*
887	* The important part here (we think) is to make sure the 0xc0000000
888	* function returns 0xc0000001. As for the features, we don't currently
889	* let on about any of those... 0xc0000002 seems to be some
890	* temperature/hz/++ stuff, include it as well (static).
891	*/
892	if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
893	&& pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
894	{
895	pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
896	pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
897	for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
898	i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
899	i++)
900	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
901	}
902	else
903	for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
904	pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
905
906
907	/*
908	* Load CPUID overrides from configuration.
909	* Note: Kind of redundant now, but allows unchanged overrides
910	*/
911	/** @cfgm{CPUM/CPUID/[000000xx\|800000xx\|c000000x]/[eax\|ebx\|ecx\|edx],32-bit}
912	* Overrides the CPUID leaf values. */
913	PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
914	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
915	AssertRCReturn(rc, rc);
916	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
917	AssertRCReturn(rc, rc);
918	rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
919	AssertRCReturn(rc, rc);
920
921	/*
922	* Check if PAE was explicitely enabled by the user.
923	*/
924	bool fEnable;
925	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
926	if (fEnable)
927	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
928
929	/*
930	* We don't normally enable NX for raw-mode, so give the user a chance to
931	* force it on.
932	*/
933	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
934	if (fEnable)
935	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
936
937	/*
938	* We don't enable the Hypervisor Present bit by default, but it may
939	* be needed by some guests.
940	*/
941	rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
942	if (fEnable)
943	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
944	/*
945	* Log the cpuid and we're good.
946	*/
947	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
948	RTCPUSET OnlineSet;
949	LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
950	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
951	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
952	LogRel(("*********************** CPUID dump **********************\n"));
953	DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
954	LogRel(("\n"));
955	DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
956	RTLogRelSetBuffering(fOldBuffered);
957	LogRel(("****************** End of CPUID dump ********************\n"));
958
959	#undef PORTABLE_DISABLE_FEATURE_BIT
960	#undef PORTABLE_CLEAR_BITS_WHEN
961
962	return VINF_SUCCESS;
963	}
964
965
966	/**
967	* Applies relocations to data and code managed by this
968	* component. This function will be called at init and
969	* whenever the VMM need to relocate it self inside the GC.
970	*
971	* The CPUM will update the addresses used by the switcher.
972	*
973	* @param pVM The VM.
974	*/
975	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
976	{
977	LogFlow(("CPUMR3Relocate\n"));
978	for (VMCPUID i = 0; i < pVM->cCpus; i++)
979	{
980	/*
981	* Switcher pointers.
982	*/
983	PVMCPU pVCpu = &pVM->aCpus[i];
984	pVCpu->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVCpu->cpum.s.pHyperCoreR3);
985	Assert(pVCpu->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
986
987	}
988	}
989
990
991	/**
992	* Apply late CPUM property changes based on the fHWVirtEx setting
993	*
994	* @param pVM The VM to operate on.
995	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
996	*/
997	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
998	{
999	/*
1000	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1001	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1002	* of processors from (cpuid(4).eax >> 26) + 1.
1003	*
1004	* Note: this code is obsolete, but let's keep it here for reference.
1005	* Purpose is valid when we artificially cap the max std id to less than 4.
1006	*/
1007	if (!fHWVirtExEnabled)
1008	{
1009	Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1010	\|\| pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1011	pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1012	}
1013	}
1014
1015	/**
1016	* Terminates the CPUM.
1017	*
1018	* Termination means cleaning up and freeing all resources,
1019	* the VM it self is at this point powered off or suspended.
1020	*
1021	* @returns VBox status code.
1022	* @param pVM The VM to operate on.
1023	*/
1024	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1025	{
1026	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1027	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1028	{
1029	PVMCPU pVCpu = &pVM->aCpus[i];
1030	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1031
1032	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1033	pVCpu->cpum.s.uMagic = 0;
1034	pCtx->dr[5] = 0;
1035	}
1036	#else
1037	NOREF(pVM);
1038	#endif
1039	return VINF_SUCCESS;
1040	}
1041
1042
1043	/**
1044	* Resets a virtual CPU.
1045	*
1046	* Used by CPUMR3Reset and CPU hot plugging.
1047	*
1048	* @param pVCpu The virtual CPU handle.
1049	*/
1050	VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1051	{
1052	/** @todo anything different for VCPU > 0? */
1053	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1054
1055	/*
1056	* Initialize everything to ZERO first.
1057	*/
1058	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1059	memset(pCtx, 0, sizeof(*pCtx));
1060	pVCpu->cpum.s.fUseFlags = fUseFlags;
1061
1062	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1063	pCtx->eip = 0x0000fff0;
1064	pCtx->edx = 0x00000600; /* P6 processor */
1065	pCtx->eflags.Bits.u1Reserved0 = 1;
1066
1067	pCtx->cs = 0xf000;
1068	pCtx->csHid.u64Base = UINT64_C(0xffff0000);
1069	pCtx->csHid.u32Limit = 0x0000ffff;
1070	pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
1071	pCtx->csHid.Attr.n.u1Present = 1;
1072	pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ \| X86_SEL_TYPE_CODE;
1073
1074	pCtx->dsHid.u32Limit = 0x0000ffff;
1075	pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
1076	pCtx->dsHid.Attr.n.u1Present = 1;
1077	pCtx->dsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1078
1079	pCtx->esHid.u32Limit = 0x0000ffff;
1080	pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
1081	pCtx->esHid.Attr.n.u1Present = 1;
1082	pCtx->esHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1083
1084	pCtx->fsHid.u32Limit = 0x0000ffff;
1085	pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
1086	pCtx->fsHid.Attr.n.u1Present = 1;
1087	pCtx->fsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1088
1089	pCtx->gsHid.u32Limit = 0x0000ffff;
1090	pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
1091	pCtx->gsHid.Attr.n.u1Present = 1;
1092	pCtx->gsHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1093
1094	pCtx->ssHid.u32Limit = 0x0000ffff;
1095	pCtx->ssHid.Attr.n.u1Present = 1;
1096	pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
1097	pCtx->ssHid.Attr.n.u4Type = X86_SEL_TYPE_RW;
1098
1099	pCtx->idtr.cbIdt = 0xffff;
1100	pCtx->gdtr.cbGdt = 0xffff;
1101
1102	pCtx->ldtrHid.u32Limit = 0xffff;
1103	pCtx->ldtrHid.Attr.n.u1Present = 1;
1104	pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1105
1106	pCtx->trHid.u32Limit = 0xffff;
1107	pCtx->trHid.Attr.n.u1Present = 1;
1108	pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1109
1110	pCtx->dr[6] = X86_DR6_INIT_VAL;
1111	pCtx->dr[7] = X86_DR7_INIT_VAL;
1112
1113	pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1114	pCtx->fpu.FCW = 0x37f;
1115
1116	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1117	IA-32 Processor States Following Power-up, Reset, or INIT */
1118	pCtx->fpu.MXCSR = 0x1F80;
1119	pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1120	supports all bits, since a zero value here should be read as 0xffbf. */
1121
1122	/* Init PAT MSR */
1123	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1124
1125	/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
1126	* The Intel docs don't mention it.
1127	*/
1128	pCtx->msrEFER = 0;
1129	}
1130
1131
1132	/**
1133	* Resets the CPU.
1134	*
1135	* @returns VINF_SUCCESS.
1136	* @param pVM The VM handle.
1137	*/
1138	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1139	{
1140	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1141	{
1142	CPUMR3ResetCpu(&pVM->aCpus[i]);
1143
1144	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1145	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(&pVM->aCpus[i]);
1146
1147	/* Magic marker for searching in crash dumps. */
1148	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1149	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1150	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1151	#endif
1152	}
1153	}
1154
1155
1156	/**
1157	* Called both in pass 0 and the final pass.
1158	*
1159	* @param pVM The VM handle.
1160	* @param pSSM The saved state handle.
1161	*/
1162	static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1163	{
1164	/*
1165	* Save all the CPU ID leaves here so we can check them for compatibility
1166	* upon loading.
1167	*/
1168	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1169	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1170
1171	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1172	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1173
1174	SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1175	SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1176
1177	SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1178
1179	/*
1180	* Save a good portion of the raw CPU IDs as well as they may come in
1181	* handy when validating features for raw mode.
1182	*/
1183	CPUMCPUID aRawStd[16];
1184	for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1185	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1186	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1187	SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1188
1189	CPUMCPUID aRawExt[32];
1190	for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1191	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1192	SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1193	SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1194	}
1195
1196
1197	/**
1198	* Loads the CPU ID leaves saved by pass 0.
1199	*
1200	* @returns VBox status code.
1201	* @param pVM The VM handle.
1202	* @param pSSM The saved state handle.
1203	* @param uVersion The format version.
1204	*/
1205	static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1206	{
1207	AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1208
1209	/*
1210	* Define a bunch of macros for simplifying the code.
1211	*/
1212	/* Generic expression + failure message. */
1213	#define CPUID_CHECK_RET(expr, fmt) \
1214	do { \
1215	if (!(expr)) \
1216	{ \
1217	char pszMsg = RTStrAPrintf2 fmt; / lack of variadic macros sucks */ \
1218	if (fStrictCpuIdChecks) \
1219	{ \
1220	int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1221	RTStrFree(pszMsg); \
1222	return rcCpuid; \
1223	} \
1224	LogRel(("CPUM: %s\n", pszMsg)); \
1225	RTStrFree(pszMsg); \
1226	} \
1227	} while (0)
1228	#define CPUID_CHECK_WRN(expr, fmt) \
1229	do { \
1230	if (!(expr)) \
1231	LogRel(fmt); \
1232	} while (0)
1233
1234	/* For comparing two values and bitch if they differs. */
1235	#define CPUID_CHECK2_RET(what, host, saved) \
1236	do { \
1237	if ((host) != (saved)) \
1238	{ \
1239	if (fStrictCpuIdChecks) \
1240	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1241	N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1242	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1243	} \
1244	} while (0)
1245	#define CPUID_CHECK2_WRN(what, host, saved) \
1246	do { \
1247	if ((host) != (saved)) \
1248	LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1249	} while (0)
1250
1251	/* For checking raw cpu features (raw mode). */
1252	#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1253	do { \
1254	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1255	{ \
1256	if (fStrictCpuIdChecks) \
1257	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1258	N_(#bit " mismatch: host=%d saved=%d"), \
1259	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1260	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1261	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1262	} \
1263	} while (0)
1264	#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1265	do { \
1266	if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1267	LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1268	!!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1269	} while (0)
1270	#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1271
1272	/* For checking guest features. */
1273	#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1274	do { \
1275	if ( (aGuestCpuId##set [1].reg & bit) \
1276	&& !(aHostRaw##set [1].reg & bit) \
1277	&& !(aHostOverride##set [1].reg & bit) \
1278	&& !(aGuestOverride##set [1].reg & bit) \
1279	) \
1280	{ \
1281	if (fStrictCpuIdChecks) \
1282	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1283	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1284	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1285	} \
1286	} while (0)
1287	#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1288	do { \
1289	if ( (aGuestCpuId##set [1].reg & bit) \
1290	&& !(aHostRaw##set [1].reg & bit) \
1291	&& !(aHostOverride##set [1].reg & bit) \
1292	&& !(aGuestOverride##set [1].reg & bit) \
1293	) \
1294	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1295	} while (0)
1296	#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1297	do { \
1298	if ( (aGuestCpuId##set [1].reg & bit) \
1299	&& !(aHostRaw##set [1].reg & bit) \
1300	&& !(aHostOverride##set [1].reg & bit) \
1301	&& !(aGuestOverride##set [1].reg & bit) \
1302	) \
1303	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1304	} while (0)
1305	#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1306
1307	/* For checking guest features if AMD guest CPU. */
1308	#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1309	do { \
1310	if ( (aGuestCpuId##set [1].reg & bit) \
1311	&& fGuestAmd \
1312	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1313	&& !(aHostOverride##set [1].reg & bit) \
1314	&& !(aGuestOverride##set [1].reg & bit) \
1315	) \
1316	{ \
1317	if (fStrictCpuIdChecks) \
1318	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1319	N_(#bit " is not supported by the host but has already exposed to the guest")); \
1320	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1321	} \
1322	} while (0)
1323	#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1324	do { \
1325	if ( (aGuestCpuId##set [1].reg & bit) \
1326	&& fGuestAmd \
1327	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1328	&& !(aHostOverride##set [1].reg & bit) \
1329	&& !(aGuestOverride##set [1].reg & bit) \
1330	) \
1331	LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1332	} while (0)
1333	#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1334	do { \
1335	if ( (aGuestCpuId##set [1].reg & bit) \
1336	&& fGuestAmd \
1337	&& (!fGuestAmd \|\| !(aHostRaw##set [1].reg & bit)) \
1338	&& !(aHostOverride##set [1].reg & bit) \
1339	&& !(aGuestOverride##set [1].reg & bit) \
1340	) \
1341	LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1342	} while (0)
1343	#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1344
1345	/* For checking AMD features which have a corresponding bit in the standard
1346	range. (Intel defines very few bits in the extended feature sets.) */
1347	#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1348	do { \
1349	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1350	&& !(fHostAmd \
1351	? aHostRawExt[1].reg & (ExtBit) \
1352	: aHostRawStd[1].reg & (StdBit)) \
1353	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1354	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1355	) \
1356	{ \
1357	if (fStrictCpuIdChecks) \
1358	return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1359	N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1360	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1361	} \
1362	} while (0)
1363	#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1364	do { \
1365	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1366	&& !(fHostAmd \
1367	? aHostRawExt[1].reg & (ExtBit) \
1368	: aHostRawStd[1].reg & (StdBit)) \
1369	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1370	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1371	) \
1372	LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1373	} while (0)
1374	#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1375	do { \
1376	if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1377	&& !(fHostAmd \
1378	? aHostRawExt[1].reg & (ExtBit) \
1379	: aHostRawStd[1].reg & (StdBit)) \
1380	&& !(aHostOverrideExt[1].reg & (ExtBit)) \
1381	&& !(aGuestOverrideExt[1].reg & (ExtBit)) \
1382	) \
1383	LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1384	} while (0)
1385	#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1386
1387	/*
1388	* Load them into stack buffers first.
1389	*/
1390	CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1391	uint32_t cGuestCpuIdStd;
1392	int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1393	if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1394	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1395	SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1396
1397	CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1398	uint32_t cGuestCpuIdExt;
1399	rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1400	if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1401	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1402	SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1403
1404	CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1405	uint32_t cGuestCpuIdCentaur;
1406	rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1407	if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1408	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1409	SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1410
1411	CPUMCPUID GuestCpuIdDef;
1412	rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1413	AssertRCReturn(rc, rc);
1414
1415	CPUMCPUID aRawStd[16];
1416	uint32_t cRawStd;
1417	rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1418	if (cRawStd > RT_ELEMENTS(aRawStd))
1419	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1420	SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1421
1422	CPUMCPUID aRawExt[32];
1423	uint32_t cRawExt;
1424	rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1425	if (cRawExt > RT_ELEMENTS(aRawExt))
1426	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1427	rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1428	AssertRCReturn(rc, rc);
1429
1430	/*
1431	* Note that we support restoring less than the current amount of standard
1432	* leaves because we've been allowed more is newer version of VBox.
1433	*
1434	* So, pad new entries with the default.
1435	*/
1436	for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1437	aGuestCpuIdStd[i] = GuestCpuIdDef;
1438
1439	for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1440	aGuestCpuIdExt[i] = GuestCpuIdDef;
1441
1442	for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1443	aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1444
1445	for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1446	ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1447
1448	for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1449	ASMCpuId(i \| UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1450
1451	/*
1452	* Get the raw CPU IDs for the current host.
1453	*/
1454	CPUMCPUID aHostRawStd[16];
1455	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1456	ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1457
1458	CPUMCPUID aHostRawExt[32];
1459	for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1460	ASMCpuId(i \| UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1461
1462	/*
1463	* Get the host and guest overrides so we don't reject the state because
1464	* some feature was enabled thru these interfaces.
1465	* Note! We currently only need the feature leaves, so skip rest.
1466	*/
1467	PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1468	CPUMCPUID aGuestOverrideStd[2];
1469	memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1470	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1471
1472	CPUMCPUID aGuestOverrideExt[2];
1473	memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1474	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1475
1476	pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1477	CPUMCPUID aHostOverrideStd[2];
1478	memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1479	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1480
1481	CPUMCPUID aHostOverrideExt[2];
1482	memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1483	cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1484
1485	/*
1486	* This can be skipped.
1487	*/
1488	bool fStrictCpuIdChecks;
1489	CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1490
1491
1492
1493	/*
1494	* For raw-mode we'll require that the CPUs are very similar since we don't
1495	* intercept CPUID instructions for user mode applications.
1496	*/
1497	if (!HWACCMIsEnabled(pVM))
1498	{
1499	/* CPUID(0) */
1500	CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1501	&& aHostRawStd[0].ecx == aRawStd[0].ecx
1502	&& aHostRawStd[0].edx == aRawStd[0].edx,
1503	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1504	&aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1505	&aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1506	CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1507	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1508	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1509
1510	bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1511
1512	/* CPUID(1).eax */
1513	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1514	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1515	CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1516
1517	/* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1518	CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1519	CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1520
1521	/* CPUID(1).ecx */
1522	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1523	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1524	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1525	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1526	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1527	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1528	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1529	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1530	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1531	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1532	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1533	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1534	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1535	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1536	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1537	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1538	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1539	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1540	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1541	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1542	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1543	CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1544	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
1545	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
1546	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1547	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
1548	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
1549	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
1550	CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
1551	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1552	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1553	CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1554
1555	/* CPUID(1).edx */
1556	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1557	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1558	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
1559	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1560	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
1561	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
1562	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1563	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1564	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
1565	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1566	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1567	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1568	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1569	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1570	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1571	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
1572	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1573	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1574	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1575	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
1576	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1577	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
1578	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
1579	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
1580	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
1581	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
1582	CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
1583	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
1584	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
1585	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
1586	CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/);
1587	CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
1588
1589	/* CPUID(2) - config, mostly about caches. ignore. */
1590	/* CPUID(3) - processor serial number. ignore. */
1591	/* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
1592	/* CPUID(5) - mwait/monitor config. ignore. */
1593	/* CPUID(6) - power management. ignore. */
1594	/* CPUID(7) - ???. ignore. */
1595	/* CPUID(8) - ???. ignore. */
1596	/* CPUID(9) - DCA. ignore for now. */
1597	/* CPUID(a) - PeMo info. ignore for now. */
1598	/* CPUID(b) - topology info - takes ECX as input. ignore. */
1599
1600	/* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
1601	CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
1602	\|\| aHostRawStd[0].eax >= UINT32_C(0x0000000d),
1603	("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
1604	if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
1605	&& aHostRawStd[0].eax >= UINT32_C(0x0000000d))
1606	{
1607	CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
1608	CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
1609	CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
1610	CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
1611	}
1612
1613	/* CPUID(0x80000000) - same as CPUID(0) except for eax.
1614	Note! Intel have/is marking many of the fields here as reserved. We
1615	will verify them as if it's an AMD CPU. */
1616	CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
1617	\|\| !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
1618	(N_("Extended leaves was present on saved state host, but is missing on the current\n")));
1619	if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
1620	{
1621	CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
1622	&& aHostRawExt[0].ecx == aRawExt[0].ecx
1623	&& aHostRawExt[0].edx == aRawExt[0].edx,
1624	(N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1625	&aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
1626	&aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
1627	CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
1628
1629	/* CPUID(0x80000001).eax - same as CPUID(0).eax. */
1630	CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
1631	CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
1632	CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
1633	CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
1634	CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1635
1636	/* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
1637	CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
1638	CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
1639	CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
1640
1641	/* CPUID(0x80000001).ecx */
1642	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF);
1643	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
1644	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
1645	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
1646	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1647	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
1648	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
1649	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
1650	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
1651	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
1652	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
1653	CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
1654	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
1655	CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
1656	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1657	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1658	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1659	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1660	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1661	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1662	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1663	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1664	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1665	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1666	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1667	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1668	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1669	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1670	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1671	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1672	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1673	CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1674
1675	/* CPUID(0x80000001).edx */
1676	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
1677	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
1678	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
1679	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
1680	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
1681	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
1682	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
1683	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
1684	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
1685	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
1686	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /reserved/);
1687	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP);
1688	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
1689	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
1690	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
1691	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1692	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
1693	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
1694	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /reserved/);
1695	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /reserved/);
1696	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1697	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /reserved/);
1698	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1699	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
1700	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
1701	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1702	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1703	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1704	CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /reserved/);
1705	CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1706	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1707	CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1708
1709	/** @todo verify the rest as well. */
1710	}
1711	}
1712
1713
1714
1715	/*
1716	* Verify that we can support the features already exposed to the guest on
1717	* this host.
1718	*
1719	* Most of the features we're emulating requires intercepting instruction
1720	* and doing it the slow way, so there is no need to warn when they aren't
1721	* present in the host CPU. Thus we use IGN instead of EMU on these.
1722	*
1723	* Trailing comments:
1724	* "EMU" - Possible to emulate, could be lots of work and very slow.
1725	* "EMU?" - Can this be emulated?
1726	*/
1727	/* CPUID(1).ecx */
1728	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
1729	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
1730	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
1731	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1732	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
1733	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
1734	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
1735	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
1736	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
1737	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
1738	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
1739	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /reserved/ );
1740	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
1741	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
1742	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
1743	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
1744	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /reserved/);
1745	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /reserved/);
1746	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
1747	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
1748	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
1749	CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
1750	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
1751	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
1752	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /reserved/);
1753	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
1754	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
1755	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
1756	CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
1757	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /reserved/);
1758	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /reserved/);
1759	CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(31) /reserved/);
1760
1761	/* CPUID(1).edx */
1762	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
1763	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
1764	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
1765	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
1766	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1767	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1768	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
1769	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
1770	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1771	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
1772	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /reserved/);
1773	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
1774	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
1775	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
1776	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
1777	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1778	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
1779	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
1780	CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
1781	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
1782	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /reserved/);
1783	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
1784	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
1785	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1786	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1787	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
1788	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
1789	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
1790	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
1791	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
1792	CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /JMPE/IA64/); // -> EMU
1793	CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
1794
1795	/* CPUID(0x80000000). */
1796	if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
1797	&& aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
1798	{
1799	/** @todo deal with no 0x80000001 on the host. */
1800	bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
1801	bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
1802
1803	/* CPUID(0x80000001).ecx */
1804	CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF); // -> EMU
1805	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
1806	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
1807	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
1808	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
1809	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
1810	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
1811	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
1812	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
1813	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
1814	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
1815	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
1816	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
1817	CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
1818	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
1819	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
1820	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
1821	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
1822	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
1823	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
1824	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
1825	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
1826	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
1827	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
1828	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
1829	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
1830	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
1831	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
1832	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
1833	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
1834	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
1835	CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
1836
1837	/* CPUID(0x80000001).edx */
1838	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
1839	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
1840	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
1841	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
1842	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
1843	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
1844	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
1845	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
1846	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
1847	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
1848	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /reserved/);
1849	CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_SEP); // Intel: long mode only.
1850	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
1851	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
1852	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
1853	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
1854	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
1855	CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
1856	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /reserved/);
1857	CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /reserved/);
1858	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_NX);
1859	CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /reserved/);
1860	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
1861	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
1862	CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
1863	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1864	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAGE1GB);
1865	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_RDTSCP);
1866	CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /reserved/);
1867	CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_LONG_MODE);
1868	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1869	CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1870	}
1871
1872	/*
1873	* We're good, commit the CPU ID leaves.
1874	*/
1875	memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
1876	memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
1877	memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
1878	pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
1879
1880	#undef CPUID_CHECK_RET
1881	#undef CPUID_CHECK_WRN
1882	#undef CPUID_CHECK2_RET
1883	#undef CPUID_CHECK2_WRN
1884	#undef CPUID_RAW_FEATURE_RET
1885	#undef CPUID_RAW_FEATURE_WRN
1886	#undef CPUID_RAW_FEATURE_IGN
1887	#undef CPUID_GST_FEATURE_RET
1888	#undef CPUID_GST_FEATURE_WRN
1889	#undef CPUID_GST_FEATURE_EMU
1890	#undef CPUID_GST_FEATURE_IGN
1891	#undef CPUID_GST_FEATURE2_RET
1892	#undef CPUID_GST_FEATURE2_WRN
1893	#undef CPUID_GST_FEATURE2_EMU
1894	#undef CPUID_GST_FEATURE2_IGN
1895	#undef CPUID_GST_AMD_FEATURE_RET
1896	#undef CPUID_GST_AMD_FEATURE_WRN
1897	#undef CPUID_GST_AMD_FEATURE_EMU
1898	#undef CPUID_GST_AMD_FEATURE_IGN
1899
1900	return VINF_SUCCESS;
1901	}
1902
1903
1904	/**
1905	* Pass 0 live exec callback.
1906	*
1907	* @returns VINF_SSM_DONT_CALL_AGAIN.
1908	* @param pVM The VM handle.
1909	* @param pSSM The saved state handle.
1910	* @param uPass The pass (0).
1911	*/
1912	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1913	{
1914	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1915	cpumR3SaveCpuId(pVM, pSSM);
1916	return VINF_SSM_DONT_CALL_AGAIN;
1917	}
1918
1919
1920	/**
1921	* Execute state save operation.
1922	*
1923	* @returns VBox status code.
1924	* @param pVM VM Handle.
1925	* @param pSSM SSM operation handle.
1926	*/
1927	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1928	{
1929	/*
1930	* Save.
1931	*/
1932	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1933	{
1934	PVMCPU pVCpu = &pVM->aCpus[i];
1935
1936	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
1937	}
1938
1939	SSMR3PutU32(pSSM, pVM->cCpus);
1940	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1941	{
1942	PVMCPU pVCpu = &pVM->aCpus[i];
1943
1944	SSMR3PutMem(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest));
1945	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1946	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1947	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsr, sizeof(pVCpu->cpum.s.GuestMsr));
1948	}
1949
1950	cpumR3SaveCpuId(pVM, pSSM);
1951	return VINF_SUCCESS;
1952	}
1953
1954
1955	/**
1956	* Load a version 1.6 CPUMCTX structure.
1957	*
1958	* @returns VBox status code.
1959	* @param pVM VM Handle.
1960	* @param pCpumctx16 Version 1.6 CPUMCTX
1961	*/
1962	static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
1963	{
1964	#define CPUMCTX16_LOADREG(RegName) \
1965	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName;
1966
1967	#define CPUMCTX16_LOADDRXREG(RegName) \
1968	pVM->aCpus[0].cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
1969
1970	#define CPUMCTX16_LOADHIDREG(RegName) \
1971	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u64Base = pCpumctx16->RegName##Hid.u32Base; \
1972	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
1973	pVM->aCpus[0].cpum.s.Guest.RegName##Hid.Attr = pCpumctx16->RegName##Hid.Attr;
1974
1975	#define CPUMCTX16_LOADSEGREG(RegName) \
1976	pVM->aCpus[0].cpum.s.Guest.RegName = pCpumctx16->RegName; \
1977	CPUMCTX16_LOADHIDREG(RegName);
1978
1979	pVM->aCpus[0].cpum.s.Guest.fpu = pCpumctx16->fpu;
1980
1981	CPUMCTX16_LOADREG(rax);
1982	CPUMCTX16_LOADREG(rbx);
1983	CPUMCTX16_LOADREG(rcx);
1984	CPUMCTX16_LOADREG(rdx);
1985	CPUMCTX16_LOADREG(rdi);
1986	CPUMCTX16_LOADREG(rsi);
1987	CPUMCTX16_LOADREG(rbp);
1988	CPUMCTX16_LOADREG(esp);
1989	CPUMCTX16_LOADREG(rip);
1990	CPUMCTX16_LOADREG(rflags);
1991
1992	CPUMCTX16_LOADSEGREG(cs);
1993	CPUMCTX16_LOADSEGREG(ds);
1994	CPUMCTX16_LOADSEGREG(es);
1995	CPUMCTX16_LOADSEGREG(fs);
1996	CPUMCTX16_LOADSEGREG(gs);
1997	CPUMCTX16_LOADSEGREG(ss);
1998
1999	CPUMCTX16_LOADREG(r8);
2000	CPUMCTX16_LOADREG(r9);
2001	CPUMCTX16_LOADREG(r10);
2002	CPUMCTX16_LOADREG(r11);
2003	CPUMCTX16_LOADREG(r12);
2004	CPUMCTX16_LOADREG(r13);
2005	CPUMCTX16_LOADREG(r14);
2006	CPUMCTX16_LOADREG(r15);
2007
2008	CPUMCTX16_LOADREG(cr0);
2009	CPUMCTX16_LOADREG(cr2);
2010	CPUMCTX16_LOADREG(cr3);
2011	CPUMCTX16_LOADREG(cr4);
2012
2013	CPUMCTX16_LOADDRXREG(0);
2014	CPUMCTX16_LOADDRXREG(1);
2015	CPUMCTX16_LOADDRXREG(2);
2016	CPUMCTX16_LOADDRXREG(3);
2017	CPUMCTX16_LOADDRXREG(4);
2018	CPUMCTX16_LOADDRXREG(5);
2019	CPUMCTX16_LOADDRXREG(6);
2020	CPUMCTX16_LOADDRXREG(7);
2021
2022	pVM->aCpus[0].cpum.s.Guest.gdtr.cbGdt = pCpumctx16->gdtr.cbGdt;
2023	pVM->aCpus[0].cpum.s.Guest.gdtr.pGdt = pCpumctx16->gdtr.pGdt;
2024	pVM->aCpus[0].cpum.s.Guest.idtr.cbIdt = pCpumctx16->idtr.cbIdt;
2025	pVM->aCpus[0].cpum.s.Guest.idtr.pIdt = pCpumctx16->idtr.pIdt;
2026
2027	CPUMCTX16_LOADREG(ldtr);
2028	CPUMCTX16_LOADREG(tr);
2029
2030	pVM->aCpus[0].cpum.s.Guest.SysEnter = pCpumctx16->SysEnter;
2031
2032	CPUMCTX16_LOADREG(msrEFER);
2033	CPUMCTX16_LOADREG(msrSTAR);
2034	CPUMCTX16_LOADREG(msrPAT);
2035	CPUMCTX16_LOADREG(msrLSTAR);
2036	CPUMCTX16_LOADREG(msrCSTAR);
2037	CPUMCTX16_LOADREG(msrSFMASK);
2038	CPUMCTX16_LOADREG(msrKERNELGSBASE);
2039
2040	CPUMCTX16_LOADHIDREG(ldtr);
2041	CPUMCTX16_LOADHIDREG(tr);
2042
2043	#undef CPUMCTX16_LOADSEGREG
2044	#undef CPUMCTX16_LOADHIDREG
2045	#undef CPUMCTX16_LOADDRXREG
2046	#undef CPUMCTX16_LOADREG
2047	}
2048
2049
2050	/**
2051	* @copydoc FNSSMINTLOADPREP
2052	*/
2053	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2054	{
2055	NOREF(pSSM);
2056	pVM->cpum.s.fPendingRestore = true;
2057	return VINF_SUCCESS;
2058	}
2059
2060
2061	/**
2062	* @copydoc FNSSMINTLOADEXEC
2063	*/
2064	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2065	{
2066	/*
2067	* Validate version.
2068	*/
2069	if ( uVersion != CPUM_SAVED_STATE_VERSION
2070	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2071	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2072	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2073	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2074	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2075	{
2076	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2077	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2078	}
2079
2080	if (uPass == SSM_PASS_FINAL)
2081	{
2082	/*
2083	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2084	* really old SSM file versions.)
2085	*/
2086	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2087	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2088	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2089	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2090
2091	/*
2092	* Restore.
2093	*/
2094	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2095	{
2096	PVMCPU pVCpu = &pVM->aCpus[i];
2097	uint32_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2098	uint32_t uESP = pVCpu->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
2099
2100	SSMR3GetMem(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper));
2101	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2102	pVCpu->cpum.s.Hyper.esp = uESP;
2103	}
2104
2105	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2106	{
2107	CPUMCTX_VER1_6 cpumctx16;
2108	memset(&pVM->aCpus[0].cpum.s.Guest, 0, sizeof(pVM->aCpus[0].cpum.s.Guest));
2109	SSMR3GetMem(pSSM, &cpumctx16, sizeof(cpumctx16));
2110
2111	/* Save the old cpumctx state into the new one. */
2112	cpumR3LoadCPUM1_6(pVM, &cpumctx16);
2113
2114	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fUseFlags);
2115	SSMR3GetU32(pSSM, &pVM->aCpus[0].cpum.s.fChanged);
2116	}
2117	else
2118	{
2119	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2120	{
2121	uint32_t cCpus;
2122	int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2123	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2124	VERR_SSM_UNEXPECTED_DATA);
2125	}
2126	AssertLogRelMsgReturn( uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2127	\|\| pVM->cCpus == 1,
2128	("cCpus=%u\n", pVM->cCpus),
2129	VERR_SSM_UNEXPECTED_DATA);
2130
2131	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2132	{
2133	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.Guest, sizeof(pVM->aCpus[i].cpum.s.Guest));
2134	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fUseFlags);
2135	SSMR3GetU32(pSSM, &pVM->aCpus[i].cpum.s.fChanged);
2136	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2137	SSMR3GetMem(pSSM, &pVM->aCpus[i].cpum.s.GuestMsr, sizeof(pVM->aCpus[i].cpum.s.GuestMsr));
2138	}
2139	}
2140
2141	/* Older states does not set CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID for
2142	raw-mode guest, so we have to do it ourselves. */
2143	if ( uVersion <= CPUM_SAVED_STATE_VERSION_VER3_2
2144	&& !HWACCMIsEnabled(pVM))
2145	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2146	pVM->aCpus[iCpu].cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2147	}
2148
2149	pVM->cpum.s.fPendingRestore = false;
2150
2151	/*
2152	* Guest CPUIDs.
2153	*/
2154	if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2155	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2156
2157	/** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2158	* actually required. */
2159
2160	/*
2161	* Restore the CPUID leaves.
2162	*
2163	* Note that we support restoring less than the current amount of standard
2164	* leaves because we've been allowed more is newer version of VBox.
2165	*/
2166	uint32_t cElements;
2167	int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2168	if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2169	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2170	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2171
2172	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2173	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2174	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2175	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2176
2177	rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2178	if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2179	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2180	SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2181
2182	SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2183
2184	/*
2185	* Check that the basic cpuid id information is unchanged.
2186	*/
2187	/** @todo we should check the 64 bits capabilities too! */
2188	uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2189	ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2190	ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2191	uint32_t au32CpuIdSaved[8];
2192	rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2193	if (RT_SUCCESS(rc))
2194	{
2195	/* Ignore CPU stepping. */
2196	au32CpuId[4] &= 0xfffffff0;
2197	au32CpuIdSaved[4] &= 0xfffffff0;
2198
2199	/* Ignore APIC ID (AMD specs). */
2200	au32CpuId[5] &= ~0xff000000;
2201	au32CpuIdSaved[5] &= ~0xff000000;
2202
2203	/* Ignore the number of Logical CPUs (AMD specs). */
2204	au32CpuId[5] &= ~0x00ff0000;
2205	au32CpuIdSaved[5] &= ~0x00ff0000;
2206
2207	/* Ignore some advanced capability bits, that we don't expose to the guest. */
2208	au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2209	\| X86_CPUID_FEATURE_ECX_VMX
2210	\| X86_CPUID_FEATURE_ECX_SMX
2211	\| X86_CPUID_FEATURE_ECX_EST
2212	\| X86_CPUID_FEATURE_ECX_TM2
2213	\| X86_CPUID_FEATURE_ECX_CNTXID
2214	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2215	\| X86_CPUID_FEATURE_ECX_PDCM
2216	\| X86_CPUID_FEATURE_ECX_DCA
2217	\| X86_CPUID_FEATURE_ECX_X2APIC
2218	);
2219	au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2220	\| X86_CPUID_FEATURE_ECX_VMX
2221	\| X86_CPUID_FEATURE_ECX_SMX
2222	\| X86_CPUID_FEATURE_ECX_EST
2223	\| X86_CPUID_FEATURE_ECX_TM2
2224	\| X86_CPUID_FEATURE_ECX_CNTXID
2225	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2226	\| X86_CPUID_FEATURE_ECX_PDCM
2227	\| X86_CPUID_FEATURE_ECX_DCA
2228	\| X86_CPUID_FEATURE_ECX_X2APIC
2229	);
2230
2231	/* Make sure we don't forget to update the masks when enabling
2232	* features in the future.
2233	*/
2234	AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2235	( X86_CPUID_FEATURE_ECX_DTES64
2236	\| X86_CPUID_FEATURE_ECX_VMX
2237	\| X86_CPUID_FEATURE_ECX_SMX
2238	\| X86_CPUID_FEATURE_ECX_EST
2239	\| X86_CPUID_FEATURE_ECX_TM2
2240	\| X86_CPUID_FEATURE_ECX_CNTXID
2241	\| X86_CPUID_FEATURE_ECX_TPRUPDATE
2242	\| X86_CPUID_FEATURE_ECX_PDCM
2243	\| X86_CPUID_FEATURE_ECX_DCA
2244	\| X86_CPUID_FEATURE_ECX_X2APIC
2245	)));
2246	/* do the compare */
2247	if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2248	{
2249	if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2250	LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2251	"Saved=%.*Rhxs\n"
2252	"Real =%.*Rhxs\n",
2253	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2254	sizeof(au32CpuId), au32CpuId));
2255	else
2256	{
2257	LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2258	"Saved=%.*Rhxs\n"
2259	"Real =%.*Rhxs\n",
2260	sizeof(au32CpuIdSaved), au32CpuIdSaved,
2261	sizeof(au32CpuId), au32CpuId));
2262	rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2263	}
2264	}
2265	}
2266
2267	return rc;
2268	}
2269
2270
2271	/**
2272	* @copydoc FNSSMINTLOADPREP
2273	*/
2274	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2275	{
2276	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2277	return VINF_SUCCESS;
2278
2279	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2280	if (pVM->cpum.s.fPendingRestore)
2281	{
2282	LogRel(("CPUM: Missing state!\n"));
2283	return VERR_INTERNAL_ERROR_2;
2284	}
2285
2286	/* Notify PGM of the NXE states in case they've changed. */
2287	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2288	PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2289	return VINF_SUCCESS;
2290	}
2291
2292
2293	/**
2294	* Checks if the CPUM state restore is still pending.
2295	*
2296	* @returns true / false.
2297	* @param pVM The VM handle.
2298	*/
2299	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2300	{
2301	return pVM->cpum.s.fPendingRestore;
2302	}
2303
2304
2305	/**
2306	* Formats the EFLAGS value into mnemonics.
2307	*
2308	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2309	* @param efl The EFLAGS value.
2310	*/
2311	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2312	{
2313	/*
2314	* Format the flags.
2315	*/
2316	static const struct
2317	{
2318	const char pszSet; const char pszClear; uint32_t fFlag;
2319	} s_aFlags[] =
2320	{
2321	{ "vip",NULL, X86_EFL_VIP },
2322	{ "vif",NULL, X86_EFL_VIF },
2323	{ "ac", NULL, X86_EFL_AC },
2324	{ "vm", NULL, X86_EFL_VM },
2325	{ "rf", NULL, X86_EFL_RF },
2326	{ "nt", NULL, X86_EFL_NT },
2327	{ "ov", "nv", X86_EFL_OF },
2328	{ "dn", "up", X86_EFL_DF },
2329	{ "ei", "di", X86_EFL_IF },
2330	{ "tf", NULL, X86_EFL_TF },
2331	{ "nt", "pl", X86_EFL_SF },
2332	{ "nz", "zr", X86_EFL_ZF },
2333	{ "ac", "na", X86_EFL_AF },
2334	{ "po", "pe", X86_EFL_PF },
2335	{ "cy", "nc", X86_EFL_CF },
2336	};
2337	char *psz = pszEFlags;
2338	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2339	{
2340	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2341	if (pszAdd)
2342	{
2343	strcpy(psz, pszAdd);
2344	psz += strlen(pszAdd);
2345	*psz++ = ' ';
2346	}
2347	}
2348	psz[-1] = '\0';
2349	}
2350
2351
2352	/**
2353	* Formats a full register dump.
2354	*
2355	* @param pVM VM Handle.
2356	* @param pCtx The context to format.
2357	* @param pCtxCore The context core to format.
2358	* @param pHlp Output functions.
2359	* @param enmType The dump type.
2360	* @param pszPrefix Register name prefix.
2361	*/
2362	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2363	const char *pszPrefix)
2364	{
2365	NOREF(pVM);
2366
2367	/*
2368	* Format the EFLAGS.
2369	*/
2370	uint32_t efl = pCtxCore->eflags.u32;
2371	char szEFlags[80];
2372	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2373
2374	/*
2375	* Format the registers.
2376	*/
2377	switch (enmType)
2378	{
2379	case CPUMDUMPTYPE_TERSE:
2380	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2381	pHlp->pfnPrintf(pHlp,
2382	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2383	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2384	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2385	"%sr14=%016RX64 %sr15=%016RX64\n"
2386	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2387	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2388	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2389	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2390	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2391	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2392	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2393	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2394	else
2395	pHlp->pfnPrintf(pHlp,
2396	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2397	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2398	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2399	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2400	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2401	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2402	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
2403	break;
2404
2405	case CPUMDUMPTYPE_DEFAULT:
2406	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2407	pHlp->pfnPrintf(pHlp,
2408	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2409	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2410	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2411	"%sr14=%016RX64 %sr15=%016RX64\n"
2412	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2413	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2414	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2415	,
2416	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2417	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2418	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2419	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2420	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2421	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2422	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2423	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2424	else
2425	pHlp->pfnPrintf(pHlp,
2426	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2427	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2428	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2429	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2430	,
2431	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2432	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2433	pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
2434	pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
2435	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2436	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
2437	break;
2438
2439	case CPUMDUMPTYPE_VERBOSE:
2440	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2441	pHlp->pfnPrintf(pHlp,
2442	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2443	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2444	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2445	"%sr14=%016RX64 %sr15=%016RX64\n"
2446	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2447	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2448	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2449	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2450	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2451	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2452	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2453	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2454	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2455	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2456	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2457	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2458	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2459	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2460	,
2461	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2462	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2463	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2464	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2465	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
2466	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
2467	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
2468	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
2469	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
2470	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
2471	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2472	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2473	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2474	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2475	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2476	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2477	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2478	else
2479	pHlp->pfnPrintf(pHlp,
2480	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2481	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2482	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2483	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2484	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2485	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2486	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2487	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2488	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2489	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2490	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2491	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2492	,
2493	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2494	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2495	pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2496	pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2497	pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2498	pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2499	pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2500	pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2501	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2502	pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
2503	pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
2504	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2505
2506	pHlp->pfnPrintf(pHlp,
2507	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2508	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2509	,
2510	pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2511	pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2512	pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2513	pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2514	);
2515	unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2516	for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2517	{
2518	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2519	unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2520	char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2521	unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2522	uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2523	unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2524	/** @todo This isn't entirenly correct and needs more work! */
2525	pHlp->pfnPrintf(pHlp,
2526	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2527	pszPrefix, iST, pszPrefix, iFPR,
2528	pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2529	uTag, chSign, iInteger, u64Fraction, uExponent);
2530	if (pCtx->fpu.aRegs[0].au16[5] \|\| pCtx->fpu.aRegs[0].au16[6] \|\| pCtx->fpu.aRegs[0].au16[7])
2531	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2532	pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2533	else
2534	pHlp->pfnPrintf(pHlp, "\n");
2535	}
2536	for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2537	pHlp->pfnPrintf(pHlp,
2538	iXMM & 1
2539	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2540	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2541	pszPrefix, iXMM, iXMM < 10 ? " " : "",
2542	pCtx->fpu.aXMM[iXMM].au32[3],
2543	pCtx->fpu.aXMM[iXMM].au32[2],
2544	pCtx->fpu.aXMM[iXMM].au32[1],
2545	pCtx->fpu.aXMM[iXMM].au32[0]);
2546	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2547	if (pCtx->fpu.au32RsrvdRest[i])
2548	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2549	pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2550
2551	pHlp->pfnPrintf(pHlp,
2552	"%sEFER =%016RX64\n"
2553	"%sPAT =%016RX64\n"
2554	"%sSTAR =%016RX64\n"
2555	"%sCSTAR =%016RX64\n"
2556	"%sLSTAR =%016RX64\n"
2557	"%sSFMASK =%016RX64\n"
2558	"%sKERNELGSBASE =%016RX64\n",
2559	pszPrefix, pCtx->msrEFER,
2560	pszPrefix, pCtx->msrPAT,
2561	pszPrefix, pCtx->msrSTAR,
2562	pszPrefix, pCtx->msrCSTAR,
2563	pszPrefix, pCtx->msrLSTAR,
2564	pszPrefix, pCtx->msrSFMASK,
2565	pszPrefix, pCtx->msrKERNELGSBASE);
2566	break;
2567	}
2568	}
2569
2570
2571	/**
2572	* Display all cpu states and any other cpum info.
2573	*
2574	* @param pVM VM Handle.
2575	* @param pHlp The info helper functions.
2576	* @param pszArgs Arguments, ignored.
2577	*/
2578	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2579	{
2580	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2581	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2582	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2583	cpumR3InfoHost(pVM, pHlp, pszArgs);
2584	}
2585
2586
2587	/**
2588	* Parses the info argument.
2589	*
2590	* The argument starts with 'verbose', 'terse' or 'default' and then
2591	* continues with the comment string.
2592	*
2593	* @param pszArgs The pointer to the argument string.
2594	* @param penmType Where to store the dump type request.
2595	* @param ppszComment Where to store the pointer to the comment string.
2596	*/
2597	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2598	{
2599	if (!pszArgs)
2600	{
2601	*penmType = CPUMDUMPTYPE_DEFAULT;
2602	*ppszComment = "";
2603	}
2604	else
2605	{
2606	if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
2607	{
2608	pszArgs += 5;
2609	*penmType = CPUMDUMPTYPE_VERBOSE;
2610	}
2611	else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
2612	{
2613	pszArgs += 5;
2614	*penmType = CPUMDUMPTYPE_TERSE;
2615	}
2616	else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
2617	{
2618	pszArgs += 7;
2619	*penmType = CPUMDUMPTYPE_DEFAULT;
2620	}
2621	else
2622	*penmType = CPUMDUMPTYPE_DEFAULT;
2623	*ppszComment = RTStrStripL(pszArgs);
2624	}
2625	}
2626
2627
2628	/**
2629	* Display the guest cpu state.
2630	*
2631	* @param pVM VM Handle.
2632	* @param pHlp The info helper functions.
2633	* @param pszArgs Arguments, ignored.
2634	*/
2635	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2636	{
2637	CPUMDUMPTYPE enmType;
2638	const char *pszComment;
2639	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2640
2641	/* @todo SMP support! */
2642	PVMCPU pVCpu = VMMGetCpu(pVM);
2643	if (!pVCpu)
2644	pVCpu = &pVM->aCpus[0];
2645
2646	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2647
2648	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2649	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2650	}
2651
2652
2653	/**
2654	* Display the current guest instruction
2655	*
2656	* @param pVM VM Handle.
2657	* @param pHlp The info helper functions.
2658	* @param pszArgs Arguments, ignored.
2659	*/
2660	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2661	{
2662	NOREF(pszArgs);
2663
2664	/** @todo SMP support! */
2665	PVMCPU pVCpu = VMMGetCpu(pVM);
2666	if (!pVCpu)
2667	pVCpu = &pVM->aCpus[0];
2668
2669	char szInstruction[256];
2670	int rc = DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2671	if (RT_SUCCESS(rc))
2672	pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2673	}
2674
2675
2676	/**
2677	* Display the hypervisor cpu state.
2678	*
2679	* @param pVM VM Handle.
2680	* @param pHlp The info helper functions.
2681	* @param pszArgs Arguments, ignored.
2682	*/
2683	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2684	{
2685	CPUMDUMPTYPE enmType;
2686	const char *pszComment;
2687	/* @todo SMP */
2688	PVMCPU pVCpu = &pVM->aCpus[0];
2689
2690	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2691	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2692	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, pVCpu->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
2693	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2694	}
2695
2696
2697	/**
2698	* Display the host cpu state.
2699	*
2700	* @param pVM VM Handle.
2701	* @param pHlp The info helper functions.
2702	* @param pszArgs Arguments, ignored.
2703	*/
2704	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2705	{
2706	CPUMDUMPTYPE enmType;
2707	const char *pszComment;
2708	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2709	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2710
2711	/*
2712	* Format the EFLAGS.
2713	*/
2714	/* @todo SMP */
2715	PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2716	#if HC_ARCH_BITS == 32
2717	uint32_t efl = pCtx->eflags.u32;
2718	#else
2719	uint64_t efl = pCtx->rflags;
2720	#endif
2721	char szEFlags[80];
2722	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2723
2724	/*
2725	* Format the registers.
2726	*/
2727	#if HC_ARCH_BITS == 32
2728	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2729	if (!(pCtx->efer & MSR_K6_EFER_LMA))
2730	# endif
2731	{
2732	pHlp->pfnPrintf(pHlp,
2733	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2734	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2735	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2736	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2737	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2738	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2739	,
2740	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2741	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2742	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2743	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2744	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2745	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
2746	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2747	}
2748	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2749	else
2750	# endif
2751	#endif
2752	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2753	{
2754	pHlp->pfnPrintf(pHlp,
2755	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2756	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2757	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2758	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2759	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2760	"r14=%016RX64 r15=%016RX64\n"
2761	"iopl=%d %31s\n"
2762	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2763	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2764	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2765	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2766	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2767	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2768	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2769	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2770	,
2771	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2772	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2773	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2774	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2775	pCtx->r11, pCtx->r12, pCtx->r13,
2776	pCtx->r14, pCtx->r15,
2777	X86_EFL_GET_IOPL(efl), szEFlags,
2778	(RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
2779	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2780	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2781	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2782	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2783	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2784	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2785	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2786	}
2787	#endif
2788	}
2789
2790
2791	/**
2792	* Get L1 cache / TLS associativity.
2793	*/
2794	static const char getCacheAss(unsigned u, char pszBuf)
2795	{
2796	if (u == 0)
2797	return "res0 ";
2798	if (u == 1)
2799	return "direct";
2800	if (u == 255)
2801	return "fully";
2802	if (u >= 256)
2803	return "???";
2804
2805	RTStrPrintf(pszBuf, 16, "%d way", u);
2806	return pszBuf;
2807	}
2808
2809
2810	/**
2811	* Get L2 cache associativity.
2812	*/
2813	const char *getL2CacheAss(unsigned u)
2814	{
2815	switch (u)
2816	{
2817	case 0: return "off ";
2818	case 1: return "direct";
2819	case 2: return "2 way ";
2820	case 3: return "res3 ";
2821	case 4: return "4 way ";
2822	case 5: return "res5 ";
2823	case 6: return "8 way ";
2824	case 7: return "res7 ";
2825	case 8: return "16 way";
2826	case 9: return "res9 ";
2827	case 10: return "res10 ";
2828	case 11: return "res11 ";
2829	case 12: return "res12 ";
2830	case 13: return "res13 ";
2831	case 14: return "res14 ";
2832	case 15: return "fully ";
2833	default: return "????";
2834	}
2835	}
2836
2837
2838	/**
2839	* Display the guest CpuId leaves.
2840	*
2841	* @param pVM VM Handle.
2842	* @param pHlp The info helper functions.
2843	* @param pszArgs "terse", "default" or "verbose".
2844	*/
2845	static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2846	{
2847	/*
2848	* Parse the argument.
2849	*/
2850	unsigned iVerbosity = 1;
2851	if (pszArgs)
2852	{
2853	pszArgs = RTStrStripL(pszArgs);
2854	if (!strcmp(pszArgs, "terse"))
2855	iVerbosity--;
2856	else if (!strcmp(pszArgs, "verbose"))
2857	iVerbosity++;
2858	}
2859
2860	/*
2861	* Start cracking.
2862	*/
2863	CPUMCPUID Host;
2864	CPUMCPUID Guest;
2865	unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
2866
2867	pHlp->pfnPrintf(pHlp,
2868	" RAW Standard CPUIDs\n"
2869	" Function eax ebx ecx edx\n");
2870	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
2871	{
2872	Guest = pVM->cpum.s.aGuestCpuIdStd[i];
2873	ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
2874
2875	pHlp->pfnPrintf(pHlp,
2876	"Gst: %08x %08x %08x %08x %08x%s\n"
2877	"Hst: %08x %08x %08x %08x\n",
2878	i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2879	i <= cStdMax ? "" : "*",
2880	Host.eax, Host.ebx, Host.ecx, Host.edx);
2881	}
2882
2883	/*
2884	* If verbose, decode it.
2885	*/
2886	if (iVerbosity)
2887	{
2888	Guest = pVM->cpum.s.aGuestCpuIdStd[0];
2889	pHlp->pfnPrintf(pHlp,
2890	"Name: %.04s%.04s%.04s\n"
2891	"Supports: 0-%x\n",
2892	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
2893	}
2894
2895	/*
2896	* Get Features.
2897	*/
2898	bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
2899	pVM->cpum.s.aGuestCpuIdStd[0].ecx,
2900	pVM->cpum.s.aGuestCpuIdStd[0].edx);
2901	if (cStdMax >= 1 && iVerbosity)
2902	{
2903	static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
2904
2905	Guest = pVM->cpum.s.aGuestCpuIdStd[1];
2906	uint32_t uEAX = Guest.eax;
2907
2908	pHlp->pfnPrintf(pHlp,
2909	"Family: %d \tExtended: %d \tEffective: %d\n"
2910	"Model: %d \tExtended: %d \tEffective: %d\n"
2911	"Stepping: %d\n"
2912	"Type: %d (%s)\n"
2913	"APIC ID: %#04x\n"
2914	"Logical CPUs: %d\n"
2915	"CLFLUSH Size: %d\n"
2916	"Brand ID: %#04x\n",
2917	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
2918	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
2919	ASMGetCpuStepping(uEAX),
2920	(uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
2921	(Guest.ebx >> 24) & 0xff,
2922	(Guest.ebx >> 16) & 0xff,
2923	(Guest.ebx >> 8) & 0xff,
2924	(Guest.ebx >> 0) & 0xff);
2925	if (iVerbosity == 1)
2926	{
2927	uint32_t uEDX = Guest.edx;
2928	pHlp->pfnPrintf(pHlp, "Features EDX: ");
2929	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
2930	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
2931	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
2932	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
2933	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
2934	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
2935	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
2936	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
2937	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
2938	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
2939	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
2940	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
2941	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
2942	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
2943	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
2944	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
2945	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
2946	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
2947	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
2948	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
2949	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
2950	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
2951	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
2952	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
2953	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
2954	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
2955	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
2956	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
2957	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
2958	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
2959	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2960	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
2961	pHlp->pfnPrintf(pHlp, "\n");
2962
2963	uint32_t uECX = Guest.ecx;
2964	pHlp->pfnPrintf(pHlp, "Features ECX: ");
2965	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
2966	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
2967	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
2968	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
2969	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
2970	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
2971	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
2972	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
2973	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
2974	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
2975	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
2976	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
2977	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
2978	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
2979	if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
2980	if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
2981	if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
2982	if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
2983	if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
2984	if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
2985	if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
2986	if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
2987	if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
2988	if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
2989	if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
2990	if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
2991	if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
2992	if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
2993	if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
2994	if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
2995	if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
2996	if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
2997	pHlp->pfnPrintf(pHlp, "\n");
2998	}
2999	else
3000	{
3001	ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3002
3003	X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3004	X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3005	X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3006	X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3007
3008	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3009	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3010	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3011	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3012	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3013	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3014	pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3015	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3016	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3017	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3018	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3019	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3020	pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3021	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3022	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3023	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3024	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3025	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3026	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3027	pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3028	pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3029	pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3030	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3031	pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3032	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3033	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3034	pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3035	pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3036	pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3037	pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3038	pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3039	pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3040	pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3041
3042	pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3043	pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3044	pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3045	pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3046	pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3047	pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3048	pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3049	pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3050	pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3051	pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3052	pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3053	pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3054	pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3055	pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3056	pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3057	pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3058	pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3059	pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3060	pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3061	pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3062	pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3063	pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3064	pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3065	pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3066	pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3067	pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3068	pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3069	pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3070	pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3071	pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3072	pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3073	}
3074	}
3075	if (cStdMax >= 2 && iVerbosity)
3076	{
3077	/** @todo */
3078	}
3079
3080	/*
3081	* Extended.
3082	* Implemented after AMD specs.
3083	*/
3084	unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3085
3086	pHlp->pfnPrintf(pHlp,
3087	"\n"
3088	" RAW Extended CPUIDs\n"
3089	" Function eax ebx ecx edx\n");
3090	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3091	{
3092	Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3093	ASMCpuId(0x80000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3094
3095	pHlp->pfnPrintf(pHlp,
3096	"Gst: %08x %08x %08x %08x %08x%s\n"
3097	"Hst: %08x %08x %08x %08x\n",
3098	0x80000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3099	i <= cExtMax ? "" : "*",
3100	Host.eax, Host.ebx, Host.ecx, Host.edx);
3101	}
3102
3103	/*
3104	* Understandable output
3105	*/
3106	if (iVerbosity)
3107	{
3108	Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3109	pHlp->pfnPrintf(pHlp,
3110	"Ext Name: %.4s%.4s%.4s\n"
3111	"Ext Supports: 0x80000000-%#010x\n",
3112	&Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3113	}
3114
3115	if (iVerbosity && cExtMax >= 1)
3116	{
3117	Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3118	uint32_t uEAX = Guest.eax;
3119	pHlp->pfnPrintf(pHlp,
3120	"Family: %d \tExtended: %d \tEffective: %d\n"
3121	"Model: %d \tExtended: %d \tEffective: %d\n"
3122	"Stepping: %d\n"
3123	"Brand ID: %#05x\n",
3124	(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3125	(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3126	ASMGetCpuStepping(uEAX),
3127	Guest.ebx & 0xfff);
3128
3129	if (iVerbosity == 1)
3130	{
3131	uint32_t uEDX = Guest.edx;
3132	pHlp->pfnPrintf(pHlp, "Features EDX: ");
3133	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3134	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3135	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3136	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3137	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3138	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3139	if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3140	if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3141	if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3142	if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3143	if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3144	if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3145	if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3146	if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3147	if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3148	if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3149	if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3150	if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3151	if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3152	if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3153	if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3154	if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3155	if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3156	if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3157	if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3158	if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3159	if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3160	if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3161	if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3162	if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3163	if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3164	if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3165	pHlp->pfnPrintf(pHlp, "\n");
3166
3167	uint32_t uECX = Guest.ecx;
3168	pHlp->pfnPrintf(pHlp, "Features ECX: ");
3169	if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3170	if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3171	if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3172	if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3173	if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3174	if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3175	if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3176	if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3177	if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3178	if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3179	if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3180	if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3181	if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3182	if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3183	for (unsigned iBit = 5; iBit < 32; iBit++)
3184	if (uECX & RT_BIT(iBit))
3185	pHlp->pfnPrintf(pHlp, " %d", iBit);
3186	pHlp->pfnPrintf(pHlp, "\n");
3187	}
3188	else
3189	{
3190	ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3191
3192	uint32_t uEdxGst = Guest.edx;
3193	uint32_t uEdxHst = Host.edx;
3194	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3195	pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3196	pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3197	pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3198	pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3199	pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3200	pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3201	pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3202	pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3203	pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3204	pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3205	pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3206	pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3207	pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3208	pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3209	pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3210	pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3211	pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3212	pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3213	pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3214	pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3215	pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3216	pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3217	pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3218	pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3219	pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3220	pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3221	pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3222	pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3223	pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3224	pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3225	pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3226	pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3227
3228	uint32_t uEcxGst = Guest.ecx;
3229	uint32_t uEcxHst = Host.ecx;
3230	pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3231	pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3232	pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3233	pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3234	pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3235	pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3236	pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3237	pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3238	pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3239	pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3240	pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3241	pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3242	pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3243	pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3244	pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3245	}
3246	}
3247
3248	if (iVerbosity && cExtMax >= 2)
3249	{
3250	char szString[443+1] = {0};
3251	uint32_t pu32 = (uint32_t )szString;
3252	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3253	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3254	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3255	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3256	if (cExtMax >= 3)
3257	{
3258	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3259	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3260	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3261	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3262	}
3263	if (cExtMax >= 4)
3264	{
3265	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3266	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3267	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3268	*pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3269	}
3270	pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3271	}
3272
3273	if (iVerbosity && cExtMax >= 5)
3274	{
3275	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3276	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3277	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3278	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3279	char sz1[32];
3280	char sz2[32];
3281
3282	pHlp->pfnPrintf(pHlp,
3283	"TLB 2/4M Instr/Uni: %s %3d entries\n"
3284	"TLB 2/4M Data: %s %3d entries\n",
3285	getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3286	getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3287	pHlp->pfnPrintf(pHlp,
3288	"TLB 4K Instr/Uni: %s %3d entries\n"
3289	"TLB 4K Data: %s %3d entries\n",
3290	getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3291	getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3292	pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3293	"L1 Instr Cache Lines Per Tag: %d\n"
3294	"L1 Instr Cache Associativity: %s\n"
3295	"L1 Instr Cache Size: %d KB\n",
3296	(uEDX >> 0) & 0xff,
3297	(uEDX >> 8) & 0xff,
3298	getCacheAss((uEDX >> 16) & 0xff, sz1),
3299	(uEDX >> 24) & 0xff);
3300	pHlp->pfnPrintf(pHlp,
3301	"L1 Data Cache Line Size: %d bytes\n"
3302	"L1 Data Cache Lines Per Tag: %d\n"
3303	"L1 Data Cache Associativity: %s\n"
3304	"L1 Data Cache Size: %d KB\n",
3305	(uECX >> 0) & 0xff,
3306	(uECX >> 8) & 0xff,
3307	getCacheAss((uECX >> 16) & 0xff, sz1),
3308	(uECX >> 24) & 0xff);
3309	}
3310
3311	if (iVerbosity && cExtMax >= 6)
3312	{
3313	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3314	uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3315	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3316
3317	pHlp->pfnPrintf(pHlp,
3318	"L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3319	"L2 TLB 2/4M Data: %s %4d entries\n",
3320	getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3321	getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3322	pHlp->pfnPrintf(pHlp,
3323	"L2 TLB 4K Instr/Uni: %s %4d entries\n"
3324	"L2 TLB 4K Data: %s %4d entries\n",
3325	getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3326	getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3327	pHlp->pfnPrintf(pHlp,
3328	"L2 Cache Line Size: %d bytes\n"
3329	"L2 Cache Lines Per Tag: %d\n"
3330	"L2 Cache Associativity: %s\n"
3331	"L2 Cache Size: %d KB\n",
3332	(uEDX >> 0) & 0xff,
3333	(uEDX >> 8) & 0xf,
3334	getL2CacheAss((uEDX >> 12) & 0xf),
3335	(uEDX >> 16) & 0xffff);
3336	}
3337
3338	if (iVerbosity && cExtMax >= 7)
3339	{
3340	uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3341
3342	pHlp->pfnPrintf(pHlp, "APM Features: ");
3343	if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3344	if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3345	if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3346	if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3347	if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3348	if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3349	for (unsigned iBit = 6; iBit < 32; iBit++)
3350	if (uEDX & RT_BIT(iBit))
3351	pHlp->pfnPrintf(pHlp, " %d", iBit);
3352	pHlp->pfnPrintf(pHlp, "\n");
3353	}
3354
3355	if (iVerbosity && cExtMax >= 8)
3356	{
3357	uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3358	uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3359
3360	pHlp->pfnPrintf(pHlp,
3361	"Physical Address Width: %d bits\n"
3362	"Virtual Address Width: %d bits\n"
3363	"Guest Physical Address Width: %d bits\n",
3364	(uEAX >> 0) & 0xff,
3365	(uEAX >> 8) & 0xff,
3366	(uEAX >> 16) & 0xff);
3367	pHlp->pfnPrintf(pHlp,
3368	"Physical Core Count: %d\n",
3369	(uECX >> 0) & 0xff);
3370	}
3371
3372
3373	/*
3374	* Centaur.
3375	*/
3376	unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3377
3378	pHlp->pfnPrintf(pHlp,
3379	"\n"
3380	" RAW Centaur CPUIDs\n"
3381	" Function eax ebx ecx edx\n");
3382	for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3383	{
3384	Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3385	ASMCpuId(0xc0000000 \| i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3386
3387	pHlp->pfnPrintf(pHlp,
3388	"Gst: %08x %08x %08x %08x %08x%s\n"
3389	"Hst: %08x %08x %08x %08x\n",
3390	0xc0000000 \| i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3391	i <= cCentaurMax ? "" : "*",
3392	Host.eax, Host.ebx, Host.ecx, Host.edx);
3393	}
3394
3395	/*
3396	* Understandable output
3397	*/
3398	if (iVerbosity)
3399	{
3400	Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3401	pHlp->pfnPrintf(pHlp,
3402	"Centaur Supports: 0xc0000000-%#010x\n",
3403	Guest.eax);
3404	}
3405
3406	if (iVerbosity && cCentaurMax >= 1)
3407	{
3408	ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3409	uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3410	uint32_t uEdxHst = Host.edx;
3411
3412	if (iVerbosity == 1)
3413	{
3414	pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3415	if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3416	if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3417	if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3418	if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3419	if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3420	if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3421	if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3422	if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3423	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3424	if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3425	if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3426	if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3427	if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3428	if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3429	if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3430	for (unsigned iBit = 14; iBit < 32; iBit++)
3431	if (uEdxGst & RT_BIT(iBit))
3432	pHlp->pfnPrintf(pHlp, " %d", iBit);
3433	pHlp->pfnPrintf(pHlp, "\n");
3434	}
3435	else
3436	{
3437	pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3438	pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3439	pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3440	pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3441	pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3442	pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3443	pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3444	pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3445	pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3446	/* possibly indicating MM/HE and MM/HE-E on older chips... */
3447	pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3448	pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3449	pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3450	pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3451	pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3452	pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3453	for (unsigned iBit = 14; iBit < 32; iBit++)
3454	if ((uEdxGst \| uEdxHst) & RT_BIT(iBit))
3455	pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3456	pHlp->pfnPrintf(pHlp, "\n");
3457	}
3458	}
3459	}
3460
3461
3462	/**
3463	* Structure used when disassembling and instructions in DBGF.
3464	* This is used so the reader function can get the stuff it needs.
3465	*/
3466	typedef struct CPUMDISASSTATE
3467	{
3468	/** Pointer to the CPU structure. */
3469	PDISCPUSTATE pCpu;
3470	/** The VM handle. */
3471	PVM pVM;
3472	/** The VMCPU handle. */
3473	PVMCPU pVCpu;
3474	/** Pointer to the first byte in the segment. */
3475	RTGCUINTPTR GCPtrSegBase;
3476	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3477	RTGCUINTPTR GCPtrSegEnd;
3478	/** The size of the segment minus 1. */
3479	RTGCUINTPTR cbSegLimit;
3480	/** Pointer to the current page - R3 Ptr. */
3481	void const *pvPageR3;
3482	/** Pointer to the current page - GC Ptr. */
3483	RTGCPTR pvPageGC;
3484	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3485	PGMPAGEMAPLOCK PageMapLock;
3486	/** Whether the PageMapLock is valid or not. */
3487	bool fLocked;
3488	/** 64 bits mode or not. */
3489	bool f64Bits;
3490	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3491
3492
3493	/**
3494	* Instruction reader.
3495	*
3496	* @returns VBox status code.
3497	* @param PtrSrc Address to read from.
3498	* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
3499	* @param pu8Dst Where to store the bytes.
3500	* @param cbRead Number of bytes to read.
3501	* @param uDisCpu Pointer to the disassembler cpu state.
3502	* In this context it's always pointer to the Core of a DBGFDISASSTATE.
3503	*/
3504	static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t pu8Dst, unsigned cbRead, void uDisCpu)
3505	{
3506	PDISCPUSTATE pCpu = (PDISCPUSTATE)uDisCpu;
3507	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->apvUserData[0];
3508	Assert(cbRead > 0);
3509	for (;;)
3510	{
3511	RTGCUINTPTR GCPtr = PtrSrc + pState->GCPtrSegBase;
3512
3513	/* Need to update the page translation? */
3514	if ( !pState->pvPageR3
3515	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3516	{
3517	int rc = VINF_SUCCESS;
3518
3519	/* translate the address */
3520	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3521	if ( MMHyperIsInsideArea(pState->pVM, pState->pvPageGC)
3522	&& !HWACCMIsEnabled(pState->pVM))
3523	{
3524	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3525	if (!pState->pvPageR3)
3526	rc = VERR_INVALID_POINTER;
3527	}
3528	else
3529	{
3530	/* Release mapping lock previously acquired. */
3531	if (pState->fLocked)
3532	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3533	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3534	pState->fLocked = RT_SUCCESS_NP(rc);
3535	}
3536	if (RT_FAILURE(rc))
3537	{
3538	pState->pvPageR3 = NULL;
3539	return rc;
3540	}
3541	}
3542
3543	/* check the segment limit */
3544	if (!pState->f64Bits && PtrSrc > pState->cbSegLimit)
3545	return VERR_OUT_OF_SELECTOR_BOUNDS;
3546
3547	/* calc how much we can read */
3548	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3549	if (!pState->f64Bits)
3550	{
3551	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3552	if (cb > cbSeg && cbSeg)
3553	cb = cbSeg;
3554	}
3555	if (cb > cbRead)
3556	cb = cbRead;
3557
3558	/* read and advance */
3559	memcpy(pu8Dst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3560	cbRead -= cb;
3561	if (!cbRead)
3562	return VINF_SUCCESS;
3563	pu8Dst += cb;
3564	PtrSrc += cb;
3565	}
3566	}
3567
3568
3569	/**
3570	* Disassemble an instruction and return the information in the provided structure.
3571	*
3572	* @returns VBox status code.
3573	* @param pVM VM Handle
3574	* @param pVCpu VMCPU Handle
3575	* @param pCtx CPU context
3576	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3577	* @param pCpu Disassembly state
3578	* @param pszPrefix String prefix for logging (debug only)
3579	*
3580	*/
3581	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
3582	{
3583	CPUMDISASSTATE State;
3584	int rc;
3585
3586	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3587	State.pCpu = pCpu;
3588	State.pvPageGC = 0;
3589	State.pvPageR3 = NULL;
3590	State.pVM = pVM;
3591	State.pVCpu = pVCpu;
3592	State.fLocked = false;
3593	State.f64Bits = false;
3594
3595	/*
3596	* Get selector information.
3597	*/
3598	if ( (pCtx->cr0 & X86_CR0_PE)
3599	&& pCtx->eflags.Bits.u1VM == 0)
3600	{
3601	if (CPUMAreHiddenSelRegsValid(pVCpu))
3602	{
3603	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->csHid.Attr.n.u1Long;
3604	State.GCPtrSegBase = pCtx->csHid.u64Base;
3605	State.GCPtrSegEnd = pCtx->csHid.u32Limit + 1 + (RTGCUINTPTR)pCtx->csHid.u64Base;
3606	State.cbSegLimit = pCtx->csHid.u32Limit;
3607	pCpu->mode = (State.f64Bits)
3608	? CPUMODE_64BIT
3609	: pCtx->csHid.Attr.n.u1DefBig
3610	? CPUMODE_32BIT
3611	: CPUMODE_16BIT;
3612	}
3613	else
3614	{
3615	DBGFSELINFO SelInfo;
3616
3617	rc = SELMR3GetShadowSelectorInfo(pVM, pCtx->cs, &SelInfo);
3618	if (RT_FAILURE(rc))
3619	{
3620	AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3621	return rc;
3622	}
3623
3624	/*
3625	* Validate the selector.
3626	*/
3627	rc = DBGFR3SelInfoValidateCS(&SelInfo, pCtx->ss);
3628	if (RT_FAILURE(rc))
3629	{
3630	AssertMsgFailed(("SELMSelInfoValidateCS failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
3631	return rc;
3632	}
3633	State.GCPtrSegBase = SelInfo.GCPtrBase;
3634	State.GCPtrSegEnd = SelInfo.cbLimit + 1 + (RTGCUINTPTR)SelInfo.GCPtrBase;
3635	State.cbSegLimit = SelInfo.cbLimit;
3636	pCpu->mode = SelInfo.u.Raw.Gen.u1DefBig ? CPUMODE_32BIT : CPUMODE_16BIT;
3637	}
3638	}
3639	else
3640	{
3641	/* real or V86 mode */
3642	pCpu->mode = CPUMODE_16BIT;
3643	State.GCPtrSegBase = pCtx->cs * 16;
3644	State.GCPtrSegEnd = 0xFFFFFFFF;
3645	State.cbSegLimit = 0xFFFFFFFF;
3646	}
3647
3648	/*
3649	* Disassemble the instruction.
3650	*/
3651	pCpu->pfnReadBytes = cpumR3DisasInstrRead;
3652	pCpu->apvUserData[0] = &State;
3653
3654	uint32_t cbInstr;
3655	#ifndef LOG_ENABLED
3656	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, NULL);
3657	if (RT_SUCCESS(rc))
3658	{
3659	#else
3660	char szOutput[160];
3661	rc = DISInstr(pCpu, GCPtrPC, 0, &cbInstr, &szOutput[0]);
3662	if (RT_SUCCESS(rc))
3663	{
3664	/* log it */
3665	if (pszPrefix)
3666	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3667	else
3668	Log(("%s", szOutput));
3669	#endif
3670	rc = VINF_SUCCESS;
3671	}
3672	else
3673	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs, GCPtrPC, rc));
3674
3675	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3676	if (State.fLocked)
3677	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3678
3679	return rc;
3680	}
3681
3682	#ifdef DEBUG
3683
3684	/**
3685	* Disassemble an instruction and dump it to the log
3686	*
3687	* @returns VBox status code.
3688	* @param pVM VM Handle
3689	* @param pVCpu VMCPU Handle
3690	* @param pCtx CPU context
3691	* @param pc GC instruction pointer
3692	* @param pszPrefix String prefix for logging
3693	*
3694	* @deprecated Use DBGFR3DisasInstrCurrentLog().
3695	*/
3696	VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
3697	{
3698	DISCPUSTATE Cpu;
3699	CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pc, &Cpu, pszPrefix);
3700	}
3701
3702
3703	/**
3704	* Debug helper - Saves guest context on raw mode entry (for fatal dump)
3705	*
3706	* @internal
3707	*/
3708	VMMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
3709	{
3710	/** @todo SMP support!! */
3711	pVM->cpum.s.GuestEntry = *CPUMQueryGuestCtxPtr(VMMGetCpu(pVM));
3712	}
3713
3714	#endif /* DEBUG */
3715
3716	/**
3717	* API for controlling a few of the CPU features found in CR4.
3718	*
3719	* Currently only X86_CR4_TSD is accepted as input.
3720	*
3721	* @returns VBox status code.
3722	*
3723	* @param pVM The VM handle.
3724	* @param fOr The CR4 OR mask.
3725	* @param fAnd The CR4 AND mask.
3726	*/
3727	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3728	{
3729	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3730	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3731
3732	pVM->cpum.s.CR4.OrMask &= fAnd;
3733	pVM->cpum.s.CR4.OrMask \|= fOr;
3734
3735	return VINF_SUCCESS;
3736	}
3737
3738
3739	/**
3740	* Gets a pointer to the array of standard CPUID leaves.
3741	*
3742	* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
3743	*
3744	* @returns Pointer to the standard CPUID leaves (read-only).
3745	* @param pVM The VM handle.
3746	* @remark Intended for PATM.
3747	*/
3748	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
3749	{
3750	return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
3751	}
3752
3753
3754	/**
3755	* Gets a pointer to the array of extended CPUID leaves.
3756	*
3757	* CPUMGetGuestCpuIdExtMax() give the size of the array.
3758	*
3759	* @returns Pointer to the extended CPUID leaves (read-only).
3760	* @param pVM The VM handle.
3761	* @remark Intended for PATM.
3762	*/
3763	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
3764	{
3765	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
3766	}
3767
3768
3769	/**
3770	* Gets a pointer to the array of centaur CPUID leaves.
3771	*
3772	* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
3773	*
3774	* @returns Pointer to the centaur CPUID leaves (read-only).
3775	* @param pVM The VM handle.
3776	* @remark Intended for PATM.
3777	*/
3778	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
3779	{
3780	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
3781	}
3782
3783
3784	/**
3785	* Gets a pointer to the default CPUID leaf.
3786	*
3787	* @returns Pointer to the default CPUID leaf (read-only).
3788	* @param pVM The VM handle.
3789	* @remark Intended for PATM.
3790	*/
3791	VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
3792	{
3793	return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
3794	}
3795
3796
3797	/**
3798	* Transforms the guest CPU state to raw-ring mode.
3799	*
3800	* This function will change the any of the cs and ss register with DPL=0 to DPL=1.
3801	*
3802	* @returns VBox status. (recompiler failure)
3803	* @param pVCpu The VMCPU handle.
3804	* @param pCtxCore The context core (for trap usage).
3805	* @see @ref pg_raw
3806	*/
3807	VMMR3DECL(int) CPUMR3RawEnter(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore)
3808	{
3809	PVM pVM = pVCpu->CTX_SUFF(pVM);
3810
3811	Assert(!pVCpu->cpum.s.fRawEntered);
3812	Assert(!pVCpu->cpum.s.fRemEntered);
3813	if (!pCtxCore)
3814	pCtxCore = CPUMCTX2CORE(&pVCpu->cpum.s.Guest);
3815
3816	/*
3817	* Are we in Ring-0?
3818	*/
3819	if ( pCtxCore->ss && (pCtxCore->ss & X86_SEL_RPL) == 0
3820	&& !pCtxCore->eflags.Bits.u1VM)
3821	{
3822	/*
3823	* Enter execution mode.
3824	*/
3825	PATMRawEnter(pVM, pCtxCore);
3826
3827	/*
3828	* Set CPL to Ring-1.
3829	*/
3830	pCtxCore->ss \|= 1;
3831	if (pCtxCore->cs && (pCtxCore->cs & X86_SEL_RPL) == 0)
3832	pCtxCore->cs \|= 1;
3833	}
3834	else
3835	{
3836	AssertMsg((pCtxCore->ss & X86_SEL_RPL) >= 2 \|\| pCtxCore->eflags.Bits.u1VM,
3837	("ring-1 code not supported\n"));
3838	/*
3839	* PATM takes care of IOPL and IF flags for Ring-3 and Ring-2 code as well.
3840	*/
3841	PATMRawEnter(pVM, pCtxCore);
3842	}
3843
3844	/*
3845	* Invalidate the hidden registers.
3846	*/
3847	pVCpu->cpum.s.fChanged \|= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3848
3849	/*
3850	* Assert sanity.
3851	*/
3852	AssertMsg((pCtxCore->eflags.u32 & X86_EFL_IF), ("X86_EFL_IF is clear\n"));
3853	AssertReleaseMsg( pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL)
3854	\|\| pCtxCore->eflags.Bits.u1VM,
3855	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3856	Assert((pVCpu->cpum.s.Guest.cr0 & (X86_CR0_PG \| X86_CR0_WP \| X86_CR0_PE)) == (X86_CR0_PG \| X86_CR0_PE \| X86_CR0_WP));
3857
3858	pCtxCore->eflags.u32 \|= X86_EFL_IF; /* paranoia */
3859
3860	pVCpu->cpum.s.fRawEntered = true;
3861	return VINF_SUCCESS;
3862	}
3863
3864
3865	/**
3866	* Transforms the guest CPU state from raw-ring mode to correct values.
3867	*
3868	* This function will change any selector registers with DPL=1 to DPL=0.
3869	*
3870	* @returns Adjusted rc.
3871	* @param pVCpu The VMCPU handle.
3872	* @param rc Raw mode return code
3873	* @param pCtxCore The context core (for trap usage).
3874	* @see @ref pg_raw
3875	*/
3876	VMMR3DECL(int) CPUMR3RawLeave(PVMCPU pVCpu, PCPUMCTXCORE pCtxCore, int rc)
3877	{
3878	PVM pVM = pVCpu->CTX_SUFF(pVM);
3879
3880	/*
3881	* Don't leave if we've already left (in GC).
3882	*/
3883	Assert(pVCpu->cpum.s.fRawEntered);
3884	Assert(!pVCpu->cpum.s.fRemEntered);
3885	if (!pVCpu->cpum.s.fRawEntered)
3886	return rc;
3887	pVCpu->cpum.s.fRawEntered = false;
3888
3889	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3890	if (!pCtxCore)
3891	pCtxCore = CPUMCTX2CORE(pCtx);
3892	Assert(pCtxCore->eflags.Bits.u1VM \|\| (pCtxCore->ss & X86_SEL_RPL));
3893	AssertMsg(pCtxCore->eflags.Bits.u1VM \|\| pCtxCore->eflags.Bits.u2IOPL < (unsigned)(pCtxCore->ss & X86_SEL_RPL),
3894	("X86_EFL_IOPL=%d CPL=%d\n", pCtxCore->eflags.Bits.u2IOPL, pCtxCore->ss & X86_SEL_RPL));
3895
3896	/*
3897	* Are we executing in raw ring-1?
3898	*/
3899	if ( (pCtxCore->ss & X86_SEL_RPL) == 1
3900	&& !pCtxCore->eflags.Bits.u1VM)
3901	{
3902	/*
3903	* Leave execution mode.
3904	*/
3905	PATMRawLeave(pVM, pCtxCore, rc);
3906	/* Not quite sure if this is really required, but shouldn't harm (too much anyways). */
3907	/** @todo See what happens if we remove this. */
3908	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3909	pCtxCore->ds &= ~X86_SEL_RPL;
3910	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3911	pCtxCore->es &= ~X86_SEL_RPL;
3912	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3913	pCtxCore->fs &= ~X86_SEL_RPL;
3914	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3915	pCtxCore->gs &= ~X86_SEL_RPL;
3916
3917	/*
3918	* Ring-1 selector => Ring-0.
3919	*/
3920	pCtxCore->ss &= ~X86_SEL_RPL;
3921	if ((pCtxCore->cs & X86_SEL_RPL) == 1)
3922	pCtxCore->cs &= ~X86_SEL_RPL;
3923	}
3924	else
3925	{
3926	/*
3927	* PATM is taking care of the IOPL and IF flags for us.
3928	*/
3929	PATMRawLeave(pVM, pCtxCore, rc);
3930	if (!pCtxCore->eflags.Bits.u1VM)
3931	{
3932	/** @todo See what happens if we remove this. */
3933	if ((pCtxCore->ds & X86_SEL_RPL) == 1)
3934	pCtxCore->ds &= ~X86_SEL_RPL;
3935	if ((pCtxCore->es & X86_SEL_RPL) == 1)
3936	pCtxCore->es &= ~X86_SEL_RPL;
3937	if ((pCtxCore->fs & X86_SEL_RPL) == 1)
3938	pCtxCore->fs &= ~X86_SEL_RPL;
3939	if ((pCtxCore->gs & X86_SEL_RPL) == 1)
3940	pCtxCore->gs &= ~X86_SEL_RPL;
3941	}
3942	}
3943
3944	return rc;
3945	}
3946
3947
3948	/**
3949	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3950	*
3951	* Only REM should ever call this function!
3952	*
3953	* @returns The changed flags.
3954	* @param pVCpu The VMCPU handle.
3955	* @param puCpl Where to return the current privilege level (CPL).
3956	*/
3957	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3958	{
3959	Assert(!pVCpu->cpum.s.fRawEntered);
3960	Assert(!pVCpu->cpum.s.fRemEntered);
3961
3962	/*
3963	* Get the CPL first.
3964	*/
3965	*puCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.s.Guest));
3966
3967	/*
3968	* Get and reset the flags, leaving CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID set.
3969	*/
3970	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3971	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID; /* leave it set */
3972
3973	/** @todo change the switcher to use the fChanged flags. */
3974	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3975	{
3976	fFlags \|= CPUM_CHANGED_FPU_REM;
3977	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3978	}
3979
3980	pVCpu->cpum.s.fRemEntered = true;
3981	return fFlags;
3982	}
3983
3984
3985	/**
3986	* Leaves REM and works the CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID flag.
3987	*
3988	* @param pVCpu The virtual CPU handle.
3989	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3990	* registers.
3991	*/
3992	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3993	{
3994	Assert(!pVCpu->cpum.s.fRawEntered);
3995	Assert(pVCpu->cpum.s.fRemEntered);
3996
3997	if (fNoOutOfSyncSels)
3998	pVCpu->cpum.s.fChanged &= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3999	else
4000	pVCpu->cpum.s.fChanged \|= ~CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
4001
4002	pVCpu->cpum.s.fRemEntered = false;
4003	}
4004

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 40082

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