VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 48653

Last change on this file since 48653 was 48646, checked in by vboxsync, 11 years ago

VMM/CPUM: Clarify by explicit comment that the msrApicBase shouldn't be added to CPUMCTX.
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1/* $Id: CPUM.cpp 48646 2013-09-24 08:03:21Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/assert.h>
58#include <iprt/asm-amd64-x86.h>
59#include <iprt/string.h>
60#include <iprt/mp.h>
61#include <iprt/cpuset.h>
62#include "internal/pgm.h"
63
64
65/*******************************************************************************
66* Defined Constants And Macros *
67*******************************************************************************/
68/** The current saved state version. */
69#define CPUM_SAVED_STATE_VERSION 14
70/** The current saved state version before using SSMR3PutStruct. */
71#define CPUM_SAVED_STATE_VERSION_MEM 13
72/** The saved state version before introducing the MSR size field. */
73#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
74/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
75 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
76#define CPUM_SAVED_STATE_VERSION_VER3_2 11
77/** The saved state version of 3.0 and 3.1 trunk before the teleportation
78 * changes. */
79#define CPUM_SAVED_STATE_VERSION_VER3_0 10
80/** The saved state version for the 2.1 trunk before the MSR changes. */
81#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
82/** The saved state version of 2.0, used for backwards compatibility. */
83#define CPUM_SAVED_STATE_VERSION_VER2_0 8
84/** The saved state version of 1.6, used for backwards compatibility. */
85#define CPUM_SAVED_STATE_VERSION_VER1_6 6
86
87
88/**
89 * This was used in the saved state up to the early life of version 14.
90 *
91 * It indicates that we may have some out-of-sync hidden segement registers.
92 * It is only relevant for raw-mode.
93 */
94#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
95
96
97/*******************************************************************************
98* Structures and Typedefs *
99*******************************************************************************/
100
101/**
102 * What kind of cpu info dump to perform.
103 */
104typedef enum CPUMDUMPTYPE
105{
106 CPUMDUMPTYPE_TERSE,
107 CPUMDUMPTYPE_DEFAULT,
108 CPUMDUMPTYPE_VERBOSE
109} CPUMDUMPTYPE;
110/** Pointer to a cpu info dump type. */
111typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
112
113
114/*******************************************************************************
115* Internal Functions *
116*******************************************************************************/
117static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
118static int cpumR3CpuIdInit(PVM pVM);
119static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
130
131
132/*******************************************************************************
133* Global Variables *
134*******************************************************************************/
135/** Saved state field descriptors for CPUMCTX. */
136static const SSMFIELD g_aCpumCtxFields[] =
137{
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
173 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
174 SSMFIELD_ENTRY( CPUMCTX, rdi),
175 SSMFIELD_ENTRY( CPUMCTX, rsi),
176 SSMFIELD_ENTRY( CPUMCTX, rbp),
177 SSMFIELD_ENTRY( CPUMCTX, rax),
178 SSMFIELD_ENTRY( CPUMCTX, rbx),
179 SSMFIELD_ENTRY( CPUMCTX, rdx),
180 SSMFIELD_ENTRY( CPUMCTX, rcx),
181 SSMFIELD_ENTRY( CPUMCTX, rsp),
182 SSMFIELD_ENTRY( CPUMCTX, rflags),
183 SSMFIELD_ENTRY( CPUMCTX, rip),
184 SSMFIELD_ENTRY( CPUMCTX, r8),
185 SSMFIELD_ENTRY( CPUMCTX, r9),
186 SSMFIELD_ENTRY( CPUMCTX, r10),
187 SSMFIELD_ENTRY( CPUMCTX, r11),
188 SSMFIELD_ENTRY( CPUMCTX, r12),
189 SSMFIELD_ENTRY( CPUMCTX, r13),
190 SSMFIELD_ENTRY( CPUMCTX, r14),
191 SSMFIELD_ENTRY( CPUMCTX, r15),
192 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
193 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
194 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
195 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
196 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
197 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
198 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, cr0),
229 SSMFIELD_ENTRY( CPUMCTX, cr2),
230 SSMFIELD_ENTRY( CPUMCTX, cr3),
231 SSMFIELD_ENTRY( CPUMCTX, cr4),
232 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
237 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
239 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
241 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
244 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
245 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
246 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
248 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
250 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
251 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
252 /* msrApicBase is not included here, it resides in the APIC device state. */
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
265 SSMFIELD_ENTRY_TERM()
266};
267
268/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
269 * registeres changed. */
270static const SSMFIELD g_aCpumCtxFieldsMem[] =
271{
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
306 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
307 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
308 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
309 SSMFIELD_ENTRY( CPUMCTX, rdi),
310 SSMFIELD_ENTRY( CPUMCTX, rsi),
311 SSMFIELD_ENTRY( CPUMCTX, rbp),
312 SSMFIELD_ENTRY( CPUMCTX, rax),
313 SSMFIELD_ENTRY( CPUMCTX, rbx),
314 SSMFIELD_ENTRY( CPUMCTX, rdx),
315 SSMFIELD_ENTRY( CPUMCTX, rcx),
316 SSMFIELD_ENTRY( CPUMCTX, rsp),
317 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
318 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
319 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
321 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
323 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
325 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
327 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
328 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
329 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
330 SSMFIELD_ENTRY( CPUMCTX, rflags),
331 SSMFIELD_ENTRY( CPUMCTX, rip),
332 SSMFIELD_ENTRY( CPUMCTX, r8),
333 SSMFIELD_ENTRY( CPUMCTX, r9),
334 SSMFIELD_ENTRY( CPUMCTX, r10),
335 SSMFIELD_ENTRY( CPUMCTX, r11),
336 SSMFIELD_ENTRY( CPUMCTX, r12),
337 SSMFIELD_ENTRY( CPUMCTX, r13),
338 SSMFIELD_ENTRY( CPUMCTX, r14),
339 SSMFIELD_ENTRY( CPUMCTX, r15),
340 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
356 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
357 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
358 SSMFIELD_ENTRY( CPUMCTX, cr0),
359 SSMFIELD_ENTRY( CPUMCTX, cr2),
360 SSMFIELD_ENTRY( CPUMCTX, cr3),
361 SSMFIELD_ENTRY( CPUMCTX, cr4),
362 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
364 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
365 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
366 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
367 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
368 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
369 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
370 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
371 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
372 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
374 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
375 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
377 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
379 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
381 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
382 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
383 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
384 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
386 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
387 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
388 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
389 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
393 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
394 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
395 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
396 SSMFIELD_ENTRY_TERM()
397};
398
399/** Saved state field descriptors for CPUMCTX_VER1_6. */
400static const SSMFIELD g_aCpumCtxFieldsV16[] =
401{
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
436 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
437 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
438 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
439 SSMFIELD_ENTRY( CPUMCTX, rdi),
440 SSMFIELD_ENTRY( CPUMCTX, rsi),
441 SSMFIELD_ENTRY( CPUMCTX, rbp),
442 SSMFIELD_ENTRY( CPUMCTX, rax),
443 SSMFIELD_ENTRY( CPUMCTX, rbx),
444 SSMFIELD_ENTRY( CPUMCTX, rdx),
445 SSMFIELD_ENTRY( CPUMCTX, rcx),
446 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
447 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
448 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
450 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
451 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
453 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
455 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
457 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
458 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
459 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
460 SSMFIELD_ENTRY( CPUMCTX, rflags),
461 SSMFIELD_ENTRY( CPUMCTX, rip),
462 SSMFIELD_ENTRY( CPUMCTX, r8),
463 SSMFIELD_ENTRY( CPUMCTX, r9),
464 SSMFIELD_ENTRY( CPUMCTX, r10),
465 SSMFIELD_ENTRY( CPUMCTX, r11),
466 SSMFIELD_ENTRY( CPUMCTX, r12),
467 SSMFIELD_ENTRY( CPUMCTX, r13),
468 SSMFIELD_ENTRY( CPUMCTX, r14),
469 SSMFIELD_ENTRY( CPUMCTX, r15),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
485 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
486 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
487 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
488 SSMFIELD_ENTRY( CPUMCTX, cr0),
489 SSMFIELD_ENTRY( CPUMCTX, cr2),
490 SSMFIELD_ENTRY( CPUMCTX, cr3),
491 SSMFIELD_ENTRY( CPUMCTX, cr4),
492 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
493 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
495 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
496 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
497 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
498 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
499 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
500 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
501 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
502 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
503 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
504 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
505 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
506 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
507 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
509 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
510 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
512 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
514 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
515 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
516 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
517 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
519 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
520 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
521 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
522 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
523 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
524 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
528 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
531 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
532 SSMFIELD_ENTRY_TERM()
533};
534
535
536/**
537 * Initializes the CPUM.
538 *
539 * @returns VBox status code.
540 * @param pVM Pointer to the VM.
541 */
542VMMR3DECL(int) CPUMR3Init(PVM pVM)
543{
544 LogFlow(("CPUMR3Init\n"));
545
546 /*
547 * Assert alignment and sizes.
548 */
549 AssertCompileMemberAlignment(VM, cpum.s, 32);
550 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
551 AssertCompileSizeAlignment(CPUMCTX, 64);
552 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
553 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
554 AssertCompileMemberAlignment(VM, cpum, 64);
555 AssertCompileMemberAlignment(VM, aCpus, 64);
556 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
557 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
558
559 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
560 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
561 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
562
563 /* Calculate the offset from CPUMCPU to CPUM. */
564 for (VMCPUID i = 0; i < pVM->cCpus; i++)
565 {
566 PVMCPU pVCpu = &pVM->aCpus[i];
567
568 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
569 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
570 }
571
572 /*
573 * Check that the CPU supports the minimum features we require.
574 */
575 if (!ASMHasCpuId())
576 {
577 Log(("The CPU doesn't support CPUID!\n"));
578 return VERR_UNSUPPORTED_CPU;
579 }
580 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
581 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
582
583 /* Setup the CR4 AND and OR masks used in the switcher */
584 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
585 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
586 {
587 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
588 /* No FXSAVE implies no SSE */
589 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
590 pVM->cpum.s.CR4.OrMask = 0;
591 }
592 else
593 {
594 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
595 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
596 }
597
598 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
599 {
600 Log(("The CPU doesn't support MMX!\n"));
601 return VERR_UNSUPPORTED_CPU;
602 }
603 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
604 {
605 Log(("The CPU doesn't support TSC!\n"));
606 return VERR_UNSUPPORTED_CPU;
607 }
608 /* Bogus on AMD? */
609 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
610 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
611
612 /*
613 * Detect the host CPU vendor.
614 * (The guest CPU vendor is re-detected later on.)
615 */
616 uint32_t uEAX, uEBX, uECX, uEDX;
617 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
618 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
619 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
620
621 /*
622 * Setup hypervisor startup values.
623 */
624
625 /*
626 * Register saved state data item.
627 */
628 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
629 NULL, cpumR3LiveExec, NULL,
630 NULL, cpumR3SaveExec, NULL,
631 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
632 if (RT_FAILURE(rc))
633 return rc;
634
635 /*
636 * Register info handlers and registers with the debugger facility.
637 */
638 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
639 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
640 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
641 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
642 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
643 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
644
645 rc = cpumR3DbgInit(pVM);
646 if (RT_FAILURE(rc))
647 return rc;
648
649 /*
650 * Initialize the Guest CPUID state.
651 */
652 rc = cpumR3CpuIdInit(pVM);
653 if (RT_FAILURE(rc))
654 return rc;
655 CPUMR3Reset(pVM);
656 return VINF_SUCCESS;
657}
658
659
660/**
661 * Detect the CPU vendor give n the
662 *
663 * @returns The vendor.
664 * @param uEAX EAX from CPUID(0).
665 * @param uEBX EBX from CPUID(0).
666 * @param uECX ECX from CPUID(0).
667 * @param uEDX EDX from CPUID(0).
668 */
669static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
670{
671 if (ASMIsValidStdRange(uEAX))
672 {
673 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
674 return CPUMCPUVENDOR_AMD;
675
676 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
677 return CPUMCPUVENDOR_INTEL;
678
679 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
680 return CPUMCPUVENDOR_VIA;
681
682 /** @todo detect the other buggers... */
683 }
684
685 return CPUMCPUVENDOR_UNKNOWN;
686}
687
688
689/**
690 * Fetches overrides for a CPUID leaf.
691 *
692 * @returns VBox status code.
693 * @param pLeaf The leaf to load the overrides into.
694 * @param pCfgNode The CFGM node containing the overrides
695 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
696 * @param iLeaf The CPUID leaf number.
697 */
698static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
699{
700 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
701 if (pLeafNode)
702 {
703 uint32_t u32;
704 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
705 if (RT_SUCCESS(rc))
706 pLeaf->eax = u32;
707 else
708 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
709
710 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
711 if (RT_SUCCESS(rc))
712 pLeaf->ebx = u32;
713 else
714 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
715
716 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
717 if (RT_SUCCESS(rc))
718 pLeaf->ecx = u32;
719 else
720 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
721
722 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
723 if (RT_SUCCESS(rc))
724 pLeaf->edx = u32;
725 else
726 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
727
728 }
729 return VINF_SUCCESS;
730}
731
732
733/**
734 * Load the overrides for a set of CPUID leaves.
735 *
736 * @returns VBox status code.
737 * @param paLeaves The leaf array.
738 * @param cLeaves The number of leaves.
739 * @param uStart The start leaf number.
740 * @param pCfgNode The CFGM node containing the overrides
741 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
742 */
743static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
744{
745 for (uint32_t i = 0; i < cLeaves; i++)
746 {
747 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
748 if (RT_FAILURE(rc))
749 return rc;
750 }
751
752 return VINF_SUCCESS;
753}
754
755/**
756 * Init a set of host CPUID leaves.
757 *
758 * @returns VBox status code.
759 * @param paLeaves The leaf array.
760 * @param cLeaves The number of leaves.
761 * @param uStart The start leaf number.
762 * @param pCfgNode The /CPUM/HostCPUID/ node.
763 */
764static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
765{
766 /* Using the ECX variant for all of them can't hurt... */
767 for (uint32_t i = 0; i < cLeaves; i++)
768 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
769
770 /* Load CPUID leaf override; we currently don't care if the user
771 specifies features the host CPU doesn't support. */
772 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
773}
774
775
776/**
777 * Initializes the emulated CPU's cpuid information.
778 *
779 * @returns VBox status code.
780 * @param pVM Pointer to the VM.
781 */
782static int cpumR3CpuIdInit(PVM pVM)
783{
784 PCPUM pCPUM = &pVM->cpum.s;
785 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
786 uint32_t i;
787 int rc;
788
789#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
790 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
791 { \
792 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
793 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
794 }
795#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
796 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
797 { \
798 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
799 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
800 }
801
802 /*
803 * Read the configuration.
804 */
805 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
806 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
807 * completely overridden by VirtualBox custom strings. Some
808 * CPUID information is withheld, like the cache info. */
809 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
810 AssertRCReturn(rc, rc);
811
812 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
813 * When non-zero CPUID features that could cause portability issues will be
814 * stripped. The higher the value the more features gets stripped. Higher
815 * values should only be used when older CPUs are involved since it may
816 * harm performance and maybe also cause problems with specific guests. */
817 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
818 AssertRCReturn(rc, rc);
819
820 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
821
822 /*
823 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
824 * been overridden).
825 */
826 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
827 * Overrides the host CPUID leaf values used for calculating the guest CPUID
828 * leaves. This can be used to preserve the CPUID values when moving a VM to a
829 * different machine. Another use is restricting (or extending) the feature set
830 * exposed to the guest. */
831 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
832 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
833 AssertRCReturn(rc, rc);
834 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
835 AssertRCReturn(rc, rc);
836 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
837 AssertRCReturn(rc, rc);
838
839 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
840 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
841
842 /*
843 * Determine the default leaf.
844 *
845 * Intel returns values of the highest standard function, while AMD
846 * returns zeros. VIA on the other hand seems to returning nothing or
847 * perhaps some random garbage, we don't try to duplicate this behavior.
848 */
849 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
850 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
851 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
852
853 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
854 * Expose CMPXCHG16B to the guest if supported by the host.
855 */
856 bool fCmpXchg16b;
857 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
858
859 bool fMonitor;
860 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true); AssertRCReturn(rc, rc);
861
862 /* Cpuid 1 & 0x80000001:
863 * Only report features we can support.
864 *
865 * Note! When enabling new features the Synthetic CPU and Portable CPUID
866 * options may require adjusting (i.e. stripping what was enabled).
867 */
868 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
869 | X86_CPUID_FEATURE_EDX_VME
870 | X86_CPUID_FEATURE_EDX_DE
871 | X86_CPUID_FEATURE_EDX_PSE
872 | X86_CPUID_FEATURE_EDX_TSC
873 | X86_CPUID_FEATURE_EDX_MSR
874 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
875 | X86_CPUID_FEATURE_EDX_MCE
876 | X86_CPUID_FEATURE_EDX_CX8
877 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
878 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
879 //| X86_CPUID_FEATURE_EDX_SEP
880 | X86_CPUID_FEATURE_EDX_MTRR
881 | X86_CPUID_FEATURE_EDX_PGE
882 | X86_CPUID_FEATURE_EDX_MCA
883 | X86_CPUID_FEATURE_EDX_CMOV
884 | X86_CPUID_FEATURE_EDX_PAT
885 | X86_CPUID_FEATURE_EDX_PSE36
886 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
887 | X86_CPUID_FEATURE_EDX_CLFSH
888 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
889 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
890 | X86_CPUID_FEATURE_EDX_MMX
891 | X86_CPUID_FEATURE_EDX_FXSR
892 | X86_CPUID_FEATURE_EDX_SSE
893 | X86_CPUID_FEATURE_EDX_SSE2
894 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
895 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
896 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
897 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
898 | 0;
899 pCPUM->aGuestCpuIdStd[1].ecx &= 0
900 | X86_CPUID_FEATURE_ECX_SSE3
901 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
902 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
903 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
904 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
905 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
906 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
907 | X86_CPUID_FEATURE_ECX_SSSE3
908 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
909 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
910 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
911 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
912 /* ECX Bit 21 - x2APIC support - not yet. */
913 // | X86_CPUID_FEATURE_ECX_X2APIC
914 /* ECX Bit 23 - POPCNT instruction. */
915 //| X86_CPUID_FEATURE_ECX_POPCNT
916 | 0;
917 if (pCPUM->u8PortableCpuIdLevel > 0)
918 {
919 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
920 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
921 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
922 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
923 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
924 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
925 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
926 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
927
928 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
929 | X86_CPUID_FEATURE_EDX_PSN
930 | X86_CPUID_FEATURE_EDX_DS
931 | X86_CPUID_FEATURE_EDX_ACPI
932 | X86_CPUID_FEATURE_EDX_SS
933 | X86_CPUID_FEATURE_EDX_TM
934 | X86_CPUID_FEATURE_EDX_PBE
935 )));
936 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
937 | X86_CPUID_FEATURE_ECX_DTES64
938 | X86_CPUID_FEATURE_ECX_CPLDS
939 | X86_CPUID_FEATURE_ECX_VMX
940 | X86_CPUID_FEATURE_ECX_SMX
941 | X86_CPUID_FEATURE_ECX_EST
942 | X86_CPUID_FEATURE_ECX_TM2
943 | X86_CPUID_FEATURE_ECX_CNTXID
944 | X86_CPUID_FEATURE_ECX_FMA
945 | X86_CPUID_FEATURE_ECX_CX16
946 | X86_CPUID_FEATURE_ECX_TPRUPDATE
947 | X86_CPUID_FEATURE_ECX_PDCM
948 | X86_CPUID_FEATURE_ECX_DCA
949 | X86_CPUID_FEATURE_ECX_MOVBE
950 | X86_CPUID_FEATURE_ECX_AES
951 | X86_CPUID_FEATURE_ECX_POPCNT
952 | X86_CPUID_FEATURE_ECX_XSAVE
953 | X86_CPUID_FEATURE_ECX_OSXSAVE
954 | X86_CPUID_FEATURE_ECX_AVX
955 )));
956 }
957
958 /* Cpuid 0x80000001:
959 * Only report features we can support.
960 *
961 * Note! When enabling new features the Synthetic CPU and Portable CPUID
962 * options may require adjusting (i.e. stripping what was enabled).
963 *
964 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
965 */
966 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
967 | X86_CPUID_AMD_FEATURE_EDX_VME
968 | X86_CPUID_AMD_FEATURE_EDX_DE
969 | X86_CPUID_AMD_FEATURE_EDX_PSE
970 | X86_CPUID_AMD_FEATURE_EDX_TSC
971 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
972 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
973 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
974 | X86_CPUID_AMD_FEATURE_EDX_CX8
975 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
976 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
977 //| X86_CPUID_EXT_FEATURE_EDX_SEP
978 | X86_CPUID_AMD_FEATURE_EDX_MTRR
979 | X86_CPUID_AMD_FEATURE_EDX_PGE
980 | X86_CPUID_AMD_FEATURE_EDX_MCA
981 | X86_CPUID_AMD_FEATURE_EDX_CMOV
982 | X86_CPUID_AMD_FEATURE_EDX_PAT
983 | X86_CPUID_AMD_FEATURE_EDX_PSE36
984 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
985 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
986 | X86_CPUID_AMD_FEATURE_EDX_MMX
987 | X86_CPUID_AMD_FEATURE_EDX_FXSR
988 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
989 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
990 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
991 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
992 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
993 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
994 | 0;
995 pCPUM->aGuestCpuIdExt[1].ecx &= 0
996 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
997 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
998 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
999 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1000 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1001 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1002 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1003 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1004 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1005 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1006 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1007 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1008 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1009 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1010 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1011 | 0;
1012 if (pCPUM->u8PortableCpuIdLevel > 0)
1013 {
1014 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1015 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1016 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1017 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1018 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1019 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1020 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1021
1022 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1023 | X86_CPUID_AMD_FEATURE_ECX_SVM
1024 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1025 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1026 | X86_CPUID_AMD_FEATURE_ECX_ABM
1027 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1028 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1029 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1030 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1031 | X86_CPUID_AMD_FEATURE_ECX_IBS
1032 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1033 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1034 | X86_CPUID_AMD_FEATURE_ECX_WDT
1035 | UINT32_C(0xffffc000)
1036 )));
1037 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1038 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1039 | RT_BIT(18)
1040 | RT_BIT(19)
1041 | RT_BIT(21)
1042 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1043 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1044 | RT_BIT(28)
1045 )));
1046 }
1047
1048 /*
1049 * Apply the Synthetic CPU modifications. (TODO: move this up)
1050 */
1051 if (pCPUM->fSyntheticCpu)
1052 {
1053 static const char s_szVendor[13] = "VirtualBox ";
1054 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1055
1056 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1057
1058 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1059 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1060
1061 /* 0: Vendor */
1062 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1063 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1064 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1065
1066 /* 1.eax: Version information. family : model : stepping */
1067 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1068
1069 /* Leaves 2 - 4 are Intel only - zero them out */
1070 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1071 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1072 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1073
1074 /* Leaf 5 = monitor/mwait */
1075
1076 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1077 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1078 /* AMD only - set to zero. */
1079 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1080
1081 /* 0x800000001: shared feature bits are set dynamically. */
1082 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1083
1084 /* 0x800000002-4: Processor Name String Identifier. */
1085 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1086 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1087 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1088 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1089 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1090 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1091 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1092 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1093 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1094 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1095 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1096 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1097
1098 /* 0x800000005-7 - reserved -> zero */
1099 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1100 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1101 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1102
1103 /* 0x800000008: only the max virtual and physical address size. */
1104 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1105 }
1106
1107 /*
1108 * Hide HTT, multicode, SMP, whatever.
1109 * (APIC-ID := 0 and #LogCpus := 0)
1110 */
1111 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1112#ifdef VBOX_WITH_MULTI_CORE
1113 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1114 && pVM->cCpus > 1)
1115 {
1116 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1117 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1118 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1119 }
1120#endif
1121
1122 /* Cpuid 2:
1123 * Intel: Cache and TLB information
1124 * AMD: Reserved
1125 * VIA: Reserved
1126 * Safe to expose; restrict the number of calls to 1 for the portable case.
1127 */
1128 if ( pCPUM->u8PortableCpuIdLevel > 0
1129 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1130 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1131 {
1132 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1133 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1134 }
1135
1136 /* Cpuid 3:
1137 * Intel: EAX, EBX - reserved (transmeta uses these)
1138 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1139 * AMD: Reserved
1140 * VIA: Reserved
1141 * Safe to expose
1142 */
1143 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1144 {
1145 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1146 if (pCPUM->u8PortableCpuIdLevel > 0)
1147 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1148 }
1149
1150 /* Cpuid 4:
1151 * Intel: Deterministic Cache Parameters Leaf
1152 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1153 * AMD: Reserved
1154 * VIA: Reserved
1155 * Safe to expose, except for EAX:
1156 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1157 * Bits 31-26: Maximum number of processor cores in this physical package**
1158 * Note: These SMP values are constant regardless of ECX
1159 */
1160 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1161 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1162#ifdef VBOX_WITH_MULTI_CORE
1163 if ( pVM->cCpus > 1
1164 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1165 {
1166 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1167 /* One logical processor with possibly multiple cores. */
1168 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1169 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1170 }
1171#endif
1172
1173 /* Cpuid 5: Monitor/mwait Leaf
1174 * Intel: ECX, EDX - reserved
1175 * EAX, EBX - Smallest and largest monitor line size
1176 * AMD: EDX - reserved
1177 * EAX, EBX - Smallest and largest monitor line size
1178 * ECX - extensions (ignored for now)
1179 * VIA: Reserved
1180 * Safe to expose
1181 */
1182 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1183 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1184
1185 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1186 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1187 * Expose MWAIT extended features to the guest. For now we expose
1188 * just MWAIT break on interrupt feature (bit 1).
1189 */
1190 bool fMWaitExtensions;
1191 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1192 if (fMWaitExtensions)
1193 {
1194 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1195 /* @todo: for now we just expose host's MWAIT C-states, although conceptually
1196 it shall be part of our power management virtualization model */
1197#if 0
1198 /* MWAIT sub C-states */
1199 pCPUM->aGuestCpuIdStd[5].edx =
1200 (0 << 0) /* 0 in C0 */ |
1201 (2 << 4) /* 2 in C1 */ |
1202 (2 << 8) /* 2 in C2 */ |
1203 (2 << 12) /* 2 in C3 */ |
1204 (0 << 16) /* 0 in C4 */
1205 ;
1206#endif
1207 }
1208 else
1209 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1210
1211 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1212 * Safe to pass on to the guest.
1213 *
1214 * Intel: 0x800000005 reserved
1215 * 0x800000006 L2 cache information
1216 * AMD: 0x800000005 L1 cache information
1217 * 0x800000006 L2/L3 cache information
1218 * VIA: 0x800000005 TLB and L1 cache information
1219 * 0x800000006 L2 cache information
1220 */
1221
1222 /* Cpuid 0x800000007:
1223 * Intel: Reserved
1224 * AMD: EAX, EBX, ECX - reserved
1225 * EDX: Advanced Power Management Information
1226 * VIA: Reserved
1227 */
1228 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1229 {
1230 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1231
1232 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1233
1234 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1235 {
1236 /* Only expose the TSC invariant capability bit to the guest. */
1237 pCPUM->aGuestCpuIdExt[7].edx &= 0
1238 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1239 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1240 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1241 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1242 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1243 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1244 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1245 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1246#if 0
1247 /*
1248 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1249 * Linux kernels blindly assume that the AMD performance counters work
1250 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1251 * bit for them though.)
1252 */
1253 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1254#endif
1255 | 0;
1256 }
1257 else
1258 pCPUM->aGuestCpuIdExt[7].edx = 0;
1259 }
1260
1261 /* Cpuid 0x800000008:
1262 * Intel: EAX: Virtual/Physical address Size
1263 * EBX, ECX, EDX - reserved
1264 * AMD: EBX, EDX - reserved
1265 * EAX: Virtual/Physical/Guest address Size
1266 * ECX: Number of cores + APICIdCoreIdSize
1267 * VIA: EAX: Virtual/Physical address Size
1268 * EBX, ECX, EDX - reserved
1269 */
1270 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1271 {
1272 /* Only expose the virtual and physical address sizes to the guest. */
1273 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1274 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1275 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1276 * NC (0-7) Number of cores; 0 equals 1 core */
1277 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1278#ifdef VBOX_WITH_MULTI_CORE
1279 if ( pVM->cCpus > 1
1280 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1281 {
1282 /* Legacy method to determine the number of cores. */
1283 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1284 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1285 }
1286#endif
1287 }
1288
1289 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1290 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1291 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1292 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1293 */
1294 bool fNt4LeafLimit;
1295 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1296 if (fNt4LeafLimit)
1297 pCPUM->aGuestCpuIdStd[0].eax = 3; /** @todo r=bird: shouldn't we check if pCPUM->aGuestCpuIdStd[0].eax > 3 before setting it 3 here? */
1298
1299 /*
1300 * Limit it the number of entries and fill the remaining with the defaults.
1301 *
1302 * The limits are masking off stuff about power saving and similar, this
1303 * is perhaps a bit crudely done as there is probably some relatively harmless
1304 * info too in these leaves (like words about having a constant TSC).
1305 */
1306 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1307 pCPUM->aGuestCpuIdStd[0].eax = 5;
1308 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1309 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1310
1311 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1312 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1313 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1314 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1315 : 0;
1316 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1317 i++)
1318 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1319
1320 /*
1321 * Centaur stuff (VIA).
1322 *
1323 * The important part here (we think) is to make sure the 0xc0000000
1324 * function returns 0xc0000001. As for the features, we don't currently
1325 * let on about any of those... 0xc0000002 seems to be some
1326 * temperature/hz/++ stuff, include it as well (static).
1327 */
1328 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1329 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1330 {
1331 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1332 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1333 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1334 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1335 i++)
1336 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1337 }
1338 else
1339 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1340 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1341
1342 /*
1343 * Hypervisor identification.
1344 *
1345 * We only return minimal information, primarily ensuring that the
1346 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1347 * Currently we do not support any hypervisor-specific interface.
1348 */
1349 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1350 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1351 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1352 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1353 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1354 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1355
1356 /*
1357 * Load CPUID overrides from configuration.
1358 * Note: Kind of redundant now, but allows unchanged overrides
1359 */
1360 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1361 * Overrides the CPUID leaf values. */
1362 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1363 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1364 AssertRCReturn(rc, rc);
1365 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1366 AssertRCReturn(rc, rc);
1367 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1368 AssertRCReturn(rc, rc);
1369
1370 /*
1371 * Check if PAE was explicitely enabled by the user.
1372 */
1373 bool fEnable;
1374 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1375 if (fEnable)
1376 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1377
1378 /*
1379 * We don't normally enable NX for raw-mode, so give the user a chance to
1380 * force it on.
1381 */
1382 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1383 if (fEnable)
1384 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1385
1386 /*
1387 * We don't enable the Hypervisor Present bit by default, but it may
1388 * be needed by some guests.
1389 */
1390 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1391 if (fEnable)
1392 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1393
1394#undef PORTABLE_DISABLE_FEATURE_BIT
1395#undef PORTABLE_CLEAR_BITS_WHEN
1396
1397 return VINF_SUCCESS;
1398}
1399
1400
1401/**
1402 * Applies relocations to data and code managed by this
1403 * component. This function will be called at init and
1404 * whenever the VMM need to relocate it self inside the GC.
1405 *
1406 * The CPUM will update the addresses used by the switcher.
1407 *
1408 * @param pVM The VM.
1409 */
1410VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1411{
1412 LogFlow(("CPUMR3Relocate\n"));
1413
1414 /* Recheck the guest DRx values in raw-mode. */
1415 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1416 CPUMRecalcHyperDRx(&pVM->aCpus[iCpu], UINT8_MAX, false);
1417}
1418
1419
1420/**
1421 * Apply late CPUM property changes based on the fHWVirtEx setting
1422 *
1423 * @param pVM Pointer to the VM.
1424 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1425 */
1426VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1427{
1428 /*
1429 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1430 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1431 * of processors from (cpuid(4).eax >> 26) + 1.
1432 *
1433 * Note: this code is obsolete, but let's keep it here for reference.
1434 * Purpose is valid when we artificially cap the max std id to less than 4.
1435 */
1436 if (!fHWVirtExEnabled)
1437 {
1438 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1439 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1440 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1441 }
1442}
1443
1444/**
1445 * Terminates the CPUM.
1446 *
1447 * Termination means cleaning up and freeing all resources,
1448 * the VM it self is at this point powered off or suspended.
1449 *
1450 * @returns VBox status code.
1451 * @param pVM Pointer to the VM.
1452 */
1453VMMR3DECL(int) CPUMR3Term(PVM pVM)
1454{
1455#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1456 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1457 {
1458 PVMCPU pVCpu = &pVM->aCpus[i];
1459 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1460
1461 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1462 pVCpu->cpum.s.uMagic = 0;
1463 pCtx->dr[5] = 0;
1464 }
1465#else
1466 NOREF(pVM);
1467#endif
1468 return VINF_SUCCESS;
1469}
1470
1471
1472/**
1473 * Resets a virtual CPU.
1474 *
1475 * Used by CPUMR3Reset and CPU hot plugging.
1476 *
1477 * @param pVCpu Pointer to the VMCPU.
1478 */
1479VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1480{
1481 /** @todo anything different for VCPU > 0? */
1482 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1483
1484 /*
1485 * Initialize everything to ZERO first.
1486 */
1487 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1488 memset(pCtx, 0, sizeof(*pCtx));
1489 pVCpu->cpum.s.fUseFlags = fUseFlags;
1490
1491 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1492 pCtx->eip = 0x0000fff0;
1493 pCtx->edx = 0x00000600; /* P6 processor */
1494 pCtx->eflags.Bits.u1Reserved0 = 1;
1495
1496 pCtx->cs.Sel = 0xf000;
1497 pCtx->cs.ValidSel = 0xf000;
1498 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1499 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1500 pCtx->cs.u32Limit = 0x0000ffff;
1501 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1502 pCtx->cs.Attr.n.u1Present = 1;
1503 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1504
1505 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1506 pCtx->ds.u32Limit = 0x0000ffff;
1507 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1508 pCtx->ds.Attr.n.u1Present = 1;
1509 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1510
1511 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1512 pCtx->es.u32Limit = 0x0000ffff;
1513 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1514 pCtx->es.Attr.n.u1Present = 1;
1515 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1516
1517 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1518 pCtx->fs.u32Limit = 0x0000ffff;
1519 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1520 pCtx->fs.Attr.n.u1Present = 1;
1521 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1522
1523 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1524 pCtx->gs.u32Limit = 0x0000ffff;
1525 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1526 pCtx->gs.Attr.n.u1Present = 1;
1527 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1528
1529 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1530 pCtx->ss.u32Limit = 0x0000ffff;
1531 pCtx->ss.Attr.n.u1Present = 1;
1532 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1533 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1534
1535 pCtx->idtr.cbIdt = 0xffff;
1536 pCtx->gdtr.cbGdt = 0xffff;
1537
1538 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1539 pCtx->ldtr.u32Limit = 0xffff;
1540 pCtx->ldtr.Attr.n.u1Present = 1;
1541 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1542
1543 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1544 pCtx->tr.u32Limit = 0xffff;
1545 pCtx->tr.Attr.n.u1Present = 1;
1546 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1547
1548 pCtx->dr[6] = X86_DR6_INIT_VAL;
1549 pCtx->dr[7] = X86_DR7_INIT_VAL;
1550
1551 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1552 pCtx->fpu.FCW = 0x37f;
1553
1554 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1555 IA-32 Processor States Following Power-up, Reset, or INIT */
1556 pCtx->fpu.MXCSR = 0x1F80;
1557 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1558 supports all bits, since a zero value here should be read as 0xffbf. */
1559
1560 /* Init PAT MSR */
1561 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1562
1563 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1564 * The Intel docs don't mention it. */
1565 Assert(!pCtx->msrEFER);
1566
1567 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1568 * called from each EMT while we're getting called by CPUMR3Reset()
1569 * iteratively on the same thread. Fix later. */
1570#if 0
1571 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1572 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1573#endif
1574
1575
1576 /* C-state control. Guesses. */
1577 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1578
1579
1580 /*
1581 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1582 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1583 */
1584 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1585}
1586
1587
1588/**
1589 * Resets the CPU.
1590 *
1591 * @returns VINF_SUCCESS.
1592 * @param pVM Pointer to the VM.
1593 */
1594VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1595{
1596 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1597 {
1598 CPUMR3ResetCpu(&pVM->aCpus[i]);
1599
1600#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1601 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1602
1603 /* Magic marker for searching in crash dumps. */
1604 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1605 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1606 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1607#endif
1608 }
1609}
1610
1611
1612/**
1613 * Called both in pass 0 and the final pass.
1614 *
1615 * @param pVM Pointer to the VM.
1616 * @param pSSM The saved state handle.
1617 */
1618static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1619{
1620 /*
1621 * Save all the CPU ID leaves here so we can check them for compatibility
1622 * upon loading.
1623 */
1624 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1625 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1626
1627 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1628 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1629
1630 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1631 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1632
1633 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1634
1635 /*
1636 * Save a good portion of the raw CPU IDs as well as they may come in
1637 * handy when validating features for raw mode.
1638 */
1639 CPUMCPUID aRawStd[16];
1640 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1641 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1642 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1643 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1644
1645 CPUMCPUID aRawExt[32];
1646 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1647 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1648 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1649 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1650}
1651
1652
1653/**
1654 * Loads the CPU ID leaves saved by pass 0.
1655 *
1656 * @returns VBox status code.
1657 * @param pVM Pointer to the VM.
1658 * @param pSSM The saved state handle.
1659 * @param uVersion The format version.
1660 */
1661static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1662{
1663 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1664
1665 /*
1666 * Define a bunch of macros for simplifying the code.
1667 */
1668 /* Generic expression + failure message. */
1669#define CPUID_CHECK_RET(expr, fmt) \
1670 do { \
1671 if (!(expr)) \
1672 { \
1673 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1674 if (fStrictCpuIdChecks) \
1675 { \
1676 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1677 RTStrFree(pszMsg); \
1678 return rcCpuid; \
1679 } \
1680 LogRel(("CPUM: %s\n", pszMsg)); \
1681 RTStrFree(pszMsg); \
1682 } \
1683 } while (0)
1684#define CPUID_CHECK_WRN(expr, fmt) \
1685 do { \
1686 if (!(expr)) \
1687 LogRel(fmt); \
1688 } while (0)
1689
1690 /* For comparing two values and bitch if they differs. */
1691#define CPUID_CHECK2_RET(what, host, saved) \
1692 do { \
1693 if ((host) != (saved)) \
1694 { \
1695 if (fStrictCpuIdChecks) \
1696 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1697 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1698 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1699 } \
1700 } while (0)
1701#define CPUID_CHECK2_WRN(what, host, saved) \
1702 do { \
1703 if ((host) != (saved)) \
1704 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1705 } while (0)
1706
1707 /* For checking raw cpu features (raw mode). */
1708#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1709 do { \
1710 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1711 { \
1712 if (fStrictCpuIdChecks) \
1713 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1714 N_(#bit " mismatch: host=%d saved=%d"), \
1715 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1716 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1717 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1718 } \
1719 } while (0)
1720#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1721 do { \
1722 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1723 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1724 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1725 } while (0)
1726#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1727
1728 /* For checking guest features. */
1729#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1730 do { \
1731 if ( (aGuestCpuId##set [1].reg & bit) \
1732 && !(aHostRaw##set [1].reg & bit) \
1733 && !(aHostOverride##set [1].reg & bit) \
1734 && !(aGuestOverride##set [1].reg & bit) \
1735 ) \
1736 { \
1737 if (fStrictCpuIdChecks) \
1738 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1739 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1740 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1741 } \
1742 } while (0)
1743#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1744 do { \
1745 if ( (aGuestCpuId##set [1].reg & bit) \
1746 && !(aHostRaw##set [1].reg & bit) \
1747 && !(aHostOverride##set [1].reg & bit) \
1748 && !(aGuestOverride##set [1].reg & bit) \
1749 ) \
1750 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1751 } while (0)
1752#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1753 do { \
1754 if ( (aGuestCpuId##set [1].reg & bit) \
1755 && !(aHostRaw##set [1].reg & bit) \
1756 && !(aHostOverride##set [1].reg & bit) \
1757 && !(aGuestOverride##set [1].reg & bit) \
1758 ) \
1759 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1760 } while (0)
1761#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1762
1763 /* For checking guest features if AMD guest CPU. */
1764#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1765 do { \
1766 if ( (aGuestCpuId##set [1].reg & bit) \
1767 && fGuestAmd \
1768 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1769 && !(aHostOverride##set [1].reg & bit) \
1770 && !(aGuestOverride##set [1].reg & bit) \
1771 ) \
1772 { \
1773 if (fStrictCpuIdChecks) \
1774 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1775 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1776 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1777 } \
1778 } while (0)
1779#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1780 do { \
1781 if ( (aGuestCpuId##set [1].reg & bit) \
1782 && fGuestAmd \
1783 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1784 && !(aHostOverride##set [1].reg & bit) \
1785 && !(aGuestOverride##set [1].reg & bit) \
1786 ) \
1787 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1788 } while (0)
1789#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1790 do { \
1791 if ( (aGuestCpuId##set [1].reg & bit) \
1792 && fGuestAmd \
1793 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1794 && !(aHostOverride##set [1].reg & bit) \
1795 && !(aGuestOverride##set [1].reg & bit) \
1796 ) \
1797 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1798 } while (0)
1799#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1800
1801 /* For checking AMD features which have a corresponding bit in the standard
1802 range. (Intel defines very few bits in the extended feature sets.) */
1803#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1804 do { \
1805 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1806 && !(fHostAmd \
1807 ? aHostRawExt[1].reg & (ExtBit) \
1808 : aHostRawStd[1].reg & (StdBit)) \
1809 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1810 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1811 ) \
1812 { \
1813 if (fStrictCpuIdChecks) \
1814 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1815 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1816 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1817 } \
1818 } while (0)
1819#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1820 do { \
1821 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1822 && !(fHostAmd \
1823 ? aHostRawExt[1].reg & (ExtBit) \
1824 : aHostRawStd[1].reg & (StdBit)) \
1825 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1826 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1827 ) \
1828 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1829 } while (0)
1830#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1831 do { \
1832 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1833 && !(fHostAmd \
1834 ? aHostRawExt[1].reg & (ExtBit) \
1835 : aHostRawStd[1].reg & (StdBit)) \
1836 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1837 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1838 ) \
1839 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1840 } while (0)
1841#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1842
1843 /*
1844 * Load them into stack buffers first.
1845 */
1846 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1847 uint32_t cGuestCpuIdStd;
1848 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1849 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1850 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1851 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1852
1853 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1854 uint32_t cGuestCpuIdExt;
1855 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1856 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1857 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1858 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1859
1860 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1861 uint32_t cGuestCpuIdCentaur;
1862 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1863 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1864 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1865 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1866
1867 CPUMCPUID GuestCpuIdDef;
1868 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1869 AssertRCReturn(rc, rc);
1870
1871 CPUMCPUID aRawStd[16];
1872 uint32_t cRawStd;
1873 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1874 if (cRawStd > RT_ELEMENTS(aRawStd))
1875 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1876 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1877
1878 CPUMCPUID aRawExt[32];
1879 uint32_t cRawExt;
1880 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1881 if (cRawExt > RT_ELEMENTS(aRawExt))
1882 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1883 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1884 AssertRCReturn(rc, rc);
1885
1886 /*
1887 * Note that we support restoring less than the current amount of standard
1888 * leaves because we've been allowed more is newer version of VBox.
1889 *
1890 * So, pad new entries with the default.
1891 */
1892 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1893 aGuestCpuIdStd[i] = GuestCpuIdDef;
1894
1895 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1896 aGuestCpuIdExt[i] = GuestCpuIdDef;
1897
1898 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1899 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1900
1901 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1902 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1903
1904 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1905 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1906
1907 /*
1908 * Get the raw CPU IDs for the current host.
1909 */
1910 CPUMCPUID aHostRawStd[16];
1911 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1912 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1913
1914 CPUMCPUID aHostRawExt[32];
1915 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1916 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1917
1918 /*
1919 * Get the host and guest overrides so we don't reject the state because
1920 * some feature was enabled thru these interfaces.
1921 * Note! We currently only need the feature leaves, so skip rest.
1922 */
1923 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1924 CPUMCPUID aGuestOverrideStd[2];
1925 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1926 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1927
1928 CPUMCPUID aGuestOverrideExt[2];
1929 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1930 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1931
1932 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1933 CPUMCPUID aHostOverrideStd[2];
1934 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1935 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1936
1937 CPUMCPUID aHostOverrideExt[2];
1938 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1939 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1940
1941 /*
1942 * This can be skipped.
1943 */
1944 bool fStrictCpuIdChecks;
1945 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1946
1947
1948
1949 /*
1950 * For raw-mode we'll require that the CPUs are very similar since we don't
1951 * intercept CPUID instructions for user mode applications.
1952 */
1953 if (!HMIsEnabled(pVM))
1954 {
1955 /* CPUID(0) */
1956 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1957 && aHostRawStd[0].ecx == aRawStd[0].ecx
1958 && aHostRawStd[0].edx == aRawStd[0].edx,
1959 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1960 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1961 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1962 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1963 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
1964 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
1965
1966 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
1967
1968 /* CPUID(1).eax */
1969 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
1970 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
1971 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
1972
1973 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
1974 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
1975 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
1976
1977 /* CPUID(1).ecx */
1978 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
1979 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
1980 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
1981 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
1982 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
1983 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
1984 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
1985 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
1986 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
1987 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
1988 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
1989 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
1990 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
1991 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
1992 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
1993 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
1994 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
1995 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
1996 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
1997 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
1998 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
1999 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2000 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2001 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2002 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2003 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2004 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2005 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2006 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2007 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2008 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2009 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2010
2011 /* CPUID(1).edx */
2012 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2013 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2014 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2015 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2016 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2017 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2018 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2019 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2020 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2021 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2022 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2023 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2024 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2025 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2026 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2027 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2028 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2029 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2030 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2031 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2032 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2033 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2034 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2035 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2036 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2037 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2038 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2039 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2040 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2041 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2042 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2043 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2044
2045 /* CPUID(2) - config, mostly about caches. ignore. */
2046 /* CPUID(3) - processor serial number. ignore. */
2047 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2048 /* CPUID(5) - mwait/monitor config. ignore. */
2049 /* CPUID(6) - power management. ignore. */
2050 /* CPUID(7) - ???. ignore. */
2051 /* CPUID(8) - ???. ignore. */
2052 /* CPUID(9) - DCA. ignore for now. */
2053 /* CPUID(a) - PeMo info. ignore for now. */
2054 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2055
2056 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2057 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2058 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2059 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2060 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2061 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2062 {
2063 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2064 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2065 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2066 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2067 }
2068
2069 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2070 Note! Intel have/is marking many of the fields here as reserved. We
2071 will verify them as if it's an AMD CPU. */
2072 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2073 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2074 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2075 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2076 {
2077 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2078 && aHostRawExt[0].ecx == aRawExt[0].ecx
2079 && aHostRawExt[0].edx == aRawExt[0].edx,
2080 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2081 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2082 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2083 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2084
2085 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2086 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2087 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2088 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2089 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2090 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2091
2092 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2093 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2094 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2095 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2096
2097 /* CPUID(0x80000001).ecx */
2098 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2099 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2100 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2101 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2102 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2103 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2104 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2105 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2106 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2107 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2108 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2109 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2110 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2111 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2112 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2113 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2114 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2115 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2116 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2117 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2118 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2119 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2120 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2121 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2122 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2123 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2124 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2125 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2126 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2127 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2128 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2129 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2130
2131 /* CPUID(0x80000001).edx */
2132 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2133 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2134 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2135 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2136 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2137 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2138 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2139 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2140 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2141 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2142 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2143 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2144 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2145 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2146 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2147 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2148 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2149 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2150 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2151 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2152 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2153 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2154 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2155 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2156 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2157 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2158 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2159 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2160 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2161 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2162 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2163 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2164
2165 /** @todo verify the rest as well. */
2166 }
2167 }
2168
2169
2170
2171 /*
2172 * Verify that we can support the features already exposed to the guest on
2173 * this host.
2174 *
2175 * Most of the features we're emulating requires intercepting instruction
2176 * and doing it the slow way, so there is no need to warn when they aren't
2177 * present in the host CPU. Thus we use IGN instead of EMU on these.
2178 *
2179 * Trailing comments:
2180 * "EMU" - Possible to emulate, could be lots of work and very slow.
2181 * "EMU?" - Can this be emulated?
2182 */
2183 /* CPUID(1).ecx */
2184 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2185 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2186 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2187 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2188 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2189 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2190 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2191 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2192 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2193 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2194 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2195 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2196 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2197 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2198 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2199 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2200 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2201 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2202 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2203 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2204 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2205 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2206 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2207 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2208 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2209 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2210 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2211 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2212 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2213 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2214 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2215 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2216
2217 /* CPUID(1).edx */
2218 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2219 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2220 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2221 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2222 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2223 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2224 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2225 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2226 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2227 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2228 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2229 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2230 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2231 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2232 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2233 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2234 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2235 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2236 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2237 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2238 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2239 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2240 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2241 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2242 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2243 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2244 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2245 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2246 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2247 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2248 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2249 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2250
2251 /* CPUID(0x80000000). */
2252 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2253 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2254 {
2255 /** @todo deal with no 0x80000001 on the host. */
2256 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2257 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2258
2259 /* CPUID(0x80000001).ecx */
2260 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2261 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2262 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2263 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2264 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2265 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2266 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2267 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2268 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2269 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2270 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2271 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2272 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2273 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2274 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2275 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2276 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2277 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2278 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2279 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2280 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2281 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2282 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2283 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2284 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2285 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2286 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2287 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2288 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2289 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2290 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2291 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2292
2293 /* CPUID(0x80000001).edx */
2294 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2295 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2296 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2297 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2298 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2299 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2300 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2301 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2302 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2303 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2304 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2305 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2306 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2307 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2308 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2309 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2310 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2311 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2312 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2313 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2314 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2315 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2316 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2317 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2318 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2319 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2320 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2321 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2322 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2323 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2324 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2325 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2326 }
2327
2328 /*
2329 * We're good, commit the CPU ID leaves.
2330 */
2331 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2332 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2333 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2334 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2335
2336#undef CPUID_CHECK_RET
2337#undef CPUID_CHECK_WRN
2338#undef CPUID_CHECK2_RET
2339#undef CPUID_CHECK2_WRN
2340#undef CPUID_RAW_FEATURE_RET
2341#undef CPUID_RAW_FEATURE_WRN
2342#undef CPUID_RAW_FEATURE_IGN
2343#undef CPUID_GST_FEATURE_RET
2344#undef CPUID_GST_FEATURE_WRN
2345#undef CPUID_GST_FEATURE_EMU
2346#undef CPUID_GST_FEATURE_IGN
2347#undef CPUID_GST_FEATURE2_RET
2348#undef CPUID_GST_FEATURE2_WRN
2349#undef CPUID_GST_FEATURE2_EMU
2350#undef CPUID_GST_FEATURE2_IGN
2351#undef CPUID_GST_AMD_FEATURE_RET
2352#undef CPUID_GST_AMD_FEATURE_WRN
2353#undef CPUID_GST_AMD_FEATURE_EMU
2354#undef CPUID_GST_AMD_FEATURE_IGN
2355
2356 return VINF_SUCCESS;
2357}
2358
2359
2360/**
2361 * Pass 0 live exec callback.
2362 *
2363 * @returns VINF_SSM_DONT_CALL_AGAIN.
2364 * @param pVM Pointer to the VM.
2365 * @param pSSM The saved state handle.
2366 * @param uPass The pass (0).
2367 */
2368static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2369{
2370 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2371 cpumR3SaveCpuId(pVM, pSSM);
2372 return VINF_SSM_DONT_CALL_AGAIN;
2373}
2374
2375
2376/**
2377 * Execute state save operation.
2378 *
2379 * @returns VBox status code.
2380 * @param pVM Pointer to the VM.
2381 * @param pSSM SSM operation handle.
2382 */
2383static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2384{
2385 /*
2386 * Save.
2387 */
2388 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2389 {
2390 PVMCPU pVCpu = &pVM->aCpus[i];
2391 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2392 }
2393
2394 SSMR3PutU32(pSSM, pVM->cCpus);
2395 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2396 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2397 {
2398 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2399
2400 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2401 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2402 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2403 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2404 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2405 }
2406
2407 cpumR3SaveCpuId(pVM, pSSM);
2408 return VINF_SUCCESS;
2409}
2410
2411
2412/**
2413 * @copydoc FNSSMINTLOADPREP
2414 */
2415static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2416{
2417 NOREF(pSSM);
2418 pVM->cpum.s.fPendingRestore = true;
2419 return VINF_SUCCESS;
2420}
2421
2422
2423/**
2424 * @copydoc FNSSMINTLOADEXEC
2425 */
2426static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2427{
2428 /*
2429 * Validate version.
2430 */
2431 if ( uVersion != CPUM_SAVED_STATE_VERSION
2432 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2433 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2434 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2435 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2436 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2437 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2438 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2439 {
2440 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2441 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2442 }
2443
2444 if (uPass == SSM_PASS_FINAL)
2445 {
2446 /*
2447 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2448 * really old SSM file versions.)
2449 */
2450 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2451 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2452 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2453 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2454
2455 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2456 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2457 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2458 paCpumCtxFields = g_aCpumCtxFieldsV16;
2459 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2460 paCpumCtxFields = g_aCpumCtxFieldsMem;
2461
2462 /*
2463 * Restore.
2464 */
2465 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2466 {
2467 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2468 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2469 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2470 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2471 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2472 pVCpu->cpum.s.Hyper.rsp = uRSP;
2473 }
2474
2475 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2476 {
2477 uint32_t cCpus;
2478 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2479 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2480 VERR_SSM_UNEXPECTED_DATA);
2481 }
2482 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2483 || pVM->cCpus == 1,
2484 ("cCpus=%u\n", pVM->cCpus),
2485 VERR_SSM_UNEXPECTED_DATA);
2486
2487 uint32_t cbMsrs = 0;
2488 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2489 {
2490 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2491 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2492 VERR_SSM_UNEXPECTED_DATA);
2493 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2494 VERR_SSM_UNEXPECTED_DATA);
2495 }
2496
2497 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2498 {
2499 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2500 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2501 paCpumCtxFields, NULL);
2502 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2503 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2504 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2505 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2506 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2507 {
2508 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2509 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2510 }
2511
2512 /* REM and other may have cleared must-be-one fields in DR6 and
2513 DR7, fix these. */
2514 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2515 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
2516 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2517 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
2518 }
2519
2520 /* Older states does not have the internal selector register flags
2521 and valid selector value. Supply those. */
2522 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2523 {
2524 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2525 {
2526 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2527 bool const fValid = HMIsEnabled(pVM)
2528 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2529 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2530 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2531 if (fValid)
2532 {
2533 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2534 {
2535 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2536 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2537 }
2538
2539 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2540 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2541 }
2542 else
2543 {
2544 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2545 {
2546 paSelReg[iSelReg].fFlags = 0;
2547 paSelReg[iSelReg].ValidSel = 0;
2548 }
2549
2550 /* This might not be 104% correct, but I think it's close
2551 enough for all practical purposes... (REM always loaded
2552 LDTR registers.) */
2553 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2554 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2555 }
2556 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2557 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2558 }
2559 }
2560
2561 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2562 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2563 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2564 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2565 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2566
2567 /*
2568 * A quick sanity check.
2569 */
2570 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2571 {
2572 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2573 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2574 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2575 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2576 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2577 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2578 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2579 }
2580 }
2581
2582 pVM->cpum.s.fPendingRestore = false;
2583
2584 /*
2585 * Guest CPUIDs.
2586 */
2587 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2588 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2589
2590 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2591 * actually required. */
2592
2593 /*
2594 * Restore the CPUID leaves.
2595 *
2596 * Note that we support restoring less than the current amount of standard
2597 * leaves because we've been allowed more is newer version of VBox.
2598 */
2599 uint32_t cElements;
2600 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2601 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2602 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2603 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2604
2605 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2606 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2607 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2608 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2609
2610 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2611 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2612 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2613 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2614
2615 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2616
2617 /*
2618 * Check that the basic cpuid id information is unchanged.
2619 */
2620 /** @todo we should check the 64 bits capabilities too! */
2621 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2622 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2623 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2624 uint32_t au32CpuIdSaved[8];
2625 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2626 if (RT_SUCCESS(rc))
2627 {
2628 /* Ignore CPU stepping. */
2629 au32CpuId[4] &= 0xfffffff0;
2630 au32CpuIdSaved[4] &= 0xfffffff0;
2631
2632 /* Ignore APIC ID (AMD specs). */
2633 au32CpuId[5] &= ~0xff000000;
2634 au32CpuIdSaved[5] &= ~0xff000000;
2635
2636 /* Ignore the number of Logical CPUs (AMD specs). */
2637 au32CpuId[5] &= ~0x00ff0000;
2638 au32CpuIdSaved[5] &= ~0x00ff0000;
2639
2640 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2641 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2642 | X86_CPUID_FEATURE_ECX_VMX
2643 | X86_CPUID_FEATURE_ECX_SMX
2644 | X86_CPUID_FEATURE_ECX_EST
2645 | X86_CPUID_FEATURE_ECX_TM2
2646 | X86_CPUID_FEATURE_ECX_CNTXID
2647 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2648 | X86_CPUID_FEATURE_ECX_PDCM
2649 | X86_CPUID_FEATURE_ECX_DCA
2650 | X86_CPUID_FEATURE_ECX_X2APIC
2651 );
2652 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2653 | X86_CPUID_FEATURE_ECX_VMX
2654 | X86_CPUID_FEATURE_ECX_SMX
2655 | X86_CPUID_FEATURE_ECX_EST
2656 | X86_CPUID_FEATURE_ECX_TM2
2657 | X86_CPUID_FEATURE_ECX_CNTXID
2658 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2659 | X86_CPUID_FEATURE_ECX_PDCM
2660 | X86_CPUID_FEATURE_ECX_DCA
2661 | X86_CPUID_FEATURE_ECX_X2APIC
2662 );
2663
2664 /* Make sure we don't forget to update the masks when enabling
2665 * features in the future.
2666 */
2667 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2668 ( X86_CPUID_FEATURE_ECX_DTES64
2669 | X86_CPUID_FEATURE_ECX_VMX
2670 | X86_CPUID_FEATURE_ECX_SMX
2671 | X86_CPUID_FEATURE_ECX_EST
2672 | X86_CPUID_FEATURE_ECX_TM2
2673 | X86_CPUID_FEATURE_ECX_CNTXID
2674 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2675 | X86_CPUID_FEATURE_ECX_PDCM
2676 | X86_CPUID_FEATURE_ECX_DCA
2677 | X86_CPUID_FEATURE_ECX_X2APIC
2678 )));
2679 /* do the compare */
2680 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2681 {
2682 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2683 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2684 "Saved=%.*Rhxs\n"
2685 "Real =%.*Rhxs\n",
2686 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2687 sizeof(au32CpuId), au32CpuId));
2688 else
2689 {
2690 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2691 "Saved=%.*Rhxs\n"
2692 "Real =%.*Rhxs\n",
2693 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2694 sizeof(au32CpuId), au32CpuId));
2695 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2696 }
2697 }
2698 }
2699
2700 return rc;
2701}
2702
2703
2704/**
2705 * @copydoc FNSSMINTLOADPREP
2706 */
2707static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2708{
2709 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2710 return VINF_SUCCESS;
2711
2712 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2713 if (pVM->cpum.s.fPendingRestore)
2714 {
2715 LogRel(("CPUM: Missing state!\n"));
2716 return VERR_INTERNAL_ERROR_2;
2717 }
2718
2719 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2720 {
2721 /* Notify PGM of the NXE states in case they've changed. */
2722 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2723
2724 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
2725 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
2726 }
2727 return VINF_SUCCESS;
2728}
2729
2730
2731/**
2732 * Checks if the CPUM state restore is still pending.
2733 *
2734 * @returns true / false.
2735 * @param pVM Pointer to the VM.
2736 */
2737VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2738{
2739 return pVM->cpum.s.fPendingRestore;
2740}
2741
2742
2743/**
2744 * Formats the EFLAGS value into mnemonics.
2745 *
2746 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2747 * @param efl The EFLAGS value.
2748 */
2749static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2750{
2751 /*
2752 * Format the flags.
2753 */
2754 static const struct
2755 {
2756 const char *pszSet; const char *pszClear; uint32_t fFlag;
2757 } s_aFlags[] =
2758 {
2759 { "vip",NULL, X86_EFL_VIP },
2760 { "vif",NULL, X86_EFL_VIF },
2761 { "ac", NULL, X86_EFL_AC },
2762 { "vm", NULL, X86_EFL_VM },
2763 { "rf", NULL, X86_EFL_RF },
2764 { "nt", NULL, X86_EFL_NT },
2765 { "ov", "nv", X86_EFL_OF },
2766 { "dn", "up", X86_EFL_DF },
2767 { "ei", "di", X86_EFL_IF },
2768 { "tf", NULL, X86_EFL_TF },
2769 { "nt", "pl", X86_EFL_SF },
2770 { "nz", "zr", X86_EFL_ZF },
2771 { "ac", "na", X86_EFL_AF },
2772 { "po", "pe", X86_EFL_PF },
2773 { "cy", "nc", X86_EFL_CF },
2774 };
2775 char *psz = pszEFlags;
2776 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2777 {
2778 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2779 if (pszAdd)
2780 {
2781 strcpy(psz, pszAdd);
2782 psz += strlen(pszAdd);
2783 *psz++ = ' ';
2784 }
2785 }
2786 psz[-1] = '\0';
2787}
2788
2789
2790/**
2791 * Formats a full register dump.
2792 *
2793 * @param pVM Pointer to the VM.
2794 * @param pCtx The context to format.
2795 * @param pCtxCore The context core to format.
2796 * @param pHlp Output functions.
2797 * @param enmType The dump type.
2798 * @param pszPrefix Register name prefix.
2799 */
2800static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2801 const char *pszPrefix)
2802{
2803 NOREF(pVM);
2804
2805 /*
2806 * Format the EFLAGS.
2807 */
2808 uint32_t efl = pCtxCore->eflags.u32;
2809 char szEFlags[80];
2810 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2811
2812 /*
2813 * Format the registers.
2814 */
2815 switch (enmType)
2816 {
2817 case CPUMDUMPTYPE_TERSE:
2818 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2819 pHlp->pfnPrintf(pHlp,
2820 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2821 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2822 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2823 "%sr14=%016RX64 %sr15=%016RX64\n"
2824 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2825 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2826 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2827 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2828 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2829 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2830 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2831 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2832 else
2833 pHlp->pfnPrintf(pHlp,
2834 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2835 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2836 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2837 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2838 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2839 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2840 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2841 break;
2842
2843 case CPUMDUMPTYPE_DEFAULT:
2844 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2845 pHlp->pfnPrintf(pHlp,
2846 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2847 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2848 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2849 "%sr14=%016RX64 %sr15=%016RX64\n"
2850 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2851 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2852 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2853 ,
2854 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2855 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2856 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2857 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2858 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2859 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2860 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2861 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2862 else
2863 pHlp->pfnPrintf(pHlp,
2864 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2865 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2866 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2867 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2868 ,
2869 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2870 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2871 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2872 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2873 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2874 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2875 break;
2876
2877 case CPUMDUMPTYPE_VERBOSE:
2878 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2879 pHlp->pfnPrintf(pHlp,
2880 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2881 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2882 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2883 "%sr14=%016RX64 %sr15=%016RX64\n"
2884 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2885 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2886 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2887 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2888 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2889 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2890 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2891 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2892 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2893 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2894 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2895 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2896 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2897 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2898 ,
2899 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2900 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2901 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2902 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2903 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2904 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2905 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2906 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2907 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2908 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2909 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2910 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2911 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2912 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2913 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2914 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2915 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2916 else
2917 pHlp->pfnPrintf(pHlp,
2918 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2919 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2920 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2921 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2922 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2923 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2924 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2925 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2926 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2927 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2928 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2929 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2930 ,
2931 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2932 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2933 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2934 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2935 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2936 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2937 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2938 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2939 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2940 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2941 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2942 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2943
2944 pHlp->pfnPrintf(pHlp,
2945 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2946 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2947 ,
2948 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2949 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2950 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2951 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2952 );
2953 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2954 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2955 {
2956 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2957 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2958 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2959 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2960 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2961 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2962 /** @todo This isn't entirenly correct and needs more work! */
2963 pHlp->pfnPrintf(pHlp,
2964 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
2965 pszPrefix, iST, pszPrefix, iFPR,
2966 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
2967 uTag, chSign, iInteger, u64Fraction, uExponent);
2968 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
2969 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2970 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
2971 else
2972 pHlp->pfnPrintf(pHlp, "\n");
2973 }
2974 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
2975 pHlp->pfnPrintf(pHlp,
2976 iXMM & 1
2977 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2978 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2979 pszPrefix, iXMM, iXMM < 10 ? " " : "",
2980 pCtx->fpu.aXMM[iXMM].au32[3],
2981 pCtx->fpu.aXMM[iXMM].au32[2],
2982 pCtx->fpu.aXMM[iXMM].au32[1],
2983 pCtx->fpu.aXMM[iXMM].au32[0]);
2984 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
2985 if (pCtx->fpu.au32RsrvdRest[i])
2986 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
2987 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2988
2989 pHlp->pfnPrintf(pHlp,
2990 "%sEFER =%016RX64\n"
2991 "%sPAT =%016RX64\n"
2992 "%sSTAR =%016RX64\n"
2993 "%sCSTAR =%016RX64\n"
2994 "%sLSTAR =%016RX64\n"
2995 "%sSFMASK =%016RX64\n"
2996 "%sKERNELGSBASE =%016RX64\n",
2997 pszPrefix, pCtx->msrEFER,
2998 pszPrefix, pCtx->msrPAT,
2999 pszPrefix, pCtx->msrSTAR,
3000 pszPrefix, pCtx->msrCSTAR,
3001 pszPrefix, pCtx->msrLSTAR,
3002 pszPrefix, pCtx->msrSFMASK,
3003 pszPrefix, pCtx->msrKERNELGSBASE);
3004 break;
3005 }
3006}
3007
3008
3009/**
3010 * Display all cpu states and any other cpum info.
3011 *
3012 * @param pVM Pointer to the VM.
3013 * @param pHlp The info helper functions.
3014 * @param pszArgs Arguments, ignored.
3015 */
3016static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3017{
3018 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3019 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3020 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3021 cpumR3InfoHost(pVM, pHlp, pszArgs);
3022}
3023
3024
3025/**
3026 * Parses the info argument.
3027 *
3028 * The argument starts with 'verbose', 'terse' or 'default' and then
3029 * continues with the comment string.
3030 *
3031 * @param pszArgs The pointer to the argument string.
3032 * @param penmType Where to store the dump type request.
3033 * @param ppszComment Where to store the pointer to the comment string.
3034 */
3035static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3036{
3037 if (!pszArgs)
3038 {
3039 *penmType = CPUMDUMPTYPE_DEFAULT;
3040 *ppszComment = "";
3041 }
3042 else
3043 {
3044 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3045 {
3046 pszArgs += 7;
3047 *penmType = CPUMDUMPTYPE_VERBOSE;
3048 }
3049 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3050 {
3051 pszArgs += 5;
3052 *penmType = CPUMDUMPTYPE_TERSE;
3053 }
3054 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3055 {
3056 pszArgs += 7;
3057 *penmType = CPUMDUMPTYPE_DEFAULT;
3058 }
3059 else
3060 *penmType = CPUMDUMPTYPE_DEFAULT;
3061 *ppszComment = RTStrStripL(pszArgs);
3062 }
3063}
3064
3065
3066/**
3067 * Display the guest cpu state.
3068 *
3069 * @param pVM Pointer to the VM.
3070 * @param pHlp The info helper functions.
3071 * @param pszArgs Arguments, ignored.
3072 */
3073static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3074{
3075 CPUMDUMPTYPE enmType;
3076 const char *pszComment;
3077 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3078
3079 /* @todo SMP support! */
3080 PVMCPU pVCpu = VMMGetCpu(pVM);
3081 if (!pVCpu)
3082 pVCpu = &pVM->aCpus[0];
3083
3084 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3085
3086 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3087 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3088}
3089
3090
3091/**
3092 * Display the current guest instruction
3093 *
3094 * @param pVM Pointer to the VM.
3095 * @param pHlp The info helper functions.
3096 * @param pszArgs Arguments, ignored.
3097 */
3098static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3099{
3100 NOREF(pszArgs);
3101
3102 /** @todo SMP support! */
3103 PVMCPU pVCpu = VMMGetCpu(pVM);
3104 if (!pVCpu)
3105 pVCpu = &pVM->aCpus[0];
3106
3107 char szInstruction[256];
3108 szInstruction[0] = '\0';
3109 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3110 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3111}
3112
3113
3114/**
3115 * Display the hypervisor cpu state.
3116 *
3117 * @param pVM Pointer to the VM.
3118 * @param pHlp The info helper functions.
3119 * @param pszArgs Arguments, ignored.
3120 */
3121static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3122{
3123 CPUMDUMPTYPE enmType;
3124 const char *pszComment;
3125 /* @todo SMP */
3126 PVMCPU pVCpu = &pVM->aCpus[0];
3127
3128 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3129 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3130 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3131 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3132}
3133
3134
3135/**
3136 * Display the host cpu state.
3137 *
3138 * @param pVM Pointer to the VM.
3139 * @param pHlp The info helper functions.
3140 * @param pszArgs Arguments, ignored.
3141 */
3142static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3143{
3144 CPUMDUMPTYPE enmType;
3145 const char *pszComment;
3146 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3147 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3148
3149 /*
3150 * Format the EFLAGS.
3151 */
3152 /* @todo SMP */
3153 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3154#if HC_ARCH_BITS == 32
3155 uint32_t efl = pCtx->eflags.u32;
3156#else
3157 uint64_t efl = pCtx->rflags;
3158#endif
3159 char szEFlags[80];
3160 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3161
3162 /*
3163 * Format the registers.
3164 */
3165#if HC_ARCH_BITS == 32
3166# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3167 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3168# endif
3169 {
3170 pHlp->pfnPrintf(pHlp,
3171 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3172 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3173 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3174 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3175 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3176 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3177 ,
3178 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3179 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3180 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3181 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3182 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3183 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3184 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3185 }
3186# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3187 else
3188# endif
3189#endif
3190#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3191 {
3192 pHlp->pfnPrintf(pHlp,
3193 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3194 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3195 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3196 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3197 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3198 "r14=%016RX64 r15=%016RX64\n"
3199 "iopl=%d %31s\n"
3200 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3201 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3202 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3203 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3204 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3205 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3206 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3207 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3208 ,
3209 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3210 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3211 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3212 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3213 pCtx->r11, pCtx->r12, pCtx->r13,
3214 pCtx->r14, pCtx->r15,
3215 X86_EFL_GET_IOPL(efl), szEFlags,
3216 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3217 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3218 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3219 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3220 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3221 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3222 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3223 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3224 }
3225#endif
3226}
3227
3228
3229/**
3230 * Get L1 cache / TLS associativity.
3231 */
3232static const char *getCacheAss(unsigned u, char *pszBuf)
3233{
3234 if (u == 0)
3235 return "res0 ";
3236 if (u == 1)
3237 return "direct";
3238 if (u == 255)
3239 return "fully";
3240 if (u >= 256)
3241 return "???";
3242
3243 RTStrPrintf(pszBuf, 16, "%d way", u);
3244 return pszBuf;
3245}
3246
3247
3248/**
3249 * Get L2 cache associativity.
3250 */
3251const char *getL2CacheAss(unsigned u)
3252{
3253 switch (u)
3254 {
3255 case 0: return "off ";
3256 case 1: return "direct";
3257 case 2: return "2 way ";
3258 case 3: return "res3 ";
3259 case 4: return "4 way ";
3260 case 5: return "res5 ";
3261 case 6: return "8 way ";
3262 case 7: return "res7 ";
3263 case 8: return "16 way";
3264 case 9: return "res9 ";
3265 case 10: return "res10 ";
3266 case 11: return "res11 ";
3267 case 12: return "res12 ";
3268 case 13: return "res13 ";
3269 case 14: return "res14 ";
3270 case 15: return "fully ";
3271 default: return "????";
3272 }
3273}
3274
3275
3276/**
3277 * Display the guest CpuId leaves.
3278 *
3279 * @param pVM Pointer to the VM.
3280 * @param pHlp The info helper functions.
3281 * @param pszArgs "terse", "default" or "verbose".
3282 */
3283static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3284{
3285 /*
3286 * Parse the argument.
3287 */
3288 unsigned iVerbosity = 1;
3289 if (pszArgs)
3290 {
3291 pszArgs = RTStrStripL(pszArgs);
3292 if (!strcmp(pszArgs, "terse"))
3293 iVerbosity--;
3294 else if (!strcmp(pszArgs, "verbose"))
3295 iVerbosity++;
3296 }
3297
3298 /*
3299 * Start cracking.
3300 */
3301 CPUMCPUID Host;
3302 CPUMCPUID Guest;
3303 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3304
3305 uint32_t cStdHstMax;
3306 uint32_t dummy;
3307 ASMCpuId_Idx_ECX(0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
3308
3309 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd), cStdHstMax);
3310
3311 pHlp->pfnPrintf(pHlp,
3312 " RAW Standard CPUIDs\n"
3313 " Function eax ebx ecx edx\n");
3314 for (unsigned i = 0; i <= cStdLstMax ; i++)
3315 {
3316 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3317 {
3318 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3319 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3320
3321 pHlp->pfnPrintf(pHlp,
3322 "Gst: %08x %08x %08x %08x %08x%s\n"
3323 "Hst: %08x %08x %08x %08x\n",
3324 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3325 i <= cStdMax ? "" : "*",
3326 Host.eax, Host.ebx, Host.ecx, Host.edx);
3327 }
3328 else
3329 {
3330 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3331
3332 pHlp->pfnPrintf(pHlp,
3333 "Hst: %08x %08x %08x %08x %08x\n",
3334 i, Host.eax, Host.ebx, Host.ecx, Host.edx);
3335 }
3336 }
3337
3338 /*
3339 * If verbose, decode it.
3340 */
3341 if (iVerbosity)
3342 {
3343 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3344 pHlp->pfnPrintf(pHlp,
3345 "Name: %.04s%.04s%.04s\n"
3346 "Supports: 0-%x\n",
3347 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3348 }
3349
3350 /*
3351 * Get Features.
3352 */
3353 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3354 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3355 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3356 if (cStdMax >= 1 && iVerbosity)
3357 {
3358 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3359
3360 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3361 uint32_t uEAX = Guest.eax;
3362
3363 pHlp->pfnPrintf(pHlp,
3364 "Family: %d \tExtended: %d \tEffective: %d\n"
3365 "Model: %d \tExtended: %d \tEffective: %d\n"
3366 "Stepping: %d\n"
3367 "Type: %d (%s)\n"
3368 "APIC ID: %#04x\n"
3369 "Logical CPUs: %d\n"
3370 "CLFLUSH Size: %d\n"
3371 "Brand ID: %#04x\n",
3372 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3373 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3374 ASMGetCpuStepping(uEAX),
3375 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3376 (Guest.ebx >> 24) & 0xff,
3377 (Guest.ebx >> 16) & 0xff,
3378 (Guest.ebx >> 8) & 0xff,
3379 (Guest.ebx >> 0) & 0xff);
3380 if (iVerbosity == 1)
3381 {
3382 uint32_t uEDX = Guest.edx;
3383 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3384 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3385 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3386 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3387 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3388 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3389 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3390 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3391 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3392 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3393 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3394 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3395 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3396 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3397 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3398 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3399 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3400 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3401 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3402 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3403 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3404 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3405 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3406 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3407 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3408 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3409 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3410 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3411 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3412 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3413 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3414 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3415 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3416 pHlp->pfnPrintf(pHlp, "\n");
3417
3418 uint32_t uECX = Guest.ecx;
3419 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3420 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3421 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3422 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3423 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3424 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3425 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3426 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3427 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3428 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3429 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3430 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3431 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3432 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3433 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3434 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3435 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3436 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3437 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3438 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3439 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3440 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3441 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3442 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3443 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3444 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3445 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3446 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3447 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3448 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3449 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3450 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3451 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3452 pHlp->pfnPrintf(pHlp, "\n");
3453 }
3454 else
3455 {
3456 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3457
3458 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3459 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3460 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3461 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3462
3463 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3464 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3465 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3466 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3467 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3468 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3469 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3470 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3471 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3472 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3473 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3474 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3475 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3476 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3477 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3478 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3479 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3480 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3481 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3482 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3483 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3484 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3485 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3486 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3487 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3488 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3489 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3490 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3491 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3492 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3493 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3494 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3495 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3496
3497 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3498 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3499 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3500 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3501 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3502 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3503 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3504 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3505 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3506 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3507 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3508 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3509 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3510 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3511 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3512 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3513 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3514 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3515 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3516 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3517 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3518 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3519 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3520 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3521 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3522 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3523 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3524 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3525 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3526 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3527 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3528 }
3529 }
3530 if (cStdMax >= 2 && iVerbosity)
3531 {
3532 /** @todo */
3533 }
3534
3535 /*
3536 * Extended.
3537 * Implemented after AMD specs.
3538 */
3539 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3540
3541 pHlp->pfnPrintf(pHlp,
3542 "\n"
3543 " RAW Extended CPUIDs\n"
3544 " Function eax ebx ecx edx\n");
3545 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3546 {
3547 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3548 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3549
3550 pHlp->pfnPrintf(pHlp,
3551 "Gst: %08x %08x %08x %08x %08x%s\n"
3552 "Hst: %08x %08x %08x %08x\n",
3553 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3554 i <= cExtMax ? "" : "*",
3555 Host.eax, Host.ebx, Host.ecx, Host.edx);
3556 }
3557
3558 /*
3559 * Understandable output
3560 */
3561 if (iVerbosity)
3562 {
3563 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3564 pHlp->pfnPrintf(pHlp,
3565 "Ext Name: %.4s%.4s%.4s\n"
3566 "Ext Supports: 0x80000000-%#010x\n",
3567 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3568 }
3569
3570 if (iVerbosity && cExtMax >= 1)
3571 {
3572 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3573 uint32_t uEAX = Guest.eax;
3574 pHlp->pfnPrintf(pHlp,
3575 "Family: %d \tExtended: %d \tEffective: %d\n"
3576 "Model: %d \tExtended: %d \tEffective: %d\n"
3577 "Stepping: %d\n"
3578 "Brand ID: %#05x\n",
3579 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3580 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3581 ASMGetCpuStepping(uEAX),
3582 Guest.ebx & 0xfff);
3583
3584 if (iVerbosity == 1)
3585 {
3586 uint32_t uEDX = Guest.edx;
3587 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3588 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3589 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3590 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3591 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3592 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3593 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3594 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3595 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3596 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3597 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3598 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3599 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3600 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3601 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3602 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3603 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3604 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3605 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3606 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3607 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3608 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3609 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3610 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3611 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3612 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3613 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3614 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3615 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3616 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3617 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3618 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3619 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3620 pHlp->pfnPrintf(pHlp, "\n");
3621
3622 uint32_t uECX = Guest.ecx;
3623 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3624 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3625 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3626 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3627 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3628 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3629 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3630 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3631 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3632 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3633 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3634 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3635 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3636 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3637 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3638 for (unsigned iBit = 5; iBit < 32; iBit++)
3639 if (uECX & RT_BIT(iBit))
3640 pHlp->pfnPrintf(pHlp, " %d", iBit);
3641 pHlp->pfnPrintf(pHlp, "\n");
3642 }
3643 else
3644 {
3645 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3646
3647 uint32_t uEdxGst = Guest.edx;
3648 uint32_t uEdxHst = Host.edx;
3649 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3650 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3651 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3652 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3653 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3654 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3655 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3656 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3657 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3658 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3659 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3660 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3661 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3662 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3663 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3664 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3665 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3666 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3667 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3668 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3669 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3670 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3671 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3672 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3673 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3674 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3675 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3676 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3677 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3678 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3679 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3680 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3681 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3682
3683 uint32_t uEcxGst = Guest.ecx;
3684 uint32_t uEcxHst = Host.ecx;
3685 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3686 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3687 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3688 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3689 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3690 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3691 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3692 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3693 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3694 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3695 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3696 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3697 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3698 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3699 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3700 }
3701 }
3702
3703 if (iVerbosity && cExtMax >= 2)
3704 {
3705 char szString[4*4*3+1] = {0};
3706 uint32_t *pu32 = (uint32_t *)szString;
3707 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3708 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3709 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3710 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3711 if (cExtMax >= 3)
3712 {
3713 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3714 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3715 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3716 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3717 }
3718 if (cExtMax >= 4)
3719 {
3720 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3721 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3722 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3723 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3724 }
3725 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3726 }
3727
3728 if (iVerbosity && cExtMax >= 5)
3729 {
3730 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3731 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3732 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3733 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3734 char sz1[32];
3735 char sz2[32];
3736
3737 pHlp->pfnPrintf(pHlp,
3738 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3739 "TLB 2/4M Data: %s %3d entries\n",
3740 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3741 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3742 pHlp->pfnPrintf(pHlp,
3743 "TLB 4K Instr/Uni: %s %3d entries\n"
3744 "TLB 4K Data: %s %3d entries\n",
3745 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3746 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3747 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3748 "L1 Instr Cache Lines Per Tag: %d\n"
3749 "L1 Instr Cache Associativity: %s\n"
3750 "L1 Instr Cache Size: %d KB\n",
3751 (uEDX >> 0) & 0xff,
3752 (uEDX >> 8) & 0xff,
3753 getCacheAss((uEDX >> 16) & 0xff, sz1),
3754 (uEDX >> 24) & 0xff);
3755 pHlp->pfnPrintf(pHlp,
3756 "L1 Data Cache Line Size: %d bytes\n"
3757 "L1 Data Cache Lines Per Tag: %d\n"
3758 "L1 Data Cache Associativity: %s\n"
3759 "L1 Data Cache Size: %d KB\n",
3760 (uECX >> 0) & 0xff,
3761 (uECX >> 8) & 0xff,
3762 getCacheAss((uECX >> 16) & 0xff, sz1),
3763 (uECX >> 24) & 0xff);
3764 }
3765
3766 if (iVerbosity && cExtMax >= 6)
3767 {
3768 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3769 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3770 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3771
3772 pHlp->pfnPrintf(pHlp,
3773 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3774 "L2 TLB 2/4M Data: %s %4d entries\n",
3775 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3776 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3777 pHlp->pfnPrintf(pHlp,
3778 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3779 "L2 TLB 4K Data: %s %4d entries\n",
3780 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3781 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3782 pHlp->pfnPrintf(pHlp,
3783 "L2 Cache Line Size: %d bytes\n"
3784 "L2 Cache Lines Per Tag: %d\n"
3785 "L2 Cache Associativity: %s\n"
3786 "L2 Cache Size: %d KB\n",
3787 (uEDX >> 0) & 0xff,
3788 (uEDX >> 8) & 0xf,
3789 getL2CacheAss((uEDX >> 12) & 0xf),
3790 (uEDX >> 16) & 0xffff);
3791 }
3792
3793 if (iVerbosity && cExtMax >= 7)
3794 {
3795 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3796
3797 pHlp->pfnPrintf(pHlp, "APM Features: ");
3798 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3799 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3800 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3801 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3802 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3803 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3804 for (unsigned iBit = 6; iBit < 32; iBit++)
3805 if (uEDX & RT_BIT(iBit))
3806 pHlp->pfnPrintf(pHlp, " %d", iBit);
3807 pHlp->pfnPrintf(pHlp, "\n");
3808 }
3809
3810 if (iVerbosity && cExtMax >= 8)
3811 {
3812 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3813 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3814
3815 pHlp->pfnPrintf(pHlp,
3816 "Physical Address Width: %d bits\n"
3817 "Virtual Address Width: %d bits\n"
3818 "Guest Physical Address Width: %d bits\n",
3819 (uEAX >> 0) & 0xff,
3820 (uEAX >> 8) & 0xff,
3821 (uEAX >> 16) & 0xff);
3822 pHlp->pfnPrintf(pHlp,
3823 "Physical Core Count: %d\n",
3824 (uECX >> 0) & 0xff);
3825 }
3826
3827
3828 /*
3829 * Centaur.
3830 */
3831 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3832
3833 pHlp->pfnPrintf(pHlp,
3834 "\n"
3835 " RAW Centaur CPUIDs\n"
3836 " Function eax ebx ecx edx\n");
3837 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3838 {
3839 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3840 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3841
3842 pHlp->pfnPrintf(pHlp,
3843 "Gst: %08x %08x %08x %08x %08x%s\n"
3844 "Hst: %08x %08x %08x %08x\n",
3845 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3846 i <= cCentaurMax ? "" : "*",
3847 Host.eax, Host.ebx, Host.ecx, Host.edx);
3848 }
3849
3850 /*
3851 * Understandable output
3852 */
3853 if (iVerbosity)
3854 {
3855 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3856 pHlp->pfnPrintf(pHlp,
3857 "Centaur Supports: 0xc0000000-%#010x\n",
3858 Guest.eax);
3859 }
3860
3861 if (iVerbosity && cCentaurMax >= 1)
3862 {
3863 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3864 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3865 uint32_t uEdxHst = Host.edx;
3866
3867 if (iVerbosity == 1)
3868 {
3869 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3870 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3871 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3872 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3873 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3874 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3875 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3876 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3877 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3878 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3879 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3880 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3881 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3882 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3883 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3884 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3885 for (unsigned iBit = 14; iBit < 32; iBit++)
3886 if (uEdxGst & RT_BIT(iBit))
3887 pHlp->pfnPrintf(pHlp, " %d", iBit);
3888 pHlp->pfnPrintf(pHlp, "\n");
3889 }
3890 else
3891 {
3892 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3893 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3894 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3895 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3896 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3897 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3898 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3899 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3900 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3901 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3902 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3903 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3904 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3905 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3906 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3907 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3908 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3909 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3910 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3911 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3912 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3913 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3914 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3915 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3916 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3917 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3918 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3919 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3920 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3921 for (unsigned iBit = 27; iBit < 32; iBit++)
3922 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3923 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3924 pHlp->pfnPrintf(pHlp, "\n");
3925 }
3926 }
3927}
3928
3929
3930/**
3931 * Structure used when disassembling and instructions in DBGF.
3932 * This is used so the reader function can get the stuff it needs.
3933 */
3934typedef struct CPUMDISASSTATE
3935{
3936 /** Pointer to the CPU structure. */
3937 PDISCPUSTATE pCpu;
3938 /** Pointer to the VM. */
3939 PVM pVM;
3940 /** Pointer to the VMCPU. */
3941 PVMCPU pVCpu;
3942 /** Pointer to the first byte in the segment. */
3943 RTGCUINTPTR GCPtrSegBase;
3944 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3945 RTGCUINTPTR GCPtrSegEnd;
3946 /** The size of the segment minus 1. */
3947 RTGCUINTPTR cbSegLimit;
3948 /** Pointer to the current page - R3 Ptr. */
3949 void const *pvPageR3;
3950 /** Pointer to the current page - GC Ptr. */
3951 RTGCPTR pvPageGC;
3952 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3953 PGMPAGEMAPLOCK PageMapLock;
3954 /** Whether the PageMapLock is valid or not. */
3955 bool fLocked;
3956 /** 64 bits mode or not. */
3957 bool f64Bits;
3958} CPUMDISASSTATE, *PCPUMDISASSTATE;
3959
3960
3961/**
3962 * @callback_method_impl{FNDISREADBYTES}
3963 */
3964static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3965{
3966 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3967 for (;;)
3968 {
3969 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3970
3971 /*
3972 * Need to update the page translation?
3973 */
3974 if ( !pState->pvPageR3
3975 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3976 {
3977 int rc = VINF_SUCCESS;
3978
3979 /* translate the address */
3980 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3981 if ( !HMIsEnabled(pState->pVM)
3982 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
3983 {
3984 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3985 if (!pState->pvPageR3)
3986 rc = VERR_INVALID_POINTER;
3987 }
3988 else
3989 {
3990 /* Release mapping lock previously acquired. */
3991 if (pState->fLocked)
3992 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3993 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3994 pState->fLocked = RT_SUCCESS_NP(rc);
3995 }
3996 if (RT_FAILURE(rc))
3997 {
3998 pState->pvPageR3 = NULL;
3999 return rc;
4000 }
4001 }
4002
4003 /*
4004 * Check the segment limit.
4005 */
4006 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4007 return VERR_OUT_OF_SELECTOR_BOUNDS;
4008
4009 /*
4010 * Calc how much we can read.
4011 */
4012 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4013 if (!pState->f64Bits)
4014 {
4015 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4016 if (cb > cbSeg && cbSeg)
4017 cb = cbSeg;
4018 }
4019 if (cb > cbMaxRead)
4020 cb = cbMaxRead;
4021
4022 /*
4023 * Read and advance or exit.
4024 */
4025 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4026 offInstr += (uint8_t)cb;
4027 if (cb >= cbMinRead)
4028 {
4029 pDis->cbCachedInstr = offInstr;
4030 return VINF_SUCCESS;
4031 }
4032 cbMinRead -= (uint8_t)cb;
4033 cbMaxRead -= (uint8_t)cb;
4034 }
4035}
4036
4037
4038/**
4039 * Disassemble an instruction and return the information in the provided structure.
4040 *
4041 * @returns VBox status code.
4042 * @param pVM Pointer to the VM.
4043 * @param pVCpu Pointer to the VMCPU.
4044 * @param pCtx Pointer to the guest CPU context.
4045 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4046 * @param pCpu Disassembly state.
4047 * @param pszPrefix String prefix for logging (debug only).
4048 *
4049 */
4050VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4051{
4052 CPUMDISASSTATE State;
4053 int rc;
4054
4055 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4056 State.pCpu = pCpu;
4057 State.pvPageGC = 0;
4058 State.pvPageR3 = NULL;
4059 State.pVM = pVM;
4060 State.pVCpu = pVCpu;
4061 State.fLocked = false;
4062 State.f64Bits = false;
4063
4064 /*
4065 * Get selector information.
4066 */
4067 DISCPUMODE enmDisCpuMode;
4068 if ( (pCtx->cr0 & X86_CR0_PE)
4069 && pCtx->eflags.Bits.u1VM == 0)
4070 {
4071 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4072 {
4073# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4074 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4075# endif
4076 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4077 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4078 }
4079 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4080 State.GCPtrSegBase = pCtx->cs.u64Base;
4081 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4082 State.cbSegLimit = pCtx->cs.u32Limit;
4083 enmDisCpuMode = (State.f64Bits)
4084 ? DISCPUMODE_64BIT
4085 : pCtx->cs.Attr.n.u1DefBig
4086 ? DISCPUMODE_32BIT
4087 : DISCPUMODE_16BIT;
4088 }
4089 else
4090 {
4091 /* real or V86 mode */
4092 enmDisCpuMode = DISCPUMODE_16BIT;
4093 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4094 State.GCPtrSegEnd = 0xFFFFFFFF;
4095 State.cbSegLimit = 0xFFFFFFFF;
4096 }
4097
4098 /*
4099 * Disassemble the instruction.
4100 */
4101 uint32_t cbInstr;
4102#ifndef LOG_ENABLED
4103 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4104 if (RT_SUCCESS(rc))
4105 {
4106#else
4107 char szOutput[160];
4108 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4109 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4110 if (RT_SUCCESS(rc))
4111 {
4112 /* log it */
4113 if (pszPrefix)
4114 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4115 else
4116 Log(("%s", szOutput));
4117#endif
4118 rc = VINF_SUCCESS;
4119 }
4120 else
4121 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4122
4123 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4124 if (State.fLocked)
4125 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4126
4127 return rc;
4128}
4129
4130
4131
4132/**
4133 * API for controlling a few of the CPU features found in CR4.
4134 *
4135 * Currently only X86_CR4_TSD is accepted as input.
4136 *
4137 * @returns VBox status code.
4138 *
4139 * @param pVM Pointer to the VM.
4140 * @param fOr The CR4 OR mask.
4141 * @param fAnd The CR4 AND mask.
4142 */
4143VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4144{
4145 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4146 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4147
4148 pVM->cpum.s.CR4.OrMask &= fAnd;
4149 pVM->cpum.s.CR4.OrMask |= fOr;
4150
4151 return VINF_SUCCESS;
4152}
4153
4154
4155/**
4156 * Gets a pointer to the array of standard CPUID leaves.
4157 *
4158 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4159 *
4160 * @returns Pointer to the standard CPUID leaves (read-only).
4161 * @param pVM Pointer to the VM.
4162 * @remark Intended for PATM.
4163 */
4164VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4165{
4166 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4167}
4168
4169
4170/**
4171 * Gets a pointer to the array of extended CPUID leaves.
4172 *
4173 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4174 *
4175 * @returns Pointer to the extended CPUID leaves (read-only).
4176 * @param pVM Pointer to the VM.
4177 * @remark Intended for PATM.
4178 */
4179VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4180{
4181 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4182}
4183
4184
4185/**
4186 * Gets a pointer to the array of centaur CPUID leaves.
4187 *
4188 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4189 *
4190 * @returns Pointer to the centaur CPUID leaves (read-only).
4191 * @param pVM Pointer to the VM.
4192 * @remark Intended for PATM.
4193 */
4194VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4195{
4196 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4197}
4198
4199
4200/**
4201 * Gets a pointer to the default CPUID leaf.
4202 *
4203 * @returns Pointer to the default CPUID leaf (read-only).
4204 * @param pVM Pointer to the VM.
4205 * @remark Intended for PATM.
4206 */
4207VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4208{
4209 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4210}
4211
4212
4213/**
4214 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4215 *
4216 * Only REM should ever call this function!
4217 *
4218 * @returns The changed flags.
4219 * @param pVCpu Pointer to the VMCPU.
4220 * @param puCpl Where to return the current privilege level (CPL).
4221 */
4222VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4223{
4224 Assert(!pVCpu->cpum.s.fRawEntered);
4225 Assert(!pVCpu->cpum.s.fRemEntered);
4226
4227 /*
4228 * Get the CPL first.
4229 */
4230 *puCpl = CPUMGetGuestCPL(pVCpu);
4231
4232 /*
4233 * Get and reset the flags.
4234 */
4235 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4236 pVCpu->cpum.s.fChanged = 0;
4237
4238 /** @todo change the switcher to use the fChanged flags. */
4239 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4240 {
4241 fFlags |= CPUM_CHANGED_FPU_REM;
4242 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4243 }
4244
4245 pVCpu->cpum.s.fRemEntered = true;
4246 return fFlags;
4247}
4248
4249
4250/**
4251 * Leaves REM.
4252 *
4253 * @param pVCpu Pointer to the VMCPU.
4254 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4255 * registers.
4256 */
4257VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4258{
4259 Assert(!pVCpu->cpum.s.fRawEntered);
4260 Assert(pVCpu->cpum.s.fRemEntered);
4261
4262 pVCpu->cpum.s.fRemEntered = false;
4263}
4264
4265
4266/**
4267 * Called when the ring-3 init phase completes.
4268 *
4269 * @returns VBox status code.
4270 * @param pVM Pointer to the VM.
4271 */
4272VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4273{
4274 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4275 {
4276 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4277 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4278 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4279 }
4280 return VINF_SUCCESS;
4281}
4282
4283/**
4284 * Called when the ring-0 init phases comleted.
4285 *
4286 * @param pVM Pointer to the VM.
4287 */
4288VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4289{
4290 /*
4291 * Log the cpuid.
4292 */
4293 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4294 RTCPUSET OnlineSet;
4295 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4296 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4297 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4298 RTCPUID cCores = RTMpGetCoreCount();
4299 if (cCores)
4300 LogRel(("Physical cores: %u\n", (unsigned)cCores));
4301 LogRel(("************************* CPUID dump ************************\n"));
4302 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4303 LogRel(("\n"));
4304 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4305 RTLogRelSetBuffering(fOldBuffered);
4306 LogRel(("******************** End of CPUID dump **********************\n"));
4307}
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