VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 48936

Last change on this file since 48936 was 48814, checked in by vboxsync, 12 years ago

Nit.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 211.7 KB
Line 
1/* $Id: CPUM.cpp 48814 2013-10-02 09:42:43Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/assert.h>
58#include <iprt/asm-amd64-x86.h>
59#include <iprt/string.h>
60#include <iprt/mp.h>
61#include <iprt/cpuset.h>
62#include "internal/pgm.h"
63
64
65/*******************************************************************************
66* Defined Constants And Macros *
67*******************************************************************************/
68/** The current saved state version. */
69#define CPUM_SAVED_STATE_VERSION 14
70/** The current saved state version before using SSMR3PutStruct. */
71#define CPUM_SAVED_STATE_VERSION_MEM 13
72/** The saved state version before introducing the MSR size field. */
73#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
74/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
75 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
76#define CPUM_SAVED_STATE_VERSION_VER3_2 11
77/** The saved state version of 3.0 and 3.1 trunk before the teleportation
78 * changes. */
79#define CPUM_SAVED_STATE_VERSION_VER3_0 10
80/** The saved state version for the 2.1 trunk before the MSR changes. */
81#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
82/** The saved state version of 2.0, used for backwards compatibility. */
83#define CPUM_SAVED_STATE_VERSION_VER2_0 8
84/** The saved state version of 1.6, used for backwards compatibility. */
85#define CPUM_SAVED_STATE_VERSION_VER1_6 6
86
87
88/**
89 * This was used in the saved state up to the early life of version 14.
90 *
91 * It indicates that we may have some out-of-sync hidden segement registers.
92 * It is only relevant for raw-mode.
93 */
94#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
95
96
97/*******************************************************************************
98* Structures and Typedefs *
99*******************************************************************************/
100
101/**
102 * What kind of cpu info dump to perform.
103 */
104typedef enum CPUMDUMPTYPE
105{
106 CPUMDUMPTYPE_TERSE,
107 CPUMDUMPTYPE_DEFAULT,
108 CPUMDUMPTYPE_VERBOSE
109} CPUMDUMPTYPE;
110/** Pointer to a cpu info dump type. */
111typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
112
113
114/*******************************************************************************
115* Internal Functions *
116*******************************************************************************/
117static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
118static int cpumR3CpuIdInit(PVM pVM);
119static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
130
131
132/*******************************************************************************
133* Global Variables *
134*******************************************************************************/
135/** Saved state field descriptors for CPUMCTX. */
136static const SSMFIELD g_aCpumCtxFields[] =
137{
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
173 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
174 SSMFIELD_ENTRY( CPUMCTX, rdi),
175 SSMFIELD_ENTRY( CPUMCTX, rsi),
176 SSMFIELD_ENTRY( CPUMCTX, rbp),
177 SSMFIELD_ENTRY( CPUMCTX, rax),
178 SSMFIELD_ENTRY( CPUMCTX, rbx),
179 SSMFIELD_ENTRY( CPUMCTX, rdx),
180 SSMFIELD_ENTRY( CPUMCTX, rcx),
181 SSMFIELD_ENTRY( CPUMCTX, rsp),
182 SSMFIELD_ENTRY( CPUMCTX, rflags),
183 SSMFIELD_ENTRY( CPUMCTX, rip),
184 SSMFIELD_ENTRY( CPUMCTX, r8),
185 SSMFIELD_ENTRY( CPUMCTX, r9),
186 SSMFIELD_ENTRY( CPUMCTX, r10),
187 SSMFIELD_ENTRY( CPUMCTX, r11),
188 SSMFIELD_ENTRY( CPUMCTX, r12),
189 SSMFIELD_ENTRY( CPUMCTX, r13),
190 SSMFIELD_ENTRY( CPUMCTX, r14),
191 SSMFIELD_ENTRY( CPUMCTX, r15),
192 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
193 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
194 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
195 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
196 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
197 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
198 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, cr0),
229 SSMFIELD_ENTRY( CPUMCTX, cr2),
230 SSMFIELD_ENTRY( CPUMCTX, cr3),
231 SSMFIELD_ENTRY( CPUMCTX, cr4),
232 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
237 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
239 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
241 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
244 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
245 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
246 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
248 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
250 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
251 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
252 /* msrApicBase is not included here, it resides in the APIC device state. */
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
265 SSMFIELD_ENTRY_TERM()
266};
267
268/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
269 * registeres changed. */
270static const SSMFIELD g_aCpumCtxFieldsMem[] =
271{
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
306 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
307 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
308 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
309 SSMFIELD_ENTRY( CPUMCTX, rdi),
310 SSMFIELD_ENTRY( CPUMCTX, rsi),
311 SSMFIELD_ENTRY( CPUMCTX, rbp),
312 SSMFIELD_ENTRY( CPUMCTX, rax),
313 SSMFIELD_ENTRY( CPUMCTX, rbx),
314 SSMFIELD_ENTRY( CPUMCTX, rdx),
315 SSMFIELD_ENTRY( CPUMCTX, rcx),
316 SSMFIELD_ENTRY( CPUMCTX, rsp),
317 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
318 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
319 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
321 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
323 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
325 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
327 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
328 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
329 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
330 SSMFIELD_ENTRY( CPUMCTX, rflags),
331 SSMFIELD_ENTRY( CPUMCTX, rip),
332 SSMFIELD_ENTRY( CPUMCTX, r8),
333 SSMFIELD_ENTRY( CPUMCTX, r9),
334 SSMFIELD_ENTRY( CPUMCTX, r10),
335 SSMFIELD_ENTRY( CPUMCTX, r11),
336 SSMFIELD_ENTRY( CPUMCTX, r12),
337 SSMFIELD_ENTRY( CPUMCTX, r13),
338 SSMFIELD_ENTRY( CPUMCTX, r14),
339 SSMFIELD_ENTRY( CPUMCTX, r15),
340 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
356 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
357 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
358 SSMFIELD_ENTRY( CPUMCTX, cr0),
359 SSMFIELD_ENTRY( CPUMCTX, cr2),
360 SSMFIELD_ENTRY( CPUMCTX, cr3),
361 SSMFIELD_ENTRY( CPUMCTX, cr4),
362 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
364 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
365 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
366 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
367 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
368 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
369 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
370 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
371 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
372 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
374 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
375 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
377 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
379 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
381 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
382 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
383 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
384 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
386 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
387 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
388 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
389 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
393 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
394 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
395 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
396 SSMFIELD_ENTRY_TERM()
397};
398
399/** Saved state field descriptors for CPUMCTX_VER1_6. */
400static const SSMFIELD g_aCpumCtxFieldsV16[] =
401{
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
436 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
437 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
438 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
439 SSMFIELD_ENTRY( CPUMCTX, rdi),
440 SSMFIELD_ENTRY( CPUMCTX, rsi),
441 SSMFIELD_ENTRY( CPUMCTX, rbp),
442 SSMFIELD_ENTRY( CPUMCTX, rax),
443 SSMFIELD_ENTRY( CPUMCTX, rbx),
444 SSMFIELD_ENTRY( CPUMCTX, rdx),
445 SSMFIELD_ENTRY( CPUMCTX, rcx),
446 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
447 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
448 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
450 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
451 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
453 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
455 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
457 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
458 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
459 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
460 SSMFIELD_ENTRY( CPUMCTX, rflags),
461 SSMFIELD_ENTRY( CPUMCTX, rip),
462 SSMFIELD_ENTRY( CPUMCTX, r8),
463 SSMFIELD_ENTRY( CPUMCTX, r9),
464 SSMFIELD_ENTRY( CPUMCTX, r10),
465 SSMFIELD_ENTRY( CPUMCTX, r11),
466 SSMFIELD_ENTRY( CPUMCTX, r12),
467 SSMFIELD_ENTRY( CPUMCTX, r13),
468 SSMFIELD_ENTRY( CPUMCTX, r14),
469 SSMFIELD_ENTRY( CPUMCTX, r15),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
485 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
486 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
487 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
488 SSMFIELD_ENTRY( CPUMCTX, cr0),
489 SSMFIELD_ENTRY( CPUMCTX, cr2),
490 SSMFIELD_ENTRY( CPUMCTX, cr3),
491 SSMFIELD_ENTRY( CPUMCTX, cr4),
492 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
493 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
495 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
496 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
497 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
498 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
499 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
500 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
501 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
502 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
503 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
504 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
505 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
506 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
507 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
509 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
510 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
512 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
514 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
515 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
516 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
517 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
519 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
520 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
521 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
522 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
523 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
524 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
528 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
531 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
532 SSMFIELD_ENTRY_TERM()
533};
534
535
536/**
537 * Initializes the CPUM.
538 *
539 * @returns VBox status code.
540 * @param pVM Pointer to the VM.
541 */
542VMMR3DECL(int) CPUMR3Init(PVM pVM)
543{
544 LogFlow(("CPUMR3Init\n"));
545
546 /*
547 * Assert alignment and sizes.
548 */
549 AssertCompileMemberAlignment(VM, cpum.s, 32);
550 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
551 AssertCompileSizeAlignment(CPUMCTX, 64);
552 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
553 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
554 AssertCompileMemberAlignment(VM, cpum, 64);
555 AssertCompileMemberAlignment(VM, aCpus, 64);
556 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
557 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
558
559 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
560 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
561 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
562
563 /* Calculate the offset from CPUMCPU to CPUM. */
564 for (VMCPUID i = 0; i < pVM->cCpus; i++)
565 {
566 PVMCPU pVCpu = &pVM->aCpus[i];
567
568 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
569 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
570 }
571
572 /*
573 * Check that the CPU supports the minimum features we require.
574 */
575 if (!ASMHasCpuId())
576 {
577 Log(("The CPU doesn't support CPUID!\n"));
578 return VERR_UNSUPPORTED_CPU;
579 }
580 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
581 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
582
583 /* Setup the CR4 AND and OR masks used in the switcher */
584 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
585 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
586 {
587 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
588 /* No FXSAVE implies no SSE */
589 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
590 pVM->cpum.s.CR4.OrMask = 0;
591 }
592 else
593 {
594 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
595 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
596 }
597
598 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
599 {
600 Log(("The CPU doesn't support MMX!\n"));
601 return VERR_UNSUPPORTED_CPU;
602 }
603 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
604 {
605 Log(("The CPU doesn't support TSC!\n"));
606 return VERR_UNSUPPORTED_CPU;
607 }
608 /* Bogus on AMD? */
609 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
610 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
611
612 /*
613 * Detect the host CPU vendor.
614 * (The guest CPU vendor is re-detected later on.)
615 */
616 uint32_t uEAX, uEBX, uECX, uEDX;
617 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
618 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
619 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
620
621 /*
622 * Setup hypervisor startup values.
623 */
624
625 /*
626 * Register saved state data item.
627 */
628 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
629 NULL, cpumR3LiveExec, NULL,
630 NULL, cpumR3SaveExec, NULL,
631 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
632 if (RT_FAILURE(rc))
633 return rc;
634
635 /*
636 * Register info handlers and registers with the debugger facility.
637 */
638 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
639 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
640 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
641 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
642 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
643 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
644
645 rc = cpumR3DbgInit(pVM);
646 if (RT_FAILURE(rc))
647 return rc;
648
649 /*
650 * Initialize the Guest CPUID state.
651 */
652 rc = cpumR3CpuIdInit(pVM);
653 if (RT_FAILURE(rc))
654 return rc;
655 CPUMR3Reset(pVM);
656 return VINF_SUCCESS;
657}
658
659
660/**
661 * Detect the CPU vendor give n the
662 *
663 * @returns The vendor.
664 * @param uEAX EAX from CPUID(0).
665 * @param uEBX EBX from CPUID(0).
666 * @param uECX ECX from CPUID(0).
667 * @param uEDX EDX from CPUID(0).
668 */
669static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
670{
671 if (ASMIsValidStdRange(uEAX))
672 {
673 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
674 return CPUMCPUVENDOR_AMD;
675
676 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
677 return CPUMCPUVENDOR_INTEL;
678
679 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
680 return CPUMCPUVENDOR_VIA;
681
682 /** @todo detect the other buggers... */
683 }
684
685 return CPUMCPUVENDOR_UNKNOWN;
686}
687
688
689/**
690 * Fetches overrides for a CPUID leaf.
691 *
692 * @returns VBox status code.
693 * @param pLeaf The leaf to load the overrides into.
694 * @param pCfgNode The CFGM node containing the overrides
695 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
696 * @param iLeaf The CPUID leaf number.
697 */
698static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
699{
700 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
701 if (pLeafNode)
702 {
703 uint32_t u32;
704 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
705 if (RT_SUCCESS(rc))
706 pLeaf->eax = u32;
707 else
708 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
709
710 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
711 if (RT_SUCCESS(rc))
712 pLeaf->ebx = u32;
713 else
714 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
715
716 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
717 if (RT_SUCCESS(rc))
718 pLeaf->ecx = u32;
719 else
720 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
721
722 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
723 if (RT_SUCCESS(rc))
724 pLeaf->edx = u32;
725 else
726 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
727
728 }
729 return VINF_SUCCESS;
730}
731
732
733/**
734 * Load the overrides for a set of CPUID leaves.
735 *
736 * @returns VBox status code.
737 * @param paLeaves The leaf array.
738 * @param cLeaves The number of leaves.
739 * @param uStart The start leaf number.
740 * @param pCfgNode The CFGM node containing the overrides
741 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
742 */
743static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
744{
745 for (uint32_t i = 0; i < cLeaves; i++)
746 {
747 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
748 if (RT_FAILURE(rc))
749 return rc;
750 }
751
752 return VINF_SUCCESS;
753}
754
755/**
756 * Init a set of host CPUID leaves.
757 *
758 * @returns VBox status code.
759 * @param paLeaves The leaf array.
760 * @param cLeaves The number of leaves.
761 * @param uStart The start leaf number.
762 * @param pCfgNode The /CPUM/HostCPUID/ node.
763 */
764static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
765{
766 /* Using the ECX variant for all of them can't hurt... */
767 for (uint32_t i = 0; i < cLeaves; i++)
768 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
769
770 /* Load CPUID leaf override; we currently don't care if the user
771 specifies features the host CPU doesn't support. */
772 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
773}
774
775
776/**
777 * Initializes the emulated CPU's cpuid information.
778 *
779 * @returns VBox status code.
780 * @param pVM Pointer to the VM.
781 */
782static int cpumR3CpuIdInit(PVM pVM)
783{
784 PCPUM pCPUM = &pVM->cpum.s;
785 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
786 uint32_t i;
787 int rc;
788
789#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
790 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
791 { \
792 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
793 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
794 }
795#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
796 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
797 { \
798 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
799 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
800 }
801
802 /*
803 * Read the configuration.
804 */
805 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
806 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
807 * completely overridden by VirtualBox custom strings. Some
808 * CPUID information is withheld, like the cache info. */
809 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
810 AssertRCReturn(rc, rc);
811
812 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
813 * When non-zero CPUID features that could cause portability issues will be
814 * stripped. The higher the value the more features gets stripped. Higher
815 * values should only be used when older CPUs are involved since it may
816 * harm performance and maybe also cause problems with specific guests. */
817 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
818 AssertRCReturn(rc, rc);
819
820 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
821
822 /*
823 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
824 * been overridden).
825 */
826 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
827 * Overrides the host CPUID leaf values used for calculating the guest CPUID
828 * leaves. This can be used to preserve the CPUID values when moving a VM to a
829 * different machine. Another use is restricting (or extending) the feature set
830 * exposed to the guest. */
831 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
832 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
833 AssertRCReturn(rc, rc);
834 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
835 AssertRCReturn(rc, rc);
836 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
837 AssertRCReturn(rc, rc);
838
839 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
840 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
841
842 /*
843 * Determine the default leaf.
844 *
845 * Intel returns values of the highest standard function, while AMD
846 * returns zeros. VIA on the other hand seems to returning nothing or
847 * perhaps some random garbage, we don't try to duplicate this behavior.
848 */
849 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
850 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
851 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
852
853 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
854 * Expose CMPXCHG16B to the guest if supported by the host.
855 */
856 bool fCmpXchg16b;
857 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
858
859 /** @cfgm{/CPUM/MONITOR, boolean, true}
860 * Expose MONITOR/MWAIT instructions to the guest.
861 */
862 bool fMonitor;
863 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true); AssertRCReturn(rc, rc);
864
865 /* Cpuid 1 & 0x80000001:
866 * Only report features we can support.
867 *
868 * Note! When enabling new features the Synthetic CPU and Portable CPUID
869 * options may require adjusting (i.e. stripping what was enabled).
870 */
871 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
872 | X86_CPUID_FEATURE_EDX_VME
873 | X86_CPUID_FEATURE_EDX_DE
874 | X86_CPUID_FEATURE_EDX_PSE
875 | X86_CPUID_FEATURE_EDX_TSC
876 | X86_CPUID_FEATURE_EDX_MSR
877 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
878 | X86_CPUID_FEATURE_EDX_MCE
879 | X86_CPUID_FEATURE_EDX_CX8
880 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
881 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
882 //| X86_CPUID_FEATURE_EDX_SEP
883 | X86_CPUID_FEATURE_EDX_MTRR
884 | X86_CPUID_FEATURE_EDX_PGE
885 | X86_CPUID_FEATURE_EDX_MCA
886 | X86_CPUID_FEATURE_EDX_CMOV
887 | X86_CPUID_FEATURE_EDX_PAT
888 | X86_CPUID_FEATURE_EDX_PSE36
889 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
890 | X86_CPUID_FEATURE_EDX_CLFSH
891 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
892 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
893 | X86_CPUID_FEATURE_EDX_MMX
894 | X86_CPUID_FEATURE_EDX_FXSR
895 | X86_CPUID_FEATURE_EDX_SSE
896 | X86_CPUID_FEATURE_EDX_SSE2
897 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
898 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
899 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
900 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
901 | 0;
902 pCPUM->aGuestCpuIdStd[1].ecx &= 0
903 | X86_CPUID_FEATURE_ECX_SSE3
904 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
905 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
906 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
907 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
908 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
909 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
910 | X86_CPUID_FEATURE_ECX_SSSE3
911 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
912 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
913 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
914 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
915 /* ECX Bit 21 - x2APIC support - not yet. */
916 // | X86_CPUID_FEATURE_ECX_X2APIC
917 /* ECX Bit 23 - POPCNT instruction. */
918 //| X86_CPUID_FEATURE_ECX_POPCNT
919 | 0;
920 if (pCPUM->u8PortableCpuIdLevel > 0)
921 {
922 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
923 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
924 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
925 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
926 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
927 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
928 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
929 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
930
931 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
932 | X86_CPUID_FEATURE_EDX_PSN
933 | X86_CPUID_FEATURE_EDX_DS
934 | X86_CPUID_FEATURE_EDX_ACPI
935 | X86_CPUID_FEATURE_EDX_SS
936 | X86_CPUID_FEATURE_EDX_TM
937 | X86_CPUID_FEATURE_EDX_PBE
938 )));
939 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
940 | X86_CPUID_FEATURE_ECX_DTES64
941 | X86_CPUID_FEATURE_ECX_CPLDS
942 | X86_CPUID_FEATURE_ECX_VMX
943 | X86_CPUID_FEATURE_ECX_SMX
944 | X86_CPUID_FEATURE_ECX_EST
945 | X86_CPUID_FEATURE_ECX_TM2
946 | X86_CPUID_FEATURE_ECX_CNTXID
947 | X86_CPUID_FEATURE_ECX_FMA
948 | X86_CPUID_FEATURE_ECX_CX16
949 | X86_CPUID_FEATURE_ECX_TPRUPDATE
950 | X86_CPUID_FEATURE_ECX_PDCM
951 | X86_CPUID_FEATURE_ECX_DCA
952 | X86_CPUID_FEATURE_ECX_MOVBE
953 | X86_CPUID_FEATURE_ECX_AES
954 | X86_CPUID_FEATURE_ECX_POPCNT
955 | X86_CPUID_FEATURE_ECX_XSAVE
956 | X86_CPUID_FEATURE_ECX_OSXSAVE
957 | X86_CPUID_FEATURE_ECX_AVX
958 )));
959 }
960
961 /* Cpuid 0x80000001:
962 * Only report features we can support.
963 *
964 * Note! When enabling new features the Synthetic CPU and Portable CPUID
965 * options may require adjusting (i.e. stripping what was enabled).
966 *
967 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
968 */
969 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
970 | X86_CPUID_AMD_FEATURE_EDX_VME
971 | X86_CPUID_AMD_FEATURE_EDX_DE
972 | X86_CPUID_AMD_FEATURE_EDX_PSE
973 | X86_CPUID_AMD_FEATURE_EDX_TSC
974 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
975 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
976 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
977 | X86_CPUID_AMD_FEATURE_EDX_CX8
978 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
979 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
980 //| X86_CPUID_EXT_FEATURE_EDX_SEP
981 | X86_CPUID_AMD_FEATURE_EDX_MTRR
982 | X86_CPUID_AMD_FEATURE_EDX_PGE
983 | X86_CPUID_AMD_FEATURE_EDX_MCA
984 | X86_CPUID_AMD_FEATURE_EDX_CMOV
985 | X86_CPUID_AMD_FEATURE_EDX_PAT
986 | X86_CPUID_AMD_FEATURE_EDX_PSE36
987 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
988 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
989 | X86_CPUID_AMD_FEATURE_EDX_MMX
990 | X86_CPUID_AMD_FEATURE_EDX_FXSR
991 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
992 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
993 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
994 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
995 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
996 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
997 | 0;
998 pCPUM->aGuestCpuIdExt[1].ecx &= 0
999 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1000 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
1001 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
1002 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1003 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1004 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1005 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1006 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1007 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1008 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1009 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1010 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1011 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1012 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1013 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1014 | 0;
1015 if (pCPUM->u8PortableCpuIdLevel > 0)
1016 {
1017 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1018 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1019 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1020 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1021 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1022 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1023 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1024
1025 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1026 | X86_CPUID_AMD_FEATURE_ECX_SVM
1027 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1028 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1029 | X86_CPUID_AMD_FEATURE_ECX_ABM
1030 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1031 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1032 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1033 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1034 | X86_CPUID_AMD_FEATURE_ECX_IBS
1035 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1036 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1037 | X86_CPUID_AMD_FEATURE_ECX_WDT
1038 | UINT32_C(0xffffc000)
1039 )));
1040 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1041 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1042 | RT_BIT(18)
1043 | RT_BIT(19)
1044 | RT_BIT(21)
1045 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1046 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1047 | RT_BIT(28)
1048 )));
1049 }
1050
1051 /*
1052 * Apply the Synthetic CPU modifications. (TODO: move this up)
1053 */
1054 if (pCPUM->fSyntheticCpu)
1055 {
1056 static const char s_szVendor[13] = "VirtualBox ";
1057 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1058
1059 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1060
1061 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1062 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1063
1064 /* 0: Vendor */
1065 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1066 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1067 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1068
1069 /* 1.eax: Version information. family : model : stepping */
1070 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1071
1072 /* Leaves 2 - 4 are Intel only - zero them out */
1073 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1074 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1075 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1076
1077 /* Leaf 5 = monitor/mwait */
1078
1079 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1080 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1081 /* AMD only - set to zero. */
1082 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1083
1084 /* 0x800000001: shared feature bits are set dynamically. */
1085 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1086
1087 /* 0x800000002-4: Processor Name String Identifier. */
1088 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1089 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1090 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1091 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1092 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1093 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1094 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1095 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1096 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1097 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1098 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1099 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1100
1101 /* 0x800000005-7 - reserved -> zero */
1102 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1103 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1104 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1105
1106 /* 0x800000008: only the max virtual and physical address size. */
1107 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1108 }
1109
1110 /*
1111 * Hide HTT, multicode, SMP, whatever.
1112 * (APIC-ID := 0 and #LogCpus := 0)
1113 */
1114 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1115#ifdef VBOX_WITH_MULTI_CORE
1116 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1117 && pVM->cCpus > 1)
1118 {
1119 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1120 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1121 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1122 }
1123#endif
1124
1125 /* Cpuid 2:
1126 * Intel: Cache and TLB information
1127 * AMD: Reserved
1128 * VIA: Reserved
1129 * Safe to expose; restrict the number of calls to 1 for the portable case.
1130 */
1131 if ( pCPUM->u8PortableCpuIdLevel > 0
1132 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1133 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1134 {
1135 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1136 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1137 }
1138
1139 /* Cpuid 3:
1140 * Intel: EAX, EBX - reserved (transmeta uses these)
1141 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1142 * AMD: Reserved
1143 * VIA: Reserved
1144 * Safe to expose
1145 */
1146 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1147 {
1148 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1149 if (pCPUM->u8PortableCpuIdLevel > 0)
1150 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1151 }
1152
1153 /* Cpuid 4:
1154 * Intel: Deterministic Cache Parameters Leaf
1155 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1156 * AMD: Reserved
1157 * VIA: Reserved
1158 * Safe to expose, except for EAX:
1159 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1160 * Bits 31-26: Maximum number of processor cores in this physical package**
1161 * Note: These SMP values are constant regardless of ECX
1162 */
1163 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1164 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1165#ifdef VBOX_WITH_MULTI_CORE
1166 if ( pVM->cCpus > 1
1167 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1168 {
1169 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1170 /* One logical processor with possibly multiple cores. */
1171 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1172 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1173 }
1174#endif
1175
1176 /* Cpuid 5: Monitor/mwait Leaf
1177 * Intel: ECX, EDX - reserved
1178 * EAX, EBX - Smallest and largest monitor line size
1179 * AMD: EDX - reserved
1180 * EAX, EBX - Smallest and largest monitor line size
1181 * ECX - extensions (ignored for now)
1182 * VIA: Reserved
1183 * Safe to expose
1184 */
1185 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1186 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1187
1188 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1189 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1190 * Expose MWAIT extended features to the guest. For now we expose
1191 * just MWAIT break on interrupt feature (bit 1).
1192 */
1193 bool fMWaitExtensions;
1194 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1195 if (fMWaitExtensions)
1196 {
1197 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1198 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
1199 it shall be part of our power management virtualization model */
1200#if 0
1201 /* MWAIT sub C-states */
1202 pCPUM->aGuestCpuIdStd[5].edx =
1203 (0 << 0) /* 0 in C0 */ |
1204 (2 << 4) /* 2 in C1 */ |
1205 (2 << 8) /* 2 in C2 */ |
1206 (2 << 12) /* 2 in C3 */ |
1207 (0 << 16) /* 0 in C4 */
1208 ;
1209#endif
1210 }
1211 else
1212 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1213
1214 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1215 * Safe to pass on to the guest.
1216 *
1217 * Intel: 0x800000005 reserved
1218 * 0x800000006 L2 cache information
1219 * AMD: 0x800000005 L1 cache information
1220 * 0x800000006 L2/L3 cache information
1221 * VIA: 0x800000005 TLB and L1 cache information
1222 * 0x800000006 L2 cache information
1223 */
1224
1225 /* Cpuid 0x800000007:
1226 * Intel: Reserved
1227 * AMD: EAX, EBX, ECX - reserved
1228 * EDX: Advanced Power Management Information
1229 * VIA: Reserved
1230 */
1231 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1232 {
1233 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1234
1235 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1236
1237 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1238 {
1239 /* Only expose the TSC invariant capability bit to the guest. */
1240 pCPUM->aGuestCpuIdExt[7].edx &= 0
1241 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1242 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1243 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1244 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1245 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1246 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1247 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1248 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1249#if 0
1250 /*
1251 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1252 * Linux kernels blindly assume that the AMD performance counters work
1253 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1254 * bit for them though.)
1255 */
1256 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1257#endif
1258 | 0;
1259 }
1260 else
1261 pCPUM->aGuestCpuIdExt[7].edx = 0;
1262 }
1263
1264 /* Cpuid 0x800000008:
1265 * Intel: EAX: Virtual/Physical address Size
1266 * EBX, ECX, EDX - reserved
1267 * AMD: EBX, EDX - reserved
1268 * EAX: Virtual/Physical/Guest address Size
1269 * ECX: Number of cores + APICIdCoreIdSize
1270 * VIA: EAX: Virtual/Physical address Size
1271 * EBX, ECX, EDX - reserved
1272 */
1273 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1274 {
1275 /* Only expose the virtual and physical address sizes to the guest. */
1276 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1277 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1278 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1279 * NC (0-7) Number of cores; 0 equals 1 core */
1280 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1281#ifdef VBOX_WITH_MULTI_CORE
1282 if ( pVM->cCpus > 1
1283 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1284 {
1285 /* Legacy method to determine the number of cores. */
1286 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1287 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1288 }
1289#endif
1290 }
1291
1292 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1293 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1294 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1295 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1296 */
1297 bool fNt4LeafLimit;
1298 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1299 if (fNt4LeafLimit && pCPUM->aGuestCpuIdStd[0].eax > 3)
1300 pCPUM->aGuestCpuIdStd[0].eax = 3;
1301
1302 /*
1303 * Limit it the number of entries and fill the remaining with the defaults.
1304 *
1305 * The limits are masking off stuff about power saving and similar, this
1306 * is perhaps a bit crudely done as there is probably some relatively harmless
1307 * info too in these leaves (like words about having a constant TSC).
1308 */
1309 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1310 pCPUM->aGuestCpuIdStd[0].eax = 5;
1311 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1312 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1313
1314 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1315 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1316 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1317 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1318 : 0;
1319 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1320 i++)
1321 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1322
1323 /*
1324 * Centaur stuff (VIA).
1325 *
1326 * The important part here (we think) is to make sure the 0xc0000000
1327 * function returns 0xc0000001. As for the features, we don't currently
1328 * let on about any of those... 0xc0000002 seems to be some
1329 * temperature/hz/++ stuff, include it as well (static).
1330 */
1331 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1332 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1333 {
1334 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1335 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1336 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1337 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1338 i++)
1339 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1340 }
1341 else
1342 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1343 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1344
1345 /*
1346 * Hypervisor identification.
1347 *
1348 * We only return minimal information, primarily ensuring that the
1349 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1350 * Currently we do not support any hypervisor-specific interface.
1351 */
1352 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1353 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1354 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1355 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1356 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1357 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1358
1359 /*
1360 * Mini CPU selection support for making Mac OS X happy.
1361 */
1362 if (pCPUM->enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1363 {
1364 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
1365 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
1366 * probably going to be a temporary hack, so don't depend on this.
1367 * The 1st byte of the value is the stepping, the 2nd byte value is the model
1368 * number and the 3rd byte value is the family, and the 4th value must be zero.
1369 */
1370 uint32_t uMaxIntelFamilyModelStep;
1371 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
1372 AssertRCReturn(rc, rc);
1373 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pCPUM->aGuestCpuIdStd[1].eax),
1374 ASMGetCpuModelIntel(pCPUM->aGuestCpuIdStd[1].eax),
1375 ASMGetCpuFamily(pCPUM->aGuestCpuIdStd[1].eax),
1376 0);
1377 if (uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1378 {
1379 uint32_t uNew = pCPUM->aGuestCpuIdStd[1].eax & UINT32_C(0xf0003000);
1380 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1381 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1382 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1383 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1384 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1385 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1386 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1387 pCPUM->aGuestCpuIdStd[1].eax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1388 pCPUM->aGuestCpuIdStd[1].eax = uNew;
1389 }
1390 }
1391
1392 /*
1393 * Load CPUID overrides from configuration.
1394 * Note: Kind of redundant now, but allows unchanged overrides
1395 */
1396 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1397 * Overrides the CPUID leaf values. */
1398 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1399 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1400 AssertRCReturn(rc, rc);
1401 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1402 AssertRCReturn(rc, rc);
1403 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1404 AssertRCReturn(rc, rc);
1405
1406 /*
1407 * Check if PAE was explicitely enabled by the user.
1408 */
1409 bool fEnable;
1410 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1411 if (fEnable)
1412 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1413
1414 /*
1415 * We don't normally enable NX for raw-mode, so give the user a chance to
1416 * force it on.
1417 */
1418 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1419 if (fEnable)
1420 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1421
1422 /*
1423 * We don't enable the Hypervisor Present bit by default, but it may
1424 * be needed by some guests.
1425 */
1426 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1427 if (fEnable)
1428 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1429
1430#undef PORTABLE_DISABLE_FEATURE_BIT
1431#undef PORTABLE_CLEAR_BITS_WHEN
1432
1433 return VINF_SUCCESS;
1434}
1435
1436
1437/**
1438 * Applies relocations to data and code managed by this
1439 * component. This function will be called at init and
1440 * whenever the VMM need to relocate it self inside the GC.
1441 *
1442 * The CPUM will update the addresses used by the switcher.
1443 *
1444 * @param pVM The VM.
1445 */
1446VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1447{
1448 LogFlow(("CPUMR3Relocate\n"));
1449
1450 /* Recheck the guest DRx values in raw-mode. */
1451 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1452 CPUMRecalcHyperDRx(&pVM->aCpus[iCpu], UINT8_MAX, false);
1453}
1454
1455
1456/**
1457 * Apply late CPUM property changes based on the fHWVirtEx setting
1458 *
1459 * @param pVM Pointer to the VM.
1460 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1461 */
1462VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1463{
1464 /*
1465 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1466 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1467 * of processors from (cpuid(4).eax >> 26) + 1.
1468 *
1469 * Note: this code is obsolete, but let's keep it here for reference.
1470 * Purpose is valid when we artificially cap the max std id to less than 4.
1471 */
1472 if (!fHWVirtExEnabled)
1473 {
1474 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1475 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1476 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1477 }
1478}
1479
1480/**
1481 * Terminates the CPUM.
1482 *
1483 * Termination means cleaning up and freeing all resources,
1484 * the VM it self is at this point powered off or suspended.
1485 *
1486 * @returns VBox status code.
1487 * @param pVM Pointer to the VM.
1488 */
1489VMMR3DECL(int) CPUMR3Term(PVM pVM)
1490{
1491#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1492 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1493 {
1494 PVMCPU pVCpu = &pVM->aCpus[i];
1495 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1496
1497 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1498 pVCpu->cpum.s.uMagic = 0;
1499 pCtx->dr[5] = 0;
1500 }
1501#else
1502 NOREF(pVM);
1503#endif
1504 return VINF_SUCCESS;
1505}
1506
1507
1508/**
1509 * Resets a virtual CPU.
1510 *
1511 * Used by CPUMR3Reset and CPU hot plugging.
1512 *
1513 * @param pVCpu Pointer to the VMCPU.
1514 */
1515VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1516{
1517 /** @todo anything different for VCPU > 0? */
1518 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1519
1520 /*
1521 * Initialize everything to ZERO first.
1522 */
1523 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1524 memset(pCtx, 0, sizeof(*pCtx));
1525 pVCpu->cpum.s.fUseFlags = fUseFlags;
1526
1527 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1528 pCtx->eip = 0x0000fff0;
1529 pCtx->edx = 0x00000600; /* P6 processor */
1530 pCtx->eflags.Bits.u1Reserved0 = 1;
1531
1532 pCtx->cs.Sel = 0xf000;
1533 pCtx->cs.ValidSel = 0xf000;
1534 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1535 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1536 pCtx->cs.u32Limit = 0x0000ffff;
1537 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1538 pCtx->cs.Attr.n.u1Present = 1;
1539 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1540
1541 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1542 pCtx->ds.u32Limit = 0x0000ffff;
1543 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1544 pCtx->ds.Attr.n.u1Present = 1;
1545 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1546
1547 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1548 pCtx->es.u32Limit = 0x0000ffff;
1549 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1550 pCtx->es.Attr.n.u1Present = 1;
1551 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1552
1553 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1554 pCtx->fs.u32Limit = 0x0000ffff;
1555 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1556 pCtx->fs.Attr.n.u1Present = 1;
1557 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1558
1559 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1560 pCtx->gs.u32Limit = 0x0000ffff;
1561 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1562 pCtx->gs.Attr.n.u1Present = 1;
1563 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1564
1565 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1566 pCtx->ss.u32Limit = 0x0000ffff;
1567 pCtx->ss.Attr.n.u1Present = 1;
1568 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1569 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1570
1571 pCtx->idtr.cbIdt = 0xffff;
1572 pCtx->gdtr.cbGdt = 0xffff;
1573
1574 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1575 pCtx->ldtr.u32Limit = 0xffff;
1576 pCtx->ldtr.Attr.n.u1Present = 1;
1577 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1578
1579 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1580 pCtx->tr.u32Limit = 0xffff;
1581 pCtx->tr.Attr.n.u1Present = 1;
1582 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1583
1584 pCtx->dr[6] = X86_DR6_INIT_VAL;
1585 pCtx->dr[7] = X86_DR7_INIT_VAL;
1586
1587 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1588 pCtx->fpu.FCW = 0x37f;
1589
1590 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1591 IA-32 Processor States Following Power-up, Reset, or INIT */
1592 pCtx->fpu.MXCSR = 0x1F80;
1593 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1594 supports all bits, since a zero value here should be read as 0xffbf. */
1595
1596 /* Init PAT MSR */
1597 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1598
1599 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1600 * The Intel docs don't mention it. */
1601 Assert(!pCtx->msrEFER);
1602
1603 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1604 * called from each EMT while we're getting called by CPUMR3Reset()
1605 * iteratively on the same thread. Fix later. */
1606#if 0
1607 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1608 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1609#endif
1610
1611
1612 /* C-state control. Guesses. */
1613 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1614
1615
1616 /*
1617 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1618 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1619 */
1620 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1621}
1622
1623
1624/**
1625 * Resets the CPU.
1626 *
1627 * @returns VINF_SUCCESS.
1628 * @param pVM Pointer to the VM.
1629 */
1630VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1631{
1632 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1633 {
1634 CPUMR3ResetCpu(&pVM->aCpus[i]);
1635
1636#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1637 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1638
1639 /* Magic marker for searching in crash dumps. */
1640 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1641 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1642 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1643#endif
1644 }
1645}
1646
1647
1648/**
1649 * Called both in pass 0 and the final pass.
1650 *
1651 * @param pVM Pointer to the VM.
1652 * @param pSSM The saved state handle.
1653 */
1654static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1655{
1656 /*
1657 * Save all the CPU ID leaves here so we can check them for compatibility
1658 * upon loading.
1659 */
1660 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1661 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1662
1663 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1664 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1665
1666 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1667 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1668
1669 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1670
1671 /*
1672 * Save a good portion of the raw CPU IDs as well as they may come in
1673 * handy when validating features for raw mode.
1674 */
1675 CPUMCPUID aRawStd[16];
1676 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1677 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1678 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1679 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1680
1681 CPUMCPUID aRawExt[32];
1682 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1683 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1684 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1685 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1686}
1687
1688
1689/**
1690 * Loads the CPU ID leaves saved by pass 0.
1691 *
1692 * @returns VBox status code.
1693 * @param pVM Pointer to the VM.
1694 * @param pSSM The saved state handle.
1695 * @param uVersion The format version.
1696 */
1697static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1698{
1699 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1700
1701 /*
1702 * Define a bunch of macros for simplifying the code.
1703 */
1704 /* Generic expression + failure message. */
1705#define CPUID_CHECK_RET(expr, fmt) \
1706 do { \
1707 if (!(expr)) \
1708 { \
1709 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1710 if (fStrictCpuIdChecks) \
1711 { \
1712 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1713 RTStrFree(pszMsg); \
1714 return rcCpuid; \
1715 } \
1716 LogRel(("CPUM: %s\n", pszMsg)); \
1717 RTStrFree(pszMsg); \
1718 } \
1719 } while (0)
1720#define CPUID_CHECK_WRN(expr, fmt) \
1721 do { \
1722 if (!(expr)) \
1723 LogRel(fmt); \
1724 } while (0)
1725
1726 /* For comparing two values and bitch if they differs. */
1727#define CPUID_CHECK2_RET(what, host, saved) \
1728 do { \
1729 if ((host) != (saved)) \
1730 { \
1731 if (fStrictCpuIdChecks) \
1732 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1733 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1734 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1735 } \
1736 } while (0)
1737#define CPUID_CHECK2_WRN(what, host, saved) \
1738 do { \
1739 if ((host) != (saved)) \
1740 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1741 } while (0)
1742
1743 /* For checking raw cpu features (raw mode). */
1744#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1745 do { \
1746 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1747 { \
1748 if (fStrictCpuIdChecks) \
1749 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1750 N_(#bit " mismatch: host=%d saved=%d"), \
1751 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1752 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1753 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1754 } \
1755 } while (0)
1756#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1757 do { \
1758 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1759 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1760 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1761 } while (0)
1762#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1763
1764 /* For checking guest features. */
1765#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1766 do { \
1767 if ( (aGuestCpuId##set [1].reg & bit) \
1768 && !(aHostRaw##set [1].reg & bit) \
1769 && !(aHostOverride##set [1].reg & bit) \
1770 && !(aGuestOverride##set [1].reg & bit) \
1771 ) \
1772 { \
1773 if (fStrictCpuIdChecks) \
1774 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1775 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1776 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1777 } \
1778 } while (0)
1779#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1780 do { \
1781 if ( (aGuestCpuId##set [1].reg & bit) \
1782 && !(aHostRaw##set [1].reg & bit) \
1783 && !(aHostOverride##set [1].reg & bit) \
1784 && !(aGuestOverride##set [1].reg & bit) \
1785 ) \
1786 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1787 } while (0)
1788#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1789 do { \
1790 if ( (aGuestCpuId##set [1].reg & bit) \
1791 && !(aHostRaw##set [1].reg & bit) \
1792 && !(aHostOverride##set [1].reg & bit) \
1793 && !(aGuestOverride##set [1].reg & bit) \
1794 ) \
1795 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1796 } while (0)
1797#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1798
1799 /* For checking guest features if AMD guest CPU. */
1800#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1801 do { \
1802 if ( (aGuestCpuId##set [1].reg & bit) \
1803 && fGuestAmd \
1804 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1805 && !(aHostOverride##set [1].reg & bit) \
1806 && !(aGuestOverride##set [1].reg & bit) \
1807 ) \
1808 { \
1809 if (fStrictCpuIdChecks) \
1810 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1811 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1812 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1813 } \
1814 } while (0)
1815#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1816 do { \
1817 if ( (aGuestCpuId##set [1].reg & bit) \
1818 && fGuestAmd \
1819 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1820 && !(aHostOverride##set [1].reg & bit) \
1821 && !(aGuestOverride##set [1].reg & bit) \
1822 ) \
1823 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1824 } while (0)
1825#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1826 do { \
1827 if ( (aGuestCpuId##set [1].reg & bit) \
1828 && fGuestAmd \
1829 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1830 && !(aHostOverride##set [1].reg & bit) \
1831 && !(aGuestOverride##set [1].reg & bit) \
1832 ) \
1833 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1834 } while (0)
1835#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1836
1837 /* For checking AMD features which have a corresponding bit in the standard
1838 range. (Intel defines very few bits in the extended feature sets.) */
1839#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1840 do { \
1841 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1842 && !(fHostAmd \
1843 ? aHostRawExt[1].reg & (ExtBit) \
1844 : aHostRawStd[1].reg & (StdBit)) \
1845 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1846 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1847 ) \
1848 { \
1849 if (fStrictCpuIdChecks) \
1850 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1851 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1852 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1853 } \
1854 } while (0)
1855#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1856 do { \
1857 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1858 && !(fHostAmd \
1859 ? aHostRawExt[1].reg & (ExtBit) \
1860 : aHostRawStd[1].reg & (StdBit)) \
1861 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1862 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1863 ) \
1864 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1865 } while (0)
1866#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1867 do { \
1868 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1869 && !(fHostAmd \
1870 ? aHostRawExt[1].reg & (ExtBit) \
1871 : aHostRawStd[1].reg & (StdBit)) \
1872 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1873 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1874 ) \
1875 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1876 } while (0)
1877#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1878
1879 /*
1880 * Load them into stack buffers first.
1881 */
1882 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1883 uint32_t cGuestCpuIdStd;
1884 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1885 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1886 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1887 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1888
1889 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1890 uint32_t cGuestCpuIdExt;
1891 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1892 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1893 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1894 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1895
1896 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1897 uint32_t cGuestCpuIdCentaur;
1898 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1899 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1900 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1901 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1902
1903 CPUMCPUID GuestCpuIdDef;
1904 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1905 AssertRCReturn(rc, rc);
1906
1907 CPUMCPUID aRawStd[16];
1908 uint32_t cRawStd;
1909 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1910 if (cRawStd > RT_ELEMENTS(aRawStd))
1911 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1912 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1913
1914 CPUMCPUID aRawExt[32];
1915 uint32_t cRawExt;
1916 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1917 if (cRawExt > RT_ELEMENTS(aRawExt))
1918 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1919 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1920 AssertRCReturn(rc, rc);
1921
1922 /*
1923 * Note that we support restoring less than the current amount of standard
1924 * leaves because we've been allowed more is newer version of VBox.
1925 *
1926 * So, pad new entries with the default.
1927 */
1928 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1929 aGuestCpuIdStd[i] = GuestCpuIdDef;
1930
1931 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1932 aGuestCpuIdExt[i] = GuestCpuIdDef;
1933
1934 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1935 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1936
1937 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1938 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1939
1940 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1941 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1942
1943 /*
1944 * Get the raw CPU IDs for the current host.
1945 */
1946 CPUMCPUID aHostRawStd[16];
1947 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1948 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1949
1950 CPUMCPUID aHostRawExt[32];
1951 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1952 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1953
1954 /*
1955 * Get the host and guest overrides so we don't reject the state because
1956 * some feature was enabled thru these interfaces.
1957 * Note! We currently only need the feature leaves, so skip rest.
1958 */
1959 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
1960 CPUMCPUID aGuestOverrideStd[2];
1961 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
1962 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
1963
1964 CPUMCPUID aGuestOverrideExt[2];
1965 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
1966 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
1967
1968 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
1969 CPUMCPUID aHostOverrideStd[2];
1970 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
1971 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
1972
1973 CPUMCPUID aHostOverrideExt[2];
1974 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
1975 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
1976
1977 /*
1978 * This can be skipped.
1979 */
1980 bool fStrictCpuIdChecks;
1981 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
1982
1983
1984
1985 /*
1986 * For raw-mode we'll require that the CPUs are very similar since we don't
1987 * intercept CPUID instructions for user mode applications.
1988 */
1989 if (!HMIsEnabled(pVM))
1990 {
1991 /* CPUID(0) */
1992 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
1993 && aHostRawStd[0].ecx == aRawStd[0].ecx
1994 && aHostRawStd[0].edx == aRawStd[0].edx,
1995 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
1996 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
1997 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
1998 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
1999 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
2000 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2001
2002 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
2003
2004 /* CPUID(1).eax */
2005 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
2006 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
2007 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
2008
2009 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
2010 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
2011 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
2012
2013 /* CPUID(1).ecx */
2014 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
2015 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
2016 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
2017 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2018 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
2019 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
2020 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
2021 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
2022 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
2023 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
2024 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
2025 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2026 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
2027 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
2028 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
2029 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
2030 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2031 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2032 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
2033 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
2034 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
2035 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2036 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2037 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2038 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2039 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2040 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2041 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2042 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2043 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2044 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2045 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2046
2047 /* CPUID(1).edx */
2048 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2049 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2050 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2051 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2052 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2053 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2054 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2055 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2056 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2057 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2058 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2059 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2060 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2061 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2062 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2063 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2064 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2065 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2066 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2067 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2068 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2069 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2070 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2071 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2072 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2073 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2074 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2075 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2076 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2077 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2078 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2079 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2080
2081 /* CPUID(2) - config, mostly about caches. ignore. */
2082 /* CPUID(3) - processor serial number. ignore. */
2083 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2084 /* CPUID(5) - mwait/monitor config. ignore. */
2085 /* CPUID(6) - power management. ignore. */
2086 /* CPUID(7) - ???. ignore. */
2087 /* CPUID(8) - ???. ignore. */
2088 /* CPUID(9) - DCA. ignore for now. */
2089 /* CPUID(a) - PeMo info. ignore for now. */
2090 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2091
2092 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2093 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2094 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2095 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2096 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2097 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2098 {
2099 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2100 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2101 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2102 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2103 }
2104
2105 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2106 Note! Intel have/is marking many of the fields here as reserved. We
2107 will verify them as if it's an AMD CPU. */
2108 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2109 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2110 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2111 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2112 {
2113 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2114 && aHostRawExt[0].ecx == aRawExt[0].ecx
2115 && aHostRawExt[0].edx == aRawExt[0].edx,
2116 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2117 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2118 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2119 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2120
2121 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2122 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2123 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2124 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2125 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2126 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2127
2128 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2129 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2130 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2131 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2132
2133 /* CPUID(0x80000001).ecx */
2134 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2135 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2136 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2137 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2138 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2139 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2140 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2141 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2142 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2143 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2144 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2145 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2146 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2147 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2148 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2149 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2150 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2151 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2152 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2153 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2154 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2155 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2156 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2157 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2158 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2159 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2160 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2161 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2162 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2163 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2164 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2165 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2166
2167 /* CPUID(0x80000001).edx */
2168 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2169 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2170 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2171 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2172 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2173 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2174 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2175 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2176 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2177 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2178 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2179 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2180 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2181 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2182 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2183 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2184 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2185 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2186 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2187 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2188 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2189 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2190 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2191 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2192 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2193 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2194 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2195 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2196 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2197 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2198 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2199 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2200
2201 /** @todo verify the rest as well. */
2202 }
2203 }
2204
2205
2206
2207 /*
2208 * Verify that we can support the features already exposed to the guest on
2209 * this host.
2210 *
2211 * Most of the features we're emulating requires intercepting instruction
2212 * and doing it the slow way, so there is no need to warn when they aren't
2213 * present in the host CPU. Thus we use IGN instead of EMU on these.
2214 *
2215 * Trailing comments:
2216 * "EMU" - Possible to emulate, could be lots of work and very slow.
2217 * "EMU?" - Can this be emulated?
2218 */
2219 /* CPUID(1).ecx */
2220 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2221 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2222 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2223 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2224 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2225 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2226 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2227 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2228 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2229 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2230 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2231 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2232 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2233 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2234 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2235 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2236 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2237 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2238 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2239 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2240 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2241 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2242 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2243 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2244 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2245 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2246 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2247 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2248 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2249 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2250 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2251 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2252
2253 /* CPUID(1).edx */
2254 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2255 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2256 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2257 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2258 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2259 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2260 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2261 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2262 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2263 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2264 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2265 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2266 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2267 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2268 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2269 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2270 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2271 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2272 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2273 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2274 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2275 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2276 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2277 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2278 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2279 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2280 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2281 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2282 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2283 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2284 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2285 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2286
2287 /* CPUID(0x80000000). */
2288 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2289 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2290 {
2291 /** @todo deal with no 0x80000001 on the host. */
2292 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2293 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2294
2295 /* CPUID(0x80000001).ecx */
2296 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2297 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2298 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2299 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2300 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2301 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2302 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2303 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2304 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2305 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2306 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2307 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2308 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2309 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2310 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2311 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2312 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2313 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2314 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2315 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2316 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2317 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2318 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2319 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2320 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2321 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2322 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2323 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2324 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2325 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2326 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2327 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2328
2329 /* CPUID(0x80000001).edx */
2330 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2331 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2332 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2333 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2334 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2335 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2336 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2337 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2338 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2339 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2340 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2341 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2342 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2343 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2344 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2345 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2346 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2347 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2348 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2349 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2350 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2351 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2352 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2353 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2354 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2355 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2356 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2357 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2358 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2359 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2360 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2361 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2362 }
2363
2364 /*
2365 * We're good, commit the CPU ID leaves.
2366 */
2367 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2368 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2369 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2370 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2371
2372#undef CPUID_CHECK_RET
2373#undef CPUID_CHECK_WRN
2374#undef CPUID_CHECK2_RET
2375#undef CPUID_CHECK2_WRN
2376#undef CPUID_RAW_FEATURE_RET
2377#undef CPUID_RAW_FEATURE_WRN
2378#undef CPUID_RAW_FEATURE_IGN
2379#undef CPUID_GST_FEATURE_RET
2380#undef CPUID_GST_FEATURE_WRN
2381#undef CPUID_GST_FEATURE_EMU
2382#undef CPUID_GST_FEATURE_IGN
2383#undef CPUID_GST_FEATURE2_RET
2384#undef CPUID_GST_FEATURE2_WRN
2385#undef CPUID_GST_FEATURE2_EMU
2386#undef CPUID_GST_FEATURE2_IGN
2387#undef CPUID_GST_AMD_FEATURE_RET
2388#undef CPUID_GST_AMD_FEATURE_WRN
2389#undef CPUID_GST_AMD_FEATURE_EMU
2390#undef CPUID_GST_AMD_FEATURE_IGN
2391
2392 return VINF_SUCCESS;
2393}
2394
2395
2396/**
2397 * Pass 0 live exec callback.
2398 *
2399 * @returns VINF_SSM_DONT_CALL_AGAIN.
2400 * @param pVM Pointer to the VM.
2401 * @param pSSM The saved state handle.
2402 * @param uPass The pass (0).
2403 */
2404static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2405{
2406 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2407 cpumR3SaveCpuId(pVM, pSSM);
2408 return VINF_SSM_DONT_CALL_AGAIN;
2409}
2410
2411
2412/**
2413 * Execute state save operation.
2414 *
2415 * @returns VBox status code.
2416 * @param pVM Pointer to the VM.
2417 * @param pSSM SSM operation handle.
2418 */
2419static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2420{
2421 /*
2422 * Save.
2423 */
2424 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2425 {
2426 PVMCPU pVCpu = &pVM->aCpus[i];
2427 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2428 }
2429
2430 SSMR3PutU32(pSSM, pVM->cCpus);
2431 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2432 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2433 {
2434 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2435
2436 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2437 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2438 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2439 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2440 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2441 }
2442
2443 cpumR3SaveCpuId(pVM, pSSM);
2444 return VINF_SUCCESS;
2445}
2446
2447
2448/**
2449 * @copydoc FNSSMINTLOADPREP
2450 */
2451static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2452{
2453 NOREF(pSSM);
2454 pVM->cpum.s.fPendingRestore = true;
2455 return VINF_SUCCESS;
2456}
2457
2458
2459/**
2460 * @copydoc FNSSMINTLOADEXEC
2461 */
2462static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2463{
2464 /*
2465 * Validate version.
2466 */
2467 if ( uVersion != CPUM_SAVED_STATE_VERSION
2468 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2469 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2470 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2471 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2472 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2473 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2474 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2475 {
2476 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2477 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2478 }
2479
2480 if (uPass == SSM_PASS_FINAL)
2481 {
2482 /*
2483 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2484 * really old SSM file versions.)
2485 */
2486 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2487 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2488 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2489 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2490
2491 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2492 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2493 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2494 paCpumCtxFields = g_aCpumCtxFieldsV16;
2495 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2496 paCpumCtxFields = g_aCpumCtxFieldsMem;
2497
2498 /*
2499 * Restore.
2500 */
2501 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2502 {
2503 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2504 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2505 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2506 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2507 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2508 pVCpu->cpum.s.Hyper.rsp = uRSP;
2509 }
2510
2511 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2512 {
2513 uint32_t cCpus;
2514 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2515 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2516 VERR_SSM_UNEXPECTED_DATA);
2517 }
2518 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2519 || pVM->cCpus == 1,
2520 ("cCpus=%u\n", pVM->cCpus),
2521 VERR_SSM_UNEXPECTED_DATA);
2522
2523 uint32_t cbMsrs = 0;
2524 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2525 {
2526 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2527 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2528 VERR_SSM_UNEXPECTED_DATA);
2529 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2530 VERR_SSM_UNEXPECTED_DATA);
2531 }
2532
2533 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2534 {
2535 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2536 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2537 paCpumCtxFields, NULL);
2538 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2539 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2540 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2541 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2542 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2543 {
2544 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2545 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2546 }
2547
2548 /* REM and other may have cleared must-be-one fields in DR6 and
2549 DR7, fix these. */
2550 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2551 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
2552 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2553 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
2554 }
2555
2556 /* Older states does not have the internal selector register flags
2557 and valid selector value. Supply those. */
2558 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2559 {
2560 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2561 {
2562 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2563 bool const fValid = HMIsEnabled(pVM)
2564 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2565 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2566 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2567 if (fValid)
2568 {
2569 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2570 {
2571 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2572 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2573 }
2574
2575 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2576 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2577 }
2578 else
2579 {
2580 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2581 {
2582 paSelReg[iSelReg].fFlags = 0;
2583 paSelReg[iSelReg].ValidSel = 0;
2584 }
2585
2586 /* This might not be 104% correct, but I think it's close
2587 enough for all practical purposes... (REM always loaded
2588 LDTR registers.) */
2589 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2590 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2591 }
2592 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2593 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2594 }
2595 }
2596
2597 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2598 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2599 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2600 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2601 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2602
2603 /*
2604 * A quick sanity check.
2605 */
2606 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2607 {
2608 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2609 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2610 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2611 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2612 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2613 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2614 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2615 }
2616 }
2617
2618 pVM->cpum.s.fPendingRestore = false;
2619
2620 /*
2621 * Guest CPUIDs.
2622 */
2623 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2624 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2625
2626 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2627 * actually required. */
2628
2629 /*
2630 * Restore the CPUID leaves.
2631 *
2632 * Note that we support restoring less than the current amount of standard
2633 * leaves because we've been allowed more is newer version of VBox.
2634 */
2635 uint32_t cElements;
2636 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2637 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2638 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2639 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2640
2641 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2642 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2643 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2644 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2645
2646 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2647 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2648 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2649 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2650
2651 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2652
2653 /*
2654 * Check that the basic cpuid id information is unchanged.
2655 */
2656 /** @todo we should check the 64 bits capabilities too! */
2657 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2658 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2659 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2660 uint32_t au32CpuIdSaved[8];
2661 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2662 if (RT_SUCCESS(rc))
2663 {
2664 /* Ignore CPU stepping. */
2665 au32CpuId[4] &= 0xfffffff0;
2666 au32CpuIdSaved[4] &= 0xfffffff0;
2667
2668 /* Ignore APIC ID (AMD specs). */
2669 au32CpuId[5] &= ~0xff000000;
2670 au32CpuIdSaved[5] &= ~0xff000000;
2671
2672 /* Ignore the number of Logical CPUs (AMD specs). */
2673 au32CpuId[5] &= ~0x00ff0000;
2674 au32CpuIdSaved[5] &= ~0x00ff0000;
2675
2676 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2677 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2678 | X86_CPUID_FEATURE_ECX_VMX
2679 | X86_CPUID_FEATURE_ECX_SMX
2680 | X86_CPUID_FEATURE_ECX_EST
2681 | X86_CPUID_FEATURE_ECX_TM2
2682 | X86_CPUID_FEATURE_ECX_CNTXID
2683 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2684 | X86_CPUID_FEATURE_ECX_PDCM
2685 | X86_CPUID_FEATURE_ECX_DCA
2686 | X86_CPUID_FEATURE_ECX_X2APIC
2687 );
2688 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2689 | X86_CPUID_FEATURE_ECX_VMX
2690 | X86_CPUID_FEATURE_ECX_SMX
2691 | X86_CPUID_FEATURE_ECX_EST
2692 | X86_CPUID_FEATURE_ECX_TM2
2693 | X86_CPUID_FEATURE_ECX_CNTXID
2694 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2695 | X86_CPUID_FEATURE_ECX_PDCM
2696 | X86_CPUID_FEATURE_ECX_DCA
2697 | X86_CPUID_FEATURE_ECX_X2APIC
2698 );
2699
2700 /* Make sure we don't forget to update the masks when enabling
2701 * features in the future.
2702 */
2703 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2704 ( X86_CPUID_FEATURE_ECX_DTES64
2705 | X86_CPUID_FEATURE_ECX_VMX
2706 | X86_CPUID_FEATURE_ECX_SMX
2707 | X86_CPUID_FEATURE_ECX_EST
2708 | X86_CPUID_FEATURE_ECX_TM2
2709 | X86_CPUID_FEATURE_ECX_CNTXID
2710 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2711 | X86_CPUID_FEATURE_ECX_PDCM
2712 | X86_CPUID_FEATURE_ECX_DCA
2713 | X86_CPUID_FEATURE_ECX_X2APIC
2714 )));
2715 /* do the compare */
2716 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2717 {
2718 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2719 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2720 "Saved=%.*Rhxs\n"
2721 "Real =%.*Rhxs\n",
2722 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2723 sizeof(au32CpuId), au32CpuId));
2724 else
2725 {
2726 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2727 "Saved=%.*Rhxs\n"
2728 "Real =%.*Rhxs\n",
2729 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2730 sizeof(au32CpuId), au32CpuId));
2731 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2732 }
2733 }
2734 }
2735
2736 return rc;
2737}
2738
2739
2740/**
2741 * @copydoc FNSSMINTLOADPREP
2742 */
2743static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2744{
2745 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2746 return VINF_SUCCESS;
2747
2748 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2749 if (pVM->cpum.s.fPendingRestore)
2750 {
2751 LogRel(("CPUM: Missing state!\n"));
2752 return VERR_INTERNAL_ERROR_2;
2753 }
2754
2755 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2756 {
2757 /* Notify PGM of the NXE states in case they've changed. */
2758 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2759
2760 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
2761 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
2762 }
2763 return VINF_SUCCESS;
2764}
2765
2766
2767/**
2768 * Checks if the CPUM state restore is still pending.
2769 *
2770 * @returns true / false.
2771 * @param pVM Pointer to the VM.
2772 */
2773VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2774{
2775 return pVM->cpum.s.fPendingRestore;
2776}
2777
2778
2779/**
2780 * Formats the EFLAGS value into mnemonics.
2781 *
2782 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2783 * @param efl The EFLAGS value.
2784 */
2785static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2786{
2787 /*
2788 * Format the flags.
2789 */
2790 static const struct
2791 {
2792 const char *pszSet; const char *pszClear; uint32_t fFlag;
2793 } s_aFlags[] =
2794 {
2795 { "vip",NULL, X86_EFL_VIP },
2796 { "vif",NULL, X86_EFL_VIF },
2797 { "ac", NULL, X86_EFL_AC },
2798 { "vm", NULL, X86_EFL_VM },
2799 { "rf", NULL, X86_EFL_RF },
2800 { "nt", NULL, X86_EFL_NT },
2801 { "ov", "nv", X86_EFL_OF },
2802 { "dn", "up", X86_EFL_DF },
2803 { "ei", "di", X86_EFL_IF },
2804 { "tf", NULL, X86_EFL_TF },
2805 { "nt", "pl", X86_EFL_SF },
2806 { "nz", "zr", X86_EFL_ZF },
2807 { "ac", "na", X86_EFL_AF },
2808 { "po", "pe", X86_EFL_PF },
2809 { "cy", "nc", X86_EFL_CF },
2810 };
2811 char *psz = pszEFlags;
2812 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2813 {
2814 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2815 if (pszAdd)
2816 {
2817 strcpy(psz, pszAdd);
2818 psz += strlen(pszAdd);
2819 *psz++ = ' ';
2820 }
2821 }
2822 psz[-1] = '\0';
2823}
2824
2825
2826/**
2827 * Formats a full register dump.
2828 *
2829 * @param pVM Pointer to the VM.
2830 * @param pCtx The context to format.
2831 * @param pCtxCore The context core to format.
2832 * @param pHlp Output functions.
2833 * @param enmType The dump type.
2834 * @param pszPrefix Register name prefix.
2835 */
2836static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2837 const char *pszPrefix)
2838{
2839 NOREF(pVM);
2840
2841 /*
2842 * Format the EFLAGS.
2843 */
2844 uint32_t efl = pCtxCore->eflags.u32;
2845 char szEFlags[80];
2846 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2847
2848 /*
2849 * Format the registers.
2850 */
2851 switch (enmType)
2852 {
2853 case CPUMDUMPTYPE_TERSE:
2854 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2855 pHlp->pfnPrintf(pHlp,
2856 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2857 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2858 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2859 "%sr14=%016RX64 %sr15=%016RX64\n"
2860 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2861 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2862 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2863 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2864 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2865 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2866 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2867 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2868 else
2869 pHlp->pfnPrintf(pHlp,
2870 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2871 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2872 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2873 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2874 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2875 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2876 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2877 break;
2878
2879 case CPUMDUMPTYPE_DEFAULT:
2880 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2881 pHlp->pfnPrintf(pHlp,
2882 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2883 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2884 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2885 "%sr14=%016RX64 %sr15=%016RX64\n"
2886 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2887 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2888 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2889 ,
2890 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2891 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2892 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2893 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2894 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2895 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2896 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2897 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2898 else
2899 pHlp->pfnPrintf(pHlp,
2900 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2901 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2902 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2903 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2904 ,
2905 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2906 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2907 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2908 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2909 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2910 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2911 break;
2912
2913 case CPUMDUMPTYPE_VERBOSE:
2914 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2915 pHlp->pfnPrintf(pHlp,
2916 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2917 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2918 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2919 "%sr14=%016RX64 %sr15=%016RX64\n"
2920 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2921 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2922 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2923 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2924 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2925 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2926 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2927 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2928 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2929 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2930 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2931 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2932 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2933 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2934 ,
2935 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2936 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2937 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2938 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2939 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2940 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2941 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2942 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2943 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2944 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2945 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2946 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2947 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2948 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2949 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2950 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2951 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2952 else
2953 pHlp->pfnPrintf(pHlp,
2954 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2955 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2956 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2957 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2958 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2959 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2960 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2961 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2962 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2963 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2964 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2965 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2966 ,
2967 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2968 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2969 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2970 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2971 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2972 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2973 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2974 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2975 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2976 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2977 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2978 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2979
2980 pHlp->pfnPrintf(pHlp,
2981 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2982 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2983 ,
2984 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
2985 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
2986 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
2987 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
2988 );
2989 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
2990 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
2991 {
2992 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
2993 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
2994 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
2995 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
2996 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
2997 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
2998 /** @todo This isn't entirenly correct and needs more work! */
2999 pHlp->pfnPrintf(pHlp,
3000 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
3001 pszPrefix, iST, pszPrefix, iFPR,
3002 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
3003 uTag, chSign, iInteger, u64Fraction, uExponent);
3004 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
3005 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3006 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
3007 else
3008 pHlp->pfnPrintf(pHlp, "\n");
3009 }
3010 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
3011 pHlp->pfnPrintf(pHlp,
3012 iXMM & 1
3013 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3014 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3015 pszPrefix, iXMM, iXMM < 10 ? " " : "",
3016 pCtx->fpu.aXMM[iXMM].au32[3],
3017 pCtx->fpu.aXMM[iXMM].au32[2],
3018 pCtx->fpu.aXMM[iXMM].au32[1],
3019 pCtx->fpu.aXMM[iXMM].au32[0]);
3020 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
3021 if (pCtx->fpu.au32RsrvdRest[i])
3022 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
3023 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
3024
3025 pHlp->pfnPrintf(pHlp,
3026 "%sEFER =%016RX64\n"
3027 "%sPAT =%016RX64\n"
3028 "%sSTAR =%016RX64\n"
3029 "%sCSTAR =%016RX64\n"
3030 "%sLSTAR =%016RX64\n"
3031 "%sSFMASK =%016RX64\n"
3032 "%sKERNELGSBASE =%016RX64\n",
3033 pszPrefix, pCtx->msrEFER,
3034 pszPrefix, pCtx->msrPAT,
3035 pszPrefix, pCtx->msrSTAR,
3036 pszPrefix, pCtx->msrCSTAR,
3037 pszPrefix, pCtx->msrLSTAR,
3038 pszPrefix, pCtx->msrSFMASK,
3039 pszPrefix, pCtx->msrKERNELGSBASE);
3040 break;
3041 }
3042}
3043
3044
3045/**
3046 * Display all cpu states and any other cpum info.
3047 *
3048 * @param pVM Pointer to the VM.
3049 * @param pHlp The info helper functions.
3050 * @param pszArgs Arguments, ignored.
3051 */
3052static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3053{
3054 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3055 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3056 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3057 cpumR3InfoHost(pVM, pHlp, pszArgs);
3058}
3059
3060
3061/**
3062 * Parses the info argument.
3063 *
3064 * The argument starts with 'verbose', 'terse' or 'default' and then
3065 * continues with the comment string.
3066 *
3067 * @param pszArgs The pointer to the argument string.
3068 * @param penmType Where to store the dump type request.
3069 * @param ppszComment Where to store the pointer to the comment string.
3070 */
3071static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3072{
3073 if (!pszArgs)
3074 {
3075 *penmType = CPUMDUMPTYPE_DEFAULT;
3076 *ppszComment = "";
3077 }
3078 else
3079 {
3080 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3081 {
3082 pszArgs += 7;
3083 *penmType = CPUMDUMPTYPE_VERBOSE;
3084 }
3085 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3086 {
3087 pszArgs += 5;
3088 *penmType = CPUMDUMPTYPE_TERSE;
3089 }
3090 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3091 {
3092 pszArgs += 7;
3093 *penmType = CPUMDUMPTYPE_DEFAULT;
3094 }
3095 else
3096 *penmType = CPUMDUMPTYPE_DEFAULT;
3097 *ppszComment = RTStrStripL(pszArgs);
3098 }
3099}
3100
3101
3102/**
3103 * Display the guest cpu state.
3104 *
3105 * @param pVM Pointer to the VM.
3106 * @param pHlp The info helper functions.
3107 * @param pszArgs Arguments, ignored.
3108 */
3109static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3110{
3111 CPUMDUMPTYPE enmType;
3112 const char *pszComment;
3113 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3114
3115 /* @todo SMP support! */
3116 PVMCPU pVCpu = VMMGetCpu(pVM);
3117 if (!pVCpu)
3118 pVCpu = &pVM->aCpus[0];
3119
3120 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3121
3122 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3123 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3124}
3125
3126
3127/**
3128 * Display the current guest instruction
3129 *
3130 * @param pVM Pointer to the VM.
3131 * @param pHlp The info helper functions.
3132 * @param pszArgs Arguments, ignored.
3133 */
3134static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3135{
3136 NOREF(pszArgs);
3137
3138 /** @todo SMP support! */
3139 PVMCPU pVCpu = VMMGetCpu(pVM);
3140 if (!pVCpu)
3141 pVCpu = &pVM->aCpus[0];
3142
3143 char szInstruction[256];
3144 szInstruction[0] = '\0';
3145 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3146 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3147}
3148
3149
3150/**
3151 * Display the hypervisor cpu state.
3152 *
3153 * @param pVM Pointer to the VM.
3154 * @param pHlp The info helper functions.
3155 * @param pszArgs Arguments, ignored.
3156 */
3157static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3158{
3159 CPUMDUMPTYPE enmType;
3160 const char *pszComment;
3161 /* @todo SMP */
3162 PVMCPU pVCpu = &pVM->aCpus[0];
3163
3164 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3165 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3166 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3167 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3168}
3169
3170
3171/**
3172 * Display the host cpu state.
3173 *
3174 * @param pVM Pointer to the VM.
3175 * @param pHlp The info helper functions.
3176 * @param pszArgs Arguments, ignored.
3177 */
3178static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3179{
3180 CPUMDUMPTYPE enmType;
3181 const char *pszComment;
3182 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3183 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3184
3185 /*
3186 * Format the EFLAGS.
3187 */
3188 /* @todo SMP */
3189 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3190#if HC_ARCH_BITS == 32
3191 uint32_t efl = pCtx->eflags.u32;
3192#else
3193 uint64_t efl = pCtx->rflags;
3194#endif
3195 char szEFlags[80];
3196 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3197
3198 /*
3199 * Format the registers.
3200 */
3201#if HC_ARCH_BITS == 32
3202# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3203 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3204# endif
3205 {
3206 pHlp->pfnPrintf(pHlp,
3207 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3208 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3209 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3210 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3211 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3212 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3213 ,
3214 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3215 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3216 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3217 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3218 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3219 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3220 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3221 }
3222# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3223 else
3224# endif
3225#endif
3226#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3227 {
3228 pHlp->pfnPrintf(pHlp,
3229 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3230 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3231 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3232 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3233 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3234 "r14=%016RX64 r15=%016RX64\n"
3235 "iopl=%d %31s\n"
3236 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3237 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3238 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3239 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3240 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3241 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3242 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3243 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3244 ,
3245 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3246 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3247 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3248 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3249 pCtx->r11, pCtx->r12, pCtx->r13,
3250 pCtx->r14, pCtx->r15,
3251 X86_EFL_GET_IOPL(efl), szEFlags,
3252 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3253 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3254 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3255 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3256 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3257 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3258 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3259 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3260 }
3261#endif
3262}
3263
3264
3265/**
3266 * Get L1 cache / TLS associativity.
3267 */
3268static const char *getCacheAss(unsigned u, char *pszBuf)
3269{
3270 if (u == 0)
3271 return "res0 ";
3272 if (u == 1)
3273 return "direct";
3274 if (u == 255)
3275 return "fully";
3276 if (u >= 256)
3277 return "???";
3278
3279 RTStrPrintf(pszBuf, 16, "%d way", u);
3280 return pszBuf;
3281}
3282
3283
3284/**
3285 * Get L2 cache associativity.
3286 */
3287const char *getL2CacheAss(unsigned u)
3288{
3289 switch (u)
3290 {
3291 case 0: return "off ";
3292 case 1: return "direct";
3293 case 2: return "2 way ";
3294 case 3: return "res3 ";
3295 case 4: return "4 way ";
3296 case 5: return "res5 ";
3297 case 6: return "8 way ";
3298 case 7: return "res7 ";
3299 case 8: return "16 way";
3300 case 9: return "res9 ";
3301 case 10: return "res10 ";
3302 case 11: return "res11 ";
3303 case 12: return "res12 ";
3304 case 13: return "res13 ";
3305 case 14: return "res14 ";
3306 case 15: return "fully ";
3307 default: return "????";
3308 }
3309}
3310
3311
3312/**
3313 * Display the guest CpuId leaves.
3314 *
3315 * @param pVM Pointer to the VM.
3316 * @param pHlp The info helper functions.
3317 * @param pszArgs "terse", "default" or "verbose".
3318 */
3319static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3320{
3321 /*
3322 * Parse the argument.
3323 */
3324 unsigned iVerbosity = 1;
3325 if (pszArgs)
3326 {
3327 pszArgs = RTStrStripL(pszArgs);
3328 if (!strcmp(pszArgs, "terse"))
3329 iVerbosity--;
3330 else if (!strcmp(pszArgs, "verbose"))
3331 iVerbosity++;
3332 }
3333
3334 /*
3335 * Start cracking.
3336 */
3337 CPUMCPUID Host;
3338 CPUMCPUID Guest;
3339 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3340
3341 uint32_t cStdHstMax;
3342 uint32_t dummy;
3343 ASMCpuId_Idx_ECX(0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
3344
3345 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd), cStdHstMax);
3346
3347 pHlp->pfnPrintf(pHlp,
3348 " RAW Standard CPUIDs\n"
3349 " Function eax ebx ecx edx\n");
3350 for (unsigned i = 0; i <= cStdLstMax ; i++)
3351 {
3352 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3353 {
3354 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3355 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3356
3357 pHlp->pfnPrintf(pHlp,
3358 "Gst: %08x %08x %08x %08x %08x%s\n"
3359 "Hst: %08x %08x %08x %08x\n",
3360 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3361 i <= cStdMax ? "" : "*",
3362 Host.eax, Host.ebx, Host.ecx, Host.edx);
3363 }
3364 else
3365 {
3366 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3367
3368 pHlp->pfnPrintf(pHlp,
3369 "Hst: %08x %08x %08x %08x %08x\n",
3370 i, Host.eax, Host.ebx, Host.ecx, Host.edx);
3371 }
3372 }
3373
3374 /*
3375 * If verbose, decode it.
3376 */
3377 if (iVerbosity)
3378 {
3379 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3380 pHlp->pfnPrintf(pHlp,
3381 "Name: %.04s%.04s%.04s\n"
3382 "Supports: 0-%x\n",
3383 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3384 }
3385
3386 /*
3387 * Get Features.
3388 */
3389 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3390 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3391 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3392 if (cStdMax >= 1 && iVerbosity)
3393 {
3394 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3395
3396 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3397 uint32_t uEAX = Guest.eax;
3398
3399 pHlp->pfnPrintf(pHlp,
3400 "Family: %d \tExtended: %d \tEffective: %d\n"
3401 "Model: %d \tExtended: %d \tEffective: %d\n"
3402 "Stepping: %d\n"
3403 "Type: %d (%s)\n"
3404 "APIC ID: %#04x\n"
3405 "Logical CPUs: %d\n"
3406 "CLFLUSH Size: %d\n"
3407 "Brand ID: %#04x\n",
3408 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3409 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3410 ASMGetCpuStepping(uEAX),
3411 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3412 (Guest.ebx >> 24) & 0xff,
3413 (Guest.ebx >> 16) & 0xff,
3414 (Guest.ebx >> 8) & 0xff,
3415 (Guest.ebx >> 0) & 0xff);
3416 if (iVerbosity == 1)
3417 {
3418 uint32_t uEDX = Guest.edx;
3419 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3420 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3421 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3422 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3423 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3424 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3425 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3426 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3427 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3428 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3429 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3430 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3431 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3432 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3433 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3434 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3435 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3436 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3437 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3438 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3439 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3440 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3441 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3442 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3443 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3444 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3445 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3446 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3447 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3448 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3449 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3450 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3451 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3452 pHlp->pfnPrintf(pHlp, "\n");
3453
3454 uint32_t uECX = Guest.ecx;
3455 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3456 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3457 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3458 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3459 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3460 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3461 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3462 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3463 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3464 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3465 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3466 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3467 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3468 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3469 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3470 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3471 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3472 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3473 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3474 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3475 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3476 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3477 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3478 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3479 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3480 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3481 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3482 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3483 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3484 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3485 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3486 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3487 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3488 pHlp->pfnPrintf(pHlp, "\n");
3489 }
3490 else
3491 {
3492 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3493
3494 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3495 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3496 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3497 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3498
3499 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3500 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3501 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3502 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3503 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3504 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3505 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3506 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3507 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3508 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3509 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3510 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3511 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3512 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3513 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3514 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3515 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3516 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3517 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3518 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3519 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3520 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3521 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3522 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3523 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3524 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3525 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3526 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3527 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3528 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3529 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3530 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3531 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3532
3533 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3534 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3535 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3536 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3537 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3538 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3539 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3540 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3541 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3542 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3543 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3544 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3545 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3546 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3547 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3548 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3549 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3550 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3551 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3552 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3553 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3554 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3555 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3556 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3557 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3558 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3559 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3560 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3561 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3562 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3563 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3564 }
3565 }
3566 if (cStdMax >= 2 && iVerbosity)
3567 {
3568 /** @todo */
3569 }
3570
3571 /*
3572 * Extended.
3573 * Implemented after AMD specs.
3574 */
3575 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3576
3577 pHlp->pfnPrintf(pHlp,
3578 "\n"
3579 " RAW Extended CPUIDs\n"
3580 " Function eax ebx ecx edx\n");
3581 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3582 {
3583 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3584 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3585
3586 pHlp->pfnPrintf(pHlp,
3587 "Gst: %08x %08x %08x %08x %08x%s\n"
3588 "Hst: %08x %08x %08x %08x\n",
3589 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3590 i <= cExtMax ? "" : "*",
3591 Host.eax, Host.ebx, Host.ecx, Host.edx);
3592 }
3593
3594 /*
3595 * Understandable output
3596 */
3597 if (iVerbosity)
3598 {
3599 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3600 pHlp->pfnPrintf(pHlp,
3601 "Ext Name: %.4s%.4s%.4s\n"
3602 "Ext Supports: 0x80000000-%#010x\n",
3603 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3604 }
3605
3606 if (iVerbosity && cExtMax >= 1)
3607 {
3608 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3609 uint32_t uEAX = Guest.eax;
3610 pHlp->pfnPrintf(pHlp,
3611 "Family: %d \tExtended: %d \tEffective: %d\n"
3612 "Model: %d \tExtended: %d \tEffective: %d\n"
3613 "Stepping: %d\n"
3614 "Brand ID: %#05x\n",
3615 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3616 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3617 ASMGetCpuStepping(uEAX),
3618 Guest.ebx & 0xfff);
3619
3620 if (iVerbosity == 1)
3621 {
3622 uint32_t uEDX = Guest.edx;
3623 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3624 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3625 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3626 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3627 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3628 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3629 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3630 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3631 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3632 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3633 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3634 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3635 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3636 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3637 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3638 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3639 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3640 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3641 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3642 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3643 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3644 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3645 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3646 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3647 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3648 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3649 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3650 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3651 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3652 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3653 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3654 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3655 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3656 pHlp->pfnPrintf(pHlp, "\n");
3657
3658 uint32_t uECX = Guest.ecx;
3659 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3660 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3661 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3662 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3663 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3664 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3665 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3666 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3667 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3668 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3669 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3670 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3671 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3672 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3673 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3674 for (unsigned iBit = 5; iBit < 32; iBit++)
3675 if (uECX & RT_BIT(iBit))
3676 pHlp->pfnPrintf(pHlp, " %d", iBit);
3677 pHlp->pfnPrintf(pHlp, "\n");
3678 }
3679 else
3680 {
3681 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3682
3683 uint32_t uEdxGst = Guest.edx;
3684 uint32_t uEdxHst = Host.edx;
3685 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3686 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3687 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3688 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3689 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3690 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3691 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3692 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3693 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3694 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3695 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3696 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3697 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3698 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3699 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3700 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3701 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3702 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3703 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3704 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3705 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3706 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3707 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3708 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3709 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3710 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3711 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3712 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3713 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3714 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3715 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3716 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3717 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3718
3719 uint32_t uEcxGst = Guest.ecx;
3720 uint32_t uEcxHst = Host.ecx;
3721 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3722 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3723 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3724 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3725 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3726 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3727 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3728 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3729 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3730 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3731 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3732 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3733 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3734 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3735 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3736 }
3737 }
3738
3739 if (iVerbosity && cExtMax >= 2)
3740 {
3741 char szString[4*4*3+1] = {0};
3742 uint32_t *pu32 = (uint32_t *)szString;
3743 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3744 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3745 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3746 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3747 if (cExtMax >= 3)
3748 {
3749 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3750 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3751 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3752 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3753 }
3754 if (cExtMax >= 4)
3755 {
3756 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3757 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3758 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3759 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3760 }
3761 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3762 }
3763
3764 if (iVerbosity && cExtMax >= 5)
3765 {
3766 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3767 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3768 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3769 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3770 char sz1[32];
3771 char sz2[32];
3772
3773 pHlp->pfnPrintf(pHlp,
3774 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3775 "TLB 2/4M Data: %s %3d entries\n",
3776 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3777 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3778 pHlp->pfnPrintf(pHlp,
3779 "TLB 4K Instr/Uni: %s %3d entries\n"
3780 "TLB 4K Data: %s %3d entries\n",
3781 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3782 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3783 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3784 "L1 Instr Cache Lines Per Tag: %d\n"
3785 "L1 Instr Cache Associativity: %s\n"
3786 "L1 Instr Cache Size: %d KB\n",
3787 (uEDX >> 0) & 0xff,
3788 (uEDX >> 8) & 0xff,
3789 getCacheAss((uEDX >> 16) & 0xff, sz1),
3790 (uEDX >> 24) & 0xff);
3791 pHlp->pfnPrintf(pHlp,
3792 "L1 Data Cache Line Size: %d bytes\n"
3793 "L1 Data Cache Lines Per Tag: %d\n"
3794 "L1 Data Cache Associativity: %s\n"
3795 "L1 Data Cache Size: %d KB\n",
3796 (uECX >> 0) & 0xff,
3797 (uECX >> 8) & 0xff,
3798 getCacheAss((uECX >> 16) & 0xff, sz1),
3799 (uECX >> 24) & 0xff);
3800 }
3801
3802 if (iVerbosity && cExtMax >= 6)
3803 {
3804 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3805 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3806 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3807
3808 pHlp->pfnPrintf(pHlp,
3809 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3810 "L2 TLB 2/4M Data: %s %4d entries\n",
3811 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3812 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3813 pHlp->pfnPrintf(pHlp,
3814 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3815 "L2 TLB 4K Data: %s %4d entries\n",
3816 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3817 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3818 pHlp->pfnPrintf(pHlp,
3819 "L2 Cache Line Size: %d bytes\n"
3820 "L2 Cache Lines Per Tag: %d\n"
3821 "L2 Cache Associativity: %s\n"
3822 "L2 Cache Size: %d KB\n",
3823 (uEDX >> 0) & 0xff,
3824 (uEDX >> 8) & 0xf,
3825 getL2CacheAss((uEDX >> 12) & 0xf),
3826 (uEDX >> 16) & 0xffff);
3827 }
3828
3829 if (iVerbosity && cExtMax >= 7)
3830 {
3831 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3832
3833 pHlp->pfnPrintf(pHlp, "APM Features: ");
3834 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3835 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3836 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3837 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3838 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3839 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3840 for (unsigned iBit = 6; iBit < 32; iBit++)
3841 if (uEDX & RT_BIT(iBit))
3842 pHlp->pfnPrintf(pHlp, " %d", iBit);
3843 pHlp->pfnPrintf(pHlp, "\n");
3844 }
3845
3846 if (iVerbosity && cExtMax >= 8)
3847 {
3848 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3849 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3850
3851 pHlp->pfnPrintf(pHlp,
3852 "Physical Address Width: %d bits\n"
3853 "Virtual Address Width: %d bits\n"
3854 "Guest Physical Address Width: %d bits\n",
3855 (uEAX >> 0) & 0xff,
3856 (uEAX >> 8) & 0xff,
3857 (uEAX >> 16) & 0xff);
3858 pHlp->pfnPrintf(pHlp,
3859 "Physical Core Count: %d\n",
3860 (uECX >> 0) & 0xff);
3861 }
3862
3863
3864 /*
3865 * Centaur.
3866 */
3867 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3868
3869 pHlp->pfnPrintf(pHlp,
3870 "\n"
3871 " RAW Centaur CPUIDs\n"
3872 " Function eax ebx ecx edx\n");
3873 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3874 {
3875 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3876 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3877
3878 pHlp->pfnPrintf(pHlp,
3879 "Gst: %08x %08x %08x %08x %08x%s\n"
3880 "Hst: %08x %08x %08x %08x\n",
3881 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3882 i <= cCentaurMax ? "" : "*",
3883 Host.eax, Host.ebx, Host.ecx, Host.edx);
3884 }
3885
3886 /*
3887 * Understandable output
3888 */
3889 if (iVerbosity)
3890 {
3891 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3892 pHlp->pfnPrintf(pHlp,
3893 "Centaur Supports: 0xc0000000-%#010x\n",
3894 Guest.eax);
3895 }
3896
3897 if (iVerbosity && cCentaurMax >= 1)
3898 {
3899 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3900 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3901 uint32_t uEdxHst = Host.edx;
3902
3903 if (iVerbosity == 1)
3904 {
3905 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3906 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3907 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3908 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3909 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3910 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3911 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3912 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3913 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3914 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3915 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3916 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3917 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3918 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3919 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3920 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3921 for (unsigned iBit = 14; iBit < 32; iBit++)
3922 if (uEdxGst & RT_BIT(iBit))
3923 pHlp->pfnPrintf(pHlp, " %d", iBit);
3924 pHlp->pfnPrintf(pHlp, "\n");
3925 }
3926 else
3927 {
3928 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3929 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3930 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3931 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3932 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3933 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3934 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3935 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3936 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3937 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3938 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3939 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3940 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3941 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3942 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3943 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3944 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3945 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3946 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3947 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3948 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3949 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3950 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3951 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3952 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3953 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3954 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3955 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3956 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3957 for (unsigned iBit = 27; iBit < 32; iBit++)
3958 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
3959 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
3960 pHlp->pfnPrintf(pHlp, "\n");
3961 }
3962 }
3963}
3964
3965
3966/**
3967 * Structure used when disassembling and instructions in DBGF.
3968 * This is used so the reader function can get the stuff it needs.
3969 */
3970typedef struct CPUMDISASSTATE
3971{
3972 /** Pointer to the CPU structure. */
3973 PDISCPUSTATE pCpu;
3974 /** Pointer to the VM. */
3975 PVM pVM;
3976 /** Pointer to the VMCPU. */
3977 PVMCPU pVCpu;
3978 /** Pointer to the first byte in the segment. */
3979 RTGCUINTPTR GCPtrSegBase;
3980 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
3981 RTGCUINTPTR GCPtrSegEnd;
3982 /** The size of the segment minus 1. */
3983 RTGCUINTPTR cbSegLimit;
3984 /** Pointer to the current page - R3 Ptr. */
3985 void const *pvPageR3;
3986 /** Pointer to the current page - GC Ptr. */
3987 RTGCPTR pvPageGC;
3988 /** The lock information that PGMPhysReleasePageMappingLock needs. */
3989 PGMPAGEMAPLOCK PageMapLock;
3990 /** Whether the PageMapLock is valid or not. */
3991 bool fLocked;
3992 /** 64 bits mode or not. */
3993 bool f64Bits;
3994} CPUMDISASSTATE, *PCPUMDISASSTATE;
3995
3996
3997/**
3998 * @callback_method_impl{FNDISREADBYTES}
3999 */
4000static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4001{
4002 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4003 for (;;)
4004 {
4005 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4006
4007 /*
4008 * Need to update the page translation?
4009 */
4010 if ( !pState->pvPageR3
4011 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4012 {
4013 int rc = VINF_SUCCESS;
4014
4015 /* translate the address */
4016 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4017 if ( !HMIsEnabled(pState->pVM)
4018 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4019 {
4020 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4021 if (!pState->pvPageR3)
4022 rc = VERR_INVALID_POINTER;
4023 }
4024 else
4025 {
4026 /* Release mapping lock previously acquired. */
4027 if (pState->fLocked)
4028 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4029 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4030 pState->fLocked = RT_SUCCESS_NP(rc);
4031 }
4032 if (RT_FAILURE(rc))
4033 {
4034 pState->pvPageR3 = NULL;
4035 return rc;
4036 }
4037 }
4038
4039 /*
4040 * Check the segment limit.
4041 */
4042 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4043 return VERR_OUT_OF_SELECTOR_BOUNDS;
4044
4045 /*
4046 * Calc how much we can read.
4047 */
4048 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4049 if (!pState->f64Bits)
4050 {
4051 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4052 if (cb > cbSeg && cbSeg)
4053 cb = cbSeg;
4054 }
4055 if (cb > cbMaxRead)
4056 cb = cbMaxRead;
4057
4058 /*
4059 * Read and advance or exit.
4060 */
4061 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4062 offInstr += (uint8_t)cb;
4063 if (cb >= cbMinRead)
4064 {
4065 pDis->cbCachedInstr = offInstr;
4066 return VINF_SUCCESS;
4067 }
4068 cbMinRead -= (uint8_t)cb;
4069 cbMaxRead -= (uint8_t)cb;
4070 }
4071}
4072
4073
4074/**
4075 * Disassemble an instruction and return the information in the provided structure.
4076 *
4077 * @returns VBox status code.
4078 * @param pVM Pointer to the VM.
4079 * @param pVCpu Pointer to the VMCPU.
4080 * @param pCtx Pointer to the guest CPU context.
4081 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4082 * @param pCpu Disassembly state.
4083 * @param pszPrefix String prefix for logging (debug only).
4084 *
4085 */
4086VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4087{
4088 CPUMDISASSTATE State;
4089 int rc;
4090
4091 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4092 State.pCpu = pCpu;
4093 State.pvPageGC = 0;
4094 State.pvPageR3 = NULL;
4095 State.pVM = pVM;
4096 State.pVCpu = pVCpu;
4097 State.fLocked = false;
4098 State.f64Bits = false;
4099
4100 /*
4101 * Get selector information.
4102 */
4103 DISCPUMODE enmDisCpuMode;
4104 if ( (pCtx->cr0 & X86_CR0_PE)
4105 && pCtx->eflags.Bits.u1VM == 0)
4106 {
4107 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4108 {
4109# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4110 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4111# endif
4112 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4113 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4114 }
4115 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4116 State.GCPtrSegBase = pCtx->cs.u64Base;
4117 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4118 State.cbSegLimit = pCtx->cs.u32Limit;
4119 enmDisCpuMode = (State.f64Bits)
4120 ? DISCPUMODE_64BIT
4121 : pCtx->cs.Attr.n.u1DefBig
4122 ? DISCPUMODE_32BIT
4123 : DISCPUMODE_16BIT;
4124 }
4125 else
4126 {
4127 /* real or V86 mode */
4128 enmDisCpuMode = DISCPUMODE_16BIT;
4129 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4130 State.GCPtrSegEnd = 0xFFFFFFFF;
4131 State.cbSegLimit = 0xFFFFFFFF;
4132 }
4133
4134 /*
4135 * Disassemble the instruction.
4136 */
4137 uint32_t cbInstr;
4138#ifndef LOG_ENABLED
4139 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4140 if (RT_SUCCESS(rc))
4141 {
4142#else
4143 char szOutput[160];
4144 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4145 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4146 if (RT_SUCCESS(rc))
4147 {
4148 /* log it */
4149 if (pszPrefix)
4150 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4151 else
4152 Log(("%s", szOutput));
4153#endif
4154 rc = VINF_SUCCESS;
4155 }
4156 else
4157 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4158
4159 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4160 if (State.fLocked)
4161 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4162
4163 return rc;
4164}
4165
4166
4167
4168/**
4169 * API for controlling a few of the CPU features found in CR4.
4170 *
4171 * Currently only X86_CR4_TSD is accepted as input.
4172 *
4173 * @returns VBox status code.
4174 *
4175 * @param pVM Pointer to the VM.
4176 * @param fOr The CR4 OR mask.
4177 * @param fAnd The CR4 AND mask.
4178 */
4179VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4180{
4181 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4182 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4183
4184 pVM->cpum.s.CR4.OrMask &= fAnd;
4185 pVM->cpum.s.CR4.OrMask |= fOr;
4186
4187 return VINF_SUCCESS;
4188}
4189
4190
4191/**
4192 * Gets a pointer to the array of standard CPUID leaves.
4193 *
4194 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4195 *
4196 * @returns Pointer to the standard CPUID leaves (read-only).
4197 * @param pVM Pointer to the VM.
4198 * @remark Intended for PATM.
4199 */
4200VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4201{
4202 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4203}
4204
4205
4206/**
4207 * Gets a pointer to the array of extended CPUID leaves.
4208 *
4209 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4210 *
4211 * @returns Pointer to the extended CPUID leaves (read-only).
4212 * @param pVM Pointer to the VM.
4213 * @remark Intended for PATM.
4214 */
4215VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4216{
4217 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4218}
4219
4220
4221/**
4222 * Gets a pointer to the array of centaur CPUID leaves.
4223 *
4224 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4225 *
4226 * @returns Pointer to the centaur CPUID leaves (read-only).
4227 * @param pVM Pointer to the VM.
4228 * @remark Intended for PATM.
4229 */
4230VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4231{
4232 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4233}
4234
4235
4236/**
4237 * Gets a pointer to the default CPUID leaf.
4238 *
4239 * @returns Pointer to the default CPUID leaf (read-only).
4240 * @param pVM Pointer to the VM.
4241 * @remark Intended for PATM.
4242 */
4243VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4244{
4245 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4246}
4247
4248
4249/**
4250 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4251 *
4252 * Only REM should ever call this function!
4253 *
4254 * @returns The changed flags.
4255 * @param pVCpu Pointer to the VMCPU.
4256 * @param puCpl Where to return the current privilege level (CPL).
4257 */
4258VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4259{
4260 Assert(!pVCpu->cpum.s.fRawEntered);
4261 Assert(!pVCpu->cpum.s.fRemEntered);
4262
4263 /*
4264 * Get the CPL first.
4265 */
4266 *puCpl = CPUMGetGuestCPL(pVCpu);
4267
4268 /*
4269 * Get and reset the flags.
4270 */
4271 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4272 pVCpu->cpum.s.fChanged = 0;
4273
4274 /** @todo change the switcher to use the fChanged flags. */
4275 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4276 {
4277 fFlags |= CPUM_CHANGED_FPU_REM;
4278 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4279 }
4280
4281 pVCpu->cpum.s.fRemEntered = true;
4282 return fFlags;
4283}
4284
4285
4286/**
4287 * Leaves REM.
4288 *
4289 * @param pVCpu Pointer to the VMCPU.
4290 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4291 * registers.
4292 */
4293VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4294{
4295 Assert(!pVCpu->cpum.s.fRawEntered);
4296 Assert(pVCpu->cpum.s.fRemEntered);
4297
4298 pVCpu->cpum.s.fRemEntered = false;
4299}
4300
4301
4302/**
4303 * Called when the ring-3 init phase completes.
4304 *
4305 * @returns VBox status code.
4306 * @param pVM Pointer to the VM.
4307 */
4308VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4309{
4310 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4311 {
4312 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4313 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4314 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4315 }
4316 return VINF_SUCCESS;
4317}
4318
4319/**
4320 * Called when the ring-0 init phases comleted.
4321 *
4322 * @param pVM Pointer to the VM.
4323 */
4324VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4325{
4326 /*
4327 * Log the cpuid.
4328 */
4329 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4330 RTCPUSET OnlineSet;
4331 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4332 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4333 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4334 RTCPUID cCores = RTMpGetCoreCount();
4335 if (cCores)
4336 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
4337 LogRel(("************************* CPUID dump ************************\n"));
4338 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4339 LogRel(("\n"));
4340 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4341 RTLogRelSetBuffering(fOldBuffered);
4342 LogRel(("******************** End of CPUID dump **********************\n"));
4343}
Note: See TracBrowser for help on using the repository browser.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette