VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 49164

Last change on this file since 49164 was 49019, checked in by vboxsync, 11 years ago

VMM: FPU cleanup.
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  • Property svn:keywords set to Id Revision
File size: 213.2 KB
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1/* $Id: CPUM.cpp 49019 2013-10-10 08:45:11Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/assert.h>
58#include <iprt/asm-amd64-x86.h>
59#include <iprt/string.h>
60#include <iprt/mp.h>
61#include <iprt/cpuset.h>
62#include "internal/pgm.h"
63
64
65/*******************************************************************************
66* Defined Constants And Macros *
67*******************************************************************************/
68/** The current saved state version. */
69#define CPUM_SAVED_STATE_VERSION 14
70/** The current saved state version before using SSMR3PutStruct. */
71#define CPUM_SAVED_STATE_VERSION_MEM 13
72/** The saved state version before introducing the MSR size field. */
73#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
74/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
75 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
76#define CPUM_SAVED_STATE_VERSION_VER3_2 11
77/** The saved state version of 3.0 and 3.1 trunk before the teleportation
78 * changes. */
79#define CPUM_SAVED_STATE_VERSION_VER3_0 10
80/** The saved state version for the 2.1 trunk before the MSR changes. */
81#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
82/** The saved state version of 2.0, used for backwards compatibility. */
83#define CPUM_SAVED_STATE_VERSION_VER2_0 8
84/** The saved state version of 1.6, used for backwards compatibility. */
85#define CPUM_SAVED_STATE_VERSION_VER1_6 6
86
87
88/**
89 * This was used in the saved state up to the early life of version 14.
90 *
91 * It indicates that we may have some out-of-sync hidden segement registers.
92 * It is only relevant for raw-mode.
93 */
94#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
95
96
97/*******************************************************************************
98* Structures and Typedefs *
99*******************************************************************************/
100
101/**
102 * What kind of cpu info dump to perform.
103 */
104typedef enum CPUMDUMPTYPE
105{
106 CPUMDUMPTYPE_TERSE,
107 CPUMDUMPTYPE_DEFAULT,
108 CPUMDUMPTYPE_VERBOSE
109} CPUMDUMPTYPE;
110/** Pointer to a cpu info dump type. */
111typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
112
113
114/*******************************************************************************
115* Internal Functions *
116*******************************************************************************/
117static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX);
118static int cpumR3CpuIdInit(PVM pVM);
119static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
120static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
121static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
122static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
123static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
124static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
125static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
126static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
127static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
129static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
130
131
132/*******************************************************************************
133* Global Variables *
134*******************************************************************************/
135/** Saved state field descriptors for CPUMCTX. */
136static const SSMFIELD g_aCpumCtxFields[] =
137{
138 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
139 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
140 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
141 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
142 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
143 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
144 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
145 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
146 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
147 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
148 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
149 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
150 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
151 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
152 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
153 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
154 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
155 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
156 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
157 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
158 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
159 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
160 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
161 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
162 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
163 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
164 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
165 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
166 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
167 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
168 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
169 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
170 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
171 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
172 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
173 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
174 SSMFIELD_ENTRY( CPUMCTX, rdi),
175 SSMFIELD_ENTRY( CPUMCTX, rsi),
176 SSMFIELD_ENTRY( CPUMCTX, rbp),
177 SSMFIELD_ENTRY( CPUMCTX, rax),
178 SSMFIELD_ENTRY( CPUMCTX, rbx),
179 SSMFIELD_ENTRY( CPUMCTX, rdx),
180 SSMFIELD_ENTRY( CPUMCTX, rcx),
181 SSMFIELD_ENTRY( CPUMCTX, rsp),
182 SSMFIELD_ENTRY( CPUMCTX, rflags),
183 SSMFIELD_ENTRY( CPUMCTX, rip),
184 SSMFIELD_ENTRY( CPUMCTX, r8),
185 SSMFIELD_ENTRY( CPUMCTX, r9),
186 SSMFIELD_ENTRY( CPUMCTX, r10),
187 SSMFIELD_ENTRY( CPUMCTX, r11),
188 SSMFIELD_ENTRY( CPUMCTX, r12),
189 SSMFIELD_ENTRY( CPUMCTX, r13),
190 SSMFIELD_ENTRY( CPUMCTX, r14),
191 SSMFIELD_ENTRY( CPUMCTX, r15),
192 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
193 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
194 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
195 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
196 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
197 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
198 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, cr0),
229 SSMFIELD_ENTRY( CPUMCTX, cr2),
230 SSMFIELD_ENTRY( CPUMCTX, cr3),
231 SSMFIELD_ENTRY( CPUMCTX, cr4),
232 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
233 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
234 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
235 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
236 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
237 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
238 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
239 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
240 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
241 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
242 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
243 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
244 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
245 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
246 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
247 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
248 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
249 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
250 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
251 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
252 /* msrApicBase is not included here, it resides in the APIC device state. */
253 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
254 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
255 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
256 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
257 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
258 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
259 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
265 SSMFIELD_ENTRY_TERM()
266};
267
268/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
269 * registeres changed. */
270static const SSMFIELD g_aCpumCtxFieldsMem[] =
271{
272 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
273 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
274 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
275 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
276 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
277 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
278 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
279 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
280 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
281 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
282 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
283 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
284 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
285 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
286 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
287 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
288 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
289 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
290 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
291 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
292 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
293 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
294 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
295 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
296 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
297 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
298 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
299 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
300 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
301 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
302 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
303 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
304 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
305 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
306 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
307 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
308 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
309 SSMFIELD_ENTRY( CPUMCTX, rdi),
310 SSMFIELD_ENTRY( CPUMCTX, rsi),
311 SSMFIELD_ENTRY( CPUMCTX, rbp),
312 SSMFIELD_ENTRY( CPUMCTX, rax),
313 SSMFIELD_ENTRY( CPUMCTX, rbx),
314 SSMFIELD_ENTRY( CPUMCTX, rdx),
315 SSMFIELD_ENTRY( CPUMCTX, rcx),
316 SSMFIELD_ENTRY( CPUMCTX, rsp),
317 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
318 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
319 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
320 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
321 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
322 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
323 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
324 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
325 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
326 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
327 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
328 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
329 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
330 SSMFIELD_ENTRY( CPUMCTX, rflags),
331 SSMFIELD_ENTRY( CPUMCTX, rip),
332 SSMFIELD_ENTRY( CPUMCTX, r8),
333 SSMFIELD_ENTRY( CPUMCTX, r9),
334 SSMFIELD_ENTRY( CPUMCTX, r10),
335 SSMFIELD_ENTRY( CPUMCTX, r11),
336 SSMFIELD_ENTRY( CPUMCTX, r12),
337 SSMFIELD_ENTRY( CPUMCTX, r13),
338 SSMFIELD_ENTRY( CPUMCTX, r14),
339 SSMFIELD_ENTRY( CPUMCTX, r15),
340 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
350 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
351 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
352 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
353 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
354 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
355 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
356 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
357 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
358 SSMFIELD_ENTRY( CPUMCTX, cr0),
359 SSMFIELD_ENTRY( CPUMCTX, cr2),
360 SSMFIELD_ENTRY( CPUMCTX, cr3),
361 SSMFIELD_ENTRY( CPUMCTX, cr4),
362 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
363 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
364 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
365 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
366 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
367 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
368 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
369 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
370 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
371 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
372 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
373 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
374 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
375 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
376 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
377 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
378 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
379 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
380 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
381 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
382 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
383 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
384 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
385 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
386 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
387 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
388 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
389 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
390 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
391 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
392 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
393 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
394 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
395 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
396 SSMFIELD_ENTRY_TERM()
397};
398
399/** Saved state field descriptors for CPUMCTX_VER1_6. */
400static const SSMFIELD g_aCpumCtxFieldsV16[] =
401{
402 SSMFIELD_ENTRY( CPUMCTX, fpu.FCW),
403 SSMFIELD_ENTRY( CPUMCTX, fpu.FSW),
404 SSMFIELD_ENTRY( CPUMCTX, fpu.FTW),
405 SSMFIELD_ENTRY( CPUMCTX, fpu.FOP),
406 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUIP),
407 SSMFIELD_ENTRY( CPUMCTX, fpu.CS),
408 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd1),
409 SSMFIELD_ENTRY( CPUMCTX, fpu.FPUDP),
410 SSMFIELD_ENTRY( CPUMCTX, fpu.DS),
411 SSMFIELD_ENTRY( CPUMCTX, fpu.Rsrvd2),
412 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR),
413 SSMFIELD_ENTRY( CPUMCTX, fpu.MXCSR_MASK),
414 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[0]),
415 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[1]),
416 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[2]),
417 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[3]),
418 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[4]),
419 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[5]),
420 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[6]),
421 SSMFIELD_ENTRY( CPUMCTX, fpu.aRegs[7]),
422 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[0]),
423 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[1]),
424 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[2]),
425 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[3]),
426 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[4]),
427 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[5]),
428 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[6]),
429 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[7]),
430 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[8]),
431 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[9]),
432 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[10]),
433 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[11]),
434 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[12]),
435 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[13]),
436 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[14]),
437 SSMFIELD_ENTRY( CPUMCTX, fpu.aXMM[15]),
438 SSMFIELD_ENTRY_IGNORE( CPUMCTX, fpu.au32RsrvdRest),
439 SSMFIELD_ENTRY( CPUMCTX, rdi),
440 SSMFIELD_ENTRY( CPUMCTX, rsi),
441 SSMFIELD_ENTRY( CPUMCTX, rbp),
442 SSMFIELD_ENTRY( CPUMCTX, rax),
443 SSMFIELD_ENTRY( CPUMCTX, rbx),
444 SSMFIELD_ENTRY( CPUMCTX, rdx),
445 SSMFIELD_ENTRY( CPUMCTX, rcx),
446 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
447 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
448 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
450 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
451 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
452 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
453 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
454 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
455 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
456 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
457 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
458 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
459 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
460 SSMFIELD_ENTRY( CPUMCTX, rflags),
461 SSMFIELD_ENTRY( CPUMCTX, rip),
462 SSMFIELD_ENTRY( CPUMCTX, r8),
463 SSMFIELD_ENTRY( CPUMCTX, r9),
464 SSMFIELD_ENTRY( CPUMCTX, r10),
465 SSMFIELD_ENTRY( CPUMCTX, r11),
466 SSMFIELD_ENTRY( CPUMCTX, r12),
467 SSMFIELD_ENTRY( CPUMCTX, r13),
468 SSMFIELD_ENTRY( CPUMCTX, r14),
469 SSMFIELD_ENTRY( CPUMCTX, r15),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
485 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
486 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
487 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
488 SSMFIELD_ENTRY( CPUMCTX, cr0),
489 SSMFIELD_ENTRY( CPUMCTX, cr2),
490 SSMFIELD_ENTRY( CPUMCTX, cr3),
491 SSMFIELD_ENTRY( CPUMCTX, cr4),
492 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
493 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
494 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
495 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
496 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
497 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
498 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
499 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
500 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
501 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
502 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
503 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
504 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
505 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
506 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
507 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
509 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
510 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
511 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
512 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
513 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
514 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
515 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
516 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
517 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
519 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
520 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
521 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
522 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
523 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
524 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
528 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
531 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
532 SSMFIELD_ENTRY_TERM()
533};
534
535
536/**
537 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
538 *
539 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error
540 * pointers (last instruction pointer, last data pointer, last opcode)
541 * except when the ES bit (Exception Summary) in x87 FSW (FPU Status
542 * Word) is set. Thus if we don't clear these registers there is
543 * potential, local FPU leakage from a process using the FPU to
544 * another.
545 *
546 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
547 *
548 * @param pVM Pointer to the VM.
549 */
550static void cpumR3CheckLeakyFpu(PVM pVM)
551{
552 uint32_t u32CpuVersion;
553 uint32_t u32Dummy;
554 ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Dummy);
555 uint32_t const u32Family = u32CpuVersion >> 8;
556 if ( u32Family >= 6 /* K7 and higher */
557 && ASMIsAmdCpu())
558 {
559 uint32_t cExt = 0;
560 ASMCpuId(0x80000000, &cExt, &u32Dummy, &u32Dummy, &u32Dummy);
561 if (ASMIsValidExtRange(cExt))
562 {
563 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
564 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
565 {
566 for (VMCPUID i = 0; i < pVM->cCpus; i++)
567 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
568 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
569 }
570 }
571 }
572}
573
574
575/**
576 * Initializes the CPUM.
577 *
578 * @returns VBox status code.
579 * @param pVM Pointer to the VM.
580 */
581VMMR3DECL(int) CPUMR3Init(PVM pVM)
582{
583 LogFlow(("CPUMR3Init\n"));
584
585 /*
586 * Assert alignment and sizes.
587 */
588 AssertCompileMemberAlignment(VM, cpum.s, 32);
589 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
590 AssertCompileSizeAlignment(CPUMCTX, 64);
591 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
592 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
593 AssertCompileMemberAlignment(VM, cpum, 64);
594 AssertCompileMemberAlignment(VM, aCpus, 64);
595 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
596 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
597
598 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
599 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
600 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
601
602 /* Calculate the offset from CPUMCPU to CPUM. */
603 for (VMCPUID i = 0; i < pVM->cCpus; i++)
604 {
605 PVMCPU pVCpu = &pVM->aCpus[i];
606
607 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
608 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
609 }
610
611 /*
612 * Check that the CPU supports the minimum features we require.
613 */
614 if (!ASMHasCpuId())
615 {
616 Log(("The CPU doesn't support CPUID!\n"));
617 return VERR_UNSUPPORTED_CPU;
618 }
619 ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
620 ASMCpuId_ECX_EDX(0x80000001, &pVM->cpum.s.CPUFeaturesExt.ecx, &pVM->cpum.s.CPUFeaturesExt.edx);
621
622 /* Setup the CR4 AND and OR masks used in the switcher */
623 /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
624 if (!pVM->cpum.s.CPUFeatures.edx.u1FXSR)
625 {
626 Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
627 /* No FXSAVE implies no SSE */
628 pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
629 pVM->cpum.s.CR4.OrMask = 0;
630 }
631 else
632 {
633 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
634 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFSXR;
635 }
636
637 if (!pVM->cpum.s.CPUFeatures.edx.u1MMX)
638 {
639 Log(("The CPU doesn't support MMX!\n"));
640 return VERR_UNSUPPORTED_CPU;
641 }
642 if (!pVM->cpum.s.CPUFeatures.edx.u1TSC)
643 {
644 Log(("The CPU doesn't support TSC!\n"));
645 return VERR_UNSUPPORTED_CPU;
646 }
647 /* Bogus on AMD? */
648 if (!pVM->cpum.s.CPUFeatures.edx.u1SEP)
649 Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
650
651 /*
652 * Detect the host CPU vendor.
653 * (The guest CPU vendor is re-detected later on.)
654 */
655 uint32_t uEAX, uEBX, uECX, uEDX;
656 ASMCpuId(0, &uEAX, &uEBX, &uECX, &uEDX);
657 pVM->cpum.s.enmHostCpuVendor = cpumR3DetectVendor(uEAX, uEBX, uECX, uEDX);
658 pVM->cpum.s.enmGuestCpuVendor = pVM->cpum.s.enmHostCpuVendor;
659
660 /*
661 * Setup hypervisor startup values.
662 */
663
664 /*
665 * Register saved state data item.
666 */
667 int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
668 NULL, cpumR3LiveExec, NULL,
669 NULL, cpumR3SaveExec, NULL,
670 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
671 if (RT_FAILURE(rc))
672 return rc;
673
674 /*
675 * Register info handlers and registers with the debugger facility.
676 */
677 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
678 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
679 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
680 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
681 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
682 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
683
684 rc = cpumR3DbgInit(pVM);
685 if (RT_FAILURE(rc))
686 return rc;
687
688 /*
689 * Check if we need to workaround partial/leaky FPU handling.
690 */
691 cpumR3CheckLeakyFpu(pVM);
692
693 /*
694 * Initialize the Guest CPUID state.
695 */
696 rc = cpumR3CpuIdInit(pVM);
697 if (RT_FAILURE(rc))
698 return rc;
699 CPUMR3Reset(pVM);
700 return VINF_SUCCESS;
701}
702
703
704/**
705 * Detect the CPU vendor give n the
706 *
707 * @returns The vendor.
708 * @param uEAX EAX from CPUID(0).
709 * @param uEBX EBX from CPUID(0).
710 * @param uECX ECX from CPUID(0).
711 * @param uEDX EDX from CPUID(0).
712 */
713static CPUMCPUVENDOR cpumR3DetectVendor(uint32_t uEAX, uint32_t uEBX, uint32_t uECX, uint32_t uEDX)
714{
715 if (ASMIsValidStdRange(uEAX))
716 {
717 if (ASMIsAmdCpuEx(uEBX, uECX, uEDX))
718 return CPUMCPUVENDOR_AMD;
719
720 if (ASMIsIntelCpuEx(uEBX, uECX, uEDX))
721 return CPUMCPUVENDOR_INTEL;
722
723 if (ASMIsViaCentaurCpuEx(uEBX, uECX, uEDX))
724 return CPUMCPUVENDOR_VIA;
725
726 /** @todo detect the other buggers... */
727 }
728
729 return CPUMCPUVENDOR_UNKNOWN;
730}
731
732
733/**
734 * Fetches overrides for a CPUID leaf.
735 *
736 * @returns VBox status code.
737 * @param pLeaf The leaf to load the overrides into.
738 * @param pCfgNode The CFGM node containing the overrides
739 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
740 * @param iLeaf The CPUID leaf number.
741 */
742static int cpumR3CpuIdFetchLeafOverride(PCPUMCPUID pLeaf, PCFGMNODE pCfgNode, uint32_t iLeaf)
743{
744 PCFGMNODE pLeafNode = CFGMR3GetChildF(pCfgNode, "%RX32", iLeaf);
745 if (pLeafNode)
746 {
747 uint32_t u32;
748 int rc = CFGMR3QueryU32(pLeafNode, "eax", &u32);
749 if (RT_SUCCESS(rc))
750 pLeaf->eax = u32;
751 else
752 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
753
754 rc = CFGMR3QueryU32(pLeafNode, "ebx", &u32);
755 if (RT_SUCCESS(rc))
756 pLeaf->ebx = u32;
757 else
758 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
759
760 rc = CFGMR3QueryU32(pLeafNode, "ecx", &u32);
761 if (RT_SUCCESS(rc))
762 pLeaf->ecx = u32;
763 else
764 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
765
766 rc = CFGMR3QueryU32(pLeafNode, "edx", &u32);
767 if (RT_SUCCESS(rc))
768 pLeaf->edx = u32;
769 else
770 AssertReturn(rc == VERR_CFGM_VALUE_NOT_FOUND, rc);
771
772 }
773 return VINF_SUCCESS;
774}
775
776
777/**
778 * Load the overrides for a set of CPUID leaves.
779 *
780 * @returns VBox status code.
781 * @param paLeaves The leaf array.
782 * @param cLeaves The number of leaves.
783 * @param uStart The start leaf number.
784 * @param pCfgNode The CFGM node containing the overrides
785 * (/CPUM/HostCPUID/ or /CPUM/CPUID/).
786 */
787static int cpumR3CpuIdInitLoadOverrideSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
788{
789 for (uint32_t i = 0; i < cLeaves; i++)
790 {
791 int rc = cpumR3CpuIdFetchLeafOverride(&paLeaves[i], pCfgNode, uStart + i);
792 if (RT_FAILURE(rc))
793 return rc;
794 }
795
796 return VINF_SUCCESS;
797}
798
799/**
800 * Init a set of host CPUID leaves.
801 *
802 * @returns VBox status code.
803 * @param paLeaves The leaf array.
804 * @param cLeaves The number of leaves.
805 * @param uStart The start leaf number.
806 * @param pCfgNode The /CPUM/HostCPUID/ node.
807 */
808static int cpumR3CpuIdInitHostSet(uint32_t uStart, PCPUMCPUID paLeaves, uint32_t cLeaves, PCFGMNODE pCfgNode)
809{
810 /* Using the ECX variant for all of them can't hurt... */
811 for (uint32_t i = 0; i < cLeaves; i++)
812 ASMCpuId_Idx_ECX(uStart + i, 0, &paLeaves[i].eax, &paLeaves[i].ebx, &paLeaves[i].ecx, &paLeaves[i].edx);
813
814 /* Load CPUID leaf override; we currently don't care if the user
815 specifies features the host CPU doesn't support. */
816 return cpumR3CpuIdInitLoadOverrideSet(uStart, paLeaves, cLeaves, pCfgNode);
817}
818
819
820/**
821 * Initializes the emulated CPU's cpuid information.
822 *
823 * @returns VBox status code.
824 * @param pVM Pointer to the VM.
825 */
826static int cpumR3CpuIdInit(PVM pVM)
827{
828 PCPUM pCPUM = &pVM->cpum.s;
829 PCFGMNODE pCpumCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM");
830 uint32_t i;
831 int rc;
832
833#define PORTABLE_CLEAR_BITS_WHEN(Lvl, LeafSuffReg, FeatNm, fMask, uValue) \
834 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fMask)) == (uValue) ) \
835 { \
836 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: %#x -> 0\n", pCPUM->aGuestCpuId##LeafSuffReg & (fMask))); \
837 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fMask); \
838 }
839#define PORTABLE_DISABLE_FEATURE_BIT(Lvl, LeafSuffReg, FeatNm, fBitMask) \
840 if (pCPUM->u8PortableCpuIdLevel >= (Lvl) && (pCPUM->aGuestCpuId##LeafSuffReg & (fBitMask)) ) \
841 { \
842 LogRel(("PortableCpuId: " #LeafSuffReg "[" #FeatNm "]: 1 -> 0\n")); \
843 pCPUM->aGuestCpuId##LeafSuffReg &= ~(uint32_t)(fBitMask); \
844 }
845
846 /*
847 * Read the configuration.
848 */
849 /** @cfgm{CPUM/SyntheticCpu, boolean, false}
850 * Enables the Synthetic CPU. The Vendor ID and Processor Name are
851 * completely overridden by VirtualBox custom strings. Some
852 * CPUID information is withheld, like the cache info. */
853 rc = CFGMR3QueryBoolDef(pCpumCfg, "SyntheticCpu", &pCPUM->fSyntheticCpu, false);
854 AssertRCReturn(rc, rc);
855
856 /** @cfgm{CPUM/PortableCpuIdLevel, 8-bit, 0, 3, 0}
857 * When non-zero CPUID features that could cause portability issues will be
858 * stripped. The higher the value the more features gets stripped. Higher
859 * values should only be used when older CPUs are involved since it may
860 * harm performance and maybe also cause problems with specific guests. */
861 rc = CFGMR3QueryU8Def(pCpumCfg, "PortableCpuIdLevel", &pCPUM->u8PortableCpuIdLevel, 0);
862 AssertRCReturn(rc, rc);
863
864 AssertLogRelReturn(!pCPUM->fSyntheticCpu || !pCPUM->u8PortableCpuIdLevel, VERR_CPUM_INCOMPATIBLE_CONFIG);
865
866 /*
867 * Get the host CPUID leaves and redetect the guest CPU vendor (could've
868 * been overridden).
869 */
870 /** @cfgm{CPUM/HostCPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
871 * Overrides the host CPUID leaf values used for calculating the guest CPUID
872 * leaves. This can be used to preserve the CPUID values when moving a VM to a
873 * different machine. Another use is restricting (or extending) the feature set
874 * exposed to the guest. */
875 PCFGMNODE pHostOverrideCfg = CFGMR3GetChild(pCpumCfg, "HostCPUID");
876 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pHostOverrideCfg);
877 AssertRCReturn(rc, rc);
878 rc = cpumR3CpuIdInitHostSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pHostOverrideCfg);
879 AssertRCReturn(rc, rc);
880 rc = cpumR3CpuIdInitHostSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pHostOverrideCfg);
881 AssertRCReturn(rc, rc);
882
883 pCPUM->enmGuestCpuVendor = cpumR3DetectVendor(pCPUM->aGuestCpuIdStd[0].eax, pCPUM->aGuestCpuIdStd[0].ebx,
884 pCPUM->aGuestCpuIdStd[0].ecx, pCPUM->aGuestCpuIdStd[0].edx);
885
886 /*
887 * Determine the default leaf.
888 *
889 * Intel returns values of the highest standard function, while AMD
890 * returns zeros. VIA on the other hand seems to returning nothing or
891 * perhaps some random garbage, we don't try to duplicate this behavior.
892 */
893 ASMCpuId(pCPUM->aGuestCpuIdStd[0].eax + 10, /** @todo r=bird: Use the host value here in case of overrides and more than 10 leaves being stripped already. */
894 &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
895 &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
896
897 /** @cfgm{/CPUM/CMPXCHG16B, boolean, false}
898 * Expose CMPXCHG16B to the guest if supported by the host.
899 */
900 bool fCmpXchg16b;
901 rc = CFGMR3QueryBoolDef(pCpumCfg, "CMPXCHG16B", &fCmpXchg16b, false); AssertRCReturn(rc, rc);
902
903 /** @cfgm{/CPUM/MONITOR, boolean, true}
904 * Expose MONITOR/MWAIT instructions to the guest.
905 */
906 bool fMonitor;
907 rc = CFGMR3QueryBoolDef(pCpumCfg, "MONITOR", &fMonitor, true); AssertRCReturn(rc, rc);
908
909 /* Cpuid 1 & 0x80000001:
910 * Only report features we can support.
911 *
912 * Note! When enabling new features the Synthetic CPU and Portable CPUID
913 * options may require adjusting (i.e. stripping what was enabled).
914 */
915 pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
916 | X86_CPUID_FEATURE_EDX_VME
917 | X86_CPUID_FEATURE_EDX_DE
918 | X86_CPUID_FEATURE_EDX_PSE
919 | X86_CPUID_FEATURE_EDX_TSC
920 | X86_CPUID_FEATURE_EDX_MSR
921 //| X86_CPUID_FEATURE_EDX_PAE - set later if configured.
922 | X86_CPUID_FEATURE_EDX_MCE
923 | X86_CPUID_FEATURE_EDX_CX8
924 //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
925 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
926 //| X86_CPUID_FEATURE_EDX_SEP
927 | X86_CPUID_FEATURE_EDX_MTRR
928 | X86_CPUID_FEATURE_EDX_PGE
929 | X86_CPUID_FEATURE_EDX_MCA
930 | X86_CPUID_FEATURE_EDX_CMOV
931 | X86_CPUID_FEATURE_EDX_PAT
932 | X86_CPUID_FEATURE_EDX_PSE36
933 //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
934 | X86_CPUID_FEATURE_EDX_CLFSH
935 //| X86_CPUID_FEATURE_EDX_DS - no debug store.
936 //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
937 | X86_CPUID_FEATURE_EDX_MMX
938 | X86_CPUID_FEATURE_EDX_FXSR
939 | X86_CPUID_FEATURE_EDX_SSE
940 | X86_CPUID_FEATURE_EDX_SSE2
941 //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
942 //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
943 //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
944 //| X86_CPUID_FEATURE_EDX_PBE - no pending break enabled.
945 | 0;
946 pCPUM->aGuestCpuIdStd[1].ecx &= 0
947 | X86_CPUID_FEATURE_ECX_SSE3
948 /* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
949 | ((fMonitor && pVM->cCpus == 1) ? X86_CPUID_FEATURE_ECX_MONITOR : 0)
950 //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
951 //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
952 //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
953 //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
954 | X86_CPUID_FEATURE_ECX_SSSE3
955 //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
956 | (fCmpXchg16b ? X86_CPUID_FEATURE_ECX_CX16 : 0)
957 /* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
958 //| X86_CPUID_FEATURE_ECX_TPRUPDATE
959 /* ECX Bit 21 - x2APIC support - not yet. */
960 // | X86_CPUID_FEATURE_ECX_X2APIC
961 /* ECX Bit 23 - POPCNT instruction. */
962 //| X86_CPUID_FEATURE_ECX_POPCNT
963 | 0;
964 if (pCPUM->u8PortableCpuIdLevel > 0)
965 {
966 PORTABLE_CLEAR_BITS_WHEN(1, Std[1].eax, ProcessorType, (UINT32_C(3) << 12), (UINT32_C(2) << 12));
967 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSSE3, X86_CPUID_FEATURE_ECX_SSSE3);
968 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, SSE3, X86_CPUID_FEATURE_ECX_SSE3);
969 PORTABLE_DISABLE_FEATURE_BIT(1, Std[1].ecx, CX16, X86_CPUID_FEATURE_ECX_CX16);
970 PORTABLE_DISABLE_FEATURE_BIT(2, Std[1].edx, SSE2, X86_CPUID_FEATURE_EDX_SSE2);
971 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, SSE, X86_CPUID_FEATURE_EDX_SSE);
972 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CLFSH, X86_CPUID_FEATURE_EDX_CLFSH);
973 PORTABLE_DISABLE_FEATURE_BIT(3, Std[1].edx, CMOV, X86_CPUID_FEATURE_EDX_CMOV);
974
975 Assert(!(pCPUM->aGuestCpuIdStd[1].edx & ( X86_CPUID_FEATURE_EDX_SEP
976 | X86_CPUID_FEATURE_EDX_PSN
977 | X86_CPUID_FEATURE_EDX_DS
978 | X86_CPUID_FEATURE_EDX_ACPI
979 | X86_CPUID_FEATURE_EDX_SS
980 | X86_CPUID_FEATURE_EDX_TM
981 | X86_CPUID_FEATURE_EDX_PBE
982 )));
983 Assert(!(pCPUM->aGuestCpuIdStd[1].ecx & ( X86_CPUID_FEATURE_ECX_PCLMUL
984 | X86_CPUID_FEATURE_ECX_DTES64
985 | X86_CPUID_FEATURE_ECX_CPLDS
986 | X86_CPUID_FEATURE_ECX_VMX
987 | X86_CPUID_FEATURE_ECX_SMX
988 | X86_CPUID_FEATURE_ECX_EST
989 | X86_CPUID_FEATURE_ECX_TM2
990 | X86_CPUID_FEATURE_ECX_CNTXID
991 | X86_CPUID_FEATURE_ECX_FMA
992 | X86_CPUID_FEATURE_ECX_CX16
993 | X86_CPUID_FEATURE_ECX_TPRUPDATE
994 | X86_CPUID_FEATURE_ECX_PDCM
995 | X86_CPUID_FEATURE_ECX_DCA
996 | X86_CPUID_FEATURE_ECX_MOVBE
997 | X86_CPUID_FEATURE_ECX_AES
998 | X86_CPUID_FEATURE_ECX_POPCNT
999 | X86_CPUID_FEATURE_ECX_XSAVE
1000 | X86_CPUID_FEATURE_ECX_OSXSAVE
1001 | X86_CPUID_FEATURE_ECX_AVX
1002 )));
1003 }
1004
1005 /* Cpuid 0x80000001:
1006 * Only report features we can support.
1007 *
1008 * Note! When enabling new features the Synthetic CPU and Portable CPUID
1009 * options may require adjusting (i.e. stripping what was enabled).
1010 *
1011 * ASSUMES that this is ALWAYS the AMD defined feature set if present.
1012 */
1013 pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
1014 | X86_CPUID_AMD_FEATURE_EDX_VME
1015 | X86_CPUID_AMD_FEATURE_EDX_DE
1016 | X86_CPUID_AMD_FEATURE_EDX_PSE
1017 | X86_CPUID_AMD_FEATURE_EDX_TSC
1018 | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
1019 //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
1020 //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
1021 | X86_CPUID_AMD_FEATURE_EDX_CX8
1022 //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
1023 /* Note! we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see @bugref{1757}) */
1024 //| X86_CPUID_EXT_FEATURE_EDX_SEP
1025 | X86_CPUID_AMD_FEATURE_EDX_MTRR
1026 | X86_CPUID_AMD_FEATURE_EDX_PGE
1027 | X86_CPUID_AMD_FEATURE_EDX_MCA
1028 | X86_CPUID_AMD_FEATURE_EDX_CMOV
1029 | X86_CPUID_AMD_FEATURE_EDX_PAT
1030 | X86_CPUID_AMD_FEATURE_EDX_PSE36
1031 //| X86_CPUID_EXT_FEATURE_EDX_NX - not virtualized, requires PAE.
1032 //| X86_CPUID_AMD_FEATURE_EDX_AXMMX
1033 | X86_CPUID_AMD_FEATURE_EDX_MMX
1034 | X86_CPUID_AMD_FEATURE_EDX_FXSR
1035 | X86_CPUID_AMD_FEATURE_EDX_FFXSR
1036 //| X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1037 | X86_CPUID_EXT_FEATURE_EDX_RDTSCP
1038 //| X86_CPUID_EXT_FEATURE_EDX_LONG_MODE - turned on when necessary
1039 | X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX
1040 | X86_CPUID_AMD_FEATURE_EDX_3DNOW
1041 | 0;
1042 pCPUM->aGuestCpuIdExt[1].ecx &= 0
1043 //| X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF
1044 //| X86_CPUID_AMD_FEATURE_ECX_CMPL
1045 //| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
1046 //| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1047 /* Note: This could prevent teleporting from AMD to Intel CPUs! */
1048 | X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
1049 //| X86_CPUID_AMD_FEATURE_ECX_ABM
1050 //| X86_CPUID_AMD_FEATURE_ECX_SSE4A
1051 //| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1052 //| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1053 //| X86_CPUID_AMD_FEATURE_ECX_OSVW
1054 //| X86_CPUID_AMD_FEATURE_ECX_IBS
1055 //| X86_CPUID_AMD_FEATURE_ECX_SSE5
1056 //| X86_CPUID_AMD_FEATURE_ECX_SKINIT
1057 //| X86_CPUID_AMD_FEATURE_ECX_WDT
1058 | 0;
1059 if (pCPUM->u8PortableCpuIdLevel > 0)
1060 {
1061 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].ecx, CR8L, X86_CPUID_AMD_FEATURE_ECX_CR8L);
1062 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
1063 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, 3DNOW_EX, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
1064 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, FFXSR, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
1065 PORTABLE_DISABLE_FEATURE_BIT(1, Ext[1].edx, RDTSCP, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
1066 PORTABLE_DISABLE_FEATURE_BIT(2, Ext[1].ecx, LAHF_SAHF, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
1067 PORTABLE_DISABLE_FEATURE_BIT(3, Ext[1].ecx, CMOV, X86_CPUID_AMD_FEATURE_EDX_CMOV);
1068
1069 Assert(!(pCPUM->aGuestCpuIdExt[1].ecx & ( X86_CPUID_AMD_FEATURE_ECX_CMPL
1070 | X86_CPUID_AMD_FEATURE_ECX_SVM
1071 | X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
1072 | X86_CPUID_AMD_FEATURE_ECX_CR8L
1073 | X86_CPUID_AMD_FEATURE_ECX_ABM
1074 | X86_CPUID_AMD_FEATURE_ECX_SSE4A
1075 | X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
1076 | X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
1077 | X86_CPUID_AMD_FEATURE_ECX_OSVW
1078 | X86_CPUID_AMD_FEATURE_ECX_IBS
1079 | X86_CPUID_AMD_FEATURE_ECX_SSE5
1080 | X86_CPUID_AMD_FEATURE_ECX_SKINIT
1081 | X86_CPUID_AMD_FEATURE_ECX_WDT
1082 | UINT32_C(0xffffc000)
1083 )));
1084 Assert(!(pCPUM->aGuestCpuIdExt[1].edx & ( RT_BIT(10)
1085 | X86_CPUID_EXT_FEATURE_EDX_SYSCALL
1086 | RT_BIT(18)
1087 | RT_BIT(19)
1088 | RT_BIT(21)
1089 | X86_CPUID_AMD_FEATURE_EDX_AXMMX
1090 | X86_CPUID_EXT_FEATURE_EDX_PAGE1GB
1091 | RT_BIT(28)
1092 )));
1093 }
1094
1095 /*
1096 * Apply the Synthetic CPU modifications. (TODO: move this up)
1097 */
1098 if (pCPUM->fSyntheticCpu)
1099 {
1100 static const char s_szVendor[13] = "VirtualBox ";
1101 static const char s_szProcessor[48] = "VirtualBox SPARCx86 Processor v1000 "; /* includes null terminator */
1102
1103 pCPUM->enmGuestCpuVendor = CPUMCPUVENDOR_SYNTHETIC;
1104
1105 /* Limit the nr of standard leaves; 5 for monitor/mwait */
1106 pCPUM->aGuestCpuIdStd[0].eax = RT_MIN(pCPUM->aGuestCpuIdStd[0].eax, 5);
1107
1108 /* 0: Vendor */
1109 pCPUM->aGuestCpuIdStd[0].ebx = pCPUM->aGuestCpuIdExt[0].ebx = ((uint32_t *)s_szVendor)[0];
1110 pCPUM->aGuestCpuIdStd[0].ecx = pCPUM->aGuestCpuIdExt[0].ecx = ((uint32_t *)s_szVendor)[2];
1111 pCPUM->aGuestCpuIdStd[0].edx = pCPUM->aGuestCpuIdExt[0].edx = ((uint32_t *)s_szVendor)[1];
1112
1113 /* 1.eax: Version information. family : model : stepping */
1114 pCPUM->aGuestCpuIdStd[1].eax = (0xf << 8) + (0x1 << 4) + 1;
1115
1116 /* Leaves 2 - 4 are Intel only - zero them out */
1117 memset(&pCPUM->aGuestCpuIdStd[2], 0, sizeof(pCPUM->aGuestCpuIdStd[2]));
1118 memset(&pCPUM->aGuestCpuIdStd[3], 0, sizeof(pCPUM->aGuestCpuIdStd[3]));
1119 memset(&pCPUM->aGuestCpuIdStd[4], 0, sizeof(pCPUM->aGuestCpuIdStd[4]));
1120
1121 /* Leaf 5 = monitor/mwait */
1122
1123 /* Limit the nr of extended leaves: 0x80000008 to include the max virtual and physical address size (64 bits guests). */
1124 pCPUM->aGuestCpuIdExt[0].eax = RT_MIN(pCPUM->aGuestCpuIdExt[0].eax, 0x80000008);
1125 /* AMD only - set to zero. */
1126 pCPUM->aGuestCpuIdExt[0].ebx = pCPUM->aGuestCpuIdExt[0].ecx = pCPUM->aGuestCpuIdExt[0].edx = 0;
1127
1128 /* 0x800000001: shared feature bits are set dynamically. */
1129 memset(&pCPUM->aGuestCpuIdExt[1], 0, sizeof(pCPUM->aGuestCpuIdExt[1]));
1130
1131 /* 0x800000002-4: Processor Name String Identifier. */
1132 pCPUM->aGuestCpuIdExt[2].eax = ((uint32_t *)s_szProcessor)[0];
1133 pCPUM->aGuestCpuIdExt[2].ebx = ((uint32_t *)s_szProcessor)[1];
1134 pCPUM->aGuestCpuIdExt[2].ecx = ((uint32_t *)s_szProcessor)[2];
1135 pCPUM->aGuestCpuIdExt[2].edx = ((uint32_t *)s_szProcessor)[3];
1136 pCPUM->aGuestCpuIdExt[3].eax = ((uint32_t *)s_szProcessor)[4];
1137 pCPUM->aGuestCpuIdExt[3].ebx = ((uint32_t *)s_szProcessor)[5];
1138 pCPUM->aGuestCpuIdExt[3].ecx = ((uint32_t *)s_szProcessor)[6];
1139 pCPUM->aGuestCpuIdExt[3].edx = ((uint32_t *)s_szProcessor)[7];
1140 pCPUM->aGuestCpuIdExt[4].eax = ((uint32_t *)s_szProcessor)[8];
1141 pCPUM->aGuestCpuIdExt[4].ebx = ((uint32_t *)s_szProcessor)[9];
1142 pCPUM->aGuestCpuIdExt[4].ecx = ((uint32_t *)s_szProcessor)[10];
1143 pCPUM->aGuestCpuIdExt[4].edx = ((uint32_t *)s_szProcessor)[11];
1144
1145 /* 0x800000005-7 - reserved -> zero */
1146 memset(&pCPUM->aGuestCpuIdExt[5], 0, sizeof(pCPUM->aGuestCpuIdExt[5]));
1147 memset(&pCPUM->aGuestCpuIdExt[6], 0, sizeof(pCPUM->aGuestCpuIdExt[6]));
1148 memset(&pCPUM->aGuestCpuIdExt[7], 0, sizeof(pCPUM->aGuestCpuIdExt[7]));
1149
1150 /* 0x800000008: only the max virtual and physical address size. */
1151 pCPUM->aGuestCpuIdExt[8].ecx = pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1152 }
1153
1154 /*
1155 * Hide HTT, multicode, SMP, whatever.
1156 * (APIC-ID := 0 and #LogCpus := 0)
1157 */
1158 pCPUM->aGuestCpuIdStd[1].ebx &= 0x0000ffff;
1159#ifdef VBOX_WITH_MULTI_CORE
1160 if ( pCPUM->enmGuestCpuVendor != CPUMCPUVENDOR_SYNTHETIC
1161 && pVM->cCpus > 1)
1162 {
1163 /* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
1164 pCPUM->aGuestCpuIdStd[1].ebx |= (pVM->cCpus << 16);
1165 pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
1166 }
1167#endif
1168
1169 /* Cpuid 2:
1170 * Intel: Cache and TLB information
1171 * AMD: Reserved
1172 * VIA: Reserved
1173 * Safe to expose; restrict the number of calls to 1 for the portable case.
1174 */
1175 if ( pCPUM->u8PortableCpuIdLevel > 0
1176 && pCPUM->aGuestCpuIdStd[0].eax >= 2
1177 && (pCPUM->aGuestCpuIdStd[2].eax & 0xff) > 1)
1178 {
1179 LogRel(("PortableCpuId: Std[2].al: %d -> 1\n", pCPUM->aGuestCpuIdStd[2].eax & 0xff));
1180 pCPUM->aGuestCpuIdStd[2].eax &= UINT32_C(0xfffffffe);
1181 }
1182
1183 /* Cpuid 3:
1184 * Intel: EAX, EBX - reserved (transmeta uses these)
1185 * ECX, EDX - Processor Serial Number if available, otherwise reserved
1186 * AMD: Reserved
1187 * VIA: Reserved
1188 * Safe to expose
1189 */
1190 if (!(pCPUM->aGuestCpuIdStd[1].edx & X86_CPUID_FEATURE_EDX_PSN))
1191 {
1192 pCPUM->aGuestCpuIdStd[3].ecx = pCPUM->aGuestCpuIdStd[3].edx = 0;
1193 if (pCPUM->u8PortableCpuIdLevel > 0)
1194 pCPUM->aGuestCpuIdStd[3].eax = pCPUM->aGuestCpuIdStd[3].ebx = 0;
1195 }
1196
1197 /* Cpuid 4:
1198 * Intel: Deterministic Cache Parameters Leaf
1199 * Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
1200 * AMD: Reserved
1201 * VIA: Reserved
1202 * Safe to expose, except for EAX:
1203 * Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
1204 * Bits 31-26: Maximum number of processor cores in this physical package**
1205 * Note: These SMP values are constant regardless of ECX
1206 */
1207 pCPUM->aGuestCpuIdStd[4].ecx = pCPUM->aGuestCpuIdStd[4].edx = 0;
1208 pCPUM->aGuestCpuIdStd[4].eax = pCPUM->aGuestCpuIdStd[4].ebx = 0;
1209#ifdef VBOX_WITH_MULTI_CORE
1210 if ( pVM->cCpus > 1
1211 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1212 {
1213 AssertReturn(pVM->cCpus <= 64, VERR_TOO_MANY_CPUS);
1214 /* One logical processor with possibly multiple cores. */
1215 /* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
1216 pCPUM->aGuestCpuIdStd[4].eax |= ((pVM->cCpus - 1) << 26); /* 6 bits only -> 64 cores! */
1217 }
1218#endif
1219
1220 /* Cpuid 5: Monitor/mwait Leaf
1221 * Intel: ECX, EDX - reserved
1222 * EAX, EBX - Smallest and largest monitor line size
1223 * AMD: EDX - reserved
1224 * EAX, EBX - Smallest and largest monitor line size
1225 * ECX - extensions (ignored for now)
1226 * VIA: Reserved
1227 * Safe to expose
1228 */
1229 if (!(pCPUM->aGuestCpuIdStd[1].ecx & X86_CPUID_FEATURE_ECX_MONITOR))
1230 pCPUM->aGuestCpuIdStd[5].eax = pCPUM->aGuestCpuIdStd[5].ebx = 0;
1231
1232 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1233 /** @cfgm{/CPUM/MWaitExtensions, boolean, false}
1234 * Expose MWAIT extended features to the guest. For now we expose
1235 * just MWAIT break on interrupt feature (bit 1).
1236 */
1237 bool fMWaitExtensions;
1238 rc = CFGMR3QueryBoolDef(pCpumCfg, "MWaitExtensions", &fMWaitExtensions, false); AssertRCReturn(rc, rc);
1239 if (fMWaitExtensions)
1240 {
1241 pCPUM->aGuestCpuIdStd[5].ecx = X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0;
1242 /** @todo: for now we just expose host's MWAIT C-states, although conceptually
1243 it shall be part of our power management virtualization model */
1244#if 0
1245 /* MWAIT sub C-states */
1246 pCPUM->aGuestCpuIdStd[5].edx =
1247 (0 << 0) /* 0 in C0 */ |
1248 (2 << 4) /* 2 in C1 */ |
1249 (2 << 8) /* 2 in C2 */ |
1250 (2 << 12) /* 2 in C3 */ |
1251 (0 << 16) /* 0 in C4 */
1252 ;
1253#endif
1254 }
1255 else
1256 pCPUM->aGuestCpuIdStd[5].ecx = pCPUM->aGuestCpuIdStd[5].edx = 0;
1257
1258 /* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
1259 * Safe to pass on to the guest.
1260 *
1261 * Intel: 0x800000005 reserved
1262 * 0x800000006 L2 cache information
1263 * AMD: 0x800000005 L1 cache information
1264 * 0x800000006 L2/L3 cache information
1265 * VIA: 0x800000005 TLB and L1 cache information
1266 * 0x800000006 L2 cache information
1267 */
1268
1269 /* Cpuid 0x800000007:
1270 * Intel: Reserved
1271 * AMD: EAX, EBX, ECX - reserved
1272 * EDX: Advanced Power Management Information
1273 * VIA: Reserved
1274 */
1275 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000007))
1276 {
1277 Assert(pVM->cpum.s.enmGuestCpuVendor != CPUMCPUVENDOR_INVALID);
1278
1279 pCPUM->aGuestCpuIdExt[7].eax = pCPUM->aGuestCpuIdExt[7].ebx = pCPUM->aGuestCpuIdExt[7].ecx = 0;
1280
1281 if (pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1282 {
1283 /* Only expose the TSC invariant capability bit to the guest. */
1284 pCPUM->aGuestCpuIdExt[7].edx &= 0
1285 //| X86_CPUID_AMD_ADVPOWER_EDX_TS
1286 //| X86_CPUID_AMD_ADVPOWER_EDX_FID
1287 //| X86_CPUID_AMD_ADVPOWER_EDX_VID
1288 //| X86_CPUID_AMD_ADVPOWER_EDX_TTP
1289 //| X86_CPUID_AMD_ADVPOWER_EDX_TM
1290 //| X86_CPUID_AMD_ADVPOWER_EDX_STC
1291 //| X86_CPUID_AMD_ADVPOWER_EDX_MC
1292 //| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
1293#if 0
1294 /*
1295 * We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer
1296 * Linux kernels blindly assume that the AMD performance counters work
1297 * if this is set for 64 bits guests. (Can't really find a CPUID feature
1298 * bit for them though.)
1299 */
1300 | X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR
1301#endif
1302 | 0;
1303 }
1304 else
1305 pCPUM->aGuestCpuIdExt[7].edx = 0;
1306 }
1307
1308 /* Cpuid 0x800000008:
1309 * Intel: EAX: Virtual/Physical address Size
1310 * EBX, ECX, EDX - reserved
1311 * AMD: EBX, EDX - reserved
1312 * EAX: Virtual/Physical/Guest address Size
1313 * ECX: Number of cores + APICIdCoreIdSize
1314 * VIA: EAX: Virtual/Physical address Size
1315 * EBX, ECX, EDX - reserved
1316 */
1317 if (pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000008))
1318 {
1319 /* Only expose the virtual and physical address sizes to the guest. */
1320 pCPUM->aGuestCpuIdExt[8].eax &= UINT32_C(0x0000ffff);
1321 pCPUM->aGuestCpuIdExt[8].ebx = pCPUM->aGuestCpuIdExt[8].edx = 0; /* reserved */
1322 /* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
1323 * NC (0-7) Number of cores; 0 equals 1 core */
1324 pCPUM->aGuestCpuIdExt[8].ecx = 0;
1325#ifdef VBOX_WITH_MULTI_CORE
1326 if ( pVM->cCpus > 1
1327 && pVM->cpum.s.enmGuestCpuVendor == CPUMCPUVENDOR_AMD)
1328 {
1329 /* Legacy method to determine the number of cores. */
1330 pCPUM->aGuestCpuIdExt[1].ecx |= X86_CPUID_AMD_FEATURE_ECX_CMPL;
1331 pCPUM->aGuestCpuIdExt[8].ecx |= (pVM->cCpus - 1); /* NC: Number of CPU cores - 1; 8 bits */
1332 }
1333#endif
1334 }
1335
1336 /** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
1337 * Limit the number of standard CPUID leaves to 0..3 to prevent NT4 from
1338 * bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
1339 * This option corresponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
1340 */
1341 bool fNt4LeafLimit;
1342 rc = CFGMR3QueryBoolDef(pCpumCfg, "NT4LeafLimit", &fNt4LeafLimit, false); AssertRCReturn(rc, rc);
1343 if (fNt4LeafLimit && pCPUM->aGuestCpuIdStd[0].eax > 3)
1344 pCPUM->aGuestCpuIdStd[0].eax = 3;
1345
1346 /*
1347 * Limit it the number of entries and fill the remaining with the defaults.
1348 *
1349 * The limits are masking off stuff about power saving and similar, this
1350 * is perhaps a bit crudely done as there is probably some relatively harmless
1351 * info too in these leaves (like words about having a constant TSC).
1352 */
1353 if (pCPUM->aGuestCpuIdStd[0].eax > 5)
1354 pCPUM->aGuestCpuIdStd[0].eax = 5;
1355 for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
1356 pCPUM->aGuestCpuIdStd[i] = pCPUM->GuestCpuIdDef;
1357
1358 if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000008))
1359 pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000008);
1360 for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
1361 ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
1362 : 0;
1363 i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt);
1364 i++)
1365 pCPUM->aGuestCpuIdExt[i] = pCPUM->GuestCpuIdDef;
1366
1367 /*
1368 * Centaur stuff (VIA).
1369 *
1370 * The important part here (we think) is to make sure the 0xc0000000
1371 * function returns 0xc0000001. As for the features, we don't currently
1372 * let on about any of those... 0xc0000002 seems to be some
1373 * temperature/hz/++ stuff, include it as well (static).
1374 */
1375 if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
1376 && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
1377 {
1378 pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
1379 pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
1380 for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
1381 i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
1382 i++)
1383 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1384 }
1385 else
1386 for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
1387 pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
1388
1389 /*
1390 * Hypervisor identification.
1391 *
1392 * We only return minimal information, primarily ensuring that the
1393 * 0x40000000 function returns 0x40000001 and identifying ourselves.
1394 * Currently we do not support any hypervisor-specific interface.
1395 */
1396 pCPUM->aGuestCpuIdHyper[0].eax = UINT32_C(0x40000001);
1397 pCPUM->aGuestCpuIdHyper[0].ebx = pCPUM->aGuestCpuIdHyper[0].ecx
1398 = pCPUM->aGuestCpuIdHyper[0].edx = 0x786f4256; /* 'VBox' */
1399 pCPUM->aGuestCpuIdHyper[1].eax = 0x656e6f6e; /* 'none' */
1400 pCPUM->aGuestCpuIdHyper[1].ebx = pCPUM->aGuestCpuIdHyper[1].ecx
1401 = pCPUM->aGuestCpuIdHyper[1].edx = 0; /* Reserved */
1402
1403 /*
1404 * Mini CPU selection support for making Mac OS X happy.
1405 */
1406 if (pCPUM->enmGuestCpuVendor == CPUMCPUVENDOR_INTEL)
1407 {
1408 /** @cfgm{/CPUM/MaxIntelFamilyModelStep, uint32_t, UINT32_MAX}
1409 * Restrict the reported CPU family+model+stepping of intel CPUs. This is
1410 * probably going to be a temporary hack, so don't depend on this.
1411 * The 1st byte of the value is the stepping, the 2nd byte value is the model
1412 * number and the 3rd byte value is the family, and the 4th value must be zero.
1413 */
1414 uint32_t uMaxIntelFamilyModelStep;
1415 rc = CFGMR3QueryU32Def(pCpumCfg, "MaxIntelFamilyModelStep", &uMaxIntelFamilyModelStep, UINT32_MAX);
1416 AssertRCReturn(rc, rc);
1417 uint32_t uCurIntelFamilyModelStep = RT_MAKE_U32_FROM_U8(ASMGetCpuStepping(pCPUM->aGuestCpuIdStd[1].eax),
1418 ASMGetCpuModelIntel(pCPUM->aGuestCpuIdStd[1].eax),
1419 ASMGetCpuFamily(pCPUM->aGuestCpuIdStd[1].eax),
1420 0);
1421 if (uMaxIntelFamilyModelStep < uCurIntelFamilyModelStep)
1422 {
1423 uint32_t uNew = pCPUM->aGuestCpuIdStd[1].eax & UINT32_C(0xf0003000);
1424 uNew |= RT_BYTE1(uMaxIntelFamilyModelStep) & 0xf; /* stepping */
1425 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) & 0xf) << 4; /* 4 low model bits */
1426 uNew |= (RT_BYTE2(uMaxIntelFamilyModelStep) >> 4) << 16; /* 4 high model bits */
1427 uNew |= (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf) << 8; /* 4 low family bits */
1428 if (RT_BYTE3(uMaxIntelFamilyModelStep) > 0xf) /* 8 high family bits, using intel's suggested calculation. */
1429 uNew |= ( (RT_BYTE3(uMaxIntelFamilyModelStep) - (RT_BYTE3(uMaxIntelFamilyModelStep) & 0xf)) & 0xff ) << 20;
1430 LogRel(("CPU: CPUID(0).EAX %#x -> %#x (uMaxIntelFamilyModelStep=%#x, uCurIntelFamilyModelStep=%#x\n",
1431 pCPUM->aGuestCpuIdStd[1].eax, uNew, uMaxIntelFamilyModelStep, uCurIntelFamilyModelStep));
1432 pCPUM->aGuestCpuIdStd[1].eax = uNew;
1433 }
1434 }
1435
1436 /*
1437 * Load CPUID overrides from configuration.
1438 * Note: Kind of redundant now, but allows unchanged overrides
1439 */
1440 /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
1441 * Overrides the CPUID leaf values. */
1442 PCFGMNODE pOverrideCfg = CFGMR3GetChild(pCpumCfg, "CPUID");
1443 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &pCPUM->aGuestCpuIdStd[0], RT_ELEMENTS(pCPUM->aGuestCpuIdStd), pOverrideCfg);
1444 AssertRCReturn(rc, rc);
1445 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &pCPUM->aGuestCpuIdExt[0], RT_ELEMENTS(pCPUM->aGuestCpuIdExt), pOverrideCfg);
1446 AssertRCReturn(rc, rc);
1447 rc = cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0xc0000000), &pCPUM->aGuestCpuIdCentaur[0], RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur), pOverrideCfg);
1448 AssertRCReturn(rc, rc);
1449
1450 /*
1451 * Check if PAE was explicitely enabled by the user.
1452 */
1453 bool fEnable;
1454 rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable, false); AssertRCReturn(rc, rc);
1455 if (fEnable)
1456 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1457
1458 /*
1459 * We don't normally enable NX for raw-mode, so give the user a chance to
1460 * force it on.
1461 */
1462 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableNX", &fEnable, false); AssertRCReturn(rc, rc);
1463 if (fEnable)
1464 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1465
1466 /*
1467 * We don't enable the Hypervisor Present bit by default, but it may
1468 * be needed by some guests.
1469 */
1470 rc = CFGMR3QueryBoolDef(pCpumCfg, "EnableHVP", &fEnable, false); AssertRCReturn(rc, rc);
1471 if (fEnable)
1472 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_HVP);
1473
1474#undef PORTABLE_DISABLE_FEATURE_BIT
1475#undef PORTABLE_CLEAR_BITS_WHEN
1476
1477 return VINF_SUCCESS;
1478}
1479
1480
1481/**
1482 * Applies relocations to data and code managed by this
1483 * component. This function will be called at init and
1484 * whenever the VMM need to relocate it self inside the GC.
1485 *
1486 * The CPUM will update the addresses used by the switcher.
1487 *
1488 * @param pVM The VM.
1489 */
1490VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1491{
1492 LogFlow(("CPUMR3Relocate\n"));
1493
1494 /* Recheck the guest DRx values in raw-mode. */
1495 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1496 CPUMRecalcHyperDRx(&pVM->aCpus[iCpu], UINT8_MAX, false);
1497}
1498
1499
1500/**
1501 * Apply late CPUM property changes based on the fHWVirtEx setting
1502 *
1503 * @param pVM Pointer to the VM.
1504 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
1505 */
1506VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1507{
1508 /*
1509 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
1510 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1511 * of processors from (cpuid(4).eax >> 26) + 1.
1512 *
1513 * Note: this code is obsolete, but let's keep it here for reference.
1514 * Purpose is valid when we artificially cap the max std id to less than 4.
1515 */
1516 if (!fHWVirtExEnabled)
1517 {
1518 Assert( pVM->cpum.s.aGuestCpuIdStd[4].eax == 0
1519 || pVM->cpum.s.aGuestCpuIdStd[0].eax < 0x4);
1520 pVM->cpum.s.aGuestCpuIdStd[4].eax = 0;
1521 }
1522}
1523
1524/**
1525 * Terminates the CPUM.
1526 *
1527 * Termination means cleaning up and freeing all resources,
1528 * the VM it self is at this point powered off or suspended.
1529 *
1530 * @returns VBox status code.
1531 * @param pVM Pointer to the VM.
1532 */
1533VMMR3DECL(int) CPUMR3Term(PVM pVM)
1534{
1535#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1536 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1537 {
1538 PVMCPU pVCpu = &pVM->aCpus[i];
1539 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1540
1541 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1542 pVCpu->cpum.s.uMagic = 0;
1543 pCtx->dr[5] = 0;
1544 }
1545#else
1546 NOREF(pVM);
1547#endif
1548 return VINF_SUCCESS;
1549}
1550
1551
1552/**
1553 * Resets a virtual CPU.
1554 *
1555 * Used by CPUMR3Reset and CPU hot plugging.
1556 *
1557 * @param pVCpu Pointer to the VMCPU.
1558 */
1559VMMR3DECL(void) CPUMR3ResetCpu(PVMCPU pVCpu)
1560{
1561 /** @todo anything different for VCPU > 0? */
1562 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1563
1564 /*
1565 * Initialize everything to ZERO first.
1566 */
1567 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1568 memset(pCtx, 0, sizeof(*pCtx));
1569 pVCpu->cpum.s.fUseFlags = fUseFlags;
1570
1571 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1572 pCtx->eip = 0x0000fff0;
1573 pCtx->edx = 0x00000600; /* P6 processor */
1574 pCtx->eflags.Bits.u1Reserved0 = 1;
1575
1576 pCtx->cs.Sel = 0xf000;
1577 pCtx->cs.ValidSel = 0xf000;
1578 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1579 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1580 pCtx->cs.u32Limit = 0x0000ffff;
1581 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1582 pCtx->cs.Attr.n.u1Present = 1;
1583 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1584
1585 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1586 pCtx->ds.u32Limit = 0x0000ffff;
1587 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1588 pCtx->ds.Attr.n.u1Present = 1;
1589 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1590
1591 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1592 pCtx->es.u32Limit = 0x0000ffff;
1593 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1594 pCtx->es.Attr.n.u1Present = 1;
1595 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1596
1597 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1598 pCtx->fs.u32Limit = 0x0000ffff;
1599 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1600 pCtx->fs.Attr.n.u1Present = 1;
1601 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1602
1603 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1604 pCtx->gs.u32Limit = 0x0000ffff;
1605 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1606 pCtx->gs.Attr.n.u1Present = 1;
1607 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1608
1609 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1610 pCtx->ss.u32Limit = 0x0000ffff;
1611 pCtx->ss.Attr.n.u1Present = 1;
1612 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1613 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1614
1615 pCtx->idtr.cbIdt = 0xffff;
1616 pCtx->gdtr.cbGdt = 0xffff;
1617
1618 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1619 pCtx->ldtr.u32Limit = 0xffff;
1620 pCtx->ldtr.Attr.n.u1Present = 1;
1621 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1622
1623 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1624 pCtx->tr.u32Limit = 0xffff;
1625 pCtx->tr.Attr.n.u1Present = 1;
1626 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1627
1628 pCtx->dr[6] = X86_DR6_INIT_VAL;
1629 pCtx->dr[7] = X86_DR7_INIT_VAL;
1630
1631 pCtx->fpu.FTW = 0x00; /* All empty (abbridged tag reg edition). */
1632 pCtx->fpu.FCW = 0x37f;
1633
1634 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1635 IA-32 Processor States Following Power-up, Reset, or INIT */
1636 pCtx->fpu.MXCSR = 0x1F80;
1637 pCtx->fpu.MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1638 supports all bits, since a zero value here should be read as 0xffbf. */
1639
1640 /* Init PAT MSR */
1641 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1642
1643 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1644 * The Intel docs don't mention it. */
1645 Assert(!pCtx->msrEFER);
1646
1647 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1648 * called from each EMT while we're getting called by CPUMR3Reset()
1649 * iteratively on the same thread. Fix later. */
1650#if 0
1651 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1652 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1653#endif
1654
1655
1656 /* C-state control. Guesses. */
1657 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1658
1659
1660 /*
1661 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1662 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1663 */
1664 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1665}
1666
1667
1668/**
1669 * Resets the CPU.
1670 *
1671 * @returns VINF_SUCCESS.
1672 * @param pVM Pointer to the VM.
1673 */
1674VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1675{
1676 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1677 {
1678 CPUMR3ResetCpu(&pVM->aCpus[i]);
1679
1680#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1681 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1682
1683 /* Magic marker for searching in crash dumps. */
1684 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1685 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1686 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1687#endif
1688 }
1689}
1690
1691
1692/**
1693 * Called both in pass 0 and the final pass.
1694 *
1695 * @param pVM Pointer to the VM.
1696 * @param pSSM The saved state handle.
1697 */
1698static void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM)
1699{
1700 /*
1701 * Save all the CPU ID leaves here so we can check them for compatibility
1702 * upon loading.
1703 */
1704 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
1705 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
1706
1707 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
1708 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
1709
1710 SSMR3PutU32(pSSM, RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
1711 SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
1712
1713 SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
1714
1715 /*
1716 * Save a good portion of the raw CPU IDs as well as they may come in
1717 * handy when validating features for raw mode.
1718 */
1719 CPUMCPUID aRawStd[16];
1720 for (unsigned i = 0; i < RT_ELEMENTS(aRawStd); i++)
1721 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1722 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawStd));
1723 SSMR3PutMem(pSSM, &aRawStd[0], sizeof(aRawStd));
1724
1725 CPUMCPUID aRawExt[32];
1726 for (unsigned i = 0; i < RT_ELEMENTS(aRawExt); i++)
1727 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1728 SSMR3PutU32(pSSM, RT_ELEMENTS(aRawExt));
1729 SSMR3PutMem(pSSM, &aRawExt[0], sizeof(aRawExt));
1730}
1731
1732
1733/**
1734 * Loads the CPU ID leaves saved by pass 0.
1735 *
1736 * @returns VBox status code.
1737 * @param pVM Pointer to the VM.
1738 * @param pSSM The saved state handle.
1739 * @param uVersion The format version.
1740 */
1741static int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion)
1742{
1743 AssertMsgReturn(uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2, ("%u\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
1744
1745 /*
1746 * Define a bunch of macros for simplifying the code.
1747 */
1748 /* Generic expression + failure message. */
1749#define CPUID_CHECK_RET(expr, fmt) \
1750 do { \
1751 if (!(expr)) \
1752 { \
1753 char *pszMsg = RTStrAPrintf2 fmt; /* lack of variadic macros sucks */ \
1754 if (fStrictCpuIdChecks) \
1755 { \
1756 int rcCpuid = SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, "%s", pszMsg); \
1757 RTStrFree(pszMsg); \
1758 return rcCpuid; \
1759 } \
1760 LogRel(("CPUM: %s\n", pszMsg)); \
1761 RTStrFree(pszMsg); \
1762 } \
1763 } while (0)
1764#define CPUID_CHECK_WRN(expr, fmt) \
1765 do { \
1766 if (!(expr)) \
1767 LogRel(fmt); \
1768 } while (0)
1769
1770 /* For comparing two values and bitch if they differs. */
1771#define CPUID_CHECK2_RET(what, host, saved) \
1772 do { \
1773 if ((host) != (saved)) \
1774 { \
1775 if (fStrictCpuIdChecks) \
1776 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1777 N_(#what " mismatch: host=%#x saved=%#x"), (host), (saved)); \
1778 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1779 } \
1780 } while (0)
1781#define CPUID_CHECK2_WRN(what, host, saved) \
1782 do { \
1783 if ((host) != (saved)) \
1784 LogRel(("CPUM: " #what " differs: host=%#x saved=%#x\n", (host), (saved))); \
1785 } while (0)
1786
1787 /* For checking raw cpu features (raw mode). */
1788#define CPUID_RAW_FEATURE_RET(set, reg, bit) \
1789 do { \
1790 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1791 { \
1792 if (fStrictCpuIdChecks) \
1793 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1794 N_(#bit " mismatch: host=%d saved=%d"), \
1795 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) ); \
1796 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1797 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1798 } \
1799 } while (0)
1800#define CPUID_RAW_FEATURE_WRN(set, reg, bit) \
1801 do { \
1802 if ((aHostRaw##set [1].reg & bit) != (aRaw##set [1].reg & bit)) \
1803 LogRel(("CPUM: " #bit" differs: host=%d saved=%d\n", \
1804 !!(aHostRaw##set [1].reg & (bit)), !!(aRaw##set [1].reg & (bit)) )); \
1805 } while (0)
1806#define CPUID_RAW_FEATURE_IGN(set, reg, bit) do { } while (0)
1807
1808 /* For checking guest features. */
1809#define CPUID_GST_FEATURE_RET(set, reg, bit) \
1810 do { \
1811 if ( (aGuestCpuId##set [1].reg & bit) \
1812 && !(aHostRaw##set [1].reg & bit) \
1813 && !(aHostOverride##set [1].reg & bit) \
1814 && !(aGuestOverride##set [1].reg & bit) \
1815 ) \
1816 { \
1817 if (fStrictCpuIdChecks) \
1818 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1819 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1820 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1821 } \
1822 } while (0)
1823#define CPUID_GST_FEATURE_WRN(set, reg, bit) \
1824 do { \
1825 if ( (aGuestCpuId##set [1].reg & bit) \
1826 && !(aHostRaw##set [1].reg & bit) \
1827 && !(aHostOverride##set [1].reg & bit) \
1828 && !(aGuestOverride##set [1].reg & bit) \
1829 ) \
1830 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1831 } while (0)
1832#define CPUID_GST_FEATURE_EMU(set, reg, bit) \
1833 do { \
1834 if ( (aGuestCpuId##set [1].reg & bit) \
1835 && !(aHostRaw##set [1].reg & bit) \
1836 && !(aHostOverride##set [1].reg & bit) \
1837 && !(aGuestOverride##set [1].reg & bit) \
1838 ) \
1839 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1840 } while (0)
1841#define CPUID_GST_FEATURE_IGN(set, reg, bit) do { } while (0)
1842
1843 /* For checking guest features if AMD guest CPU. */
1844#define CPUID_GST_AMD_FEATURE_RET(set, reg, bit) \
1845 do { \
1846 if ( (aGuestCpuId##set [1].reg & bit) \
1847 && fGuestAmd \
1848 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1849 && !(aHostOverride##set [1].reg & bit) \
1850 && !(aGuestOverride##set [1].reg & bit) \
1851 ) \
1852 { \
1853 if (fStrictCpuIdChecks) \
1854 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1855 N_(#bit " is not supported by the host but has already exposed to the guest")); \
1856 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1857 } \
1858 } while (0)
1859#define CPUID_GST_AMD_FEATURE_WRN(set, reg, bit) \
1860 do { \
1861 if ( (aGuestCpuId##set [1].reg & bit) \
1862 && fGuestAmd \
1863 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1864 && !(aHostOverride##set [1].reg & bit) \
1865 && !(aGuestOverride##set [1].reg & bit) \
1866 ) \
1867 LogRel(("CPUM: " #bit " is not supported by the host but has already exposed to the guest\n")); \
1868 } while (0)
1869#define CPUID_GST_AMD_FEATURE_EMU(set, reg, bit) \
1870 do { \
1871 if ( (aGuestCpuId##set [1].reg & bit) \
1872 && fGuestAmd \
1873 && (!fGuestAmd || !(aHostRaw##set [1].reg & bit)) \
1874 && !(aHostOverride##set [1].reg & bit) \
1875 && !(aGuestOverride##set [1].reg & bit) \
1876 ) \
1877 LogRel(("CPUM: Warning - " #bit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1878 } while (0)
1879#define CPUID_GST_AMD_FEATURE_IGN(set, reg, bit) do { } while (0)
1880
1881 /* For checking AMD features which have a corresponding bit in the standard
1882 range. (Intel defines very few bits in the extended feature sets.) */
1883#define CPUID_GST_FEATURE2_RET(reg, ExtBit, StdBit) \
1884 do { \
1885 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1886 && !(fHostAmd \
1887 ? aHostRawExt[1].reg & (ExtBit) \
1888 : aHostRawStd[1].reg & (StdBit)) \
1889 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1890 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1891 ) \
1892 { \
1893 if (fStrictCpuIdChecks) \
1894 return SSMR3SetLoadError(pSSM, VERR_SSM_LOAD_CPUID_MISMATCH, RT_SRC_POS, \
1895 N_(#ExtBit " is not supported by the host but has already exposed to the guest")); \
1896 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1897 } \
1898 } while (0)
1899#define CPUID_GST_FEATURE2_WRN(reg, ExtBit, StdBit) \
1900 do { \
1901 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1902 && !(fHostAmd \
1903 ? aHostRawExt[1].reg & (ExtBit) \
1904 : aHostRawStd[1].reg & (StdBit)) \
1905 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1906 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1907 ) \
1908 LogRel(("CPUM: " #ExtBit " is not supported by the host but has already exposed to the guest\n")); \
1909 } while (0)
1910#define CPUID_GST_FEATURE2_EMU(reg, ExtBit, StdBit) \
1911 do { \
1912 if ( (aGuestCpuIdExt [1].reg & (ExtBit)) \
1913 && !(fHostAmd \
1914 ? aHostRawExt[1].reg & (ExtBit) \
1915 : aHostRawStd[1].reg & (StdBit)) \
1916 && !(aHostOverrideExt[1].reg & (ExtBit)) \
1917 && !(aGuestOverrideExt[1].reg & (ExtBit)) \
1918 ) \
1919 LogRel(("CPUM: Warning - " #ExtBit " is not supported by the host but already exposed to the guest. This may impact performance.\n")); \
1920 } while (0)
1921#define CPUID_GST_FEATURE2_IGN(reg, ExtBit, StdBit) do { } while (0)
1922
1923 /*
1924 * Load them into stack buffers first.
1925 */
1926 CPUMCPUID aGuestCpuIdStd[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd)];
1927 uint32_t cGuestCpuIdStd;
1928 int rc = SSMR3GetU32(pSSM, &cGuestCpuIdStd); AssertRCReturn(rc, rc);
1929 if (cGuestCpuIdStd > RT_ELEMENTS(aGuestCpuIdStd))
1930 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1931 SSMR3GetMem(pSSM, &aGuestCpuIdStd[0], cGuestCpuIdStd * sizeof(aGuestCpuIdStd[0]));
1932
1933 CPUMCPUID aGuestCpuIdExt[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt)];
1934 uint32_t cGuestCpuIdExt;
1935 rc = SSMR3GetU32(pSSM, &cGuestCpuIdExt); AssertRCReturn(rc, rc);
1936 if (cGuestCpuIdExt > RT_ELEMENTS(aGuestCpuIdExt))
1937 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1938 SSMR3GetMem(pSSM, &aGuestCpuIdExt[0], cGuestCpuIdExt * sizeof(aGuestCpuIdExt[0]));
1939
1940 CPUMCPUID aGuestCpuIdCentaur[RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur)];
1941 uint32_t cGuestCpuIdCentaur;
1942 rc = SSMR3GetU32(pSSM, &cGuestCpuIdCentaur); AssertRCReturn(rc, rc);
1943 if (cGuestCpuIdCentaur > RT_ELEMENTS(aGuestCpuIdCentaur))
1944 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1945 SSMR3GetMem(pSSM, &aGuestCpuIdCentaur[0], cGuestCpuIdCentaur * sizeof(aGuestCpuIdCentaur[0]));
1946
1947 CPUMCPUID GuestCpuIdDef;
1948 rc = SSMR3GetMem(pSSM, &GuestCpuIdDef, sizeof(GuestCpuIdDef));
1949 AssertRCReturn(rc, rc);
1950
1951 CPUMCPUID aRawStd[16];
1952 uint32_t cRawStd;
1953 rc = SSMR3GetU32(pSSM, &cRawStd); AssertRCReturn(rc, rc);
1954 if (cRawStd > RT_ELEMENTS(aRawStd))
1955 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1956 SSMR3GetMem(pSSM, &aRawStd[0], cRawStd * sizeof(aRawStd[0]));
1957
1958 CPUMCPUID aRawExt[32];
1959 uint32_t cRawExt;
1960 rc = SSMR3GetU32(pSSM, &cRawExt); AssertRCReturn(rc, rc);
1961 if (cRawExt > RT_ELEMENTS(aRawExt))
1962 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1963 rc = SSMR3GetMem(pSSM, &aRawExt[0], cRawExt * sizeof(aRawExt[0]));
1964 AssertRCReturn(rc, rc);
1965
1966 /*
1967 * Note that we support restoring less than the current amount of standard
1968 * leaves because we've been allowed more is newer version of VBox.
1969 *
1970 * So, pad new entries with the default.
1971 */
1972 for (uint32_t i = cGuestCpuIdStd; i < RT_ELEMENTS(aGuestCpuIdStd); i++)
1973 aGuestCpuIdStd[i] = GuestCpuIdDef;
1974
1975 for (uint32_t i = cGuestCpuIdExt; i < RT_ELEMENTS(aGuestCpuIdExt); i++)
1976 aGuestCpuIdExt[i] = GuestCpuIdDef;
1977
1978 for (uint32_t i = cGuestCpuIdCentaur; i < RT_ELEMENTS(aGuestCpuIdCentaur); i++)
1979 aGuestCpuIdCentaur[i] = GuestCpuIdDef;
1980
1981 for (uint32_t i = cRawStd; i < RT_ELEMENTS(aRawStd); i++)
1982 ASMCpuId(i, &aRawStd[i].eax, &aRawStd[i].ebx, &aRawStd[i].ecx, &aRawStd[i].edx);
1983
1984 for (uint32_t i = cRawExt; i < RT_ELEMENTS(aRawExt); i++)
1985 ASMCpuId(i | UINT32_C(0x80000000), &aRawExt[i].eax, &aRawExt[i].ebx, &aRawExt[i].ecx, &aRawExt[i].edx);
1986
1987 /*
1988 * Get the raw CPU IDs for the current host.
1989 */
1990 CPUMCPUID aHostRawStd[16];
1991 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawStd); i++)
1992 ASMCpuId(i, &aHostRawStd[i].eax, &aHostRawStd[i].ebx, &aHostRawStd[i].ecx, &aHostRawStd[i].edx);
1993
1994 CPUMCPUID aHostRawExt[32];
1995 for (unsigned i = 0; i < RT_ELEMENTS(aHostRawExt); i++)
1996 ASMCpuId(i | UINT32_C(0x80000000), &aHostRawExt[i].eax, &aHostRawExt[i].ebx, &aHostRawExt[i].ecx, &aHostRawExt[i].edx);
1997
1998 /*
1999 * Get the host and guest overrides so we don't reject the state because
2000 * some feature was enabled thru these interfaces.
2001 * Note! We currently only need the feature leaves, so skip rest.
2002 */
2003 PCFGMNODE pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/CPUID");
2004 CPUMCPUID aGuestOverrideStd[2];
2005 memcpy(&aGuestOverrideStd[0], &aHostRawStd[0], sizeof(aGuestOverrideStd));
2006 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aGuestOverrideStd[0], RT_ELEMENTS(aGuestOverrideStd), pOverrideCfg);
2007
2008 CPUMCPUID aGuestOverrideExt[2];
2009 memcpy(&aGuestOverrideExt[0], &aHostRawExt[0], sizeof(aGuestOverrideExt));
2010 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aGuestOverrideExt[0], RT_ELEMENTS(aGuestOverrideExt), pOverrideCfg);
2011
2012 pOverrideCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/HostCPUID");
2013 CPUMCPUID aHostOverrideStd[2];
2014 memcpy(&aHostOverrideStd[0], &aHostRawStd[0], sizeof(aHostOverrideStd));
2015 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x00000000), &aHostOverrideStd[0], RT_ELEMENTS(aHostOverrideStd), pOverrideCfg);
2016
2017 CPUMCPUID aHostOverrideExt[2];
2018 memcpy(&aHostOverrideExt[0], &aHostRawExt[0], sizeof(aHostOverrideExt));
2019 cpumR3CpuIdInitLoadOverrideSet(UINT32_C(0x80000000), &aHostOverrideExt[0], RT_ELEMENTS(aHostOverrideExt), pOverrideCfg);
2020
2021 /*
2022 * This can be skipped.
2023 */
2024 bool fStrictCpuIdChecks;
2025 CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "StrictCpuIdChecks", &fStrictCpuIdChecks, true);
2026
2027
2028
2029 /*
2030 * For raw-mode we'll require that the CPUs are very similar since we don't
2031 * intercept CPUID instructions for user mode applications.
2032 */
2033 if (!HMIsEnabled(pVM))
2034 {
2035 /* CPUID(0) */
2036 CPUID_CHECK_RET( aHostRawStd[0].ebx == aRawStd[0].ebx
2037 && aHostRawStd[0].ecx == aRawStd[0].ecx
2038 && aHostRawStd[0].edx == aRawStd[0].edx,
2039 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2040 &aHostRawStd[0].ebx, &aHostRawStd[0].edx, &aHostRawStd[0].ecx,
2041 &aRawStd[0].ebx, &aRawStd[0].edx, &aRawStd[0].ecx));
2042 CPUID_CHECK2_WRN("Std CPUID max leaf", aHostRawStd[0].eax, aRawStd[0].eax);
2043 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3);
2044 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2045
2046 bool const fIntel = ASMIsIntelCpuEx(aRawStd[0].ebx, aRawStd[0].ecx, aRawStd[0].edx);
2047
2048 /* CPUID(1).eax */
2049 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawStd[1].eax), ASMGetCpuFamily(aRawStd[1].eax));
2050 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawStd[1].eax, fIntel), ASMGetCpuModel(aRawStd[1].eax, fIntel));
2051 CPUID_CHECK2_WRN("CPU type", (aHostRawStd[1].eax >> 12) & 3, (aRawStd[1].eax >> 12) & 3 );
2052
2053 /* CPUID(1).ebx - completely ignore CPU count and APIC ID. */
2054 CPUID_CHECK2_RET("CPU brand ID", aHostRawStd[1].ebx & 0xff, aRawStd[1].ebx & 0xff);
2055 CPUID_CHECK2_WRN("CLFLUSH chunk count", (aHostRawStd[1].ebx >> 8) & 0xff, (aRawStd[1].ebx >> 8) & 0xff);
2056
2057 /* CPUID(1).ecx */
2058 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3);
2059 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL);
2060 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64);
2061 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2062 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS);
2063 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_VMX);
2064 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_SMX);
2065 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_EST);
2066 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TM2);
2067 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3);
2068 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID);
2069 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2070 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA);
2071 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16);
2072 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);
2073 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM);
2074 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2075 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2076 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_DCA);
2077 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1);
2078 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2);
2079 CPUID_RAW_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2080 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE);
2081 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT);
2082 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2083 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES);
2084 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE);
2085 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE);
2086 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX);
2087 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2088 CPUID_RAW_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2089 CPUID_RAW_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_HVP);
2090
2091 /* CPUID(1).edx */
2092 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2093 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2094 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE);
2095 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2096 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC);
2097 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR);
2098 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2099 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2100 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8);
2101 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2102 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2103 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2104 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2105 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2106 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2107 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV);
2108 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2109 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2110 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2111 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH);
2112 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2113 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_DS);
2114 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_ACPI);
2115 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX);
2116 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR);
2117 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE);
2118 CPUID_RAW_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2);
2119 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SS);
2120 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_HTT);
2121 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_TM);
2122 CPUID_RAW_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/);
2123 CPUID_RAW_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PBE);
2124
2125 /* CPUID(2) - config, mostly about caches. ignore. */
2126 /* CPUID(3) - processor serial number. ignore. */
2127 /* CPUID(4) - config, cache and topology - takes ECX as input. ignore. */
2128 /* CPUID(5) - mwait/monitor config. ignore. */
2129 /* CPUID(6) - power management. ignore. */
2130 /* CPUID(7) - ???. ignore. */
2131 /* CPUID(8) - ???. ignore. */
2132 /* CPUID(9) - DCA. ignore for now. */
2133 /* CPUID(a) - PeMo info. ignore for now. */
2134 /* CPUID(b) - topology info - takes ECX as input. ignore. */
2135
2136 /* CPUID(d) - XCR0 stuff - takes ECX as input. We only warn about the main level (ECX=0) for now. */
2137 CPUID_CHECK_WRN( aRawStd[0].eax < UINT32_C(0x0000000d)
2138 || aHostRawStd[0].eax >= UINT32_C(0x0000000d),
2139 ("CPUM: Standard leaf D was present on saved state host, not present on current.\n"));
2140 if ( aRawStd[0].eax >= UINT32_C(0x0000000d)
2141 && aHostRawStd[0].eax >= UINT32_C(0x0000000d))
2142 {
2143 CPUID_CHECK2_WRN("Valid low XCR0 bits", aHostRawStd[0xd].eax, aRawStd[0xd].eax);
2144 CPUID_CHECK2_WRN("Valid high XCR0 bits", aHostRawStd[0xd].edx, aRawStd[0xd].edx);
2145 CPUID_CHECK2_WRN("Current XSAVE/XRSTOR area size", aHostRawStd[0xd].ebx, aRawStd[0xd].ebx);
2146 CPUID_CHECK2_WRN("Max XSAVE/XRSTOR area size", aHostRawStd[0xd].ecx, aRawStd[0xd].ecx);
2147 }
2148
2149 /* CPUID(0x80000000) - same as CPUID(0) except for eax.
2150 Note! Intel have/is marking many of the fields here as reserved. We
2151 will verify them as if it's an AMD CPU. */
2152 CPUID_CHECK_RET( (aHostRawExt[0].eax >= UINT32_C(0x80000001) && aHostRawExt[0].eax <= UINT32_C(0x8000007f))
2153 || !(aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f)),
2154 (N_("Extended leaves was present on saved state host, but is missing on the current\n")));
2155 if (aRawExt[0].eax >= UINT32_C(0x80000001) && aRawExt[0].eax <= UINT32_C(0x8000007f))
2156 {
2157 CPUID_CHECK_RET( aHostRawExt[0].ebx == aRawExt[0].ebx
2158 && aHostRawExt[0].ecx == aRawExt[0].ecx
2159 && aHostRawExt[0].edx == aRawExt[0].edx,
2160 (N_("CPU vendor mismatch: host='%.4s%.4s%.4s' saved='%.4s%.4s%.4s'"),
2161 &aHostRawExt[0].ebx, &aHostRawExt[0].edx, &aHostRawExt[0].ecx,
2162 &aRawExt[0].ebx, &aRawExt[0].edx, &aRawExt[0].ecx));
2163 CPUID_CHECK2_WRN("Ext CPUID max leaf", aHostRawExt[0].eax, aRawExt[0].eax);
2164
2165 /* CPUID(0x80000001).eax - same as CPUID(0).eax. */
2166 CPUID_CHECK2_RET("CPU family", ASMGetCpuFamily(aHostRawExt[1].eax), ASMGetCpuFamily(aRawExt[1].eax));
2167 CPUID_CHECK2_RET("CPU model", ASMGetCpuModel(aHostRawExt[1].eax, fIntel), ASMGetCpuModel(aRawExt[1].eax, fIntel));
2168 CPUID_CHECK2_WRN("CPU type", (aHostRawExt[1].eax >> 12) & 3, (aRawExt[1].eax >> 12) & 3 );
2169 CPUID_CHECK2_WRN("Reserved bits 15:14", (aHostRawExt[1].eax >> 14) & 3, (aRawExt[1].eax >> 14) & 3 );
2170 CPUID_CHECK2_WRN("Reserved bits 31:28", aHostRawExt[1].eax >> 28, aRawExt[1].eax >> 28);
2171
2172 /* CPUID(0x80000001).ebx - Brand ID (maybe), just warn if things differs. */
2173 CPUID_CHECK2_WRN("CPU BrandID", aHostRawExt[1].ebx & 0xffff, aRawExt[1].ebx & 0xffff);
2174 CPUID_CHECK2_WRN("Reserved bits 16:27", (aHostRawExt[1].ebx >> 16) & 0xfff, (aRawExt[1].ebx >> 16) & 0xfff);
2175 CPUID_CHECK2_WRN("PkgType", (aHostRawExt[1].ebx >> 28) & 0xf, (aRawExt[1].ebx >> 28) & 0xf);
2176
2177 /* CPUID(0x80000001).ecx */
2178 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF);
2179 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL);
2180 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM);
2181 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);
2182 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L);
2183 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM);
2184 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A);
2185 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);
2186 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);
2187 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW);
2188 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS);
2189 CPUID_RAW_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5);
2190 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT);
2191 CPUID_RAW_FEATURE_IGN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT);
2192 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2193 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2194 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2195 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2196 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2197 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2198 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2199 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2200 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2201 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2202 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2203 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2204 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2205 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2206 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2207 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2208 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2209 CPUID_RAW_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2210
2211 /* CPUID(0x80000001).edx */
2212 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FPU);
2213 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_VME);
2214 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_DE);
2215 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE);
2216 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_TSC);
2217 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MSR);
2218 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAE);
2219 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCE);
2220 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CX8);
2221 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_APIC);
2222 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2223 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SEP);
2224 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MTRR);
2225 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PGE);
2226 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MCA);
2227 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_CMOV);
2228 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PAT);
2229 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_PSE36);
2230 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2231 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2232 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2233 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(21) /*reserved*/);
2234 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2235 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_MMX);
2236 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FXSR);
2237 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2238 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2239 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2240 CPUID_RAW_FEATURE_IGN(Ext, edx, RT_BIT_32(28) /*reserved*/);
2241 CPUID_RAW_FEATURE_IGN(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2242 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2243 CPUID_RAW_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2244
2245 /** @todo verify the rest as well. */
2246 }
2247 }
2248
2249
2250
2251 /*
2252 * Verify that we can support the features already exposed to the guest on
2253 * this host.
2254 *
2255 * Most of the features we're emulating requires intercepting instruction
2256 * and doing it the slow way, so there is no need to warn when they aren't
2257 * present in the host CPU. Thus we use IGN instead of EMU on these.
2258 *
2259 * Trailing comments:
2260 * "EMU" - Possible to emulate, could be lots of work and very slow.
2261 * "EMU?" - Can this be emulated?
2262 */
2263 /* CPUID(1).ecx */
2264 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE3); // -> EMU
2265 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PCLMUL); // -> EMU?
2266 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DTES64); // -> EMU?
2267 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_MONITOR);
2268 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CPLDS); // -> EMU?
2269 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_VMX); // -> EMU
2270 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SMX); // -> EMU
2271 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_EST); // -> EMU
2272 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TM2); // -> EMU?
2273 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSSE3); // -> EMU
2274 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CNTXID); // -> EMU
2275 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(11) /*reserved*/ );
2276 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_FMA); // -> EMU? what's this?
2277 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_CX16); // -> EMU?
2278 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_TPRUPDATE);//-> EMU
2279 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_PDCM); // -> EMU
2280 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(16) /*reserved*/);
2281 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(17) /*reserved*/);
2282 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_DCA); // -> EMU?
2283 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_1); // -> EMU
2284 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_SSE4_2); // -> EMU
2285 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_X2APIC);
2286 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_MOVBE); // -> EMU
2287 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_POPCNT); // -> EMU
2288 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(24) /*reserved*/);
2289 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AES); // -> EMU
2290 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_XSAVE); // -> EMU
2291 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_OSXSAVE); // -> EMU
2292 CPUID_GST_FEATURE_RET(Std, ecx, X86_CPUID_FEATURE_ECX_AVX); // -> EMU?
2293 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(29) /*reserved*/);
2294 CPUID_GST_FEATURE_RET(Std, ecx, RT_BIT_32(30) /*reserved*/);
2295 CPUID_GST_FEATURE_IGN(Std, ecx, X86_CPUID_FEATURE_ECX_HVP); // Normally not set by host
2296
2297 /* CPUID(1).edx */
2298 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FPU);
2299 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_VME);
2300 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DE); // -> EMU?
2301 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE);
2302 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2303 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2304 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PAE);
2305 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCE);
2306 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2307 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_APIC);
2308 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(10) /*reserved*/);
2309 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_SEP);
2310 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MTRR);
2311 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PGE);
2312 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_MCA);
2313 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2314 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PAT);
2315 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSE36);
2316 CPUID_GST_FEATURE_IGN(Std, edx, X86_CPUID_FEATURE_EDX_PSN);
2317 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_CLFSH); // -> EMU
2318 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(20) /*reserved*/);
2319 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_DS); // -> EMU?
2320 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_ACPI); // -> EMU?
2321 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2322 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2323 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE); // -> EMU
2324 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SSE2); // -> EMU
2325 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_SS); // -> EMU?
2326 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_HTT); // -> EMU?
2327 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_TM); // -> EMU?
2328 CPUID_GST_FEATURE_RET(Std, edx, RT_BIT_32(30) /*JMPE/IA64*/); // -> EMU
2329 CPUID_GST_FEATURE_RET(Std, edx, X86_CPUID_FEATURE_EDX_PBE); // -> EMU?
2330
2331 /* CPUID(0x80000000). */
2332 if ( aGuestCpuIdExt[0].eax >= UINT32_C(0x80000001)
2333 && aGuestCpuIdExt[0].eax < UINT32_C(0x8000007f))
2334 {
2335 /** @todo deal with no 0x80000001 on the host. */
2336 bool const fHostAmd = ASMIsAmdCpuEx(aHostRawStd[0].ebx, aHostRawStd[0].ecx, aHostRawStd[0].edx);
2337 bool const fGuestAmd = ASMIsAmdCpuEx(aGuestCpuIdExt[0].ebx, aGuestCpuIdExt[0].ecx, aGuestCpuIdExt[0].edx);
2338
2339 /* CPUID(0x80000001).ecx */
2340 CPUID_GST_FEATURE_WRN(Ext, ecx, X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF); // -> EMU
2341 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CMPL); // -> EMU
2342 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SVM); // -> EMU
2343 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_EXT_APIC);// ???
2344 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_CR8L); // -> EMU
2345 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_ABM); // -> EMU
2346 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE4A); // -> EMU
2347 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_MISALNSSE);//-> EMU
2348 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF);// -> EMU
2349 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_OSVW); // -> EMU?
2350 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_IBS); // -> EMU
2351 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SSE5); // -> EMU
2352 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_SKINIT); // -> EMU
2353 CPUID_GST_AMD_FEATURE_RET(Ext, ecx, X86_CPUID_AMD_FEATURE_ECX_WDT); // -> EMU
2354 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(14));
2355 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(15));
2356 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(16));
2357 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(17));
2358 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(18));
2359 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(19));
2360 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(20));
2361 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(21));
2362 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(22));
2363 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(23));
2364 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(24));
2365 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(25));
2366 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(26));
2367 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(27));
2368 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(28));
2369 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(29));
2370 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(30));
2371 CPUID_GST_AMD_FEATURE_WRN(Ext, ecx, RT_BIT_32(31));
2372
2373 /* CPUID(0x80000001).edx */
2374 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FPU, X86_CPUID_FEATURE_EDX_FPU); // -> EMU
2375 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_VME, X86_CPUID_FEATURE_EDX_VME); // -> EMU
2376 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_DE, X86_CPUID_FEATURE_EDX_DE); // -> EMU
2377 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE, X86_CPUID_FEATURE_EDX_PSE);
2378 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_TSC, X86_CPUID_FEATURE_EDX_TSC); // -> EMU
2379 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MSR, X86_CPUID_FEATURE_EDX_MSR); // -> EMU
2380 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_PAE, X86_CPUID_FEATURE_EDX_PAE);
2381 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCE, X86_CPUID_FEATURE_EDX_MCE);
2382 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CX8, X86_CPUID_FEATURE_EDX_CX8); // -> EMU?
2383 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_APIC, X86_CPUID_FEATURE_EDX_APIC);
2384 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(10) /*reserved*/);
2385 CPUID_GST_FEATURE_IGN( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_SYSCALL); // On Intel: long mode only.
2386 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MTRR, X86_CPUID_FEATURE_EDX_MTRR);
2387 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PGE, X86_CPUID_FEATURE_EDX_PGE);
2388 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_MCA, X86_CPUID_FEATURE_EDX_MCA);
2389 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_CMOV, X86_CPUID_FEATURE_EDX_CMOV); // -> EMU
2390 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PAT, X86_CPUID_FEATURE_EDX_PAT);
2391 CPUID_GST_FEATURE2_IGN( edx, X86_CPUID_AMD_FEATURE_EDX_PSE36, X86_CPUID_FEATURE_EDX_PSE36);
2392 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(18) /*reserved*/);
2393 CPUID_GST_AMD_FEATURE_WRN(Ext, edx, RT_BIT_32(19) /*reserved*/);
2394 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_NX);
2395 CPUID_GST_FEATURE_WRN( Ext, edx, RT_BIT_32(21) /*reserved*/);
2396 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_AMD_FEATURE_EDX_AXMMX);
2397 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_MMX, X86_CPUID_FEATURE_EDX_MMX); // -> EMU
2398 CPUID_GST_FEATURE2_RET( edx, X86_CPUID_AMD_FEATURE_EDX_FXSR, X86_CPUID_FEATURE_EDX_FXSR); // -> EMU
2399 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_FFXSR);
2400 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_PAGE1GB);
2401 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_EXT_FEATURE_EDX_RDTSCP);
2402 CPUID_GST_FEATURE_IGN( Ext, edx, RT_BIT_32(28) /*reserved*/);
2403 CPUID_GST_FEATURE_RET( Ext, edx, X86_CPUID_EXT_FEATURE_EDX_LONG_MODE);
2404 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX);
2405 CPUID_GST_AMD_FEATURE_RET(Ext, edx, X86_CPUID_AMD_FEATURE_EDX_3DNOW);
2406 }
2407
2408 /*
2409 * We're good, commit the CPU ID leaves.
2410 */
2411 memcpy(&pVM->cpum.s.aGuestCpuIdStd[0], &aGuestCpuIdStd[0], sizeof(aGuestCpuIdStd));
2412 memcpy(&pVM->cpum.s.aGuestCpuIdExt[0], &aGuestCpuIdExt[0], sizeof(aGuestCpuIdExt));
2413 memcpy(&pVM->cpum.s.aGuestCpuIdCentaur[0], &aGuestCpuIdCentaur[0], sizeof(aGuestCpuIdCentaur));
2414 pVM->cpum.s.GuestCpuIdDef = GuestCpuIdDef;
2415
2416#undef CPUID_CHECK_RET
2417#undef CPUID_CHECK_WRN
2418#undef CPUID_CHECK2_RET
2419#undef CPUID_CHECK2_WRN
2420#undef CPUID_RAW_FEATURE_RET
2421#undef CPUID_RAW_FEATURE_WRN
2422#undef CPUID_RAW_FEATURE_IGN
2423#undef CPUID_GST_FEATURE_RET
2424#undef CPUID_GST_FEATURE_WRN
2425#undef CPUID_GST_FEATURE_EMU
2426#undef CPUID_GST_FEATURE_IGN
2427#undef CPUID_GST_FEATURE2_RET
2428#undef CPUID_GST_FEATURE2_WRN
2429#undef CPUID_GST_FEATURE2_EMU
2430#undef CPUID_GST_FEATURE2_IGN
2431#undef CPUID_GST_AMD_FEATURE_RET
2432#undef CPUID_GST_AMD_FEATURE_WRN
2433#undef CPUID_GST_AMD_FEATURE_EMU
2434#undef CPUID_GST_AMD_FEATURE_IGN
2435
2436 return VINF_SUCCESS;
2437}
2438
2439
2440/**
2441 * Pass 0 live exec callback.
2442 *
2443 * @returns VINF_SSM_DONT_CALL_AGAIN.
2444 * @param pVM Pointer to the VM.
2445 * @param pSSM The saved state handle.
2446 * @param uPass The pass (0).
2447 */
2448static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2449{
2450 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2451 cpumR3SaveCpuId(pVM, pSSM);
2452 return VINF_SSM_DONT_CALL_AGAIN;
2453}
2454
2455
2456/**
2457 * Execute state save operation.
2458 *
2459 * @returns VBox status code.
2460 * @param pVM Pointer to the VM.
2461 * @param pSSM SSM operation handle.
2462 */
2463static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2464{
2465 /*
2466 * Save.
2467 */
2468 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2469 {
2470 PVMCPU pVCpu = &pVM->aCpus[i];
2471 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2472 }
2473
2474 SSMR3PutU32(pSSM, pVM->cCpus);
2475 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2476 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2477 {
2478 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2479
2480 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), 0, g_aCpumCtxFields, NULL);
2481 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2482 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2483 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2484 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2485 }
2486
2487 cpumR3SaveCpuId(pVM, pSSM);
2488 return VINF_SUCCESS;
2489}
2490
2491
2492/**
2493 * @copydoc FNSSMINTLOADPREP
2494 */
2495static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2496{
2497 NOREF(pSSM);
2498 pVM->cpum.s.fPendingRestore = true;
2499 return VINF_SUCCESS;
2500}
2501
2502
2503/**
2504 * @copydoc FNSSMINTLOADEXEC
2505 */
2506static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2507{
2508 /*
2509 * Validate version.
2510 */
2511 if ( uVersion != CPUM_SAVED_STATE_VERSION
2512 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
2513 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2514 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2515 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2516 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2517 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2518 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2519 {
2520 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2521 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2522 }
2523
2524 if (uPass == SSM_PASS_FINAL)
2525 {
2526 /*
2527 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2528 * really old SSM file versions.)
2529 */
2530 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2531 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2532 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2533 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2534
2535 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2536 PCSSMFIELD paCpumCtxFields = g_aCpumCtxFields;
2537 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2538 paCpumCtxFields = g_aCpumCtxFieldsV16;
2539 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2540 paCpumCtxFields = g_aCpumCtxFieldsMem;
2541
2542 /*
2543 * Restore.
2544 */
2545 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2546 {
2547 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2548 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2549 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2550 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), fLoad, paCpumCtxFields, NULL);
2551 pVCpu->cpum.s.Hyper.cr3 = uCR3;
2552 pVCpu->cpum.s.Hyper.rsp = uRSP;
2553 }
2554
2555 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2556 {
2557 uint32_t cCpus;
2558 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2559 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2560 VERR_SSM_UNEXPECTED_DATA);
2561 }
2562 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2563 || pVM->cCpus == 1,
2564 ("cCpus=%u\n", pVM->cCpus),
2565 VERR_SSM_UNEXPECTED_DATA);
2566
2567 uint32_t cbMsrs = 0;
2568 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2569 {
2570 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2571 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2572 VERR_SSM_UNEXPECTED_DATA);
2573 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2574 VERR_SSM_UNEXPECTED_DATA);
2575 }
2576
2577 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2578 {
2579 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2580 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest), fLoad,
2581 paCpumCtxFields, NULL);
2582 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2583 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2584 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2585 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2586 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2587 {
2588 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2589 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2590 }
2591
2592 /* REM and other may have cleared must-be-one fields in DR6 and
2593 DR7, fix these. */
2594 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
2595 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
2596 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
2597 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
2598 }
2599
2600 /* Older states does not have the internal selector register flags
2601 and valid selector value. Supply those. */
2602 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2603 {
2604 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2605 {
2606 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2607 bool const fValid = HMIsEnabled(pVM)
2608 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2609 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2610 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2611 if (fValid)
2612 {
2613 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2614 {
2615 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2616 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2617 }
2618
2619 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2620 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2621 }
2622 else
2623 {
2624 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2625 {
2626 paSelReg[iSelReg].fFlags = 0;
2627 paSelReg[iSelReg].ValidSel = 0;
2628 }
2629
2630 /* This might not be 104% correct, but I think it's close
2631 enough for all practical purposes... (REM always loaded
2632 LDTR registers.) */
2633 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2634 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2635 }
2636 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2637 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2638 }
2639 }
2640
2641 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2642 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2643 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2644 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2645 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2646
2647 /*
2648 * A quick sanity check.
2649 */
2650 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2651 {
2652 PVMCPU pVCpu = &pVM->aCpus[iCpu];
2653 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2654 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2655 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2656 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2657 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2658 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2659 }
2660 }
2661
2662 pVM->cpum.s.fPendingRestore = false;
2663
2664 /*
2665 * Guest CPUIDs.
2666 */
2667 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
2668 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2669
2670 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
2671 * actually required. */
2672
2673 /*
2674 * Restore the CPUID leaves.
2675 *
2676 * Note that we support restoring less than the current amount of standard
2677 * leaves because we've been allowed more is newer version of VBox.
2678 */
2679 uint32_t cElements;
2680 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2681 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
2682 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2683 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdStd[0]));
2684
2685 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2686 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
2687 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2688 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
2689
2690 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
2691 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
2692 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2693 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
2694
2695 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
2696
2697 /*
2698 * Check that the basic cpuid id information is unchanged.
2699 */
2700 /** @todo we should check the 64 bits capabilities too! */
2701 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
2702 ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
2703 ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
2704 uint32_t au32CpuIdSaved[8];
2705 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
2706 if (RT_SUCCESS(rc))
2707 {
2708 /* Ignore CPU stepping. */
2709 au32CpuId[4] &= 0xfffffff0;
2710 au32CpuIdSaved[4] &= 0xfffffff0;
2711
2712 /* Ignore APIC ID (AMD specs). */
2713 au32CpuId[5] &= ~0xff000000;
2714 au32CpuIdSaved[5] &= ~0xff000000;
2715
2716 /* Ignore the number of Logical CPUs (AMD specs). */
2717 au32CpuId[5] &= ~0x00ff0000;
2718 au32CpuIdSaved[5] &= ~0x00ff0000;
2719
2720 /* Ignore some advanced capability bits, that we don't expose to the guest. */
2721 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2722 | X86_CPUID_FEATURE_ECX_VMX
2723 | X86_CPUID_FEATURE_ECX_SMX
2724 | X86_CPUID_FEATURE_ECX_EST
2725 | X86_CPUID_FEATURE_ECX_TM2
2726 | X86_CPUID_FEATURE_ECX_CNTXID
2727 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2728 | X86_CPUID_FEATURE_ECX_PDCM
2729 | X86_CPUID_FEATURE_ECX_DCA
2730 | X86_CPUID_FEATURE_ECX_X2APIC
2731 );
2732 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
2733 | X86_CPUID_FEATURE_ECX_VMX
2734 | X86_CPUID_FEATURE_ECX_SMX
2735 | X86_CPUID_FEATURE_ECX_EST
2736 | X86_CPUID_FEATURE_ECX_TM2
2737 | X86_CPUID_FEATURE_ECX_CNTXID
2738 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2739 | X86_CPUID_FEATURE_ECX_PDCM
2740 | X86_CPUID_FEATURE_ECX_DCA
2741 | X86_CPUID_FEATURE_ECX_X2APIC
2742 );
2743
2744 /* Make sure we don't forget to update the masks when enabling
2745 * features in the future.
2746 */
2747 AssertRelease(!(pVM->cpum.s.aGuestCpuIdStd[1].ecx &
2748 ( X86_CPUID_FEATURE_ECX_DTES64
2749 | X86_CPUID_FEATURE_ECX_VMX
2750 | X86_CPUID_FEATURE_ECX_SMX
2751 | X86_CPUID_FEATURE_ECX_EST
2752 | X86_CPUID_FEATURE_ECX_TM2
2753 | X86_CPUID_FEATURE_ECX_CNTXID
2754 | X86_CPUID_FEATURE_ECX_TPRUPDATE
2755 | X86_CPUID_FEATURE_ECX_PDCM
2756 | X86_CPUID_FEATURE_ECX_DCA
2757 | X86_CPUID_FEATURE_ECX_X2APIC
2758 )));
2759 /* do the compare */
2760 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
2761 {
2762 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
2763 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
2764 "Saved=%.*Rhxs\n"
2765 "Real =%.*Rhxs\n",
2766 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2767 sizeof(au32CpuId), au32CpuId));
2768 else
2769 {
2770 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
2771 "Saved=%.*Rhxs\n"
2772 "Real =%.*Rhxs\n",
2773 sizeof(au32CpuIdSaved), au32CpuIdSaved,
2774 sizeof(au32CpuId), au32CpuId));
2775 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
2776 }
2777 }
2778 }
2779
2780 return rc;
2781}
2782
2783
2784/**
2785 * @copydoc FNSSMINTLOADPREP
2786 */
2787static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2788{
2789 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2790 return VINF_SUCCESS;
2791
2792 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2793 if (pVM->cpum.s.fPendingRestore)
2794 {
2795 LogRel(("CPUM: Missing state!\n"));
2796 return VERR_INTERNAL_ERROR_2;
2797 }
2798
2799 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2800 {
2801 /* Notify PGM of the NXE states in case they've changed. */
2802 PGMNotifyNxeChanged(&pVM->aCpus[iCpu], !!(pVM->aCpus[iCpu].cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2803
2804 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
2805 PDMApicGetBase(&pVM->aCpus[iCpu], &pVM->aCpus[iCpu].cpum.s.Guest.msrApicBase);
2806 }
2807 return VINF_SUCCESS;
2808}
2809
2810
2811/**
2812 * Checks if the CPUM state restore is still pending.
2813 *
2814 * @returns true / false.
2815 * @param pVM Pointer to the VM.
2816 */
2817VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2818{
2819 return pVM->cpum.s.fPendingRestore;
2820}
2821
2822
2823/**
2824 * Formats the EFLAGS value into mnemonics.
2825 *
2826 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2827 * @param efl The EFLAGS value.
2828 */
2829static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2830{
2831 /*
2832 * Format the flags.
2833 */
2834 static const struct
2835 {
2836 const char *pszSet; const char *pszClear; uint32_t fFlag;
2837 } s_aFlags[] =
2838 {
2839 { "vip",NULL, X86_EFL_VIP },
2840 { "vif",NULL, X86_EFL_VIF },
2841 { "ac", NULL, X86_EFL_AC },
2842 { "vm", NULL, X86_EFL_VM },
2843 { "rf", NULL, X86_EFL_RF },
2844 { "nt", NULL, X86_EFL_NT },
2845 { "ov", "nv", X86_EFL_OF },
2846 { "dn", "up", X86_EFL_DF },
2847 { "ei", "di", X86_EFL_IF },
2848 { "tf", NULL, X86_EFL_TF },
2849 { "nt", "pl", X86_EFL_SF },
2850 { "nz", "zr", X86_EFL_ZF },
2851 { "ac", "na", X86_EFL_AF },
2852 { "po", "pe", X86_EFL_PF },
2853 { "cy", "nc", X86_EFL_CF },
2854 };
2855 char *psz = pszEFlags;
2856 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2857 {
2858 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2859 if (pszAdd)
2860 {
2861 strcpy(psz, pszAdd);
2862 psz += strlen(pszAdd);
2863 *psz++ = ' ';
2864 }
2865 }
2866 psz[-1] = '\0';
2867}
2868
2869
2870/**
2871 * Formats a full register dump.
2872 *
2873 * @param pVM Pointer to the VM.
2874 * @param pCtx The context to format.
2875 * @param pCtxCore The context core to format.
2876 * @param pHlp Output functions.
2877 * @param enmType The dump type.
2878 * @param pszPrefix Register name prefix.
2879 */
2880static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2881 const char *pszPrefix)
2882{
2883 NOREF(pVM);
2884
2885 /*
2886 * Format the EFLAGS.
2887 */
2888 uint32_t efl = pCtxCore->eflags.u32;
2889 char szEFlags[80];
2890 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2891
2892 /*
2893 * Format the registers.
2894 */
2895 switch (enmType)
2896 {
2897 case CPUMDUMPTYPE_TERSE:
2898 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2899 pHlp->pfnPrintf(pHlp,
2900 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2901 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2902 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2903 "%sr14=%016RX64 %sr15=%016RX64\n"
2904 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2905 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2906 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2907 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2908 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2909 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2910 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2911 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2912 else
2913 pHlp->pfnPrintf(pHlp,
2914 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2915 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2916 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2917 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2918 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2919 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2920 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2921 break;
2922
2923 case CPUMDUMPTYPE_DEFAULT:
2924 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2925 pHlp->pfnPrintf(pHlp,
2926 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2927 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2928 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2929 "%sr14=%016RX64 %sr15=%016RX64\n"
2930 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2931 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2932 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2933 ,
2934 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2935 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2936 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2937 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2938 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2939 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2940 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2941 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2942 else
2943 pHlp->pfnPrintf(pHlp,
2944 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2945 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2946 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2947 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2948 ,
2949 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2950 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2951 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2952 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2953 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2954 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2955 break;
2956
2957 case CPUMDUMPTYPE_VERBOSE:
2958 if (CPUMIsGuestIn64BitCodeEx(pCtx))
2959 pHlp->pfnPrintf(pHlp,
2960 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2961 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2962 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2963 "%sr14=%016RX64 %sr15=%016RX64\n"
2964 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2965 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2966 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2967 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2968 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2969 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2970 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2971 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2972 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2973 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2974 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2975 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2976 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2977 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2978 ,
2979 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2980 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2981 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2982 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2983 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2984 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2985 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2986 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2987 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2988 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2989 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2990 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2991 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2992 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2993 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2994 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2995 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2996 else
2997 pHlp->pfnPrintf(pHlp,
2998 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2999 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3000 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3001 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3002 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3003 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3004 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3005 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3006 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3007 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3008 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3009 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3010 ,
3011 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3012 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3013 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3014 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3015 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3016 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3017 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3018 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3019 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3020 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3021 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3022 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3023
3024 pHlp->pfnPrintf(pHlp,
3025 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3026 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3027 ,
3028 pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW, pszPrefix, pCtx->fpu.FOP,
3029 pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK,
3030 pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsrvd1,
3031 pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2
3032 );
3033 unsigned iShift = (pCtx->fpu.FSW >> 11) & 7;
3034 for (unsigned iST = 0; iST < RT_ELEMENTS(pCtx->fpu.aRegs); iST++)
3035 {
3036 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pCtx->fpu.aRegs);
3037 unsigned uTag = pCtx->fpu.FTW & (1 << iFPR) ? 1 : 0;
3038 char chSign = pCtx->fpu.aRegs[0].au16[4] & 0x8000 ? '-' : '+';
3039 unsigned iInteger = (unsigned)(pCtx->fpu.aRegs[0].au64[0] >> 63);
3040 uint64_t u64Fraction = pCtx->fpu.aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
3041 unsigned uExponent = pCtx->fpu.aRegs[0].au16[4] & 0x7fff;
3042 /** @todo This isn't entirenly correct and needs more work! */
3043 pHlp->pfnPrintf(pHlp,
3044 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
3045 pszPrefix, iST, pszPrefix, iFPR,
3046 pCtx->fpu.aRegs[0].au16[4], pCtx->fpu.aRegs[0].au32[1], pCtx->fpu.aRegs[0].au32[0],
3047 uTag, chSign, iInteger, u64Fraction, uExponent);
3048 if (pCtx->fpu.aRegs[0].au16[5] || pCtx->fpu.aRegs[0].au16[6] || pCtx->fpu.aRegs[0].au16[7])
3049 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3050 pCtx->fpu.aRegs[0].au16[5], pCtx->fpu.aRegs[0].au16[6], pCtx->fpu.aRegs[0].au16[7]);
3051 else
3052 pHlp->pfnPrintf(pHlp, "\n");
3053 }
3054 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pCtx->fpu.aXMM); iXMM++)
3055 pHlp->pfnPrintf(pHlp,
3056 iXMM & 1
3057 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3058 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3059 pszPrefix, iXMM, iXMM < 10 ? " " : "",
3060 pCtx->fpu.aXMM[iXMM].au32[3],
3061 pCtx->fpu.aXMM[iXMM].au32[2],
3062 pCtx->fpu.aXMM[iXMM].au32[1],
3063 pCtx->fpu.aXMM[iXMM].au32[0]);
3064 for (unsigned i = 0; i < RT_ELEMENTS(pCtx->fpu.au32RsrvdRest); i++)
3065 if (pCtx->fpu.au32RsrvdRest[i])
3066 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
3067 pszPrefix, i, pCtx->fpu.au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
3068
3069 pHlp->pfnPrintf(pHlp,
3070 "%sEFER =%016RX64\n"
3071 "%sPAT =%016RX64\n"
3072 "%sSTAR =%016RX64\n"
3073 "%sCSTAR =%016RX64\n"
3074 "%sLSTAR =%016RX64\n"
3075 "%sSFMASK =%016RX64\n"
3076 "%sKERNELGSBASE =%016RX64\n",
3077 pszPrefix, pCtx->msrEFER,
3078 pszPrefix, pCtx->msrPAT,
3079 pszPrefix, pCtx->msrSTAR,
3080 pszPrefix, pCtx->msrCSTAR,
3081 pszPrefix, pCtx->msrLSTAR,
3082 pszPrefix, pCtx->msrSFMASK,
3083 pszPrefix, pCtx->msrKERNELGSBASE);
3084 break;
3085 }
3086}
3087
3088
3089/**
3090 * Display all cpu states and any other cpum info.
3091 *
3092 * @param pVM Pointer to the VM.
3093 * @param pHlp The info helper functions.
3094 * @param pszArgs Arguments, ignored.
3095 */
3096static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3097{
3098 cpumR3InfoGuest(pVM, pHlp, pszArgs);
3099 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3100 cpumR3InfoHyper(pVM, pHlp, pszArgs);
3101 cpumR3InfoHost(pVM, pHlp, pszArgs);
3102}
3103
3104
3105/**
3106 * Parses the info argument.
3107 *
3108 * The argument starts with 'verbose', 'terse' or 'default' and then
3109 * continues with the comment string.
3110 *
3111 * @param pszArgs The pointer to the argument string.
3112 * @param penmType Where to store the dump type request.
3113 * @param ppszComment Where to store the pointer to the comment string.
3114 */
3115static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
3116{
3117 if (!pszArgs)
3118 {
3119 *penmType = CPUMDUMPTYPE_DEFAULT;
3120 *ppszComment = "";
3121 }
3122 else
3123 {
3124 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3125 {
3126 pszArgs += 7;
3127 *penmType = CPUMDUMPTYPE_VERBOSE;
3128 }
3129 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3130 {
3131 pszArgs += 5;
3132 *penmType = CPUMDUMPTYPE_TERSE;
3133 }
3134 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3135 {
3136 pszArgs += 7;
3137 *penmType = CPUMDUMPTYPE_DEFAULT;
3138 }
3139 else
3140 *penmType = CPUMDUMPTYPE_DEFAULT;
3141 *ppszComment = RTStrStripL(pszArgs);
3142 }
3143}
3144
3145
3146/**
3147 * Display the guest cpu state.
3148 *
3149 * @param pVM Pointer to the VM.
3150 * @param pHlp The info helper functions.
3151 * @param pszArgs Arguments, ignored.
3152 */
3153static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3154{
3155 CPUMDUMPTYPE enmType;
3156 const char *pszComment;
3157 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3158
3159 /* @todo SMP support! */
3160 PVMCPU pVCpu = VMMGetCpu(pVM);
3161 if (!pVCpu)
3162 pVCpu = &pVM->aCpus[0];
3163
3164 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3165
3166 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3167 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3168}
3169
3170
3171/**
3172 * Display the current guest instruction
3173 *
3174 * @param pVM Pointer to the VM.
3175 * @param pHlp The info helper functions.
3176 * @param pszArgs Arguments, ignored.
3177 */
3178static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3179{
3180 NOREF(pszArgs);
3181
3182 /** @todo SMP support! */
3183 PVMCPU pVCpu = VMMGetCpu(pVM);
3184 if (!pVCpu)
3185 pVCpu = &pVM->aCpus[0];
3186
3187 char szInstruction[256];
3188 szInstruction[0] = '\0';
3189 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3190 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
3191}
3192
3193
3194/**
3195 * Display the hypervisor cpu state.
3196 *
3197 * @param pVM Pointer to the VM.
3198 * @param pHlp The info helper functions.
3199 * @param pszArgs Arguments, ignored.
3200 */
3201static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3202{
3203 CPUMDUMPTYPE enmType;
3204 const char *pszComment;
3205 /* @todo SMP */
3206 PVMCPU pVCpu = &pVM->aCpus[0];
3207
3208 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3209 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3210 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3211 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3212}
3213
3214
3215/**
3216 * Display the host cpu state.
3217 *
3218 * @param pVM Pointer to the VM.
3219 * @param pHlp The info helper functions.
3220 * @param pszArgs Arguments, ignored.
3221 */
3222static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3223{
3224 CPUMDUMPTYPE enmType;
3225 const char *pszComment;
3226 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3227 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3228
3229 /*
3230 * Format the EFLAGS.
3231 */
3232 /* @todo SMP */
3233 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
3234#if HC_ARCH_BITS == 32
3235 uint32_t efl = pCtx->eflags.u32;
3236#else
3237 uint64_t efl = pCtx->rflags;
3238#endif
3239 char szEFlags[80];
3240 cpumR3InfoFormatFlags(&szEFlags[0], efl);
3241
3242 /*
3243 * Format the registers.
3244 */
3245#if HC_ARCH_BITS == 32
3246# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3247 if (!(pCtx->efer & MSR_K6_EFER_LMA))
3248# endif
3249 {
3250 pHlp->pfnPrintf(pHlp,
3251 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3252 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3253 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3254 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3255 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3256 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3257 ,
3258 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
3259 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3260 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3261 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
3262 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3263 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3264 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3265 }
3266# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
3267 else
3268# endif
3269#endif
3270#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
3271 {
3272 pHlp->pfnPrintf(pHlp,
3273 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3274 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3275 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3276 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3277 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3278 "r14=%016RX64 r15=%016RX64\n"
3279 "iopl=%d %31s\n"
3280 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3281 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3282 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
3283 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3284 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3285 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3286 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3287 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3288 ,
3289 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
3290 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3291 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
3292 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
3293 pCtx->r11, pCtx->r12, pCtx->r13,
3294 pCtx->r14, pCtx->r15,
3295 X86_EFL_GET_IOPL(efl), szEFlags,
3296 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3297 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
3298 pCtx->cr4, pCtx->ldtr, pCtx->tr,
3299 pCtx->dr0, pCtx->dr1, pCtx->dr2,
3300 pCtx->dr3, pCtx->dr6, pCtx->dr7,
3301 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3302 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3303 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3304 }
3305#endif
3306}
3307
3308
3309/**
3310 * Get L1 cache / TLS associativity.
3311 */
3312static const char *getCacheAss(unsigned u, char *pszBuf)
3313{
3314 if (u == 0)
3315 return "res0 ";
3316 if (u == 1)
3317 return "direct";
3318 if (u == 255)
3319 return "fully";
3320 if (u >= 256)
3321 return "???";
3322
3323 RTStrPrintf(pszBuf, 16, "%d way", u);
3324 return pszBuf;
3325}
3326
3327
3328/**
3329 * Get L2 cache associativity.
3330 */
3331const char *getL2CacheAss(unsigned u)
3332{
3333 switch (u)
3334 {
3335 case 0: return "off ";
3336 case 1: return "direct";
3337 case 2: return "2 way ";
3338 case 3: return "res3 ";
3339 case 4: return "4 way ";
3340 case 5: return "res5 ";
3341 case 6: return "8 way ";
3342 case 7: return "res7 ";
3343 case 8: return "16 way";
3344 case 9: return "res9 ";
3345 case 10: return "res10 ";
3346 case 11: return "res11 ";
3347 case 12: return "res12 ";
3348 case 13: return "res13 ";
3349 case 14: return "res14 ";
3350 case 15: return "fully ";
3351 default: return "????";
3352 }
3353}
3354
3355
3356/**
3357 * Display the guest CpuId leaves.
3358 *
3359 * @param pVM Pointer to the VM.
3360 * @param pHlp The info helper functions.
3361 * @param pszArgs "terse", "default" or "verbose".
3362 */
3363static DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3364{
3365 /*
3366 * Parse the argument.
3367 */
3368 unsigned iVerbosity = 1;
3369 if (pszArgs)
3370 {
3371 pszArgs = RTStrStripL(pszArgs);
3372 if (!strcmp(pszArgs, "terse"))
3373 iVerbosity--;
3374 else if (!strcmp(pszArgs, "verbose"))
3375 iVerbosity++;
3376 }
3377
3378 /*
3379 * Start cracking.
3380 */
3381 CPUMCPUID Host;
3382 CPUMCPUID Guest;
3383 unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
3384
3385 uint32_t cStdHstMax;
3386 uint32_t dummy;
3387 ASMCpuId_Idx_ECX(0, 0, &cStdHstMax, &dummy, &dummy, &dummy);
3388
3389 unsigned cStdLstMax = RT_MAX(RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd), cStdHstMax);
3390
3391 pHlp->pfnPrintf(pHlp,
3392 " RAW Standard CPUIDs\n"
3393 " Function eax ebx ecx edx\n");
3394 for (unsigned i = 0; i <= cStdLstMax ; i++)
3395 {
3396 if (i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
3397 {
3398 Guest = pVM->cpum.s.aGuestCpuIdStd[i];
3399 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3400
3401 pHlp->pfnPrintf(pHlp,
3402 "Gst: %08x %08x %08x %08x %08x%s\n"
3403 "Hst: %08x %08x %08x %08x\n",
3404 i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3405 i <= cStdMax ? "" : "*",
3406 Host.eax, Host.ebx, Host.ecx, Host.edx);
3407 }
3408 else
3409 {
3410 ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3411
3412 pHlp->pfnPrintf(pHlp,
3413 "Hst: %08x %08x %08x %08x %08x\n",
3414 i, Host.eax, Host.ebx, Host.ecx, Host.edx);
3415 }
3416 }
3417
3418 /*
3419 * If verbose, decode it.
3420 */
3421 if (iVerbosity)
3422 {
3423 Guest = pVM->cpum.s.aGuestCpuIdStd[0];
3424 pHlp->pfnPrintf(pHlp,
3425 "Name: %.04s%.04s%.04s\n"
3426 "Supports: 0-%x\n",
3427 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3428 }
3429
3430 /*
3431 * Get Features.
3432 */
3433 bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
3434 pVM->cpum.s.aGuestCpuIdStd[0].ecx,
3435 pVM->cpum.s.aGuestCpuIdStd[0].edx);
3436 if (cStdMax >= 1 && iVerbosity)
3437 {
3438 static const char * const s_apszTypes[4] = { "primary", "overdrive", "MP", "reserved" };
3439
3440 Guest = pVM->cpum.s.aGuestCpuIdStd[1];
3441 uint32_t uEAX = Guest.eax;
3442
3443 pHlp->pfnPrintf(pHlp,
3444 "Family: %d \tExtended: %d \tEffective: %d\n"
3445 "Model: %d \tExtended: %d \tEffective: %d\n"
3446 "Stepping: %d\n"
3447 "Type: %d (%s)\n"
3448 "APIC ID: %#04x\n"
3449 "Logical CPUs: %d\n"
3450 "CLFLUSH Size: %d\n"
3451 "Brand ID: %#04x\n",
3452 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3453 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3454 ASMGetCpuStepping(uEAX),
3455 (uEAX >> 12) & 3, s_apszTypes[(uEAX >> 12) & 3],
3456 (Guest.ebx >> 24) & 0xff,
3457 (Guest.ebx >> 16) & 0xff,
3458 (Guest.ebx >> 8) & 0xff,
3459 (Guest.ebx >> 0) & 0xff);
3460 if (iVerbosity == 1)
3461 {
3462 uint32_t uEDX = Guest.edx;
3463 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3464 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3465 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3466 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3467 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3468 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3469 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3470 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3471 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3472 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3473 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3474 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3475 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
3476 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3477 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3478 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3479 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3480 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3481 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3482 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
3483 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
3484 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
3485 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
3486 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
3487 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3488 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3489 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
3490 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
3491 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
3492 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
3493 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
3494 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3495 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
3496 pHlp->pfnPrintf(pHlp, "\n");
3497
3498 uint32_t uECX = Guest.ecx;
3499 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3500 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
3501 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " PCLMUL");
3502 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DTES64");
3503 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
3504 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
3505 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
3506 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SMX");
3507 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
3508 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
3509 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " SSSE3");
3510 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
3511 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
3512 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " FMA");
3513 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
3514 if (uECX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " TPRUPDATE");
3515 if (uECX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " PDCM");
3516 if (uECX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " 16");
3517 if (uECX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PCID");
3518 if (uECX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " DCA");
3519 if (uECX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " SSE4.1");
3520 if (uECX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " SSE4.2");
3521 if (uECX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " X2APIC");
3522 if (uECX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " MOVBE");
3523 if (uECX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " POPCNT");
3524 if (uECX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " TSCDEADL");
3525 if (uECX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " AES");
3526 if (uECX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " XSAVE");
3527 if (uECX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " OSXSAVE");
3528 if (uECX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " AVX");
3529 if (uECX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " 29");
3530 if (uECX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
3531 if (uECX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 31");
3532 pHlp->pfnPrintf(pHlp, "\n");
3533 }
3534 else
3535 {
3536 ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3537
3538 X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
3539 X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
3540 X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
3541 X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
3542
3543 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3544 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
3545 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
3546 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
3547 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
3548 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
3549 pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
3550 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
3551 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
3552 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
3553 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
3554 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
3555 pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
3556 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
3557 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
3558 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
3559 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
3560 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
3561 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
3562 pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
3563 pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
3564 pHlp->pfnPrintf(pHlp, "20 - Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
3565 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
3566 pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
3567 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
3568 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
3569 pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
3570 pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
3571 pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
3572 pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technology = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
3573 pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
3574 pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
3575 pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
3576
3577 pHlp->pfnPrintf(pHlp, "Supports SSE3 = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
3578 pHlp->pfnPrintf(pHlp, "PCLMULQDQ = %d (%d)\n", EcxGuest.u1PCLMULQDQ, EcxHost.u1PCLMULQDQ);
3579 pHlp->pfnPrintf(pHlp, "DS Area 64-bit layout = %d (%d)\n", EcxGuest.u1DTE64, EcxHost.u1DTE64);
3580 pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
3581 pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
3582 pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
3583 pHlp->pfnPrintf(pHlp, "SMX - Safer Mode Extensions = %d (%d)\n", EcxGuest.u1SMX, EcxHost.u1SMX);
3584 pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
3585 pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
3586 pHlp->pfnPrintf(pHlp, "Supplemental SSE3 instructions = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
3587 pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
3588 pHlp->pfnPrintf(pHlp, "11 - Reserved = %d (%d)\n", EcxGuest.u1Reserved1, EcxHost.u1Reserved1);
3589 pHlp->pfnPrintf(pHlp, "FMA extensions using YMM state = %d (%d)\n", EcxGuest.u1FMA, EcxHost.u1FMA);
3590 pHlp->pfnPrintf(pHlp, "CMPXCHG16B instruction = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
3591 pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
3592 pHlp->pfnPrintf(pHlp, "Perf/Debug Capability MSR = %d (%d)\n", EcxGuest.u1PDCM, EcxHost.u1PDCM);
3593 pHlp->pfnPrintf(pHlp, "16 - Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
3594 pHlp->pfnPrintf(pHlp, "PCID - Process-context identifiers = %d (%d)\n", EcxGuest.u1PCID, EcxHost.u1PCID);
3595 pHlp->pfnPrintf(pHlp, "DCA - Direct Cache Access = %d (%d)\n", EcxGuest.u1DCA, EcxHost.u1DCA);
3596 pHlp->pfnPrintf(pHlp, "SSE4.1 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_1, EcxHost.u1SSE4_1);
3597 pHlp->pfnPrintf(pHlp, "SSE4.2 instruction extensions = %d (%d)\n", EcxGuest.u1SSE4_2, EcxHost.u1SSE4_2);
3598 pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
3599 pHlp->pfnPrintf(pHlp, "MOVBE instruction = %d (%d)\n", EcxGuest.u1MOVBE, EcxHost.u1MOVBE);
3600 pHlp->pfnPrintf(pHlp, "POPCNT instruction = %d (%d)\n", EcxGuest.u1POPCNT, EcxHost.u1POPCNT);
3601 pHlp->pfnPrintf(pHlp, "TSC-Deadline LAPIC timer mode = %d (%d)\n", EcxGuest.u1TSCDEADLINE,EcxHost.u1TSCDEADLINE);
3602 pHlp->pfnPrintf(pHlp, "AESNI instruction extensions = %d (%d)\n", EcxGuest.u1AES, EcxHost.u1AES);
3603 pHlp->pfnPrintf(pHlp, "XSAVE/XRSTOR extended state feature = %d (%d)\n", EcxGuest.u1XSAVE, EcxHost.u1XSAVE);
3604 pHlp->pfnPrintf(pHlp, "Supports OSXSAVE = %d (%d)\n", EcxGuest.u1OSXSAVE, EcxHost.u1OSXSAVE);
3605 pHlp->pfnPrintf(pHlp, "AVX instruction extensions = %d (%d)\n", EcxGuest.u1AVX, EcxHost.u1AVX);
3606 pHlp->pfnPrintf(pHlp, "29/30 - Reserved = %#x (%#x)\n",EcxGuest.u2Reserved3, EcxHost.u2Reserved3);
3607 pHlp->pfnPrintf(pHlp, "Hypervisor Present (we're a guest) = %d (%d)\n", EcxGuest.u1HVP, EcxHost.u1HVP);
3608 }
3609 }
3610 if (cStdMax >= 2 && iVerbosity)
3611 {
3612 /** @todo */
3613 }
3614
3615 /*
3616 * Extended.
3617 * Implemented after AMD specs.
3618 */
3619 unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
3620
3621 pHlp->pfnPrintf(pHlp,
3622 "\n"
3623 " RAW Extended CPUIDs\n"
3624 " Function eax ebx ecx edx\n");
3625 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
3626 {
3627 Guest = pVM->cpum.s.aGuestCpuIdExt[i];
3628 ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3629
3630 pHlp->pfnPrintf(pHlp,
3631 "Gst: %08x %08x %08x %08x %08x%s\n"
3632 "Hst: %08x %08x %08x %08x\n",
3633 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3634 i <= cExtMax ? "" : "*",
3635 Host.eax, Host.ebx, Host.ecx, Host.edx);
3636 }
3637
3638 /*
3639 * Understandable output
3640 */
3641 if (iVerbosity)
3642 {
3643 Guest = pVM->cpum.s.aGuestCpuIdExt[0];
3644 pHlp->pfnPrintf(pHlp,
3645 "Ext Name: %.4s%.4s%.4s\n"
3646 "Ext Supports: 0x80000000-%#010x\n",
3647 &Guest.ebx, &Guest.edx, &Guest.ecx, Guest.eax);
3648 }
3649
3650 if (iVerbosity && cExtMax >= 1)
3651 {
3652 Guest = pVM->cpum.s.aGuestCpuIdExt[1];
3653 uint32_t uEAX = Guest.eax;
3654 pHlp->pfnPrintf(pHlp,
3655 "Family: %d \tExtended: %d \tEffective: %d\n"
3656 "Model: %d \tExtended: %d \tEffective: %d\n"
3657 "Stepping: %d\n"
3658 "Brand ID: %#05x\n",
3659 (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
3660 (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
3661 ASMGetCpuStepping(uEAX),
3662 Guest.ebx & 0xfff);
3663
3664 if (iVerbosity == 1)
3665 {
3666 uint32_t uEDX = Guest.edx;
3667 pHlp->pfnPrintf(pHlp, "Features EDX: ");
3668 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
3669 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
3670 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
3671 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
3672 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
3673 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
3674 if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
3675 if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
3676 if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
3677 if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
3678 if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
3679 if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
3680 if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
3681 if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
3682 if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
3683 if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
3684 if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
3685 if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
3686 if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
3687 if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
3688 if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
3689 if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
3690 if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
3691 if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
3692 if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
3693 if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
3694 if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
3695 if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
3696 if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
3697 if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
3698 if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
3699 if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
3700 pHlp->pfnPrintf(pHlp, "\n");
3701
3702 uint32_t uECX = Guest.ecx;
3703 pHlp->pfnPrintf(pHlp, "Features ECX: ");
3704 if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
3705 if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
3706 if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
3707 if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
3708 if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
3709 if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
3710 if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
3711 if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
3712 if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
3713 if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
3714 if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
3715 if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
3716 if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
3717 if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
3718 for (unsigned iBit = 5; iBit < 32; iBit++)
3719 if (uECX & RT_BIT(iBit))
3720 pHlp->pfnPrintf(pHlp, " %d", iBit);
3721 pHlp->pfnPrintf(pHlp, "\n");
3722 }
3723 else
3724 {
3725 ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3726
3727 uint32_t uEdxGst = Guest.edx;
3728 uint32_t uEdxHst = Host.edx;
3729 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3730 pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3731 pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3732 pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3733 pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3734 pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3735 pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3736 pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3737 pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3738 pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3739 pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3740 pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3741 pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3742 pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3743 pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3744 pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3745 pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3746 pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3747 pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3748 pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3749 pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3750 pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3751 pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3752 pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3753 pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3754 pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3755 pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
3756 pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
3757 pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
3758 pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
3759 pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
3760 pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
3761 pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow! = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
3762
3763 uint32_t uEcxGst = Guest.ecx;
3764 uint32_t uEcxHst = Host.ecx;
3765 pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
3766 pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
3767 pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
3768 pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
3769 pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
3770 pHlp->pfnPrintf(pHlp, "5 - Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
3771 pHlp->pfnPrintf(pHlp, "6 - SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
3772 pHlp->pfnPrintf(pHlp, "7 - Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
3773 pHlp->pfnPrintf(pHlp, "8 - PREFETCH and PREFETCHW instruction= %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
3774 pHlp->pfnPrintf(pHlp, "9 - OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
3775 pHlp->pfnPrintf(pHlp, "10 - Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
3776 pHlp->pfnPrintf(pHlp, "11 - SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
3777 pHlp->pfnPrintf(pHlp, "12 - SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
3778 pHlp->pfnPrintf(pHlp, "13 - Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
3779 pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
3780 }
3781 }
3782
3783 if (iVerbosity && cExtMax >= 2)
3784 {
3785 char szString[4*4*3+1] = {0};
3786 uint32_t *pu32 = (uint32_t *)szString;
3787 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].eax;
3788 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ebx;
3789 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].ecx;
3790 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[2].edx;
3791 if (cExtMax >= 3)
3792 {
3793 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].eax;
3794 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ebx;
3795 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].ecx;
3796 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[3].edx;
3797 }
3798 if (cExtMax >= 4)
3799 {
3800 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].eax;
3801 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ebx;
3802 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].ecx;
3803 *pu32++ = pVM->cpum.s.aGuestCpuIdExt[4].edx;
3804 }
3805 pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
3806 }
3807
3808 if (iVerbosity && cExtMax >= 5)
3809 {
3810 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[5].eax;
3811 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[5].ebx;
3812 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[5].ecx;
3813 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[5].edx;
3814 char sz1[32];
3815 char sz2[32];
3816
3817 pHlp->pfnPrintf(pHlp,
3818 "TLB 2/4M Instr/Uni: %s %3d entries\n"
3819 "TLB 2/4M Data: %s %3d entries\n",
3820 getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
3821 getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
3822 pHlp->pfnPrintf(pHlp,
3823 "TLB 4K Instr/Uni: %s %3d entries\n"
3824 "TLB 4K Data: %s %3d entries\n",
3825 getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
3826 getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
3827 pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
3828 "L1 Instr Cache Lines Per Tag: %d\n"
3829 "L1 Instr Cache Associativity: %s\n"
3830 "L1 Instr Cache Size: %d KB\n",
3831 (uEDX >> 0) & 0xff,
3832 (uEDX >> 8) & 0xff,
3833 getCacheAss((uEDX >> 16) & 0xff, sz1),
3834 (uEDX >> 24) & 0xff);
3835 pHlp->pfnPrintf(pHlp,
3836 "L1 Data Cache Line Size: %d bytes\n"
3837 "L1 Data Cache Lines Per Tag: %d\n"
3838 "L1 Data Cache Associativity: %s\n"
3839 "L1 Data Cache Size: %d KB\n",
3840 (uECX >> 0) & 0xff,
3841 (uECX >> 8) & 0xff,
3842 getCacheAss((uECX >> 16) & 0xff, sz1),
3843 (uECX >> 24) & 0xff);
3844 }
3845
3846 if (iVerbosity && cExtMax >= 6)
3847 {
3848 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[6].eax;
3849 uint32_t uEBX = pVM->cpum.s.aGuestCpuIdExt[6].ebx;
3850 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[6].edx;
3851
3852 pHlp->pfnPrintf(pHlp,
3853 "L2 TLB 2/4M Instr/Uni: %s %4d entries\n"
3854 "L2 TLB 2/4M Data: %s %4d entries\n",
3855 getL2CacheAss((uEAX >> 12) & 0xf), (uEAX >> 0) & 0xfff,
3856 getL2CacheAss((uEAX >> 28) & 0xf), (uEAX >> 16) & 0xfff);
3857 pHlp->pfnPrintf(pHlp,
3858 "L2 TLB 4K Instr/Uni: %s %4d entries\n"
3859 "L2 TLB 4K Data: %s %4d entries\n",
3860 getL2CacheAss((uEBX >> 12) & 0xf), (uEBX >> 0) & 0xfff,
3861 getL2CacheAss((uEBX >> 28) & 0xf), (uEBX >> 16) & 0xfff);
3862 pHlp->pfnPrintf(pHlp,
3863 "L2 Cache Line Size: %d bytes\n"
3864 "L2 Cache Lines Per Tag: %d\n"
3865 "L2 Cache Associativity: %s\n"
3866 "L2 Cache Size: %d KB\n",
3867 (uEDX >> 0) & 0xff,
3868 (uEDX >> 8) & 0xf,
3869 getL2CacheAss((uEDX >> 12) & 0xf),
3870 (uEDX >> 16) & 0xffff);
3871 }
3872
3873 if (iVerbosity && cExtMax >= 7)
3874 {
3875 uint32_t uEDX = pVM->cpum.s.aGuestCpuIdExt[7].edx;
3876
3877 pHlp->pfnPrintf(pHlp, "APM Features: ");
3878 if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " TS");
3879 if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " FID");
3880 if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " VID");
3881 if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " TTP");
3882 if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TM");
3883 if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " STC");
3884 for (unsigned iBit = 6; iBit < 32; iBit++)
3885 if (uEDX & RT_BIT(iBit))
3886 pHlp->pfnPrintf(pHlp, " %d", iBit);
3887 pHlp->pfnPrintf(pHlp, "\n");
3888 }
3889
3890 if (iVerbosity && cExtMax >= 8)
3891 {
3892 uint32_t uEAX = pVM->cpum.s.aGuestCpuIdExt[8].eax;
3893 uint32_t uECX = pVM->cpum.s.aGuestCpuIdExt[8].ecx;
3894
3895 pHlp->pfnPrintf(pHlp,
3896 "Physical Address Width: %d bits\n"
3897 "Virtual Address Width: %d bits\n"
3898 "Guest Physical Address Width: %d bits\n",
3899 (uEAX >> 0) & 0xff,
3900 (uEAX >> 8) & 0xff,
3901 (uEAX >> 16) & 0xff);
3902 pHlp->pfnPrintf(pHlp,
3903 "Physical Core Count: %d\n",
3904 (uECX >> 0) & 0xff);
3905 }
3906
3907
3908 /*
3909 * Centaur.
3910 */
3911 unsigned cCentaurMax = pVM->cpum.s.aGuestCpuIdCentaur[0].eax & 0xffff;
3912
3913 pHlp->pfnPrintf(pHlp,
3914 "\n"
3915 " RAW Centaur CPUIDs\n"
3916 " Function eax ebx ecx edx\n");
3917 for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur); i++)
3918 {
3919 Guest = pVM->cpum.s.aGuestCpuIdCentaur[i];
3920 ASMCpuId(0xc0000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3921
3922 pHlp->pfnPrintf(pHlp,
3923 "Gst: %08x %08x %08x %08x %08x%s\n"
3924 "Hst: %08x %08x %08x %08x\n",
3925 0xc0000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
3926 i <= cCentaurMax ? "" : "*",
3927 Host.eax, Host.ebx, Host.ecx, Host.edx);
3928 }
3929
3930 /*
3931 * Understandable output
3932 */
3933 if (iVerbosity)
3934 {
3935 Guest = pVM->cpum.s.aGuestCpuIdCentaur[0];
3936 pHlp->pfnPrintf(pHlp,
3937 "Centaur Supports: 0xc0000000-%#010x\n",
3938 Guest.eax);
3939 }
3940
3941 if (iVerbosity && cCentaurMax >= 1)
3942 {
3943 ASMCpuId(0xc0000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
3944 uint32_t uEdxGst = pVM->cpum.s.aGuestCpuIdExt[1].edx;
3945 uint32_t uEdxHst = Host.edx;
3946
3947 if (iVerbosity == 1)
3948 {
3949 pHlp->pfnPrintf(pHlp, "Centaur Features EDX: ");
3950 if (uEdxGst & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " AIS");
3951 if (uEdxGst & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " AIS-E");
3952 if (uEdxGst & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " RNG");
3953 if (uEdxGst & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " RNG-E");
3954 if (uEdxGst & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " LH");
3955 if (uEdxGst & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " FEMMS");
3956 if (uEdxGst & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " ACE");
3957 if (uEdxGst & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " ACE-E");
3958 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3959 if (uEdxGst & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " ACE2");
3960 if (uEdxGst & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " ACE2-E");
3961 if (uEdxGst & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " PHE");
3962 if (uEdxGst & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " PHE-E");
3963 if (uEdxGst & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " PMM");
3964 if (uEdxGst & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PMM-E");
3965 for (unsigned iBit = 14; iBit < 32; iBit++)
3966 if (uEdxGst & RT_BIT(iBit))
3967 pHlp->pfnPrintf(pHlp, " %d", iBit);
3968 pHlp->pfnPrintf(pHlp, "\n");
3969 }
3970 else
3971 {
3972 pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
3973 pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
3974 pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
3975 pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
3976 pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
3977 pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
3978 pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
3979 pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
3980 pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
3981 /* possibly indicating MM/HE and MM/HE-E on older chips... */
3982 pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
3983 pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
3984 pHlp->pfnPrintf(pHlp, "PHE - Padlock Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
3985 pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
3986 pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
3987 pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
3988 pHlp->pfnPrintf(pHlp, "14 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
3989 pHlp->pfnPrintf(pHlp, "15 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
3990 pHlp->pfnPrintf(pHlp, "Parallax = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
3991 pHlp->pfnPrintf(pHlp, "Parallax enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
3992 pHlp->pfnPrintf(pHlp, "Overstress = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
3993 pHlp->pfnPrintf(pHlp, "Overstress enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
3994 pHlp->pfnPrintf(pHlp, "TM3 - Temperature Monitoring 3 = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
3995 pHlp->pfnPrintf(pHlp, "TM3-E - TM3 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
3996 pHlp->pfnPrintf(pHlp, "RNG2 - Random Number Generator 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
3997 pHlp->pfnPrintf(pHlp, "RNG2-E - RNG2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
3998 pHlp->pfnPrintf(pHlp, "24 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
3999 pHlp->pfnPrintf(pHlp, "PHE2 - Padlock Hash Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
4000 pHlp->pfnPrintf(pHlp, "PHE2-E - PHE2 enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
4001 for (unsigned iBit = 27; iBit < 32; iBit++)
4002 if ((uEdxGst | uEdxHst) & RT_BIT(iBit))
4003 pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", iBit, !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
4004 pHlp->pfnPrintf(pHlp, "\n");
4005 }
4006 }
4007}
4008
4009
4010/**
4011 * Structure used when disassembling and instructions in DBGF.
4012 * This is used so the reader function can get the stuff it needs.
4013 */
4014typedef struct CPUMDISASSTATE
4015{
4016 /** Pointer to the CPU structure. */
4017 PDISCPUSTATE pCpu;
4018 /** Pointer to the VM. */
4019 PVM pVM;
4020 /** Pointer to the VMCPU. */
4021 PVMCPU pVCpu;
4022 /** Pointer to the first byte in the segment. */
4023 RTGCUINTPTR GCPtrSegBase;
4024 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
4025 RTGCUINTPTR GCPtrSegEnd;
4026 /** The size of the segment minus 1. */
4027 RTGCUINTPTR cbSegLimit;
4028 /** Pointer to the current page - R3 Ptr. */
4029 void const *pvPageR3;
4030 /** Pointer to the current page - GC Ptr. */
4031 RTGCPTR pvPageGC;
4032 /** The lock information that PGMPhysReleasePageMappingLock needs. */
4033 PGMPAGEMAPLOCK PageMapLock;
4034 /** Whether the PageMapLock is valid or not. */
4035 bool fLocked;
4036 /** 64 bits mode or not. */
4037 bool f64Bits;
4038} CPUMDISASSTATE, *PCPUMDISASSTATE;
4039
4040
4041/**
4042 * @callback_method_impl{FNDISREADBYTES}
4043 */
4044static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4045{
4046 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4047 for (;;)
4048 {
4049 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4050
4051 /*
4052 * Need to update the page translation?
4053 */
4054 if ( !pState->pvPageR3
4055 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4056 {
4057 int rc = VINF_SUCCESS;
4058
4059 /* translate the address */
4060 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4061 if ( !HMIsEnabled(pState->pVM)
4062 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4063 {
4064 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4065 if (!pState->pvPageR3)
4066 rc = VERR_INVALID_POINTER;
4067 }
4068 else
4069 {
4070 /* Release mapping lock previously acquired. */
4071 if (pState->fLocked)
4072 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4073 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4074 pState->fLocked = RT_SUCCESS_NP(rc);
4075 }
4076 if (RT_FAILURE(rc))
4077 {
4078 pState->pvPageR3 = NULL;
4079 return rc;
4080 }
4081 }
4082
4083 /*
4084 * Check the segment limit.
4085 */
4086 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4087 return VERR_OUT_OF_SELECTOR_BOUNDS;
4088
4089 /*
4090 * Calc how much we can read.
4091 */
4092 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4093 if (!pState->f64Bits)
4094 {
4095 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4096 if (cb > cbSeg && cbSeg)
4097 cb = cbSeg;
4098 }
4099 if (cb > cbMaxRead)
4100 cb = cbMaxRead;
4101
4102 /*
4103 * Read and advance or exit.
4104 */
4105 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4106 offInstr += (uint8_t)cb;
4107 if (cb >= cbMinRead)
4108 {
4109 pDis->cbCachedInstr = offInstr;
4110 return VINF_SUCCESS;
4111 }
4112 cbMinRead -= (uint8_t)cb;
4113 cbMaxRead -= (uint8_t)cb;
4114 }
4115}
4116
4117
4118/**
4119 * Disassemble an instruction and return the information in the provided structure.
4120 *
4121 * @returns VBox status code.
4122 * @param pVM Pointer to the VM.
4123 * @param pVCpu Pointer to the VMCPU.
4124 * @param pCtx Pointer to the guest CPU context.
4125 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
4126 * @param pCpu Disassembly state.
4127 * @param pszPrefix String prefix for logging (debug only).
4128 *
4129 */
4130VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
4131{
4132 CPUMDISASSTATE State;
4133 int rc;
4134
4135 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4136 State.pCpu = pCpu;
4137 State.pvPageGC = 0;
4138 State.pvPageR3 = NULL;
4139 State.pVM = pVM;
4140 State.pVCpu = pVCpu;
4141 State.fLocked = false;
4142 State.f64Bits = false;
4143
4144 /*
4145 * Get selector information.
4146 */
4147 DISCPUMODE enmDisCpuMode;
4148 if ( (pCtx->cr0 & X86_CR0_PE)
4149 && pCtx->eflags.Bits.u1VM == 0)
4150 {
4151 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4152 {
4153# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4154 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4155# endif
4156 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4157 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4158 }
4159 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4160 State.GCPtrSegBase = pCtx->cs.u64Base;
4161 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4162 State.cbSegLimit = pCtx->cs.u32Limit;
4163 enmDisCpuMode = (State.f64Bits)
4164 ? DISCPUMODE_64BIT
4165 : pCtx->cs.Attr.n.u1DefBig
4166 ? DISCPUMODE_32BIT
4167 : DISCPUMODE_16BIT;
4168 }
4169 else
4170 {
4171 /* real or V86 mode */
4172 enmDisCpuMode = DISCPUMODE_16BIT;
4173 State.GCPtrSegBase = pCtx->cs.Sel * 16;
4174 State.GCPtrSegEnd = 0xFFFFFFFF;
4175 State.cbSegLimit = 0xFFFFFFFF;
4176 }
4177
4178 /*
4179 * Disassemble the instruction.
4180 */
4181 uint32_t cbInstr;
4182#ifndef LOG_ENABLED
4183 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4184 if (RT_SUCCESS(rc))
4185 {
4186#else
4187 char szOutput[160];
4188 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4189 pCpu, &cbInstr, szOutput, sizeof(szOutput));
4190 if (RT_SUCCESS(rc))
4191 {
4192 /* log it */
4193 if (pszPrefix)
4194 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4195 else
4196 Log(("%s", szOutput));
4197#endif
4198 rc = VINF_SUCCESS;
4199 }
4200 else
4201 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4202
4203 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
4204 if (State.fLocked)
4205 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4206
4207 return rc;
4208}
4209
4210
4211
4212/**
4213 * API for controlling a few of the CPU features found in CR4.
4214 *
4215 * Currently only X86_CR4_TSD is accepted as input.
4216 *
4217 * @returns VBox status code.
4218 *
4219 * @param pVM Pointer to the VM.
4220 * @param fOr The CR4 OR mask.
4221 * @param fAnd The CR4 AND mask.
4222 */
4223VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4224{
4225 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4226 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4227
4228 pVM->cpum.s.CR4.OrMask &= fAnd;
4229 pVM->cpum.s.CR4.OrMask |= fOr;
4230
4231 return VINF_SUCCESS;
4232}
4233
4234
4235/**
4236 * Gets a pointer to the array of standard CPUID leaves.
4237 *
4238 * CPUMR3GetGuestCpuIdStdMax() give the size of the array.
4239 *
4240 * @returns Pointer to the standard CPUID leaves (read-only).
4241 * @param pVM Pointer to the VM.
4242 * @remark Intended for PATM.
4243 */
4244VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdStdRCPtr(PVM pVM)
4245{
4246 return RCPTRTYPE(PCCPUMCPUID)VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdStd[0]);
4247}
4248
4249
4250/**
4251 * Gets a pointer to the array of extended CPUID leaves.
4252 *
4253 * CPUMGetGuestCpuIdExtMax() give the size of the array.
4254 *
4255 * @returns Pointer to the extended CPUID leaves (read-only).
4256 * @param pVM Pointer to the VM.
4257 * @remark Intended for PATM.
4258 */
4259VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdExtRCPtr(PVM pVM)
4260{
4261 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
4262}
4263
4264
4265/**
4266 * Gets a pointer to the array of centaur CPUID leaves.
4267 *
4268 * CPUMGetGuestCpuIdCentaurMax() give the size of the array.
4269 *
4270 * @returns Pointer to the centaur CPUID leaves (read-only).
4271 * @param pVM Pointer to the VM.
4272 * @remark Intended for PATM.
4273 */
4274VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdCentaurRCPtr(PVM pVM)
4275{
4276 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
4277}
4278
4279
4280/**
4281 * Gets a pointer to the default CPUID leaf.
4282 *
4283 * @returns Pointer to the default CPUID leaf (read-only).
4284 * @param pVM Pointer to the VM.
4285 * @remark Intended for PATM.
4286 */
4287VMMR3DECL(RCPTRTYPE(PCCPUMCPUID)) CPUMR3GetGuestCpuIdDefRCPtr(PVM pVM)
4288{
4289 return (RCPTRTYPE(PCCPUMCPUID))VM_RC_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
4290}
4291
4292
4293/**
4294 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4295 *
4296 * Only REM should ever call this function!
4297 *
4298 * @returns The changed flags.
4299 * @param pVCpu Pointer to the VMCPU.
4300 * @param puCpl Where to return the current privilege level (CPL).
4301 */
4302VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4303{
4304 Assert(!pVCpu->cpum.s.fRawEntered);
4305 Assert(!pVCpu->cpum.s.fRemEntered);
4306
4307 /*
4308 * Get the CPL first.
4309 */
4310 *puCpl = CPUMGetGuestCPL(pVCpu);
4311
4312 /*
4313 * Get and reset the flags.
4314 */
4315 uint32_t fFlags = pVCpu->cpum.s.fChanged;
4316 pVCpu->cpum.s.fChanged = 0;
4317
4318 /** @todo change the switcher to use the fChanged flags. */
4319 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4320 {
4321 fFlags |= CPUM_CHANGED_FPU_REM;
4322 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4323 }
4324
4325 pVCpu->cpum.s.fRemEntered = true;
4326 return fFlags;
4327}
4328
4329
4330/**
4331 * Leaves REM.
4332 *
4333 * @param pVCpu Pointer to the VMCPU.
4334 * @param fNoOutOfSyncSels This is @c false if there are out of sync
4335 * registers.
4336 */
4337VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4338{
4339 Assert(!pVCpu->cpum.s.fRawEntered);
4340 Assert(pVCpu->cpum.s.fRemEntered);
4341
4342 pVCpu->cpum.s.fRemEntered = false;
4343}
4344
4345
4346/**
4347 * Called when the ring-3 init phase completes.
4348 *
4349 * @returns VBox status code.
4350 * @param pVM Pointer to the VM.
4351 */
4352VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
4353{
4354 for (VMCPUID i = 0; i < pVM->cCpus; i++)
4355 {
4356 /* Cache the APIC base (from the APIC device) once it has been initialized. */
4357 PDMApicGetBase(&pVM->aCpus[i], &pVM->aCpus[i].cpum.s.Guest.msrApicBase);
4358 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVM->aCpus[i].cpum.s.Guest.msrApicBase));
4359 }
4360 return VINF_SUCCESS;
4361}
4362
4363/**
4364 * Called when the ring-0 init phases comleted.
4365 *
4366 * @param pVM Pointer to the VM.
4367 */
4368VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
4369{
4370 /*
4371 * Log the cpuid.
4372 */
4373 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
4374 RTCPUSET OnlineSet;
4375 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4376 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4377 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4378 RTCPUID cCores = RTMpGetCoreCount();
4379 if (cCores)
4380 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
4381 LogRel(("************************* CPUID dump ************************\n"));
4382 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4383 LogRel(("\n"));
4384 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
4385 RTLogRelSetBuffering(fOldBuffered);
4386 LogRel(("******************** End of CPUID dump **********************\n"));
4387}
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