VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 55323

Last change on this file since 55323 was 55229, checked in by vboxsync, 10 years ago

CPUM,IEM: Expose GuestFeatures and HostFeatures (exploded CPUID), making IEM use it. Early XSAVE/AVX guest support preps.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 94.2 KB
Line 
1/* $Id: CPUM.cpp 55229 2015-04-14 06:35:43Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/assert.h>
59#include <iprt/cpuset.h>
60#include <iprt/mem.h>
61#include <iprt/mp.h>
62#include <iprt/string.h>
63#include "internal/pgm.h"
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/**
70 * This was used in the saved state up to the early life of version 14.
71 *
72 * It indicates that we may have some out-of-sync hidden segement registers.
73 * It is only relevant for raw-mode.
74 */
75#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
76
77
78/*******************************************************************************
79* Structures and Typedefs *
80*******************************************************************************/
81
82/**
83 * What kind of cpu info dump to perform.
84 */
85typedef enum CPUMDUMPTYPE
86{
87 CPUMDUMPTYPE_TERSE,
88 CPUMDUMPTYPE_DEFAULT,
89 CPUMDUMPTYPE_VERBOSE
90} CPUMDUMPTYPE;
91/** Pointer to a cpu info dump type. */
92typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
93
94
95/*******************************************************************************
96* Internal Functions *
97*******************************************************************************/
98static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
99static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
100static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
101static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108
109
110/*******************************************************************************
111* Global Variables *
112*******************************************************************************/
113/** Saved state field descriptors for CPUMCTX. */
114static const SSMFIELD g_aCpumX87Fields[] =
115{
116 SSMFIELD_ENTRY( X86FXSTATE, FCW),
117 SSMFIELD_ENTRY( X86FXSTATE, FSW),
118 SSMFIELD_ENTRY( X86FXSTATE, FTW),
119 SSMFIELD_ENTRY( X86FXSTATE, FOP),
120 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
121 SSMFIELD_ENTRY( X86FXSTATE, CS),
122 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
123 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
124 SSMFIELD_ENTRY( X86FXSTATE, DS),
125 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
126 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
127 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
128 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
129 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
130 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
131 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
132 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
133 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
134 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
135 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
136 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
137 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
138 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
139 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
140 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
141 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
142 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
143 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
144 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
145 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
146 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
147 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
148 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
149 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
150 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
151 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
152 SSMFIELD_ENTRY_TERM()
153};
154
155/** Saved state field descriptors for CPUMCTX. */
156static const SSMFIELD g_aCpumCtxFields[] =
157{
158 SSMFIELD_ENTRY( CPUMCTX, rdi),
159 SSMFIELD_ENTRY( CPUMCTX, rsi),
160 SSMFIELD_ENTRY( CPUMCTX, rbp),
161 SSMFIELD_ENTRY( CPUMCTX, rax),
162 SSMFIELD_ENTRY( CPUMCTX, rbx),
163 SSMFIELD_ENTRY( CPUMCTX, rdx),
164 SSMFIELD_ENTRY( CPUMCTX, rcx),
165 SSMFIELD_ENTRY( CPUMCTX, rsp),
166 SSMFIELD_ENTRY( CPUMCTX, rflags),
167 SSMFIELD_ENTRY( CPUMCTX, rip),
168 SSMFIELD_ENTRY( CPUMCTX, r8),
169 SSMFIELD_ENTRY( CPUMCTX, r9),
170 SSMFIELD_ENTRY( CPUMCTX, r10),
171 SSMFIELD_ENTRY( CPUMCTX, r11),
172 SSMFIELD_ENTRY( CPUMCTX, r12),
173 SSMFIELD_ENTRY( CPUMCTX, r13),
174 SSMFIELD_ENTRY( CPUMCTX, r14),
175 SSMFIELD_ENTRY( CPUMCTX, r15),
176 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
177 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
178 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
179 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
180 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
181 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
182 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
183 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
184 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
185 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
186 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
187 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
188 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
189 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
190 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
191 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
192 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
193 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
194 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
195 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
196 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
197 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
198 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
199 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
200 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
201 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
202 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
203 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
204 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
205 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
206 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
207 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
208 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
209 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
210 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
211 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
212 SSMFIELD_ENTRY( CPUMCTX, cr0),
213 SSMFIELD_ENTRY( CPUMCTX, cr2),
214 SSMFIELD_ENTRY( CPUMCTX, cr3),
215 SSMFIELD_ENTRY( CPUMCTX, cr4),
216 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
217 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
218 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
219 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
220 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
221 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
222 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
223 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
224 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
225 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
226 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
227 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
228 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
229 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
230 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
231 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
232 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
233 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
234 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
235 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
236 /* msrApicBase is not included here, it resides in the APIC device state. */
237 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
238 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
239 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
240 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
241 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
242 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
243 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
244 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
245 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
246 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
247 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
248 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
249 SSMFIELD_ENTRY_TERM()
250};
251
252/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
253 * registeres changed. */
254static const SSMFIELD g_aCpumX87FieldsMem[] =
255{
256 SSMFIELD_ENTRY( X86FXSTATE, FCW),
257 SSMFIELD_ENTRY( X86FXSTATE, FSW),
258 SSMFIELD_ENTRY( X86FXSTATE, FTW),
259 SSMFIELD_ENTRY( X86FXSTATE, FOP),
260 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
261 SSMFIELD_ENTRY( X86FXSTATE, CS),
262 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
263 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
264 SSMFIELD_ENTRY( X86FXSTATE, DS),
265 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
266 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
267 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
268 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
269 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
270 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
271 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
272 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
273 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
274 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
275 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
276 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
277 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
278 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
279 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
280 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
281 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
282 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
283 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
284 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
285 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
286 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
287 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
288 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
289 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
290 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
291 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
292 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
293 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
294};
295
296/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
297 * registeres changed. */
298static const SSMFIELD g_aCpumCtxFieldsMem[] =
299{
300 SSMFIELD_ENTRY( CPUMCTX, rdi),
301 SSMFIELD_ENTRY( CPUMCTX, rsi),
302 SSMFIELD_ENTRY( CPUMCTX, rbp),
303 SSMFIELD_ENTRY( CPUMCTX, rax),
304 SSMFIELD_ENTRY( CPUMCTX, rbx),
305 SSMFIELD_ENTRY( CPUMCTX, rdx),
306 SSMFIELD_ENTRY( CPUMCTX, rcx),
307 SSMFIELD_ENTRY( CPUMCTX, rsp),
308 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
309 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
310 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
311 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
312 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
313 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
314 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
315 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
316 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
317 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
318 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
319 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
320 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
321 SSMFIELD_ENTRY( CPUMCTX, rflags),
322 SSMFIELD_ENTRY( CPUMCTX, rip),
323 SSMFIELD_ENTRY( CPUMCTX, r8),
324 SSMFIELD_ENTRY( CPUMCTX, r9),
325 SSMFIELD_ENTRY( CPUMCTX, r10),
326 SSMFIELD_ENTRY( CPUMCTX, r11),
327 SSMFIELD_ENTRY( CPUMCTX, r12),
328 SSMFIELD_ENTRY( CPUMCTX, r13),
329 SSMFIELD_ENTRY( CPUMCTX, r14),
330 SSMFIELD_ENTRY( CPUMCTX, r15),
331 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
332 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
333 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
334 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
335 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
336 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
337 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
338 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
339 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
340 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
341 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
342 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
343 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
344 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
345 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
346 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
347 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
348 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
349 SSMFIELD_ENTRY( CPUMCTX, cr0),
350 SSMFIELD_ENTRY( CPUMCTX, cr2),
351 SSMFIELD_ENTRY( CPUMCTX, cr3),
352 SSMFIELD_ENTRY( CPUMCTX, cr4),
353 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
354 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
355 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
356 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
357 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
358 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
359 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
360 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
361 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
362 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
363 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
364 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
365 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
366 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
367 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
368 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
369 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
370 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
371 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
372 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
373 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
374 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
375 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
376 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
377 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
378 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
379 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
380 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
381 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
382 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
383 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
384 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
385 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
386 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
387 SSMFIELD_ENTRY_TERM()
388};
389
390/** Saved state field descriptors for CPUMCTX_VER1_6. */
391static const SSMFIELD g_aCpumX87FieldsV16[] =
392{
393 SSMFIELD_ENTRY( X86FXSTATE, FCW),
394 SSMFIELD_ENTRY( X86FXSTATE, FSW),
395 SSMFIELD_ENTRY( X86FXSTATE, FTW),
396 SSMFIELD_ENTRY( X86FXSTATE, FOP),
397 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
398 SSMFIELD_ENTRY( X86FXSTATE, CS),
399 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
400 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
401 SSMFIELD_ENTRY( X86FXSTATE, DS),
402 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
403 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
404 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
405 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
406 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
407 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
408 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
409 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
410 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
411 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
412 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
413 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
414 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
415 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
416 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
417 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
418 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
419 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
420 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
421 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
422 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
423 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
424 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
425 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
426 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
427 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
428 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
429 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
430 SSMFIELD_ENTRY_TERM()
431};
432
433/** Saved state field descriptors for CPUMCTX_VER1_6. */
434static const SSMFIELD g_aCpumCtxFieldsV16[] =
435{
436 SSMFIELD_ENTRY( CPUMCTX, rdi),
437 SSMFIELD_ENTRY( CPUMCTX, rsi),
438 SSMFIELD_ENTRY( CPUMCTX, rbp),
439 SSMFIELD_ENTRY( CPUMCTX, rax),
440 SSMFIELD_ENTRY( CPUMCTX, rbx),
441 SSMFIELD_ENTRY( CPUMCTX, rdx),
442 SSMFIELD_ENTRY( CPUMCTX, rcx),
443 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
444 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
445 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
446 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
447 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
448 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
449 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
450 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
451 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
452 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
453 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
454 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
455 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
456 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
457 SSMFIELD_ENTRY( CPUMCTX, rflags),
458 SSMFIELD_ENTRY( CPUMCTX, rip),
459 SSMFIELD_ENTRY( CPUMCTX, r8),
460 SSMFIELD_ENTRY( CPUMCTX, r9),
461 SSMFIELD_ENTRY( CPUMCTX, r10),
462 SSMFIELD_ENTRY( CPUMCTX, r11),
463 SSMFIELD_ENTRY( CPUMCTX, r12),
464 SSMFIELD_ENTRY( CPUMCTX, r13),
465 SSMFIELD_ENTRY( CPUMCTX, r14),
466 SSMFIELD_ENTRY( CPUMCTX, r15),
467 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
468 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
469 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
470 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
471 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
472 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
473 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
474 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
475 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
476 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
477 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
478 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
479 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
480 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
481 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
482 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
483 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
484 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
485 SSMFIELD_ENTRY( CPUMCTX, cr0),
486 SSMFIELD_ENTRY( CPUMCTX, cr2),
487 SSMFIELD_ENTRY( CPUMCTX, cr3),
488 SSMFIELD_ENTRY( CPUMCTX, cr4),
489 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
490 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
491 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
492 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
493 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
494 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
495 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
496 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
497 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
498 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
499 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
500 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
501 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
502 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
503 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
504 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
505 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
506 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
507 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
508 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
509 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
510 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
511 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
512 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
513 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
514 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
515 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
516 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
517 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
518 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
519 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
520 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
521 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
522 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
523 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
524 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
525 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
528 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
529 SSMFIELD_ENTRY_TERM()
530};
531
532
533/**
534 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
535 *
536 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
537 * (last instruction pointer, last data pointer, last opcode) except when the ES
538 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
539 * clear these registers there is potential, local FPU leakage from a process
540 * using the FPU to another.
541 *
542 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
543 *
544 * @param pVM Pointer to the VM.
545 */
546static void cpumR3CheckLeakyFpu(PVM pVM)
547{
548 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
549 uint32_t const u32Family = u32CpuVersion >> 8;
550 if ( u32Family >= 6 /* K7 and higher */
551 && ASMIsAmdCpu())
552 {
553 uint32_t cExt = ASMCpuId_EAX(0x80000000);
554 if (ASMIsValidExtRange(cExt))
555 {
556 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
557 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
558 {
559 for (VMCPUID i = 0; i < pVM->cCpus; i++)
560 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
561 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
562 }
563 }
564 }
565}
566
567
568/**
569 * Initializes the CPUM.
570 *
571 * @returns VBox status code.
572 * @param pVM Pointer to the VM.
573 */
574VMMR3DECL(int) CPUMR3Init(PVM pVM)
575{
576 LogFlow(("CPUMR3Init\n"));
577
578 /*
579 * Assert alignment, sizes and tables.
580 */
581 AssertCompileMemberAlignment(VM, cpum.s, 32);
582 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
583 AssertCompileSizeAlignment(CPUMCTX, 64);
584 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
585 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
586 AssertCompileMemberAlignment(VM, cpum, 64);
587 AssertCompileMemberAlignment(VM, aCpus, 64);
588 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
589 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
590#ifdef VBOX_STRICT
591 int rc2 = cpumR3MsrStrictInitChecks();
592 AssertRCReturn(rc2, rc2);
593#endif
594
595 /*
596 * Initialize offsets.
597 */
598
599 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
600 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
601 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
602
603
604 /* Calculate the offset from CPUMCPU to CPUM. */
605 for (VMCPUID i = 0; i < pVM->cCpus; i++)
606 {
607 PVMCPU pVCpu = &pVM->aCpus[i];
608
609 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
610 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
611 }
612
613 /*
614 * Gather info about the host CPU.
615 */
616 if (!ASMHasCpuId())
617 {
618 Log(("The CPU doesn't support CPUID!\n"));
619 return VERR_UNSUPPORTED_CPU;
620 }
621
622 PCPUMCPUIDLEAF paLeaves;
623 uint32_t cLeaves;
624 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
625 AssertLogRelRCReturn(rc, rc);
626
627 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
628 RTMemFree(paLeaves);
629 AssertLogRelRCReturn(rc, rc);
630 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
631
632 /*
633 * Check that the CPU supports the minimum features we require.
634 */
635 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
636 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
637 if (!pVM->cpum.s.HostFeatures.fMmx)
638 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
639 if (!pVM->cpum.s.HostFeatures.fTsc)
640 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
641
642 /*
643 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
644 */
645 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
646 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
647
648 /*
649 * Figure out which XSAVE/XRSTOR features are available on the host.
650 */
651 uint64_t fXStateHostMask = 0;
652 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
653 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
654 {
655 fXStateHostMask = ASMGetXcr0() & ( XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK
656 | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI);
657 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
658 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
659 }
660 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
661 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
662 fXStateHostMask = 0;
663 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx\n", pVM->cpum.s.fXStateHostMask, fXStateHostMask));
664
665 /*
666 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
667 */
668 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
669 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
670 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
671
672 uint8_t *pbXStates;
673 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
674 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
675 AssertLogRelRCReturn(rc, rc);
676
677 for (VMCPUID i = 0; i < pVM->cCpus; i++)
678 {
679 PVMCPU pVCpu = &pVM->aCpus[i];
680
681 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
682 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
683 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
684 pbXStates += cbMaxXState;
685
686 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
687 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
688 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
689 pbXStates += cbMaxXState;
690
691 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
692 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
693 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
694 pbXStates += cbMaxXState;
695
696 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
697 }
698
699 /*
700 * Setup hypervisor startup values.
701 */
702
703 /*
704 * Register saved state data item.
705 */
706 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
707 NULL, cpumR3LiveExec, NULL,
708 NULL, cpumR3SaveExec, NULL,
709 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
710 if (RT_FAILURE(rc))
711 return rc;
712
713 /*
714 * Register info handlers and registers with the debugger facility.
715 */
716 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
717 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
718 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
719 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
720 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
721 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
722
723 rc = cpumR3DbgInit(pVM);
724 if (RT_FAILURE(rc))
725 return rc;
726
727 /*
728 * Check if we need to workaround partial/leaky FPU handling.
729 */
730 cpumR3CheckLeakyFpu(pVM);
731
732 /*
733 * Initialize the Guest CPUID and MSR states.
734 */
735 rc = cpumR3InitCpuIdAndMsrs(pVM);
736 if (RT_FAILURE(rc))
737 return rc;
738 CPUMR3Reset(pVM);
739 return VINF_SUCCESS;
740}
741
742
743/**
744 * Applies relocations to data and code managed by this
745 * component. This function will be called at init and
746 * whenever the VMM need to relocate it self inside the GC.
747 *
748 * The CPUM will update the addresses used by the switcher.
749 *
750 * @param pVM The VM.
751 */
752VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
753{
754 LogFlow(("CPUMR3Relocate\n"));
755
756 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
757 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
758
759 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
760 {
761 PVMCPU pVCpu = &pVM->aCpus[iCpu];
762 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
763 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
764 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
765
766 /* Recheck the guest DRx values in raw-mode. */
767 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
768 }
769}
770
771
772/**
773 * Apply late CPUM property changes based on the fHWVirtEx setting
774 *
775 * @param pVM Pointer to the VM.
776 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
777 */
778VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
779{
780 /*
781 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
782 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
783 * of processors from (cpuid(4).eax >> 26) + 1.
784 *
785 * Note: this code is obsolete, but let's keep it here for reference.
786 * Purpose is valid when we artificially cap the max std id to less than 4.
787 */
788 if (!fHWVirtExEnabled)
789 {
790 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
791 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
792 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
793 }
794}
795
796/**
797 * Terminates the CPUM.
798 *
799 * Termination means cleaning up and freeing all resources,
800 * the VM it self is at this point powered off or suspended.
801 *
802 * @returns VBox status code.
803 * @param pVM Pointer to the VM.
804 */
805VMMR3DECL(int) CPUMR3Term(PVM pVM)
806{
807#ifdef VBOX_WITH_CRASHDUMP_MAGIC
808 for (VMCPUID i = 0; i < pVM->cCpus; i++)
809 {
810 PVMCPU pVCpu = &pVM->aCpus[i];
811 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
812
813 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
814 pVCpu->cpum.s.uMagic = 0;
815 pCtx->dr[5] = 0;
816 }
817#else
818 NOREF(pVM);
819#endif
820 return VINF_SUCCESS;
821}
822
823
824/**
825 * Resets a virtual CPU.
826 *
827 * Used by CPUMR3Reset and CPU hot plugging.
828 *
829 * @param pVM Pointer to the cross context VM structure.
830 * @param pVCpu Pointer to the cross context virtual CPU structure of
831 * the CPU that is being reset. This may differ from the
832 * current EMT.
833 */
834VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
835{
836 /** @todo anything different for VCPU > 0? */
837 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
838
839 /*
840 * Initialize everything to ZERO first.
841 */
842 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
843
844 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
845 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
846 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
847
848 pVCpu->cpum.s.fUseFlags = fUseFlags;
849
850 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
851 pCtx->eip = 0x0000fff0;
852 pCtx->edx = 0x00000600; /* P6 processor */
853 pCtx->eflags.Bits.u1Reserved0 = 1;
854
855 pCtx->cs.Sel = 0xf000;
856 pCtx->cs.ValidSel = 0xf000;
857 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
858 pCtx->cs.u64Base = UINT64_C(0xffff0000);
859 pCtx->cs.u32Limit = 0x0000ffff;
860 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
861 pCtx->cs.Attr.n.u1Present = 1;
862 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
863
864 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
865 pCtx->ds.u32Limit = 0x0000ffff;
866 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
867 pCtx->ds.Attr.n.u1Present = 1;
868 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
869
870 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
871 pCtx->es.u32Limit = 0x0000ffff;
872 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
873 pCtx->es.Attr.n.u1Present = 1;
874 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
875
876 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
877 pCtx->fs.u32Limit = 0x0000ffff;
878 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
879 pCtx->fs.Attr.n.u1Present = 1;
880 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
881
882 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
883 pCtx->gs.u32Limit = 0x0000ffff;
884 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
885 pCtx->gs.Attr.n.u1Present = 1;
886 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
887
888 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
889 pCtx->ss.u32Limit = 0x0000ffff;
890 pCtx->ss.Attr.n.u1Present = 1;
891 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
892 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
893
894 pCtx->idtr.cbIdt = 0xffff;
895 pCtx->gdtr.cbGdt = 0xffff;
896
897 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
898 pCtx->ldtr.u32Limit = 0xffff;
899 pCtx->ldtr.Attr.n.u1Present = 1;
900 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
901
902 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
903 pCtx->tr.u32Limit = 0xffff;
904 pCtx->tr.Attr.n.u1Present = 1;
905 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
906
907 pCtx->dr[6] = X86_DR6_INIT_VAL;
908 pCtx->dr[7] = X86_DR7_INIT_VAL;
909
910 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
911 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
912 pFpuCtx->FCW = 0x37f;
913
914 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
915 IA-32 Processor States Following Power-up, Reset, or INIT */
916 pFpuCtx->MXCSR = 0x1F80;
917 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
918 supports all bits, since a zero value here should be read as 0xffbf. */
919 pCtx->aXcr[0] = XSAVE_C_X87;
920 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
921 {
922 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
923 as we don't know what happened before. (Bother optimize later?) */
924 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
925 }
926
927 /*
928 * MSRs.
929 */
930 /* Init PAT MSR */
931 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
932
933 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
934 * The Intel docs don't mention it. */
935 Assert(!pCtx->msrEFER);
936
937 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
938 is supposed to be here, just trying provide useful/sensible values. */
939 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
940 if (pRange)
941 {
942 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
943 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
944 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
945 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
946 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
947 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
948 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
949 }
950
951 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
952
953 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
954 * called from each EMT while we're getting called by CPUMR3Reset()
955 * iteratively on the same thread. Fix later. */
956#if 0 /** @todo r=bird: This we will do in TM, not here. */
957 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
958 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
959#endif
960
961
962 /* C-state control. Guesses. */
963 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
964
965
966 /*
967 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
968 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
969 */
970 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
971}
972
973
974/**
975 * Resets the CPU.
976 *
977 * @returns VINF_SUCCESS.
978 * @param pVM Pointer to the VM.
979 */
980VMMR3DECL(void) CPUMR3Reset(PVM pVM)
981{
982 for (VMCPUID i = 0; i < pVM->cCpus; i++)
983 {
984 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
985
986#ifdef VBOX_WITH_CRASHDUMP_MAGIC
987 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
988
989 /* Magic marker for searching in crash dumps. */
990 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
991 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
992 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
993#endif
994 }
995}
996
997
998
999
1000/**
1001 * Pass 0 live exec callback.
1002 *
1003 * @returns VINF_SSM_DONT_CALL_AGAIN.
1004 * @param pVM Pointer to the VM.
1005 * @param pSSM The saved state handle.
1006 * @param uPass The pass (0).
1007 */
1008static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1009{
1010 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1011 cpumR3SaveCpuId(pVM, pSSM);
1012 return VINF_SSM_DONT_CALL_AGAIN;
1013}
1014
1015
1016/**
1017 * Execute state save operation.
1018 *
1019 * @returns VBox status code.
1020 * @param pVM Pointer to the VM.
1021 * @param pSSM SSM operation handle.
1022 */
1023static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1024{
1025 /*
1026 * Save.
1027 */
1028 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1029 {
1030 PVMCPU pVCpu = &pVM->aCpus[i];
1031 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper.pXStateR3->x87, sizeof(*pVCpu->cpum.s.Hyper.pXStateR3),
1032 SSMSTRUCT_FLAGS_NO_TAIL_MARKER, g_aCpumX87Fields, NULL);
1033 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1034 SSMSTRUCT_FLAGS_NO_LEAD_MARKER, g_aCpumCtxFields, NULL);
1035 }
1036
1037 SSMR3PutU32(pSSM, pVM->cCpus);
1038 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1039 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1040 {
1041 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1042
1043 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest.pXStateR3->x87, sizeof(*pVCpu->cpum.s.Guest.pXStateR3),
1044 SSMSTRUCT_FLAGS_NO_TAIL_MARKER, g_aCpumX87Fields, NULL);
1045 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest),
1046 SSMSTRUCT_FLAGS_NO_LEAD_MARKER, g_aCpumCtxFields, NULL);
1047 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1048 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1049 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1050 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1051 }
1052
1053 cpumR3SaveCpuId(pVM, pSSM);
1054 return VINF_SUCCESS;
1055}
1056
1057
1058/**
1059 * @copydoc FNSSMINTLOADPREP
1060 */
1061static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1062{
1063 NOREF(pSSM);
1064 pVM->cpum.s.fPendingRestore = true;
1065 return VINF_SUCCESS;
1066}
1067
1068
1069/**
1070 * @copydoc FNSSMINTLOADEXEC
1071 */
1072static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1073{
1074 /*
1075 * Validate version.
1076 */
1077 if ( uVersion != CPUM_SAVED_STATE_VERSION
1078 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1079 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1080 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1081 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1082 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1083 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1084 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1085 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1086 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1087 {
1088 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1089 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1090 }
1091
1092 if (uPass == SSM_PASS_FINAL)
1093 {
1094 /*
1095 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1096 * really old SSM file versions.)
1097 */
1098 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1099 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1100 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1101 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1102
1103 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1104 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1105 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1106 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1107 {
1108 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1109 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1110 }
1111 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1112 {
1113 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1114 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1115 }
1116
1117 /*
1118 * Restore.
1119 */
1120 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1121 {
1122 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1123 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1124 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1125 /** @todo drop the FPU bits here! */
1126 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper.pXStateR3->x87, sizeof(pVCpu->cpum.s.Hyper.pXStateR3->x87),
1127 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1128 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1129 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1130 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1131 pVCpu->cpum.s.Hyper.rsp = uRSP;
1132 }
1133
1134 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1135 {
1136 uint32_t cCpus;
1137 int rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1138 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1139 VERR_SSM_UNEXPECTED_DATA);
1140 }
1141 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1142 || pVM->cCpus == 1,
1143 ("cCpus=%u\n", pVM->cCpus),
1144 VERR_SSM_UNEXPECTED_DATA);
1145
1146 uint32_t cbMsrs = 0;
1147 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1148 {
1149 int rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1150 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1151 VERR_SSM_UNEXPECTED_DATA);
1152 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1153 VERR_SSM_UNEXPECTED_DATA);
1154 }
1155
1156 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1157 {
1158 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1159 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest.pXStateR3->x87, sizeof(pVCpu->cpum.s.Guest.pXStateR3->x87),
1160 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1161 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Guest, sizeof(pVCpu->cpum.s.Guest),
1162 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1163 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1164 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1165 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1166 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1167 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1168 {
1169 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1170 SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1171 }
1172
1173 /* REM and other may have cleared must-be-one fields in DR6 and
1174 DR7, fix these. */
1175 pVCpu->cpum.s.Guest.dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1176 pVCpu->cpum.s.Guest.dr[6] |= X86_DR6_RA1_MASK;
1177 pVCpu->cpum.s.Guest.dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1178 pVCpu->cpum.s.Guest.dr[7] |= X86_DR7_RA1_MASK;
1179 }
1180
1181 /* Older states does not have the internal selector register flags
1182 and valid selector value. Supply those. */
1183 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1184 {
1185 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1186 {
1187 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1188 bool const fValid = HMIsEnabled(pVM)
1189 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1190 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1191 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1192 if (fValid)
1193 {
1194 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1195 {
1196 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1197 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1198 }
1199
1200 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1201 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1202 }
1203 else
1204 {
1205 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1206 {
1207 paSelReg[iSelReg].fFlags = 0;
1208 paSelReg[iSelReg].ValidSel = 0;
1209 }
1210
1211 /* This might not be 104% correct, but I think it's close
1212 enough for all practical purposes... (REM always loaded
1213 LDTR registers.) */
1214 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1215 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1216 }
1217 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1218 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1219 }
1220 }
1221
1222 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1223 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1224 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1225 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1226 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1227
1228 /*
1229 * A quick sanity check.
1230 */
1231 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1232 {
1233 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1234 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1235 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1236 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1237 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1238 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1239 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1240 }
1241 }
1242
1243 pVM->cpum.s.fPendingRestore = false;
1244
1245 /*
1246 * Guest CPUIDs.
1247 */
1248 if (uVersion > CPUM_SAVED_STATE_VERSION_VER3_0)
1249 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1250
1251 /** @todo Merge the code below into cpumR3LoadCpuId when we've found out what is
1252 * actually required. */
1253
1254 /*
1255 * Restore the CPUID leaves.
1256 *
1257 * Note that we support restoring less than the current amount of standard
1258 * leaves because we've been allowed more is newer version of VBox.
1259 */
1260 uint32_t cElements;
1261 int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1262 if (cElements > RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmStd))
1263 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1264 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmStd[0], cElements*sizeof(pVM->cpum.s.aGuestCpuIdPatmStd[0]));
1265
1266 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1267 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmExt))
1268 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1269 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmExt[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmExt));
1270
1271 rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
1272 if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdPatmCentaur))
1273 return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1274 SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdPatmCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdPatmCentaur));
1275
1276 SSMR3GetMem(pSSM, &pVM->cpum.s.GuestInfo.DefCpuId, sizeof(pVM->cpum.s.GuestInfo.DefCpuId));
1277
1278 /*
1279 * Check that the basic cpuid id information is unchanged.
1280 */
1281 /** @todo we should check the 64 bits capabilities too! */
1282 uint32_t au32CpuId[8] = {0,0,0,0, 0,0,0,0};
1283 ASMCpuIdExSlow(0, 0, 0, 0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
1284 ASMCpuIdExSlow(1, 0, 0, 0, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
1285 uint32_t au32CpuIdSaved[8];
1286 rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
1287 if (RT_SUCCESS(rc))
1288 {
1289 /* Ignore CPU stepping. */
1290 au32CpuId[4] &= 0xfffffff0;
1291 au32CpuIdSaved[4] &= 0xfffffff0;
1292
1293 /* Ignore APIC ID (AMD specs). */
1294 au32CpuId[5] &= ~0xff000000;
1295 au32CpuIdSaved[5] &= ~0xff000000;
1296
1297 /* Ignore the number of Logical CPUs (AMD specs). */
1298 au32CpuId[5] &= ~0x00ff0000;
1299 au32CpuIdSaved[5] &= ~0x00ff0000;
1300
1301 /* Ignore some advanced capability bits, that we don't expose to the guest. */
1302 au32CpuId[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1303 | X86_CPUID_FEATURE_ECX_VMX
1304 | X86_CPUID_FEATURE_ECX_SMX
1305 | X86_CPUID_FEATURE_ECX_EST
1306 | X86_CPUID_FEATURE_ECX_TM2
1307 | X86_CPUID_FEATURE_ECX_CNTXID
1308 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1309 | X86_CPUID_FEATURE_ECX_PDCM
1310 | X86_CPUID_FEATURE_ECX_DCA
1311 | X86_CPUID_FEATURE_ECX_X2APIC
1312 );
1313 au32CpuIdSaved[6] &= ~( X86_CPUID_FEATURE_ECX_DTES64
1314 | X86_CPUID_FEATURE_ECX_VMX
1315 | X86_CPUID_FEATURE_ECX_SMX
1316 | X86_CPUID_FEATURE_ECX_EST
1317 | X86_CPUID_FEATURE_ECX_TM2
1318 | X86_CPUID_FEATURE_ECX_CNTXID
1319 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1320 | X86_CPUID_FEATURE_ECX_PDCM
1321 | X86_CPUID_FEATURE_ECX_DCA
1322 | X86_CPUID_FEATURE_ECX_X2APIC
1323 );
1324
1325 /* Make sure we don't forget to update the masks when enabling
1326 * features in the future.
1327 */
1328 AssertRelease(!(pVM->cpum.s.aGuestCpuIdPatmStd[1].uEcx &
1329 ( X86_CPUID_FEATURE_ECX_DTES64
1330 | X86_CPUID_FEATURE_ECX_VMX
1331 | X86_CPUID_FEATURE_ECX_SMX
1332 | X86_CPUID_FEATURE_ECX_EST
1333 | X86_CPUID_FEATURE_ECX_TM2
1334 | X86_CPUID_FEATURE_ECX_CNTXID
1335 | X86_CPUID_FEATURE_ECX_TPRUPDATE
1336 | X86_CPUID_FEATURE_ECX_PDCM
1337 | X86_CPUID_FEATURE_ECX_DCA
1338 | X86_CPUID_FEATURE_ECX_X2APIC
1339 )));
1340 /* do the compare */
1341 if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
1342 {
1343 if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
1344 LogRel(("cpumR3LoadExec: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
1345 "Saved=%.*Rhxs\n"
1346 "Real =%.*Rhxs\n",
1347 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1348 sizeof(au32CpuId), au32CpuId));
1349 else
1350 {
1351 LogRel(("cpumR3LoadExec: CpuId mismatch!\n"
1352 "Saved=%.*Rhxs\n"
1353 "Real =%.*Rhxs\n",
1354 sizeof(au32CpuIdSaved), au32CpuIdSaved,
1355 sizeof(au32CpuId), au32CpuId));
1356 rc = VERR_SSM_LOAD_CPUID_MISMATCH;
1357 }
1358 }
1359 }
1360
1361 return rc;
1362}
1363
1364
1365/**
1366 * @copydoc FNSSMINTLOADPREP
1367 */
1368static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1369{
1370 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1371 return VINF_SUCCESS;
1372
1373 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1374 if (pVM->cpum.s.fPendingRestore)
1375 {
1376 LogRel(("CPUM: Missing state!\n"));
1377 return VERR_INTERNAL_ERROR_2;
1378 }
1379
1380 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1381 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1382 {
1383 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1384
1385 /* Notify PGM of the NXE states in case they've changed. */
1386 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1387
1388 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
1389 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
1390
1391 /* During init. this is done in CPUMR3InitCompleted(). */
1392 if (fSupportsLongMode)
1393 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1394 }
1395 return VINF_SUCCESS;
1396}
1397
1398
1399/**
1400 * Checks if the CPUM state restore is still pending.
1401 *
1402 * @returns true / false.
1403 * @param pVM Pointer to the VM.
1404 */
1405VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1406{
1407 return pVM->cpum.s.fPendingRestore;
1408}
1409
1410
1411/**
1412 * Formats the EFLAGS value into mnemonics.
1413 *
1414 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1415 * @param efl The EFLAGS value.
1416 */
1417static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1418{
1419 /*
1420 * Format the flags.
1421 */
1422 static const struct
1423 {
1424 const char *pszSet; const char *pszClear; uint32_t fFlag;
1425 } s_aFlags[] =
1426 {
1427 { "vip",NULL, X86_EFL_VIP },
1428 { "vif",NULL, X86_EFL_VIF },
1429 { "ac", NULL, X86_EFL_AC },
1430 { "vm", NULL, X86_EFL_VM },
1431 { "rf", NULL, X86_EFL_RF },
1432 { "nt", NULL, X86_EFL_NT },
1433 { "ov", "nv", X86_EFL_OF },
1434 { "dn", "up", X86_EFL_DF },
1435 { "ei", "di", X86_EFL_IF },
1436 { "tf", NULL, X86_EFL_TF },
1437 { "nt", "pl", X86_EFL_SF },
1438 { "nz", "zr", X86_EFL_ZF },
1439 { "ac", "na", X86_EFL_AF },
1440 { "po", "pe", X86_EFL_PF },
1441 { "cy", "nc", X86_EFL_CF },
1442 };
1443 char *psz = pszEFlags;
1444 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1445 {
1446 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1447 if (pszAdd)
1448 {
1449 strcpy(psz, pszAdd);
1450 psz += strlen(pszAdd);
1451 *psz++ = ' ';
1452 }
1453 }
1454 psz[-1] = '\0';
1455}
1456
1457
1458/**
1459 * Formats a full register dump.
1460 *
1461 * @param pVM Pointer to the VM.
1462 * @param pCtx The context to format.
1463 * @param pCtxCore The context core to format.
1464 * @param pHlp Output functions.
1465 * @param enmType The dump type.
1466 * @param pszPrefix Register name prefix.
1467 */
1468static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1469 const char *pszPrefix)
1470{
1471 NOREF(pVM);
1472
1473 /*
1474 * Format the EFLAGS.
1475 */
1476 uint32_t efl = pCtxCore->eflags.u32;
1477 char szEFlags[80];
1478 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1479
1480 /*
1481 * Format the registers.
1482 */
1483 switch (enmType)
1484 {
1485 case CPUMDUMPTYPE_TERSE:
1486 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1487 pHlp->pfnPrintf(pHlp,
1488 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1489 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1490 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1491 "%sr14=%016RX64 %sr15=%016RX64\n"
1492 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1493 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1494 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1495 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1496 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1497 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1498 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1499 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1500 else
1501 pHlp->pfnPrintf(pHlp,
1502 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1503 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1504 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1505 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1506 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1507 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1508 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1509 break;
1510
1511 case CPUMDUMPTYPE_DEFAULT:
1512 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1513 pHlp->pfnPrintf(pHlp,
1514 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1515 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1516 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1517 "%sr14=%016RX64 %sr15=%016RX64\n"
1518 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1519 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1520 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1521 ,
1522 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1523 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1524 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1525 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1526 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1527 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1528 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1529 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1530 else
1531 pHlp->pfnPrintf(pHlp,
1532 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1533 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1534 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1535 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1536 ,
1537 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1538 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1539 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1540 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1541 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1542 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1543 break;
1544
1545 case CPUMDUMPTYPE_VERBOSE:
1546 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1547 pHlp->pfnPrintf(pHlp,
1548 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1549 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1550 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1551 "%sr14=%016RX64 %sr15=%016RX64\n"
1552 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1553 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1554 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1555 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1556 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1557 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1558 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1559 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1560 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1561 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1562 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1563 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1564 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1565 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1566 ,
1567 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1568 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1569 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1570 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1571 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1572 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1573 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1574 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1575 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1576 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1577 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1578 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1579 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1580 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1581 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1582 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1583 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1584 else
1585 pHlp->pfnPrintf(pHlp,
1586 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1587 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1588 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1589 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1590 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1591 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1592 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1593 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1594 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1595 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1596 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1597 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1598 ,
1599 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1600 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1601 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1602 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1603 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1604 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1605 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1606 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1607 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1608 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1609 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1610 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1611
1612 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1613 pHlp->pfnPrintf(pHlp,
1614 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1615 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1616 ,
1617 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1618 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1619 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1620 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1621 );
1622 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1623 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1624 {
1625 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1626 unsigned uTag = pFpuCtx->FTW & (1 << iFPR) ? 1 : 0;
1627 char chSign = pFpuCtx->aRegs[0].au16[4] & 0x8000 ? '-' : '+';
1628 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[0].au64[0] >> 63);
1629 uint64_t u64Fraction = pFpuCtx->aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
1630 unsigned uExponent = pFpuCtx->aRegs[0].au16[4] & 0x7fff;
1631 /** @todo This isn't entirenly correct and needs more work! */
1632 pHlp->pfnPrintf(pHlp,
1633 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u",
1634 pszPrefix, iST, pszPrefix, iFPR,
1635 pFpuCtx->aRegs[0].au16[4], pFpuCtx->aRegs[0].au32[1], pFpuCtx->aRegs[0].au32[0],
1636 uTag, chSign, iInteger, u64Fraction, uExponent);
1637 if (pFpuCtx->aRegs[0].au16[5] || pFpuCtx->aRegs[0].au16[6] || pFpuCtx->aRegs[0].au16[7])
1638 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1639 pFpuCtx->aRegs[0].au16[5], pFpuCtx->aRegs[0].au16[6], pFpuCtx->aRegs[0].au16[7]);
1640 else
1641 pHlp->pfnPrintf(pHlp, "\n");
1642 }
1643 for (unsigned iXMM = 0; iXMM < RT_ELEMENTS(pFpuCtx->aXMM); iXMM++)
1644 pHlp->pfnPrintf(pHlp,
1645 iXMM & 1
1646 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1647 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1648 pszPrefix, iXMM, iXMM < 10 ? " " : "",
1649 pFpuCtx->aXMM[iXMM].au32[3],
1650 pFpuCtx->aXMM[iXMM].au32[2],
1651 pFpuCtx->aXMM[iXMM].au32[1],
1652 pFpuCtx->aXMM[iXMM].au32[0]);
1653 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1654 if (pFpuCtx->au32RsrvdRest[i])
1655 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
1656 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1657
1658 pHlp->pfnPrintf(pHlp,
1659 "%sEFER =%016RX64\n"
1660 "%sPAT =%016RX64\n"
1661 "%sSTAR =%016RX64\n"
1662 "%sCSTAR =%016RX64\n"
1663 "%sLSTAR =%016RX64\n"
1664 "%sSFMASK =%016RX64\n"
1665 "%sKERNELGSBASE =%016RX64\n",
1666 pszPrefix, pCtx->msrEFER,
1667 pszPrefix, pCtx->msrPAT,
1668 pszPrefix, pCtx->msrSTAR,
1669 pszPrefix, pCtx->msrCSTAR,
1670 pszPrefix, pCtx->msrLSTAR,
1671 pszPrefix, pCtx->msrSFMASK,
1672 pszPrefix, pCtx->msrKERNELGSBASE);
1673 break;
1674 }
1675}
1676
1677
1678/**
1679 * Display all cpu states and any other cpum info.
1680 *
1681 * @param pVM Pointer to the VM.
1682 * @param pHlp The info helper functions.
1683 * @param pszArgs Arguments, ignored.
1684 */
1685static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1686{
1687 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1688 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1689 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1690 cpumR3InfoHost(pVM, pHlp, pszArgs);
1691}
1692
1693
1694/**
1695 * Parses the info argument.
1696 *
1697 * The argument starts with 'verbose', 'terse' or 'default' and then
1698 * continues with the comment string.
1699 *
1700 * @param pszArgs The pointer to the argument string.
1701 * @param penmType Where to store the dump type request.
1702 * @param ppszComment Where to store the pointer to the comment string.
1703 */
1704static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1705{
1706 if (!pszArgs)
1707 {
1708 *penmType = CPUMDUMPTYPE_DEFAULT;
1709 *ppszComment = "";
1710 }
1711 else
1712 {
1713 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
1714 {
1715 pszArgs += 7;
1716 *penmType = CPUMDUMPTYPE_VERBOSE;
1717 }
1718 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
1719 {
1720 pszArgs += 5;
1721 *penmType = CPUMDUMPTYPE_TERSE;
1722 }
1723 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
1724 {
1725 pszArgs += 7;
1726 *penmType = CPUMDUMPTYPE_DEFAULT;
1727 }
1728 else
1729 *penmType = CPUMDUMPTYPE_DEFAULT;
1730 *ppszComment = RTStrStripL(pszArgs);
1731 }
1732}
1733
1734
1735/**
1736 * Display the guest cpu state.
1737 *
1738 * @param pVM Pointer to the VM.
1739 * @param pHlp The info helper functions.
1740 * @param pszArgs Arguments, ignored.
1741 */
1742static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1743{
1744 CPUMDUMPTYPE enmType;
1745 const char *pszComment;
1746 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1747
1748 /* @todo SMP support! */
1749 PVMCPU pVCpu = VMMGetCpu(pVM);
1750 if (!pVCpu)
1751 pVCpu = &pVM->aCpus[0];
1752
1753 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1754
1755 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1756 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1757}
1758
1759
1760/**
1761 * Display the current guest instruction
1762 *
1763 * @param pVM Pointer to the VM.
1764 * @param pHlp The info helper functions.
1765 * @param pszArgs Arguments, ignored.
1766 */
1767static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1768{
1769 NOREF(pszArgs);
1770
1771 /** @todo SMP support! */
1772 PVMCPU pVCpu = VMMGetCpu(pVM);
1773 if (!pVCpu)
1774 pVCpu = &pVM->aCpus[0];
1775
1776 char szInstruction[256];
1777 szInstruction[0] = '\0';
1778 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
1779 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
1780}
1781
1782
1783/**
1784 * Display the hypervisor cpu state.
1785 *
1786 * @param pVM Pointer to the VM.
1787 * @param pHlp The info helper functions.
1788 * @param pszArgs Arguments, ignored.
1789 */
1790static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1791{
1792 CPUMDUMPTYPE enmType;
1793 const char *pszComment;
1794 /* @todo SMP */
1795 PVMCPU pVCpu = &pVM->aCpus[0];
1796
1797 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1798 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
1799 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
1800 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
1801}
1802
1803
1804/**
1805 * Display the host cpu state.
1806 *
1807 * @param pVM Pointer to the VM.
1808 * @param pHlp The info helper functions.
1809 * @param pszArgs Arguments, ignored.
1810 */
1811static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1812{
1813 CPUMDUMPTYPE enmType;
1814 const char *pszComment;
1815 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1816 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
1817
1818 /*
1819 * Format the EFLAGS.
1820 */
1821 /* @todo SMP */
1822 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
1823#if HC_ARCH_BITS == 32
1824 uint32_t efl = pCtx->eflags.u32;
1825#else
1826 uint64_t efl = pCtx->rflags;
1827#endif
1828 char szEFlags[80];
1829 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1830
1831 /*
1832 * Format the registers.
1833 */
1834#if HC_ARCH_BITS == 32
1835# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1836 if (!(pCtx->efer & MSR_K6_EFER_LMA))
1837# endif
1838 {
1839 pHlp->pfnPrintf(pHlp,
1840 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
1841 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
1842 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
1843 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
1844 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
1845 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1846 ,
1847 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
1848 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
1849 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
1850 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
1851 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
1852 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
1853 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1854 }
1855# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
1856 else
1857# endif
1858#endif
1859#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1860 {
1861 pHlp->pfnPrintf(pHlp,
1862 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
1863 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
1864 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
1865 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
1866 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
1867 "r14=%016RX64 r15=%016RX64\n"
1868 "iopl=%d %31s\n"
1869 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
1870 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
1871 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
1872 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
1873 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
1874 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
1875 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
1876 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
1877 ,
1878 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
1879 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
1880 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
1881 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
1882 pCtx->r11, pCtx->r12, pCtx->r13,
1883 pCtx->r14, pCtx->r15,
1884 X86_EFL_GET_IOPL(efl), szEFlags,
1885 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
1886 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
1887 pCtx->cr4, pCtx->ldtr, pCtx->tr,
1888 pCtx->dr0, pCtx->dr1, pCtx->dr2,
1889 pCtx->dr3, pCtx->dr6, pCtx->dr7,
1890 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
1891 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
1892 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
1893 }
1894#endif
1895}
1896
1897/**
1898 * Structure used when disassembling and instructions in DBGF.
1899 * This is used so the reader function can get the stuff it needs.
1900 */
1901typedef struct CPUMDISASSTATE
1902{
1903 /** Pointer to the CPU structure. */
1904 PDISCPUSTATE pCpu;
1905 /** Pointer to the VM. */
1906 PVM pVM;
1907 /** Pointer to the VMCPU. */
1908 PVMCPU pVCpu;
1909 /** Pointer to the first byte in the segment. */
1910 RTGCUINTPTR GCPtrSegBase;
1911 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
1912 RTGCUINTPTR GCPtrSegEnd;
1913 /** The size of the segment minus 1. */
1914 RTGCUINTPTR cbSegLimit;
1915 /** Pointer to the current page - R3 Ptr. */
1916 void const *pvPageR3;
1917 /** Pointer to the current page - GC Ptr. */
1918 RTGCPTR pvPageGC;
1919 /** The lock information that PGMPhysReleasePageMappingLock needs. */
1920 PGMPAGEMAPLOCK PageMapLock;
1921 /** Whether the PageMapLock is valid or not. */
1922 bool fLocked;
1923 /** 64 bits mode or not. */
1924 bool f64Bits;
1925} CPUMDISASSTATE, *PCPUMDISASSTATE;
1926
1927
1928/**
1929 * @callback_method_impl{FNDISREADBYTES}
1930 */
1931static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
1932{
1933 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
1934 for (;;)
1935 {
1936 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
1937
1938 /*
1939 * Need to update the page translation?
1940 */
1941 if ( !pState->pvPageR3
1942 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
1943 {
1944 int rc = VINF_SUCCESS;
1945
1946 /* translate the address */
1947 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
1948 if ( !HMIsEnabled(pState->pVM)
1949 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
1950 {
1951 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
1952 if (!pState->pvPageR3)
1953 rc = VERR_INVALID_POINTER;
1954 }
1955 else
1956 {
1957 /* Release mapping lock previously acquired. */
1958 if (pState->fLocked)
1959 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
1960 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
1961 pState->fLocked = RT_SUCCESS_NP(rc);
1962 }
1963 if (RT_FAILURE(rc))
1964 {
1965 pState->pvPageR3 = NULL;
1966 return rc;
1967 }
1968 }
1969
1970 /*
1971 * Check the segment limit.
1972 */
1973 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
1974 return VERR_OUT_OF_SELECTOR_BOUNDS;
1975
1976 /*
1977 * Calc how much we can read.
1978 */
1979 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
1980 if (!pState->f64Bits)
1981 {
1982 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
1983 if (cb > cbSeg && cbSeg)
1984 cb = cbSeg;
1985 }
1986 if (cb > cbMaxRead)
1987 cb = cbMaxRead;
1988
1989 /*
1990 * Read and advance or exit.
1991 */
1992 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
1993 offInstr += (uint8_t)cb;
1994 if (cb >= cbMinRead)
1995 {
1996 pDis->cbCachedInstr = offInstr;
1997 return VINF_SUCCESS;
1998 }
1999 cbMinRead -= (uint8_t)cb;
2000 cbMaxRead -= (uint8_t)cb;
2001 }
2002}
2003
2004
2005/**
2006 * Disassemble an instruction and return the information in the provided structure.
2007 *
2008 * @returns VBox status code.
2009 * @param pVM Pointer to the VM.
2010 * @param pVCpu Pointer to the VMCPU.
2011 * @param pCtx Pointer to the guest CPU context.
2012 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2013 * @param pCpu Disassembly state.
2014 * @param pszPrefix String prefix for logging (debug only).
2015 *
2016 */
2017VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2018{
2019 CPUMDISASSTATE State;
2020 int rc;
2021
2022 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2023 State.pCpu = pCpu;
2024 State.pvPageGC = 0;
2025 State.pvPageR3 = NULL;
2026 State.pVM = pVM;
2027 State.pVCpu = pVCpu;
2028 State.fLocked = false;
2029 State.f64Bits = false;
2030
2031 /*
2032 * Get selector information.
2033 */
2034 DISCPUMODE enmDisCpuMode;
2035 if ( (pCtx->cr0 & X86_CR0_PE)
2036 && pCtx->eflags.Bits.u1VM == 0)
2037 {
2038 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2039 {
2040# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2041 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2042# endif
2043 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2044 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2045 }
2046 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2047 State.GCPtrSegBase = pCtx->cs.u64Base;
2048 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2049 State.cbSegLimit = pCtx->cs.u32Limit;
2050 enmDisCpuMode = (State.f64Bits)
2051 ? DISCPUMODE_64BIT
2052 : pCtx->cs.Attr.n.u1DefBig
2053 ? DISCPUMODE_32BIT
2054 : DISCPUMODE_16BIT;
2055 }
2056 else
2057 {
2058 /* real or V86 mode */
2059 enmDisCpuMode = DISCPUMODE_16BIT;
2060 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2061 State.GCPtrSegEnd = 0xFFFFFFFF;
2062 State.cbSegLimit = 0xFFFFFFFF;
2063 }
2064
2065 /*
2066 * Disassemble the instruction.
2067 */
2068 uint32_t cbInstr;
2069#ifndef LOG_ENABLED
2070 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2071 if (RT_SUCCESS(rc))
2072 {
2073#else
2074 char szOutput[160];
2075 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2076 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2077 if (RT_SUCCESS(rc))
2078 {
2079 /* log it */
2080 if (pszPrefix)
2081 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2082 else
2083 Log(("%s", szOutput));
2084#endif
2085 rc = VINF_SUCCESS;
2086 }
2087 else
2088 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2089
2090 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2091 if (State.fLocked)
2092 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2093
2094 return rc;
2095}
2096
2097
2098
2099/**
2100 * API for controlling a few of the CPU features found in CR4.
2101 *
2102 * Currently only X86_CR4_TSD is accepted as input.
2103 *
2104 * @returns VBox status code.
2105 *
2106 * @param pVM Pointer to the VM.
2107 * @param fOr The CR4 OR mask.
2108 * @param fAnd The CR4 AND mask.
2109 */
2110VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2111{
2112 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2113 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2114
2115 pVM->cpum.s.CR4.OrMask &= fAnd;
2116 pVM->cpum.s.CR4.OrMask |= fOr;
2117
2118 return VINF_SUCCESS;
2119}
2120
2121
2122/**
2123 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2124 *
2125 * Only REM should ever call this function!
2126 *
2127 * @returns The changed flags.
2128 * @param pVCpu Pointer to the VMCPU.
2129 * @param puCpl Where to return the current privilege level (CPL).
2130 */
2131VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2132{
2133 Assert(!pVCpu->cpum.s.fRawEntered);
2134 Assert(!pVCpu->cpum.s.fRemEntered);
2135
2136 /*
2137 * Get the CPL first.
2138 */
2139 *puCpl = CPUMGetGuestCPL(pVCpu);
2140
2141 /*
2142 * Get and reset the flags.
2143 */
2144 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2145 pVCpu->cpum.s.fChanged = 0;
2146
2147 /** @todo change the switcher to use the fChanged flags. */
2148 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2149 {
2150 fFlags |= CPUM_CHANGED_FPU_REM;
2151 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2152 }
2153
2154 pVCpu->cpum.s.fRemEntered = true;
2155 return fFlags;
2156}
2157
2158
2159/**
2160 * Leaves REM.
2161 *
2162 * @param pVCpu Pointer to the VMCPU.
2163 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2164 * registers.
2165 */
2166VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2167{
2168 Assert(!pVCpu->cpum.s.fRawEntered);
2169 Assert(pVCpu->cpum.s.fRemEntered);
2170
2171 pVCpu->cpum.s.fRemEntered = false;
2172}
2173
2174
2175/**
2176 * Called when the ring-3 init phase completes.
2177 *
2178 * @returns VBox status code.
2179 * @param pVM Pointer to the VM.
2180 */
2181VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
2182{
2183 /*
2184 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2185 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2186 */
2187 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2188 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2189 {
2190 PVMCPU pVCpu = &pVM->aCpus[i];
2191
2192 /* Cache the APIC base (from the APIC device) once it has been initialized. */
2193 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
2194 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVCpu->cpum.s.Guest.msrApicBase));
2195
2196 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2197 if (fSupportsLongMode)
2198 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2199 }
2200 return VINF_SUCCESS;
2201}
2202
2203
2204/**
2205 * Called when the ring-0 init phases comleted.
2206 *
2207 * @param pVM Pointer to the VM.
2208 */
2209VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2210{
2211 /*
2212 * Log the cpuid.
2213 */
2214 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2215 RTCPUSET OnlineSet;
2216 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2217 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2218 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2219 RTCPUID cCores = RTMpGetCoreCount();
2220 if (cCores)
2221 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
2222 LogRel(("************************* CPUID dump ************************\n"));
2223 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2224 LogRel(("\n"));
2225 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
2226 RTLogRelSetBuffering(fOldBuffered);
2227 LogRel(("******************** End of CPUID dump **********************\n"));
2228}
2229
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette