VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 55890

Last change on this file since 55890 was 55736, checked in by vboxsync, 10 years ago

CPUM.cpp/info: Missed on place where CPUMCTX_XSAVE_C_PTR should be applied.
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1/* $Id: CPUM.cpp 55736 2015-05-07 18:05:20Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_CPUM
38#include <VBox/vmm/cpum.h>
39#include <VBox/vmm/cpumdis.h>
40#include <VBox/vmm/cpumctx-v1_6.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/selm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/patm.h>
48#include <VBox/vmm/hm.h>
49#include <VBox/vmm/ssm.h>
50#include "CPUMInternal.h"
51#include <VBox/vmm/vm.h>
52
53#include <VBox/param.h>
54#include <VBox/dis.h>
55#include <VBox/err.h>
56#include <VBox/log.h>
57#include <iprt/asm-amd64-x86.h>
58#include <iprt/assert.h>
59#include <iprt/cpuset.h>
60#include <iprt/mem.h>
61#include <iprt/mp.h>
62#include <iprt/string.h>
63#include "internal/pgm.h"
64
65
66/*******************************************************************************
67* Defined Constants And Macros *
68*******************************************************************************/
69/**
70 * This was used in the saved state up to the early life of version 14.
71 *
72 * It indicates that we may have some out-of-sync hidden segement registers.
73 * It is only relevant for raw-mode.
74 */
75#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
76
77
78/*******************************************************************************
79* Structures and Typedefs *
80*******************************************************************************/
81
82/**
83 * What kind of cpu info dump to perform.
84 */
85typedef enum CPUMDUMPTYPE
86{
87 CPUMDUMPTYPE_TERSE,
88 CPUMDUMPTYPE_DEFAULT,
89 CPUMDUMPTYPE_VERBOSE
90} CPUMDUMPTYPE;
91/** Pointer to a cpu info dump type. */
92typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
93
94
95/*******************************************************************************
96* Internal Functions *
97*******************************************************************************/
98static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
99static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
100static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
101static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
102static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
103static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108
109
110/*******************************************************************************
111* Global Variables *
112*******************************************************************************/
113/** Saved state field descriptors for CPUMCTX. */
114static const SSMFIELD g_aCpumCtxFields[] =
115{
116 SSMFIELD_ENTRY( CPUMCTX, rdi),
117 SSMFIELD_ENTRY( CPUMCTX, rsi),
118 SSMFIELD_ENTRY( CPUMCTX, rbp),
119 SSMFIELD_ENTRY( CPUMCTX, rax),
120 SSMFIELD_ENTRY( CPUMCTX, rbx),
121 SSMFIELD_ENTRY( CPUMCTX, rdx),
122 SSMFIELD_ENTRY( CPUMCTX, rcx),
123 SSMFIELD_ENTRY( CPUMCTX, rsp),
124 SSMFIELD_ENTRY( CPUMCTX, rflags),
125 SSMFIELD_ENTRY( CPUMCTX, rip),
126 SSMFIELD_ENTRY( CPUMCTX, r8),
127 SSMFIELD_ENTRY( CPUMCTX, r9),
128 SSMFIELD_ENTRY( CPUMCTX, r10),
129 SSMFIELD_ENTRY( CPUMCTX, r11),
130 SSMFIELD_ENTRY( CPUMCTX, r12),
131 SSMFIELD_ENTRY( CPUMCTX, r13),
132 SSMFIELD_ENTRY( CPUMCTX, r14),
133 SSMFIELD_ENTRY( CPUMCTX, r15),
134 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
135 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
136 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
137 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
138 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
139 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
140 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
141 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
142 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
143 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
144 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
145 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
146 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
147 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
148 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
149 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
150 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
151 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
152 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
153 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
154 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
155 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
156 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
157 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
158 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
159 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
160 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
161 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
162 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
163 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
164 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
165 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
166 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
167 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
168 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
169 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
170 SSMFIELD_ENTRY( CPUMCTX, cr0),
171 SSMFIELD_ENTRY( CPUMCTX, cr2),
172 SSMFIELD_ENTRY( CPUMCTX, cr3),
173 SSMFIELD_ENTRY( CPUMCTX, cr4),
174 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
175 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
176 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
177 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
178 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
179 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
180 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
181 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
182 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
183 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
184 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
185 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
186 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
187 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
188 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
189 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
190 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
191 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
192 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
193 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
194 /* msrApicBase is not included here, it resides in the APIC device state. */
195 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
196 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
197 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
198 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
199 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
200 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
201 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
202 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
203 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
204 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
205 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
206 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
207 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
208 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
209 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
210 SSMFIELD_ENTRY_TERM()
211};
212
213/** Saved state field descriptors for CPUMCTX. */
214static const SSMFIELD g_aCpumX87Fields[] =
215{
216 SSMFIELD_ENTRY( X86FXSTATE, FCW),
217 SSMFIELD_ENTRY( X86FXSTATE, FSW),
218 SSMFIELD_ENTRY( X86FXSTATE, FTW),
219 SSMFIELD_ENTRY( X86FXSTATE, FOP),
220 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
221 SSMFIELD_ENTRY( X86FXSTATE, CS),
222 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
223 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
224 SSMFIELD_ENTRY( X86FXSTATE, DS),
225 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
226 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
227 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
228 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
229 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
230 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
231 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
232 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
233 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
234 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
235 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
236 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
237 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
238 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
239 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
240 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
241 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
242 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
243 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
244 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
245 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
246 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
247 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
248 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
249 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
250 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
251 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
252 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
253 SSMFIELD_ENTRY_TERM()
254};
255
256/** Saved state field descriptors for X86XSAVEHDR. */
257static const SSMFIELD g_aCpumXSaveHdrFields[] =
258{
259 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
260 SSMFIELD_ENTRY_TERM()
261};
262
263/** Saved state field descriptors for X86XSAVEYMMHI. */
264static const SSMFIELD g_aCpumYmmHiFields[] =
265{
266 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
267 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
268 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
269 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
270 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
271 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
272 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
273 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
274 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
275 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
276 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
277 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
278 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
279 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
280 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
281 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
282 SSMFIELD_ENTRY_TERM()
283};
284
285/** Saved state field descriptors for X86XSAVEBNDREGS. */
286static const SSMFIELD g_aCpumBndRegsFields[] =
287{
288 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
289 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
290 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
291 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
292 SSMFIELD_ENTRY_TERM()
293};
294
295/** Saved state field descriptors for X86XSAVEBNDCFG. */
296static const SSMFIELD g_aCpumBndCfgFields[] =
297{
298 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
299 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
300 SSMFIELD_ENTRY_TERM()
301};
302
303/** Saved state field descriptors for X86XSAVEOPMASK. */
304static const SSMFIELD g_aCpumOpmaskFields[] =
305{
306 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
307 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
308 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
309 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
310 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
311 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
312 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
313 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
314 SSMFIELD_ENTRY_TERM()
315};
316
317/** Saved state field descriptors for X86XSAVEZMMHI256. */
318static const SSMFIELD g_aCpumZmmHi256Fields[] =
319{
320 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
321 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
322 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
323 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
324 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
325 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
326 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
327 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
328 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
329 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
330 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
331 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
332 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
333 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
334 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
335 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
336 SSMFIELD_ENTRY_TERM()
337};
338
339/** Saved state field descriptors for X86XSAVEZMM16HI. */
340static const SSMFIELD g_aCpumZmm16HiFields[] =
341{
342 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
343 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
344 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
345 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
346 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
347 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
348 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
349 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
350 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
351 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
352 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
353 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
354 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
355 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
356 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
357 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
358 SSMFIELD_ENTRY_TERM()
359};
360
361
362
363/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
364 * registeres changed. */
365static const SSMFIELD g_aCpumX87FieldsMem[] =
366{
367 SSMFIELD_ENTRY( X86FXSTATE, FCW),
368 SSMFIELD_ENTRY( X86FXSTATE, FSW),
369 SSMFIELD_ENTRY( X86FXSTATE, FTW),
370 SSMFIELD_ENTRY( X86FXSTATE, FOP),
371 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
372 SSMFIELD_ENTRY( X86FXSTATE, CS),
373 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
374 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
375 SSMFIELD_ENTRY( X86FXSTATE, DS),
376 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
377 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
378 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
379 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
380 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
381 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
382 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
383 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
384 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
385 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
386 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
387 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
388 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
389 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
390 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
391 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
392 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
393 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
394 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
395 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
396 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
397 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
398 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
399 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
400 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
401 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
402 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
403 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
404 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
405};
406
407/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
408 * registeres changed. */
409static const SSMFIELD g_aCpumCtxFieldsMem[] =
410{
411 SSMFIELD_ENTRY( CPUMCTX, rdi),
412 SSMFIELD_ENTRY( CPUMCTX, rsi),
413 SSMFIELD_ENTRY( CPUMCTX, rbp),
414 SSMFIELD_ENTRY( CPUMCTX, rax),
415 SSMFIELD_ENTRY( CPUMCTX, rbx),
416 SSMFIELD_ENTRY( CPUMCTX, rdx),
417 SSMFIELD_ENTRY( CPUMCTX, rcx),
418 SSMFIELD_ENTRY( CPUMCTX, rsp),
419 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
420 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
421 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
422 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
423 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
424 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
425 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
426 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
427 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
428 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
429 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
430 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
431 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
432 SSMFIELD_ENTRY( CPUMCTX, rflags),
433 SSMFIELD_ENTRY( CPUMCTX, rip),
434 SSMFIELD_ENTRY( CPUMCTX, r8),
435 SSMFIELD_ENTRY( CPUMCTX, r9),
436 SSMFIELD_ENTRY( CPUMCTX, r10),
437 SSMFIELD_ENTRY( CPUMCTX, r11),
438 SSMFIELD_ENTRY( CPUMCTX, r12),
439 SSMFIELD_ENTRY( CPUMCTX, r13),
440 SSMFIELD_ENTRY( CPUMCTX, r14),
441 SSMFIELD_ENTRY( CPUMCTX, r15),
442 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
443 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
444 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
445 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
446 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
447 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
448 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
449 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
450 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
451 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
452 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
453 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
454 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
455 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
456 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
457 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
458 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
459 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
460 SSMFIELD_ENTRY( CPUMCTX, cr0),
461 SSMFIELD_ENTRY( CPUMCTX, cr2),
462 SSMFIELD_ENTRY( CPUMCTX, cr3),
463 SSMFIELD_ENTRY( CPUMCTX, cr4),
464 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
465 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
466 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
467 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
468 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
469 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
470 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
471 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
472 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
473 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
474 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
475 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
476 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
477 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
478 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
479 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
480 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
481 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
482 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
483 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
484 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
485 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
486 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
487 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
488 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
489 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
490 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
491 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
492 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
493 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
494 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
495 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
496 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
497 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
498 SSMFIELD_ENTRY_TERM()
499};
500
501/** Saved state field descriptors for CPUMCTX_VER1_6. */
502static const SSMFIELD g_aCpumX87FieldsV16[] =
503{
504 SSMFIELD_ENTRY( X86FXSTATE, FCW),
505 SSMFIELD_ENTRY( X86FXSTATE, FSW),
506 SSMFIELD_ENTRY( X86FXSTATE, FTW),
507 SSMFIELD_ENTRY( X86FXSTATE, FOP),
508 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
509 SSMFIELD_ENTRY( X86FXSTATE, CS),
510 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
511 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
512 SSMFIELD_ENTRY( X86FXSTATE, DS),
513 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
514 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
515 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
516 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
517 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
518 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
519 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
520 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
521 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
522 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
523 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
524 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
525 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
526 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
527 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
528 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
529 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
530 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
531 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
532 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
533 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
534 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
535 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
536 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
537 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
538 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
539 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
540 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
541 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
542 SSMFIELD_ENTRY_TERM()
543};
544
545/** Saved state field descriptors for CPUMCTX_VER1_6. */
546static const SSMFIELD g_aCpumCtxFieldsV16[] =
547{
548 SSMFIELD_ENTRY( CPUMCTX, rdi),
549 SSMFIELD_ENTRY( CPUMCTX, rsi),
550 SSMFIELD_ENTRY( CPUMCTX, rbp),
551 SSMFIELD_ENTRY( CPUMCTX, rax),
552 SSMFIELD_ENTRY( CPUMCTX, rbx),
553 SSMFIELD_ENTRY( CPUMCTX, rdx),
554 SSMFIELD_ENTRY( CPUMCTX, rcx),
555 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
556 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
557 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
558 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
559 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
560 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
561 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
562 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
563 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
564 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
565 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
566 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
567 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
568 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
569 SSMFIELD_ENTRY( CPUMCTX, rflags),
570 SSMFIELD_ENTRY( CPUMCTX, rip),
571 SSMFIELD_ENTRY( CPUMCTX, r8),
572 SSMFIELD_ENTRY( CPUMCTX, r9),
573 SSMFIELD_ENTRY( CPUMCTX, r10),
574 SSMFIELD_ENTRY( CPUMCTX, r11),
575 SSMFIELD_ENTRY( CPUMCTX, r12),
576 SSMFIELD_ENTRY( CPUMCTX, r13),
577 SSMFIELD_ENTRY( CPUMCTX, r14),
578 SSMFIELD_ENTRY( CPUMCTX, r15),
579 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
580 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
581 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
582 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
583 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
584 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
585 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
586 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
587 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
588 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
589 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
590 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
591 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
592 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
593 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
594 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
595 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
596 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
597 SSMFIELD_ENTRY( CPUMCTX, cr0),
598 SSMFIELD_ENTRY( CPUMCTX, cr2),
599 SSMFIELD_ENTRY( CPUMCTX, cr3),
600 SSMFIELD_ENTRY( CPUMCTX, cr4),
601 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
602 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
603 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
604 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
605 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
606 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
607 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
608 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
609 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
610 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
611 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
612 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
613 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
614 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
615 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
616 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
617 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
618 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
619 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
620 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
621 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
622 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
623 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
624 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
625 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
626 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
627 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
628 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
629 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
630 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
631 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
632 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
633 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
634 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
635 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
636 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
637 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
638 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
639 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
640 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
641 SSMFIELD_ENTRY_TERM()
642};
643
644
645/**
646 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
647 *
648 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
649 * (last instruction pointer, last data pointer, last opcode) except when the ES
650 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
651 * clear these registers there is potential, local FPU leakage from a process
652 * using the FPU to another.
653 *
654 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
655 *
656 * @param pVM Pointer to the VM.
657 */
658static void cpumR3CheckLeakyFpu(PVM pVM)
659{
660 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
661 uint32_t const u32Family = u32CpuVersion >> 8;
662 if ( u32Family >= 6 /* K7 and higher */
663 && ASMIsAmdCpu())
664 {
665 uint32_t cExt = ASMCpuId_EAX(0x80000000);
666 if (ASMIsValidExtRange(cExt))
667 {
668 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
669 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
670 {
671 for (VMCPUID i = 0; i < pVM->cCpus; i++)
672 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
673 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
674 }
675 }
676 }
677}
678
679
680/**
681 * Initializes the CPUM.
682 *
683 * @returns VBox status code.
684 * @param pVM Pointer to the VM.
685 */
686VMMR3DECL(int) CPUMR3Init(PVM pVM)
687{
688 LogFlow(("CPUMR3Init\n"));
689
690 /*
691 * Assert alignment, sizes and tables.
692 */
693 AssertCompileMemberAlignment(VM, cpum.s, 32);
694 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
695 AssertCompileSizeAlignment(CPUMCTX, 64);
696 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
697 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
698 AssertCompileMemberAlignment(VM, cpum, 64);
699 AssertCompileMemberAlignment(VM, aCpus, 64);
700 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
701 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
702#ifdef VBOX_STRICT
703 int rc2 = cpumR3MsrStrictInitChecks();
704 AssertRCReturn(rc2, rc2);
705#endif
706
707 /*
708 * Initialize offsets.
709 */
710
711 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
712 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
713 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
714
715
716 /* Calculate the offset from CPUMCPU to CPUM. */
717 for (VMCPUID i = 0; i < pVM->cCpus; i++)
718 {
719 PVMCPU pVCpu = &pVM->aCpus[i];
720
721 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
722 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
723 }
724
725 /*
726 * Gather info about the host CPU.
727 */
728 if (!ASMHasCpuId())
729 {
730 Log(("The CPU doesn't support CPUID!\n"));
731 return VERR_UNSUPPORTED_CPU;
732 }
733
734 PCPUMCPUIDLEAF paLeaves;
735 uint32_t cLeaves;
736 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
737 AssertLogRelRCReturn(rc, rc);
738
739 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
740 RTMemFree(paLeaves);
741 AssertLogRelRCReturn(rc, rc);
742 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
743
744 /*
745 * Check that the CPU supports the minimum features we require.
746 */
747 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
748 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
749 if (!pVM->cpum.s.HostFeatures.fMmx)
750 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
751 if (!pVM->cpum.s.HostFeatures.fTsc)
752 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
753
754 /*
755 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
756 */
757 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
758 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
759
760 /*
761 * Figure out which XSAVE/XRSTOR features are available on the host.
762 */
763 uint64_t fXStateHostMask = 0;
764 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
765 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
766 {
767 fXStateHostMask = ASMGetXcr0() & ( XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK
768 | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI);
769 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
770 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
771 }
772 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
773 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
774 fXStateHostMask = 0;
775 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx\n", pVM->cpum.s.fXStateHostMask, fXStateHostMask));
776
777 /*
778 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
779 */
780 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
781 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
782 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
783
784 uint8_t *pbXStates;
785 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
786 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
787 AssertLogRelRCReturn(rc, rc);
788
789 for (VMCPUID i = 0; i < pVM->cCpus; i++)
790 {
791 PVMCPU pVCpu = &pVM->aCpus[i];
792
793 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
794 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
795 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
796 pbXStates += cbMaxXState;
797
798 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
799 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
800 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
801 pbXStates += cbMaxXState;
802
803 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
804 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
805 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
806 pbXStates += cbMaxXState;
807
808 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
809 }
810
811 /*
812 * Setup hypervisor startup values.
813 */
814
815 /*
816 * Register saved state data item.
817 */
818 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
819 NULL, cpumR3LiveExec, NULL,
820 NULL, cpumR3SaveExec, NULL,
821 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
822 if (RT_FAILURE(rc))
823 return rc;
824
825 /*
826 * Register info handlers and registers with the debugger facility.
827 */
828 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
829 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
830 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
831 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
832 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
833 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
834
835 rc = cpumR3DbgInit(pVM);
836 if (RT_FAILURE(rc))
837 return rc;
838
839 /*
840 * Check if we need to workaround partial/leaky FPU handling.
841 */
842 cpumR3CheckLeakyFpu(pVM);
843
844 /*
845 * Initialize the Guest CPUID and MSR states.
846 */
847 rc = cpumR3InitCpuIdAndMsrs(pVM);
848 if (RT_FAILURE(rc))
849 return rc;
850 CPUMR3Reset(pVM);
851 return VINF_SUCCESS;
852}
853
854
855/**
856 * Applies relocations to data and code managed by this
857 * component. This function will be called at init and
858 * whenever the VMM need to relocate it self inside the GC.
859 *
860 * The CPUM will update the addresses used by the switcher.
861 *
862 * @param pVM The VM.
863 */
864VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
865{
866 LogFlow(("CPUMR3Relocate\n"));
867
868 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
869 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
870
871 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
872 {
873 PVMCPU pVCpu = &pVM->aCpus[iCpu];
874 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
875 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
876 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
877
878 /* Recheck the guest DRx values in raw-mode. */
879 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
880 }
881}
882
883
884/**
885 * Apply late CPUM property changes based on the fHWVirtEx setting
886 *
887 * @param pVM Pointer to the VM.
888 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
889 */
890VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
891{
892 /*
893 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
894 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
895 * of processors from (cpuid(4).eax >> 26) + 1.
896 *
897 * Note: this code is obsolete, but let's keep it here for reference.
898 * Purpose is valid when we artificially cap the max std id to less than 4.
899 */
900 if (!fHWVirtExEnabled)
901 {
902 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
903 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
904 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
905 }
906}
907
908/**
909 * Terminates the CPUM.
910 *
911 * Termination means cleaning up and freeing all resources,
912 * the VM it self is at this point powered off or suspended.
913 *
914 * @returns VBox status code.
915 * @param pVM Pointer to the VM.
916 */
917VMMR3DECL(int) CPUMR3Term(PVM pVM)
918{
919#ifdef VBOX_WITH_CRASHDUMP_MAGIC
920 for (VMCPUID i = 0; i < pVM->cCpus; i++)
921 {
922 PVMCPU pVCpu = &pVM->aCpus[i];
923 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
924
925 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
926 pVCpu->cpum.s.uMagic = 0;
927 pCtx->dr[5] = 0;
928 }
929#else
930 NOREF(pVM);
931#endif
932 return VINF_SUCCESS;
933}
934
935
936/**
937 * Resets a virtual CPU.
938 *
939 * Used by CPUMR3Reset and CPU hot plugging.
940 *
941 * @param pVM Pointer to the cross context VM structure.
942 * @param pVCpu Pointer to the cross context virtual CPU structure of
943 * the CPU that is being reset. This may differ from the
944 * current EMT.
945 */
946VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
947{
948 /** @todo anything different for VCPU > 0? */
949 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
950
951 /*
952 * Initialize everything to ZERO first.
953 */
954 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
955
956 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
957 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
958 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
959
960 pVCpu->cpum.s.fUseFlags = fUseFlags;
961
962 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
963 pCtx->eip = 0x0000fff0;
964 pCtx->edx = 0x00000600; /* P6 processor */
965 pCtx->eflags.Bits.u1Reserved0 = 1;
966
967 pCtx->cs.Sel = 0xf000;
968 pCtx->cs.ValidSel = 0xf000;
969 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
970 pCtx->cs.u64Base = UINT64_C(0xffff0000);
971 pCtx->cs.u32Limit = 0x0000ffff;
972 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
973 pCtx->cs.Attr.n.u1Present = 1;
974 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
975
976 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
977 pCtx->ds.u32Limit = 0x0000ffff;
978 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
979 pCtx->ds.Attr.n.u1Present = 1;
980 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
981
982 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
983 pCtx->es.u32Limit = 0x0000ffff;
984 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
985 pCtx->es.Attr.n.u1Present = 1;
986 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
987
988 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
989 pCtx->fs.u32Limit = 0x0000ffff;
990 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
991 pCtx->fs.Attr.n.u1Present = 1;
992 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
993
994 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
995 pCtx->gs.u32Limit = 0x0000ffff;
996 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
997 pCtx->gs.Attr.n.u1Present = 1;
998 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
999
1000 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1001 pCtx->ss.u32Limit = 0x0000ffff;
1002 pCtx->ss.Attr.n.u1Present = 1;
1003 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1004 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1005
1006 pCtx->idtr.cbIdt = 0xffff;
1007 pCtx->gdtr.cbGdt = 0xffff;
1008
1009 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1010 pCtx->ldtr.u32Limit = 0xffff;
1011 pCtx->ldtr.Attr.n.u1Present = 1;
1012 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1013
1014 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1015 pCtx->tr.u32Limit = 0xffff;
1016 pCtx->tr.Attr.n.u1Present = 1;
1017 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1018
1019 pCtx->dr[6] = X86_DR6_INIT_VAL;
1020 pCtx->dr[7] = X86_DR7_INIT_VAL;
1021
1022 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1023 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1024 pFpuCtx->FCW = 0x37f;
1025
1026 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1027 IA-32 Processor States Following Power-up, Reset, or INIT */
1028 pFpuCtx->MXCSR = 0x1F80;
1029 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1030 supports all bits, since a zero value here should be read as 0xffbf. */
1031 pCtx->aXcr[0] = XSAVE_C_X87;
1032 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1033 {
1034 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1035 as we don't know what happened before. (Bother optimize later?) */
1036 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1037 }
1038
1039 /*
1040 * MSRs.
1041 */
1042 /* Init PAT MSR */
1043 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1044
1045 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1046 * The Intel docs don't mention it. */
1047 Assert(!pCtx->msrEFER);
1048
1049 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1050 is supposed to be here, just trying provide useful/sensible values. */
1051 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1052 if (pRange)
1053 {
1054 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1055 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1056 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1057 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1058 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1059 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1060 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1061 }
1062
1063 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1064
1065 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1066 * called from each EMT while we're getting called by CPUMR3Reset()
1067 * iteratively on the same thread. Fix later. */
1068#if 0 /** @todo r=bird: This we will do in TM, not here. */
1069 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1070 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1071#endif
1072
1073
1074 /* C-state control. Guesses. */
1075 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1076
1077
1078 /*
1079 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1080 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1081 */
1082 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1083}
1084
1085
1086/**
1087 * Resets the CPU.
1088 *
1089 * @returns VINF_SUCCESS.
1090 * @param pVM Pointer to the VM.
1091 */
1092VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1093{
1094 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1095 {
1096 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1097
1098#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1099 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1100
1101 /* Magic marker for searching in crash dumps. */
1102 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1103 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1104 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1105#endif
1106 }
1107}
1108
1109
1110
1111
1112/**
1113 * Pass 0 live exec callback.
1114 *
1115 * @returns VINF_SSM_DONT_CALL_AGAIN.
1116 * @param pVM Pointer to the VM.
1117 * @param pSSM The saved state handle.
1118 * @param uPass The pass (0).
1119 */
1120static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1121{
1122 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1123 cpumR3SaveCpuId(pVM, pSSM);
1124 return VINF_SSM_DONT_CALL_AGAIN;
1125}
1126
1127
1128/**
1129 * Execute state save operation.
1130 *
1131 * @returns VBox status code.
1132 * @param pVM Pointer to the VM.
1133 * @param pSSM SSM operation handle.
1134 */
1135static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1136{
1137 /*
1138 * Save.
1139 */
1140 SSMR3PutU32(pSSM, pVM->cCpus);
1141 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1142 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1143 {
1144 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1145
1146 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1147
1148 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1149 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1150 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1151 if (pGstCtx->fXStateMask != 0)
1152 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1153 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1154 {
1155 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1156 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1157 }
1158 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1159 {
1160 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1161 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1162 }
1163 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1164 {
1165 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1166 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1167 }
1168 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1169 {
1170 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1171 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1172 }
1173 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1174 {
1175 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1176 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1177 }
1178
1179 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1180 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1181 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1182 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1183 }
1184
1185 cpumR3SaveCpuId(pVM, pSSM);
1186 return VINF_SUCCESS;
1187}
1188
1189
1190/**
1191 * @copydoc FNSSMINTLOADPREP
1192 */
1193static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1194{
1195 NOREF(pSSM);
1196 pVM->cpum.s.fPendingRestore = true;
1197 return VINF_SUCCESS;
1198}
1199
1200
1201/**
1202 * @copydoc FNSSMINTLOADEXEC
1203 */
1204static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1205{
1206 int rc; /* Only for AssertRCReturn use. */
1207
1208 /*
1209 * Validate version.
1210 */
1211 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1212 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1213 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1214 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1215 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1216 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1217 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1218 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1219 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1220 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1221 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1222 {
1223 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1224 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1225 }
1226
1227 if (uPass == SSM_PASS_FINAL)
1228 {
1229 /*
1230 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1231 * really old SSM file versions.)
1232 */
1233 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1234 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1235 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1236 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1237
1238 /*
1239 * Figure x86 and ctx field definitions to use for older states.
1240 */
1241 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1242 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1243 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1244 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1245 {
1246 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1247 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1248 }
1249 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1250 {
1251 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1252 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1253 }
1254
1255 /*
1256 * The hyper state used to preceed the CPU count. Starting with
1257 * XSAVE it was moved down till after we've got the count.
1258 */
1259 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1260 {
1261 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1262 {
1263 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1264 X86FXSTATE Ign;
1265 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1266 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1267 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1268 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1269 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1270 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1271 pVCpu->cpum.s.Hyper.rsp = uRSP;
1272 }
1273 }
1274
1275 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1276 {
1277 uint32_t cCpus;
1278 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1279 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1280 VERR_SSM_UNEXPECTED_DATA);
1281 }
1282 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1283 || pVM->cCpus == 1,
1284 ("cCpus=%u\n", pVM->cCpus),
1285 VERR_SSM_UNEXPECTED_DATA);
1286
1287 uint32_t cbMsrs = 0;
1288 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1289 {
1290 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1291 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1292 VERR_SSM_UNEXPECTED_DATA);
1293 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1294 VERR_SSM_UNEXPECTED_DATA);
1295 }
1296
1297 /*
1298 * Do the per-CPU restoring.
1299 */
1300 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1301 {
1302 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1303 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1304
1305 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1306 {
1307 /*
1308 * The XSAVE saved state layout moved the hyper state down here.
1309 */
1310 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1311 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1312 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1313 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1314 pVCpu->cpum.s.Hyper.rsp = uRSP;
1315 AssertRCReturn(rc, rc);
1316
1317 /*
1318 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1319 */
1320 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1321 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1322 AssertRCReturn(rc, rc);
1323
1324 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1325 if (pGstCtx->fXStateMask != 0)
1326 {
1327 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1328 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1329 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1330 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1331 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1332 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1333 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1334 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1335 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1336 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1337 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1338 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1339 }
1340
1341 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1342 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1343 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1344 {
1345 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1346 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1347 VERR_CPUM_INVALID_XCR0);
1348 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1349 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1350 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1351 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1352 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1353 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1354 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1355 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1356 }
1357
1358 /* Check that the XCR1 is zero, as we don't implement it yet. */
1359 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1360
1361 /*
1362 * Restore the individual extended state components we support.
1363 */
1364 if (pGstCtx->fXStateMask != 0)
1365 {
1366 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1367 0, g_aCpumXSaveHdrFields, NULL);
1368 AssertRCReturn(rc, rc);
1369 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1370 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1371 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1372 VERR_CPUM_INVALID_XSAVE_HDR);
1373 }
1374 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1375 {
1376 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1377 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1378 }
1379 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1380 {
1381 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1382 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1383 }
1384 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1385 {
1386 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1387 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1388 }
1389 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1390 {
1391 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1392 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1393 }
1394 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1395 {
1396 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1397 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1398 }
1399 }
1400 else
1401 {
1402 /*
1403 * Pre XSAVE saved state.
1404 */
1405 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1406 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1407 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1408 }
1409
1410 /*
1411 * Restore a couple of flags and the MSRs.
1412 */
1413 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1414 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1415
1416 rc = VINF_SUCCESS;
1417 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1418 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1419 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1420 {
1421 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1422 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1423 }
1424 AssertRCReturn(rc, rc);
1425
1426 /* REM and other may have cleared must-be-one fields in DR6 and
1427 DR7, fix these. */
1428 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1429 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1430 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1431 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1432 }
1433
1434 /* Older states does not have the internal selector register flags
1435 and valid selector value. Supply those. */
1436 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1437 {
1438 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1439 {
1440 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1441 bool const fValid = HMIsEnabled(pVM)
1442 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1443 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1444 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1445 if (fValid)
1446 {
1447 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1448 {
1449 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1450 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1451 }
1452
1453 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1454 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1455 }
1456 else
1457 {
1458 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1459 {
1460 paSelReg[iSelReg].fFlags = 0;
1461 paSelReg[iSelReg].ValidSel = 0;
1462 }
1463
1464 /* This might not be 104% correct, but I think it's close
1465 enough for all practical purposes... (REM always loaded
1466 LDTR registers.) */
1467 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1468 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1469 }
1470 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1471 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1472 }
1473 }
1474
1475 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1476 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1477 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1478 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1479 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1480
1481 /*
1482 * A quick sanity check.
1483 */
1484 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1485 {
1486 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1487 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1488 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1489 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1490 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1491 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1492 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1493 }
1494 }
1495
1496 pVM->cpum.s.fPendingRestore = false;
1497
1498 /*
1499 * Guest CPUIDs.
1500 */
1501 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1502 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1503 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1504}
1505
1506
1507/**
1508 * @copydoc FNSSMINTLOADPREP
1509 */
1510static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1511{
1512 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1513 return VINF_SUCCESS;
1514
1515 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1516 if (pVM->cpum.s.fPendingRestore)
1517 {
1518 LogRel(("CPUM: Missing state!\n"));
1519 return VERR_INTERNAL_ERROR_2;
1520 }
1521
1522 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1523 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1524 {
1525 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1526
1527 /* Notify PGM of the NXE states in case they've changed. */
1528 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1529
1530 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
1531 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
1532
1533 /* During init. this is done in CPUMR3InitCompleted(). */
1534 if (fSupportsLongMode)
1535 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1536 }
1537 return VINF_SUCCESS;
1538}
1539
1540
1541/**
1542 * Checks if the CPUM state restore is still pending.
1543 *
1544 * @returns true / false.
1545 * @param pVM Pointer to the VM.
1546 */
1547VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1548{
1549 return pVM->cpum.s.fPendingRestore;
1550}
1551
1552
1553/**
1554 * Formats the EFLAGS value into mnemonics.
1555 *
1556 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1557 * @param efl The EFLAGS value.
1558 */
1559static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1560{
1561 /*
1562 * Format the flags.
1563 */
1564 static const struct
1565 {
1566 const char *pszSet; const char *pszClear; uint32_t fFlag;
1567 } s_aFlags[] =
1568 {
1569 { "vip",NULL, X86_EFL_VIP },
1570 { "vif",NULL, X86_EFL_VIF },
1571 { "ac", NULL, X86_EFL_AC },
1572 { "vm", NULL, X86_EFL_VM },
1573 { "rf", NULL, X86_EFL_RF },
1574 { "nt", NULL, X86_EFL_NT },
1575 { "ov", "nv", X86_EFL_OF },
1576 { "dn", "up", X86_EFL_DF },
1577 { "ei", "di", X86_EFL_IF },
1578 { "tf", NULL, X86_EFL_TF },
1579 { "nt", "pl", X86_EFL_SF },
1580 { "nz", "zr", X86_EFL_ZF },
1581 { "ac", "na", X86_EFL_AF },
1582 { "po", "pe", X86_EFL_PF },
1583 { "cy", "nc", X86_EFL_CF },
1584 };
1585 char *psz = pszEFlags;
1586 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1587 {
1588 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1589 if (pszAdd)
1590 {
1591 strcpy(psz, pszAdd);
1592 psz += strlen(pszAdd);
1593 *psz++ = ' ';
1594 }
1595 }
1596 psz[-1] = '\0';
1597}
1598
1599
1600/**
1601 * Formats a full register dump.
1602 *
1603 * @param pVM Pointer to the VM.
1604 * @param pCtx The context to format.
1605 * @param pCtxCore The context core to format.
1606 * @param pHlp Output functions.
1607 * @param enmType The dump type.
1608 * @param pszPrefix Register name prefix.
1609 */
1610static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1611 const char *pszPrefix)
1612{
1613 NOREF(pVM);
1614
1615 /*
1616 * Format the EFLAGS.
1617 */
1618 uint32_t efl = pCtxCore->eflags.u32;
1619 char szEFlags[80];
1620 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1621
1622 /*
1623 * Format the registers.
1624 */
1625 switch (enmType)
1626 {
1627 case CPUMDUMPTYPE_TERSE:
1628 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1629 pHlp->pfnPrintf(pHlp,
1630 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1631 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1632 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1633 "%sr14=%016RX64 %sr15=%016RX64\n"
1634 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1635 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1636 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1637 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1638 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1639 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1640 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1641 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1642 else
1643 pHlp->pfnPrintf(pHlp,
1644 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1645 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1646 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1647 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1648 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1649 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1650 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1651 break;
1652
1653 case CPUMDUMPTYPE_DEFAULT:
1654 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1655 pHlp->pfnPrintf(pHlp,
1656 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1657 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1658 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1659 "%sr14=%016RX64 %sr15=%016RX64\n"
1660 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1661 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1662 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1663 ,
1664 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1665 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1666 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1667 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1668 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1669 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1670 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1671 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1672 else
1673 pHlp->pfnPrintf(pHlp,
1674 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1675 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1676 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1677 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1678 ,
1679 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1680 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1681 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1682 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1683 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1684 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1685 break;
1686
1687 case CPUMDUMPTYPE_VERBOSE:
1688 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1689 pHlp->pfnPrintf(pHlp,
1690 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1691 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1692 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1693 "%sr14=%016RX64 %sr15=%016RX64\n"
1694 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1695 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1696 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1697 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1698 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1699 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1700 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1701 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1702 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1703 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1704 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1705 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1706 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1707 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1708 ,
1709 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1710 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1711 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1712 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1713 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1714 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1715 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1716 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1717 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1718 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1719 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1720 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1721 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1722 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1723 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1724 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1725 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1726 else
1727 pHlp->pfnPrintf(pHlp,
1728 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1729 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1730 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1731 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1732 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1733 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1734 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1735 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1736 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1737 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1738 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1739 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1740 ,
1741 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1742 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1743 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1744 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1745 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1746 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1747 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1748 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1749 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1750 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1751 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1752 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1753
1754 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1755 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1756 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1757 if (pCtx->CTX_SUFF(pXState))
1758 {
1759 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1760 pHlp->pfnPrintf(pHlp,
1761 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1762 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1763 ,
1764 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1765 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1766 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1767 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1768 );
1769 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1770 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1771 {
1772 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1773 unsigned uTag = pFpuCtx->FTW & (1 << iFPR) ? 1 : 0;
1774 char chSign = pFpuCtx->aRegs[0].au16[4] & 0x8000 ? '-' : '+';
1775 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[0].au64[0] >> 63);
1776 uint64_t u64Fraction = pFpuCtx->aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
1777 unsigned uExponent = pFpuCtx->aRegs[0].au16[4] & 0x7fff;
1778 /** @todo This isn't entirenly correct and needs more work! */
1779 pHlp->pfnPrintf(pHlp,
1780 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u (*)",
1781 pszPrefix, iST, pszPrefix, iFPR,
1782 pFpuCtx->aRegs[0].au16[4], pFpuCtx->aRegs[0].au32[1], pFpuCtx->aRegs[0].au32[0],
1783 uTag, chSign, iInteger, u64Fraction, uExponent);
1784 if (pFpuCtx->aRegs[0].au16[5] || pFpuCtx->aRegs[0].au16[6] || pFpuCtx->aRegs[0].au16[7])
1785 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1786 pFpuCtx->aRegs[0].au16[5], pFpuCtx->aRegs[0].au16[6], pFpuCtx->aRegs[0].au16[7]);
1787 else
1788 pHlp->pfnPrintf(pHlp, "\n");
1789 }
1790
1791 /* XMM/YMM/ZMM registers. */
1792 if (pCtx->fXStateMask & XSAVE_C_YMM)
1793 {
1794 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1795 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1796 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1797 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1798 pszPrefix, i, i < 10 ? " " : "",
1799 pYmmHiCtx->aYmmHi[i].au32[3],
1800 pYmmHiCtx->aYmmHi[i].au32[2],
1801 pYmmHiCtx->aYmmHi[i].au32[1],
1802 pYmmHiCtx->aYmmHi[i].au32[0],
1803 pFpuCtx->aXMM[i].au32[3],
1804 pFpuCtx->aXMM[i].au32[2],
1805 pFpuCtx->aXMM[i].au32[1],
1806 pFpuCtx->aXMM[i].au32[0]);
1807 else
1808 {
1809 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1810 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1811 pHlp->pfnPrintf(pHlp,
1812 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1813 pszPrefix, i, i < 10 ? " " : "",
1814 pZmmHi256->aHi256Regs[i].au32[7],
1815 pZmmHi256->aHi256Regs[i].au32[6],
1816 pZmmHi256->aHi256Regs[i].au32[5],
1817 pZmmHi256->aHi256Regs[i].au32[4],
1818 pZmmHi256->aHi256Regs[i].au32[3],
1819 pZmmHi256->aHi256Regs[i].au32[2],
1820 pZmmHi256->aHi256Regs[i].au32[1],
1821 pZmmHi256->aHi256Regs[i].au32[0],
1822 pYmmHiCtx->aYmmHi[i].au32[3],
1823 pYmmHiCtx->aYmmHi[i].au32[2],
1824 pYmmHiCtx->aYmmHi[i].au32[1],
1825 pYmmHiCtx->aYmmHi[i].au32[0],
1826 pFpuCtx->aXMM[i].au32[3],
1827 pFpuCtx->aXMM[i].au32[2],
1828 pFpuCtx->aXMM[i].au32[1],
1829 pFpuCtx->aXMM[i].au32[0]);
1830
1831 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1832 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
1833 pHlp->pfnPrintf(pHlp,
1834 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1835 pszPrefix, i + 16,
1836 pZmm16Hi->aRegs[i].au32[15],
1837 pZmm16Hi->aRegs[i].au32[14],
1838 pZmm16Hi->aRegs[i].au32[13],
1839 pZmm16Hi->aRegs[i].au32[12],
1840 pZmm16Hi->aRegs[i].au32[11],
1841 pZmm16Hi->aRegs[i].au32[10],
1842 pZmm16Hi->aRegs[i].au32[9],
1843 pZmm16Hi->aRegs[i].au32[8],
1844 pZmm16Hi->aRegs[i].au32[7],
1845 pZmm16Hi->aRegs[i].au32[6],
1846 pZmm16Hi->aRegs[i].au32[5],
1847 pZmm16Hi->aRegs[i].au32[4],
1848 pZmm16Hi->aRegs[i].au32[3],
1849 pZmm16Hi->aRegs[i].au32[2],
1850 pZmm16Hi->aRegs[i].au32[1],
1851 pZmm16Hi->aRegs[i].au32[0]);
1852 }
1853 }
1854 else
1855 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1856 pHlp->pfnPrintf(pHlp,
1857 i & 1
1858 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1859 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1860 pszPrefix, i, i < 10 ? " " : "",
1861 pFpuCtx->aXMM[i].au32[3],
1862 pFpuCtx->aXMM[i].au32[2],
1863 pFpuCtx->aXMM[i].au32[1],
1864 pFpuCtx->aXMM[i].au32[0]);
1865
1866 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
1867 {
1868 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
1869 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
1870 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
1871 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
1872 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
1873 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
1874 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
1875 }
1876
1877 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
1878 {
1879 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1880 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
1881 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
1882 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
1883 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
1884 }
1885
1886 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
1887 {
1888 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1889 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
1890 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
1891 }
1892
1893 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1894 if (pFpuCtx->au32RsrvdRest[i])
1895 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[i]=%RX32 (offset=%#x)\n",
1896 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1897 }
1898
1899 pHlp->pfnPrintf(pHlp,
1900 "%sEFER =%016RX64\n"
1901 "%sPAT =%016RX64\n"
1902 "%sSTAR =%016RX64\n"
1903 "%sCSTAR =%016RX64\n"
1904 "%sLSTAR =%016RX64\n"
1905 "%sSFMASK =%016RX64\n"
1906 "%sKERNELGSBASE =%016RX64\n",
1907 pszPrefix, pCtx->msrEFER,
1908 pszPrefix, pCtx->msrPAT,
1909 pszPrefix, pCtx->msrSTAR,
1910 pszPrefix, pCtx->msrCSTAR,
1911 pszPrefix, pCtx->msrLSTAR,
1912 pszPrefix, pCtx->msrSFMASK,
1913 pszPrefix, pCtx->msrKERNELGSBASE);
1914 break;
1915 }
1916}
1917
1918
1919/**
1920 * Display all cpu states and any other cpum info.
1921 *
1922 * @param pVM Pointer to the VM.
1923 * @param pHlp The info helper functions.
1924 * @param pszArgs Arguments, ignored.
1925 */
1926static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1927{
1928 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1929 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1930 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1931 cpumR3InfoHost(pVM, pHlp, pszArgs);
1932}
1933
1934
1935/**
1936 * Parses the info argument.
1937 *
1938 * The argument starts with 'verbose', 'terse' or 'default' and then
1939 * continues with the comment string.
1940 *
1941 * @param pszArgs The pointer to the argument string.
1942 * @param penmType Where to store the dump type request.
1943 * @param ppszComment Where to store the pointer to the comment string.
1944 */
1945static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1946{
1947 if (!pszArgs)
1948 {
1949 *penmType = CPUMDUMPTYPE_DEFAULT;
1950 *ppszComment = "";
1951 }
1952 else
1953 {
1954 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
1955 {
1956 pszArgs += 7;
1957 *penmType = CPUMDUMPTYPE_VERBOSE;
1958 }
1959 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
1960 {
1961 pszArgs += 5;
1962 *penmType = CPUMDUMPTYPE_TERSE;
1963 }
1964 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
1965 {
1966 pszArgs += 7;
1967 *penmType = CPUMDUMPTYPE_DEFAULT;
1968 }
1969 else
1970 *penmType = CPUMDUMPTYPE_DEFAULT;
1971 *ppszComment = RTStrStripL(pszArgs);
1972 }
1973}
1974
1975
1976/**
1977 * Display the guest cpu state.
1978 *
1979 * @param pVM Pointer to the VM.
1980 * @param pHlp The info helper functions.
1981 * @param pszArgs Arguments, ignored.
1982 */
1983static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1984{
1985 CPUMDUMPTYPE enmType;
1986 const char *pszComment;
1987 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1988
1989 /* @todo SMP support! */
1990 PVMCPU pVCpu = VMMGetCpu(pVM);
1991 if (!pVCpu)
1992 pVCpu = &pVM->aCpus[0];
1993
1994 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1995
1996 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1997 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
1998}
1999
2000
2001/**
2002 * Display the current guest instruction
2003 *
2004 * @param pVM Pointer to the VM.
2005 * @param pHlp The info helper functions.
2006 * @param pszArgs Arguments, ignored.
2007 */
2008static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2009{
2010 NOREF(pszArgs);
2011
2012 /** @todo SMP support! */
2013 PVMCPU pVCpu = VMMGetCpu(pVM);
2014 if (!pVCpu)
2015 pVCpu = &pVM->aCpus[0];
2016
2017 char szInstruction[256];
2018 szInstruction[0] = '\0';
2019 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2020 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2021}
2022
2023
2024/**
2025 * Display the hypervisor cpu state.
2026 *
2027 * @param pVM Pointer to the VM.
2028 * @param pHlp The info helper functions.
2029 * @param pszArgs Arguments, ignored.
2030 */
2031static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2032{
2033 CPUMDUMPTYPE enmType;
2034 const char *pszComment;
2035 /* @todo SMP */
2036 PVMCPU pVCpu = &pVM->aCpus[0];
2037
2038 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2039 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2040 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2041 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2042}
2043
2044
2045/**
2046 * Display the host cpu state.
2047 *
2048 * @param pVM Pointer to the VM.
2049 * @param pHlp The info helper functions.
2050 * @param pszArgs Arguments, ignored.
2051 */
2052static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2053{
2054 CPUMDUMPTYPE enmType;
2055 const char *pszComment;
2056 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2057 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2058
2059 /*
2060 * Format the EFLAGS.
2061 */
2062 /* @todo SMP */
2063 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2064#if HC_ARCH_BITS == 32
2065 uint32_t efl = pCtx->eflags.u32;
2066#else
2067 uint64_t efl = pCtx->rflags;
2068#endif
2069 char szEFlags[80];
2070 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2071
2072 /*
2073 * Format the registers.
2074 */
2075#if HC_ARCH_BITS == 32
2076# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2077 if (!(pCtx->efer & MSR_K6_EFER_LMA))
2078# endif
2079 {
2080 pHlp->pfnPrintf(pHlp,
2081 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2082 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2083 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2084 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2085 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2086 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2087 ,
2088 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2089 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2090 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2091 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2092 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2093 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2094 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2095 }
2096# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
2097 else
2098# endif
2099#endif
2100#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
2101 {
2102 pHlp->pfnPrintf(pHlp,
2103 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2104 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2105 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2106 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2107 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2108 "r14=%016RX64 r15=%016RX64\n"
2109 "iopl=%d %31s\n"
2110 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2111 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2112 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2113 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2114 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2115 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2116 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2117 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2118 ,
2119 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2120 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2121 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2122 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2123 pCtx->r11, pCtx->r12, pCtx->r13,
2124 pCtx->r14, pCtx->r15,
2125 X86_EFL_GET_IOPL(efl), szEFlags,
2126 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2127 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2128 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2129 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2130 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2131 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2132 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2133 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2134 }
2135#endif
2136}
2137
2138/**
2139 * Structure used when disassembling and instructions in DBGF.
2140 * This is used so the reader function can get the stuff it needs.
2141 */
2142typedef struct CPUMDISASSTATE
2143{
2144 /** Pointer to the CPU structure. */
2145 PDISCPUSTATE pCpu;
2146 /** Pointer to the VM. */
2147 PVM pVM;
2148 /** Pointer to the VMCPU. */
2149 PVMCPU pVCpu;
2150 /** Pointer to the first byte in the segment. */
2151 RTGCUINTPTR GCPtrSegBase;
2152 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2153 RTGCUINTPTR GCPtrSegEnd;
2154 /** The size of the segment minus 1. */
2155 RTGCUINTPTR cbSegLimit;
2156 /** Pointer to the current page - R3 Ptr. */
2157 void const *pvPageR3;
2158 /** Pointer to the current page - GC Ptr. */
2159 RTGCPTR pvPageGC;
2160 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2161 PGMPAGEMAPLOCK PageMapLock;
2162 /** Whether the PageMapLock is valid or not. */
2163 bool fLocked;
2164 /** 64 bits mode or not. */
2165 bool f64Bits;
2166} CPUMDISASSTATE, *PCPUMDISASSTATE;
2167
2168
2169/**
2170 * @callback_method_impl{FNDISREADBYTES}
2171 */
2172static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2173{
2174 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2175 for (;;)
2176 {
2177 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2178
2179 /*
2180 * Need to update the page translation?
2181 */
2182 if ( !pState->pvPageR3
2183 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2184 {
2185 int rc = VINF_SUCCESS;
2186
2187 /* translate the address */
2188 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2189 if ( !HMIsEnabled(pState->pVM)
2190 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2191 {
2192 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2193 if (!pState->pvPageR3)
2194 rc = VERR_INVALID_POINTER;
2195 }
2196 else
2197 {
2198 /* Release mapping lock previously acquired. */
2199 if (pState->fLocked)
2200 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2201 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2202 pState->fLocked = RT_SUCCESS_NP(rc);
2203 }
2204 if (RT_FAILURE(rc))
2205 {
2206 pState->pvPageR3 = NULL;
2207 return rc;
2208 }
2209 }
2210
2211 /*
2212 * Check the segment limit.
2213 */
2214 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2215 return VERR_OUT_OF_SELECTOR_BOUNDS;
2216
2217 /*
2218 * Calc how much we can read.
2219 */
2220 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2221 if (!pState->f64Bits)
2222 {
2223 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2224 if (cb > cbSeg && cbSeg)
2225 cb = cbSeg;
2226 }
2227 if (cb > cbMaxRead)
2228 cb = cbMaxRead;
2229
2230 /*
2231 * Read and advance or exit.
2232 */
2233 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2234 offInstr += (uint8_t)cb;
2235 if (cb >= cbMinRead)
2236 {
2237 pDis->cbCachedInstr = offInstr;
2238 return VINF_SUCCESS;
2239 }
2240 cbMinRead -= (uint8_t)cb;
2241 cbMaxRead -= (uint8_t)cb;
2242 }
2243}
2244
2245
2246/**
2247 * Disassemble an instruction and return the information in the provided structure.
2248 *
2249 * @returns VBox status code.
2250 * @param pVM Pointer to the VM.
2251 * @param pVCpu Pointer to the VMCPU.
2252 * @param pCtx Pointer to the guest CPU context.
2253 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2254 * @param pCpu Disassembly state.
2255 * @param pszPrefix String prefix for logging (debug only).
2256 *
2257 */
2258VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2259{
2260 CPUMDISASSTATE State;
2261 int rc;
2262
2263 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2264 State.pCpu = pCpu;
2265 State.pvPageGC = 0;
2266 State.pvPageR3 = NULL;
2267 State.pVM = pVM;
2268 State.pVCpu = pVCpu;
2269 State.fLocked = false;
2270 State.f64Bits = false;
2271
2272 /*
2273 * Get selector information.
2274 */
2275 DISCPUMODE enmDisCpuMode;
2276 if ( (pCtx->cr0 & X86_CR0_PE)
2277 && pCtx->eflags.Bits.u1VM == 0)
2278 {
2279 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2280 {
2281# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2282 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2283# endif
2284 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2285 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2286 }
2287 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2288 State.GCPtrSegBase = pCtx->cs.u64Base;
2289 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2290 State.cbSegLimit = pCtx->cs.u32Limit;
2291 enmDisCpuMode = (State.f64Bits)
2292 ? DISCPUMODE_64BIT
2293 : pCtx->cs.Attr.n.u1DefBig
2294 ? DISCPUMODE_32BIT
2295 : DISCPUMODE_16BIT;
2296 }
2297 else
2298 {
2299 /* real or V86 mode */
2300 enmDisCpuMode = DISCPUMODE_16BIT;
2301 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2302 State.GCPtrSegEnd = 0xFFFFFFFF;
2303 State.cbSegLimit = 0xFFFFFFFF;
2304 }
2305
2306 /*
2307 * Disassemble the instruction.
2308 */
2309 uint32_t cbInstr;
2310#ifndef LOG_ENABLED
2311 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2312 if (RT_SUCCESS(rc))
2313 {
2314#else
2315 char szOutput[160];
2316 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2317 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2318 if (RT_SUCCESS(rc))
2319 {
2320 /* log it */
2321 if (pszPrefix)
2322 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2323 else
2324 Log(("%s", szOutput));
2325#endif
2326 rc = VINF_SUCCESS;
2327 }
2328 else
2329 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2330
2331 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2332 if (State.fLocked)
2333 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2334
2335 return rc;
2336}
2337
2338
2339
2340/**
2341 * API for controlling a few of the CPU features found in CR4.
2342 *
2343 * Currently only X86_CR4_TSD is accepted as input.
2344 *
2345 * @returns VBox status code.
2346 *
2347 * @param pVM Pointer to the VM.
2348 * @param fOr The CR4 OR mask.
2349 * @param fAnd The CR4 AND mask.
2350 */
2351VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2352{
2353 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2354 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2355
2356 pVM->cpum.s.CR4.OrMask &= fAnd;
2357 pVM->cpum.s.CR4.OrMask |= fOr;
2358
2359 return VINF_SUCCESS;
2360}
2361
2362
2363/**
2364 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2365 *
2366 * Only REM should ever call this function!
2367 *
2368 * @returns The changed flags.
2369 * @param pVCpu Pointer to the VMCPU.
2370 * @param puCpl Where to return the current privilege level (CPL).
2371 */
2372VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2373{
2374 Assert(!pVCpu->cpum.s.fRawEntered);
2375 Assert(!pVCpu->cpum.s.fRemEntered);
2376
2377 /*
2378 * Get the CPL first.
2379 */
2380 *puCpl = CPUMGetGuestCPL(pVCpu);
2381
2382 /*
2383 * Get and reset the flags.
2384 */
2385 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2386 pVCpu->cpum.s.fChanged = 0;
2387
2388 /** @todo change the switcher to use the fChanged flags. */
2389 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2390 {
2391 fFlags |= CPUM_CHANGED_FPU_REM;
2392 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2393 }
2394
2395 pVCpu->cpum.s.fRemEntered = true;
2396 return fFlags;
2397}
2398
2399
2400/**
2401 * Leaves REM.
2402 *
2403 * @param pVCpu Pointer to the VMCPU.
2404 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2405 * registers.
2406 */
2407VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2408{
2409 Assert(!pVCpu->cpum.s.fRawEntered);
2410 Assert(pVCpu->cpum.s.fRemEntered);
2411
2412 pVCpu->cpum.s.fRemEntered = false;
2413}
2414
2415
2416/**
2417 * Called when the ring-3 init phase completes.
2418 *
2419 * @returns VBox status code.
2420 * @param pVM Pointer to the VM.
2421 */
2422VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
2423{
2424 /*
2425 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2426 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2427 */
2428 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2429 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2430 {
2431 PVMCPU pVCpu = &pVM->aCpus[i];
2432
2433 /* Cache the APIC base (from the APIC device) once it has been initialized. */
2434 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
2435 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVCpu->cpum.s.Guest.msrApicBase));
2436
2437 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2438 if (fSupportsLongMode)
2439 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2440 }
2441 return VINF_SUCCESS;
2442}
2443
2444
2445/**
2446 * Called when the ring-0 init phases comleted.
2447 *
2448 * @param pVM Pointer to the VM.
2449 */
2450VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2451{
2452 /*
2453 * Log the cpuid.
2454 */
2455 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2456 RTCPUSET OnlineSet;
2457 LogRel(("Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2458 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2459 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2460 RTCPUID cCores = RTMpGetCoreCount();
2461 if (cCores)
2462 LogRel(("Physical host cores: %u\n", (unsigned)cCores));
2463 LogRel(("************************* CPUID dump ************************\n"));
2464 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2465 LogRel(("\n"));
2466 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
2467 RTLogRelSetBuffering(fOldBuffered);
2468 LogRel(("******************** End of CPUID dump **********************\n"));
2469}
2470
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