VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 59140

Last change on this file since 59140 was 58126, checked in by vboxsync, 9 years ago

VMM: Fixed almost all the Doxygen warnings.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 110.2 KB
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1/* $Id: CPUM.cpp 58126 2015-10-08 20:59:48Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 */
33
34
35/*********************************************************************************************************************************
36* Header Files *
37*********************************************************************************************************************************/
38#define LOG_GROUP LOG_GROUP_CPUM
39#include <VBox/vmm/cpum.h>
40#include <VBox/vmm/cpumdis.h>
41#include <VBox/vmm/cpumctx-v1_6.h>
42#include <VBox/vmm/pgm.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/vmm/mm.h>
45#include <VBox/vmm/em.h>
46#include <VBox/vmm/selm.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/patm.h>
49#include <VBox/vmm/hm.h>
50#include <VBox/vmm/ssm.h>
51#include "CPUMInternal.h"
52#include <VBox/vmm/vm.h>
53
54#include <VBox/param.h>
55#include <VBox/dis.h>
56#include <VBox/err.h>
57#include <VBox/log.h>
58#include <iprt/asm-amd64-x86.h>
59#include <iprt/assert.h>
60#include <iprt/cpuset.h>
61#include <iprt/mem.h>
62#include <iprt/mp.h>
63#include <iprt/string.h>
64#include "internal/pgm.h"
65
66
67/*********************************************************************************************************************************
68* Defined Constants And Macros *
69*********************************************************************************************************************************/
70/**
71 * This was used in the saved state up to the early life of version 14.
72 *
73 * It indicates that we may have some out-of-sync hidden segement registers.
74 * It is only relevant for raw-mode.
75 */
76#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
77
78
79/*********************************************************************************************************************************
80* Structures and Typedefs *
81*********************************************************************************************************************************/
82
83/**
84 * What kind of cpu info dump to perform.
85 */
86typedef enum CPUMDUMPTYPE
87{
88 CPUMDUMPTYPE_TERSE,
89 CPUMDUMPTYPE_DEFAULT,
90 CPUMDUMPTYPE_VERBOSE
91} CPUMDUMPTYPE;
92/** Pointer to a cpu info dump type. */
93typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
94
95
96/*********************************************************************************************************************************
97* Internal Functions *
98*********************************************************************************************************************************/
99static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
100static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
101static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
102static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
103static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
104static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
105static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
106static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
107static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
108static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
109
110
111/*********************************************************************************************************************************
112* Global Variables *
113*********************************************************************************************************************************/
114/** Saved state field descriptors for CPUMCTX. */
115static const SSMFIELD g_aCpumCtxFields[] =
116{
117 SSMFIELD_ENTRY( CPUMCTX, rdi),
118 SSMFIELD_ENTRY( CPUMCTX, rsi),
119 SSMFIELD_ENTRY( CPUMCTX, rbp),
120 SSMFIELD_ENTRY( CPUMCTX, rax),
121 SSMFIELD_ENTRY( CPUMCTX, rbx),
122 SSMFIELD_ENTRY( CPUMCTX, rdx),
123 SSMFIELD_ENTRY( CPUMCTX, rcx),
124 SSMFIELD_ENTRY( CPUMCTX, rsp),
125 SSMFIELD_ENTRY( CPUMCTX, rflags),
126 SSMFIELD_ENTRY( CPUMCTX, rip),
127 SSMFIELD_ENTRY( CPUMCTX, r8),
128 SSMFIELD_ENTRY( CPUMCTX, r9),
129 SSMFIELD_ENTRY( CPUMCTX, r10),
130 SSMFIELD_ENTRY( CPUMCTX, r11),
131 SSMFIELD_ENTRY( CPUMCTX, r12),
132 SSMFIELD_ENTRY( CPUMCTX, r13),
133 SSMFIELD_ENTRY( CPUMCTX, r14),
134 SSMFIELD_ENTRY( CPUMCTX, r15),
135 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
136 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
137 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
138 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
139 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
140 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
141 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
142 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
143 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
144 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
145 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
146 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
147 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
148 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
149 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
150 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
151 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
152 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
153 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
154 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
155 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
156 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
157 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
158 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
159 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
160 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
161 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
162 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
163 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
164 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
165 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
166 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
167 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
168 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
169 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
170 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
171 SSMFIELD_ENTRY( CPUMCTX, cr0),
172 SSMFIELD_ENTRY( CPUMCTX, cr2),
173 SSMFIELD_ENTRY( CPUMCTX, cr3),
174 SSMFIELD_ENTRY( CPUMCTX, cr4),
175 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
176 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
177 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
178 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
179 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
180 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
181 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
182 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
183 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
184 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
185 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
186 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
187 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
188 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
189 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
190 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
191 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
192 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
193 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
194 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
195 /* msrApicBase is not included here, it resides in the APIC device state. */
196 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
197 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
198 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
199 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
200 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
201 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
202 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
203 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
204 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
205 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
206 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
207 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
208 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
209 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
210 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
211 SSMFIELD_ENTRY_TERM()
212};
213
214/** Saved state field descriptors for CPUMCTX. */
215static const SSMFIELD g_aCpumX87Fields[] =
216{
217 SSMFIELD_ENTRY( X86FXSTATE, FCW),
218 SSMFIELD_ENTRY( X86FXSTATE, FSW),
219 SSMFIELD_ENTRY( X86FXSTATE, FTW),
220 SSMFIELD_ENTRY( X86FXSTATE, FOP),
221 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
222 SSMFIELD_ENTRY( X86FXSTATE, CS),
223 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
224 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
225 SSMFIELD_ENTRY( X86FXSTATE, DS),
226 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
227 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
228 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
229 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
230 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
231 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
232 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
233 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
234 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
235 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
236 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
237 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
238 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
239 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
240 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
241 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
242 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
243 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
244 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
245 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
246 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
247 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
248 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
249 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
250 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
251 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
252 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
253 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
254 SSMFIELD_ENTRY_TERM()
255};
256
257/** Saved state field descriptors for X86XSAVEHDR. */
258static const SSMFIELD g_aCpumXSaveHdrFields[] =
259{
260 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
261 SSMFIELD_ENTRY_TERM()
262};
263
264/** Saved state field descriptors for X86XSAVEYMMHI. */
265static const SSMFIELD g_aCpumYmmHiFields[] =
266{
267 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
268 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
269 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
270 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
271 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
272 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
273 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
274 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
275 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
276 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
277 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
278 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
279 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
280 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
281 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
282 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
283 SSMFIELD_ENTRY_TERM()
284};
285
286/** Saved state field descriptors for X86XSAVEBNDREGS. */
287static const SSMFIELD g_aCpumBndRegsFields[] =
288{
289 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
290 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
291 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
292 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
293 SSMFIELD_ENTRY_TERM()
294};
295
296/** Saved state field descriptors for X86XSAVEBNDCFG. */
297static const SSMFIELD g_aCpumBndCfgFields[] =
298{
299 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
300 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
301 SSMFIELD_ENTRY_TERM()
302};
303
304/** Saved state field descriptors for X86XSAVEOPMASK. */
305static const SSMFIELD g_aCpumOpmaskFields[] =
306{
307 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
308 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
309 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
310 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
311 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
312 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
313 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
314 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
315 SSMFIELD_ENTRY_TERM()
316};
317
318/** Saved state field descriptors for X86XSAVEZMMHI256. */
319static const SSMFIELD g_aCpumZmmHi256Fields[] =
320{
321 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
322 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
323 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
324 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
325 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
326 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
327 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
328 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
329 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
330 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
331 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
332 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
333 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
334 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
335 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
336 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
337 SSMFIELD_ENTRY_TERM()
338};
339
340/** Saved state field descriptors for X86XSAVEZMM16HI. */
341static const SSMFIELD g_aCpumZmm16HiFields[] =
342{
343 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
344 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
345 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
346 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
347 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
348 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
349 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
350 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
351 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
352 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
353 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
354 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
355 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
356 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
357 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
358 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
359 SSMFIELD_ENTRY_TERM()
360};
361
362
363
364/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
365 * registeres changed. */
366static const SSMFIELD g_aCpumX87FieldsMem[] =
367{
368 SSMFIELD_ENTRY( X86FXSTATE, FCW),
369 SSMFIELD_ENTRY( X86FXSTATE, FSW),
370 SSMFIELD_ENTRY( X86FXSTATE, FTW),
371 SSMFIELD_ENTRY( X86FXSTATE, FOP),
372 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
373 SSMFIELD_ENTRY( X86FXSTATE, CS),
374 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
375 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
376 SSMFIELD_ENTRY( X86FXSTATE, DS),
377 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
378 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
379 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
380 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
381 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
382 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
383 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
384 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
385 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
386 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
387 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
388 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
389 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
390 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
391 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
392 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
393 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
394 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
395 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
396 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
397 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
398 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
399 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
400 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
401 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
402 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
403 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
404 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
405 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
406};
407
408/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
409 * registeres changed. */
410static const SSMFIELD g_aCpumCtxFieldsMem[] =
411{
412 SSMFIELD_ENTRY( CPUMCTX, rdi),
413 SSMFIELD_ENTRY( CPUMCTX, rsi),
414 SSMFIELD_ENTRY( CPUMCTX, rbp),
415 SSMFIELD_ENTRY( CPUMCTX, rax),
416 SSMFIELD_ENTRY( CPUMCTX, rbx),
417 SSMFIELD_ENTRY( CPUMCTX, rdx),
418 SSMFIELD_ENTRY( CPUMCTX, rcx),
419 SSMFIELD_ENTRY( CPUMCTX, rsp),
420 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
421 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
422 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
423 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
424 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
425 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
426 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
427 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
428 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
429 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
430 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
431 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
432 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
433 SSMFIELD_ENTRY( CPUMCTX, rflags),
434 SSMFIELD_ENTRY( CPUMCTX, rip),
435 SSMFIELD_ENTRY( CPUMCTX, r8),
436 SSMFIELD_ENTRY( CPUMCTX, r9),
437 SSMFIELD_ENTRY( CPUMCTX, r10),
438 SSMFIELD_ENTRY( CPUMCTX, r11),
439 SSMFIELD_ENTRY( CPUMCTX, r12),
440 SSMFIELD_ENTRY( CPUMCTX, r13),
441 SSMFIELD_ENTRY( CPUMCTX, r14),
442 SSMFIELD_ENTRY( CPUMCTX, r15),
443 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
444 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
445 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
446 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
447 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
448 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
449 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
450 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
451 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
452 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
453 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
454 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
455 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
456 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
457 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
458 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
459 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
460 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
461 SSMFIELD_ENTRY( CPUMCTX, cr0),
462 SSMFIELD_ENTRY( CPUMCTX, cr2),
463 SSMFIELD_ENTRY( CPUMCTX, cr3),
464 SSMFIELD_ENTRY( CPUMCTX, cr4),
465 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
466 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
467 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
468 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
469 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
470 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
471 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
472 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
473 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
474 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
475 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
476 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
477 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
478 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
479 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
480 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
481 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
482 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
483 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
484 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
485 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
486 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
487 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
488 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
489 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
490 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
491 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
492 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
493 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
494 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
495 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
496 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
497 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
498 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
499 SSMFIELD_ENTRY_TERM()
500};
501
502/** Saved state field descriptors for CPUMCTX_VER1_6. */
503static const SSMFIELD g_aCpumX87FieldsV16[] =
504{
505 SSMFIELD_ENTRY( X86FXSTATE, FCW),
506 SSMFIELD_ENTRY( X86FXSTATE, FSW),
507 SSMFIELD_ENTRY( X86FXSTATE, FTW),
508 SSMFIELD_ENTRY( X86FXSTATE, FOP),
509 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
510 SSMFIELD_ENTRY( X86FXSTATE, CS),
511 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
512 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
513 SSMFIELD_ENTRY( X86FXSTATE, DS),
514 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
515 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
516 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
517 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
518 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
519 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
520 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
521 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
522 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
523 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
524 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
525 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
526 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
527 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
528 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
529 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
530 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
531 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
532 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
533 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
534 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
535 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
536 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
537 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
538 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
539 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
540 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
541 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
542 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
543 SSMFIELD_ENTRY_TERM()
544};
545
546/** Saved state field descriptors for CPUMCTX_VER1_6. */
547static const SSMFIELD g_aCpumCtxFieldsV16[] =
548{
549 SSMFIELD_ENTRY( CPUMCTX, rdi),
550 SSMFIELD_ENTRY( CPUMCTX, rsi),
551 SSMFIELD_ENTRY( CPUMCTX, rbp),
552 SSMFIELD_ENTRY( CPUMCTX, rax),
553 SSMFIELD_ENTRY( CPUMCTX, rbx),
554 SSMFIELD_ENTRY( CPUMCTX, rdx),
555 SSMFIELD_ENTRY( CPUMCTX, rcx),
556 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
557 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
558 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
559 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
560 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
561 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
562 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
563 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
564 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
565 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
566 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
567 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
568 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
569 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
570 SSMFIELD_ENTRY( CPUMCTX, rflags),
571 SSMFIELD_ENTRY( CPUMCTX, rip),
572 SSMFIELD_ENTRY( CPUMCTX, r8),
573 SSMFIELD_ENTRY( CPUMCTX, r9),
574 SSMFIELD_ENTRY( CPUMCTX, r10),
575 SSMFIELD_ENTRY( CPUMCTX, r11),
576 SSMFIELD_ENTRY( CPUMCTX, r12),
577 SSMFIELD_ENTRY( CPUMCTX, r13),
578 SSMFIELD_ENTRY( CPUMCTX, r14),
579 SSMFIELD_ENTRY( CPUMCTX, r15),
580 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
581 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
582 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
583 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
584 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
585 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
586 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
587 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
588 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
589 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
590 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
591 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
592 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
593 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
594 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
595 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
596 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
597 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
598 SSMFIELD_ENTRY( CPUMCTX, cr0),
599 SSMFIELD_ENTRY( CPUMCTX, cr2),
600 SSMFIELD_ENTRY( CPUMCTX, cr3),
601 SSMFIELD_ENTRY( CPUMCTX, cr4),
602 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
603 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
604 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
605 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
606 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
607 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
608 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
609 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
610 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
611 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
612 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
613 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
614 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
615 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
616 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
617 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
618 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
619 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
620 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
621 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
622 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
623 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
624 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
625 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
626 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
627 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
628 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
629 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
630 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
631 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
632 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
633 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
634 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
635 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
636 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
637 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
638 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
639 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
640 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
641 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
642 SSMFIELD_ENTRY_TERM()
643};
644
645
646/**
647 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
648 *
649 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
650 * (last instruction pointer, last data pointer, last opcode) except when the ES
651 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
652 * clear these registers there is potential, local FPU leakage from a process
653 * using the FPU to another.
654 *
655 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
656 *
657 * @param pVM The cross context VM structure.
658 */
659static void cpumR3CheckLeakyFpu(PVM pVM)
660{
661 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
662 uint32_t const u32Family = u32CpuVersion >> 8;
663 if ( u32Family >= 6 /* K7 and higher */
664 && ASMIsAmdCpu())
665 {
666 uint32_t cExt = ASMCpuId_EAX(0x80000000);
667 if (ASMIsValidExtRange(cExt))
668 {
669 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
670 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
671 {
672 for (VMCPUID i = 0; i < pVM->cCpus; i++)
673 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
674 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
675 }
676 }
677 }
678}
679
680
681/**
682 * Initializes the CPUM.
683 *
684 * @returns VBox status code.
685 * @param pVM The cross context VM structure.
686 */
687VMMR3DECL(int) CPUMR3Init(PVM pVM)
688{
689 LogFlow(("CPUMR3Init\n"));
690
691 /*
692 * Assert alignment, sizes and tables.
693 */
694 AssertCompileMemberAlignment(VM, cpum.s, 32);
695 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
696 AssertCompileSizeAlignment(CPUMCTX, 64);
697 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
698 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
699 AssertCompileMemberAlignment(VM, cpum, 64);
700 AssertCompileMemberAlignment(VM, aCpus, 64);
701 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
702 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
703#ifdef VBOX_STRICT
704 int rc2 = cpumR3MsrStrictInitChecks();
705 AssertRCReturn(rc2, rc2);
706#endif
707
708 /*
709 * Initialize offsets.
710 */
711
712 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
713 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
714 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
715
716
717 /* Calculate the offset from CPUMCPU to CPUM. */
718 for (VMCPUID i = 0; i < pVM->cCpus; i++)
719 {
720 PVMCPU pVCpu = &pVM->aCpus[i];
721
722 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
723 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
724 }
725
726 /*
727 * Gather info about the host CPU.
728 */
729 if (!ASMHasCpuId())
730 {
731 Log(("The CPU doesn't support CPUID!\n"));
732 return VERR_UNSUPPORTED_CPU;
733 }
734
735 PCPUMCPUIDLEAF paLeaves;
736 uint32_t cLeaves;
737 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
738 AssertLogRelRCReturn(rc, rc);
739
740 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
741 RTMemFree(paLeaves);
742 AssertLogRelRCReturn(rc, rc);
743 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
744
745 /*
746 * Check that the CPU supports the minimum features we require.
747 */
748 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
749 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
750 if (!pVM->cpum.s.HostFeatures.fMmx)
751 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
752 if (!pVM->cpum.s.HostFeatures.fTsc)
753 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
754
755 /*
756 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
757 */
758 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
759 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
760
761 /*
762 * Figure out which XSAVE/XRSTOR features are available on the host.
763 */
764 uint64_t fXcr0Host = 0;
765 uint64_t fXStateHostMask = 0;
766 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
767 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
768 {
769 fXStateHostMask = fXcr0Host = ASMGetXcr0();
770 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
771 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
772 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
773 }
774 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
775 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
776 fXStateHostMask = 0;
777 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
778 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
779
780 /*
781 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
782 */
783 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
784 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
785 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
786
787 uint8_t *pbXStates;
788 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
789 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
790 AssertLogRelRCReturn(rc, rc);
791
792 for (VMCPUID i = 0; i < pVM->cCpus; i++)
793 {
794 PVMCPU pVCpu = &pVM->aCpus[i];
795
796 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
797 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
798 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
799 pbXStates += cbMaxXState;
800
801 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
802 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
803 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
804 pbXStates += cbMaxXState;
805
806 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
807 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
808 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
809 pbXStates += cbMaxXState;
810
811 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
812 }
813
814 /*
815 * Setup hypervisor startup values.
816 */
817
818 /*
819 * Register saved state data item.
820 */
821 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
822 NULL, cpumR3LiveExec, NULL,
823 NULL, cpumR3SaveExec, NULL,
824 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
825 if (RT_FAILURE(rc))
826 return rc;
827
828 /*
829 * Register info handlers and registers with the debugger facility.
830 */
831 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
832 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
833 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
834 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
835 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
836 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
837
838 rc = cpumR3DbgInit(pVM);
839 if (RT_FAILURE(rc))
840 return rc;
841
842 /*
843 * Check if we need to workaround partial/leaky FPU handling.
844 */
845 cpumR3CheckLeakyFpu(pVM);
846
847 /*
848 * Initialize the Guest CPUID and MSR states.
849 */
850 rc = cpumR3InitCpuIdAndMsrs(pVM);
851 if (RT_FAILURE(rc))
852 return rc;
853 CPUMR3Reset(pVM);
854 return VINF_SUCCESS;
855}
856
857
858/**
859 * Applies relocations to data and code managed by this
860 * component. This function will be called at init and
861 * whenever the VMM need to relocate it self inside the GC.
862 *
863 * The CPUM will update the addresses used by the switcher.
864 *
865 * @param pVM The cross context VM structure.
866 */
867VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
868{
869 LogFlow(("CPUMR3Relocate\n"));
870
871 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
872 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
873
874 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
875 {
876 PVMCPU pVCpu = &pVM->aCpus[iCpu];
877 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
878 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
879 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
880
881 /* Recheck the guest DRx values in raw-mode. */
882 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
883 }
884}
885
886
887/**
888 * Apply late CPUM property changes based on the fHWVirtEx setting
889 *
890 * @param pVM The cross context VM structure.
891 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
892 */
893VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
894{
895 /*
896 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
897 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
898 * of processors from (cpuid(4).eax >> 26) + 1.
899 *
900 * Note: this code is obsolete, but let's keep it here for reference.
901 * Purpose is valid when we artificially cap the max std id to less than 4.
902 */
903 if (!fHWVirtExEnabled)
904 {
905 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
906 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
907 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
908 }
909}
910
911/**
912 * Terminates the CPUM.
913 *
914 * Termination means cleaning up and freeing all resources,
915 * the VM it self is at this point powered off or suspended.
916 *
917 * @returns VBox status code.
918 * @param pVM The cross context VM structure.
919 */
920VMMR3DECL(int) CPUMR3Term(PVM pVM)
921{
922#ifdef VBOX_WITH_CRASHDUMP_MAGIC
923 for (VMCPUID i = 0; i < pVM->cCpus; i++)
924 {
925 PVMCPU pVCpu = &pVM->aCpus[i];
926 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
927
928 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
929 pVCpu->cpum.s.uMagic = 0;
930 pCtx->dr[5] = 0;
931 }
932#else
933 NOREF(pVM);
934#endif
935 return VINF_SUCCESS;
936}
937
938
939/**
940 * Resets a virtual CPU.
941 *
942 * Used by CPUMR3Reset and CPU hot plugging.
943 *
944 * @param pVM The cross context VM structure.
945 * @param pVCpu The cross context virtual CPU structure of the CPU that is
946 * being reset. This may differ from the current EMT.
947 */
948VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
949{
950 /** @todo anything different for VCPU > 0? */
951 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
952
953 /*
954 * Initialize everything to ZERO first.
955 */
956 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
957
958 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
959 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
960 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
961
962 pVCpu->cpum.s.fUseFlags = fUseFlags;
963
964 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
965 pCtx->eip = 0x0000fff0;
966 pCtx->edx = 0x00000600; /* P6 processor */
967 pCtx->eflags.Bits.u1Reserved0 = 1;
968
969 pCtx->cs.Sel = 0xf000;
970 pCtx->cs.ValidSel = 0xf000;
971 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
972 pCtx->cs.u64Base = UINT64_C(0xffff0000);
973 pCtx->cs.u32Limit = 0x0000ffff;
974 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
975 pCtx->cs.Attr.n.u1Present = 1;
976 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
977
978 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
979 pCtx->ds.u32Limit = 0x0000ffff;
980 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
981 pCtx->ds.Attr.n.u1Present = 1;
982 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
983
984 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
985 pCtx->es.u32Limit = 0x0000ffff;
986 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
987 pCtx->es.Attr.n.u1Present = 1;
988 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
989
990 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
991 pCtx->fs.u32Limit = 0x0000ffff;
992 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
993 pCtx->fs.Attr.n.u1Present = 1;
994 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
995
996 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
997 pCtx->gs.u32Limit = 0x0000ffff;
998 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
999 pCtx->gs.Attr.n.u1Present = 1;
1000 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1001
1002 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1003 pCtx->ss.u32Limit = 0x0000ffff;
1004 pCtx->ss.Attr.n.u1Present = 1;
1005 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1006 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1007
1008 pCtx->idtr.cbIdt = 0xffff;
1009 pCtx->gdtr.cbGdt = 0xffff;
1010
1011 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1012 pCtx->ldtr.u32Limit = 0xffff;
1013 pCtx->ldtr.Attr.n.u1Present = 1;
1014 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1015
1016 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1017 pCtx->tr.u32Limit = 0xffff;
1018 pCtx->tr.Attr.n.u1Present = 1;
1019 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1020
1021 pCtx->dr[6] = X86_DR6_INIT_VAL;
1022 pCtx->dr[7] = X86_DR7_INIT_VAL;
1023
1024 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1025 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1026 pFpuCtx->FCW = 0x37f;
1027
1028 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1029 IA-32 Processor States Following Power-up, Reset, or INIT */
1030 pFpuCtx->MXCSR = 0x1F80;
1031 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1032 supports all bits, since a zero value here should be read as 0xffbf. */
1033 pCtx->aXcr[0] = XSAVE_C_X87;
1034 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1035 {
1036 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1037 as we don't know what happened before. (Bother optimize later?) */
1038 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1039 }
1040
1041 /*
1042 * MSRs.
1043 */
1044 /* Init PAT MSR */
1045 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1046
1047 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1048 * The Intel docs don't mention it. */
1049 Assert(!pCtx->msrEFER);
1050
1051 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1052 is supposed to be here, just trying provide useful/sensible values. */
1053 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1054 if (pRange)
1055 {
1056 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1057 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1058 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1059 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1060 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1061 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1062 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1063 }
1064
1065 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1066
1067 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1068 * called from each EMT while we're getting called by CPUMR3Reset()
1069 * iteratively on the same thread. Fix later. */
1070#if 0 /** @todo r=bird: This we will do in TM, not here. */
1071 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1072 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1073#endif
1074
1075
1076 /* C-state control. Guesses. */
1077 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1078
1079
1080 /*
1081 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1082 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1083 */
1084 PDMApicGetBase(pVCpu, &pCtx->msrApicBase);
1085}
1086
1087
1088/**
1089 * Resets the CPU.
1090 *
1091 * @returns VINF_SUCCESS.
1092 * @param pVM The cross context VM structure.
1093 */
1094VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1095{
1096 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1097 {
1098 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1099
1100#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1101 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1102
1103 /* Magic marker for searching in crash dumps. */
1104 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1105 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1106 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1107#endif
1108 }
1109}
1110
1111
1112
1113
1114/**
1115 * Pass 0 live exec callback.
1116 *
1117 * @returns VINF_SSM_DONT_CALL_AGAIN.
1118 * @param pVM The cross context VM structure.
1119 * @param pSSM The saved state handle.
1120 * @param uPass The pass (0).
1121 */
1122static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1123{
1124 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1125 cpumR3SaveCpuId(pVM, pSSM);
1126 return VINF_SSM_DONT_CALL_AGAIN;
1127}
1128
1129
1130/**
1131 * Execute state save operation.
1132 *
1133 * @returns VBox status code.
1134 * @param pVM The cross context VM structure.
1135 * @param pSSM SSM operation handle.
1136 */
1137static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1138{
1139 /*
1140 * Save.
1141 */
1142 SSMR3PutU32(pSSM, pVM->cCpus);
1143 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1144 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1145 {
1146 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1147
1148 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1149
1150 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1151 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1152 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1153 if (pGstCtx->fXStateMask != 0)
1154 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1155 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1156 {
1157 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1158 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1159 }
1160 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1161 {
1162 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1163 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1164 }
1165 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1166 {
1167 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1168 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1169 }
1170 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1171 {
1172 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1173 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1174 }
1175 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1176 {
1177 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1178 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1179 }
1180
1181 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1182 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1183 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1184 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1185 }
1186
1187 cpumR3SaveCpuId(pVM, pSSM);
1188 return VINF_SUCCESS;
1189}
1190
1191
1192/**
1193 * @callback_method_impl{FNSSMINTLOADPREP}
1194 */
1195static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1196{
1197 NOREF(pSSM);
1198 pVM->cpum.s.fPendingRestore = true;
1199 return VINF_SUCCESS;
1200}
1201
1202
1203/**
1204 * @callback_method_impl{FNSSMINTLOADEXEC}
1205 */
1206static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1207{
1208 int rc; /* Only for AssertRCReturn use. */
1209
1210 /*
1211 * Validate version.
1212 */
1213 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1214 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1215 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1216 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1217 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1218 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1219 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1220 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1221 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1222 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1223 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1224 {
1225 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1226 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1227 }
1228
1229 if (uPass == SSM_PASS_FINAL)
1230 {
1231 /*
1232 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1233 * really old SSM file versions.)
1234 */
1235 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1236 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1237 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1238 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1239
1240 /*
1241 * Figure x86 and ctx field definitions to use for older states.
1242 */
1243 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1244 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1245 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1246 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1247 {
1248 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1249 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1250 }
1251 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1252 {
1253 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1254 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1255 }
1256
1257 /*
1258 * The hyper state used to preceed the CPU count. Starting with
1259 * XSAVE it was moved down till after we've got the count.
1260 */
1261 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1262 {
1263 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1264 {
1265 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1266 X86FXSTATE Ign;
1267 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1268 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1269 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1270 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1271 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1272 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1273 pVCpu->cpum.s.Hyper.rsp = uRSP;
1274 }
1275 }
1276
1277 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1278 {
1279 uint32_t cCpus;
1280 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1281 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1282 VERR_SSM_UNEXPECTED_DATA);
1283 }
1284 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1285 || pVM->cCpus == 1,
1286 ("cCpus=%u\n", pVM->cCpus),
1287 VERR_SSM_UNEXPECTED_DATA);
1288
1289 uint32_t cbMsrs = 0;
1290 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1291 {
1292 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1293 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1294 VERR_SSM_UNEXPECTED_DATA);
1295 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1296 VERR_SSM_UNEXPECTED_DATA);
1297 }
1298
1299 /*
1300 * Do the per-CPU restoring.
1301 */
1302 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1303 {
1304 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1305 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1306
1307 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1308 {
1309 /*
1310 * The XSAVE saved state layout moved the hyper state down here.
1311 */
1312 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1313 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1314 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1315 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1316 pVCpu->cpum.s.Hyper.rsp = uRSP;
1317 AssertRCReturn(rc, rc);
1318
1319 /*
1320 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1321 */
1322 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1323 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1324 AssertRCReturn(rc, rc);
1325
1326 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1327 if (pGstCtx->fXStateMask != 0)
1328 {
1329 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1330 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1331 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1332 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1333 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1334 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1335 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1336 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1337 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1338 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1339 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1340 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1341 }
1342
1343 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1344 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1345 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1346 {
1347 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1348 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1349 VERR_CPUM_INVALID_XCR0);
1350 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1351 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1352 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1353 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1354 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1355 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1356 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1357 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1358 }
1359
1360 /* Check that the XCR1 is zero, as we don't implement it yet. */
1361 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1362
1363 /*
1364 * Restore the individual extended state components we support.
1365 */
1366 if (pGstCtx->fXStateMask != 0)
1367 {
1368 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1369 0, g_aCpumXSaveHdrFields, NULL);
1370 AssertRCReturn(rc, rc);
1371 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1372 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1373 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1374 VERR_CPUM_INVALID_XSAVE_HDR);
1375 }
1376 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1377 {
1378 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1379 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1380 }
1381 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1382 {
1383 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1384 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1385 }
1386 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1387 {
1388 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1389 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1390 }
1391 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1392 {
1393 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1394 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1395 }
1396 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1397 {
1398 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1399 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1400 }
1401 }
1402 else
1403 {
1404 /*
1405 * Pre XSAVE saved state.
1406 */
1407 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1408 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1409 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1410 }
1411
1412 /*
1413 * Restore a couple of flags and the MSRs.
1414 */
1415 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1416 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1417
1418 rc = VINF_SUCCESS;
1419 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1420 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1421 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1422 {
1423 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1424 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1425 }
1426 AssertRCReturn(rc, rc);
1427
1428 /* REM and other may have cleared must-be-one fields in DR6 and
1429 DR7, fix these. */
1430 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1431 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1432 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1433 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1434 }
1435
1436 /* Older states does not have the internal selector register flags
1437 and valid selector value. Supply those. */
1438 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1439 {
1440 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1441 {
1442 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1443 bool const fValid = HMIsEnabled(pVM)
1444 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1445 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1446 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1447 if (fValid)
1448 {
1449 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1450 {
1451 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1452 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1453 }
1454
1455 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1456 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1457 }
1458 else
1459 {
1460 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1461 {
1462 paSelReg[iSelReg].fFlags = 0;
1463 paSelReg[iSelReg].ValidSel = 0;
1464 }
1465
1466 /* This might not be 104% correct, but I think it's close
1467 enough for all practical purposes... (REM always loaded
1468 LDTR registers.) */
1469 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1470 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1471 }
1472 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1473 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1474 }
1475 }
1476
1477 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1478 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1479 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1480 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1481 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1482
1483 /*
1484 * A quick sanity check.
1485 */
1486 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1487 {
1488 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1489 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1490 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1491 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1492 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1493 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1494 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & !CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1495 }
1496 }
1497
1498 pVM->cpum.s.fPendingRestore = false;
1499
1500 /*
1501 * Guest CPUIDs.
1502 */
1503 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1504 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1505 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1506}
1507
1508
1509/**
1510 * @callback_method_impl{FNSSMINTLOADDONE}
1511 */
1512static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1513{
1514 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1515 return VINF_SUCCESS;
1516
1517 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1518 if (pVM->cpum.s.fPendingRestore)
1519 {
1520 LogRel(("CPUM: Missing state!\n"));
1521 return VERR_INTERNAL_ERROR_2;
1522 }
1523
1524 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1525 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1526 {
1527 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1528
1529 /* Notify PGM of the NXE states in case they've changed. */
1530 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1531
1532 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
1533 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
1534
1535 /* During init. this is done in CPUMR3InitCompleted(). */
1536 if (fSupportsLongMode)
1537 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1538 }
1539 return VINF_SUCCESS;
1540}
1541
1542
1543/**
1544 * Checks if the CPUM state restore is still pending.
1545 *
1546 * @returns true / false.
1547 * @param pVM The cross context VM structure.
1548 */
1549VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1550{
1551 return pVM->cpum.s.fPendingRestore;
1552}
1553
1554
1555/**
1556 * Formats the EFLAGS value into mnemonics.
1557 *
1558 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1559 * @param efl The EFLAGS value.
1560 */
1561static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1562{
1563 /*
1564 * Format the flags.
1565 */
1566 static const struct
1567 {
1568 const char *pszSet; const char *pszClear; uint32_t fFlag;
1569 } s_aFlags[] =
1570 {
1571 { "vip",NULL, X86_EFL_VIP },
1572 { "vif",NULL, X86_EFL_VIF },
1573 { "ac", NULL, X86_EFL_AC },
1574 { "vm", NULL, X86_EFL_VM },
1575 { "rf", NULL, X86_EFL_RF },
1576 { "nt", NULL, X86_EFL_NT },
1577 { "ov", "nv", X86_EFL_OF },
1578 { "dn", "up", X86_EFL_DF },
1579 { "ei", "di", X86_EFL_IF },
1580 { "tf", NULL, X86_EFL_TF },
1581 { "nt", "pl", X86_EFL_SF },
1582 { "nz", "zr", X86_EFL_ZF },
1583 { "ac", "na", X86_EFL_AF },
1584 { "po", "pe", X86_EFL_PF },
1585 { "cy", "nc", X86_EFL_CF },
1586 };
1587 char *psz = pszEFlags;
1588 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1589 {
1590 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1591 if (pszAdd)
1592 {
1593 strcpy(psz, pszAdd);
1594 psz += strlen(pszAdd);
1595 *psz++ = ' ';
1596 }
1597 }
1598 psz[-1] = '\0';
1599}
1600
1601
1602/**
1603 * Formats a full register dump.
1604 *
1605 * @param pVM The cross context VM structure.
1606 * @param pCtx The context to format.
1607 * @param pCtxCore The context core to format.
1608 * @param pHlp Output functions.
1609 * @param enmType The dump type.
1610 * @param pszPrefix Register name prefix.
1611 */
1612static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1613 const char *pszPrefix)
1614{
1615 NOREF(pVM);
1616
1617 /*
1618 * Format the EFLAGS.
1619 */
1620 uint32_t efl = pCtxCore->eflags.u32;
1621 char szEFlags[80];
1622 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1623
1624 /*
1625 * Format the registers.
1626 */
1627 switch (enmType)
1628 {
1629 case CPUMDUMPTYPE_TERSE:
1630 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1631 pHlp->pfnPrintf(pHlp,
1632 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1633 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1634 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1635 "%sr14=%016RX64 %sr15=%016RX64\n"
1636 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1637 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1638 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1639 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1640 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1641 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1642 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1643 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1644 else
1645 pHlp->pfnPrintf(pHlp,
1646 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1647 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1648 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1649 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1650 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1651 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1652 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1653 break;
1654
1655 case CPUMDUMPTYPE_DEFAULT:
1656 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1657 pHlp->pfnPrintf(pHlp,
1658 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1659 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1660 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1661 "%sr14=%016RX64 %sr15=%016RX64\n"
1662 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1663 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1664 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1665 ,
1666 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1667 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1668 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1669 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1670 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1671 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1672 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1673 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1674 else
1675 pHlp->pfnPrintf(pHlp,
1676 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1677 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1678 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1679 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1680 ,
1681 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1682 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1683 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1684 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1685 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1686 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1687 break;
1688
1689 case CPUMDUMPTYPE_VERBOSE:
1690 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1691 pHlp->pfnPrintf(pHlp,
1692 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1693 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1694 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1695 "%sr14=%016RX64 %sr15=%016RX64\n"
1696 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1697 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1698 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1699 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1700 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1701 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1702 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1703 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1704 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1705 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1706 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1707 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1708 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1709 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1710 ,
1711 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1712 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1713 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1714 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1715 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1716 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1717 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1718 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1719 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1720 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1721 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1722 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1723 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1724 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1725 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1726 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1727 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1728 else
1729 pHlp->pfnPrintf(pHlp,
1730 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1731 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1732 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1733 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1734 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1735 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1736 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1737 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1738 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1739 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1740 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1741 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1742 ,
1743 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1744 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1745 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1746 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1747 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1748 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1749 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1750 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1751 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1752 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1753 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1754 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1755
1756 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1757 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1758 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1759 if (pCtx->CTX_SUFF(pXState))
1760 {
1761 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1762 pHlp->pfnPrintf(pHlp,
1763 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1764 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1765 ,
1766 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1767 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1768 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1769 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1770 );
1771 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1772 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1773 {
1774 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1775 unsigned uTag = pFpuCtx->FTW & (1 << iFPR) ? 1 : 0;
1776 char chSign = pFpuCtx->aRegs[0].au16[4] & 0x8000 ? '-' : '+';
1777 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[0].au64[0] >> 63);
1778 uint64_t u64Fraction = pFpuCtx->aRegs[0].au64[0] & UINT64_C(0x7fffffffffffffff);
1779 unsigned uExponent = pFpuCtx->aRegs[0].au16[4] & 0x7fff;
1780 /** @todo This isn't entirenly correct and needs more work! */
1781 pHlp->pfnPrintf(pHlp,
1782 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu ^ %u (*)",
1783 pszPrefix, iST, pszPrefix, iFPR,
1784 pFpuCtx->aRegs[0].au16[4], pFpuCtx->aRegs[0].au32[1], pFpuCtx->aRegs[0].au32[0],
1785 uTag, chSign, iInteger, u64Fraction, uExponent);
1786 if (pFpuCtx->aRegs[0].au16[5] || pFpuCtx->aRegs[0].au16[6] || pFpuCtx->aRegs[0].au16[7])
1787 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1788 pFpuCtx->aRegs[0].au16[5], pFpuCtx->aRegs[0].au16[6], pFpuCtx->aRegs[0].au16[7]);
1789 else
1790 pHlp->pfnPrintf(pHlp, "\n");
1791 }
1792
1793 /* XMM/YMM/ZMM registers. */
1794 if (pCtx->fXStateMask & XSAVE_C_YMM)
1795 {
1796 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1797 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1798 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1799 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1800 pszPrefix, i, i < 10 ? " " : "",
1801 pYmmHiCtx->aYmmHi[i].au32[3],
1802 pYmmHiCtx->aYmmHi[i].au32[2],
1803 pYmmHiCtx->aYmmHi[i].au32[1],
1804 pYmmHiCtx->aYmmHi[i].au32[0],
1805 pFpuCtx->aXMM[i].au32[3],
1806 pFpuCtx->aXMM[i].au32[2],
1807 pFpuCtx->aXMM[i].au32[1],
1808 pFpuCtx->aXMM[i].au32[0]);
1809 else
1810 {
1811 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1812 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1813 pHlp->pfnPrintf(pHlp,
1814 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1815 pszPrefix, i, i < 10 ? " " : "",
1816 pZmmHi256->aHi256Regs[i].au32[7],
1817 pZmmHi256->aHi256Regs[i].au32[6],
1818 pZmmHi256->aHi256Regs[i].au32[5],
1819 pZmmHi256->aHi256Regs[i].au32[4],
1820 pZmmHi256->aHi256Regs[i].au32[3],
1821 pZmmHi256->aHi256Regs[i].au32[2],
1822 pZmmHi256->aHi256Regs[i].au32[1],
1823 pZmmHi256->aHi256Regs[i].au32[0],
1824 pYmmHiCtx->aYmmHi[i].au32[3],
1825 pYmmHiCtx->aYmmHi[i].au32[2],
1826 pYmmHiCtx->aYmmHi[i].au32[1],
1827 pYmmHiCtx->aYmmHi[i].au32[0],
1828 pFpuCtx->aXMM[i].au32[3],
1829 pFpuCtx->aXMM[i].au32[2],
1830 pFpuCtx->aXMM[i].au32[1],
1831 pFpuCtx->aXMM[i].au32[0]);
1832
1833 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1834 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
1835 pHlp->pfnPrintf(pHlp,
1836 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1837 pszPrefix, i + 16,
1838 pZmm16Hi->aRegs[i].au32[15],
1839 pZmm16Hi->aRegs[i].au32[14],
1840 pZmm16Hi->aRegs[i].au32[13],
1841 pZmm16Hi->aRegs[i].au32[12],
1842 pZmm16Hi->aRegs[i].au32[11],
1843 pZmm16Hi->aRegs[i].au32[10],
1844 pZmm16Hi->aRegs[i].au32[9],
1845 pZmm16Hi->aRegs[i].au32[8],
1846 pZmm16Hi->aRegs[i].au32[7],
1847 pZmm16Hi->aRegs[i].au32[6],
1848 pZmm16Hi->aRegs[i].au32[5],
1849 pZmm16Hi->aRegs[i].au32[4],
1850 pZmm16Hi->aRegs[i].au32[3],
1851 pZmm16Hi->aRegs[i].au32[2],
1852 pZmm16Hi->aRegs[i].au32[1],
1853 pZmm16Hi->aRegs[i].au32[0]);
1854 }
1855 }
1856 else
1857 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1858 pHlp->pfnPrintf(pHlp,
1859 i & 1
1860 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1861 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1862 pszPrefix, i, i < 10 ? " " : "",
1863 pFpuCtx->aXMM[i].au32[3],
1864 pFpuCtx->aXMM[i].au32[2],
1865 pFpuCtx->aXMM[i].au32[1],
1866 pFpuCtx->aXMM[i].au32[0]);
1867
1868 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
1869 {
1870 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
1871 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
1872 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
1873 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
1874 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
1875 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
1876 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
1877 }
1878
1879 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
1880 {
1881 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1882 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
1883 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
1884 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
1885 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
1886 }
1887
1888 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
1889 {
1890 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1891 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
1892 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
1893 }
1894
1895 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1896 if (pFpuCtx->au32RsrvdRest[i])
1897 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
1898 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1899 }
1900
1901 pHlp->pfnPrintf(pHlp,
1902 "%sEFER =%016RX64\n"
1903 "%sPAT =%016RX64\n"
1904 "%sSTAR =%016RX64\n"
1905 "%sCSTAR =%016RX64\n"
1906 "%sLSTAR =%016RX64\n"
1907 "%sSFMASK =%016RX64\n"
1908 "%sKERNELGSBASE =%016RX64\n",
1909 pszPrefix, pCtx->msrEFER,
1910 pszPrefix, pCtx->msrPAT,
1911 pszPrefix, pCtx->msrSTAR,
1912 pszPrefix, pCtx->msrCSTAR,
1913 pszPrefix, pCtx->msrLSTAR,
1914 pszPrefix, pCtx->msrSFMASK,
1915 pszPrefix, pCtx->msrKERNELGSBASE);
1916 break;
1917 }
1918}
1919
1920
1921/**
1922 * Display all cpu states and any other cpum info.
1923 *
1924 * @param pVM The cross context VM structure.
1925 * @param pHlp The info helper functions.
1926 * @param pszArgs Arguments, ignored.
1927 */
1928static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1929{
1930 cpumR3InfoGuest(pVM, pHlp, pszArgs);
1931 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
1932 cpumR3InfoHyper(pVM, pHlp, pszArgs);
1933 cpumR3InfoHost(pVM, pHlp, pszArgs);
1934}
1935
1936
1937/**
1938 * Parses the info argument.
1939 *
1940 * The argument starts with 'verbose', 'terse' or 'default' and then
1941 * continues with the comment string.
1942 *
1943 * @param pszArgs The pointer to the argument string.
1944 * @param penmType Where to store the dump type request.
1945 * @param ppszComment Where to store the pointer to the comment string.
1946 */
1947static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
1948{
1949 if (!pszArgs)
1950 {
1951 *penmType = CPUMDUMPTYPE_DEFAULT;
1952 *ppszComment = "";
1953 }
1954 else
1955 {
1956 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
1957 {
1958 pszArgs += 7;
1959 *penmType = CPUMDUMPTYPE_VERBOSE;
1960 }
1961 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
1962 {
1963 pszArgs += 5;
1964 *penmType = CPUMDUMPTYPE_TERSE;
1965 }
1966 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
1967 {
1968 pszArgs += 7;
1969 *penmType = CPUMDUMPTYPE_DEFAULT;
1970 }
1971 else
1972 *penmType = CPUMDUMPTYPE_DEFAULT;
1973 *ppszComment = RTStrStripL(pszArgs);
1974 }
1975}
1976
1977
1978/**
1979 * Display the guest cpu state.
1980 *
1981 * @param pVM The cross context VM structure.
1982 * @param pHlp The info helper functions.
1983 * @param pszArgs Arguments, ignored.
1984 */
1985static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1986{
1987 CPUMDUMPTYPE enmType;
1988 const char *pszComment;
1989 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
1990
1991 /* @todo SMP support! */
1992 PVMCPU pVCpu = VMMGetCpu(pVM);
1993 if (!pVCpu)
1994 pVCpu = &pVM->aCpus[0];
1995
1996 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
1997
1998 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1999 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2000}
2001
2002
2003/**
2004 * Display the current guest instruction
2005 *
2006 * @param pVM The cross context VM structure.
2007 * @param pHlp The info helper functions.
2008 * @param pszArgs Arguments, ignored.
2009 */
2010static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2011{
2012 NOREF(pszArgs);
2013
2014 /** @todo SMP support! */
2015 PVMCPU pVCpu = VMMGetCpu(pVM);
2016 if (!pVCpu)
2017 pVCpu = &pVM->aCpus[0];
2018
2019 char szInstruction[256];
2020 szInstruction[0] = '\0';
2021 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2022 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2023}
2024
2025
2026/**
2027 * Display the hypervisor cpu state.
2028 *
2029 * @param pVM The cross context VM structure.
2030 * @param pHlp The info helper functions.
2031 * @param pszArgs Arguments, ignored.
2032 */
2033static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2034{
2035 CPUMDUMPTYPE enmType;
2036 const char *pszComment;
2037 /* @todo SMP */
2038 PVMCPU pVCpu = &pVM->aCpus[0];
2039
2040 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2041 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2042 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2043 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2044}
2045
2046
2047/**
2048 * Display the host cpu state.
2049 *
2050 * @param pVM The cross context VM structure.
2051 * @param pHlp The info helper functions.
2052 * @param pszArgs Arguments, ignored.
2053 */
2054static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2055{
2056 CPUMDUMPTYPE enmType;
2057 const char *pszComment;
2058 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2059 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2060
2061 /*
2062 * Format the EFLAGS.
2063 */
2064 /* @todo SMP */
2065 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2066#if HC_ARCH_BITS == 32
2067 uint32_t efl = pCtx->eflags.u32;
2068#else
2069 uint64_t efl = pCtx->rflags;
2070#endif
2071 char szEFlags[80];
2072 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2073
2074 /*
2075 * Format the registers.
2076 */
2077#if HC_ARCH_BITS == 32
2078 pHlp->pfnPrintf(pHlp,
2079 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2080 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2081 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2082 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2083 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2084 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2085 ,
2086 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2087 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2088 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2089 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2090 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2091 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2092 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2093#else
2094 pHlp->pfnPrintf(pHlp,
2095 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2096 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2097 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2098 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2099 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2100 "r14=%016RX64 r15=%016RX64\n"
2101 "iopl=%d %31s\n"
2102 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2103 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2104 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2105 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2106 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2107 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2108 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2109 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2110 ,
2111 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2112 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2113 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2114 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2115 pCtx->r11, pCtx->r12, pCtx->r13,
2116 pCtx->r14, pCtx->r15,
2117 X86_EFL_GET_IOPL(efl), szEFlags,
2118 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2119 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2120 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2121 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2122 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2123 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2124 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2125 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2126#endif
2127}
2128
2129/**
2130 * Structure used when disassembling and instructions in DBGF.
2131 * This is used so the reader function can get the stuff it needs.
2132 */
2133typedef struct CPUMDISASSTATE
2134{
2135 /** Pointer to the CPU structure. */
2136 PDISCPUSTATE pCpu;
2137 /** Pointer to the VM. */
2138 PVM pVM;
2139 /** Pointer to the VMCPU. */
2140 PVMCPU pVCpu;
2141 /** Pointer to the first byte in the segment. */
2142 RTGCUINTPTR GCPtrSegBase;
2143 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2144 RTGCUINTPTR GCPtrSegEnd;
2145 /** The size of the segment minus 1. */
2146 RTGCUINTPTR cbSegLimit;
2147 /** Pointer to the current page - R3 Ptr. */
2148 void const *pvPageR3;
2149 /** Pointer to the current page - GC Ptr. */
2150 RTGCPTR pvPageGC;
2151 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2152 PGMPAGEMAPLOCK PageMapLock;
2153 /** Whether the PageMapLock is valid or not. */
2154 bool fLocked;
2155 /** 64 bits mode or not. */
2156 bool f64Bits;
2157} CPUMDISASSTATE, *PCPUMDISASSTATE;
2158
2159
2160/**
2161 * @callback_method_impl{FNDISREADBYTES}
2162 */
2163static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2164{
2165 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2166 for (;;)
2167 {
2168 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2169
2170 /*
2171 * Need to update the page translation?
2172 */
2173 if ( !pState->pvPageR3
2174 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2175 {
2176 int rc = VINF_SUCCESS;
2177
2178 /* translate the address */
2179 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2180 if ( !HMIsEnabled(pState->pVM)
2181 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2182 {
2183 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2184 if (!pState->pvPageR3)
2185 rc = VERR_INVALID_POINTER;
2186 }
2187 else
2188 {
2189 /* Release mapping lock previously acquired. */
2190 if (pState->fLocked)
2191 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2192 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2193 pState->fLocked = RT_SUCCESS_NP(rc);
2194 }
2195 if (RT_FAILURE(rc))
2196 {
2197 pState->pvPageR3 = NULL;
2198 return rc;
2199 }
2200 }
2201
2202 /*
2203 * Check the segment limit.
2204 */
2205 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2206 return VERR_OUT_OF_SELECTOR_BOUNDS;
2207
2208 /*
2209 * Calc how much we can read.
2210 */
2211 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2212 if (!pState->f64Bits)
2213 {
2214 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2215 if (cb > cbSeg && cbSeg)
2216 cb = cbSeg;
2217 }
2218 if (cb > cbMaxRead)
2219 cb = cbMaxRead;
2220
2221 /*
2222 * Read and advance or exit.
2223 */
2224 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2225 offInstr += (uint8_t)cb;
2226 if (cb >= cbMinRead)
2227 {
2228 pDis->cbCachedInstr = offInstr;
2229 return VINF_SUCCESS;
2230 }
2231 cbMinRead -= (uint8_t)cb;
2232 cbMaxRead -= (uint8_t)cb;
2233 }
2234}
2235
2236
2237/**
2238 * Disassemble an instruction and return the information in the provided structure.
2239 *
2240 * @returns VBox status code.
2241 * @param pVM The cross context VM structure.
2242 * @param pVCpu The cross context virtual CPU structure.
2243 * @param pCtx Pointer to the guest CPU context.
2244 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2245 * @param pCpu Disassembly state.
2246 * @param pszPrefix String prefix for logging (debug only).
2247 *
2248 */
2249VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2250{
2251 CPUMDISASSTATE State;
2252 int rc;
2253
2254 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2255 State.pCpu = pCpu;
2256 State.pvPageGC = 0;
2257 State.pvPageR3 = NULL;
2258 State.pVM = pVM;
2259 State.pVCpu = pVCpu;
2260 State.fLocked = false;
2261 State.f64Bits = false;
2262
2263 /*
2264 * Get selector information.
2265 */
2266 DISCPUMODE enmDisCpuMode;
2267 if ( (pCtx->cr0 & X86_CR0_PE)
2268 && pCtx->eflags.Bits.u1VM == 0)
2269 {
2270 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2271 {
2272# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2273 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2274# endif
2275 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2276 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2277 }
2278 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2279 State.GCPtrSegBase = pCtx->cs.u64Base;
2280 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2281 State.cbSegLimit = pCtx->cs.u32Limit;
2282 enmDisCpuMode = (State.f64Bits)
2283 ? DISCPUMODE_64BIT
2284 : pCtx->cs.Attr.n.u1DefBig
2285 ? DISCPUMODE_32BIT
2286 : DISCPUMODE_16BIT;
2287 }
2288 else
2289 {
2290 /* real or V86 mode */
2291 enmDisCpuMode = DISCPUMODE_16BIT;
2292 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2293 State.GCPtrSegEnd = 0xFFFFFFFF;
2294 State.cbSegLimit = 0xFFFFFFFF;
2295 }
2296
2297 /*
2298 * Disassemble the instruction.
2299 */
2300 uint32_t cbInstr;
2301#ifndef LOG_ENABLED
2302 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2303 if (RT_SUCCESS(rc))
2304 {
2305#else
2306 char szOutput[160];
2307 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2308 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2309 if (RT_SUCCESS(rc))
2310 {
2311 /* log it */
2312 if (pszPrefix)
2313 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2314 else
2315 Log(("%s", szOutput));
2316#endif
2317 rc = VINF_SUCCESS;
2318 }
2319 else
2320 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2321
2322 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2323 if (State.fLocked)
2324 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2325
2326 return rc;
2327}
2328
2329
2330
2331/**
2332 * API for controlling a few of the CPU features found in CR4.
2333 *
2334 * Currently only X86_CR4_TSD is accepted as input.
2335 *
2336 * @returns VBox status code.
2337 *
2338 * @param pVM The cross context VM structure.
2339 * @param fOr The CR4 OR mask.
2340 * @param fAnd The CR4 AND mask.
2341 */
2342VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2343{
2344 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2345 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2346
2347 pVM->cpum.s.CR4.OrMask &= fAnd;
2348 pVM->cpum.s.CR4.OrMask |= fOr;
2349
2350 return VINF_SUCCESS;
2351}
2352
2353
2354/**
2355 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2356 *
2357 * Only REM should ever call this function!
2358 *
2359 * @returns The changed flags.
2360 * @param pVCpu The cross context virtual CPU structure.
2361 * @param puCpl Where to return the current privilege level (CPL).
2362 */
2363VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2364{
2365 Assert(!pVCpu->cpum.s.fRawEntered);
2366 Assert(!pVCpu->cpum.s.fRemEntered);
2367
2368 /*
2369 * Get the CPL first.
2370 */
2371 *puCpl = CPUMGetGuestCPL(pVCpu);
2372
2373 /*
2374 * Get and reset the flags.
2375 */
2376 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2377 pVCpu->cpum.s.fChanged = 0;
2378
2379 /** @todo change the switcher to use the fChanged flags. */
2380 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2381 {
2382 fFlags |= CPUM_CHANGED_FPU_REM;
2383 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2384 }
2385
2386 pVCpu->cpum.s.fRemEntered = true;
2387 return fFlags;
2388}
2389
2390
2391/**
2392 * Leaves REM.
2393 *
2394 * @param pVCpu The cross context virtual CPU structure.
2395 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2396 * registers.
2397 */
2398VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2399{
2400 Assert(!pVCpu->cpum.s.fRawEntered);
2401 Assert(pVCpu->cpum.s.fRemEntered);
2402
2403 pVCpu->cpum.s.fRemEntered = false;
2404}
2405
2406
2407/**
2408 * Called when the ring-3 init phase completes.
2409 *
2410 * @returns VBox status code.
2411 * @param pVM The cross context VM structure.
2412 */
2413VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM)
2414{
2415 /*
2416 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2417 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2418 */
2419 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2420 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2421 {
2422 PVMCPU pVCpu = &pVM->aCpus[i];
2423
2424 /* Cache the APIC base (from the APIC device) once it has been initialized. */
2425 PDMApicGetBase(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase);
2426 Log(("CPUMR3InitCompleted pVM=%p APIC base[%u]=%RX64\n", pVM, (unsigned)i, pVCpu->cpum.s.Guest.msrApicBase));
2427
2428 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2429 if (fSupportsLongMode)
2430 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2431 }
2432
2433 cpumR3MsrRegStats(pVM);
2434 return VINF_SUCCESS;
2435}
2436
2437
2438/**
2439 * Called when the ring-0 init phases completed.
2440 *
2441 * @param pVM The cross context VM structure.
2442 */
2443VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2444{
2445 /*
2446 * Log the cpuid.
2447 */
2448 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2449 RTCPUSET OnlineSet;
2450 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2451 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2452 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2453 RTCPUID cCores = RTMpGetCoreCount();
2454 if (cCores)
2455 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2456 LogRel(("************************* CPUID dump ************************\n"));
2457 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2458 LogRel(("\n"));
2459 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
2460 RTLogRelSetBuffering(fOldBuffered);
2461 LogRel(("******************** End of CPUID dump **********************\n"));
2462}
2463
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