VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 61341

Last change on this file since 61341 was 61341, checked in by vboxsync, 9 years ago

CPUM: words about FPU state.
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1/* $Id: CPUM.cpp 61341 2016-05-31 15:30:30Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 *
33 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34 *
35 * TODO: proper write up, currently just some notes.
36 *
37 * The ring-0 FPU handling per OS:
38 *
39 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
40 * convention (Visual C++ doesn't seem to have a way to disable
41 * generating such code either), so CR0.TS/EM are always zero from what I
42 * can tell. We are also forced to always load/save the guest XMM0-XMM15
43 * registers when entering/leaving guest context. Interrupt handlers
44 * using FPU/SSE will offically have call save and restore functions
45 * exported by the kernel, if the really really have to use the state.
46 *
47 * - 32-bit windows does lazy FPU handling, I think, probably including
48 * lazying saving. The Windows Internals book states that it's a bad
49 * idea to use the FPU in kernel space. However, it looks like it will
50 * restore the FPU state of the current thread in case of a kernel \#NM.
51 * Interrupt handlers should be same as for 64-bit.
52 *
53 * - Darwin allows taking \#NM in kernel space, restoring current thread's
54 * state if I read the code correctly. It saves the FPU state of the
55 * outgoing thread, and uses CR0.TS to lazily load the state of the
56 * incoming one. No idea yet how the FPU is treated by interrupt
57 * handlers, i.e. whether they are allowed to disable the state or
58 * something.
59 *
60 * - Linux also allows \#NM in kernel space (don't know since when), and
61 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62 * loads the incoming unless configured to agressivly load it. Interrupt
63 * handlers can ask whether they're allowed to use the FPU, and may
64 * freely trash the state if Linux thinks it has saved the thread's state
65 * already. This is a problem.
66 *
67 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68 * context. When switching threads, the kernel will save the state of
69 * the outgoing thread and lazy load the incoming one using CR0.TS.
70 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
71 * to do stuff, HAT are among the users. The routines there will
72 * manually clear CR0.TS and save the XMM registers they use only if
73 * CR0.TS was zero upon entry. They will skip it when not, because as
74 * mentioned above, the FPU state is saved when switching away from a
75 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76 * preserve. This is a problem if we restore CR0.TS to 1 after loading
77 * the guest state.
78 *
79 * - FreeBSD - no idea yet.
80 *
81 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83 * FPU states.
84 *
85 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86 * saving and restoring the host and guest states. The motivation for this
87 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88 *
89 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90 * state and only restore it once we've restore the host FPU state. This has the
91 * accidental side effect of triggering Solaris to preserve XMM registers in
92 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94 *
95 */
96
97
98/*********************************************************************************************************************************
99* Header Files *
100*********************************************************************************************************************************/
101#define LOG_GROUP LOG_GROUP_CPUM
102#include <VBox/vmm/cpum.h>
103#include <VBox/vmm/cpumdis.h>
104#include <VBox/vmm/cpumctx-v1_6.h>
105#include <VBox/vmm/pgm.h>
106#include <VBox/vmm/pdmapi.h>
107#include <VBox/vmm/mm.h>
108#include <VBox/vmm/em.h>
109#include <VBox/vmm/selm.h>
110#include <VBox/vmm/dbgf.h>
111#include <VBox/vmm/patm.h>
112#include <VBox/vmm/hm.h>
113#include <VBox/vmm/ssm.h>
114#include "CPUMInternal.h"
115#include <VBox/vmm/vm.h>
116
117#include <VBox/param.h>
118#include <VBox/dis.h>
119#include <VBox/err.h>
120#include <VBox/log.h>
121#include <iprt/asm-amd64-x86.h>
122#include <iprt/assert.h>
123#include <iprt/cpuset.h>
124#include <iprt/mem.h>
125#include <iprt/mp.h>
126#include <iprt/string.h>
127#include "internal/pgm.h"
128
129
130/*********************************************************************************************************************************
131* Defined Constants And Macros *
132*********************************************************************************************************************************/
133/**
134 * This was used in the saved state up to the early life of version 14.
135 *
136 * It indicates that we may have some out-of-sync hidden segement registers.
137 * It is only relevant for raw-mode.
138 */
139#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
140
141
142/*********************************************************************************************************************************
143* Structures and Typedefs *
144*********************************************************************************************************************************/
145
146/**
147 * What kind of cpu info dump to perform.
148 */
149typedef enum CPUMDUMPTYPE
150{
151 CPUMDUMPTYPE_TERSE,
152 CPUMDUMPTYPE_DEFAULT,
153 CPUMDUMPTYPE_VERBOSE
154} CPUMDUMPTYPE;
155/** Pointer to a cpu info dump type. */
156typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
157
158
159/*********************************************************************************************************************************
160* Internal Functions *
161*********************************************************************************************************************************/
162static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
163static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
164static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
165static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
166static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
167static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
168static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
169static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
170static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
171static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
172
173
174/*********************************************************************************************************************************
175* Global Variables *
176*********************************************************************************************************************************/
177/** Saved state field descriptors for CPUMCTX. */
178static const SSMFIELD g_aCpumCtxFields[] =
179{
180 SSMFIELD_ENTRY( CPUMCTX, rdi),
181 SSMFIELD_ENTRY( CPUMCTX, rsi),
182 SSMFIELD_ENTRY( CPUMCTX, rbp),
183 SSMFIELD_ENTRY( CPUMCTX, rax),
184 SSMFIELD_ENTRY( CPUMCTX, rbx),
185 SSMFIELD_ENTRY( CPUMCTX, rdx),
186 SSMFIELD_ENTRY( CPUMCTX, rcx),
187 SSMFIELD_ENTRY( CPUMCTX, rsp),
188 SSMFIELD_ENTRY( CPUMCTX, rflags),
189 SSMFIELD_ENTRY( CPUMCTX, rip),
190 SSMFIELD_ENTRY( CPUMCTX, r8),
191 SSMFIELD_ENTRY( CPUMCTX, r9),
192 SSMFIELD_ENTRY( CPUMCTX, r10),
193 SSMFIELD_ENTRY( CPUMCTX, r11),
194 SSMFIELD_ENTRY( CPUMCTX, r12),
195 SSMFIELD_ENTRY( CPUMCTX, r13),
196 SSMFIELD_ENTRY( CPUMCTX, r14),
197 SSMFIELD_ENTRY( CPUMCTX, r15),
198 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
199 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
200 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
201 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
202 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
203 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
204 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
229 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
230 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
231 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
232 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
233 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
234 SSMFIELD_ENTRY( CPUMCTX, cr0),
235 SSMFIELD_ENTRY( CPUMCTX, cr2),
236 SSMFIELD_ENTRY( CPUMCTX, cr3),
237 SSMFIELD_ENTRY( CPUMCTX, cr4),
238 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
239 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
240 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
241 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
242 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
243 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
244 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
245 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
246 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
247 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
248 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
249 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
250 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
251 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
252 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
253 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
254 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
255 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
256 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
257 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
258 /* msrApicBase is not included here, it resides in the APIC device state. */
259 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
260 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
261 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
262 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
263 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
264 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
265 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
266 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
267 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
268 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
269 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
270 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
271 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
272 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
273 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
274 SSMFIELD_ENTRY_TERM()
275};
276
277/** Saved state field descriptors for CPUMCTX. */
278static const SSMFIELD g_aCpumX87Fields[] =
279{
280 SSMFIELD_ENTRY( X86FXSTATE, FCW),
281 SSMFIELD_ENTRY( X86FXSTATE, FSW),
282 SSMFIELD_ENTRY( X86FXSTATE, FTW),
283 SSMFIELD_ENTRY( X86FXSTATE, FOP),
284 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
285 SSMFIELD_ENTRY( X86FXSTATE, CS),
286 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
287 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
288 SSMFIELD_ENTRY( X86FXSTATE, DS),
289 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
290 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
291 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
292 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
293 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
294 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
295 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
296 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
297 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
298 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
299 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
300 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
301 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
302 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
303 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
304 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
305 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
306 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
307 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
308 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
309 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
310 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
311 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
312 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
313 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
314 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
315 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
316 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
317 SSMFIELD_ENTRY_TERM()
318};
319
320/** Saved state field descriptors for X86XSAVEHDR. */
321static const SSMFIELD g_aCpumXSaveHdrFields[] =
322{
323 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
324 SSMFIELD_ENTRY_TERM()
325};
326
327/** Saved state field descriptors for X86XSAVEYMMHI. */
328static const SSMFIELD g_aCpumYmmHiFields[] =
329{
330 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
331 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
332 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
333 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
334 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
335 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
336 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
337 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
338 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
339 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
340 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
341 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
342 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
343 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
344 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
345 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
346 SSMFIELD_ENTRY_TERM()
347};
348
349/** Saved state field descriptors for X86XSAVEBNDREGS. */
350static const SSMFIELD g_aCpumBndRegsFields[] =
351{
352 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
353 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
354 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
355 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
356 SSMFIELD_ENTRY_TERM()
357};
358
359/** Saved state field descriptors for X86XSAVEBNDCFG. */
360static const SSMFIELD g_aCpumBndCfgFields[] =
361{
362 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
363 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
364 SSMFIELD_ENTRY_TERM()
365};
366
367/** Saved state field descriptors for X86XSAVEOPMASK. */
368static const SSMFIELD g_aCpumOpmaskFields[] =
369{
370 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
371 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
372 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
373 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
374 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
375 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
376 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
377 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
378 SSMFIELD_ENTRY_TERM()
379};
380
381/** Saved state field descriptors for X86XSAVEZMMHI256. */
382static const SSMFIELD g_aCpumZmmHi256Fields[] =
383{
384 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
385 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
386 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
387 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
388 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
389 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
390 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
391 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
392 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
393 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
394 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
395 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
396 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
397 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
398 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
399 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
400 SSMFIELD_ENTRY_TERM()
401};
402
403/** Saved state field descriptors for X86XSAVEZMM16HI. */
404static const SSMFIELD g_aCpumZmm16HiFields[] =
405{
406 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
407 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
408 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
409 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
410 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
411 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
412 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
413 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
414 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
415 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
416 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
417 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
418 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
419 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
420 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
421 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
422 SSMFIELD_ENTRY_TERM()
423};
424
425
426
427/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
428 * registeres changed. */
429static const SSMFIELD g_aCpumX87FieldsMem[] =
430{
431 SSMFIELD_ENTRY( X86FXSTATE, FCW),
432 SSMFIELD_ENTRY( X86FXSTATE, FSW),
433 SSMFIELD_ENTRY( X86FXSTATE, FTW),
434 SSMFIELD_ENTRY( X86FXSTATE, FOP),
435 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
436 SSMFIELD_ENTRY( X86FXSTATE, CS),
437 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
438 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
439 SSMFIELD_ENTRY( X86FXSTATE, DS),
440 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
441 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
442 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
443 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
444 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
445 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
446 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
447 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
448 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
449 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
450 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
451 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
452 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
453 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
454 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
455 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
456 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
457 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
458 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
459 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
460 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
461 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
462 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
463 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
464 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
465 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
466 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
467 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
468 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
469};
470
471/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
472 * registeres changed. */
473static const SSMFIELD g_aCpumCtxFieldsMem[] =
474{
475 SSMFIELD_ENTRY( CPUMCTX, rdi),
476 SSMFIELD_ENTRY( CPUMCTX, rsi),
477 SSMFIELD_ENTRY( CPUMCTX, rbp),
478 SSMFIELD_ENTRY( CPUMCTX, rax),
479 SSMFIELD_ENTRY( CPUMCTX, rbx),
480 SSMFIELD_ENTRY( CPUMCTX, rdx),
481 SSMFIELD_ENTRY( CPUMCTX, rcx),
482 SSMFIELD_ENTRY( CPUMCTX, rsp),
483 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
484 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
485 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
486 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
487 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
488 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
489 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
490 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
491 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
492 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
493 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
494 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
495 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
496 SSMFIELD_ENTRY( CPUMCTX, rflags),
497 SSMFIELD_ENTRY( CPUMCTX, rip),
498 SSMFIELD_ENTRY( CPUMCTX, r8),
499 SSMFIELD_ENTRY( CPUMCTX, r9),
500 SSMFIELD_ENTRY( CPUMCTX, r10),
501 SSMFIELD_ENTRY( CPUMCTX, r11),
502 SSMFIELD_ENTRY( CPUMCTX, r12),
503 SSMFIELD_ENTRY( CPUMCTX, r13),
504 SSMFIELD_ENTRY( CPUMCTX, r14),
505 SSMFIELD_ENTRY( CPUMCTX, r15),
506 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
507 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
508 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
509 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
510 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
511 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
512 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
513 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
514 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
515 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
516 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
517 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
518 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
519 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
520 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
521 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
522 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
523 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
524 SSMFIELD_ENTRY( CPUMCTX, cr0),
525 SSMFIELD_ENTRY( CPUMCTX, cr2),
526 SSMFIELD_ENTRY( CPUMCTX, cr3),
527 SSMFIELD_ENTRY( CPUMCTX, cr4),
528 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
529 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
530 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
531 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
532 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
533 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
534 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
535 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
536 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
537 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
538 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
539 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
540 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
541 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
542 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
543 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
544 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
545 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
546 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
547 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
548 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
549 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
550 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
551 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
552 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
553 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
554 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
555 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
556 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
557 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
558 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
559 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
560 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
561 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
562 SSMFIELD_ENTRY_TERM()
563};
564
565/** Saved state field descriptors for CPUMCTX_VER1_6. */
566static const SSMFIELD g_aCpumX87FieldsV16[] =
567{
568 SSMFIELD_ENTRY( X86FXSTATE, FCW),
569 SSMFIELD_ENTRY( X86FXSTATE, FSW),
570 SSMFIELD_ENTRY( X86FXSTATE, FTW),
571 SSMFIELD_ENTRY( X86FXSTATE, FOP),
572 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
573 SSMFIELD_ENTRY( X86FXSTATE, CS),
574 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
575 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
576 SSMFIELD_ENTRY( X86FXSTATE, DS),
577 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
578 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
579 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
580 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
581 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
582 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
583 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
584 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
585 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
586 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
587 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
588 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
589 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
590 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
591 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
592 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
593 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
594 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
595 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
596 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
597 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
598 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
599 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
600 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
601 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
602 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
603 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
604 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
605 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
606 SSMFIELD_ENTRY_TERM()
607};
608
609/** Saved state field descriptors for CPUMCTX_VER1_6. */
610static const SSMFIELD g_aCpumCtxFieldsV16[] =
611{
612 SSMFIELD_ENTRY( CPUMCTX, rdi),
613 SSMFIELD_ENTRY( CPUMCTX, rsi),
614 SSMFIELD_ENTRY( CPUMCTX, rbp),
615 SSMFIELD_ENTRY( CPUMCTX, rax),
616 SSMFIELD_ENTRY( CPUMCTX, rbx),
617 SSMFIELD_ENTRY( CPUMCTX, rdx),
618 SSMFIELD_ENTRY( CPUMCTX, rcx),
619 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
620 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
621 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
622 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
623 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
624 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
625 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
626 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
627 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
628 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
629 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
630 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
631 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
632 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
633 SSMFIELD_ENTRY( CPUMCTX, rflags),
634 SSMFIELD_ENTRY( CPUMCTX, rip),
635 SSMFIELD_ENTRY( CPUMCTX, r8),
636 SSMFIELD_ENTRY( CPUMCTX, r9),
637 SSMFIELD_ENTRY( CPUMCTX, r10),
638 SSMFIELD_ENTRY( CPUMCTX, r11),
639 SSMFIELD_ENTRY( CPUMCTX, r12),
640 SSMFIELD_ENTRY( CPUMCTX, r13),
641 SSMFIELD_ENTRY( CPUMCTX, r14),
642 SSMFIELD_ENTRY( CPUMCTX, r15),
643 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
644 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
645 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
646 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
647 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
648 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
649 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
650 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
651 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
652 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
653 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
654 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
655 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
656 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
657 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
658 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
659 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
660 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
661 SSMFIELD_ENTRY( CPUMCTX, cr0),
662 SSMFIELD_ENTRY( CPUMCTX, cr2),
663 SSMFIELD_ENTRY( CPUMCTX, cr3),
664 SSMFIELD_ENTRY( CPUMCTX, cr4),
665 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
666 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
667 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
668 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
669 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
670 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
671 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
672 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
673 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
674 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
675 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
676 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
677 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
678 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
679 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
680 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
681 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
682 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
683 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
684 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
685 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
686 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
687 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
688 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
689 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
690 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
691 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
692 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
693 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
694 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
695 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
696 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
697 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
698 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
699 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
700 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
701 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
702 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
703 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
704 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
705 SSMFIELD_ENTRY_TERM()
706};
707
708
709/**
710 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
711 *
712 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
713 * (last instruction pointer, last data pointer, last opcode) except when the ES
714 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
715 * clear these registers there is potential, local FPU leakage from a process
716 * using the FPU to another.
717 *
718 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
719 *
720 * @param pVM The cross context VM structure.
721 */
722static void cpumR3CheckLeakyFpu(PVM pVM)
723{
724 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
725 uint32_t const u32Family = u32CpuVersion >> 8;
726 if ( u32Family >= 6 /* K7 and higher */
727 && ASMIsAmdCpu())
728 {
729 uint32_t cExt = ASMCpuId_EAX(0x80000000);
730 if (ASMIsValidExtRange(cExt))
731 {
732 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
733 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
734 {
735 for (VMCPUID i = 0; i < pVM->cCpus; i++)
736 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
737 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
738 }
739 }
740 }
741}
742
743
744/**
745 * Initializes the CPUM.
746 *
747 * @returns VBox status code.
748 * @param pVM The cross context VM structure.
749 */
750VMMR3DECL(int) CPUMR3Init(PVM pVM)
751{
752 LogFlow(("CPUMR3Init\n"));
753
754 /*
755 * Assert alignment, sizes and tables.
756 */
757 AssertCompileMemberAlignment(VM, cpum.s, 32);
758 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
759 AssertCompileSizeAlignment(CPUMCTX, 64);
760 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
761 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
762 AssertCompileMemberAlignment(VM, cpum, 64);
763 AssertCompileMemberAlignment(VM, aCpus, 64);
764 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
765 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
766#ifdef VBOX_STRICT
767 int rc2 = cpumR3MsrStrictInitChecks();
768 AssertRCReturn(rc2, rc2);
769#endif
770
771 /*
772 * Initialize offsets.
773 */
774
775 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
776 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
777 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
778
779
780 /* Calculate the offset from CPUMCPU to CPUM. */
781 for (VMCPUID i = 0; i < pVM->cCpus; i++)
782 {
783 PVMCPU pVCpu = &pVM->aCpus[i];
784
785 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
786 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
787 }
788
789 /*
790 * Gather info about the host CPU.
791 */
792 if (!ASMHasCpuId())
793 {
794 Log(("The CPU doesn't support CPUID!\n"));
795 return VERR_UNSUPPORTED_CPU;
796 }
797
798 PCPUMCPUIDLEAF paLeaves;
799 uint32_t cLeaves;
800 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
801 AssertLogRelRCReturn(rc, rc);
802
803 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
804 RTMemFree(paLeaves);
805 AssertLogRelRCReturn(rc, rc);
806 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
807
808 /*
809 * Check that the CPU supports the minimum features we require.
810 */
811 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
812 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
813 if (!pVM->cpum.s.HostFeatures.fMmx)
814 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
815 if (!pVM->cpum.s.HostFeatures.fTsc)
816 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
817
818 /*
819 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
820 */
821 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
822 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
823
824 /*
825 * Figure out which XSAVE/XRSTOR features are available on the host.
826 */
827 uint64_t fXcr0Host = 0;
828 uint64_t fXStateHostMask = 0;
829 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
830 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
831 {
832 fXStateHostMask = fXcr0Host = ASMGetXcr0();
833 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
834 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
835 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
836 }
837 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
838 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
839 fXStateHostMask = 0;
840 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
841 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
842
843 /*
844 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
845 */
846 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
847 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
848 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
849
850 uint8_t *pbXStates;
851 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
852 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
853 AssertLogRelRCReturn(rc, rc);
854
855 for (VMCPUID i = 0; i < pVM->cCpus; i++)
856 {
857 PVMCPU pVCpu = &pVM->aCpus[i];
858
859 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
860 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
861 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
862 pbXStates += cbMaxXState;
863
864 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
865 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
866 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
867 pbXStates += cbMaxXState;
868
869 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
870 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
871 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
872 pbXStates += cbMaxXState;
873
874 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
875 }
876
877 /*
878 * Setup hypervisor startup values.
879 */
880
881 /*
882 * Register saved state data item.
883 */
884 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
885 NULL, cpumR3LiveExec, NULL,
886 NULL, cpumR3SaveExec, NULL,
887 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
888 if (RT_FAILURE(rc))
889 return rc;
890
891 /*
892 * Register info handlers and registers with the debugger facility.
893 */
894 DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
895 DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
896 DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
897 DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
898 DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
899 DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
900
901 rc = cpumR3DbgInit(pVM);
902 if (RT_FAILURE(rc))
903 return rc;
904
905 /*
906 * Check if we need to workaround partial/leaky FPU handling.
907 */
908 cpumR3CheckLeakyFpu(pVM);
909
910 /*
911 * Initialize the Guest CPUID and MSR states.
912 */
913 rc = cpumR3InitCpuIdAndMsrs(pVM);
914 if (RT_FAILURE(rc))
915 return rc;
916 CPUMR3Reset(pVM);
917 return VINF_SUCCESS;
918}
919
920
921/**
922 * Applies relocations to data and code managed by this
923 * component. This function will be called at init and
924 * whenever the VMM need to relocate it self inside the GC.
925 *
926 * The CPUM will update the addresses used by the switcher.
927 *
928 * @param pVM The cross context VM structure.
929 */
930VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
931{
932 LogFlow(("CPUMR3Relocate\n"));
933
934 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
935 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
936
937 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
938 {
939 PVMCPU pVCpu = &pVM->aCpus[iCpu];
940 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
941 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
942 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
943
944 /* Recheck the guest DRx values in raw-mode. */
945 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
946 }
947}
948
949
950/**
951 * Apply late CPUM property changes based on the fHWVirtEx setting
952 *
953 * @param pVM The cross context VM structure.
954 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
955 */
956VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
957{
958 /*
959 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
960 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
961 * of processors from (cpuid(4).eax >> 26) + 1.
962 *
963 * Note: this code is obsolete, but let's keep it here for reference.
964 * Purpose is valid when we artificially cap the max std id to less than 4.
965 */
966 if (!fHWVirtExEnabled)
967 {
968 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
969 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
970 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
971 }
972}
973
974/**
975 * Terminates the CPUM.
976 *
977 * Termination means cleaning up and freeing all resources,
978 * the VM it self is at this point powered off or suspended.
979 *
980 * @returns VBox status code.
981 * @param pVM The cross context VM structure.
982 */
983VMMR3DECL(int) CPUMR3Term(PVM pVM)
984{
985#ifdef VBOX_WITH_CRASHDUMP_MAGIC
986 for (VMCPUID i = 0; i < pVM->cCpus; i++)
987 {
988 PVMCPU pVCpu = &pVM->aCpus[i];
989 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
990
991 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
992 pVCpu->cpum.s.uMagic = 0;
993 pCtx->dr[5] = 0;
994 }
995#else
996 NOREF(pVM);
997#endif
998 return VINF_SUCCESS;
999}
1000
1001
1002/**
1003 * Resets a virtual CPU.
1004 *
1005 * Used by CPUMR3Reset and CPU hot plugging.
1006 *
1007 * @param pVM The cross context VM structure.
1008 * @param pVCpu The cross context virtual CPU structure of the CPU that is
1009 * being reset. This may differ from the current EMT.
1010 */
1011VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1012{
1013 /** @todo anything different for VCPU > 0? */
1014 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1015
1016 /*
1017 * Initialize everything to ZERO first.
1018 */
1019 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1020
1021 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1022 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1023 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1024
1025 pVCpu->cpum.s.fUseFlags = fUseFlags;
1026
1027 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1028 pCtx->eip = 0x0000fff0;
1029 pCtx->edx = 0x00000600; /* P6 processor */
1030 pCtx->eflags.Bits.u1Reserved0 = 1;
1031
1032 pCtx->cs.Sel = 0xf000;
1033 pCtx->cs.ValidSel = 0xf000;
1034 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1035 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1036 pCtx->cs.u32Limit = 0x0000ffff;
1037 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1038 pCtx->cs.Attr.n.u1Present = 1;
1039 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1040
1041 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1042 pCtx->ds.u32Limit = 0x0000ffff;
1043 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1044 pCtx->ds.Attr.n.u1Present = 1;
1045 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1046
1047 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1048 pCtx->es.u32Limit = 0x0000ffff;
1049 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1050 pCtx->es.Attr.n.u1Present = 1;
1051 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1052
1053 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1054 pCtx->fs.u32Limit = 0x0000ffff;
1055 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1056 pCtx->fs.Attr.n.u1Present = 1;
1057 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1058
1059 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1060 pCtx->gs.u32Limit = 0x0000ffff;
1061 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1062 pCtx->gs.Attr.n.u1Present = 1;
1063 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1064
1065 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1066 pCtx->ss.u32Limit = 0x0000ffff;
1067 pCtx->ss.Attr.n.u1Present = 1;
1068 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1069 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1070
1071 pCtx->idtr.cbIdt = 0xffff;
1072 pCtx->gdtr.cbGdt = 0xffff;
1073
1074 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1075 pCtx->ldtr.u32Limit = 0xffff;
1076 pCtx->ldtr.Attr.n.u1Present = 1;
1077 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1078
1079 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1080 pCtx->tr.u32Limit = 0xffff;
1081 pCtx->tr.Attr.n.u1Present = 1;
1082 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1083
1084 pCtx->dr[6] = X86_DR6_INIT_VAL;
1085 pCtx->dr[7] = X86_DR7_INIT_VAL;
1086
1087 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1088 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1089 pFpuCtx->FCW = 0x37f;
1090
1091 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1092 IA-32 Processor States Following Power-up, Reset, or INIT */
1093 pFpuCtx->MXCSR = 0x1F80;
1094 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1095 supports all bits, since a zero value here should be read as 0xffbf. */
1096 pCtx->aXcr[0] = XSAVE_C_X87;
1097 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1098 {
1099 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1100 as we don't know what happened before. (Bother optimize later?) */
1101 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1102 }
1103
1104 /*
1105 * MSRs.
1106 */
1107 /* Init PAT MSR */
1108 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1109
1110 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1111 * The Intel docs don't mention it. */
1112 Assert(!pCtx->msrEFER);
1113
1114 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1115 is supposed to be here, just trying provide useful/sensible values. */
1116 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1117 if (pRange)
1118 {
1119 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1120 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1121 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1122 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1123 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1124 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1125 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1126 }
1127
1128 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1129
1130 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1131 * called from each EMT while we're getting called by CPUMR3Reset()
1132 * iteratively on the same thread. Fix later. */
1133#if 0 /** @todo r=bird: This we will do in TM, not here. */
1134 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1135 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1136#endif
1137
1138
1139 /* C-state control. Guesses. */
1140 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1141
1142
1143 /*
1144 * Get the APIC base MSR from the APIC device. For historical reasons (saved state), the APIC base
1145 * continues to reside in the APIC device and we cache it here in the VCPU for all further accesses.
1146 */
1147 PDMApicGetBaseMsr(pVCpu, &pCtx->msrApicBase, true /* fIgnoreErrors */);
1148#ifdef VBOX_WITH_NEW_APIC
1149 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", pVCpu->idCpu, pVCpu->cpum.s.Guest.msrApicBase));
1150#endif
1151}
1152
1153
1154/**
1155 * Resets the CPU.
1156 *
1157 * @returns VINF_SUCCESS.
1158 * @param pVM The cross context VM structure.
1159 */
1160VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1161{
1162 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1163 {
1164 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1165
1166#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1167 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1168
1169 /* Magic marker for searching in crash dumps. */
1170 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1171 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1172 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1173#endif
1174 }
1175}
1176
1177
1178
1179
1180/**
1181 * Pass 0 live exec callback.
1182 *
1183 * @returns VINF_SSM_DONT_CALL_AGAIN.
1184 * @param pVM The cross context VM structure.
1185 * @param pSSM The saved state handle.
1186 * @param uPass The pass (0).
1187 */
1188static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1189{
1190 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1191 cpumR3SaveCpuId(pVM, pSSM);
1192 return VINF_SSM_DONT_CALL_AGAIN;
1193}
1194
1195
1196/**
1197 * Execute state save operation.
1198 *
1199 * @returns VBox status code.
1200 * @param pVM The cross context VM structure.
1201 * @param pSSM SSM operation handle.
1202 */
1203static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1204{
1205 /*
1206 * Save.
1207 */
1208 SSMR3PutU32(pSSM, pVM->cCpus);
1209 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1210 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1211 {
1212 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1213
1214 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1215
1216 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1217 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1218 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1219 if (pGstCtx->fXStateMask != 0)
1220 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1221 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1222 {
1223 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1224 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1225 }
1226 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1227 {
1228 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1229 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1230 }
1231 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1232 {
1233 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1234 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1235 }
1236 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1237 {
1238 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1239 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1240 }
1241 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1242 {
1243 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1244 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1245 }
1246
1247 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1248 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1249 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1250 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1251 }
1252
1253 cpumR3SaveCpuId(pVM, pSSM);
1254 return VINF_SUCCESS;
1255}
1256
1257
1258/**
1259 * @callback_method_impl{FNSSMINTLOADPREP}
1260 */
1261static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1262{
1263 NOREF(pSSM);
1264 pVM->cpum.s.fPendingRestore = true;
1265 return VINF_SUCCESS;
1266}
1267
1268
1269/**
1270 * @callback_method_impl{FNSSMINTLOADEXEC}
1271 */
1272static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1273{
1274 int rc; /* Only for AssertRCReturn use. */
1275
1276 /*
1277 * Validate version.
1278 */
1279 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1280 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1281 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1282 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1283 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1284 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1285 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1286 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1287 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1288 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1289 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1290 {
1291 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1292 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1293 }
1294
1295 if (uPass == SSM_PASS_FINAL)
1296 {
1297 /*
1298 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1299 * really old SSM file versions.)
1300 */
1301 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1302 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1303 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1304 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1305
1306 /*
1307 * Figure x86 and ctx field definitions to use for older states.
1308 */
1309 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1310 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1311 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1312 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1313 {
1314 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1315 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1316 }
1317 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1318 {
1319 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1320 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1321 }
1322
1323 /*
1324 * The hyper state used to preceed the CPU count. Starting with
1325 * XSAVE it was moved down till after we've got the count.
1326 */
1327 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1328 {
1329 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1330 {
1331 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1332 X86FXSTATE Ign;
1333 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1334 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1335 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1336 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1337 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1338 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1339 pVCpu->cpum.s.Hyper.rsp = uRSP;
1340 }
1341 }
1342
1343 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1344 {
1345 uint32_t cCpus;
1346 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1347 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1348 VERR_SSM_UNEXPECTED_DATA);
1349 }
1350 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1351 || pVM->cCpus == 1,
1352 ("cCpus=%u\n", pVM->cCpus),
1353 VERR_SSM_UNEXPECTED_DATA);
1354
1355 uint32_t cbMsrs = 0;
1356 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1357 {
1358 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1359 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1360 VERR_SSM_UNEXPECTED_DATA);
1361 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1362 VERR_SSM_UNEXPECTED_DATA);
1363 }
1364
1365 /*
1366 * Do the per-CPU restoring.
1367 */
1368 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1369 {
1370 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1371 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1372
1373 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1374 {
1375 /*
1376 * The XSAVE saved state layout moved the hyper state down here.
1377 */
1378 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1379 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1380 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1381 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1382 pVCpu->cpum.s.Hyper.rsp = uRSP;
1383 AssertRCReturn(rc, rc);
1384
1385 /*
1386 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1387 */
1388 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1389 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1390 AssertRCReturn(rc, rc);
1391
1392 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1393 if (pGstCtx->fXStateMask != 0)
1394 {
1395 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1396 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1397 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1398 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1399 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1400 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1401 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1402 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1403 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1404 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1405 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1406 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1407 }
1408
1409 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1410 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1411 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1412 {
1413 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1414 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1415 VERR_CPUM_INVALID_XCR0);
1416 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1417 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1418 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1419 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1420 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1421 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1422 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1423 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1424 }
1425
1426 /* Check that the XCR1 is zero, as we don't implement it yet. */
1427 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1428
1429 /*
1430 * Restore the individual extended state components we support.
1431 */
1432 if (pGstCtx->fXStateMask != 0)
1433 {
1434 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1435 0, g_aCpumXSaveHdrFields, NULL);
1436 AssertRCReturn(rc, rc);
1437 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1438 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1439 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1440 VERR_CPUM_INVALID_XSAVE_HDR);
1441 }
1442 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1443 {
1444 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1445 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1446 }
1447 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1448 {
1449 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1450 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1451 }
1452 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1453 {
1454 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1455 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1456 }
1457 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1458 {
1459 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1460 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1461 }
1462 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1463 {
1464 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1465 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1466 }
1467 }
1468 else
1469 {
1470 /*
1471 * Pre XSAVE saved state.
1472 */
1473 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1474 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1475 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1476 }
1477
1478 /*
1479 * Restore a couple of flags and the MSRs.
1480 */
1481 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1482 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1483
1484 rc = VINF_SUCCESS;
1485 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1486 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1487 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1488 {
1489 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1490 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1491 }
1492 AssertRCReturn(rc, rc);
1493
1494 /* REM and other may have cleared must-be-one fields in DR6 and
1495 DR7, fix these. */
1496 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1497 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1498 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1499 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1500 }
1501
1502 /* Older states does not have the internal selector register flags
1503 and valid selector value. Supply those. */
1504 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1505 {
1506 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1507 {
1508 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1509 bool const fValid = HMIsEnabled(pVM)
1510 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1511 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1512 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1513 if (fValid)
1514 {
1515 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1516 {
1517 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1518 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1519 }
1520
1521 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1522 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1523 }
1524 else
1525 {
1526 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1527 {
1528 paSelReg[iSelReg].fFlags = 0;
1529 paSelReg[iSelReg].ValidSel = 0;
1530 }
1531
1532 /* This might not be 104% correct, but I think it's close
1533 enough for all practical purposes... (REM always loaded
1534 LDTR registers.) */
1535 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1536 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1537 }
1538 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1539 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1540 }
1541 }
1542
1543 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1544 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1545 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1546 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1547 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1548
1549 /*
1550 * A quick sanity check.
1551 */
1552 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1553 {
1554 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1555 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1556 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1557 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1558 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1559 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1560 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1561 }
1562 }
1563
1564 pVM->cpum.s.fPendingRestore = false;
1565
1566 /*
1567 * Guest CPUIDs.
1568 */
1569 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1570 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1571 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1572}
1573
1574
1575/**
1576 * @callback_method_impl{FNSSMINTLOADDONE}
1577 */
1578static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1579{
1580 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1581 return VINF_SUCCESS;
1582
1583 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1584 if (pVM->cpum.s.fPendingRestore)
1585 {
1586 LogRel(("CPUM: Missing state!\n"));
1587 return VERR_INTERNAL_ERROR_2;
1588 }
1589
1590 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1591 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1592 {
1593 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1594
1595 /* Notify PGM of the NXE states in case they've changed. */
1596 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1597
1598 /* Cache the local APIC base from the APIC device. During init. this is done in CPUMR3ResetCpu(). */
1599 PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
1600#ifdef VBOX_WITH_NEW_APIC
1601 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", idCpu, pVCpu->cpum.s.Guest.msrApicBase));
1602#endif
1603
1604 /* During init. this is done in CPUMR3InitCompleted(). */
1605 if (fSupportsLongMode)
1606 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1607 }
1608 return VINF_SUCCESS;
1609}
1610
1611
1612/**
1613 * Checks if the CPUM state restore is still pending.
1614 *
1615 * @returns true / false.
1616 * @param pVM The cross context VM structure.
1617 */
1618VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1619{
1620 return pVM->cpum.s.fPendingRestore;
1621}
1622
1623
1624/**
1625 * Formats the EFLAGS value into mnemonics.
1626 *
1627 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1628 * @param efl The EFLAGS value.
1629 */
1630static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1631{
1632 /*
1633 * Format the flags.
1634 */
1635 static const struct
1636 {
1637 const char *pszSet; const char *pszClear; uint32_t fFlag;
1638 } s_aFlags[] =
1639 {
1640 { "vip",NULL, X86_EFL_VIP },
1641 { "vif",NULL, X86_EFL_VIF },
1642 { "ac", NULL, X86_EFL_AC },
1643 { "vm", NULL, X86_EFL_VM },
1644 { "rf", NULL, X86_EFL_RF },
1645 { "nt", NULL, X86_EFL_NT },
1646 { "ov", "nv", X86_EFL_OF },
1647 { "dn", "up", X86_EFL_DF },
1648 { "ei", "di", X86_EFL_IF },
1649 { "tf", NULL, X86_EFL_TF },
1650 { "nt", "pl", X86_EFL_SF },
1651 { "nz", "zr", X86_EFL_ZF },
1652 { "ac", "na", X86_EFL_AF },
1653 { "po", "pe", X86_EFL_PF },
1654 { "cy", "nc", X86_EFL_CF },
1655 };
1656 char *psz = pszEFlags;
1657 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1658 {
1659 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1660 if (pszAdd)
1661 {
1662 strcpy(psz, pszAdd);
1663 psz += strlen(pszAdd);
1664 *psz++ = ' ';
1665 }
1666 }
1667 psz[-1] = '\0';
1668}
1669
1670
1671/**
1672 * Formats a full register dump.
1673 *
1674 * @param pVM The cross context VM structure.
1675 * @param pCtx The context to format.
1676 * @param pCtxCore The context core to format.
1677 * @param pHlp Output functions.
1678 * @param enmType The dump type.
1679 * @param pszPrefix Register name prefix.
1680 */
1681static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1682 const char *pszPrefix)
1683{
1684 NOREF(pVM);
1685
1686 /*
1687 * Format the EFLAGS.
1688 */
1689 uint32_t efl = pCtxCore->eflags.u32;
1690 char szEFlags[80];
1691 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1692
1693 /*
1694 * Format the registers.
1695 */
1696 switch (enmType)
1697 {
1698 case CPUMDUMPTYPE_TERSE:
1699 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1700 pHlp->pfnPrintf(pHlp,
1701 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1702 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1703 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1704 "%sr14=%016RX64 %sr15=%016RX64\n"
1705 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1706 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1707 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1708 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1709 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1710 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1711 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1712 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1713 else
1714 pHlp->pfnPrintf(pHlp,
1715 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1716 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1717 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1718 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1719 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1720 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1721 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1722 break;
1723
1724 case CPUMDUMPTYPE_DEFAULT:
1725 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1726 pHlp->pfnPrintf(pHlp,
1727 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1728 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1729 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1730 "%sr14=%016RX64 %sr15=%016RX64\n"
1731 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1732 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1733 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1734 ,
1735 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1736 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1737 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1738 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1739 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1740 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1741 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1742 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1743 else
1744 pHlp->pfnPrintf(pHlp,
1745 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1746 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1747 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1748 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1749 ,
1750 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1751 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1752 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1753 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1754 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1755 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1756 break;
1757
1758 case CPUMDUMPTYPE_VERBOSE:
1759 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1760 pHlp->pfnPrintf(pHlp,
1761 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1762 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1763 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1764 "%sr14=%016RX64 %sr15=%016RX64\n"
1765 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1766 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1767 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1768 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1769 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1770 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1771 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1772 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1773 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1774 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1775 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1776 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1777 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1778 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1779 ,
1780 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1781 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1782 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1783 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1784 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1785 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1786 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1787 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1788 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1789 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1790 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1791 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1792 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1793 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1794 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1795 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1796 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1797 else
1798 pHlp->pfnPrintf(pHlp,
1799 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1800 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1801 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1802 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1803 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1804 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1805 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1806 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1807 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1808 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1809 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1810 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1811 ,
1812 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1813 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1814 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1815 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1816 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1817 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1818 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1819 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1820 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1821 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1822 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1823 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1824
1825 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1826 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1827 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1828 if (pCtx->CTX_SUFF(pXState))
1829 {
1830 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1831 pHlp->pfnPrintf(pHlp,
1832 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1833 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1834 ,
1835 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1836 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1837 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1838 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1839 );
1840 /*
1841 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1842 * not (FP)R0-7 as Intel SDM suggests.
1843 */
1844 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1845 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1846 {
1847 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1848 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1849 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1850 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1851 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1852 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1853 iExponent -= 16383; /* subtract bias */
1854 /** @todo This isn't entirenly correct and needs more work! */
1855 pHlp->pfnPrintf(pHlp,
1856 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1857 pszPrefix, iST, pszPrefix, iFPR,
1858 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1859 uTag, chSign, iInteger, u64Fraction, iExponent);
1860 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
1861 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1862 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1863 else
1864 pHlp->pfnPrintf(pHlp, "\n");
1865 }
1866
1867 /* XMM/YMM/ZMM registers. */
1868 if (pCtx->fXStateMask & XSAVE_C_YMM)
1869 {
1870 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1871 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1872 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1873 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1874 pszPrefix, i, i < 10 ? " " : "",
1875 pYmmHiCtx->aYmmHi[i].au32[3],
1876 pYmmHiCtx->aYmmHi[i].au32[2],
1877 pYmmHiCtx->aYmmHi[i].au32[1],
1878 pYmmHiCtx->aYmmHi[i].au32[0],
1879 pFpuCtx->aXMM[i].au32[3],
1880 pFpuCtx->aXMM[i].au32[2],
1881 pFpuCtx->aXMM[i].au32[1],
1882 pFpuCtx->aXMM[i].au32[0]);
1883 else
1884 {
1885 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1886 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1887 pHlp->pfnPrintf(pHlp,
1888 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1889 pszPrefix, i, i < 10 ? " " : "",
1890 pZmmHi256->aHi256Regs[i].au32[7],
1891 pZmmHi256->aHi256Regs[i].au32[6],
1892 pZmmHi256->aHi256Regs[i].au32[5],
1893 pZmmHi256->aHi256Regs[i].au32[4],
1894 pZmmHi256->aHi256Regs[i].au32[3],
1895 pZmmHi256->aHi256Regs[i].au32[2],
1896 pZmmHi256->aHi256Regs[i].au32[1],
1897 pZmmHi256->aHi256Regs[i].au32[0],
1898 pYmmHiCtx->aYmmHi[i].au32[3],
1899 pYmmHiCtx->aYmmHi[i].au32[2],
1900 pYmmHiCtx->aYmmHi[i].au32[1],
1901 pYmmHiCtx->aYmmHi[i].au32[0],
1902 pFpuCtx->aXMM[i].au32[3],
1903 pFpuCtx->aXMM[i].au32[2],
1904 pFpuCtx->aXMM[i].au32[1],
1905 pFpuCtx->aXMM[i].au32[0]);
1906
1907 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1908 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
1909 pHlp->pfnPrintf(pHlp,
1910 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1911 pszPrefix, i + 16,
1912 pZmm16Hi->aRegs[i].au32[15],
1913 pZmm16Hi->aRegs[i].au32[14],
1914 pZmm16Hi->aRegs[i].au32[13],
1915 pZmm16Hi->aRegs[i].au32[12],
1916 pZmm16Hi->aRegs[i].au32[11],
1917 pZmm16Hi->aRegs[i].au32[10],
1918 pZmm16Hi->aRegs[i].au32[9],
1919 pZmm16Hi->aRegs[i].au32[8],
1920 pZmm16Hi->aRegs[i].au32[7],
1921 pZmm16Hi->aRegs[i].au32[6],
1922 pZmm16Hi->aRegs[i].au32[5],
1923 pZmm16Hi->aRegs[i].au32[4],
1924 pZmm16Hi->aRegs[i].au32[3],
1925 pZmm16Hi->aRegs[i].au32[2],
1926 pZmm16Hi->aRegs[i].au32[1],
1927 pZmm16Hi->aRegs[i].au32[0]);
1928 }
1929 }
1930 else
1931 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1932 pHlp->pfnPrintf(pHlp,
1933 i & 1
1934 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1935 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1936 pszPrefix, i, i < 10 ? " " : "",
1937 pFpuCtx->aXMM[i].au32[3],
1938 pFpuCtx->aXMM[i].au32[2],
1939 pFpuCtx->aXMM[i].au32[1],
1940 pFpuCtx->aXMM[i].au32[0]);
1941
1942 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
1943 {
1944 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
1945 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
1946 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
1947 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
1948 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
1949 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
1950 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
1951 }
1952
1953 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
1954 {
1955 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1956 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
1957 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
1958 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
1959 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
1960 }
1961
1962 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
1963 {
1964 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1965 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
1966 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
1967 }
1968
1969 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1970 if (pFpuCtx->au32RsrvdRest[i])
1971 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
1972 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1973 }
1974
1975 pHlp->pfnPrintf(pHlp,
1976 "%sEFER =%016RX64\n"
1977 "%sPAT =%016RX64\n"
1978 "%sSTAR =%016RX64\n"
1979 "%sCSTAR =%016RX64\n"
1980 "%sLSTAR =%016RX64\n"
1981 "%sSFMASK =%016RX64\n"
1982 "%sKERNELGSBASE =%016RX64\n",
1983 pszPrefix, pCtx->msrEFER,
1984 pszPrefix, pCtx->msrPAT,
1985 pszPrefix, pCtx->msrSTAR,
1986 pszPrefix, pCtx->msrCSTAR,
1987 pszPrefix, pCtx->msrLSTAR,
1988 pszPrefix, pCtx->msrSFMASK,
1989 pszPrefix, pCtx->msrKERNELGSBASE);
1990 break;
1991 }
1992}
1993
1994
1995/**
1996 * Display all cpu states and any other cpum info.
1997 *
1998 * @param pVM The cross context VM structure.
1999 * @param pHlp The info helper functions.
2000 * @param pszArgs Arguments, ignored.
2001 */
2002static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2003{
2004 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2005 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2006 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2007 cpumR3InfoHost(pVM, pHlp, pszArgs);
2008}
2009
2010
2011/**
2012 * Parses the info argument.
2013 *
2014 * The argument starts with 'verbose', 'terse' or 'default' and then
2015 * continues with the comment string.
2016 *
2017 * @param pszArgs The pointer to the argument string.
2018 * @param penmType Where to store the dump type request.
2019 * @param ppszComment Where to store the pointer to the comment string.
2020 */
2021static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
2022{
2023 if (!pszArgs)
2024 {
2025 *penmType = CPUMDUMPTYPE_DEFAULT;
2026 *ppszComment = "";
2027 }
2028 else
2029 {
2030 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2031 {
2032 pszArgs += 7;
2033 *penmType = CPUMDUMPTYPE_VERBOSE;
2034 }
2035 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2036 {
2037 pszArgs += 5;
2038 *penmType = CPUMDUMPTYPE_TERSE;
2039 }
2040 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2041 {
2042 pszArgs += 7;
2043 *penmType = CPUMDUMPTYPE_DEFAULT;
2044 }
2045 else
2046 *penmType = CPUMDUMPTYPE_DEFAULT;
2047 *ppszComment = RTStrStripL(pszArgs);
2048 }
2049}
2050
2051
2052/**
2053 * Display the guest cpu state.
2054 *
2055 * @param pVM The cross context VM structure.
2056 * @param pHlp The info helper functions.
2057 * @param pszArgs Arguments, ignored.
2058 */
2059static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2060{
2061 CPUMDUMPTYPE enmType;
2062 const char *pszComment;
2063 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2064
2065 /* @todo SMP support! */
2066 PVMCPU pVCpu = VMMGetCpu(pVM);
2067 if (!pVCpu)
2068 pVCpu = &pVM->aCpus[0];
2069
2070 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2071
2072 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2073 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2074}
2075
2076
2077/**
2078 * Display the current guest instruction
2079 *
2080 * @param pVM The cross context VM structure.
2081 * @param pHlp The info helper functions.
2082 * @param pszArgs Arguments, ignored.
2083 */
2084static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2085{
2086 NOREF(pszArgs);
2087
2088 /** @todo SMP support! */
2089 PVMCPU pVCpu = VMMGetCpu(pVM);
2090 if (!pVCpu)
2091 pVCpu = &pVM->aCpus[0];
2092
2093 char szInstruction[256];
2094 szInstruction[0] = '\0';
2095 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2096 pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
2097}
2098
2099
2100/**
2101 * Display the hypervisor cpu state.
2102 *
2103 * @param pVM The cross context VM structure.
2104 * @param pHlp The info helper functions.
2105 * @param pszArgs Arguments, ignored.
2106 */
2107static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2108{
2109 CPUMDUMPTYPE enmType;
2110 const char *pszComment;
2111 /* @todo SMP */
2112 PVMCPU pVCpu = &pVM->aCpus[0];
2113
2114 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2115 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2116 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2117 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2118}
2119
2120
2121/**
2122 * Display the host cpu state.
2123 *
2124 * @param pVM The cross context VM structure.
2125 * @param pHlp The info helper functions.
2126 * @param pszArgs Arguments, ignored.
2127 */
2128static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2129{
2130 CPUMDUMPTYPE enmType;
2131 const char *pszComment;
2132 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2133 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2134
2135 /*
2136 * Format the EFLAGS.
2137 */
2138 /* @todo SMP */
2139 PCPUMHOSTCTX pCtx = &pVM->aCpus[0].cpum.s.Host;
2140#if HC_ARCH_BITS == 32
2141 uint32_t efl = pCtx->eflags.u32;
2142#else
2143 uint64_t efl = pCtx->rflags;
2144#endif
2145 char szEFlags[80];
2146 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2147
2148 /*
2149 * Format the registers.
2150 */
2151#if HC_ARCH_BITS == 32
2152 pHlp->pfnPrintf(pHlp,
2153 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2154 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2155 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2156 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2157 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2158 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2159 ,
2160 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2161 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2162 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2163 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2164 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2165 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2166 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2167#else
2168 pHlp->pfnPrintf(pHlp,
2169 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2170 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2171 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2172 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2173 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2174 "r14=%016RX64 r15=%016RX64\n"
2175 "iopl=%d %31s\n"
2176 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2177 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2178 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2179 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2180 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2181 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2182 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2183 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2184 ,
2185 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2186 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2187 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2188 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2189 pCtx->r11, pCtx->r12, pCtx->r13,
2190 pCtx->r14, pCtx->r15,
2191 X86_EFL_GET_IOPL(efl), szEFlags,
2192 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2193 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2194 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2195 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2196 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2197 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2198 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2199 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2200#endif
2201}
2202
2203/**
2204 * Structure used when disassembling and instructions in DBGF.
2205 * This is used so the reader function can get the stuff it needs.
2206 */
2207typedef struct CPUMDISASSTATE
2208{
2209 /** Pointer to the CPU structure. */
2210 PDISCPUSTATE pCpu;
2211 /** Pointer to the VM. */
2212 PVM pVM;
2213 /** Pointer to the VMCPU. */
2214 PVMCPU pVCpu;
2215 /** Pointer to the first byte in the segment. */
2216 RTGCUINTPTR GCPtrSegBase;
2217 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2218 RTGCUINTPTR GCPtrSegEnd;
2219 /** The size of the segment minus 1. */
2220 RTGCUINTPTR cbSegLimit;
2221 /** Pointer to the current page - R3 Ptr. */
2222 void const *pvPageR3;
2223 /** Pointer to the current page - GC Ptr. */
2224 RTGCPTR pvPageGC;
2225 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2226 PGMPAGEMAPLOCK PageMapLock;
2227 /** Whether the PageMapLock is valid or not. */
2228 bool fLocked;
2229 /** 64 bits mode or not. */
2230 bool f64Bits;
2231} CPUMDISASSTATE, *PCPUMDISASSTATE;
2232
2233
2234/**
2235 * @callback_method_impl{FNDISREADBYTES}
2236 */
2237static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2238{
2239 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2240 for (;;)
2241 {
2242 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2243
2244 /*
2245 * Need to update the page translation?
2246 */
2247 if ( !pState->pvPageR3
2248 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2249 {
2250 int rc = VINF_SUCCESS;
2251
2252 /* translate the address */
2253 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2254 if ( !HMIsEnabled(pState->pVM)
2255 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2256 {
2257 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2258 if (!pState->pvPageR3)
2259 rc = VERR_INVALID_POINTER;
2260 }
2261 else
2262 {
2263 /* Release mapping lock previously acquired. */
2264 if (pState->fLocked)
2265 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2266 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2267 pState->fLocked = RT_SUCCESS_NP(rc);
2268 }
2269 if (RT_FAILURE(rc))
2270 {
2271 pState->pvPageR3 = NULL;
2272 return rc;
2273 }
2274 }
2275
2276 /*
2277 * Check the segment limit.
2278 */
2279 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2280 return VERR_OUT_OF_SELECTOR_BOUNDS;
2281
2282 /*
2283 * Calc how much we can read.
2284 */
2285 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2286 if (!pState->f64Bits)
2287 {
2288 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2289 if (cb > cbSeg && cbSeg)
2290 cb = cbSeg;
2291 }
2292 if (cb > cbMaxRead)
2293 cb = cbMaxRead;
2294
2295 /*
2296 * Read and advance or exit.
2297 */
2298 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2299 offInstr += (uint8_t)cb;
2300 if (cb >= cbMinRead)
2301 {
2302 pDis->cbCachedInstr = offInstr;
2303 return VINF_SUCCESS;
2304 }
2305 cbMinRead -= (uint8_t)cb;
2306 cbMaxRead -= (uint8_t)cb;
2307 }
2308}
2309
2310
2311/**
2312 * Disassemble an instruction and return the information in the provided structure.
2313 *
2314 * @returns VBox status code.
2315 * @param pVM The cross context VM structure.
2316 * @param pVCpu The cross context virtual CPU structure.
2317 * @param pCtx Pointer to the guest CPU context.
2318 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2319 * @param pCpu Disassembly state.
2320 * @param pszPrefix String prefix for logging (debug only).
2321 *
2322 */
2323VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
2324{
2325 CPUMDISASSTATE State;
2326 int rc;
2327
2328 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2329 State.pCpu = pCpu;
2330 State.pvPageGC = 0;
2331 State.pvPageR3 = NULL;
2332 State.pVM = pVM;
2333 State.pVCpu = pVCpu;
2334 State.fLocked = false;
2335 State.f64Bits = false;
2336
2337 /*
2338 * Get selector information.
2339 */
2340 DISCPUMODE enmDisCpuMode;
2341 if ( (pCtx->cr0 & X86_CR0_PE)
2342 && pCtx->eflags.Bits.u1VM == 0)
2343 {
2344 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2345 {
2346# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2347 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2348# endif
2349 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2350 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2351 }
2352 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2353 State.GCPtrSegBase = pCtx->cs.u64Base;
2354 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2355 State.cbSegLimit = pCtx->cs.u32Limit;
2356 enmDisCpuMode = (State.f64Bits)
2357 ? DISCPUMODE_64BIT
2358 : pCtx->cs.Attr.n.u1DefBig
2359 ? DISCPUMODE_32BIT
2360 : DISCPUMODE_16BIT;
2361 }
2362 else
2363 {
2364 /* real or V86 mode */
2365 enmDisCpuMode = DISCPUMODE_16BIT;
2366 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2367 State.GCPtrSegEnd = 0xFFFFFFFF;
2368 State.cbSegLimit = 0xFFFFFFFF;
2369 }
2370
2371 /*
2372 * Disassemble the instruction.
2373 */
2374 uint32_t cbInstr;
2375#ifndef LOG_ENABLED
2376 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2377 if (RT_SUCCESS(rc))
2378 {
2379#else
2380 char szOutput[160];
2381 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2382 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2383 if (RT_SUCCESS(rc))
2384 {
2385 /* log it */
2386 if (pszPrefix)
2387 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2388 else
2389 Log(("%s", szOutput));
2390#endif
2391 rc = VINF_SUCCESS;
2392 }
2393 else
2394 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2395
2396 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2397 if (State.fLocked)
2398 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2399
2400 return rc;
2401}
2402
2403
2404
2405/**
2406 * API for controlling a few of the CPU features found in CR4.
2407 *
2408 * Currently only X86_CR4_TSD is accepted as input.
2409 *
2410 * @returns VBox status code.
2411 *
2412 * @param pVM The cross context VM structure.
2413 * @param fOr The CR4 OR mask.
2414 * @param fAnd The CR4 AND mask.
2415 */
2416VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2417{
2418 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2419 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2420
2421 pVM->cpum.s.CR4.OrMask &= fAnd;
2422 pVM->cpum.s.CR4.OrMask |= fOr;
2423
2424 return VINF_SUCCESS;
2425}
2426
2427
2428/**
2429 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2430 *
2431 * Only REM should ever call this function!
2432 *
2433 * @returns The changed flags.
2434 * @param pVCpu The cross context virtual CPU structure.
2435 * @param puCpl Where to return the current privilege level (CPL).
2436 */
2437VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2438{
2439 Assert(!pVCpu->cpum.s.fRawEntered);
2440 Assert(!pVCpu->cpum.s.fRemEntered);
2441
2442 /*
2443 * Get the CPL first.
2444 */
2445 *puCpl = CPUMGetGuestCPL(pVCpu);
2446
2447 /*
2448 * Get and reset the flags.
2449 */
2450 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2451 pVCpu->cpum.s.fChanged = 0;
2452
2453 /** @todo change the switcher to use the fChanged flags. */
2454 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2455 {
2456 fFlags |= CPUM_CHANGED_FPU_REM;
2457 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2458 }
2459
2460 pVCpu->cpum.s.fRemEntered = true;
2461 return fFlags;
2462}
2463
2464
2465/**
2466 * Leaves REM.
2467 *
2468 * @param pVCpu The cross context virtual CPU structure.
2469 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2470 * registers.
2471 */
2472VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2473{
2474 Assert(!pVCpu->cpum.s.fRawEntered);
2475 Assert(pVCpu->cpum.s.fRemEntered);
2476
2477 pVCpu->cpum.s.fRemEntered = false;
2478}
2479
2480
2481/**
2482 * Called when the ring-3 init phase completes.
2483 *
2484 * @returns VBox status code.
2485 * @param pVM The cross context VM structure.
2486 * @param enmWhat Which init phase.
2487 */
2488VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2489{
2490 switch (enmWhat)
2491 {
2492 case VMINITCOMPLETED_RING3:
2493 {
2494 /*
2495 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2496 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2497 */
2498 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2499 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2500 {
2501 PVMCPU pVCpu = &pVM->aCpus[i];
2502 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2503 if (fSupportsLongMode)
2504 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2505 }
2506
2507 cpumR3MsrRegStats(pVM);
2508 break;
2509 }
2510
2511 case VMINITCOMPLETED_RING0:
2512 {
2513 /* Cache the APIC base (from the APIC device) once it has been initialized. */
2514 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2515 {
2516 PVMCPU pVCpu = &pVM->aCpus[i];
2517 PDMApicGetBaseMsr(pVCpu, &pVCpu->cpum.s.Guest.msrApicBase, true /* fIgnoreErrors */);
2518#ifdef VBOX_WITH_NEW_APIC
2519 LogRel(("CPUM: VCPU%3d: Cached APIC base MSR = %#RX64\n", i, pVCpu->cpum.s.Guest.msrApicBase));
2520#endif
2521 }
2522 break;
2523 }
2524
2525 default:
2526 break;
2527 }
2528 return VINF_SUCCESS;
2529}
2530
2531
2532/**
2533 * Called when the ring-0 init phases completed.
2534 *
2535 * @param pVM The cross context VM structure.
2536 */
2537VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2538{
2539 /*
2540 * Log the cpuid.
2541 */
2542 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2543 RTCPUSET OnlineSet;
2544 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2545 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2546 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2547 RTCPUID cCores = RTMpGetCoreCount();
2548 if (cCores)
2549 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2550 LogRel(("************************* CPUID dump ************************\n"));
2551 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2552 LogRel(("\n"));
2553 DBGFR3_INFO_LOG(pVM, "cpuid", "verbose"); /* macro */
2554 RTLogRelSetBuffering(fOldBuffered);
2555 LogRel(("******************** End of CPUID dump **********************\n"));
2556}
2557
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