VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 65299

Last change on this file since 65299 was 64663, checked in by vboxsync, 8 years ago

VMM/APIC: Get rid of msrApicBase cache from CPUMCTX, make APIC work with configured as mode disabled as well.
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1/* $Id: CPUM.cpp 64663 2016-11-14 15:46:35Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 *
33 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34 *
35 * TODO: proper write up, currently just some notes.
36 *
37 * The ring-0 FPU handling per OS:
38 *
39 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
40 * convention (Visual C++ doesn't seem to have a way to disable
41 * generating such code either), so CR0.TS/EM are always zero from what I
42 * can tell. We are also forced to always load/save the guest XMM0-XMM15
43 * registers when entering/leaving guest context. Interrupt handlers
44 * using FPU/SSE will offically have call save and restore functions
45 * exported by the kernel, if the really really have to use the state.
46 *
47 * - 32-bit windows does lazy FPU handling, I think, probably including
48 * lazying saving. The Windows Internals book states that it's a bad
49 * idea to use the FPU in kernel space. However, it looks like it will
50 * restore the FPU state of the current thread in case of a kernel \#NM.
51 * Interrupt handlers should be same as for 64-bit.
52 *
53 * - Darwin allows taking \#NM in kernel space, restoring current thread's
54 * state if I read the code correctly. It saves the FPU state of the
55 * outgoing thread, and uses CR0.TS to lazily load the state of the
56 * incoming one. No idea yet how the FPU is treated by interrupt
57 * handlers, i.e. whether they are allowed to disable the state or
58 * something.
59 *
60 * - Linux also allows \#NM in kernel space (don't know since when), and
61 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62 * loads the incoming unless configured to agressivly load it. Interrupt
63 * handlers can ask whether they're allowed to use the FPU, and may
64 * freely trash the state if Linux thinks it has saved the thread's state
65 * already. This is a problem.
66 *
67 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68 * context. When switching threads, the kernel will save the state of
69 * the outgoing thread and lazy load the incoming one using CR0.TS.
70 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
71 * to do stuff, HAT are among the users. The routines there will
72 * manually clear CR0.TS and save the XMM registers they use only if
73 * CR0.TS was zero upon entry. They will skip it when not, because as
74 * mentioned above, the FPU state is saved when switching away from a
75 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76 * preserve. This is a problem if we restore CR0.TS to 1 after loading
77 * the guest state.
78 *
79 * - FreeBSD - no idea yet.
80 *
81 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83 * FPU states.
84 *
85 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86 * saving and restoring the host and guest states. The motivation for this
87 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88 *
89 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90 * state and only restore it once we've restore the host FPU state. This has the
91 * accidental side effect of triggering Solaris to preserve XMM registers in
92 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94 *
95 *
96 * @section sec_cpum_logging Logging Level Assignments.
97 *
98 * Following log level assignments:
99 * - Log6 is used for FPU state management.
100 * - Log7 is used for FPU state actualization.
101 *
102 */
103
104
105/*********************************************************************************************************************************
106* Header Files *
107*********************************************************************************************************************************/
108#define LOG_GROUP LOG_GROUP_CPUM
109#include <VBox/vmm/cpum.h>
110#include <VBox/vmm/cpumdis.h>
111#include <VBox/vmm/cpumctx-v1_6.h>
112#include <VBox/vmm/pgm.h>
113#include <VBox/vmm/apic.h>
114#include <VBox/vmm/mm.h>
115#include <VBox/vmm/em.h>
116#include <VBox/vmm/selm.h>
117#include <VBox/vmm/dbgf.h>
118#include <VBox/vmm/patm.h>
119#include <VBox/vmm/hm.h>
120#include <VBox/vmm/ssm.h>
121#include "CPUMInternal.h"
122#include <VBox/vmm/vm.h>
123
124#include <VBox/param.h>
125#include <VBox/dis.h>
126#include <VBox/err.h>
127#include <VBox/log.h>
128#include <iprt/asm-amd64-x86.h>
129#include <iprt/assert.h>
130#include <iprt/cpuset.h>
131#include <iprt/mem.h>
132#include <iprt/mp.h>
133#include <iprt/string.h>
134
135
136/*********************************************************************************************************************************
137* Defined Constants And Macros *
138*********************************************************************************************************************************/
139/**
140 * This was used in the saved state up to the early life of version 14.
141 *
142 * It indicates that we may have some out-of-sync hidden segement registers.
143 * It is only relevant for raw-mode.
144 */
145#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
146
147
148/*********************************************************************************************************************************
149* Structures and Typedefs *
150*********************************************************************************************************************************/
151
152/**
153 * What kind of cpu info dump to perform.
154 */
155typedef enum CPUMDUMPTYPE
156{
157 CPUMDUMPTYPE_TERSE,
158 CPUMDUMPTYPE_DEFAULT,
159 CPUMDUMPTYPE_VERBOSE
160} CPUMDUMPTYPE;
161/** Pointer to a cpu info dump type. */
162typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
163
164
165/*********************************************************************************************************************************
166* Internal Functions *
167*********************************************************************************************************************************/
168static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
169static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
171static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
172static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
173static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178
179
180/*********************************************************************************************************************************
181* Global Variables *
182*********************************************************************************************************************************/
183/** Saved state field descriptors for CPUMCTX. */
184static const SSMFIELD g_aCpumCtxFields[] =
185{
186 SSMFIELD_ENTRY( CPUMCTX, rdi),
187 SSMFIELD_ENTRY( CPUMCTX, rsi),
188 SSMFIELD_ENTRY( CPUMCTX, rbp),
189 SSMFIELD_ENTRY( CPUMCTX, rax),
190 SSMFIELD_ENTRY( CPUMCTX, rbx),
191 SSMFIELD_ENTRY( CPUMCTX, rdx),
192 SSMFIELD_ENTRY( CPUMCTX, rcx),
193 SSMFIELD_ENTRY( CPUMCTX, rsp),
194 SSMFIELD_ENTRY( CPUMCTX, rflags),
195 SSMFIELD_ENTRY( CPUMCTX, rip),
196 SSMFIELD_ENTRY( CPUMCTX, r8),
197 SSMFIELD_ENTRY( CPUMCTX, r9),
198 SSMFIELD_ENTRY( CPUMCTX, r10),
199 SSMFIELD_ENTRY( CPUMCTX, r11),
200 SSMFIELD_ENTRY( CPUMCTX, r12),
201 SSMFIELD_ENTRY( CPUMCTX, r13),
202 SSMFIELD_ENTRY( CPUMCTX, r14),
203 SSMFIELD_ENTRY( CPUMCTX, r15),
204 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
229 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
230 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
231 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
232 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
233 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
234 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
235 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
236 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
237 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
238 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
239 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
240 SSMFIELD_ENTRY( CPUMCTX, cr0),
241 SSMFIELD_ENTRY( CPUMCTX, cr2),
242 SSMFIELD_ENTRY( CPUMCTX, cr3),
243 SSMFIELD_ENTRY( CPUMCTX, cr4),
244 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
245 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
246 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
247 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
248 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
249 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
250 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
251 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
252 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
253 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
254 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
255 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
256 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
257 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
258 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
259 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
260 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
261 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
262 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
263 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
264 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
265 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
266 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
267 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
268 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
269 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
270 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
271 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
272 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
273 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
274 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
275 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
276 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
277 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
278 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
279 SSMFIELD_ENTRY_TERM()
280};
281
282/** Saved state field descriptors for CPUMCTX. */
283static const SSMFIELD g_aCpumX87Fields[] =
284{
285 SSMFIELD_ENTRY( X86FXSTATE, FCW),
286 SSMFIELD_ENTRY( X86FXSTATE, FSW),
287 SSMFIELD_ENTRY( X86FXSTATE, FTW),
288 SSMFIELD_ENTRY( X86FXSTATE, FOP),
289 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
290 SSMFIELD_ENTRY( X86FXSTATE, CS),
291 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
292 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
293 SSMFIELD_ENTRY( X86FXSTATE, DS),
294 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
295 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
296 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
297 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
298 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
299 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
300 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
301 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
302 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
303 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
304 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
305 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
306 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
307 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
308 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
309 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
310 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
311 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
312 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
313 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
314 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
315 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
316 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
317 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
318 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
319 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
320 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
321 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
322 SSMFIELD_ENTRY_TERM()
323};
324
325/** Saved state field descriptors for X86XSAVEHDR. */
326static const SSMFIELD g_aCpumXSaveHdrFields[] =
327{
328 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
329 SSMFIELD_ENTRY_TERM()
330};
331
332/** Saved state field descriptors for X86XSAVEYMMHI. */
333static const SSMFIELD g_aCpumYmmHiFields[] =
334{
335 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
336 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
337 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
338 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
339 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
340 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
341 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
342 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
343 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
344 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
345 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
346 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
347 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
348 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
349 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
350 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
351 SSMFIELD_ENTRY_TERM()
352};
353
354/** Saved state field descriptors for X86XSAVEBNDREGS. */
355static const SSMFIELD g_aCpumBndRegsFields[] =
356{
357 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
358 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
359 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
360 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
361 SSMFIELD_ENTRY_TERM()
362};
363
364/** Saved state field descriptors for X86XSAVEBNDCFG. */
365static const SSMFIELD g_aCpumBndCfgFields[] =
366{
367 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
368 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
369 SSMFIELD_ENTRY_TERM()
370};
371
372#if 0 /** @todo */
373/** Saved state field descriptors for X86XSAVEOPMASK. */
374static const SSMFIELD g_aCpumOpmaskFields[] =
375{
376 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
377 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
378 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
379 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
380 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
381 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
382 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
383 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
384 SSMFIELD_ENTRY_TERM()
385};
386#endif
387
388/** Saved state field descriptors for X86XSAVEZMMHI256. */
389static const SSMFIELD g_aCpumZmmHi256Fields[] =
390{
391 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
392 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
393 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
394 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
395 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
396 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
397 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
398 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
399 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
400 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
401 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
402 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
403 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
404 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
405 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
406 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
407 SSMFIELD_ENTRY_TERM()
408};
409
410/** Saved state field descriptors for X86XSAVEZMM16HI. */
411static const SSMFIELD g_aCpumZmm16HiFields[] =
412{
413 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
414 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
415 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
416 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
417 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
418 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
419 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
420 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
421 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
422 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
423 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
424 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
425 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
426 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
427 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
428 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
429 SSMFIELD_ENTRY_TERM()
430};
431
432
433
434/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
435 * registeres changed. */
436static const SSMFIELD g_aCpumX87FieldsMem[] =
437{
438 SSMFIELD_ENTRY( X86FXSTATE, FCW),
439 SSMFIELD_ENTRY( X86FXSTATE, FSW),
440 SSMFIELD_ENTRY( X86FXSTATE, FTW),
441 SSMFIELD_ENTRY( X86FXSTATE, FOP),
442 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
443 SSMFIELD_ENTRY( X86FXSTATE, CS),
444 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
445 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
446 SSMFIELD_ENTRY( X86FXSTATE, DS),
447 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
448 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
449 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
450 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
451 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
452 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
453 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
454 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
455 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
456 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
457 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
458 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
459 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
460 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
461 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
462 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
463 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
464 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
465 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
466 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
467 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
468 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
469 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
470 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
471 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
472 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
473 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
474 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
475 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
476};
477
478/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
479 * registeres changed. */
480static const SSMFIELD g_aCpumCtxFieldsMem[] =
481{
482 SSMFIELD_ENTRY( CPUMCTX, rdi),
483 SSMFIELD_ENTRY( CPUMCTX, rsi),
484 SSMFIELD_ENTRY( CPUMCTX, rbp),
485 SSMFIELD_ENTRY( CPUMCTX, rax),
486 SSMFIELD_ENTRY( CPUMCTX, rbx),
487 SSMFIELD_ENTRY( CPUMCTX, rdx),
488 SSMFIELD_ENTRY( CPUMCTX, rcx),
489 SSMFIELD_ENTRY( CPUMCTX, rsp),
490 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
491 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
492 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
493 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
494 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
495 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
496 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
497 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
498 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
499 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
500 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
501 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
502 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
503 SSMFIELD_ENTRY( CPUMCTX, rflags),
504 SSMFIELD_ENTRY( CPUMCTX, rip),
505 SSMFIELD_ENTRY( CPUMCTX, r8),
506 SSMFIELD_ENTRY( CPUMCTX, r9),
507 SSMFIELD_ENTRY( CPUMCTX, r10),
508 SSMFIELD_ENTRY( CPUMCTX, r11),
509 SSMFIELD_ENTRY( CPUMCTX, r12),
510 SSMFIELD_ENTRY( CPUMCTX, r13),
511 SSMFIELD_ENTRY( CPUMCTX, r14),
512 SSMFIELD_ENTRY( CPUMCTX, r15),
513 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
514 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
515 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
516 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
517 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
518 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
519 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
520 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
521 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
522 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
523 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
524 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
525 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
528 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
531 SSMFIELD_ENTRY( CPUMCTX, cr0),
532 SSMFIELD_ENTRY( CPUMCTX, cr2),
533 SSMFIELD_ENTRY( CPUMCTX, cr3),
534 SSMFIELD_ENTRY( CPUMCTX, cr4),
535 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
536 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
537 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
538 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
539 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
540 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
541 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
542 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
543 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
544 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
545 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
546 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
547 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
548 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
549 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
550 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
551 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
552 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
553 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
554 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
555 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
556 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
557 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
558 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
559 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
560 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
561 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
562 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
563 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
564 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
565 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
566 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
567 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
568 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
569 SSMFIELD_ENTRY_TERM()
570};
571
572/** Saved state field descriptors for CPUMCTX_VER1_6. */
573static const SSMFIELD g_aCpumX87FieldsV16[] =
574{
575 SSMFIELD_ENTRY( X86FXSTATE, FCW),
576 SSMFIELD_ENTRY( X86FXSTATE, FSW),
577 SSMFIELD_ENTRY( X86FXSTATE, FTW),
578 SSMFIELD_ENTRY( X86FXSTATE, FOP),
579 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
580 SSMFIELD_ENTRY( X86FXSTATE, CS),
581 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
582 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
583 SSMFIELD_ENTRY( X86FXSTATE, DS),
584 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
585 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
586 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
587 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
588 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
589 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
590 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
591 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
592 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
593 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
594 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
595 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
596 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
597 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
598 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
599 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
600 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
601 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
602 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
603 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
604 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
605 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
606 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
607 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
608 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
609 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
610 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
611 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
612 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
613 SSMFIELD_ENTRY_TERM()
614};
615
616/** Saved state field descriptors for CPUMCTX_VER1_6. */
617static const SSMFIELD g_aCpumCtxFieldsV16[] =
618{
619 SSMFIELD_ENTRY( CPUMCTX, rdi),
620 SSMFIELD_ENTRY( CPUMCTX, rsi),
621 SSMFIELD_ENTRY( CPUMCTX, rbp),
622 SSMFIELD_ENTRY( CPUMCTX, rax),
623 SSMFIELD_ENTRY( CPUMCTX, rbx),
624 SSMFIELD_ENTRY( CPUMCTX, rdx),
625 SSMFIELD_ENTRY( CPUMCTX, rcx),
626 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
627 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
628 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
629 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
630 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
631 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
632 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
633 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
634 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
635 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
636 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
637 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
638 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
639 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
640 SSMFIELD_ENTRY( CPUMCTX, rflags),
641 SSMFIELD_ENTRY( CPUMCTX, rip),
642 SSMFIELD_ENTRY( CPUMCTX, r8),
643 SSMFIELD_ENTRY( CPUMCTX, r9),
644 SSMFIELD_ENTRY( CPUMCTX, r10),
645 SSMFIELD_ENTRY( CPUMCTX, r11),
646 SSMFIELD_ENTRY( CPUMCTX, r12),
647 SSMFIELD_ENTRY( CPUMCTX, r13),
648 SSMFIELD_ENTRY( CPUMCTX, r14),
649 SSMFIELD_ENTRY( CPUMCTX, r15),
650 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
651 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
652 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
653 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
654 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
655 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
656 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
657 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
658 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
659 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
660 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
661 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
662 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
663 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
664 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
665 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
666 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
667 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
668 SSMFIELD_ENTRY( CPUMCTX, cr0),
669 SSMFIELD_ENTRY( CPUMCTX, cr2),
670 SSMFIELD_ENTRY( CPUMCTX, cr3),
671 SSMFIELD_ENTRY( CPUMCTX, cr4),
672 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
673 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
674 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
675 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
676 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
677 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
678 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
679 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
680 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
681 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
682 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
683 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
684 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
685 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
686 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
687 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
688 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
689 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
690 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
691 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
692 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
693 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
694 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
695 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
696 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
697 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
698 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
699 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
700 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
701 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
702 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
703 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
704 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
705 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
706 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
707 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
708 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
709 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
710 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
711 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
712 SSMFIELD_ENTRY_TERM()
713};
714
715
716/**
717 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
718 *
719 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
720 * (last instruction pointer, last data pointer, last opcode) except when the ES
721 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
722 * clear these registers there is potential, local FPU leakage from a process
723 * using the FPU to another.
724 *
725 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
726 *
727 * @param pVM The cross context VM structure.
728 */
729static void cpumR3CheckLeakyFpu(PVM pVM)
730{
731 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
732 uint32_t const u32Family = u32CpuVersion >> 8;
733 if ( u32Family >= 6 /* K7 and higher */
734 && ASMIsAmdCpu())
735 {
736 uint32_t cExt = ASMCpuId_EAX(0x80000000);
737 if (ASMIsValidExtRange(cExt))
738 {
739 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
740 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
741 {
742 for (VMCPUID i = 0; i < pVM->cCpus; i++)
743 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
744 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
745 }
746 }
747 }
748}
749
750
751/**
752 * Initializes the CPUM.
753 *
754 * @returns VBox status code.
755 * @param pVM The cross context VM structure.
756 */
757VMMR3DECL(int) CPUMR3Init(PVM pVM)
758{
759 LogFlow(("CPUMR3Init\n"));
760
761 /*
762 * Assert alignment, sizes and tables.
763 */
764 AssertCompileMemberAlignment(VM, cpum.s, 32);
765 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
766 AssertCompileSizeAlignment(CPUMCTX, 64);
767 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
768 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
769 AssertCompileMemberAlignment(VM, cpum, 64);
770 AssertCompileMemberAlignment(VM, aCpus, 64);
771 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
772 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
773#ifdef VBOX_STRICT
774 int rc2 = cpumR3MsrStrictInitChecks();
775 AssertRCReturn(rc2, rc2);
776#endif
777
778 /*
779 * Initialize offsets.
780 */
781
782 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
783 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
784 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
785
786
787 /* Calculate the offset from CPUMCPU to CPUM. */
788 for (VMCPUID i = 0; i < pVM->cCpus; i++)
789 {
790 PVMCPU pVCpu = &pVM->aCpus[i];
791
792 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
793 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
794 }
795
796 /*
797 * Gather info about the host CPU.
798 */
799 if (!ASMHasCpuId())
800 {
801 Log(("The CPU doesn't support CPUID!\n"));
802 return VERR_UNSUPPORTED_CPU;
803 }
804
805 PCPUMCPUIDLEAF paLeaves;
806 uint32_t cLeaves;
807 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
808 AssertLogRelRCReturn(rc, rc);
809
810 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
811 RTMemFree(paLeaves);
812 AssertLogRelRCReturn(rc, rc);
813 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
814
815 /*
816 * Check that the CPU supports the minimum features we require.
817 */
818 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
819 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
820 if (!pVM->cpum.s.HostFeatures.fMmx)
821 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
822 if (!pVM->cpum.s.HostFeatures.fTsc)
823 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
824
825 /*
826 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
827 */
828 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
829 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
830
831 /*
832 * Figure out which XSAVE/XRSTOR features are available on the host.
833 */
834 uint64_t fXcr0Host = 0;
835 uint64_t fXStateHostMask = 0;
836 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
837 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
838 {
839 fXStateHostMask = fXcr0Host = ASMGetXcr0();
840 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
841 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
842 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
843 }
844 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
845 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
846 fXStateHostMask = 0;
847 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
848 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
849
850 /*
851 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
852 */
853 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
854 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
855 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
856
857 uint8_t *pbXStates;
858 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
859 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
860 AssertLogRelRCReturn(rc, rc);
861
862 for (VMCPUID i = 0; i < pVM->cCpus; i++)
863 {
864 PVMCPU pVCpu = &pVM->aCpus[i];
865
866 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
867 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
868 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
869 pbXStates += cbMaxXState;
870
871 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
872 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
873 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
874 pbXStates += cbMaxXState;
875
876 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
877 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
878 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
879 pbXStates += cbMaxXState;
880
881 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
882 }
883
884 /*
885 * Setup hypervisor startup values.
886 */
887
888 /*
889 * Register saved state data item.
890 */
891 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
892 NULL, cpumR3LiveExec, NULL,
893 NULL, cpumR3SaveExec, NULL,
894 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
895 if (RT_FAILURE(rc))
896 return rc;
897
898 /*
899 * Register info handlers and registers with the debugger facility.
900 */
901 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
902 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
903 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
904 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
905 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
906 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
907 DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
908 &cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
909 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
910 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
911 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
912
913 rc = cpumR3DbgInit(pVM);
914 if (RT_FAILURE(rc))
915 return rc;
916
917 /*
918 * Check if we need to workaround partial/leaky FPU handling.
919 */
920 cpumR3CheckLeakyFpu(pVM);
921
922 /*
923 * Initialize the Guest CPUID and MSR states.
924 */
925 rc = cpumR3InitCpuIdAndMsrs(pVM);
926 if (RT_FAILURE(rc))
927 return rc;
928 CPUMR3Reset(pVM);
929 return VINF_SUCCESS;
930}
931
932
933/**
934 * Applies relocations to data and code managed by this
935 * component. This function will be called at init and
936 * whenever the VMM need to relocate it self inside the GC.
937 *
938 * The CPUM will update the addresses used by the switcher.
939 *
940 * @param pVM The cross context VM structure.
941 */
942VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
943{
944 LogFlow(("CPUMR3Relocate\n"));
945
946 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
947 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
948
949 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
950 {
951 PVMCPU pVCpu = &pVM->aCpus[iCpu];
952 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
953 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
954 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
955
956 /* Recheck the guest DRx values in raw-mode. */
957 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
958 }
959}
960
961
962/**
963 * Apply late CPUM property changes based on the fHWVirtEx setting
964 *
965 * @param pVM The cross context VM structure.
966 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
967 */
968VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
969{
970 /*
971 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
972 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
973 * of processors from (cpuid(4).eax >> 26) + 1.
974 *
975 * Note: this code is obsolete, but let's keep it here for reference.
976 * Purpose is valid when we artificially cap the max std id to less than 4.
977 */
978 if (!fHWVirtExEnabled)
979 {
980 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
981 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
982 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
983 }
984}
985
986/**
987 * Terminates the CPUM.
988 *
989 * Termination means cleaning up and freeing all resources,
990 * the VM it self is at this point powered off or suspended.
991 *
992 * @returns VBox status code.
993 * @param pVM The cross context VM structure.
994 */
995VMMR3DECL(int) CPUMR3Term(PVM pVM)
996{
997#ifdef VBOX_WITH_CRASHDUMP_MAGIC
998 for (VMCPUID i = 0; i < pVM->cCpus; i++)
999 {
1000 PVMCPU pVCpu = &pVM->aCpus[i];
1001 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1002
1003 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1004 pVCpu->cpum.s.uMagic = 0;
1005 pCtx->dr[5] = 0;
1006 }
1007#else
1008 NOREF(pVM);
1009#endif
1010 return VINF_SUCCESS;
1011}
1012
1013
1014/**
1015 * Resets a virtual CPU.
1016 *
1017 * Used by CPUMR3Reset and CPU hot plugging.
1018 *
1019 * @param pVM The cross context VM structure.
1020 * @param pVCpu The cross context virtual CPU structure of the CPU that is
1021 * being reset. This may differ from the current EMT.
1022 */
1023VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1024{
1025 /** @todo anything different for VCPU > 0? */
1026 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1027
1028 /*
1029 * Initialize everything to ZERO first.
1030 */
1031 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1032
1033 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1034 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1035 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1036
1037 pVCpu->cpum.s.fUseFlags = fUseFlags;
1038
1039 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1040 pCtx->eip = 0x0000fff0;
1041 pCtx->edx = 0x00000600; /* P6 processor */
1042 pCtx->eflags.Bits.u1Reserved0 = 1;
1043
1044 pCtx->cs.Sel = 0xf000;
1045 pCtx->cs.ValidSel = 0xf000;
1046 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1047 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1048 pCtx->cs.u32Limit = 0x0000ffff;
1049 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1050 pCtx->cs.Attr.n.u1Present = 1;
1051 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1052
1053 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1054 pCtx->ds.u32Limit = 0x0000ffff;
1055 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1056 pCtx->ds.Attr.n.u1Present = 1;
1057 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1058
1059 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1060 pCtx->es.u32Limit = 0x0000ffff;
1061 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1062 pCtx->es.Attr.n.u1Present = 1;
1063 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1064
1065 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1066 pCtx->fs.u32Limit = 0x0000ffff;
1067 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1068 pCtx->fs.Attr.n.u1Present = 1;
1069 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1070
1071 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1072 pCtx->gs.u32Limit = 0x0000ffff;
1073 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1074 pCtx->gs.Attr.n.u1Present = 1;
1075 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1076
1077 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1078 pCtx->ss.u32Limit = 0x0000ffff;
1079 pCtx->ss.Attr.n.u1Present = 1;
1080 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1081 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1082
1083 pCtx->idtr.cbIdt = 0xffff;
1084 pCtx->gdtr.cbGdt = 0xffff;
1085
1086 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1087 pCtx->ldtr.u32Limit = 0xffff;
1088 pCtx->ldtr.Attr.n.u1Present = 1;
1089 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1090
1091 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1092 pCtx->tr.u32Limit = 0xffff;
1093 pCtx->tr.Attr.n.u1Present = 1;
1094 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1095
1096 pCtx->dr[6] = X86_DR6_INIT_VAL;
1097 pCtx->dr[7] = X86_DR7_INIT_VAL;
1098
1099 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1100 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1101 pFpuCtx->FCW = 0x37f;
1102
1103 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1104 IA-32 Processor States Following Power-up, Reset, or INIT */
1105 pFpuCtx->MXCSR = 0x1F80;
1106 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1107 supports all bits, since a zero value here should be read as 0xffbf. */
1108 pCtx->aXcr[0] = XSAVE_C_X87;
1109 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1110 {
1111 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1112 as we don't know what happened before. (Bother optimize later?) */
1113 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1114 }
1115
1116 /*
1117 * MSRs.
1118 */
1119 /* Init PAT MSR */
1120 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1121
1122 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1123 * The Intel docs don't mention it. */
1124 Assert(!pCtx->msrEFER);
1125
1126 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1127 is supposed to be here, just trying provide useful/sensible values. */
1128 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1129 if (pRange)
1130 {
1131 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1132 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1133 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1134 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1135 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1136 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1137 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1138 }
1139
1140 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1141
1142 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1143 * called from each EMT while we're getting called by CPUMR3Reset()
1144 * iteratively on the same thread. Fix later. */
1145#if 0 /** @todo r=bird: This we will do in TM, not here. */
1146 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1147 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1148#endif
1149
1150
1151 /* C-state control. Guesses. */
1152 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1153}
1154
1155
1156/**
1157 * Resets the CPU.
1158 *
1159 * @returns VINF_SUCCESS.
1160 * @param pVM The cross context VM structure.
1161 */
1162VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1163{
1164 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1165 {
1166 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1167
1168#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1169 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1170
1171 /* Magic marker for searching in crash dumps. */
1172 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1173 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1174 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1175#endif
1176 }
1177}
1178
1179
1180
1181
1182/**
1183 * Pass 0 live exec callback.
1184 *
1185 * @returns VINF_SSM_DONT_CALL_AGAIN.
1186 * @param pVM The cross context VM structure.
1187 * @param pSSM The saved state handle.
1188 * @param uPass The pass (0).
1189 */
1190static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1191{
1192 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1193 cpumR3SaveCpuId(pVM, pSSM);
1194 return VINF_SSM_DONT_CALL_AGAIN;
1195}
1196
1197
1198/**
1199 * Execute state save operation.
1200 *
1201 * @returns VBox status code.
1202 * @param pVM The cross context VM structure.
1203 * @param pSSM SSM operation handle.
1204 */
1205static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1206{
1207 /*
1208 * Save.
1209 */
1210 SSMR3PutU32(pSSM, pVM->cCpus);
1211 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1212 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1213 {
1214 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1215
1216 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1217
1218 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1219 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1220 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1221 if (pGstCtx->fXStateMask != 0)
1222 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1223 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1224 {
1225 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1226 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1227 }
1228 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1229 {
1230 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1231 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1232 }
1233 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1234 {
1235 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1236 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1237 }
1238 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1239 {
1240 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1241 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1242 }
1243 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1244 {
1245 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1246 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1247 }
1248
1249 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1250 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1251 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1252 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1253 }
1254
1255 cpumR3SaveCpuId(pVM, pSSM);
1256 return VINF_SUCCESS;
1257}
1258
1259
1260/**
1261 * @callback_method_impl{FNSSMINTLOADPREP}
1262 */
1263static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1264{
1265 NOREF(pSSM);
1266 pVM->cpum.s.fPendingRestore = true;
1267 return VINF_SUCCESS;
1268}
1269
1270
1271/**
1272 * @callback_method_impl{FNSSMINTLOADEXEC}
1273 */
1274static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1275{
1276 int rc; /* Only for AssertRCReturn use. */
1277
1278 /*
1279 * Validate version.
1280 */
1281 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1282 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1283 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1284 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1285 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1286 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1287 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1288 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1289 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1290 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1291 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1292 {
1293 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1294 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1295 }
1296
1297 if (uPass == SSM_PASS_FINAL)
1298 {
1299 /*
1300 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1301 * really old SSM file versions.)
1302 */
1303 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1304 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1305 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1306 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1307
1308 /*
1309 * Figure x86 and ctx field definitions to use for older states.
1310 */
1311 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1312 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1313 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1314 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1315 {
1316 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1317 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1318 }
1319 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1320 {
1321 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1322 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1323 }
1324
1325 /*
1326 * The hyper state used to preceed the CPU count. Starting with
1327 * XSAVE it was moved down till after we've got the count.
1328 */
1329 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1330 {
1331 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1332 {
1333 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1334 X86FXSTATE Ign;
1335 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1336 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1337 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1338 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1339 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1340 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1341 pVCpu->cpum.s.Hyper.rsp = uRSP;
1342 }
1343 }
1344
1345 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1346 {
1347 uint32_t cCpus;
1348 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1349 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1350 VERR_SSM_UNEXPECTED_DATA);
1351 }
1352 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1353 || pVM->cCpus == 1,
1354 ("cCpus=%u\n", pVM->cCpus),
1355 VERR_SSM_UNEXPECTED_DATA);
1356
1357 uint32_t cbMsrs = 0;
1358 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1359 {
1360 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1361 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1362 VERR_SSM_UNEXPECTED_DATA);
1363 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1364 VERR_SSM_UNEXPECTED_DATA);
1365 }
1366
1367 /*
1368 * Do the per-CPU restoring.
1369 */
1370 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1371 {
1372 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1373 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1374
1375 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1376 {
1377 /*
1378 * The XSAVE saved state layout moved the hyper state down here.
1379 */
1380 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1381 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1382 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1383 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1384 pVCpu->cpum.s.Hyper.rsp = uRSP;
1385 AssertRCReturn(rc, rc);
1386
1387 /*
1388 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1389 */
1390 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1391 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1392 AssertRCReturn(rc, rc);
1393
1394 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1395 if (pGstCtx->fXStateMask != 0)
1396 {
1397 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1398 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1399 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1400 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1401 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1402 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1403 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1404 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1405 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1406 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1407 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1408 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1409 }
1410
1411 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1412 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1413 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1414 {
1415 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1416 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1417 VERR_CPUM_INVALID_XCR0);
1418 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1419 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1420 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1421 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1422 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1423 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1424 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1425 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1426 }
1427
1428 /* Check that the XCR1 is zero, as we don't implement it yet. */
1429 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1430
1431 /*
1432 * Restore the individual extended state components we support.
1433 */
1434 if (pGstCtx->fXStateMask != 0)
1435 {
1436 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1437 0, g_aCpumXSaveHdrFields, NULL);
1438 AssertRCReturn(rc, rc);
1439 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1440 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1441 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1442 VERR_CPUM_INVALID_XSAVE_HDR);
1443 }
1444 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1445 {
1446 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1447 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1448 }
1449 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1450 {
1451 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1452 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1453 }
1454 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1455 {
1456 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1457 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1458 }
1459 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1460 {
1461 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1462 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1463 }
1464 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1465 {
1466 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1467 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1468 }
1469 }
1470 else
1471 {
1472 /*
1473 * Pre XSAVE saved state.
1474 */
1475 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1476 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1477 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1478 }
1479
1480 /*
1481 * Restore a couple of flags and the MSRs.
1482 */
1483 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1484 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1485
1486 rc = VINF_SUCCESS;
1487 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1488 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1489 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1490 {
1491 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1492 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1493 }
1494 AssertRCReturn(rc, rc);
1495
1496 /* REM and other may have cleared must-be-one fields in DR6 and
1497 DR7, fix these. */
1498 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1499 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1500 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1501 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1502 }
1503
1504 /* Older states does not have the internal selector register flags
1505 and valid selector value. Supply those. */
1506 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1507 {
1508 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1509 {
1510 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1511 bool const fValid = HMIsEnabled(pVM)
1512 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1513 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1514 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1515 if (fValid)
1516 {
1517 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1518 {
1519 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1520 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1521 }
1522
1523 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1524 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1525 }
1526 else
1527 {
1528 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1529 {
1530 paSelReg[iSelReg].fFlags = 0;
1531 paSelReg[iSelReg].ValidSel = 0;
1532 }
1533
1534 /* This might not be 104% correct, but I think it's close
1535 enough for all practical purposes... (REM always loaded
1536 LDTR registers.) */
1537 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1538 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1539 }
1540 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1541 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1542 }
1543 }
1544
1545 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1546 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1547 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1548 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1549 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1550
1551 /*
1552 * A quick sanity check.
1553 */
1554 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1555 {
1556 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1557 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1558 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1559 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1560 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1561 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1562 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1563 }
1564 }
1565
1566 pVM->cpum.s.fPendingRestore = false;
1567
1568 /*
1569 * Guest CPUIDs.
1570 */
1571 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1572 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1573 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1574}
1575
1576
1577/**
1578 * @callback_method_impl{FNSSMINTLOADDONE}
1579 */
1580static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1581{
1582 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1583 return VINF_SUCCESS;
1584
1585 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1586 if (pVM->cpum.s.fPendingRestore)
1587 {
1588 LogRel(("CPUM: Missing state!\n"));
1589 return VERR_INTERNAL_ERROR_2;
1590 }
1591
1592 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1593 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1594 {
1595 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1596
1597 /* Notify PGM of the NXE states in case they've changed. */
1598 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1599
1600 /* During init. this is done in CPUMR3InitCompleted(). */
1601 if (fSupportsLongMode)
1602 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1603 }
1604 return VINF_SUCCESS;
1605}
1606
1607
1608/**
1609 * Checks if the CPUM state restore is still pending.
1610 *
1611 * @returns true / false.
1612 * @param pVM The cross context VM structure.
1613 */
1614VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1615{
1616 return pVM->cpum.s.fPendingRestore;
1617}
1618
1619
1620/**
1621 * Formats the EFLAGS value into mnemonics.
1622 *
1623 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1624 * @param efl The EFLAGS value.
1625 */
1626static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1627{
1628 /*
1629 * Format the flags.
1630 */
1631 static const struct
1632 {
1633 const char *pszSet; const char *pszClear; uint32_t fFlag;
1634 } s_aFlags[] =
1635 {
1636 { "vip",NULL, X86_EFL_VIP },
1637 { "vif",NULL, X86_EFL_VIF },
1638 { "ac", NULL, X86_EFL_AC },
1639 { "vm", NULL, X86_EFL_VM },
1640 { "rf", NULL, X86_EFL_RF },
1641 { "nt", NULL, X86_EFL_NT },
1642 { "ov", "nv", X86_EFL_OF },
1643 { "dn", "up", X86_EFL_DF },
1644 { "ei", "di", X86_EFL_IF },
1645 { "tf", NULL, X86_EFL_TF },
1646 { "nt", "pl", X86_EFL_SF },
1647 { "nz", "zr", X86_EFL_ZF },
1648 { "ac", "na", X86_EFL_AF },
1649 { "po", "pe", X86_EFL_PF },
1650 { "cy", "nc", X86_EFL_CF },
1651 };
1652 char *psz = pszEFlags;
1653 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1654 {
1655 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1656 if (pszAdd)
1657 {
1658 strcpy(psz, pszAdd);
1659 psz += strlen(pszAdd);
1660 *psz++ = ' ';
1661 }
1662 }
1663 psz[-1] = '\0';
1664}
1665
1666
1667/**
1668 * Formats a full register dump.
1669 *
1670 * @param pVM The cross context VM structure.
1671 * @param pCtx The context to format.
1672 * @param pCtxCore The context core to format.
1673 * @param pHlp Output functions.
1674 * @param enmType The dump type.
1675 * @param pszPrefix Register name prefix.
1676 */
1677static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1678 const char *pszPrefix)
1679{
1680 NOREF(pVM);
1681
1682 /*
1683 * Format the EFLAGS.
1684 */
1685 uint32_t efl = pCtxCore->eflags.u32;
1686 char szEFlags[80];
1687 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1688
1689 /*
1690 * Format the registers.
1691 */
1692 switch (enmType)
1693 {
1694 case CPUMDUMPTYPE_TERSE:
1695 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1696 pHlp->pfnPrintf(pHlp,
1697 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1698 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1699 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1700 "%sr14=%016RX64 %sr15=%016RX64\n"
1701 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1702 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1703 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1704 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1705 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1706 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1707 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1708 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1709 else
1710 pHlp->pfnPrintf(pHlp,
1711 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1712 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1713 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1714 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1715 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1716 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1717 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1718 break;
1719
1720 case CPUMDUMPTYPE_DEFAULT:
1721 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1722 pHlp->pfnPrintf(pHlp,
1723 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1724 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1725 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1726 "%sr14=%016RX64 %sr15=%016RX64\n"
1727 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1728 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1729 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1730 ,
1731 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1732 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1733 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1734 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1735 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1736 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1737 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1738 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1739 else
1740 pHlp->pfnPrintf(pHlp,
1741 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1742 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1743 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1744 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1745 ,
1746 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1747 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1748 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1749 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1750 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1751 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1752 break;
1753
1754 case CPUMDUMPTYPE_VERBOSE:
1755 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1756 pHlp->pfnPrintf(pHlp,
1757 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1758 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1759 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1760 "%sr14=%016RX64 %sr15=%016RX64\n"
1761 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1762 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1763 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1764 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1765 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1766 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1767 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1768 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1769 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1770 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1771 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1772 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1773 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1774 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1775 ,
1776 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1777 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1778 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1779 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1780 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1781 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1782 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1783 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1784 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1785 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1786 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1787 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1788 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1789 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1790 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1791 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1792 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1793 else
1794 pHlp->pfnPrintf(pHlp,
1795 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1796 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1797 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1798 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1799 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1800 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1801 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1802 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1803 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1804 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1805 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1806 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1807 ,
1808 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1809 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1810 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1811 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1812 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1813 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1814 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1815 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1816 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1817 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1818 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1819 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1820
1821 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1822 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1823 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1824 if (pCtx->CTX_SUFF(pXState))
1825 {
1826 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1827 pHlp->pfnPrintf(pHlp,
1828 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1829 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1830 ,
1831 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1832 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1833 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1834 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1835 );
1836 /*
1837 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1838 * not (FP)R0-7 as Intel SDM suggests.
1839 */
1840 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1841 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1842 {
1843 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1844 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1845 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1846 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1847 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1848 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1849 iExponent -= 16383; /* subtract bias */
1850 /** @todo This isn't entirenly correct and needs more work! */
1851 pHlp->pfnPrintf(pHlp,
1852 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1853 pszPrefix, iST, pszPrefix, iFPR,
1854 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1855 uTag, chSign, iInteger, u64Fraction, iExponent);
1856 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
1857 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1858 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1859 else
1860 pHlp->pfnPrintf(pHlp, "\n");
1861 }
1862
1863 /* XMM/YMM/ZMM registers. */
1864 if (pCtx->fXStateMask & XSAVE_C_YMM)
1865 {
1866 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1867 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1868 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1869 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1870 pszPrefix, i, i < 10 ? " " : "",
1871 pYmmHiCtx->aYmmHi[i].au32[3],
1872 pYmmHiCtx->aYmmHi[i].au32[2],
1873 pYmmHiCtx->aYmmHi[i].au32[1],
1874 pYmmHiCtx->aYmmHi[i].au32[0],
1875 pFpuCtx->aXMM[i].au32[3],
1876 pFpuCtx->aXMM[i].au32[2],
1877 pFpuCtx->aXMM[i].au32[1],
1878 pFpuCtx->aXMM[i].au32[0]);
1879 else
1880 {
1881 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1882 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1883 pHlp->pfnPrintf(pHlp,
1884 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1885 pszPrefix, i, i < 10 ? " " : "",
1886 pZmmHi256->aHi256Regs[i].au32[7],
1887 pZmmHi256->aHi256Regs[i].au32[6],
1888 pZmmHi256->aHi256Regs[i].au32[5],
1889 pZmmHi256->aHi256Regs[i].au32[4],
1890 pZmmHi256->aHi256Regs[i].au32[3],
1891 pZmmHi256->aHi256Regs[i].au32[2],
1892 pZmmHi256->aHi256Regs[i].au32[1],
1893 pZmmHi256->aHi256Regs[i].au32[0],
1894 pYmmHiCtx->aYmmHi[i].au32[3],
1895 pYmmHiCtx->aYmmHi[i].au32[2],
1896 pYmmHiCtx->aYmmHi[i].au32[1],
1897 pYmmHiCtx->aYmmHi[i].au32[0],
1898 pFpuCtx->aXMM[i].au32[3],
1899 pFpuCtx->aXMM[i].au32[2],
1900 pFpuCtx->aXMM[i].au32[1],
1901 pFpuCtx->aXMM[i].au32[0]);
1902
1903 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1904 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
1905 pHlp->pfnPrintf(pHlp,
1906 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1907 pszPrefix, i + 16,
1908 pZmm16Hi->aRegs[i].au32[15],
1909 pZmm16Hi->aRegs[i].au32[14],
1910 pZmm16Hi->aRegs[i].au32[13],
1911 pZmm16Hi->aRegs[i].au32[12],
1912 pZmm16Hi->aRegs[i].au32[11],
1913 pZmm16Hi->aRegs[i].au32[10],
1914 pZmm16Hi->aRegs[i].au32[9],
1915 pZmm16Hi->aRegs[i].au32[8],
1916 pZmm16Hi->aRegs[i].au32[7],
1917 pZmm16Hi->aRegs[i].au32[6],
1918 pZmm16Hi->aRegs[i].au32[5],
1919 pZmm16Hi->aRegs[i].au32[4],
1920 pZmm16Hi->aRegs[i].au32[3],
1921 pZmm16Hi->aRegs[i].au32[2],
1922 pZmm16Hi->aRegs[i].au32[1],
1923 pZmm16Hi->aRegs[i].au32[0]);
1924 }
1925 }
1926 else
1927 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1928 pHlp->pfnPrintf(pHlp,
1929 i & 1
1930 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1931 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1932 pszPrefix, i, i < 10 ? " " : "",
1933 pFpuCtx->aXMM[i].au32[3],
1934 pFpuCtx->aXMM[i].au32[2],
1935 pFpuCtx->aXMM[i].au32[1],
1936 pFpuCtx->aXMM[i].au32[0]);
1937
1938 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
1939 {
1940 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
1941 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
1942 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
1943 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
1944 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
1945 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
1946 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
1947 }
1948
1949 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
1950 {
1951 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1952 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
1953 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
1954 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
1955 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
1956 }
1957
1958 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
1959 {
1960 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1961 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
1962 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
1963 }
1964
1965 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1966 if (pFpuCtx->au32RsrvdRest[i])
1967 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
1968 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1969 }
1970
1971 pHlp->pfnPrintf(pHlp,
1972 "%sEFER =%016RX64\n"
1973 "%sPAT =%016RX64\n"
1974 "%sSTAR =%016RX64\n"
1975 "%sCSTAR =%016RX64\n"
1976 "%sLSTAR =%016RX64\n"
1977 "%sSFMASK =%016RX64\n"
1978 "%sKERNELGSBASE =%016RX64\n",
1979 pszPrefix, pCtx->msrEFER,
1980 pszPrefix, pCtx->msrPAT,
1981 pszPrefix, pCtx->msrSTAR,
1982 pszPrefix, pCtx->msrCSTAR,
1983 pszPrefix, pCtx->msrLSTAR,
1984 pszPrefix, pCtx->msrSFMASK,
1985 pszPrefix, pCtx->msrKERNELGSBASE);
1986 break;
1987 }
1988}
1989
1990
1991/**
1992 * Display all cpu states and any other cpum info.
1993 *
1994 * @param pVM The cross context VM structure.
1995 * @param pHlp The info helper functions.
1996 * @param pszArgs Arguments, ignored.
1997 */
1998static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1999{
2000 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2001 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2002 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2003 cpumR3InfoHost(pVM, pHlp, pszArgs);
2004}
2005
2006
2007/**
2008 * Parses the info argument.
2009 *
2010 * The argument starts with 'verbose', 'terse' or 'default' and then
2011 * continues with the comment string.
2012 *
2013 * @param pszArgs The pointer to the argument string.
2014 * @param penmType Where to store the dump type request.
2015 * @param ppszComment Where to store the pointer to the comment string.
2016 */
2017static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
2018{
2019 if (!pszArgs)
2020 {
2021 *penmType = CPUMDUMPTYPE_DEFAULT;
2022 *ppszComment = "";
2023 }
2024 else
2025 {
2026 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2027 {
2028 pszArgs += 7;
2029 *penmType = CPUMDUMPTYPE_VERBOSE;
2030 }
2031 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2032 {
2033 pszArgs += 5;
2034 *penmType = CPUMDUMPTYPE_TERSE;
2035 }
2036 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2037 {
2038 pszArgs += 7;
2039 *penmType = CPUMDUMPTYPE_DEFAULT;
2040 }
2041 else
2042 *penmType = CPUMDUMPTYPE_DEFAULT;
2043 *ppszComment = RTStrStripL(pszArgs);
2044 }
2045}
2046
2047
2048/**
2049 * Display the guest cpu state.
2050 *
2051 * @param pVM The cross context VM structure.
2052 * @param pHlp The info helper functions.
2053 * @param pszArgs Arguments, ignored.
2054 */
2055static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2056{
2057 CPUMDUMPTYPE enmType;
2058 const char *pszComment;
2059 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2060
2061 PVMCPU pVCpu = VMMGetCpu(pVM);
2062 if (!pVCpu)
2063 pVCpu = &pVM->aCpus[0];
2064
2065 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2066
2067 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2068 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2069}
2070
2071
2072/**
2073 * Display the current guest instruction
2074 *
2075 * @param pVM The cross context VM structure.
2076 * @param pHlp The info helper functions.
2077 * @param pszArgs Arguments, ignored.
2078 */
2079static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2080{
2081 NOREF(pszArgs);
2082
2083 PVMCPU pVCpu = VMMGetCpu(pVM);
2084 if (!pVCpu)
2085 pVCpu = &pVM->aCpus[0];
2086
2087 char szInstruction[256];
2088 szInstruction[0] = '\0';
2089 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2090 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2091}
2092
2093
2094/**
2095 * Display the hypervisor cpu state.
2096 *
2097 * @param pVM The cross context VM structure.
2098 * @param pHlp The info helper functions.
2099 * @param pszArgs Arguments, ignored.
2100 */
2101static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2102{
2103 PVMCPU pVCpu = VMMGetCpu(pVM);
2104 if (!pVCpu)
2105 pVCpu = &pVM->aCpus[0];
2106
2107 CPUMDUMPTYPE enmType;
2108 const char *pszComment;
2109 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2110 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2111 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2112 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2113}
2114
2115
2116/**
2117 * Display the host cpu state.
2118 *
2119 * @param pVM The cross context VM structure.
2120 * @param pHlp The info helper functions.
2121 * @param pszArgs Arguments, ignored.
2122 */
2123static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2124{
2125 CPUMDUMPTYPE enmType;
2126 const char *pszComment;
2127 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2128 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2129
2130 PVMCPU pVCpu = VMMGetCpu(pVM);
2131 if (!pVCpu)
2132 pVCpu = &pVM->aCpus[0];
2133 PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2134
2135 /*
2136 * Format the EFLAGS.
2137 */
2138#if HC_ARCH_BITS == 32
2139 uint32_t efl = pCtx->eflags.u32;
2140#else
2141 uint64_t efl = pCtx->rflags;
2142#endif
2143 char szEFlags[80];
2144 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2145
2146 /*
2147 * Format the registers.
2148 */
2149#if HC_ARCH_BITS == 32
2150 pHlp->pfnPrintf(pHlp,
2151 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2152 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2153 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2154 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2155 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2156 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2157 ,
2158 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2159 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2160 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2161 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2162 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2163 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2164 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2165#else
2166 pHlp->pfnPrintf(pHlp,
2167 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2168 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2169 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2170 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2171 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2172 "r14=%016RX64 r15=%016RX64\n"
2173 "iopl=%d %31s\n"
2174 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2175 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2176 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2177 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2178 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2179 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2180 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2181 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2182 ,
2183 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2184 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2185 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2186 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2187 pCtx->r11, pCtx->r12, pCtx->r13,
2188 pCtx->r14, pCtx->r15,
2189 X86_EFL_GET_IOPL(efl), szEFlags,
2190 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2191 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2192 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2193 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2194 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2195 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2196 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2197 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2198#endif
2199}
2200
2201/**
2202 * Structure used when disassembling and instructions in DBGF.
2203 * This is used so the reader function can get the stuff it needs.
2204 */
2205typedef struct CPUMDISASSTATE
2206{
2207 /** Pointer to the CPU structure. */
2208 PDISCPUSTATE pCpu;
2209 /** Pointer to the VM. */
2210 PVM pVM;
2211 /** Pointer to the VMCPU. */
2212 PVMCPU pVCpu;
2213 /** Pointer to the first byte in the segment. */
2214 RTGCUINTPTR GCPtrSegBase;
2215 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2216 RTGCUINTPTR GCPtrSegEnd;
2217 /** The size of the segment minus 1. */
2218 RTGCUINTPTR cbSegLimit;
2219 /** Pointer to the current page - R3 Ptr. */
2220 void const *pvPageR3;
2221 /** Pointer to the current page - GC Ptr. */
2222 RTGCPTR pvPageGC;
2223 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2224 PGMPAGEMAPLOCK PageMapLock;
2225 /** Whether the PageMapLock is valid or not. */
2226 bool fLocked;
2227 /** 64 bits mode or not. */
2228 bool f64Bits;
2229} CPUMDISASSTATE, *PCPUMDISASSTATE;
2230
2231
2232/**
2233 * @callback_method_impl{FNDISREADBYTES}
2234 */
2235static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2236{
2237 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2238 for (;;)
2239 {
2240 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2241
2242 /*
2243 * Need to update the page translation?
2244 */
2245 if ( !pState->pvPageR3
2246 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2247 {
2248 int rc = VINF_SUCCESS;
2249
2250 /* translate the address */
2251 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2252 if ( !HMIsEnabled(pState->pVM)
2253 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2254 {
2255 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2256 if (!pState->pvPageR3)
2257 rc = VERR_INVALID_POINTER;
2258 }
2259 else
2260 {
2261 /* Release mapping lock previously acquired. */
2262 if (pState->fLocked)
2263 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2264 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2265 pState->fLocked = RT_SUCCESS_NP(rc);
2266 }
2267 if (RT_FAILURE(rc))
2268 {
2269 pState->pvPageR3 = NULL;
2270 return rc;
2271 }
2272 }
2273
2274 /*
2275 * Check the segment limit.
2276 */
2277 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2278 return VERR_OUT_OF_SELECTOR_BOUNDS;
2279
2280 /*
2281 * Calc how much we can read.
2282 */
2283 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2284 if (!pState->f64Bits)
2285 {
2286 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2287 if (cb > cbSeg && cbSeg)
2288 cb = cbSeg;
2289 }
2290 if (cb > cbMaxRead)
2291 cb = cbMaxRead;
2292
2293 /*
2294 * Read and advance or exit.
2295 */
2296 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2297 offInstr += (uint8_t)cb;
2298 if (cb >= cbMinRead)
2299 {
2300 pDis->cbCachedInstr = offInstr;
2301 return VINF_SUCCESS;
2302 }
2303 cbMinRead -= (uint8_t)cb;
2304 cbMaxRead -= (uint8_t)cb;
2305 }
2306}
2307
2308
2309/**
2310 * Disassemble an instruction and return the information in the provided structure.
2311 *
2312 * @returns VBox status code.
2313 * @param pVM The cross context VM structure.
2314 * @param pVCpu The cross context virtual CPU structure.
2315 * @param pCtx Pointer to the guest CPU context.
2316 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2317 * @param pCpu Disassembly state.
2318 * @param pszPrefix String prefix for logging (debug only).
2319 *
2320 */
2321VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2322 const char *pszPrefix)
2323{
2324 CPUMDISASSTATE State;
2325 int rc;
2326
2327 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2328 State.pCpu = pCpu;
2329 State.pvPageGC = 0;
2330 State.pvPageR3 = NULL;
2331 State.pVM = pVM;
2332 State.pVCpu = pVCpu;
2333 State.fLocked = false;
2334 State.f64Bits = false;
2335
2336 /*
2337 * Get selector information.
2338 */
2339 DISCPUMODE enmDisCpuMode;
2340 if ( (pCtx->cr0 & X86_CR0_PE)
2341 && pCtx->eflags.Bits.u1VM == 0)
2342 {
2343 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2344 {
2345# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2346 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2347# endif
2348 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2349 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2350 }
2351 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2352 State.GCPtrSegBase = pCtx->cs.u64Base;
2353 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2354 State.cbSegLimit = pCtx->cs.u32Limit;
2355 enmDisCpuMode = (State.f64Bits)
2356 ? DISCPUMODE_64BIT
2357 : pCtx->cs.Attr.n.u1DefBig
2358 ? DISCPUMODE_32BIT
2359 : DISCPUMODE_16BIT;
2360 }
2361 else
2362 {
2363 /* real or V86 mode */
2364 enmDisCpuMode = DISCPUMODE_16BIT;
2365 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2366 State.GCPtrSegEnd = 0xFFFFFFFF;
2367 State.cbSegLimit = 0xFFFFFFFF;
2368 }
2369
2370 /*
2371 * Disassemble the instruction.
2372 */
2373 uint32_t cbInstr;
2374#ifndef LOG_ENABLED
2375 RT_NOREF_PV(pszPrefix);
2376 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2377 if (RT_SUCCESS(rc))
2378 {
2379#else
2380 char szOutput[160];
2381 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2382 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2383 if (RT_SUCCESS(rc))
2384 {
2385 /* log it */
2386 if (pszPrefix)
2387 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2388 else
2389 Log(("%s", szOutput));
2390#endif
2391 rc = VINF_SUCCESS;
2392 }
2393 else
2394 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2395
2396 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2397 if (State.fLocked)
2398 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2399
2400 return rc;
2401}
2402
2403
2404
2405/**
2406 * API for controlling a few of the CPU features found in CR4.
2407 *
2408 * Currently only X86_CR4_TSD is accepted as input.
2409 *
2410 * @returns VBox status code.
2411 *
2412 * @param pVM The cross context VM structure.
2413 * @param fOr The CR4 OR mask.
2414 * @param fAnd The CR4 AND mask.
2415 */
2416VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2417{
2418 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2419 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2420
2421 pVM->cpum.s.CR4.OrMask &= fAnd;
2422 pVM->cpum.s.CR4.OrMask |= fOr;
2423
2424 return VINF_SUCCESS;
2425}
2426
2427
2428/**
2429 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2430 *
2431 * Only REM should ever call this function!
2432 *
2433 * @returns The changed flags.
2434 * @param pVCpu The cross context virtual CPU structure.
2435 * @param puCpl Where to return the current privilege level (CPL).
2436 */
2437VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2438{
2439 Assert(!pVCpu->cpum.s.fRawEntered);
2440 Assert(!pVCpu->cpum.s.fRemEntered);
2441
2442 /*
2443 * Get the CPL first.
2444 */
2445 *puCpl = CPUMGetGuestCPL(pVCpu);
2446
2447 /*
2448 * Get and reset the flags.
2449 */
2450 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2451 pVCpu->cpum.s.fChanged = 0;
2452
2453 /** @todo change the switcher to use the fChanged flags. */
2454 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2455 {
2456 fFlags |= CPUM_CHANGED_FPU_REM;
2457 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2458 }
2459
2460 pVCpu->cpum.s.fRemEntered = true;
2461 return fFlags;
2462}
2463
2464
2465/**
2466 * Leaves REM.
2467 *
2468 * @param pVCpu The cross context virtual CPU structure.
2469 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2470 * registers.
2471 */
2472VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2473{
2474 Assert(!pVCpu->cpum.s.fRawEntered);
2475 Assert(pVCpu->cpum.s.fRemEntered);
2476
2477 RT_NOREF_PV(fNoOutOfSyncSels);
2478
2479 pVCpu->cpum.s.fRemEntered = false;
2480}
2481
2482
2483/**
2484 * Called when the ring-3 init phase completes.
2485 *
2486 * @returns VBox status code.
2487 * @param pVM The cross context VM structure.
2488 * @param enmWhat Which init phase.
2489 */
2490VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2491{
2492 switch (enmWhat)
2493 {
2494 case VMINITCOMPLETED_RING3:
2495 {
2496 /*
2497 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2498 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2499 */
2500 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2501 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2502 {
2503 PVMCPU pVCpu = &pVM->aCpus[i];
2504 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2505 if (fSupportsLongMode)
2506 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2507 }
2508
2509 cpumR3MsrRegStats(pVM);
2510 break;
2511 }
2512
2513 default:
2514 break;
2515 }
2516 return VINF_SUCCESS;
2517}
2518
2519
2520/**
2521 * Called when the ring-0 init phases completed.
2522 *
2523 * @param pVM The cross context VM structure.
2524 */
2525VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2526{
2527 /*
2528 * Log the cpuid.
2529 */
2530 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2531 RTCPUSET OnlineSet;
2532 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2533 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2534 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2535 RTCPUID cCores = RTMpGetCoreCount();
2536 if (cCores)
2537 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2538 LogRel(("************************* CPUID dump ************************\n"));
2539 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2540 LogRel(("\n"));
2541 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
2542 RTLogRelSetBuffering(fOldBuffered);
2543 LogRel(("******************** End of CPUID dump **********************\n"));
2544}
2545
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