VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 66124

Last change on this file since 66124 was 65904, checked in by vboxsync, 8 years ago

VMM: Nested Hw.virt: Started with tweaking the AMD bits and laying the groundwork.
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1/* $Id: CPUM.cpp 65904 2017-03-01 10:21:38Z vboxsync $ */
2/** @file
3 * CPUM - CPU Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_cpum CPUM - CPU Monitor / Manager
19 *
20 * The CPU Monitor / Manager keeps track of all the CPU registers. It is
21 * also responsible for lazy FPU handling and some of the context loading
22 * in raw mode.
23 *
24 * There are three CPU contexts, the most important one is the guest one (GC).
25 * When running in raw-mode (RC) there is a special hyper context for the VMM
26 * part that floats around inside the guest address space. When running in
27 * raw-mode, CPUM also maintains a host context for saving and restoring
28 * registers across world switches. This latter is done in cooperation with the
29 * world switcher (@see pg_vmm).
30 *
31 * @see grp_cpum
32 *
33 * @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34 *
35 * TODO: proper write up, currently just some notes.
36 *
37 * The ring-0 FPU handling per OS:
38 *
39 * - 64-bit Windows uses XMM registers in the kernel as part of the calling
40 * convention (Visual C++ doesn't seem to have a way to disable
41 * generating such code either), so CR0.TS/EM are always zero from what I
42 * can tell. We are also forced to always load/save the guest XMM0-XMM15
43 * registers when entering/leaving guest context. Interrupt handlers
44 * using FPU/SSE will offically have call save and restore functions
45 * exported by the kernel, if the really really have to use the state.
46 *
47 * - 32-bit windows does lazy FPU handling, I think, probably including
48 * lazying saving. The Windows Internals book states that it's a bad
49 * idea to use the FPU in kernel space. However, it looks like it will
50 * restore the FPU state of the current thread in case of a kernel \#NM.
51 * Interrupt handlers should be same as for 64-bit.
52 *
53 * - Darwin allows taking \#NM in kernel space, restoring current thread's
54 * state if I read the code correctly. It saves the FPU state of the
55 * outgoing thread, and uses CR0.TS to lazily load the state of the
56 * incoming one. No idea yet how the FPU is treated by interrupt
57 * handlers, i.e. whether they are allowed to disable the state or
58 * something.
59 *
60 * - Linux also allows \#NM in kernel space (don't know since when), and
61 * uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62 * loads the incoming unless configured to agressivly load it. Interrupt
63 * handlers can ask whether they're allowed to use the FPU, and may
64 * freely trash the state if Linux thinks it has saved the thread's state
65 * already. This is a problem.
66 *
67 * - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68 * context. When switching threads, the kernel will save the state of
69 * the outgoing thread and lazy load the incoming one using CR0.TS.
70 * There are a few routines in seeblk.s which uses the SSE unit in ring-0
71 * to do stuff, HAT are among the users. The routines there will
72 * manually clear CR0.TS and save the XMM registers they use only if
73 * CR0.TS was zero upon entry. They will skip it when not, because as
74 * mentioned above, the FPU state is saved when switching away from a
75 * thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76 * preserve. This is a problem if we restore CR0.TS to 1 after loading
77 * the guest state.
78 *
79 * - FreeBSD - no idea yet.
80 *
81 * - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82 * possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83 * FPU states.
84 *
85 * Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86 * saving and restoring the host and guest states. The motivation for this
87 * change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88 *
89 * Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90 * state and only restore it once we've restore the host FPU state. This has the
91 * accidental side effect of triggering Solaris to preserve XMM registers in
92 * sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93 * the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94 *
95 *
96 * @section sec_cpum_logging Logging Level Assignments.
97 *
98 * Following log level assignments:
99 * - Log6 is used for FPU state management.
100 * - Log7 is used for FPU state actualization.
101 *
102 */
103
104
105/*********************************************************************************************************************************
106* Header Files *
107*********************************************************************************************************************************/
108#define LOG_GROUP LOG_GROUP_CPUM
109#include <VBox/vmm/cpum.h>
110#include <VBox/vmm/cpumdis.h>
111#include <VBox/vmm/cpumctx-v1_6.h>
112#include <VBox/vmm/pgm.h>
113#include <VBox/vmm/apic.h>
114#include <VBox/vmm/mm.h>
115#include <VBox/vmm/em.h>
116#include <VBox/vmm/selm.h>
117#include <VBox/vmm/dbgf.h>
118#include <VBox/vmm/patm.h>
119#include <VBox/vmm/hm.h>
120#include <VBox/vmm/ssm.h>
121#include "CPUMInternal.h"
122#include <VBox/vmm/vm.h>
123
124#include <VBox/param.h>
125#include <VBox/dis.h>
126#include <VBox/err.h>
127#include <VBox/log.h>
128#include <iprt/asm-amd64-x86.h>
129#include <iprt/assert.h>
130#include <iprt/cpuset.h>
131#include <iprt/mem.h>
132#include <iprt/mp.h>
133#include <iprt/string.h>
134
135
136/*********************************************************************************************************************************
137* Defined Constants And Macros *
138*********************************************************************************************************************************/
139/**
140 * This was used in the saved state up to the early life of version 14.
141 *
142 * It indicates that we may have some out-of-sync hidden segement registers.
143 * It is only relevant for raw-mode.
144 */
145#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
146
147
148/*********************************************************************************************************************************
149* Structures and Typedefs *
150*********************************************************************************************************************************/
151
152/**
153 * What kind of cpu info dump to perform.
154 */
155typedef enum CPUMDUMPTYPE
156{
157 CPUMDUMPTYPE_TERSE,
158 CPUMDUMPTYPE_DEFAULT,
159 CPUMDUMPTYPE_VERBOSE
160} CPUMDUMPTYPE;
161/** Pointer to a cpu info dump type. */
162typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
163
164
165/*********************************************************************************************************************************
166* Internal Functions *
167*********************************************************************************************************************************/
168static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
169static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
170static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
171static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
172static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
173static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
174static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178
179
180/*********************************************************************************************************************************
181* Global Variables *
182*********************************************************************************************************************************/
183/** Saved state field descriptors for CPUMCTX. */
184static const SSMFIELD g_aCpumCtxFields[] =
185{
186 SSMFIELD_ENTRY( CPUMCTX, rdi),
187 SSMFIELD_ENTRY( CPUMCTX, rsi),
188 SSMFIELD_ENTRY( CPUMCTX, rbp),
189 SSMFIELD_ENTRY( CPUMCTX, rax),
190 SSMFIELD_ENTRY( CPUMCTX, rbx),
191 SSMFIELD_ENTRY( CPUMCTX, rdx),
192 SSMFIELD_ENTRY( CPUMCTX, rcx),
193 SSMFIELD_ENTRY( CPUMCTX, rsp),
194 SSMFIELD_ENTRY( CPUMCTX, rflags),
195 SSMFIELD_ENTRY( CPUMCTX, rip),
196 SSMFIELD_ENTRY( CPUMCTX, r8),
197 SSMFIELD_ENTRY( CPUMCTX, r9),
198 SSMFIELD_ENTRY( CPUMCTX, r10),
199 SSMFIELD_ENTRY( CPUMCTX, r11),
200 SSMFIELD_ENTRY( CPUMCTX, r12),
201 SSMFIELD_ENTRY( CPUMCTX, r13),
202 SSMFIELD_ENTRY( CPUMCTX, r14),
203 SSMFIELD_ENTRY( CPUMCTX, r15),
204 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
205 SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
206 SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
207 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
208 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
209 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
210 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
211 SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
212 SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
213 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
214 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
215 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
216 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
217 SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
218 SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
219 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
220 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
221 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
222 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
223 SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
224 SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
225 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
226 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
227 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
228 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
229 SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
230 SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
231 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
232 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
233 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
234 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
235 SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
236 SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
237 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
238 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
239 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
240 SSMFIELD_ENTRY( CPUMCTX, cr0),
241 SSMFIELD_ENTRY( CPUMCTX, cr2),
242 SSMFIELD_ENTRY( CPUMCTX, cr3),
243 SSMFIELD_ENTRY( CPUMCTX, cr4),
244 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
245 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
246 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
247 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
248 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
249 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
250 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
251 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
252 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
253 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
254 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
255 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
256 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
257 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
258 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
259 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
260 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
261 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
262 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
263 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
264 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
265 SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
266 SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
267 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
268 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
269 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
270 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
271 SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
272 SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
273 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
274 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
275 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
276 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
277 SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
278 SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
279 SSMFIELD_ENTRY_TERM()
280};
281
282/** Saved state field descriptors for CPUMCTX. */
283static const SSMFIELD g_aCpumX87Fields[] =
284{
285 SSMFIELD_ENTRY( X86FXSTATE, FCW),
286 SSMFIELD_ENTRY( X86FXSTATE, FSW),
287 SSMFIELD_ENTRY( X86FXSTATE, FTW),
288 SSMFIELD_ENTRY( X86FXSTATE, FOP),
289 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
290 SSMFIELD_ENTRY( X86FXSTATE, CS),
291 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
292 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
293 SSMFIELD_ENTRY( X86FXSTATE, DS),
294 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
295 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
296 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
297 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
298 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
299 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
300 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
301 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
302 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
303 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
304 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
305 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
306 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
307 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
308 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
309 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
310 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
311 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
312 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
313 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
314 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
315 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
316 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
317 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
318 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
319 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
320 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
321 SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
322 SSMFIELD_ENTRY_TERM()
323};
324
325/** Saved state field descriptors for X86XSAVEHDR. */
326static const SSMFIELD g_aCpumXSaveHdrFields[] =
327{
328 SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
329 SSMFIELD_ENTRY_TERM()
330};
331
332/** Saved state field descriptors for X86XSAVEYMMHI. */
333static const SSMFIELD g_aCpumYmmHiFields[] =
334{
335 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
336 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
337 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
338 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
339 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
340 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
341 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
342 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
343 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
344 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
345 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
346 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
347 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
348 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
349 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
350 SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
351 SSMFIELD_ENTRY_TERM()
352};
353
354/** Saved state field descriptors for X86XSAVEBNDREGS. */
355static const SSMFIELD g_aCpumBndRegsFields[] =
356{
357 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
358 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
359 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
360 SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
361 SSMFIELD_ENTRY_TERM()
362};
363
364/** Saved state field descriptors for X86XSAVEBNDCFG. */
365static const SSMFIELD g_aCpumBndCfgFields[] =
366{
367 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
368 SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
369 SSMFIELD_ENTRY_TERM()
370};
371
372#if 0 /** @todo */
373/** Saved state field descriptors for X86XSAVEOPMASK. */
374static const SSMFIELD g_aCpumOpmaskFields[] =
375{
376 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
377 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
378 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
379 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
380 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
381 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
382 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
383 SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
384 SSMFIELD_ENTRY_TERM()
385};
386#endif
387
388/** Saved state field descriptors for X86XSAVEZMMHI256. */
389static const SSMFIELD g_aCpumZmmHi256Fields[] =
390{
391 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
392 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
393 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
394 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
395 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
396 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
397 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
398 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
399 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
400 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
401 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
402 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
403 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
404 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
405 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
406 SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
407 SSMFIELD_ENTRY_TERM()
408};
409
410/** Saved state field descriptors for X86XSAVEZMM16HI. */
411static const SSMFIELD g_aCpumZmm16HiFields[] =
412{
413 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
414 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
415 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
416 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
417 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
418 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
419 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
420 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
421 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
422 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
423 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
424 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
425 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
426 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
427 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
428 SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
429 SSMFIELD_ENTRY_TERM()
430};
431
432
433
434/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
435 * registeres changed. */
436static const SSMFIELD g_aCpumX87FieldsMem[] =
437{
438 SSMFIELD_ENTRY( X86FXSTATE, FCW),
439 SSMFIELD_ENTRY( X86FXSTATE, FSW),
440 SSMFIELD_ENTRY( X86FXSTATE, FTW),
441 SSMFIELD_ENTRY( X86FXSTATE, FOP),
442 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
443 SSMFIELD_ENTRY( X86FXSTATE, CS),
444 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
445 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
446 SSMFIELD_ENTRY( X86FXSTATE, DS),
447 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
448 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
449 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
450 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
451 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
452 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
453 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
454 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
455 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
456 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
457 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
458 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
459 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
460 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
461 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
462 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
463 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
464 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
465 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
466 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
467 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
468 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
469 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
470 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
471 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
472 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
473 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
474 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
475 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
476};
477
478/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
479 * registeres changed. */
480static const SSMFIELD g_aCpumCtxFieldsMem[] =
481{
482 SSMFIELD_ENTRY( CPUMCTX, rdi),
483 SSMFIELD_ENTRY( CPUMCTX, rsi),
484 SSMFIELD_ENTRY( CPUMCTX, rbp),
485 SSMFIELD_ENTRY( CPUMCTX, rax),
486 SSMFIELD_ENTRY( CPUMCTX, rbx),
487 SSMFIELD_ENTRY( CPUMCTX, rdx),
488 SSMFIELD_ENTRY( CPUMCTX, rcx),
489 SSMFIELD_ENTRY( CPUMCTX, rsp),
490 SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
491 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
492 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
493 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
494 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
495 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
496 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
497 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
498 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
499 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
500 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
501 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
502 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
503 SSMFIELD_ENTRY( CPUMCTX, rflags),
504 SSMFIELD_ENTRY( CPUMCTX, rip),
505 SSMFIELD_ENTRY( CPUMCTX, r8),
506 SSMFIELD_ENTRY( CPUMCTX, r9),
507 SSMFIELD_ENTRY( CPUMCTX, r10),
508 SSMFIELD_ENTRY( CPUMCTX, r11),
509 SSMFIELD_ENTRY( CPUMCTX, r12),
510 SSMFIELD_ENTRY( CPUMCTX, r13),
511 SSMFIELD_ENTRY( CPUMCTX, r14),
512 SSMFIELD_ENTRY( CPUMCTX, r15),
513 SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
514 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
515 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
516 SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
517 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
518 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
519 SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
520 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
521 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
522 SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
523 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
524 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
525 SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
526 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
527 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
528 SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
529 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
530 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
531 SSMFIELD_ENTRY( CPUMCTX, cr0),
532 SSMFIELD_ENTRY( CPUMCTX, cr2),
533 SSMFIELD_ENTRY( CPUMCTX, cr3),
534 SSMFIELD_ENTRY( CPUMCTX, cr4),
535 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
536 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
537 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
538 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
539 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
540 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
541 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
542 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
543 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
544 SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
545 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
546 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
547 SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
548 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
549 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
550 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
551 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
552 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
553 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
554 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
555 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
556 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
557 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
558 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
559 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
560 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
561 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
562 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
563 SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
564 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
565 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
566 SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
567 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
568 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
569 SSMFIELD_ENTRY_TERM()
570};
571
572/** Saved state field descriptors for CPUMCTX_VER1_6. */
573static const SSMFIELD g_aCpumX87FieldsV16[] =
574{
575 SSMFIELD_ENTRY( X86FXSTATE, FCW),
576 SSMFIELD_ENTRY( X86FXSTATE, FSW),
577 SSMFIELD_ENTRY( X86FXSTATE, FTW),
578 SSMFIELD_ENTRY( X86FXSTATE, FOP),
579 SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
580 SSMFIELD_ENTRY( X86FXSTATE, CS),
581 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
582 SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
583 SSMFIELD_ENTRY( X86FXSTATE, DS),
584 SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
585 SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
586 SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
587 SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
588 SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
589 SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
590 SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
591 SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
592 SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
593 SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
594 SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
595 SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
596 SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
597 SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
598 SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
599 SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
600 SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
601 SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
602 SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
603 SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
604 SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
605 SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
606 SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
607 SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
608 SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
609 SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
610 SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
611 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
612 SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
613 SSMFIELD_ENTRY_TERM()
614};
615
616/** Saved state field descriptors for CPUMCTX_VER1_6. */
617static const SSMFIELD g_aCpumCtxFieldsV16[] =
618{
619 SSMFIELD_ENTRY( CPUMCTX, rdi),
620 SSMFIELD_ENTRY( CPUMCTX, rsi),
621 SSMFIELD_ENTRY( CPUMCTX, rbp),
622 SSMFIELD_ENTRY( CPUMCTX, rax),
623 SSMFIELD_ENTRY( CPUMCTX, rbx),
624 SSMFIELD_ENTRY( CPUMCTX, rdx),
625 SSMFIELD_ENTRY( CPUMCTX, rcx),
626 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
627 SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
628 SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
629 SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /*rsp_notused*/),
630 SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
631 SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
632 SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
633 SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
634 SSMFIELD_ENTRY( CPUMCTX, es.Sel),
635 SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
636 SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
637 SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
638 SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
639 SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
640 SSMFIELD_ENTRY( CPUMCTX, rflags),
641 SSMFIELD_ENTRY( CPUMCTX, rip),
642 SSMFIELD_ENTRY( CPUMCTX, r8),
643 SSMFIELD_ENTRY( CPUMCTX, r9),
644 SSMFIELD_ENTRY( CPUMCTX, r10),
645 SSMFIELD_ENTRY( CPUMCTX, r11),
646 SSMFIELD_ENTRY( CPUMCTX, r12),
647 SSMFIELD_ENTRY( CPUMCTX, r13),
648 SSMFIELD_ENTRY( CPUMCTX, r14),
649 SSMFIELD_ENTRY( CPUMCTX, r15),
650 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
651 SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
652 SSMFIELD_ENTRY( CPUMCTX, es.Attr),
653 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
654 SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
655 SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
656 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
657 SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
658 SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
659 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
660 SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
661 SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
662 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
663 SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
664 SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
665 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
666 SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
667 SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
668 SSMFIELD_ENTRY( CPUMCTX, cr0),
669 SSMFIELD_ENTRY( CPUMCTX, cr2),
670 SSMFIELD_ENTRY( CPUMCTX, cr3),
671 SSMFIELD_ENTRY( CPUMCTX, cr4),
672 SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
673 SSMFIELD_ENTRY( CPUMCTX, dr[0]),
674 SSMFIELD_ENTRY( CPUMCTX, dr[1]),
675 SSMFIELD_ENTRY( CPUMCTX, dr[2]),
676 SSMFIELD_ENTRY( CPUMCTX, dr[3]),
677 SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
678 SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
679 SSMFIELD_ENTRY( CPUMCTX, dr[6]),
680 SSMFIELD_ENTRY( CPUMCTX, dr[7]),
681 SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
682 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
683 SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
684 SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
685 SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
686 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
687 SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
688 SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
689 SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
690 SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
691 SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
692 SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
693 SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
694 SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
695 SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
696 SSMFIELD_ENTRY( CPUMCTX, msrEFER),
697 SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
698 SSMFIELD_ENTRY( CPUMCTX, msrPAT),
699 SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
700 SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
701 SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
702 SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
703 SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
704 SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
705 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
706 SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
707 SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
708 SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
709 SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
710 SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
711 SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
712 SSMFIELD_ENTRY_TERM()
713};
714
715
716/**
717 * Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
718 *
719 * AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
720 * (last instruction pointer, last data pointer, last opcode) except when the ES
721 * bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
722 * clear these registers there is potential, local FPU leakage from a process
723 * using the FPU to another.
724 *
725 * See AMD Instruction Reference for FXSAVE, FXRSTOR.
726 *
727 * @param pVM The cross context VM structure.
728 */
729static void cpumR3CheckLeakyFpu(PVM pVM)
730{
731 uint32_t u32CpuVersion = ASMCpuId_EAX(1);
732 uint32_t const u32Family = u32CpuVersion >> 8;
733 if ( u32Family >= 6 /* K7 and higher */
734 && ASMIsAmdCpu())
735 {
736 uint32_t cExt = ASMCpuId_EAX(0x80000000);
737 if (ASMIsValidExtRange(cExt))
738 {
739 uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
740 if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
741 {
742 for (VMCPUID i = 0; i < pVM->cCpus; i++)
743 pVM->aCpus[i].cpum.s.fUseFlags |= CPUM_USE_FFXSR_LEAKY;
744 Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
745 }
746 }
747 }
748}
749
750
751/**
752 * Initializes the CPUM.
753 *
754 * @returns VBox status code.
755 * @param pVM The cross context VM structure.
756 */
757VMMR3DECL(int) CPUMR3Init(PVM pVM)
758{
759 LogFlow(("CPUMR3Init\n"));
760
761 /*
762 * Assert alignment, sizes and tables.
763 */
764 AssertCompileMemberAlignment(VM, cpum.s, 32);
765 AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
766 AssertCompileSizeAlignment(CPUMCTX, 64);
767 AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
768 AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
769 AssertCompileMemberAlignment(VM, cpum, 64);
770 AssertCompileMemberAlignment(VM, aCpus, 64);
771 AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
772 AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
773#ifdef VBOX_STRICT
774 int rc2 = cpumR3MsrStrictInitChecks();
775 AssertRCReturn(rc2, rc2);
776#endif
777
778 /*
779 * Initialize offsets.
780 */
781
782 /* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
783 pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
784 Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
785
786
787 /* Calculate the offset from CPUMCPU to CPUM. */
788 for (VMCPUID i = 0; i < pVM->cCpus; i++)
789 {
790 PVMCPU pVCpu = &pVM->aCpus[i];
791
792 pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
793 Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
794 }
795
796 /*
797 * Gather info about the host CPU.
798 */
799 if (!ASMHasCpuId())
800 {
801 Log(("The CPU doesn't support CPUID!\n"));
802 return VERR_UNSUPPORTED_CPU;
803 }
804
805 PCPUMCPUIDLEAF paLeaves;
806 uint32_t cLeaves;
807 int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
808 AssertLogRelRCReturn(rc, rc);
809
810 rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
811 RTMemFree(paLeaves);
812 AssertLogRelRCReturn(rc, rc);
813 pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
814
815 /*
816 * Check that the CPU supports the minimum features we require.
817 */
818 if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
819 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
820 if (!pVM->cpum.s.HostFeatures.fMmx)
821 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
822 if (!pVM->cpum.s.HostFeatures.fTsc)
823 return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
824
825 /*
826 * Setup the CR4 AND and OR masks used in the raw-mode switcher.
827 */
828 pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
829 pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
830
831 /*
832 * Figure out which XSAVE/XRSTOR features are available on the host.
833 */
834 uint64_t fXcr0Host = 0;
835 uint64_t fXStateHostMask = 0;
836 if ( pVM->cpum.s.HostFeatures.fXSaveRstor
837 && pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
838 {
839 fXStateHostMask = fXcr0Host = ASMGetXcr0();
840 fXStateHostMask &= XSAVE_C_X87 | XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI;
841 AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 | XSAVE_C_SSE)) == (XSAVE_C_X87 | XSAVE_C_SSE),
842 ("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
843 }
844 pVM->cpum.s.fXStateHostMask = fXStateHostMask;
845 if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
846 fXStateHostMask = 0;
847 LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
848 pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
849
850 /*
851 * Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
852 */
853 uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
854 cbMaxXState = RT_ALIGN(cbMaxXState, 128);
855 AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
856
857 uint8_t *pbXStates;
858 rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
859 MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
860 AssertLogRelRCReturn(rc, rc);
861
862 for (VMCPUID i = 0; i < pVM->cCpus; i++)
863 {
864 PVMCPU pVCpu = &pVM->aCpus[i];
865
866 pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
867 pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
868 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
869 pbXStates += cbMaxXState;
870
871 pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
872 pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
873 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
874 pbXStates += cbMaxXState;
875
876 pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
877 pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
878 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
879 pbXStates += cbMaxXState;
880
881 pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
882 }
883
884 /*
885 * Setup hypervisor startup values.
886 */
887
888 /*
889 * Register saved state data item.
890 */
891 rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
892 NULL, cpumR3LiveExec, NULL,
893 NULL, cpumR3SaveExec, NULL,
894 cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
895 if (RT_FAILURE(rc))
896 return rc;
897
898 /*
899 * Register info handlers and registers with the debugger facility.
900 */
901 DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
902 &cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
903 DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
904 &cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
905 DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
906 &cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
907 DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
908 &cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
909 DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
910 &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
911 DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
912
913 rc = cpumR3DbgInit(pVM);
914 if (RT_FAILURE(rc))
915 return rc;
916
917 /*
918 * Check if we need to workaround partial/leaky FPU handling.
919 */
920 cpumR3CheckLeakyFpu(pVM);
921
922 /*
923 * Initialize the Guest CPUID and MSR states.
924 */
925 rc = cpumR3InitCpuIdAndMsrs(pVM);
926 if (RT_FAILURE(rc))
927 return rc;
928 CPUMR3Reset(pVM);
929 return VINF_SUCCESS;
930}
931
932
933/**
934 * Applies relocations to data and code managed by this
935 * component. This function will be called at init and
936 * whenever the VMM need to relocate it self inside the GC.
937 *
938 * The CPUM will update the addresses used by the switcher.
939 *
940 * @param pVM The cross context VM structure.
941 */
942VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
943{
944 LogFlow(("CPUMR3Relocate\n"));
945
946 pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
947 pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
948
949 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
950 {
951 PVMCPU pVCpu = &pVM->aCpus[iCpu];
952 pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
953 pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
954 pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
955
956 /* Recheck the guest DRx values in raw-mode. */
957 CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
958 }
959}
960
961
962/**
963 * Apply late CPUM property changes based on the fHWVirtEx setting
964 *
965 * @param pVM The cross context VM structure.
966 * @param fHWVirtExEnabled HWVirtEx enabled/disabled
967 */
968VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
969{
970 /*
971 * Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
972 * If we miss to patch a cpuid(0).eax then Linux tries to determine the number
973 * of processors from (cpuid(4).eax >> 26) + 1.
974 *
975 * Note: this code is obsolete, but let's keep it here for reference.
976 * Purpose is valid when we artificially cap the max std id to less than 4.
977 */
978 if (!fHWVirtExEnabled)
979 {
980 Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
981 || pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
982 pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
983 }
984}
985
986/**
987 * Terminates the CPUM.
988 *
989 * Termination means cleaning up and freeing all resources,
990 * the VM it self is at this point powered off or suspended.
991 *
992 * @returns VBox status code.
993 * @param pVM The cross context VM structure.
994 */
995VMMR3DECL(int) CPUMR3Term(PVM pVM)
996{
997#ifdef VBOX_WITH_CRASHDUMP_MAGIC
998 for (VMCPUID i = 0; i < pVM->cCpus; i++)
999 {
1000 PVMCPU pVCpu = &pVM->aCpus[i];
1001 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1002
1003 memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1004 pVCpu->cpum.s.uMagic = 0;
1005 pCtx->dr[5] = 0;
1006 }
1007#else
1008 NOREF(pVM);
1009#endif
1010 return VINF_SUCCESS;
1011}
1012
1013
1014/**
1015 * Resets a virtual CPU.
1016 *
1017 * Used by CPUMR3Reset and CPU hot plugging.
1018 *
1019 * @param pVM The cross context VM structure.
1020 * @param pVCpu The cross context virtual CPU structure of the CPU that is
1021 * being reset. This may differ from the current EMT.
1022 */
1023VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1024{
1025 /** @todo anything different for VCPU > 0? */
1026 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1027
1028 /*
1029 * Initialize everything to ZERO first.
1030 */
1031 uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1032
1033 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1034 AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1035 memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1036
1037 pVCpu->cpum.s.fUseFlags = fUseFlags;
1038
1039 pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
1040 pCtx->eip = 0x0000fff0;
1041 pCtx->edx = 0x00000600; /* P6 processor */
1042 pCtx->eflags.Bits.u1Reserved0 = 1;
1043
1044 pCtx->cs.Sel = 0xf000;
1045 pCtx->cs.ValidSel = 0xf000;
1046 pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1047 pCtx->cs.u64Base = UINT64_C(0xffff0000);
1048 pCtx->cs.u32Limit = 0x0000ffff;
1049 pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1050 pCtx->cs.Attr.n.u1Present = 1;
1051 pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1052
1053 pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1054 pCtx->ds.u32Limit = 0x0000ffff;
1055 pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1056 pCtx->ds.Attr.n.u1Present = 1;
1057 pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1058
1059 pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1060 pCtx->es.u32Limit = 0x0000ffff;
1061 pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1062 pCtx->es.Attr.n.u1Present = 1;
1063 pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1064
1065 pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1066 pCtx->fs.u32Limit = 0x0000ffff;
1067 pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1068 pCtx->fs.Attr.n.u1Present = 1;
1069 pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1070
1071 pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1072 pCtx->gs.u32Limit = 0x0000ffff;
1073 pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1074 pCtx->gs.Attr.n.u1Present = 1;
1075 pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1076
1077 pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1078 pCtx->ss.u32Limit = 0x0000ffff;
1079 pCtx->ss.Attr.n.u1Present = 1;
1080 pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1081 pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1082
1083 pCtx->idtr.cbIdt = 0xffff;
1084 pCtx->gdtr.cbGdt = 0xffff;
1085
1086 pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1087 pCtx->ldtr.u32Limit = 0xffff;
1088 pCtx->ldtr.Attr.n.u1Present = 1;
1089 pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1090
1091 pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1092 pCtx->tr.u32Limit = 0xffff;
1093 pCtx->tr.Attr.n.u1Present = 1;
1094 pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1095
1096 pCtx->dr[6] = X86_DR6_INIT_VAL;
1097 pCtx->dr[7] = X86_DR7_INIT_VAL;
1098
1099 PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1100 pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1101 pFpuCtx->FCW = 0x37f;
1102
1103 /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1104 IA-32 Processor States Following Power-up, Reset, or INIT */
1105 pFpuCtx->MXCSR = 0x1F80;
1106 pFpuCtx->MXCSR_MASK = 0xffff; /** @todo REM always changed this for us. Should probably check if the HW really
1107 supports all bits, since a zero value here should be read as 0xffbf. */
1108 pCtx->aXcr[0] = XSAVE_C_X87;
1109 if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1110 {
1111 /* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1112 as we don't know what happened before. (Bother optimize later?) */
1113 pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 | XSAVE_C_SSE;
1114 }
1115
1116 /*
1117 * MSRs.
1118 */
1119 /* Init PAT MSR */
1120 pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1121
1122 /* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1123 * The Intel docs don't mention it. */
1124 Assert(!pCtx->msrEFER);
1125
1126 /* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1127 is supposed to be here, just trying provide useful/sensible values. */
1128 PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1129 if (pRange)
1130 {
1131 pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1132 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1133 | (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1134 | MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1135 pRange->fWrIgnMask |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1136 | MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1137 pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1138 }
1139
1140 /** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1141
1142 /** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1143 * called from each EMT while we're getting called by CPUMR3Reset()
1144 * iteratively on the same thread. Fix later. */
1145#if 0 /** @todo r=bird: This we will do in TM, not here. */
1146 /* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1147 CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1148#endif
1149
1150
1151 /* C-state control. Guesses. */
1152 pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /*C1*/ | RT_BIT_32(25) | RT_BIT_32(26) | RT_BIT_32(27) | RT_BIT_32(28);
1153
1154 /*
1155 * Hardware virtualization state.
1156 */
1157 memset(&pCtx->hwvirt, 0, sizeof(pCtx->hwvirt));
1158 /* SVM. */
1159 pCtx->hwvirt.svm.fGif = 1;
1160}
1161
1162
1163/**
1164 * Resets the CPU.
1165 *
1166 * @returns VINF_SUCCESS.
1167 * @param pVM The cross context VM structure.
1168 */
1169VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1170{
1171 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1172 {
1173 CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1174
1175#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1176 PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1177
1178 /* Magic marker for searching in crash dumps. */
1179 strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1180 pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1181 pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1182#endif
1183 }
1184}
1185
1186
1187
1188
1189/**
1190 * Pass 0 live exec callback.
1191 *
1192 * @returns VINF_SSM_DONT_CALL_AGAIN.
1193 * @param pVM The cross context VM structure.
1194 * @param pSSM The saved state handle.
1195 * @param uPass The pass (0).
1196 */
1197static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1198{
1199 AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1200 cpumR3SaveCpuId(pVM, pSSM);
1201 return VINF_SSM_DONT_CALL_AGAIN;
1202}
1203
1204
1205/**
1206 * Execute state save operation.
1207 *
1208 * @returns VBox status code.
1209 * @param pVM The cross context VM structure.
1210 * @param pSSM SSM operation handle.
1211 */
1212static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1213{
1214 /*
1215 * Save.
1216 */
1217 SSMR3PutU32(pSSM, pVM->cCpus);
1218 SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1219 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1220 {
1221 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1222
1223 SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1224
1225 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1226 SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1227 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1228 if (pGstCtx->fXStateMask != 0)
1229 SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1230 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1231 {
1232 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1233 SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1234 }
1235 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1236 {
1237 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1238 SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1239 }
1240 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1241 {
1242 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1243 SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1244 }
1245 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1246 {
1247 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1248 SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1249 }
1250 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1251 {
1252 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1253 SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1254 }
1255
1256 SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1257 SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1258 AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1259 SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1260 }
1261
1262 cpumR3SaveCpuId(pVM, pSSM);
1263 return VINF_SUCCESS;
1264}
1265
1266
1267/**
1268 * @callback_method_impl{FNSSMINTLOADPREP}
1269 */
1270static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1271{
1272 NOREF(pSSM);
1273 pVM->cpum.s.fPendingRestore = true;
1274 return VINF_SUCCESS;
1275}
1276
1277
1278/**
1279 * @callback_method_impl{FNSSMINTLOADEXEC}
1280 */
1281static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1282{
1283 int rc; /* Only for AssertRCReturn use. */
1284
1285 /*
1286 * Validate version.
1287 */
1288 if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1289 && uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1290 && uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1291 && uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1292 && uVersion != CPUM_SAVED_STATE_VERSION_MEM
1293 && uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1294 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1295 && uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1296 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1297 && uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1298 && uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1299 {
1300 AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1301 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1302 }
1303
1304 if (uPass == SSM_PASS_FINAL)
1305 {
1306 /*
1307 * Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1308 * really old SSM file versions.)
1309 */
1310 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1311 SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1312 else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1313 SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1314
1315 /*
1316 * Figure x86 and ctx field definitions to use for older states.
1317 */
1318 uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1319 PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1320 PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1321 if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1322 {
1323 paCpumCtx1Fields = g_aCpumX87FieldsV16;
1324 paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1325 }
1326 else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1327 {
1328 paCpumCtx1Fields = g_aCpumX87FieldsMem;
1329 paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1330 }
1331
1332 /*
1333 * The hyper state used to preceed the CPU count. Starting with
1334 * XSAVE it was moved down till after we've got the count.
1335 */
1336 if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1337 {
1338 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1339 {
1340 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1341 X86FXSTATE Ign;
1342 SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1343 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1344 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1345 SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1346 fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1347 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1348 pVCpu->cpum.s.Hyper.rsp = uRSP;
1349 }
1350 }
1351
1352 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1353 {
1354 uint32_t cCpus;
1355 rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1356 AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1357 VERR_SSM_UNEXPECTED_DATA);
1358 }
1359 AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1360 || pVM->cCpus == 1,
1361 ("cCpus=%u\n", pVM->cCpus),
1362 VERR_SSM_UNEXPECTED_DATA);
1363
1364 uint32_t cbMsrs = 0;
1365 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1366 {
1367 rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1368 AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1369 VERR_SSM_UNEXPECTED_DATA);
1370 AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1371 VERR_SSM_UNEXPECTED_DATA);
1372 }
1373
1374 /*
1375 * Do the per-CPU restoring.
1376 */
1377 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1378 {
1379 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1380 PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1381
1382 if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1383 {
1384 /*
1385 * The XSAVE saved state layout moved the hyper state down here.
1386 */
1387 uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1388 uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1389 rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1390 pVCpu->cpum.s.Hyper.cr3 = uCR3;
1391 pVCpu->cpum.s.Hyper.rsp = uRSP;
1392 AssertRCReturn(rc, rc);
1393
1394 /*
1395 * Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1396 */
1397 rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1398 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1399 AssertRCReturn(rc, rc);
1400
1401 /* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1402 if (pGstCtx->fXStateMask != 0)
1403 {
1404 AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1405 ("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1406 pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1407 VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1408 AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1409 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1410 AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1411 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1412 AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1413 || (pGstCtx->fXStateMask & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1414 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1415 ("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1416 }
1417
1418 /* Check that the XCR0 mask is valid (invalid results in #GP). */
1419 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1420 if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1421 {
1422 AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask | XSAVE_C_X87)),
1423 ("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1424 VERR_CPUM_INVALID_XCR0);
1425 AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1426 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1427 AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM)) != XSAVE_C_YMM,
1428 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1429 AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI)) == 0
1430 || (pGstCtx->aXcr[0] & (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI))
1431 == (XSAVE_C_SSE | XSAVE_C_YMM | XSAVE_C_OPMASK | XSAVE_C_ZMM_HI256 | XSAVE_C_ZMM_16HI),
1432 ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1433 }
1434
1435 /* Check that the XCR1 is zero, as we don't implement it yet. */
1436 AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1437
1438 /*
1439 * Restore the individual extended state components we support.
1440 */
1441 if (pGstCtx->fXStateMask != 0)
1442 {
1443 rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1444 0, g_aCpumXSaveHdrFields, NULL);
1445 AssertRCReturn(rc, rc);
1446 AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1447 ("bmXState=%#RX64 fXStateMask=%#RX64\n",
1448 pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1449 VERR_CPUM_INVALID_XSAVE_HDR);
1450 }
1451 if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1452 {
1453 PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1454 SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1455 }
1456 if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1457 {
1458 PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1459 SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1460 }
1461 if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1462 {
1463 PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1464 SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1465 }
1466 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1467 {
1468 PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1469 SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1470 }
1471 if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1472 {
1473 PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1474 SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1475 }
1476 }
1477 else
1478 {
1479 /*
1480 * Pre XSAVE saved state.
1481 */
1482 SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1483 fLoad | SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1484 SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad | SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1485 }
1486
1487 /*
1488 * Restore a couple of flags and the MSRs.
1489 */
1490 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1491 SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1492
1493 rc = VINF_SUCCESS;
1494 if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1495 rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1496 else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1497 {
1498 SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1499 rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1500 }
1501 AssertRCReturn(rc, rc);
1502
1503 /* REM and other may have cleared must-be-one fields in DR6 and
1504 DR7, fix these. */
1505 pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK | X86_DR6_MBZ_MASK);
1506 pGstCtx->dr[6] |= X86_DR6_RA1_MASK;
1507 pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK | X86_DR7_MBZ_MASK);
1508 pGstCtx->dr[7] |= X86_DR7_RA1_MASK;
1509 }
1510
1511 /* Older states does not have the internal selector register flags
1512 and valid selector value. Supply those. */
1513 if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1514 {
1515 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1516 {
1517 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1518 bool const fValid = HMIsEnabled(pVM)
1519 || ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1520 && !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1521 PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1522 if (fValid)
1523 {
1524 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1525 {
1526 paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1527 paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1528 }
1529
1530 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1531 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1532 }
1533 else
1534 {
1535 for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1536 {
1537 paSelReg[iSelReg].fFlags = 0;
1538 paSelReg[iSelReg].ValidSel = 0;
1539 }
1540
1541 /* This might not be 104% correct, but I think it's close
1542 enough for all practical purposes... (REM always loaded
1543 LDTR registers.) */
1544 pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1545 pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1546 }
1547 pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1548 pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1549 }
1550 }
1551
1552 /* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1553 if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1554 && uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1555 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1556 pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1557
1558 /*
1559 * A quick sanity check.
1560 */
1561 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1562 {
1563 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1564 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1565 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1566 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1567 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1568 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1569 AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1570 }
1571 }
1572
1573 pVM->cpum.s.fPendingRestore = false;
1574
1575 /*
1576 * Guest CPUIDs.
1577 */
1578 if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1579 return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1580 return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1581}
1582
1583
1584/**
1585 * @callback_method_impl{FNSSMINTLOADDONE}
1586 */
1587static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1588{
1589 if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1590 return VINF_SUCCESS;
1591
1592 /* just check this since we can. */ /** @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1593 if (pVM->cpum.s.fPendingRestore)
1594 {
1595 LogRel(("CPUM: Missing state!\n"));
1596 return VERR_INTERNAL_ERROR_2;
1597 }
1598
1599 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1600 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1601 {
1602 PVMCPU pVCpu = &pVM->aCpus[idCpu];
1603
1604 /* Notify PGM of the NXE states in case they've changed. */
1605 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1606
1607 /* During init. this is done in CPUMR3InitCompleted(). */
1608 if (fSupportsLongMode)
1609 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
1610 }
1611 return VINF_SUCCESS;
1612}
1613
1614
1615/**
1616 * Checks if the CPUM state restore is still pending.
1617 *
1618 * @returns true / false.
1619 * @param pVM The cross context VM structure.
1620 */
1621VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1622{
1623 return pVM->cpum.s.fPendingRestore;
1624}
1625
1626
1627/**
1628 * Formats the EFLAGS value into mnemonics.
1629 *
1630 * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1631 * @param efl The EFLAGS value.
1632 */
1633static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1634{
1635 /*
1636 * Format the flags.
1637 */
1638 static const struct
1639 {
1640 const char *pszSet; const char *pszClear; uint32_t fFlag;
1641 } s_aFlags[] =
1642 {
1643 { "vip",NULL, X86_EFL_VIP },
1644 { "vif",NULL, X86_EFL_VIF },
1645 { "ac", NULL, X86_EFL_AC },
1646 { "vm", NULL, X86_EFL_VM },
1647 { "rf", NULL, X86_EFL_RF },
1648 { "nt", NULL, X86_EFL_NT },
1649 { "ov", "nv", X86_EFL_OF },
1650 { "dn", "up", X86_EFL_DF },
1651 { "ei", "di", X86_EFL_IF },
1652 { "tf", NULL, X86_EFL_TF },
1653 { "nt", "pl", X86_EFL_SF },
1654 { "nz", "zr", X86_EFL_ZF },
1655 { "ac", "na", X86_EFL_AF },
1656 { "po", "pe", X86_EFL_PF },
1657 { "cy", "nc", X86_EFL_CF },
1658 };
1659 char *psz = pszEFlags;
1660 for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1661 {
1662 const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1663 if (pszAdd)
1664 {
1665 strcpy(psz, pszAdd);
1666 psz += strlen(pszAdd);
1667 *psz++ = ' ';
1668 }
1669 }
1670 psz[-1] = '\0';
1671}
1672
1673
1674/**
1675 * Formats a full register dump.
1676 *
1677 * @param pVM The cross context VM structure.
1678 * @param pCtx The context to format.
1679 * @param pCtxCore The context core to format.
1680 * @param pHlp Output functions.
1681 * @param enmType The dump type.
1682 * @param pszPrefix Register name prefix.
1683 */
1684static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1685 const char *pszPrefix)
1686{
1687 NOREF(pVM);
1688
1689 /*
1690 * Format the EFLAGS.
1691 */
1692 uint32_t efl = pCtxCore->eflags.u32;
1693 char szEFlags[80];
1694 cpumR3InfoFormatFlags(&szEFlags[0], efl);
1695
1696 /*
1697 * Format the registers.
1698 */
1699 switch (enmType)
1700 {
1701 case CPUMDUMPTYPE_TERSE:
1702 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1703 pHlp->pfnPrintf(pHlp,
1704 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1705 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1706 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1707 "%sr14=%016RX64 %sr15=%016RX64\n"
1708 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1709 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1710 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1711 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1712 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1713 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1714 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1715 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1716 else
1717 pHlp->pfnPrintf(pHlp,
1718 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1719 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1720 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1721 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1722 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1723 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1724 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1725 break;
1726
1727 case CPUMDUMPTYPE_DEFAULT:
1728 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1729 pHlp->pfnPrintf(pHlp,
1730 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1731 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1732 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1733 "%sr14=%016RX64 %sr15=%016RX64\n"
1734 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1735 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1736 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1737 ,
1738 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1739 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1740 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1741 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1742 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1743 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1744 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1745 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1746 else
1747 pHlp->pfnPrintf(pHlp,
1748 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1749 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1750 "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1751 "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1752 ,
1753 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1754 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1755 pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1756 pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1757 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1758 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1759 break;
1760
1761 case CPUMDUMPTYPE_VERBOSE:
1762 if (CPUMIsGuestIn64BitCodeEx(pCtx))
1763 pHlp->pfnPrintf(pHlp,
1764 "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1765 "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1766 "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1767 "%sr14=%016RX64 %sr15=%016RX64\n"
1768 "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1769 "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1770 "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1771 "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1772 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1773 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1774 "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1775 "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1776 "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1777 "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1778 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1779 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1780 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1781 "%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1782 ,
1783 pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1784 pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1785 pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1786 pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1787 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1788 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1789 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1790 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1791 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1792 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1793 pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1794 pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1795 pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1796 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1797 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1798 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1799 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1800 else
1801 pHlp->pfnPrintf(pHlp,
1802 "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1803 "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1804 "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1805 "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1806 "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1807 "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1808 "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1809 "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1810 "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1811 "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1812 "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1813 "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1814 ,
1815 pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1816 pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1817 pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1818 pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1819 pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1820 pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1821 pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1822 pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1823 pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1824 pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1825 pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1826 pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1827
1828 pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1829 pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1830 pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1831 if (pCtx->CTX_SUFF(pXState))
1832 {
1833 PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1834 pHlp->pfnPrintf(pHlp,
1835 "%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1836 "%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1837 ,
1838 pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1839 pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1840 pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1841 pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1842 );
1843 /*
1844 * The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1845 * not (FP)R0-7 as Intel SDM suggests.
1846 */
1847 unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1848 for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1849 {
1850 unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1851 unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1852 char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1853 unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1854 uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1855 int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1856 iExponent -= 16383; /* subtract bias */
1857 /** @todo This isn't entirenly correct and needs more work! */
1858 pHlp->pfnPrintf(pHlp,
1859 "%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1860 pszPrefix, iST, pszPrefix, iFPR,
1861 pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1862 uTag, chSign, iInteger, u64Fraction, iExponent);
1863 if (pFpuCtx->aRegs[iST].au16[5] || pFpuCtx->aRegs[iST].au16[6] || pFpuCtx->aRegs[iST].au16[7])
1864 pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1865 pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1866 else
1867 pHlp->pfnPrintf(pHlp, "\n");
1868 }
1869
1870 /* XMM/YMM/ZMM registers. */
1871 if (pCtx->fXStateMask & XSAVE_C_YMM)
1872 {
1873 PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1874 if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1875 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1876 pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1877 pszPrefix, i, i < 10 ? " " : "",
1878 pYmmHiCtx->aYmmHi[i].au32[3],
1879 pYmmHiCtx->aYmmHi[i].au32[2],
1880 pYmmHiCtx->aYmmHi[i].au32[1],
1881 pYmmHiCtx->aYmmHi[i].au32[0],
1882 pFpuCtx->aXMM[i].au32[3],
1883 pFpuCtx->aXMM[i].au32[2],
1884 pFpuCtx->aXMM[i].au32[1],
1885 pFpuCtx->aXMM[i].au32[0]);
1886 else
1887 {
1888 PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1889 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1890 pHlp->pfnPrintf(pHlp,
1891 "%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1892 pszPrefix, i, i < 10 ? " " : "",
1893 pZmmHi256->aHi256Regs[i].au32[7],
1894 pZmmHi256->aHi256Regs[i].au32[6],
1895 pZmmHi256->aHi256Regs[i].au32[5],
1896 pZmmHi256->aHi256Regs[i].au32[4],
1897 pZmmHi256->aHi256Regs[i].au32[3],
1898 pZmmHi256->aHi256Regs[i].au32[2],
1899 pZmmHi256->aHi256Regs[i].au32[1],
1900 pZmmHi256->aHi256Regs[i].au32[0],
1901 pYmmHiCtx->aYmmHi[i].au32[3],
1902 pYmmHiCtx->aYmmHi[i].au32[2],
1903 pYmmHiCtx->aYmmHi[i].au32[1],
1904 pYmmHiCtx->aYmmHi[i].au32[0],
1905 pFpuCtx->aXMM[i].au32[3],
1906 pFpuCtx->aXMM[i].au32[2],
1907 pFpuCtx->aXMM[i].au32[1],
1908 pFpuCtx->aXMM[i].au32[0]);
1909
1910 PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1911 for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
1912 pHlp->pfnPrintf(pHlp,
1913 "%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1914 pszPrefix, i + 16,
1915 pZmm16Hi->aRegs[i].au32[15],
1916 pZmm16Hi->aRegs[i].au32[14],
1917 pZmm16Hi->aRegs[i].au32[13],
1918 pZmm16Hi->aRegs[i].au32[12],
1919 pZmm16Hi->aRegs[i].au32[11],
1920 pZmm16Hi->aRegs[i].au32[10],
1921 pZmm16Hi->aRegs[i].au32[9],
1922 pZmm16Hi->aRegs[i].au32[8],
1923 pZmm16Hi->aRegs[i].au32[7],
1924 pZmm16Hi->aRegs[i].au32[6],
1925 pZmm16Hi->aRegs[i].au32[5],
1926 pZmm16Hi->aRegs[i].au32[4],
1927 pZmm16Hi->aRegs[i].au32[3],
1928 pZmm16Hi->aRegs[i].au32[2],
1929 pZmm16Hi->aRegs[i].au32[1],
1930 pZmm16Hi->aRegs[i].au32[0]);
1931 }
1932 }
1933 else
1934 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1935 pHlp->pfnPrintf(pHlp,
1936 i & 1
1937 ? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
1938 : "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
1939 pszPrefix, i, i < 10 ? " " : "",
1940 pFpuCtx->aXMM[i].au32[3],
1941 pFpuCtx->aXMM[i].au32[2],
1942 pFpuCtx->aXMM[i].au32[1],
1943 pFpuCtx->aXMM[i].au32[0]);
1944
1945 if (pCtx->fXStateMask & XSAVE_C_OPMASK)
1946 {
1947 PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
1948 for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
1949 pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
1950 pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
1951 pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
1952 pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
1953 pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
1954 }
1955
1956 if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
1957 {
1958 PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1959 for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
1960 pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
1961 pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
1962 pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
1963 }
1964
1965 if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
1966 {
1967 PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1968 pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
1969 pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
1970 }
1971
1972 for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
1973 if (pFpuCtx->au32RsrvdRest[i])
1974 pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
1975 pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
1976 }
1977
1978 pHlp->pfnPrintf(pHlp,
1979 "%sEFER =%016RX64\n"
1980 "%sPAT =%016RX64\n"
1981 "%sSTAR =%016RX64\n"
1982 "%sCSTAR =%016RX64\n"
1983 "%sLSTAR =%016RX64\n"
1984 "%sSFMASK =%016RX64\n"
1985 "%sKERNELGSBASE =%016RX64\n",
1986 pszPrefix, pCtx->msrEFER,
1987 pszPrefix, pCtx->msrPAT,
1988 pszPrefix, pCtx->msrSTAR,
1989 pszPrefix, pCtx->msrCSTAR,
1990 pszPrefix, pCtx->msrLSTAR,
1991 pszPrefix, pCtx->msrSFMASK,
1992 pszPrefix, pCtx->msrKERNELGSBASE);
1993 break;
1994 }
1995}
1996
1997
1998/**
1999 * Display all cpu states and any other cpum info.
2000 *
2001 * @param pVM The cross context VM structure.
2002 * @param pHlp The info helper functions.
2003 * @param pszArgs Arguments, ignored.
2004 */
2005static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2006{
2007 cpumR3InfoGuest(pVM, pHlp, pszArgs);
2008 cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2009 cpumR3InfoHyper(pVM, pHlp, pszArgs);
2010 cpumR3InfoHost(pVM, pHlp, pszArgs);
2011}
2012
2013
2014/**
2015 * Parses the info argument.
2016 *
2017 * The argument starts with 'verbose', 'terse' or 'default' and then
2018 * continues with the comment string.
2019 *
2020 * @param pszArgs The pointer to the argument string.
2021 * @param penmType Where to store the dump type request.
2022 * @param ppszComment Where to store the pointer to the comment string.
2023 */
2024static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
2025{
2026 if (!pszArgs)
2027 {
2028 *penmType = CPUMDUMPTYPE_DEFAULT;
2029 *ppszComment = "";
2030 }
2031 else
2032 {
2033 if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2034 {
2035 pszArgs += 7;
2036 *penmType = CPUMDUMPTYPE_VERBOSE;
2037 }
2038 else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2039 {
2040 pszArgs += 5;
2041 *penmType = CPUMDUMPTYPE_TERSE;
2042 }
2043 else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2044 {
2045 pszArgs += 7;
2046 *penmType = CPUMDUMPTYPE_DEFAULT;
2047 }
2048 else
2049 *penmType = CPUMDUMPTYPE_DEFAULT;
2050 *ppszComment = RTStrStripL(pszArgs);
2051 }
2052}
2053
2054
2055/**
2056 * Display the guest cpu state.
2057 *
2058 * @param pVM The cross context VM structure.
2059 * @param pHlp The info helper functions.
2060 * @param pszArgs Arguments, ignored.
2061 */
2062static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2063{
2064 CPUMDUMPTYPE enmType;
2065 const char *pszComment;
2066 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2067
2068 PVMCPU pVCpu = VMMGetCpu(pVM);
2069 if (!pVCpu)
2070 pVCpu = &pVM->aCpus[0];
2071
2072 pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2073
2074 PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2075 cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2076}
2077
2078
2079/**
2080 * Display the current guest instruction
2081 *
2082 * @param pVM The cross context VM structure.
2083 * @param pHlp The info helper functions.
2084 * @param pszArgs Arguments, ignored.
2085 */
2086static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2087{
2088 NOREF(pszArgs);
2089
2090 PVMCPU pVCpu = VMMGetCpu(pVM);
2091 if (!pVCpu)
2092 pVCpu = &pVM->aCpus[0];
2093
2094 char szInstruction[256];
2095 szInstruction[0] = '\0';
2096 DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2097 pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2098}
2099
2100
2101/**
2102 * Display the hypervisor cpu state.
2103 *
2104 * @param pVM The cross context VM structure.
2105 * @param pHlp The info helper functions.
2106 * @param pszArgs Arguments, ignored.
2107 */
2108static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2109{
2110 PVMCPU pVCpu = VMMGetCpu(pVM);
2111 if (!pVCpu)
2112 pVCpu = &pVM->aCpus[0];
2113
2114 CPUMDUMPTYPE enmType;
2115 const char *pszComment;
2116 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2117 pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2118 cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2119 pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2120}
2121
2122
2123/**
2124 * Display the host cpu state.
2125 *
2126 * @param pVM The cross context VM structure.
2127 * @param pHlp The info helper functions.
2128 * @param pszArgs Arguments, ignored.
2129 */
2130static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2131{
2132 CPUMDUMPTYPE enmType;
2133 const char *pszComment;
2134 cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2135 pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2136
2137 PVMCPU pVCpu = VMMGetCpu(pVM);
2138 if (!pVCpu)
2139 pVCpu = &pVM->aCpus[0];
2140 PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2141
2142 /*
2143 * Format the EFLAGS.
2144 */
2145#if HC_ARCH_BITS == 32
2146 uint32_t efl = pCtx->eflags.u32;
2147#else
2148 uint64_t efl = pCtx->rflags;
2149#endif
2150 char szEFlags[80];
2151 cpumR3InfoFormatFlags(&szEFlags[0], efl);
2152
2153 /*
2154 * Format the registers.
2155 */
2156#if HC_ARCH_BITS == 32
2157 pHlp->pfnPrintf(pHlp,
2158 "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2159 "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2160 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2161 "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2162 "dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2163 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2164 ,
2165 /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
2166 /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2167 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2168 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3, pCtx->cr4,
2169 pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2170 (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2171 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2172#else
2173 pHlp->pfnPrintf(pHlp,
2174 "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2175 "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2176 "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2177 " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2178 "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2179 "r14=%016RX64 r15=%016RX64\n"
2180 "iopl=%d %31s\n"
2181 "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2182 "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2183 "cr4=%016RX64 ldtr=%04x tr=%04x\n"
2184 "dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2185 "dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2186 "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2187 "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2188 "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2189 ,
2190 /*pCtx->rax,*/ pCtx->rbx, /*pCtx->rcx,
2191 pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2192 /*pCtx->rip,*/ pCtx->rsp, pCtx->rbp,
2193 /*pCtx->r8, pCtx->r9,*/ pCtx->r10,
2194 pCtx->r11, pCtx->r12, pCtx->r13,
2195 pCtx->r14, pCtx->r15,
2196 X86_EFL_GET_IOPL(efl), szEFlags,
2197 pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2198 pCtx->cr0, /*pCtx->cr2,*/ pCtx->cr3,
2199 pCtx->cr4, pCtx->ldtr, pCtx->tr,
2200 pCtx->dr0, pCtx->dr1, pCtx->dr2,
2201 pCtx->dr3, pCtx->dr6, pCtx->dr7,
2202 pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2203 pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2204 pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2205#endif
2206}
2207
2208/**
2209 * Structure used when disassembling and instructions in DBGF.
2210 * This is used so the reader function can get the stuff it needs.
2211 */
2212typedef struct CPUMDISASSTATE
2213{
2214 /** Pointer to the CPU structure. */
2215 PDISCPUSTATE pCpu;
2216 /** Pointer to the VM. */
2217 PVM pVM;
2218 /** Pointer to the VMCPU. */
2219 PVMCPU pVCpu;
2220 /** Pointer to the first byte in the segment. */
2221 RTGCUINTPTR GCPtrSegBase;
2222 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
2223 RTGCUINTPTR GCPtrSegEnd;
2224 /** The size of the segment minus 1. */
2225 RTGCUINTPTR cbSegLimit;
2226 /** Pointer to the current page - R3 Ptr. */
2227 void const *pvPageR3;
2228 /** Pointer to the current page - GC Ptr. */
2229 RTGCPTR pvPageGC;
2230 /** The lock information that PGMPhysReleasePageMappingLock needs. */
2231 PGMPAGEMAPLOCK PageMapLock;
2232 /** Whether the PageMapLock is valid or not. */
2233 bool fLocked;
2234 /** 64 bits mode or not. */
2235 bool f64Bits;
2236} CPUMDISASSTATE, *PCPUMDISASSTATE;
2237
2238
2239/**
2240 * @callback_method_impl{FNDISREADBYTES}
2241 */
2242static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2243{
2244 PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2245 for (;;)
2246 {
2247 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2248
2249 /*
2250 * Need to update the page translation?
2251 */
2252 if ( !pState->pvPageR3
2253 || (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2254 {
2255 int rc = VINF_SUCCESS;
2256
2257 /* translate the address */
2258 pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2259 if ( !HMIsEnabled(pState->pVM)
2260 && MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2261 {
2262 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2263 if (!pState->pvPageR3)
2264 rc = VERR_INVALID_POINTER;
2265 }
2266 else
2267 {
2268 /* Release mapping lock previously acquired. */
2269 if (pState->fLocked)
2270 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2271 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2272 pState->fLocked = RT_SUCCESS_NP(rc);
2273 }
2274 if (RT_FAILURE(rc))
2275 {
2276 pState->pvPageR3 = NULL;
2277 return rc;
2278 }
2279 }
2280
2281 /*
2282 * Check the segment limit.
2283 */
2284 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2285 return VERR_OUT_OF_SELECTOR_BOUNDS;
2286
2287 /*
2288 * Calc how much we can read.
2289 */
2290 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2291 if (!pState->f64Bits)
2292 {
2293 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2294 if (cb > cbSeg && cbSeg)
2295 cb = cbSeg;
2296 }
2297 if (cb > cbMaxRead)
2298 cb = cbMaxRead;
2299
2300 /*
2301 * Read and advance or exit.
2302 */
2303 memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2304 offInstr += (uint8_t)cb;
2305 if (cb >= cbMinRead)
2306 {
2307 pDis->cbCachedInstr = offInstr;
2308 return VINF_SUCCESS;
2309 }
2310 cbMinRead -= (uint8_t)cb;
2311 cbMaxRead -= (uint8_t)cb;
2312 }
2313}
2314
2315
2316/**
2317 * Disassemble an instruction and return the information in the provided structure.
2318 *
2319 * @returns VBox status code.
2320 * @param pVM The cross context VM structure.
2321 * @param pVCpu The cross context virtual CPU structure.
2322 * @param pCtx Pointer to the guest CPU context.
2323 * @param GCPtrPC Program counter (relative to CS) to disassemble from.
2324 * @param pCpu Disassembly state.
2325 * @param pszPrefix String prefix for logging (debug only).
2326 *
2327 */
2328VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2329 const char *pszPrefix)
2330{
2331 CPUMDISASSTATE State;
2332 int rc;
2333
2334 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2335 State.pCpu = pCpu;
2336 State.pvPageGC = 0;
2337 State.pvPageR3 = NULL;
2338 State.pVM = pVM;
2339 State.pVCpu = pVCpu;
2340 State.fLocked = false;
2341 State.f64Bits = false;
2342
2343 /*
2344 * Get selector information.
2345 */
2346 DISCPUMODE enmDisCpuMode;
2347 if ( (pCtx->cr0 & X86_CR0_PE)
2348 && pCtx->eflags.Bits.u1VM == 0)
2349 {
2350 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2351 {
2352# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2353 CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2354# endif
2355 if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2356 return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2357 }
2358 State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2359 State.GCPtrSegBase = pCtx->cs.u64Base;
2360 State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2361 State.cbSegLimit = pCtx->cs.u32Limit;
2362 enmDisCpuMode = (State.f64Bits)
2363 ? DISCPUMODE_64BIT
2364 : pCtx->cs.Attr.n.u1DefBig
2365 ? DISCPUMODE_32BIT
2366 : DISCPUMODE_16BIT;
2367 }
2368 else
2369 {
2370 /* real or V86 mode */
2371 enmDisCpuMode = DISCPUMODE_16BIT;
2372 State.GCPtrSegBase = pCtx->cs.Sel * 16;
2373 State.GCPtrSegEnd = 0xFFFFFFFF;
2374 State.cbSegLimit = 0xFFFFFFFF;
2375 }
2376
2377 /*
2378 * Disassemble the instruction.
2379 */
2380 uint32_t cbInstr;
2381#ifndef LOG_ENABLED
2382 RT_NOREF_PV(pszPrefix);
2383 rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2384 if (RT_SUCCESS(rc))
2385 {
2386#else
2387 char szOutput[160];
2388 rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2389 pCpu, &cbInstr, szOutput, sizeof(szOutput));
2390 if (RT_SUCCESS(rc))
2391 {
2392 /* log it */
2393 if (pszPrefix)
2394 Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2395 else
2396 Log(("%s", szOutput));
2397#endif
2398 rc = VINF_SUCCESS;
2399 }
2400 else
2401 Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2402
2403 /* Release mapping lock acquired in cpumR3DisasInstrRead. */
2404 if (State.fLocked)
2405 PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2406
2407 return rc;
2408}
2409
2410
2411
2412/**
2413 * API for controlling a few of the CPU features found in CR4.
2414 *
2415 * Currently only X86_CR4_TSD is accepted as input.
2416 *
2417 * @returns VBox status code.
2418 *
2419 * @param pVM The cross context VM structure.
2420 * @param fOr The CR4 OR mask.
2421 * @param fAnd The CR4 AND mask.
2422 */
2423VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2424{
2425 AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2426 AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2427
2428 pVM->cpum.s.CR4.OrMask &= fAnd;
2429 pVM->cpum.s.CR4.OrMask |= fOr;
2430
2431 return VINF_SUCCESS;
2432}
2433
2434
2435/**
2436 * Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2437 *
2438 * Only REM should ever call this function!
2439 *
2440 * @returns The changed flags.
2441 * @param pVCpu The cross context virtual CPU structure.
2442 * @param puCpl Where to return the current privilege level (CPL).
2443 */
2444VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2445{
2446 Assert(!pVCpu->cpum.s.fRawEntered);
2447 Assert(!pVCpu->cpum.s.fRemEntered);
2448
2449 /*
2450 * Get the CPL first.
2451 */
2452 *puCpl = CPUMGetGuestCPL(pVCpu);
2453
2454 /*
2455 * Get and reset the flags.
2456 */
2457 uint32_t fFlags = pVCpu->cpum.s.fChanged;
2458 pVCpu->cpum.s.fChanged = 0;
2459
2460 /** @todo change the switcher to use the fChanged flags. */
2461 if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2462 {
2463 fFlags |= CPUM_CHANGED_FPU_REM;
2464 pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2465 }
2466
2467 pVCpu->cpum.s.fRemEntered = true;
2468 return fFlags;
2469}
2470
2471
2472/**
2473 * Leaves REM.
2474 *
2475 * @param pVCpu The cross context virtual CPU structure.
2476 * @param fNoOutOfSyncSels This is @c false if there are out of sync
2477 * registers.
2478 */
2479VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2480{
2481 Assert(!pVCpu->cpum.s.fRawEntered);
2482 Assert(pVCpu->cpum.s.fRemEntered);
2483
2484 RT_NOREF_PV(fNoOutOfSyncSels);
2485
2486 pVCpu->cpum.s.fRemEntered = false;
2487}
2488
2489
2490/**
2491 * Called when the ring-3 init phase completes.
2492 *
2493 * @returns VBox status code.
2494 * @param pVM The cross context VM structure.
2495 * @param enmWhat Which init phase.
2496 */
2497VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2498{
2499 switch (enmWhat)
2500 {
2501 case VMINITCOMPLETED_RING3:
2502 {
2503 /*
2504 * Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2505 * Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2506 */
2507 bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2508 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2509 {
2510 PVMCPU pVCpu = &pVM->aCpus[i];
2511 /* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2512 if (fSupportsLongMode)
2513 pVCpu->cpum.s.fUseFlags |= CPUM_USE_SUPPORTS_LONGMODE;
2514 }
2515
2516 cpumR3MsrRegStats(pVM);
2517 break;
2518 }
2519
2520 default:
2521 break;
2522 }
2523 return VINF_SUCCESS;
2524}
2525
2526
2527/**
2528 * Called when the ring-0 init phases completed.
2529 *
2530 * @param pVM The cross context VM structure.
2531 */
2532VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2533{
2534 /*
2535 * Log the cpuid.
2536 */
2537 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
2538 RTCPUSET OnlineSet;
2539 LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2540 (unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2541 RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2542 RTCPUID cCores = RTMpGetCoreCount();
2543 if (cCores)
2544 LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2545 LogRel(("************************* CPUID dump ************************\n"));
2546 DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2547 LogRel(("\n"));
2548 DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
2549 RTLogRelSetBuffering(fOldBuffered);
2550 LogRel(("******************** End of CPUID dump **********************\n"));
2551}
2552
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