CPUM.cpp@ 68155

Last change on this file since 68155 was 67924, checked in by vboxsync, 7 years ago
VMM/CPUM: Nested Hw.virt: Allocate the nested-guest VMCB (controls and state-save area) dynamically.
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1	/* $Id: CPUM.cpp 67924 2017-07-12 11:12:15Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for CPUMCTX. */
285	static const SSMFIELD g_aCpumX87Fields[] =
286	{
287	SSMFIELD_ENTRY( X86FXSTATE, FCW),
288	SSMFIELD_ENTRY( X86FXSTATE, FSW),
289	SSMFIELD_ENTRY( X86FXSTATE, FTW),
290	SSMFIELD_ENTRY( X86FXSTATE, FOP),
291	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
292	SSMFIELD_ENTRY( X86FXSTATE, CS),
293	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
294	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
295	SSMFIELD_ENTRY( X86FXSTATE, DS),
296	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
297	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
298	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
299	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
300	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
301	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
302	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
303	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
304	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
305	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
306	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
307	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
308	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
309	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
310	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
311	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
312	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
313	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
314	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
315	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
316	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
317	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
318	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
319	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
320	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
321	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
322	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
323	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
324	SSMFIELD_ENTRY_TERM()
325	};
326
327	/** Saved state field descriptors for X86XSAVEHDR. */
328	static const SSMFIELD g_aCpumXSaveHdrFields[] =
329	{
330	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
331	SSMFIELD_ENTRY_TERM()
332	};
333
334	/** Saved state field descriptors for X86XSAVEYMMHI. */
335	static const SSMFIELD g_aCpumYmmHiFields[] =
336	{
337	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
338	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
339	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
340	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
341	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
342	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
343	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
344	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
345	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
346	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
347	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
348	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
349	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
350	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
351	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
352	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
353	SSMFIELD_ENTRY_TERM()
354	};
355
356	/** Saved state field descriptors for X86XSAVEBNDREGS. */
357	static const SSMFIELD g_aCpumBndRegsFields[] =
358	{
359	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
360	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
361	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
362	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
363	SSMFIELD_ENTRY_TERM()
364	};
365
366	/** Saved state field descriptors for X86XSAVEBNDCFG. */
367	static const SSMFIELD g_aCpumBndCfgFields[] =
368	{
369	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
370	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
371	SSMFIELD_ENTRY_TERM()
372	};
373
374	#if 0 /** @todo */
375	/** Saved state field descriptors for X86XSAVEOPMASK. */
376	static const SSMFIELD g_aCpumOpmaskFields[] =
377	{
378	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
379	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
380	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
381	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
382	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
383	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
384	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
385	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
386	SSMFIELD_ENTRY_TERM()
387	};
388	#endif
389
390	/** Saved state field descriptors for X86XSAVEZMMHI256. */
391	static const SSMFIELD g_aCpumZmmHi256Fields[] =
392	{
393	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
394	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
395	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
396	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
397	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
398	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
399	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
400	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
401	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
402	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
403	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
404	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
405	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
406	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
407	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
408	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
409	SSMFIELD_ENTRY_TERM()
410	};
411
412	/** Saved state field descriptors for X86XSAVEZMM16HI. */
413	static const SSMFIELD g_aCpumZmm16HiFields[] =
414	{
415	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
416	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
417	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
418	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
419	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
420	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
421	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
422	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
423	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
424	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
425	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
426	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
427	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
428	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
429	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
430	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
431	SSMFIELD_ENTRY_TERM()
432	};
433
434
435
436	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
437	* registeres changed. */
438	static const SSMFIELD g_aCpumX87FieldsMem[] =
439	{
440	SSMFIELD_ENTRY( X86FXSTATE, FCW),
441	SSMFIELD_ENTRY( X86FXSTATE, FSW),
442	SSMFIELD_ENTRY( X86FXSTATE, FTW),
443	SSMFIELD_ENTRY( X86FXSTATE, FOP),
444	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
445	SSMFIELD_ENTRY( X86FXSTATE, CS),
446	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
447	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
448	SSMFIELD_ENTRY( X86FXSTATE, DS),
449	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
450	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
451	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
452	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
453	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
454	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
455	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
456	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
457	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
458	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
459	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
460	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
461	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
462	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
463	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
464	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
465	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
466	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
467	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
468	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
469	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
470	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
471	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
472	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
473	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
474	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
475	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
476	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
477	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
478	};
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumCtxFieldsMem[] =
483	{
484	SSMFIELD_ENTRY( CPUMCTX, rdi),
485	SSMFIELD_ENTRY( CPUMCTX, rsi),
486	SSMFIELD_ENTRY( CPUMCTX, rbp),
487	SSMFIELD_ENTRY( CPUMCTX, rax),
488	SSMFIELD_ENTRY( CPUMCTX, rbx),
489	SSMFIELD_ENTRY( CPUMCTX, rdx),
490	SSMFIELD_ENTRY( CPUMCTX, rcx),
491	SSMFIELD_ENTRY( CPUMCTX, rsp),
492	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
493	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
494	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
495	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
496	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
497	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
498	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
499	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
500	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
501	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
502	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
503	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
504	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
505	SSMFIELD_ENTRY( CPUMCTX, rflags),
506	SSMFIELD_ENTRY( CPUMCTX, rip),
507	SSMFIELD_ENTRY( CPUMCTX, r8),
508	SSMFIELD_ENTRY( CPUMCTX, r9),
509	SSMFIELD_ENTRY( CPUMCTX, r10),
510	SSMFIELD_ENTRY( CPUMCTX, r11),
511	SSMFIELD_ENTRY( CPUMCTX, r12),
512	SSMFIELD_ENTRY( CPUMCTX, r13),
513	SSMFIELD_ENTRY( CPUMCTX, r14),
514	SSMFIELD_ENTRY( CPUMCTX, r15),
515	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
516	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
517	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
518	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
519	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
520	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
521	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
522	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
523	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
524	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
525	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
526	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
527	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
528	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
529	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
530	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
531	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
532	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
533	SSMFIELD_ENTRY( CPUMCTX, cr0),
534	SSMFIELD_ENTRY( CPUMCTX, cr2),
535	SSMFIELD_ENTRY( CPUMCTX, cr3),
536	SSMFIELD_ENTRY( CPUMCTX, cr4),
537	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
538	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
539	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
540	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
541	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
542	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
543	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
544	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
545	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
546	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
547	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
548	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
549	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
550	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
551	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
552	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
553	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
554	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
555	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
556	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
557	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
558	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
559	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
560	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
561	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
562	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
563	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
564	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
565	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
571	SSMFIELD_ENTRY_TERM()
572	};
573
574	/** Saved state field descriptors for CPUMCTX_VER1_6. */
575	static const SSMFIELD g_aCpumX87FieldsV16[] =
576	{
577	SSMFIELD_ENTRY( X86FXSTATE, FCW),
578	SSMFIELD_ENTRY( X86FXSTATE, FSW),
579	SSMFIELD_ENTRY( X86FXSTATE, FTW),
580	SSMFIELD_ENTRY( X86FXSTATE, FOP),
581	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
582	SSMFIELD_ENTRY( X86FXSTATE, CS),
583	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
584	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
585	SSMFIELD_ENTRY( X86FXSTATE, DS),
586	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
587	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
588	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
589	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
590	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
591	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
592	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
593	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
594	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
595	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
596	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
597	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
598	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
599	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
600	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
601	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
602	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
603	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
604	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
605	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
606	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
607	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
608	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
609	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
610	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
611	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
612	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
613	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
614	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumCtxFieldsV16[] =
620	{
621	SSMFIELD_ENTRY( CPUMCTX, rdi),
622	SSMFIELD_ENTRY( CPUMCTX, rsi),
623	SSMFIELD_ENTRY( CPUMCTX, rbp),
624	SSMFIELD_ENTRY( CPUMCTX, rax),
625	SSMFIELD_ENTRY( CPUMCTX, rbx),
626	SSMFIELD_ENTRY( CPUMCTX, rdx),
627	SSMFIELD_ENTRY( CPUMCTX, rcx),
628	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
629	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
630	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
631	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
632	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
633	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
634	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
635	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
636	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
637	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
638	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
639	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
640	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
641	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
642	SSMFIELD_ENTRY( CPUMCTX, rflags),
643	SSMFIELD_ENTRY( CPUMCTX, rip),
644	SSMFIELD_ENTRY( CPUMCTX, r8),
645	SSMFIELD_ENTRY( CPUMCTX, r9),
646	SSMFIELD_ENTRY( CPUMCTX, r10),
647	SSMFIELD_ENTRY( CPUMCTX, r11),
648	SSMFIELD_ENTRY( CPUMCTX, r12),
649	SSMFIELD_ENTRY( CPUMCTX, r13),
650	SSMFIELD_ENTRY( CPUMCTX, r14),
651	SSMFIELD_ENTRY( CPUMCTX, r15),
652	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
653	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
654	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
655	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
656	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
657	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
658	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
659	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
660	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
661	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
662	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
663	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
664	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
665	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
666	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
667	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
668	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
669	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
670	SSMFIELD_ENTRY( CPUMCTX, cr0),
671	SSMFIELD_ENTRY( CPUMCTX, cr2),
672	SSMFIELD_ENTRY( CPUMCTX, cr3),
673	SSMFIELD_ENTRY( CPUMCTX, cr4),
674	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
675	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
676	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
677	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
678	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
679	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
680	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
681	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
682	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
683	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
684	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
685	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
686	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
687	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
688	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
689	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
690	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
691	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
692	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
693	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
694	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
695	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
696	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
697	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
698	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
699	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
700	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
701	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
702	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
703	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
704	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
705	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
706	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
707	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
708	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
709	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
710	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
711	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
712	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
713	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
714	SSMFIELD_ENTRY_TERM()
715	};
716
717
718	/**
719	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
720	*
721	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
722	* (last instruction pointer, last data pointer, last opcode) except when the ES
723	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
724	* clear these registers there is potential, local FPU leakage from a process
725	* using the FPU to another.
726	*
727	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
728	*
729	* @param pVM The cross context VM structure.
730	*/
731	static void cpumR3CheckLeakyFpu(PVM pVM)
732	{
733	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
734	uint32_t const u32Family = u32CpuVersion >> 8;
735	if ( u32Family >= 6 /* K7 and higher */
736	&& ASMIsAmdCpu())
737	{
738	uint32_t cExt = ASMCpuId_EAX(0x80000000);
739	if (ASMIsValidExtRange(cExt))
740	{
741	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
742	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
743	{
744	for (VMCPUID i = 0; i < pVM->cCpus; i++)
745	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
746	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
747	}
748	}
749	}
750	}
751
752
753	/**
754	* Frees memory allocated by cpumR3AllocHwVirtState().
755	*
756	* @param pVM The cross context VM structure.
757	*/
758	static void cpumR3FreeHwVirtState(PVM pVM)
759	{
760	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
761	for (VMCPUID i = 0; i < pVM->cCpus; i++)
762	{
763	PVMCPU pVCpu = &pVM->aCpus[i];
764	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
765	{
766	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
767	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
768	}
769
770	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
771	{
772	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
773	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
774	}
775
776	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
777	{
778	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
779	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
780	}
781	}
782	}
783
784
785	/**
786	* Allocates memory required by the hardware virtualization state.
787	*
788	* @returns VBox status code.
789	* @param pVM The cross context VM structure.
790	*/
791	static int cpumR3AllocHwVirtState(PVM pVM)
792	{
793	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
794
795	int rc = VINF_SUCCESS;
796	LogRel(("CPUM: Allocating a total of %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
797	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
798	for (VMCPUID i = 0; i < pVM->cCpus; i++)
799	{
800	PVMCPU pVCpu = &pVM->aCpus[i];
801
802	/*
803	* Allocate the nested-guest VMCB.
804	*/
805	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
806	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
807	(PRTR0PTR)pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, NULL /* paPages */);
808	if (RT_FAILURE(rc))
809	{
810	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
811	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
812	break;
813	}
814
815	/*
816	* Allocate the MSRPM (MSR Permission bitmap).
817	*/
818	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
819	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
820	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
821	if (RT_FAILURE(rc))
822	{
823	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
824	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
825	SVM_MSRPM_PAGES));
826	break;
827	}
828
829	/*
830	* Allocate the IOPM (IO Permission bitmap).
831	*/
832	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
833	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
834	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
835	if (RT_FAILURE(rc))
836	{
837	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
838	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
839	SVM_IOPM_PAGES));
840	break;
841	}
842	}
843
844	/* On any failure, cleanup. */
845	if (RT_FAILURE(rc))
846	cpumR3FreeHwVirtState(pVM);
847
848	return rc;
849	}
850
851
852	/**
853	* Initializes the CPUM.
854	*
855	* @returns VBox status code.
856	* @param pVM The cross context VM structure.
857	*/
858	VMMR3DECL(int) CPUMR3Init(PVM pVM)
859	{
860	LogFlow(("CPUMR3Init\n"));
861
862	/*
863	* Assert alignment, sizes and tables.
864	*/
865	AssertCompileMemberAlignment(VM, cpum.s, 32);
866	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
867	AssertCompileSizeAlignment(CPUMCTX, 64);
868	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
869	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
870	AssertCompileMemberAlignment(VM, cpum, 64);
871	AssertCompileMemberAlignment(VM, aCpus, 64);
872	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
873	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
874	#ifdef VBOX_STRICT
875	int rc2 = cpumR3MsrStrictInitChecks();
876	AssertRCReturn(rc2, rc2);
877	#endif
878
879	/*
880	* Initialize offsets.
881	*/
882
883	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
884	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
885	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
886
887
888	/* Calculate the offset from CPUMCPU to CPUM. */
889	for (VMCPUID i = 0; i < pVM->cCpus; i++)
890	{
891	PVMCPU pVCpu = &pVM->aCpus[i];
892
893	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
894	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
895	}
896
897	/*
898	* Gather info about the host CPU.
899	*/
900	if (!ASMHasCpuId())
901	{
902	Log(("The CPU doesn't support CPUID!\n"));
903	return VERR_UNSUPPORTED_CPU;
904	}
905
906	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
907
908	PCPUMCPUIDLEAF paLeaves;
909	uint32_t cLeaves;
910	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
911	AssertLogRelRCReturn(rc, rc);
912
913	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
914	RTMemFree(paLeaves);
915	AssertLogRelRCReturn(rc, rc);
916	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
917
918	/*
919	* Check that the CPU supports the minimum features we require.
920	*/
921	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
922	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
923	if (!pVM->cpum.s.HostFeatures.fMmx)
924	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
925	if (!pVM->cpum.s.HostFeatures.fTsc)
926	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
927
928	/*
929	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
930	*/
931	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
932	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
933
934	/*
935	* Figure out which XSAVE/XRSTOR features are available on the host.
936	*/
937	uint64_t fXcr0Host = 0;
938	uint64_t fXStateHostMask = 0;
939	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
940	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
941	{
942	fXStateHostMask = fXcr0Host = ASMGetXcr0();
943	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
944	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
945	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
946	}
947	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
948	if (!HMIsEnabled(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
949	fXStateHostMask = 0;
950	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
951	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
952
953	/*
954	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
955	*/
956	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
957	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
958	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
959
960	uint8_t *pbXStates;
961	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
962	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
963	AssertLogRelRCReturn(rc, rc);
964
965	for (VMCPUID i = 0; i < pVM->cCpus; i++)
966	{
967	PVMCPU pVCpu = &pVM->aCpus[i];
968
969	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
970	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
971	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
972	pbXStates += cbMaxXState;
973
974	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
975	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
976	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
977	pbXStates += cbMaxXState;
978
979	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
980	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
981	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
982	pbXStates += cbMaxXState;
983
984	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
985	}
986
987	/*
988	* Register saved state data item.
989	*/
990	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
991	NULL, cpumR3LiveExec, NULL,
992	NULL, cpumR3SaveExec, NULL,
993	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
994	if (RT_FAILURE(rc))
995	return rc;
996
997	/*
998	* Register info handlers and registers with the debugger facility.
999	*/
1000	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1001	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1002	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1003	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1004	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1005	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1006	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1007	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1008	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1009	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1010	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1011	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1012	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1013
1014	rc = cpumR3DbgInit(pVM);
1015	if (RT_FAILURE(rc))
1016	return rc;
1017
1018	/*
1019	* Check if we need to workaround partial/leaky FPU handling.
1020	*/
1021	cpumR3CheckLeakyFpu(pVM);
1022
1023	/*
1024	* Initialize the Guest CPUID and MSR states.
1025	*/
1026	rc = cpumR3InitCpuIdAndMsrs(pVM);
1027	if (RT_FAILURE(rc))
1028	return rc;
1029
1030	/*
1031	* Allocate memory required by the guest hardware virtualization state.
1032	*/
1033	if (pVM->cpum.ro.GuestFeatures.fSvm)
1034	{
1035	rc = cpumR3AllocHwVirtState(pVM);
1036	if (RT_FAILURE(rc))
1037	return rc;
1038	}
1039
1040	CPUMR3Reset(pVM);
1041	return VINF_SUCCESS;
1042	}
1043
1044
1045	/**
1046	* Applies relocations to data and code managed by this
1047	* component. This function will be called at init and
1048	* whenever the VMM need to relocate it self inside the GC.
1049	*
1050	* The CPUM will update the addresses used by the switcher.
1051	*
1052	* @param pVM The cross context VM structure.
1053	*/
1054	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1055	{
1056	LogFlow(("CPUMR3Relocate\n"));
1057
1058	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1059	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1060
1061	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1062	{
1063	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1064	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1065	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1066	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1067
1068	/* Recheck the guest DRx values in raw-mode. */
1069	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1070	}
1071	}
1072
1073
1074	/**
1075	* Apply late CPUM property changes based on the fHWVirtEx setting
1076	*
1077	* @param pVM The cross context VM structure.
1078	* @param fHWVirtExEnabled HWVirtEx enabled/disabled
1079	*/
1080	VMMR3DECL(void) CPUMR3SetHWVirtEx(PVM pVM, bool fHWVirtExEnabled)
1081	{
1082	/*
1083	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1084	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1085	* of processors from (cpuid(4).eax >> 26) + 1.
1086	*
1087	* Note: this code is obsolete, but let's keep it here for reference.
1088	* Purpose is valid when we artificially cap the max std id to less than 4.
1089	*/
1090	if (!fHWVirtExEnabled)
1091	{
1092	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1093	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1094	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1095	}
1096	}
1097
1098	/**
1099	* Terminates the CPUM.
1100	*
1101	* Termination means cleaning up and freeing all resources,
1102	* the VM it self is at this point powered off or suspended.
1103	*
1104	* @returns VBox status code.
1105	* @param pVM The cross context VM structure.
1106	*/
1107	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1108	{
1109	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1110	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1111	{
1112	PVMCPU pVCpu = &pVM->aCpus[i];
1113	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1114
1115	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1116	pVCpu->cpum.s.uMagic = 0;
1117	pCtx->dr[5] = 0;
1118	}
1119	#endif
1120
1121	if (pVM->cpum.ro.GuestFeatures.fSvm)
1122	cpumR3FreeHwVirtState(pVM);
1123	return VINF_SUCCESS;
1124	}
1125
1126
1127	/**
1128	* Resets a virtual CPU.
1129	*
1130	* Used by CPUMR3Reset and CPU hot plugging.
1131	*
1132	* @param pVM The cross context VM structure.
1133	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1134	* being reset. This may differ from the current EMT.
1135	*/
1136	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1137	{
1138	/** @todo anything different for VCPU > 0? */
1139	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1140
1141	/*
1142	* Initialize everything to ZERO first.
1143	*/
1144	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1145
1146	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1147	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1148	memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1149
1150	pVCpu->cpum.s.fUseFlags = fUseFlags;
1151
1152	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1153	pCtx->eip = 0x0000fff0;
1154	pCtx->edx = 0x00000600; /* P6 processor */
1155	pCtx->eflags.Bits.u1Reserved0 = 1;
1156
1157	pCtx->cs.Sel = 0xf000;
1158	pCtx->cs.ValidSel = 0xf000;
1159	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1160	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1161	pCtx->cs.u32Limit = 0x0000ffff;
1162	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1163	pCtx->cs.Attr.n.u1Present = 1;
1164	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1165
1166	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1167	pCtx->ds.u32Limit = 0x0000ffff;
1168	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1169	pCtx->ds.Attr.n.u1Present = 1;
1170	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1171
1172	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1173	pCtx->es.u32Limit = 0x0000ffff;
1174	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1175	pCtx->es.Attr.n.u1Present = 1;
1176	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1177
1178	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1179	pCtx->fs.u32Limit = 0x0000ffff;
1180	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1181	pCtx->fs.Attr.n.u1Present = 1;
1182	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1183
1184	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1185	pCtx->gs.u32Limit = 0x0000ffff;
1186	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1187	pCtx->gs.Attr.n.u1Present = 1;
1188	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1189
1190	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1191	pCtx->ss.u32Limit = 0x0000ffff;
1192	pCtx->ss.Attr.n.u1Present = 1;
1193	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1194	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1195
1196	pCtx->idtr.cbIdt = 0xffff;
1197	pCtx->gdtr.cbGdt = 0xffff;
1198
1199	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1200	pCtx->ldtr.u32Limit = 0xffff;
1201	pCtx->ldtr.Attr.n.u1Present = 1;
1202	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1203
1204	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1205	pCtx->tr.u32Limit = 0xffff;
1206	pCtx->tr.Attr.n.u1Present = 1;
1207	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1208
1209	pCtx->dr[6] = X86_DR6_INIT_VAL;
1210	pCtx->dr[7] = X86_DR7_INIT_VAL;
1211
1212	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1213	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1214	pFpuCtx->FCW = 0x37f;
1215
1216	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1217	IA-32 Processor States Following Power-up, Reset, or INIT */
1218	pFpuCtx->MXCSR = 0x1F80;
1219	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1220
1221	pCtx->aXcr[0] = XSAVE_C_X87;
1222	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1223	{
1224	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1225	as we don't know what happened before. (Bother optimize later?) */
1226	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1227	}
1228
1229	/*
1230	* MSRs.
1231	*/
1232	/* Init PAT MSR */
1233	pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
1234
1235	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1236	* The Intel docs don't mention it. */
1237	Assert(!pCtx->msrEFER);
1238
1239	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1240	is supposed to be here, just trying provide useful/sensible values. */
1241	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1242	if (pRange)
1243	{
1244	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1245	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1246	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1247	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1248	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1249	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1250	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1251	}
1252
1253	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1254
1255	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1256	* called from each EMT while we're getting called by CPUMR3Reset()
1257	* iteratively on the same thread. Fix later. */
1258	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1259	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1260	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1261	#endif
1262
1263
1264	/* C-state control. Guesses. */
1265	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1266
1267	/*
1268	* Hardware virtualization state.
1269	*/
1270	/* SVM. */
1271	memset(&pCtx->hwvirt.svm, 0, sizeof(pCtx->hwvirt.svm));
1272	pCtx->hwvirt.svm.fGif = 1;
1273	}
1274
1275
1276	/**
1277	* Resets the CPU.
1278	*
1279	* @returns VINF_SUCCESS.
1280	* @param pVM The cross context VM structure.
1281	*/
1282	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1283	{
1284	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1285	{
1286	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1287
1288	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1289	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1290
1291	/* Magic marker for searching in crash dumps. */
1292	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1293	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1294	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1295	#endif
1296	}
1297	}
1298
1299
1300
1301
1302	/**
1303	* Pass 0 live exec callback.
1304	*
1305	* @returns VINF_SSM_DONT_CALL_AGAIN.
1306	* @param pVM The cross context VM structure.
1307	* @param pSSM The saved state handle.
1308	* @param uPass The pass (0).
1309	*/
1310	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1311	{
1312	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1313	cpumR3SaveCpuId(pVM, pSSM);
1314	return VINF_SSM_DONT_CALL_AGAIN;
1315	}
1316
1317
1318	/**
1319	* Execute state save operation.
1320	*
1321	* @returns VBox status code.
1322	* @param pVM The cross context VM structure.
1323	* @param pSSM SSM operation handle.
1324	*/
1325	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1326	{
1327	/*
1328	* Save.
1329	*/
1330	SSMR3PutU32(pSSM, pVM->cCpus);
1331	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1332	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1333	{
1334	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1335
1336	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1337
1338	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1339	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1340	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1341	if (pGstCtx->fXStateMask != 0)
1342	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1343	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1344	{
1345	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1346	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1347	}
1348	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1349	{
1350	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1351	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1352	}
1353	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1354	{
1355	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1356	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1357	}
1358	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1359	{
1360	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1361	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1362	}
1363	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1364	{
1365	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1366	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1367	}
1368
1369	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1370	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1371	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1372	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1373	}
1374
1375	cpumR3SaveCpuId(pVM, pSSM);
1376	return VINF_SUCCESS;
1377	}
1378
1379
1380	/**
1381	* @callback_method_impl{FNSSMINTLOADPREP}
1382	*/
1383	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1384	{
1385	NOREF(pSSM);
1386	pVM->cpum.s.fPendingRestore = true;
1387	return VINF_SUCCESS;
1388	}
1389
1390
1391	/**
1392	* @callback_method_impl{FNSSMINTLOADEXEC}
1393	*/
1394	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1395	{
1396	int rc; /* Only for AssertRCReturn use. */
1397
1398	/*
1399	* Validate version.
1400	*/
1401	if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1402	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1403	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1404	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1405	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
1406	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1407	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1408	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1409	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1410	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1411	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1412	{
1413	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1414	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1415	}
1416
1417	if (uPass == SSM_PASS_FINAL)
1418	{
1419	/*
1420	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1421	* really old SSM file versions.)
1422	*/
1423	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1424	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1425	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1426	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1427
1428	/*
1429	* Figure x86 and ctx field definitions to use for older states.
1430	*/
1431	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1432	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1433	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1434	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1435	{
1436	paCpumCtx1Fields = g_aCpumX87FieldsV16;
1437	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1438	}
1439	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1440	{
1441	paCpumCtx1Fields = g_aCpumX87FieldsMem;
1442	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1443	}
1444
1445	/*
1446	* The hyper state used to preceed the CPU count. Starting with
1447	* XSAVE it was moved down till after we've got the count.
1448	*/
1449	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1450	{
1451	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1452	{
1453	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1454	X86FXSTATE Ign;
1455	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1456	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1457	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1458	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1459	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1460	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1461	pVCpu->cpum.s.Hyper.rsp = uRSP;
1462	}
1463	}
1464
1465	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1466	{
1467	uint32_t cCpus;
1468	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1469	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1470	VERR_SSM_UNEXPECTED_DATA);
1471	}
1472	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1473	\|\| pVM->cCpus == 1,
1474	("cCpus=%u\n", pVM->cCpus),
1475	VERR_SSM_UNEXPECTED_DATA);
1476
1477	uint32_t cbMsrs = 0;
1478	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1479	{
1480	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1481	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1482	VERR_SSM_UNEXPECTED_DATA);
1483	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1484	VERR_SSM_UNEXPECTED_DATA);
1485	}
1486
1487	/*
1488	* Do the per-CPU restoring.
1489	*/
1490	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1491	{
1492	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1493	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1494
1495	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1496	{
1497	/*
1498	* The XSAVE saved state layout moved the hyper state down here.
1499	*/
1500	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1501	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1502	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1503	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1504	pVCpu->cpum.s.Hyper.rsp = uRSP;
1505	AssertRCReturn(rc, rc);
1506
1507	/*
1508	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1509	*/
1510	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1511	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1512	AssertRCReturn(rc, rc);
1513
1514	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1515	if (pGstCtx->fXStateMask != 0)
1516	{
1517	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1518	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1519	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1520	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1521	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1522	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1523	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1524	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1525	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1526	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1527	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1528	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1529	}
1530
1531	/* Check that the XCR0 mask is valid (invalid results in #GP). */
1532	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1533	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1534	{
1535	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
1536	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1537	VERR_CPUM_INVALID_XCR0);
1538	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1539	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1540	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1541	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1542	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1543	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1544	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1545	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1546	}
1547
1548	/* Check that the XCR1 is zero, as we don't implement it yet. */
1549	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1550
1551	/*
1552	* Restore the individual extended state components we support.
1553	*/
1554	if (pGstCtx->fXStateMask != 0)
1555	{
1556	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1557	0, g_aCpumXSaveHdrFields, NULL);
1558	AssertRCReturn(rc, rc);
1559	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1560	("bmXState=%#RX64 fXStateMask=%#RX64\n",
1561	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1562	VERR_CPUM_INVALID_XSAVE_HDR);
1563	}
1564	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1565	{
1566	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1567	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1568	}
1569	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1570	{
1571	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1572	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1573	}
1574	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1575	{
1576	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1577	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1578	}
1579	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1580	{
1581	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1582	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1583	}
1584	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1585	{
1586	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1587	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1588	}
1589	}
1590	else
1591	{
1592	/*
1593	* Pre XSAVE saved state.
1594	*/
1595	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1596	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1597	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1598	}
1599
1600	/*
1601	* Restore a couple of flags and the MSRs.
1602	*/
1603	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1604	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1605
1606	rc = VINF_SUCCESS;
1607	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1608	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1609	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1610	{
1611	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1612	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1613	}
1614	AssertRCReturn(rc, rc);
1615
1616	/* REM and other may have cleared must-be-one fields in DR6 and
1617	DR7, fix these. */
1618	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
1619	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
1620	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
1621	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
1622	}
1623
1624	/* Older states does not have the internal selector register flags
1625	and valid selector value. Supply those. */
1626	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1627	{
1628	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1629	{
1630	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1631	bool const fValid = HMIsEnabled(pVM)
1632	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1633	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1634	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1635	if (fValid)
1636	{
1637	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1638	{
1639	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1640	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1641	}
1642
1643	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1644	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1645	}
1646	else
1647	{
1648	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1649	{
1650	paSelReg[iSelReg].fFlags = 0;
1651	paSelReg[iSelReg].ValidSel = 0;
1652	}
1653
1654	/* This might not be 104% correct, but I think it's close
1655	enough for all practical purposes... (REM always loaded
1656	LDTR registers.) */
1657	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1658	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1659	}
1660	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1661	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1662	}
1663	}
1664
1665	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1666	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1667	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1668	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1669	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1670
1671	/*
1672	* A quick sanity check.
1673	*/
1674	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1675	{
1676	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1677	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1678	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1679	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1680	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1681	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1682	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1683	}
1684	}
1685
1686	pVM->cpum.s.fPendingRestore = false;
1687
1688	/*
1689	* Guest CPUIDs.
1690	*/
1691	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1692	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1693	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1694	}
1695
1696
1697	/**
1698	* @callback_method_impl{FNSSMINTLOADDONE}
1699	*/
1700	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1701	{
1702	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1703	return VINF_SUCCESS;
1704
1705	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1706	if (pVM->cpum.s.fPendingRestore)
1707	{
1708	LogRel(("CPUM: Missing state!\n"));
1709	return VERR_INTERNAL_ERROR_2;
1710	}
1711
1712	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1713	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1714	{
1715	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1716
1717	/* Notify PGM of the NXE states in case they've changed. */
1718	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1719
1720	/* During init. this is done in CPUMR3InitCompleted(). */
1721	if (fSupportsLongMode)
1722	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
1723	}
1724	return VINF_SUCCESS;
1725	}
1726
1727
1728	/**
1729	* Checks if the CPUM state restore is still pending.
1730	*
1731	* @returns true / false.
1732	* @param pVM The cross context VM structure.
1733	*/
1734	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1735	{
1736	return pVM->cpum.s.fPendingRestore;
1737	}
1738
1739
1740	/**
1741	* Formats the EFLAGS value into mnemonics.
1742	*
1743	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1744	* @param efl The EFLAGS value.
1745	*/
1746	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1747	{
1748	/*
1749	* Format the flags.
1750	*/
1751	static const struct
1752	{
1753	const char pszSet; const char pszClear; uint32_t fFlag;
1754	} s_aFlags[] =
1755	{
1756	{ "vip",NULL, X86_EFL_VIP },
1757	{ "vif",NULL, X86_EFL_VIF },
1758	{ "ac", NULL, X86_EFL_AC },
1759	{ "vm", NULL, X86_EFL_VM },
1760	{ "rf", NULL, X86_EFL_RF },
1761	{ "nt", NULL, X86_EFL_NT },
1762	{ "ov", "nv", X86_EFL_OF },
1763	{ "dn", "up", X86_EFL_DF },
1764	{ "ei", "di", X86_EFL_IF },
1765	{ "tf", NULL, X86_EFL_TF },
1766	{ "nt", "pl", X86_EFL_SF },
1767	{ "nz", "zr", X86_EFL_ZF },
1768	{ "ac", "na", X86_EFL_AF },
1769	{ "po", "pe", X86_EFL_PF },
1770	{ "cy", "nc", X86_EFL_CF },
1771	};
1772	char *psz = pszEFlags;
1773	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1774	{
1775	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1776	if (pszAdd)
1777	{
1778	strcpy(psz, pszAdd);
1779	psz += strlen(pszAdd);
1780	*psz++ = ' ';
1781	}
1782	}
1783	psz[-1] = '\0';
1784	}
1785
1786
1787	/**
1788	* Formats a full register dump.
1789	*
1790	* @param pVM The cross context VM structure.
1791	* @param pCtx The context to format.
1792	* @param pCtxCore The context core to format.
1793	* @param pHlp Output functions.
1794	* @param enmType The dump type.
1795	* @param pszPrefix Register name prefix.
1796	*/
1797	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1798	const char *pszPrefix)
1799	{
1800	NOREF(pVM);
1801
1802	/*
1803	* Format the EFLAGS.
1804	*/
1805	uint32_t efl = pCtxCore->eflags.u32;
1806	char szEFlags[80];
1807	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1808
1809	/*
1810	* Format the registers.
1811	*/
1812	switch (enmType)
1813	{
1814	case CPUMDUMPTYPE_TERSE:
1815	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1816	pHlp->pfnPrintf(pHlp,
1817	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1818	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1819	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1820	"%sr14=%016RX64 %sr15=%016RX64\n"
1821	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1822	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1823	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1824	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1825	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1826	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1827	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1828	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1829	else
1830	pHlp->pfnPrintf(pHlp,
1831	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1832	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1833	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1834	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1835	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1836	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1837	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1838	break;
1839
1840	case CPUMDUMPTYPE_DEFAULT:
1841	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1842	pHlp->pfnPrintf(pHlp,
1843	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1844	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1845	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1846	"%sr14=%016RX64 %sr15=%016RX64\n"
1847	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1848	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1849	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1850	,
1851	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1852	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1853	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1854	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1855	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1856	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1857	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1858	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1859	else
1860	pHlp->pfnPrintf(pHlp,
1861	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1862	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1863	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1864	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1865	,
1866	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1867	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1868	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1869	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1870	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1871	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1872	break;
1873
1874	case CPUMDUMPTYPE_VERBOSE:
1875	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1876	pHlp->pfnPrintf(pHlp,
1877	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1878	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1879	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1880	"%sr14=%016RX64 %sr15=%016RX64\n"
1881	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1882	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1883	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1884	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1885	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1886	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1887	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1888	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1889	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1890	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1891	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1892	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1893	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1894	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1895	,
1896	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1897	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1898	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1899	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1900	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1901	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1902	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1903	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1904	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1905	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1906	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1907	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1908	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1909	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1910	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1911	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1912	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1913	else
1914	pHlp->pfnPrintf(pHlp,
1915	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1916	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1917	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1918	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1919	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1920	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1921	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1922	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1923	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1924	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1925	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1926	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1927	,
1928	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1929	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1930	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1931	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1932	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1933	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1934	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1935	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1936	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1937	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1938	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1939	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1940
1941	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1942	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1943	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1944	if (pCtx->CTX_SUFF(pXState))
1945	{
1946	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1947	pHlp->pfnPrintf(pHlp,
1948	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1949	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1950	,
1951	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1952	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1953	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1954	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1955	);
1956	/*
1957	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1958	* not (FP)R0-7 as Intel SDM suggests.
1959	*/
1960	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1961	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1962	{
1963	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1964	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1965	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1966	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1967	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1968	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1969	iExponent -= 16383; /* subtract bias */
1970	/** @todo This isn't entirenly correct and needs more work! */
1971	pHlp->pfnPrintf(pHlp,
1972	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1973	pszPrefix, iST, pszPrefix, iFPR,
1974	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1975	uTag, chSign, iInteger, u64Fraction, iExponent);
1976	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
1977	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1978	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1979	else
1980	pHlp->pfnPrintf(pHlp, "\n");
1981	}
1982
1983	/* XMM/YMM/ZMM registers. */
1984	if (pCtx->fXStateMask & XSAVE_C_YMM)
1985	{
1986	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1987	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
1988	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
1989	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
1990	pszPrefix, i, i < 10 ? " " : "",
1991	pYmmHiCtx->aYmmHi[i].au32[3],
1992	pYmmHiCtx->aYmmHi[i].au32[2],
1993	pYmmHiCtx->aYmmHi[i].au32[1],
1994	pYmmHiCtx->aYmmHi[i].au32[0],
1995	pFpuCtx->aXMM[i].au32[3],
1996	pFpuCtx->aXMM[i].au32[2],
1997	pFpuCtx->aXMM[i].au32[1],
1998	pFpuCtx->aXMM[i].au32[0]);
1999	else
2000	{
2001	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2002	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2003	pHlp->pfnPrintf(pHlp,
2004	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2005	pszPrefix, i, i < 10 ? " " : "",
2006	pZmmHi256->aHi256Regs[i].au32[7],
2007	pZmmHi256->aHi256Regs[i].au32[6],
2008	pZmmHi256->aHi256Regs[i].au32[5],
2009	pZmmHi256->aHi256Regs[i].au32[4],
2010	pZmmHi256->aHi256Regs[i].au32[3],
2011	pZmmHi256->aHi256Regs[i].au32[2],
2012	pZmmHi256->aHi256Regs[i].au32[1],
2013	pZmmHi256->aHi256Regs[i].au32[0],
2014	pYmmHiCtx->aYmmHi[i].au32[3],
2015	pYmmHiCtx->aYmmHi[i].au32[2],
2016	pYmmHiCtx->aYmmHi[i].au32[1],
2017	pYmmHiCtx->aYmmHi[i].au32[0],
2018	pFpuCtx->aXMM[i].au32[3],
2019	pFpuCtx->aXMM[i].au32[2],
2020	pFpuCtx->aXMM[i].au32[1],
2021	pFpuCtx->aXMM[i].au32[0]);
2022
2023	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2024	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2025	pHlp->pfnPrintf(pHlp,
2026	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2027	pszPrefix, i + 16,
2028	pZmm16Hi->aRegs[i].au32[15],
2029	pZmm16Hi->aRegs[i].au32[14],
2030	pZmm16Hi->aRegs[i].au32[13],
2031	pZmm16Hi->aRegs[i].au32[12],
2032	pZmm16Hi->aRegs[i].au32[11],
2033	pZmm16Hi->aRegs[i].au32[10],
2034	pZmm16Hi->aRegs[i].au32[9],
2035	pZmm16Hi->aRegs[i].au32[8],
2036	pZmm16Hi->aRegs[i].au32[7],
2037	pZmm16Hi->aRegs[i].au32[6],
2038	pZmm16Hi->aRegs[i].au32[5],
2039	pZmm16Hi->aRegs[i].au32[4],
2040	pZmm16Hi->aRegs[i].au32[3],
2041	pZmm16Hi->aRegs[i].au32[2],
2042	pZmm16Hi->aRegs[i].au32[1],
2043	pZmm16Hi->aRegs[i].au32[0]);
2044	}
2045	}
2046	else
2047	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2048	pHlp->pfnPrintf(pHlp,
2049	i & 1
2050	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2051	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2052	pszPrefix, i, i < 10 ? " " : "",
2053	pFpuCtx->aXMM[i].au32[3],
2054	pFpuCtx->aXMM[i].au32[2],
2055	pFpuCtx->aXMM[i].au32[1],
2056	pFpuCtx->aXMM[i].au32[0]);
2057
2058	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2059	{
2060	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2061	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2062	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2063	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2064	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2065	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2066	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2067	}
2068
2069	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2070	{
2071	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2072	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2073	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2074	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2075	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2076	}
2077
2078	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2079	{
2080	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2081	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2082	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2083	}
2084
2085	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2086	if (pFpuCtx->au32RsrvdRest[i])
2087	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2088	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2089	}
2090
2091	pHlp->pfnPrintf(pHlp,
2092	"%sEFER =%016RX64\n"
2093	"%sPAT =%016RX64\n"
2094	"%sSTAR =%016RX64\n"
2095	"%sCSTAR =%016RX64\n"
2096	"%sLSTAR =%016RX64\n"
2097	"%sSFMASK =%016RX64\n"
2098	"%sKERNELGSBASE =%016RX64\n",
2099	pszPrefix, pCtx->msrEFER,
2100	pszPrefix, pCtx->msrPAT,
2101	pszPrefix, pCtx->msrSTAR,
2102	pszPrefix, pCtx->msrCSTAR,
2103	pszPrefix, pCtx->msrLSTAR,
2104	pszPrefix, pCtx->msrSFMASK,
2105	pszPrefix, pCtx->msrKERNELGSBASE);
2106	break;
2107	}
2108	}
2109
2110
2111	/**
2112	* Display all cpu states and any other cpum info.
2113	*
2114	* @param pVM The cross context VM structure.
2115	* @param pHlp The info helper functions.
2116	* @param pszArgs Arguments, ignored.
2117	*/
2118	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2119	{
2120	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2121	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2122	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2123	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2124	cpumR3InfoHost(pVM, pHlp, pszArgs);
2125	}
2126
2127
2128	/**
2129	* Parses the info argument.
2130	*
2131	* The argument starts with 'verbose', 'terse' or 'default' and then
2132	* continues with the comment string.
2133	*
2134	* @param pszArgs The pointer to the argument string.
2135	* @param penmType Where to store the dump type request.
2136	* @param ppszComment Where to store the pointer to the comment string.
2137	*/
2138	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2139	{
2140	if (!pszArgs)
2141	{
2142	*penmType = CPUMDUMPTYPE_DEFAULT;
2143	*ppszComment = "";
2144	}
2145	else
2146	{
2147	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2148	{
2149	pszArgs += 7;
2150	*penmType = CPUMDUMPTYPE_VERBOSE;
2151	}
2152	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2153	{
2154	pszArgs += 5;
2155	*penmType = CPUMDUMPTYPE_TERSE;
2156	}
2157	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2158	{
2159	pszArgs += 7;
2160	*penmType = CPUMDUMPTYPE_DEFAULT;
2161	}
2162	else
2163	*penmType = CPUMDUMPTYPE_DEFAULT;
2164	*ppszComment = RTStrStripL(pszArgs);
2165	}
2166	}
2167
2168
2169	/**
2170	* Display the guest cpu state.
2171	*
2172	* @param pVM The cross context VM structure.
2173	* @param pHlp The info helper functions.
2174	* @param pszArgs Arguments.
2175	*/
2176	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2177	{
2178	CPUMDUMPTYPE enmType;
2179	const char *pszComment;
2180	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2181
2182	PVMCPU pVCpu = VMMGetCpu(pVM);
2183	if (!pVCpu)
2184	pVCpu = &pVM->aCpus[0];
2185
2186	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2187
2188	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2189	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2190	}
2191
2192
2193	/**
2194	* Display the guest's hardware-virtualization cpu state.
2195	*
2196	* @param pVM The cross context VM structure.
2197	* @param pHlp The info helper functions.
2198	* @param pszArgs Arguments, ignored.
2199	*/
2200	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2201	{
2202	RT_NOREF(pszArgs);
2203
2204	PVMCPU pVCpu = VMMGetCpu(pVM);
2205	if (!pVCpu)
2206	pVCpu = &pVM->aCpus[0];
2207
2208	/*
2209	* Figure out what to dump.
2210	*
2211	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
2212	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2213	* dump hwvirt. state when the guest CPU is executing a nested-guest.
2214	*/
2215	/** @todo perhaps make this configurable through pszArgs, depending on how much
2216	* noise we wish to accept when nested hwvirt. isn't used. */
2217	#define CPUMHWVIRTDUMP_NONE (0)
2218	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2219	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2220	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2221	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2222	#define CPUMHWVIRTDUMP_ALL (CPUMHWVIRTDUMP_COMMON \| CPUMHWVIRTDUMP_VMX \| CPUMHWVIRTDUMP_SVM)
2223
2224	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2225	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2226	uint8_t const idxHwvirtState = CPUMIsGuestInSvmNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_SVM
2227	: CPUMIsGuestInVmxNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE;
2228	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2229	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2230	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2231	uint32_t const fDumpState = idxHwvirtState; /* \| CPUMHWVIRTDUMP_ALL */
2232
2233	/*
2234	* Dump it.
2235	*/
2236	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2237
2238	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2239	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2240	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, fDumpState ? ":" : "");
2241	if (fDumpState & CPUMHWVIRTDUMP_SVM)
2242	{
2243	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2244	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2245	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2246	HMR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2247	/** @todo HMR3InfoSvmVmcbStateSave. */
2248	pHlp->pfnPrintf(pHlp, " HostState:\n");
2249	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2250	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2251	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2252	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2253	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2254	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2255	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2256	pHlp->pfnPrintf(pHlp, " rflags = %#RX64\n", pCtx->hwvirt.svm.HostState.rflags.u64);
2257	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2258	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2259	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2260	pSel = &pCtx->hwvirt.svm.HostState.cs;
2261	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2262	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2263	pSel = &pCtx->hwvirt.svm.HostState.ss;
2264	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2265	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2266	pSel = &pCtx->hwvirt.svm.HostState.ds;
2267	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2268	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->fFlags);
2269	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2270	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2271	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2272	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2273	pHlp->pfnPrintf(pHlp, " fGif = %u\n", pCtx->hwvirt.svm.fGif);
2274	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2275	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2276	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2277	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2278	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2279	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2280	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2281	}
2282
2283	/** @todo Intel. */
2284	#if 0
2285	if (fDumpState & CPUMHWVIRTDUMP_VMX)
2286	{
2287	}
2288	#endif
2289
2290	#undef CPUMHWVIRTDUMP_NONE
2291	#undef CPUMHWVIRTDUMP_COMMON
2292	#undef CPUMHWVIRTDUMP_SVM
2293	#undef CPUMHWVIRTDUMP_VMX
2294	#undef CPUMHWVIRTDUMP_LAST
2295	#undef CPUMHWVIRTDUMP_ALL
2296	}
2297
2298	/**
2299	* Display the current guest instruction
2300	*
2301	* @param pVM The cross context VM structure.
2302	* @param pHlp The info helper functions.
2303	* @param pszArgs Arguments, ignored.
2304	*/
2305	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2306	{
2307	NOREF(pszArgs);
2308
2309	PVMCPU pVCpu = VMMGetCpu(pVM);
2310	if (!pVCpu)
2311	pVCpu = &pVM->aCpus[0];
2312
2313	char szInstruction[256];
2314	szInstruction[0] = '\0';
2315	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2316	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2317	}
2318
2319
2320	/**
2321	* Display the hypervisor cpu state.
2322	*
2323	* @param pVM The cross context VM structure.
2324	* @param pHlp The info helper functions.
2325	* @param pszArgs Arguments, ignored.
2326	*/
2327	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2328	{
2329	PVMCPU pVCpu = VMMGetCpu(pVM);
2330	if (!pVCpu)
2331	pVCpu = &pVM->aCpus[0];
2332
2333	CPUMDUMPTYPE enmType;
2334	const char *pszComment;
2335	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2336	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2337	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2338	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2339	}
2340
2341
2342	/**
2343	* Display the host cpu state.
2344	*
2345	* @param pVM The cross context VM structure.
2346	* @param pHlp The info helper functions.
2347	* @param pszArgs Arguments, ignored.
2348	*/
2349	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2350	{
2351	CPUMDUMPTYPE enmType;
2352	const char *pszComment;
2353	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2354	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2355
2356	PVMCPU pVCpu = VMMGetCpu(pVM);
2357	if (!pVCpu)
2358	pVCpu = &pVM->aCpus[0];
2359	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2360
2361	/*
2362	* Format the EFLAGS.
2363	*/
2364	#if HC_ARCH_BITS == 32
2365	uint32_t efl = pCtx->eflags.u32;
2366	#else
2367	uint64_t efl = pCtx->rflags;
2368	#endif
2369	char szEFlags[80];
2370	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2371
2372	/*
2373	* Format the registers.
2374	*/
2375	#if HC_ARCH_BITS == 32
2376	pHlp->pfnPrintf(pHlp,
2377	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2378	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2379	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2380	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2381	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2382	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2383	,
2384	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2385	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2386	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2387	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2388	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2389	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2390	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2391	#else
2392	pHlp->pfnPrintf(pHlp,
2393	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2394	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2395	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2396	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2397	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2398	"r14=%016RX64 r15=%016RX64\n"
2399	"iopl=%d %31s\n"
2400	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2401	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2402	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2403	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2404	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2405	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2406	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2407	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2408	,
2409	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2410	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2411	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2412	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2413	pCtx->r11, pCtx->r12, pCtx->r13,
2414	pCtx->r14, pCtx->r15,
2415	X86_EFL_GET_IOPL(efl), szEFlags,
2416	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2417	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2418	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2419	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2420	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2421	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2422	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2423	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2424	#endif
2425	}
2426
2427	/**
2428	* Structure used when disassembling and instructions in DBGF.
2429	* This is used so the reader function can get the stuff it needs.
2430	*/
2431	typedef struct CPUMDISASSTATE
2432	{
2433	/** Pointer to the CPU structure. */
2434	PDISCPUSTATE pCpu;
2435	/** Pointer to the VM. */
2436	PVM pVM;
2437	/** Pointer to the VMCPU. */
2438	PVMCPU pVCpu;
2439	/** Pointer to the first byte in the segment. */
2440	RTGCUINTPTR GCPtrSegBase;
2441	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
2442	RTGCUINTPTR GCPtrSegEnd;
2443	/** The size of the segment minus 1. */
2444	RTGCUINTPTR cbSegLimit;
2445	/** Pointer to the current page - R3 Ptr. */
2446	void const *pvPageR3;
2447	/** Pointer to the current page - GC Ptr. */
2448	RTGCPTR pvPageGC;
2449	/** The lock information that PGMPhysReleasePageMappingLock needs. */
2450	PGMPAGEMAPLOCK PageMapLock;
2451	/** Whether the PageMapLock is valid or not. */
2452	bool fLocked;
2453	/** 64 bits mode or not. */
2454	bool f64Bits;
2455	} CPUMDISASSTATE, *PCPUMDISASSTATE;
2456
2457
2458	/**
2459	* @callback_method_impl{FNDISREADBYTES}
2460	*/
2461	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2462	{
2463	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2464	for (;;)
2465	{
2466	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2467
2468	/*
2469	* Need to update the page translation?
2470	*/
2471	if ( !pState->pvPageR3
2472	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2473	{
2474	int rc = VINF_SUCCESS;
2475
2476	/* translate the address */
2477	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2478	if ( !HMIsEnabled(pState->pVM)
2479	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2480	{
2481	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2482	if (!pState->pvPageR3)
2483	rc = VERR_INVALID_POINTER;
2484	}
2485	else
2486	{
2487	/* Release mapping lock previously acquired. */
2488	if (pState->fLocked)
2489	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2490	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2491	pState->fLocked = RT_SUCCESS_NP(rc);
2492	}
2493	if (RT_FAILURE(rc))
2494	{
2495	pState->pvPageR3 = NULL;
2496	return rc;
2497	}
2498	}
2499
2500	/*
2501	* Check the segment limit.
2502	*/
2503	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2504	return VERR_OUT_OF_SELECTOR_BOUNDS;
2505
2506	/*
2507	* Calc how much we can read.
2508	*/
2509	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2510	if (!pState->f64Bits)
2511	{
2512	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2513	if (cb > cbSeg && cbSeg)
2514	cb = cbSeg;
2515	}
2516	if (cb > cbMaxRead)
2517	cb = cbMaxRead;
2518
2519	/*
2520	* Read and advance or exit.
2521	*/
2522	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2523	offInstr += (uint8_t)cb;
2524	if (cb >= cbMinRead)
2525	{
2526	pDis->cbCachedInstr = offInstr;
2527	return VINF_SUCCESS;
2528	}
2529	cbMinRead -= (uint8_t)cb;
2530	cbMaxRead -= (uint8_t)cb;
2531	}
2532	}
2533
2534
2535	/**
2536	* Disassemble an instruction and return the information in the provided structure.
2537	*
2538	* @returns VBox status code.
2539	* @param pVM The cross context VM structure.
2540	* @param pVCpu The cross context virtual CPU structure.
2541	* @param pCtx Pointer to the guest CPU context.
2542	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
2543	* @param pCpu Disassembly state.
2544	* @param pszPrefix String prefix for logging (debug only).
2545	*
2546	*/
2547	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2548	const char *pszPrefix)
2549	{
2550	CPUMDISASSTATE State;
2551	int rc;
2552
2553	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2554	State.pCpu = pCpu;
2555	State.pvPageGC = 0;
2556	State.pvPageR3 = NULL;
2557	State.pVM = pVM;
2558	State.pVCpu = pVCpu;
2559	State.fLocked = false;
2560	State.f64Bits = false;
2561
2562	/*
2563	* Get selector information.
2564	*/
2565	DISCPUMODE enmDisCpuMode;
2566	if ( (pCtx->cr0 & X86_CR0_PE)
2567	&& pCtx->eflags.Bits.u1VM == 0)
2568	{
2569	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2570	{
2571	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2572	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2573	# endif
2574	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2575	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2576	}
2577	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2578	State.GCPtrSegBase = pCtx->cs.u64Base;
2579	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2580	State.cbSegLimit = pCtx->cs.u32Limit;
2581	enmDisCpuMode = (State.f64Bits)
2582	? DISCPUMODE_64BIT
2583	: pCtx->cs.Attr.n.u1DefBig
2584	? DISCPUMODE_32BIT
2585	: DISCPUMODE_16BIT;
2586	}
2587	else
2588	{
2589	/* real or V86 mode */
2590	enmDisCpuMode = DISCPUMODE_16BIT;
2591	State.GCPtrSegBase = pCtx->cs.Sel * 16;
2592	State.GCPtrSegEnd = 0xFFFFFFFF;
2593	State.cbSegLimit = 0xFFFFFFFF;
2594	}
2595
2596	/*
2597	* Disassemble the instruction.
2598	*/
2599	uint32_t cbInstr;
2600	#ifndef LOG_ENABLED
2601	RT_NOREF_PV(pszPrefix);
2602	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2603	if (RT_SUCCESS(rc))
2604	{
2605	#else
2606	char szOutput[160];
2607	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2608	pCpu, &cbInstr, szOutput, sizeof(szOutput));
2609	if (RT_SUCCESS(rc))
2610	{
2611	/* log it */
2612	if (pszPrefix)
2613	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2614	else
2615	Log(("%s", szOutput));
2616	#endif
2617	rc = VINF_SUCCESS;
2618	}
2619	else
2620	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2621
2622	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
2623	if (State.fLocked)
2624	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2625
2626	return rc;
2627	}
2628
2629
2630
2631	/**
2632	* API for controlling a few of the CPU features found in CR4.
2633	*
2634	* Currently only X86_CR4_TSD is accepted as input.
2635	*
2636	* @returns VBox status code.
2637	*
2638	* @param pVM The cross context VM structure.
2639	* @param fOr The CR4 OR mask.
2640	* @param fAnd The CR4 AND mask.
2641	*/
2642	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2643	{
2644	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2645	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2646
2647	pVM->cpum.s.CR4.OrMask &= fAnd;
2648	pVM->cpum.s.CR4.OrMask \|= fOr;
2649
2650	return VINF_SUCCESS;
2651	}
2652
2653
2654	/**
2655	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2656	*
2657	* Only REM should ever call this function!
2658	*
2659	* @returns The changed flags.
2660	* @param pVCpu The cross context virtual CPU structure.
2661	* @param puCpl Where to return the current privilege level (CPL).
2662	*/
2663	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2664	{
2665	Assert(!pVCpu->cpum.s.fRawEntered);
2666	Assert(!pVCpu->cpum.s.fRemEntered);
2667
2668	/*
2669	* Get the CPL first.
2670	*/
2671	*puCpl = CPUMGetGuestCPL(pVCpu);
2672
2673	/*
2674	* Get and reset the flags.
2675	*/
2676	uint32_t fFlags = pVCpu->cpum.s.fChanged;
2677	pVCpu->cpum.s.fChanged = 0;
2678
2679	/** @todo change the switcher to use the fChanged flags. */
2680	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2681	{
2682	fFlags \|= CPUM_CHANGED_FPU_REM;
2683	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2684	}
2685
2686	pVCpu->cpum.s.fRemEntered = true;
2687	return fFlags;
2688	}
2689
2690
2691	/**
2692	* Leaves REM.
2693	*
2694	* @param pVCpu The cross context virtual CPU structure.
2695	* @param fNoOutOfSyncSels This is @c false if there are out of sync
2696	* registers.
2697	*/
2698	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2699	{
2700	Assert(!pVCpu->cpum.s.fRawEntered);
2701	Assert(pVCpu->cpum.s.fRemEntered);
2702
2703	RT_NOREF_PV(fNoOutOfSyncSels);
2704
2705	pVCpu->cpum.s.fRemEntered = false;
2706	}
2707
2708
2709	/**
2710	* Called when the ring-3 init phase completes.
2711	*
2712	* @returns VBox status code.
2713	* @param pVM The cross context VM structure.
2714	* @param enmWhat Which init phase.
2715	*/
2716	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2717	{
2718	switch (enmWhat)
2719	{
2720	case VMINITCOMPLETED_RING3:
2721	{
2722	/*
2723	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2724	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2725	*/
2726	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2727	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2728	{
2729	PVMCPU pVCpu = &pVM->aCpus[i];
2730	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2731	if (fSupportsLongMode)
2732	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2733	}
2734
2735	cpumR3MsrRegStats(pVM);
2736	break;
2737	}
2738
2739	default:
2740	break;
2741	}
2742	return VINF_SUCCESS;
2743	}
2744
2745
2746	/**
2747	* Called when the ring-0 init phases completed.
2748	*
2749	* @param pVM The cross context VM structure.
2750	*/
2751	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2752	{
2753	/*
2754	* Log the cpuid.
2755	*/
2756	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
2757	RTCPUSET OnlineSet;
2758	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2759	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2760	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2761	RTCPUID cCores = RTMpGetCoreCount();
2762	if (cCores)
2763	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2764	LogRel(("*********************** CPUID dump **********************\n"));
2765	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2766	LogRel(("\n"));
2767	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
2768	RTLogRelSetBuffering(fOldBuffered);
2769	LogRel(("****************** End of CPUID dump ********************\n"));
2770	}
2771

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 68155

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