CPUM.cpp@ 71833

Last change on this file since 71833 was 71833, checked in by vboxsync, 7 years ago
VMM: Nested hw.virt: Implement pause-filter and pause-filter threshold.
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1	/* $Id: CPUM.cpp 71833 2018-04-12 07:20:33Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for CPUMCTX. */
285	static const SSMFIELD g_aCpumX87Fields[] =
286	{
287	SSMFIELD_ENTRY( X86FXSTATE, FCW),
288	SSMFIELD_ENTRY( X86FXSTATE, FSW),
289	SSMFIELD_ENTRY( X86FXSTATE, FTW),
290	SSMFIELD_ENTRY( X86FXSTATE, FOP),
291	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
292	SSMFIELD_ENTRY( X86FXSTATE, CS),
293	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
294	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
295	SSMFIELD_ENTRY( X86FXSTATE, DS),
296	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
297	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
298	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
299	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
300	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
301	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
302	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
303	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
304	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
305	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
306	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
307	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
308	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
309	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
310	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
311	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
312	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
313	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
314	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
315	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
316	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
317	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
318	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
319	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
320	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
321	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
322	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
323	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
324	SSMFIELD_ENTRY_TERM()
325	};
326
327	/** Saved state field descriptors for X86XSAVEHDR. */
328	static const SSMFIELD g_aCpumXSaveHdrFields[] =
329	{
330	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
331	SSMFIELD_ENTRY_TERM()
332	};
333
334	/** Saved state field descriptors for X86XSAVEYMMHI. */
335	static const SSMFIELD g_aCpumYmmHiFields[] =
336	{
337	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
338	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
339	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
340	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
341	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
342	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
343	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
344	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
345	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
346	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
347	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
348	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
349	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
350	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
351	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
352	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
353	SSMFIELD_ENTRY_TERM()
354	};
355
356	/** Saved state field descriptors for X86XSAVEBNDREGS. */
357	static const SSMFIELD g_aCpumBndRegsFields[] =
358	{
359	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
360	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
361	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
362	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
363	SSMFIELD_ENTRY_TERM()
364	};
365
366	/** Saved state field descriptors for X86XSAVEBNDCFG. */
367	static const SSMFIELD g_aCpumBndCfgFields[] =
368	{
369	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
370	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
371	SSMFIELD_ENTRY_TERM()
372	};
373
374	#if 0 /** @todo */
375	/** Saved state field descriptors for X86XSAVEOPMASK. */
376	static const SSMFIELD g_aCpumOpmaskFields[] =
377	{
378	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
379	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
380	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
381	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
382	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
383	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
384	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
385	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
386	SSMFIELD_ENTRY_TERM()
387	};
388	#endif
389
390	/** Saved state field descriptors for X86XSAVEZMMHI256. */
391	static const SSMFIELD g_aCpumZmmHi256Fields[] =
392	{
393	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
394	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
395	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
396	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
397	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
398	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
399	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
400	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
401	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
402	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
403	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
404	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
405	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
406	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
407	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
408	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
409	SSMFIELD_ENTRY_TERM()
410	};
411
412	/** Saved state field descriptors for X86XSAVEZMM16HI. */
413	static const SSMFIELD g_aCpumZmm16HiFields[] =
414	{
415	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
416	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
417	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
418	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
419	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
420	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
421	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
422	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
423	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
424	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
425	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
426	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
427	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
428	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
429	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
430	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
431	SSMFIELD_ENTRY_TERM()
432	};
433
434
435
436	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
437	* registeres changed. */
438	static const SSMFIELD g_aCpumX87FieldsMem[] =
439	{
440	SSMFIELD_ENTRY( X86FXSTATE, FCW),
441	SSMFIELD_ENTRY( X86FXSTATE, FSW),
442	SSMFIELD_ENTRY( X86FXSTATE, FTW),
443	SSMFIELD_ENTRY( X86FXSTATE, FOP),
444	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
445	SSMFIELD_ENTRY( X86FXSTATE, CS),
446	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
447	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
448	SSMFIELD_ENTRY( X86FXSTATE, DS),
449	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
450	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
451	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
452	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
453	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
454	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
455	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
456	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
457	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
458	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
459	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
460	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
461	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
462	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
463	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
464	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
465	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
466	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
467	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
468	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
469	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
470	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
471	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
472	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
473	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
474	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
475	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
476	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
477	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
478	};
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumCtxFieldsMem[] =
483	{
484	SSMFIELD_ENTRY( CPUMCTX, rdi),
485	SSMFIELD_ENTRY( CPUMCTX, rsi),
486	SSMFIELD_ENTRY( CPUMCTX, rbp),
487	SSMFIELD_ENTRY( CPUMCTX, rax),
488	SSMFIELD_ENTRY( CPUMCTX, rbx),
489	SSMFIELD_ENTRY( CPUMCTX, rdx),
490	SSMFIELD_ENTRY( CPUMCTX, rcx),
491	SSMFIELD_ENTRY( CPUMCTX, rsp),
492	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
493	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
494	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
495	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
496	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
497	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
498	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
499	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
500	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
501	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
502	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
503	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
504	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
505	SSMFIELD_ENTRY( CPUMCTX, rflags),
506	SSMFIELD_ENTRY( CPUMCTX, rip),
507	SSMFIELD_ENTRY( CPUMCTX, r8),
508	SSMFIELD_ENTRY( CPUMCTX, r9),
509	SSMFIELD_ENTRY( CPUMCTX, r10),
510	SSMFIELD_ENTRY( CPUMCTX, r11),
511	SSMFIELD_ENTRY( CPUMCTX, r12),
512	SSMFIELD_ENTRY( CPUMCTX, r13),
513	SSMFIELD_ENTRY( CPUMCTX, r14),
514	SSMFIELD_ENTRY( CPUMCTX, r15),
515	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
516	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
517	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
518	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
519	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
520	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
521	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
522	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
523	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
524	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
525	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
526	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
527	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
528	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
529	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
530	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
531	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
532	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
533	SSMFIELD_ENTRY( CPUMCTX, cr0),
534	SSMFIELD_ENTRY( CPUMCTX, cr2),
535	SSMFIELD_ENTRY( CPUMCTX, cr3),
536	SSMFIELD_ENTRY( CPUMCTX, cr4),
537	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
538	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
539	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
540	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
541	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
542	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
543	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
544	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
545	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
546	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
547	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
548	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
549	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
550	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
551	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
552	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
553	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
554	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
555	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
556	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
557	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
558	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
559	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
560	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
561	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
562	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
563	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
564	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
565	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
571	SSMFIELD_ENTRY_TERM()
572	};
573
574	/** Saved state field descriptors for CPUMCTX_VER1_6. */
575	static const SSMFIELD g_aCpumX87FieldsV16[] =
576	{
577	SSMFIELD_ENTRY( X86FXSTATE, FCW),
578	SSMFIELD_ENTRY( X86FXSTATE, FSW),
579	SSMFIELD_ENTRY( X86FXSTATE, FTW),
580	SSMFIELD_ENTRY( X86FXSTATE, FOP),
581	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
582	SSMFIELD_ENTRY( X86FXSTATE, CS),
583	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
584	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
585	SSMFIELD_ENTRY( X86FXSTATE, DS),
586	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
587	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
588	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
589	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
590	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
591	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
592	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
593	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
594	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
595	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
596	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
597	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
598	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
599	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
600	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
601	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
602	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
603	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
604	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
605	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
606	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
607	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
608	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
609	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
610	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
611	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
612	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
613	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
614	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumCtxFieldsV16[] =
620	{
621	SSMFIELD_ENTRY( CPUMCTX, rdi),
622	SSMFIELD_ENTRY( CPUMCTX, rsi),
623	SSMFIELD_ENTRY( CPUMCTX, rbp),
624	SSMFIELD_ENTRY( CPUMCTX, rax),
625	SSMFIELD_ENTRY( CPUMCTX, rbx),
626	SSMFIELD_ENTRY( CPUMCTX, rdx),
627	SSMFIELD_ENTRY( CPUMCTX, rcx),
628	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
629	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
630	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
631	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
632	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
633	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
634	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
635	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
636	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
637	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
638	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
639	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
640	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
641	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
642	SSMFIELD_ENTRY( CPUMCTX, rflags),
643	SSMFIELD_ENTRY( CPUMCTX, rip),
644	SSMFIELD_ENTRY( CPUMCTX, r8),
645	SSMFIELD_ENTRY( CPUMCTX, r9),
646	SSMFIELD_ENTRY( CPUMCTX, r10),
647	SSMFIELD_ENTRY( CPUMCTX, r11),
648	SSMFIELD_ENTRY( CPUMCTX, r12),
649	SSMFIELD_ENTRY( CPUMCTX, r13),
650	SSMFIELD_ENTRY( CPUMCTX, r14),
651	SSMFIELD_ENTRY( CPUMCTX, r15),
652	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
653	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
654	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
655	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
656	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
657	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
658	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
659	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
660	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
661	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
662	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
663	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
664	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
665	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
666	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
667	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
668	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
669	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
670	SSMFIELD_ENTRY( CPUMCTX, cr0),
671	SSMFIELD_ENTRY( CPUMCTX, cr2),
672	SSMFIELD_ENTRY( CPUMCTX, cr3),
673	SSMFIELD_ENTRY( CPUMCTX, cr4),
674	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
675	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
676	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
677	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
678	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
679	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
680	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
681	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
682	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
683	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
684	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
685	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
686	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
687	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
688	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
689	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
690	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
691	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
692	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
693	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
694	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
695	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
696	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
697	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
698	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
699	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
700	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
701	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
702	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
703	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
704	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
705	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
706	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
707	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
708	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
709	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
710	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
711	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
712	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
713	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
714	SSMFIELD_ENTRY_TERM()
715	};
716
717
718	/**
719	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
720	*
721	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
722	* (last instruction pointer, last data pointer, last opcode) except when the ES
723	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
724	* clear these registers there is potential, local FPU leakage from a process
725	* using the FPU to another.
726	*
727	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
728	*
729	* @param pVM The cross context VM structure.
730	*/
731	static void cpumR3CheckLeakyFpu(PVM pVM)
732	{
733	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
734	uint32_t const u32Family = u32CpuVersion >> 8;
735	if ( u32Family >= 6 /* K7 and higher */
736	&& ASMIsAmdCpu())
737	{
738	uint32_t cExt = ASMCpuId_EAX(0x80000000);
739	if (ASMIsValidExtRange(cExt))
740	{
741	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
742	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
743	{
744	for (VMCPUID i = 0; i < pVM->cCpus; i++)
745	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
746	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
747	}
748	}
749	}
750	}
751
752
753	/**
754	* Frees memory allocated for the SVM hardware virtualization state.
755	*
756	* @param pVM The cross context VM structure.
757	*/
758	static void cpumR3FreeSvmHwVirtState(PVM pVM)
759	{
760	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
761	for (VMCPUID i = 0; i < pVM->cCpus; i++)
762	{
763	PVMCPU pVCpu = &pVM->aCpus[i];
764	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
765	{
766	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
767	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
768	}
769	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
770
771	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
772	{
773	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
774	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
775	}
776
777	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
778	{
779	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
780	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
781	}
782	}
783	}
784
785
786	/**
787	* Allocates memory for the SVM hardware virtualization state.
788	*
789	* @returns VBox status code.
790	* @param pVM The cross context VM structure.
791	*/
792	static int cpumR3AllocSvmHwVirtState(PVM pVM)
793	{
794	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
795
796	int rc = VINF_SUCCESS;
797	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
798	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
799	for (VMCPUID i = 0; i < pVM->cCpus; i++)
800	{
801	PVMCPU pVCpu = &pVM->aCpus[i];
802
803	/*
804	* Allocate the nested-guest VMCB.
805	*/
806	SUPPAGE SupNstGstVmcbPage;
807	RT_ZERO(SupNstGstVmcbPage);
808	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
809	Assert(SVM_VMCB_PAGES == 1);
810	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
811	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
812	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
813	if (RT_FAILURE(rc))
814	{
815	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
816	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
817	break;
818	}
819	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
820
821	/*
822	* Allocate the MSRPM (MSR Permission bitmap).
823	*/
824	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
825	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
826	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
827	if (RT_FAILURE(rc))
828	{
829	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
830	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
831	SVM_MSRPM_PAGES));
832	break;
833	}
834
835	/*
836	* Allocate the IOPM (IO Permission bitmap).
837	*/
838	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
839	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
840	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
841	if (RT_FAILURE(rc))
842	{
843	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
844	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
845	SVM_IOPM_PAGES));
846	break;
847	}
848	}
849
850	/* On any failure, cleanup. */
851	if (RT_FAILURE(rc))
852	cpumR3FreeSvmHwVirtState(pVM);
853
854	return rc;
855	}
856
857
858	/**
859	* Initializes the CPUM.
860	*
861	* @returns VBox status code.
862	* @param pVM The cross context VM structure.
863	*/
864	VMMR3DECL(int) CPUMR3Init(PVM pVM)
865	{
866	LogFlow(("CPUMR3Init\n"));
867
868	/*
869	* Assert alignment, sizes and tables.
870	*/
871	AssertCompileMemberAlignment(VM, cpum.s, 32);
872	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
873	AssertCompileSizeAlignment(CPUMCTX, 64);
874	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
875	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
876	AssertCompileMemberAlignment(VM, cpum, 64);
877	AssertCompileMemberAlignment(VM, aCpus, 64);
878	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
879	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
880	#ifdef VBOX_STRICT
881	int rc2 = cpumR3MsrStrictInitChecks();
882	AssertRCReturn(rc2, rc2);
883	#endif
884
885	/*
886	* Initialize offsets.
887	*/
888
889	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
890	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
891	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
892
893
894	/* Calculate the offset from CPUMCPU to CPUM. */
895	for (VMCPUID i = 0; i < pVM->cCpus; i++)
896	{
897	PVMCPU pVCpu = &pVM->aCpus[i];
898
899	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
900	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
901	}
902
903	/*
904	* Gather info about the host CPU.
905	*/
906	if (!ASMHasCpuId())
907	{
908	Log(("The CPU doesn't support CPUID!\n"));
909	return VERR_UNSUPPORTED_CPU;
910	}
911
912	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
913
914	PCPUMCPUIDLEAF paLeaves;
915	uint32_t cLeaves;
916	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
917	AssertLogRelRCReturn(rc, rc);
918
919	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
920	RTMemFree(paLeaves);
921	AssertLogRelRCReturn(rc, rc);
922	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
923
924	/*
925	* Check that the CPU supports the minimum features we require.
926	*/
927	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
928	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
929	if (!pVM->cpum.s.HostFeatures.fMmx)
930	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
931	if (!pVM->cpum.s.HostFeatures.fTsc)
932	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
933
934	/*
935	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
936	*/
937	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
938	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
939
940	/*
941	* Figure out which XSAVE/XRSTOR features are available on the host.
942	*/
943	uint64_t fXcr0Host = 0;
944	uint64_t fXStateHostMask = 0;
945	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
946	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
947	{
948	fXStateHostMask = fXcr0Host = ASMGetXcr0();
949	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
950	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
951	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
952	}
953	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
954	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
955	fXStateHostMask = 0;
956	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
957	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
958
959	/*
960	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
961	*/
962	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
963	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
964	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
965
966	uint8_t *pbXStates;
967	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
968	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
969	AssertLogRelRCReturn(rc, rc);
970
971	for (VMCPUID i = 0; i < pVM->cCpus; i++)
972	{
973	PVMCPU pVCpu = &pVM->aCpus[i];
974
975	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
976	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
977	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
978	pbXStates += cbMaxXState;
979
980	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
981	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
982	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
983	pbXStates += cbMaxXState;
984
985	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
986	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
987	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
988	pbXStates += cbMaxXState;
989
990	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
991	}
992
993	/*
994	* Register saved state data item.
995	*/
996	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
997	NULL, cpumR3LiveExec, NULL,
998	NULL, cpumR3SaveExec, NULL,
999	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1000	if (RT_FAILURE(rc))
1001	return rc;
1002
1003	/*
1004	* Register info handlers and registers with the debugger facility.
1005	*/
1006	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1007	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1008	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1009	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1010	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1011	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1012	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1013	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1014	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1015	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1016	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1017	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1018	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1019
1020	rc = cpumR3DbgInit(pVM);
1021	if (RT_FAILURE(rc))
1022	return rc;
1023
1024	/*
1025	* Check if we need to workaround partial/leaky FPU handling.
1026	*/
1027	cpumR3CheckLeakyFpu(pVM);
1028
1029	/*
1030	* Initialize the Guest CPUID and MSR states.
1031	*/
1032	rc = cpumR3InitCpuIdAndMsrs(pVM);
1033	if (RT_FAILURE(rc))
1034	return rc;
1035
1036	/*
1037	* Allocate memory required by the guest hardware virtualization state.
1038	*/
1039	if (pVM->cpum.ro.GuestFeatures.fSvm)
1040	{
1041	rc = cpumR3AllocSvmHwVirtState(pVM);
1042	if (RT_FAILURE(rc))
1043	return rc;
1044	}
1045
1046	/*
1047	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1048	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1049	* of processors from (cpuid(4).eax >> 26) + 1.
1050	*
1051	* Note: this code is obsolete, but let's keep it here for reference.
1052	* Purpose is valid when we artificially cap the max std id to less than 4.
1053	*
1054	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
1055	* after VMINITCOMPLETED_HM.
1056	*/
1057	if (VM_IS_RAW_MODE_ENABLED(pVM))
1058	{
1059	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1060	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1061	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1062	}
1063
1064	CPUMR3Reset(pVM);
1065	return VINF_SUCCESS;
1066	}
1067
1068
1069	/**
1070	* Applies relocations to data and code managed by this
1071	* component. This function will be called at init and
1072	* whenever the VMM need to relocate it self inside the GC.
1073	*
1074	* The CPUM will update the addresses used by the switcher.
1075	*
1076	* @param pVM The cross context VM structure.
1077	*/
1078	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1079	{
1080	LogFlow(("CPUMR3Relocate\n"));
1081
1082	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1083	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1084
1085	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1086	{
1087	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1088	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1089	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1090	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1091
1092	/* Recheck the guest DRx values in raw-mode. */
1093	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1094	}
1095	}
1096
1097
1098	/**
1099	* Terminates the CPUM.
1100	*
1101	* Termination means cleaning up and freeing all resources,
1102	* the VM it self is at this point powered off or suspended.
1103	*
1104	* @returns VBox status code.
1105	* @param pVM The cross context VM structure.
1106	*/
1107	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1108	{
1109	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1110	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1111	{
1112	PVMCPU pVCpu = &pVM->aCpus[i];
1113	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1114
1115	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1116	pVCpu->cpum.s.uMagic = 0;
1117	pCtx->dr[5] = 0;
1118	}
1119	#endif
1120
1121	if (pVM->cpum.ro.GuestFeatures.fSvm)
1122	cpumR3FreeSvmHwVirtState(pVM);
1123	return VINF_SUCCESS;
1124	}
1125
1126
1127	/**
1128	* Resets a virtual CPU.
1129	*
1130	* Used by CPUMR3Reset and CPU hot plugging.
1131	*
1132	* @param pVM The cross context VM structure.
1133	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1134	* being reset. This may differ from the current EMT.
1135	*/
1136	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1137	{
1138	/** @todo anything different for VCPU > 0? */
1139	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1140
1141	/*
1142	* Initialize everything to ZERO first.
1143	*/
1144	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1145
1146	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1147	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1148	memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1149
1150	pVCpu->cpum.s.fUseFlags = fUseFlags;
1151
1152	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1153	pCtx->eip = 0x0000fff0;
1154	pCtx->edx = 0x00000600; /* P6 processor */
1155	pCtx->eflags.Bits.u1Reserved0 = 1;
1156
1157	pCtx->cs.Sel = 0xf000;
1158	pCtx->cs.ValidSel = 0xf000;
1159	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1160	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1161	pCtx->cs.u32Limit = 0x0000ffff;
1162	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1163	pCtx->cs.Attr.n.u1Present = 1;
1164	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1165
1166	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1167	pCtx->ds.u32Limit = 0x0000ffff;
1168	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1169	pCtx->ds.Attr.n.u1Present = 1;
1170	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1171
1172	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1173	pCtx->es.u32Limit = 0x0000ffff;
1174	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1175	pCtx->es.Attr.n.u1Present = 1;
1176	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1177
1178	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1179	pCtx->fs.u32Limit = 0x0000ffff;
1180	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1181	pCtx->fs.Attr.n.u1Present = 1;
1182	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1183
1184	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1185	pCtx->gs.u32Limit = 0x0000ffff;
1186	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1187	pCtx->gs.Attr.n.u1Present = 1;
1188	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1189
1190	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1191	pCtx->ss.u32Limit = 0x0000ffff;
1192	pCtx->ss.Attr.n.u1Present = 1;
1193	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1194	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1195
1196	pCtx->idtr.cbIdt = 0xffff;
1197	pCtx->gdtr.cbGdt = 0xffff;
1198
1199	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1200	pCtx->ldtr.u32Limit = 0xffff;
1201	pCtx->ldtr.Attr.n.u1Present = 1;
1202	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1203
1204	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1205	pCtx->tr.u32Limit = 0xffff;
1206	pCtx->tr.Attr.n.u1Present = 1;
1207	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1208
1209	pCtx->dr[6] = X86_DR6_INIT_VAL;
1210	pCtx->dr[7] = X86_DR7_INIT_VAL;
1211
1212	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1213	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1214	pFpuCtx->FCW = 0x37f;
1215
1216	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1217	IA-32 Processor States Following Power-up, Reset, or INIT */
1218	pFpuCtx->MXCSR = 0x1F80;
1219	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1220
1221	pCtx->aXcr[0] = XSAVE_C_X87;
1222	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1223	{
1224	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1225	as we don't know what happened before. (Bother optimize later?) */
1226	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1227	}
1228
1229	/*
1230	* MSRs.
1231	*/
1232	/* Init PAT MSR */
1233	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
1234
1235	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1236	* The Intel docs don't mention it. */
1237	Assert(!pCtx->msrEFER);
1238
1239	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1240	is supposed to be here, just trying provide useful/sensible values. */
1241	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1242	if (pRange)
1243	{
1244	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1245	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1246	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1247	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1248	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1249	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1250	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1251	}
1252
1253	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1254
1255	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1256	* called from each EMT while we're getting called by CPUMR3Reset()
1257	* iteratively on the same thread. Fix later. */
1258	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1259	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1260	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1261	#endif
1262
1263
1264	/* C-state control. Guesses. */
1265	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1266	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
1267	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
1268	* functionality. The default value must be different due to incompatible write mask.
1269	*/
1270	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
1271	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
1272	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
1273	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
1274
1275	/*
1276	* Hardware virtualization state.
1277	*/
1278	pCtx->hwvirt.fGif = true;
1279
1280	/* SVM. */
1281	if (pCtx->hwvirt.svm.CTX_SUFF(pVmcb))
1282	{
1283	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1284	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1285	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1286	}
1287	}
1288
1289
1290	/**
1291	* Resets the CPU.
1292	*
1293	* @returns VINF_SUCCESS.
1294	* @param pVM The cross context VM structure.
1295	*/
1296	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1297	{
1298	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1299	{
1300	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1301
1302	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1303	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1304
1305	/* Magic marker for searching in crash dumps. */
1306	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1307	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1308	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1309	#endif
1310	}
1311	}
1312
1313
1314
1315
1316	/**
1317	* Pass 0 live exec callback.
1318	*
1319	* @returns VINF_SSM_DONT_CALL_AGAIN.
1320	* @param pVM The cross context VM structure.
1321	* @param pSSM The saved state handle.
1322	* @param uPass The pass (0).
1323	*/
1324	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1325	{
1326	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1327	cpumR3SaveCpuId(pVM, pSSM);
1328	return VINF_SSM_DONT_CALL_AGAIN;
1329	}
1330
1331
1332	/**
1333	* Execute state save operation.
1334	*
1335	* @returns VBox status code.
1336	* @param pVM The cross context VM structure.
1337	* @param pSSM SSM operation handle.
1338	*/
1339	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1340	{
1341	/*
1342	* Save.
1343	*/
1344	SSMR3PutU32(pSSM, pVM->cCpus);
1345	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1346	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1347	{
1348	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1349
1350	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1351
1352	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1353	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1354	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1355	if (pGstCtx->fXStateMask != 0)
1356	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1357	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1358	{
1359	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1360	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1361	}
1362	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1363	{
1364	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1365	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1366	}
1367	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1368	{
1369	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1370	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1371	}
1372	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1373	{
1374	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1375	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1376	}
1377	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1378	{
1379	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1380	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1381	}
1382
1383	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1384	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1385	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1386	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1387	}
1388
1389	cpumR3SaveCpuId(pVM, pSSM);
1390	return VINF_SUCCESS;
1391	}
1392
1393
1394	/**
1395	* @callback_method_impl{FNSSMINTLOADPREP}
1396	*/
1397	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1398	{
1399	NOREF(pSSM);
1400	pVM->cpum.s.fPendingRestore = true;
1401	return VINF_SUCCESS;
1402	}
1403
1404
1405	/**
1406	* @callback_method_impl{FNSSMINTLOADEXEC}
1407	*/
1408	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1409	{
1410	int rc; /* Only for AssertRCReturn use. */
1411
1412	/*
1413	* Validate version.
1414	*/
1415	if ( uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1416	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1417	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1418	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1419	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
1420	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1421	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1422	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1423	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1424	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1425	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1426	{
1427	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1428	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1429	}
1430
1431	if (uPass == SSM_PASS_FINAL)
1432	{
1433	/*
1434	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1435	* really old SSM file versions.)
1436	*/
1437	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1438	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1439	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1440	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1441
1442	/*
1443	* Figure x86 and ctx field definitions to use for older states.
1444	*/
1445	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1446	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1447	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1448	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1449	{
1450	paCpumCtx1Fields = g_aCpumX87FieldsV16;
1451	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1452	}
1453	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1454	{
1455	paCpumCtx1Fields = g_aCpumX87FieldsMem;
1456	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1457	}
1458
1459	/*
1460	* The hyper state used to preceed the CPU count. Starting with
1461	* XSAVE it was moved down till after we've got the count.
1462	*/
1463	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1464	{
1465	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1466	{
1467	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1468	X86FXSTATE Ign;
1469	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1470	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1471	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1472	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1473	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1474	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1475	pVCpu->cpum.s.Hyper.rsp = uRSP;
1476	}
1477	}
1478
1479	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1480	{
1481	uint32_t cCpus;
1482	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1483	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1484	VERR_SSM_UNEXPECTED_DATA);
1485	}
1486	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1487	\|\| pVM->cCpus == 1,
1488	("cCpus=%u\n", pVM->cCpus),
1489	VERR_SSM_UNEXPECTED_DATA);
1490
1491	uint32_t cbMsrs = 0;
1492	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1493	{
1494	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1495	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1496	VERR_SSM_UNEXPECTED_DATA);
1497	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1498	VERR_SSM_UNEXPECTED_DATA);
1499	}
1500
1501	/*
1502	* Do the per-CPU restoring.
1503	*/
1504	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1505	{
1506	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1507	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1508
1509	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1510	{
1511	/*
1512	* The XSAVE saved state layout moved the hyper state down here.
1513	*/
1514	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1515	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1516	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1517	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1518	pVCpu->cpum.s.Hyper.rsp = uRSP;
1519	AssertRCReturn(rc, rc);
1520
1521	/*
1522	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1523	*/
1524	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1525	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1526	AssertRCReturn(rc, rc);
1527
1528	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1529	if (pGstCtx->fXStateMask != 0)
1530	{
1531	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1532	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1533	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1534	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1535	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1536	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1537	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1538	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1539	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1540	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1541	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1542	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1543	}
1544
1545	/* Check that the XCR0 mask is valid (invalid results in #GP). */
1546	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1547	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1548	{
1549	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
1550	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1551	VERR_CPUM_INVALID_XCR0);
1552	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1553	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1554	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1555	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1556	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1557	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1558	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1559	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1560	}
1561
1562	/* Check that the XCR1 is zero, as we don't implement it yet. */
1563	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1564
1565	/*
1566	* Restore the individual extended state components we support.
1567	*/
1568	if (pGstCtx->fXStateMask != 0)
1569	{
1570	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1571	0, g_aCpumXSaveHdrFields, NULL);
1572	AssertRCReturn(rc, rc);
1573	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1574	("bmXState=%#RX64 fXStateMask=%#RX64\n",
1575	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1576	VERR_CPUM_INVALID_XSAVE_HDR);
1577	}
1578	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1579	{
1580	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1581	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1582	}
1583	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1584	{
1585	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1586	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1587	}
1588	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1589	{
1590	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1591	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1592	}
1593	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1594	{
1595	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1596	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1597	}
1598	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1599	{
1600	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1601	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1602	}
1603	}
1604	else
1605	{
1606	/*
1607	* Pre XSAVE saved state.
1608	*/
1609	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1610	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1611	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1612	}
1613
1614	/*
1615	* Restore a couple of flags and the MSRs.
1616	*/
1617	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1618	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1619
1620	rc = VINF_SUCCESS;
1621	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1622	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1623	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1624	{
1625	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1626	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1627	}
1628	AssertRCReturn(rc, rc);
1629
1630	/* REM and other may have cleared must-be-one fields in DR6 and
1631	DR7, fix these. */
1632	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
1633	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
1634	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
1635	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
1636	}
1637
1638	/* Older states does not have the internal selector register flags
1639	and valid selector value. Supply those. */
1640	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1641	{
1642	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1643	{
1644	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1645	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
1646	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1647	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1648	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1649	if (fValid)
1650	{
1651	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1652	{
1653	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1654	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1655	}
1656
1657	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1658	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1659	}
1660	else
1661	{
1662	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1663	{
1664	paSelReg[iSelReg].fFlags = 0;
1665	paSelReg[iSelReg].ValidSel = 0;
1666	}
1667
1668	/* This might not be 104% correct, but I think it's close
1669	enough for all practical purposes... (REM always loaded
1670	LDTR registers.) */
1671	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1672	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1673	}
1674	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1675	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1676	}
1677	}
1678
1679	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1680	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1681	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1682	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1683	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1684
1685	/*
1686	* A quick sanity check.
1687	*/
1688	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1689	{
1690	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1691	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1692	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1693	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1694	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1695	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1696	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1697	}
1698	}
1699
1700	pVM->cpum.s.fPendingRestore = false;
1701
1702	/*
1703	* Guest CPUIDs.
1704	*/
1705	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1706	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1707	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1708	}
1709
1710
1711	/**
1712	* @callback_method_impl{FNSSMINTLOADDONE}
1713	*/
1714	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1715	{
1716	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1717	return VINF_SUCCESS;
1718
1719	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1720	if (pVM->cpum.s.fPendingRestore)
1721	{
1722	LogRel(("CPUM: Missing state!\n"));
1723	return VERR_INTERNAL_ERROR_2;
1724	}
1725
1726	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1727	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1728	{
1729	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1730
1731	/* Notify PGM of the NXE states in case they've changed. */
1732	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1733
1734	/* During init. this is done in CPUMR3InitCompleted(). */
1735	if (fSupportsLongMode)
1736	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
1737	}
1738	return VINF_SUCCESS;
1739	}
1740
1741
1742	/**
1743	* Checks if the CPUM state restore is still pending.
1744	*
1745	* @returns true / false.
1746	* @param pVM The cross context VM structure.
1747	*/
1748	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1749	{
1750	return pVM->cpum.s.fPendingRestore;
1751	}
1752
1753
1754	/**
1755	* Formats the EFLAGS value into mnemonics.
1756	*
1757	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1758	* @param efl The EFLAGS value.
1759	*/
1760	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1761	{
1762	/*
1763	* Format the flags.
1764	*/
1765	static const struct
1766	{
1767	const char pszSet; const char pszClear; uint32_t fFlag;
1768	} s_aFlags[] =
1769	{
1770	{ "vip",NULL, X86_EFL_VIP },
1771	{ "vif",NULL, X86_EFL_VIF },
1772	{ "ac", NULL, X86_EFL_AC },
1773	{ "vm", NULL, X86_EFL_VM },
1774	{ "rf", NULL, X86_EFL_RF },
1775	{ "nt", NULL, X86_EFL_NT },
1776	{ "ov", "nv", X86_EFL_OF },
1777	{ "dn", "up", X86_EFL_DF },
1778	{ "ei", "di", X86_EFL_IF },
1779	{ "tf", NULL, X86_EFL_TF },
1780	{ "nt", "pl", X86_EFL_SF },
1781	{ "nz", "zr", X86_EFL_ZF },
1782	{ "ac", "na", X86_EFL_AF },
1783	{ "po", "pe", X86_EFL_PF },
1784	{ "cy", "nc", X86_EFL_CF },
1785	};
1786	char *psz = pszEFlags;
1787	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1788	{
1789	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1790	if (pszAdd)
1791	{
1792	strcpy(psz, pszAdd);
1793	psz += strlen(pszAdd);
1794	*psz++ = ' ';
1795	}
1796	}
1797	psz[-1] = '\0';
1798	}
1799
1800
1801	/**
1802	* Formats a full register dump.
1803	*
1804	* @param pVM The cross context VM structure.
1805	* @param pCtx The context to format.
1806	* @param pCtxCore The context core to format.
1807	* @param pHlp Output functions.
1808	* @param enmType The dump type.
1809	* @param pszPrefix Register name prefix.
1810	*/
1811	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1812	const char *pszPrefix)
1813	{
1814	NOREF(pVM);
1815
1816	/*
1817	* Format the EFLAGS.
1818	*/
1819	uint32_t efl = pCtxCore->eflags.u32;
1820	char szEFlags[80];
1821	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1822
1823	/*
1824	* Format the registers.
1825	*/
1826	switch (enmType)
1827	{
1828	case CPUMDUMPTYPE_TERSE:
1829	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1830	pHlp->pfnPrintf(pHlp,
1831	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1832	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1833	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1834	"%sr14=%016RX64 %sr15=%016RX64\n"
1835	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1836	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1837	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1838	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1839	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1840	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1841	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1842	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1843	else
1844	pHlp->pfnPrintf(pHlp,
1845	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1846	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1847	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1848	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1849	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1850	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1851	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1852	break;
1853
1854	case CPUMDUMPTYPE_DEFAULT:
1855	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1856	pHlp->pfnPrintf(pHlp,
1857	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1858	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1859	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1860	"%sr14=%016RX64 %sr15=%016RX64\n"
1861	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1862	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1863	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1864	,
1865	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1866	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1867	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1868	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1869	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1870	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1871	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1872	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1873	else
1874	pHlp->pfnPrintf(pHlp,
1875	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1876	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1877	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1878	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1879	,
1880	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1881	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1882	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1883	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1884	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1885	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1886	break;
1887
1888	case CPUMDUMPTYPE_VERBOSE:
1889	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1890	pHlp->pfnPrintf(pHlp,
1891	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1892	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1893	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1894	"%sr14=%016RX64 %sr15=%016RX64\n"
1895	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1896	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1897	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1898	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1899	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1900	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1901	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1902	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1903	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1904	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1905	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1906	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1907	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1908	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1909	,
1910	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1911	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1912	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1913	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1914	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1915	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1916	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
1917	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
1918	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
1919	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
1920	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1921	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1922	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1923	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1924	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1925	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1926	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1927	else
1928	pHlp->pfnPrintf(pHlp,
1929	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1930	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1931	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
1932	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
1933	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
1934	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
1935	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
1936	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
1937	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1938	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1939	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1940	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
1941	,
1942	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1943	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1944	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
1945	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
1946	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
1947	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
1948	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
1949	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1950	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
1951	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
1952	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
1953	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
1954
1955	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
1956	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
1957	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
1958	if (pCtx->CTX_SUFF(pXState))
1959	{
1960	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
1961	pHlp->pfnPrintf(pHlp,
1962	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
1963	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
1964	,
1965	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
1966	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
1967	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
1968	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
1969	);
1970	/*
1971	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
1972	* not (FP)R0-7 as Intel SDM suggests.
1973	*/
1974	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
1975	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
1976	{
1977	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
1978	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
1979	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
1980	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
1981	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
1982	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
1983	iExponent -= 16383; /* subtract bias */
1984	/** @todo This isn't entirenly correct and needs more work! */
1985	pHlp->pfnPrintf(pHlp,
1986	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
1987	pszPrefix, iST, pszPrefix, iFPR,
1988	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
1989	uTag, chSign, iInteger, u64Fraction, iExponent);
1990	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
1991	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
1992	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
1993	else
1994	pHlp->pfnPrintf(pHlp, "\n");
1995	}
1996
1997	/* XMM/YMM/ZMM registers. */
1998	if (pCtx->fXStateMask & XSAVE_C_YMM)
1999	{
2000	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2001	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2002	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2003	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2004	pszPrefix, i, i < 10 ? " " : "",
2005	pYmmHiCtx->aYmmHi[i].au32[3],
2006	pYmmHiCtx->aYmmHi[i].au32[2],
2007	pYmmHiCtx->aYmmHi[i].au32[1],
2008	pYmmHiCtx->aYmmHi[i].au32[0],
2009	pFpuCtx->aXMM[i].au32[3],
2010	pFpuCtx->aXMM[i].au32[2],
2011	pFpuCtx->aXMM[i].au32[1],
2012	pFpuCtx->aXMM[i].au32[0]);
2013	else
2014	{
2015	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2016	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2017	pHlp->pfnPrintf(pHlp,
2018	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2019	pszPrefix, i, i < 10 ? " " : "",
2020	pZmmHi256->aHi256Regs[i].au32[7],
2021	pZmmHi256->aHi256Regs[i].au32[6],
2022	pZmmHi256->aHi256Regs[i].au32[5],
2023	pZmmHi256->aHi256Regs[i].au32[4],
2024	pZmmHi256->aHi256Regs[i].au32[3],
2025	pZmmHi256->aHi256Regs[i].au32[2],
2026	pZmmHi256->aHi256Regs[i].au32[1],
2027	pZmmHi256->aHi256Regs[i].au32[0],
2028	pYmmHiCtx->aYmmHi[i].au32[3],
2029	pYmmHiCtx->aYmmHi[i].au32[2],
2030	pYmmHiCtx->aYmmHi[i].au32[1],
2031	pYmmHiCtx->aYmmHi[i].au32[0],
2032	pFpuCtx->aXMM[i].au32[3],
2033	pFpuCtx->aXMM[i].au32[2],
2034	pFpuCtx->aXMM[i].au32[1],
2035	pFpuCtx->aXMM[i].au32[0]);
2036
2037	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2038	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2039	pHlp->pfnPrintf(pHlp,
2040	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2041	pszPrefix, i + 16,
2042	pZmm16Hi->aRegs[i].au32[15],
2043	pZmm16Hi->aRegs[i].au32[14],
2044	pZmm16Hi->aRegs[i].au32[13],
2045	pZmm16Hi->aRegs[i].au32[12],
2046	pZmm16Hi->aRegs[i].au32[11],
2047	pZmm16Hi->aRegs[i].au32[10],
2048	pZmm16Hi->aRegs[i].au32[9],
2049	pZmm16Hi->aRegs[i].au32[8],
2050	pZmm16Hi->aRegs[i].au32[7],
2051	pZmm16Hi->aRegs[i].au32[6],
2052	pZmm16Hi->aRegs[i].au32[5],
2053	pZmm16Hi->aRegs[i].au32[4],
2054	pZmm16Hi->aRegs[i].au32[3],
2055	pZmm16Hi->aRegs[i].au32[2],
2056	pZmm16Hi->aRegs[i].au32[1],
2057	pZmm16Hi->aRegs[i].au32[0]);
2058	}
2059	}
2060	else
2061	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2062	pHlp->pfnPrintf(pHlp,
2063	i & 1
2064	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2065	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2066	pszPrefix, i, i < 10 ? " " : "",
2067	pFpuCtx->aXMM[i].au32[3],
2068	pFpuCtx->aXMM[i].au32[2],
2069	pFpuCtx->aXMM[i].au32[1],
2070	pFpuCtx->aXMM[i].au32[0]);
2071
2072	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2073	{
2074	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2075	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2076	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2077	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2078	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2079	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2080	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2081	}
2082
2083	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2084	{
2085	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2086	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2087	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2088	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2089	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2090	}
2091
2092	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2093	{
2094	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2095	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2096	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2097	}
2098
2099	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2100	if (pFpuCtx->au32RsrvdRest[i])
2101	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2102	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2103	}
2104
2105	pHlp->pfnPrintf(pHlp,
2106	"%sEFER =%016RX64\n"
2107	"%sPAT =%016RX64\n"
2108	"%sSTAR =%016RX64\n"
2109	"%sCSTAR =%016RX64\n"
2110	"%sLSTAR =%016RX64\n"
2111	"%sSFMASK =%016RX64\n"
2112	"%sKERNELGSBASE =%016RX64\n",
2113	pszPrefix, pCtx->msrEFER,
2114	pszPrefix, pCtx->msrPAT,
2115	pszPrefix, pCtx->msrSTAR,
2116	pszPrefix, pCtx->msrCSTAR,
2117	pszPrefix, pCtx->msrLSTAR,
2118	pszPrefix, pCtx->msrSFMASK,
2119	pszPrefix, pCtx->msrKERNELGSBASE);
2120	break;
2121	}
2122	}
2123
2124
2125	/**
2126	* Display all cpu states and any other cpum info.
2127	*
2128	* @param pVM The cross context VM structure.
2129	* @param pHlp The info helper functions.
2130	* @param pszArgs Arguments, ignored.
2131	*/
2132	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2133	{
2134	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2135	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2136	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2137	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2138	cpumR3InfoHost(pVM, pHlp, pszArgs);
2139	}
2140
2141
2142	/**
2143	* Parses the info argument.
2144	*
2145	* The argument starts with 'verbose', 'terse' or 'default' and then
2146	* continues with the comment string.
2147	*
2148	* @param pszArgs The pointer to the argument string.
2149	* @param penmType Where to store the dump type request.
2150	* @param ppszComment Where to store the pointer to the comment string.
2151	*/
2152	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2153	{
2154	if (!pszArgs)
2155	{
2156	*penmType = CPUMDUMPTYPE_DEFAULT;
2157	*ppszComment = "";
2158	}
2159	else
2160	{
2161	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2162	{
2163	pszArgs += 7;
2164	*penmType = CPUMDUMPTYPE_VERBOSE;
2165	}
2166	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2167	{
2168	pszArgs += 5;
2169	*penmType = CPUMDUMPTYPE_TERSE;
2170	}
2171	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2172	{
2173	pszArgs += 7;
2174	*penmType = CPUMDUMPTYPE_DEFAULT;
2175	}
2176	else
2177	*penmType = CPUMDUMPTYPE_DEFAULT;
2178	*ppszComment = RTStrStripL(pszArgs);
2179	}
2180	}
2181
2182
2183	/**
2184	* Display the guest cpu state.
2185	*
2186	* @param pVM The cross context VM structure.
2187	* @param pHlp The info helper functions.
2188	* @param pszArgs Arguments.
2189	*/
2190	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2191	{
2192	CPUMDUMPTYPE enmType;
2193	const char *pszComment;
2194	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2195
2196	PVMCPU pVCpu = VMMGetCpu(pVM);
2197	if (!pVCpu)
2198	pVCpu = &pVM->aCpus[0];
2199
2200	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2201
2202	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2203	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2204	}
2205
2206
2207	/**
2208	* Displays an SVM VMCB control area.
2209	*
2210	* @param pHlp The info helper functions.
2211	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
2212	* @param pszPrefix Caller specified string prefix.
2213	*/
2214	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
2215	{
2216	AssertReturnVoid(pHlp);
2217	AssertReturnVoid(pVmcbCtrl);
2218
2219	pHlp->pfnPrintf(pHlp, "%su16InterceptRdCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
2220	pHlp->pfnPrintf(pHlp, "%su16InterceptWrCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
2221	pHlp->pfnPrintf(pHlp, "%su16InterceptRdDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
2222	pHlp->pfnPrintf(pHlp, "%su16InterceptWrDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
2223	pHlp->pfnPrintf(pHlp, "%su32InterceptXcpt = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
2224	pHlp->pfnPrintf(pHlp, "%su64InterceptCtrl = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
2225	pHlp->pfnPrintf(pHlp, "%su16PauseFilterThreshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
2226	pHlp->pfnPrintf(pHlp, "%su16PauseFilterCount = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
2227	pHlp->pfnPrintf(pHlp, "%su64IOPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
2228	pHlp->pfnPrintf(pHlp, "%su64MSRPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
2229	pHlp->pfnPrintf(pHlp, "%su64TSCOffset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
2230	pHlp->pfnPrintf(pHlp, "%sTLBCtrl\n", pszPrefix);
2231	pHlp->pfnPrintf(pHlp, "%s u32ASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
2232	pHlp->pfnPrintf(pHlp, "%s u8TLBFlush = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
2233	pHlp->pfnPrintf(pHlp, "%sIntCtrl\n", pszPrefix);
2234	pHlp->pfnPrintf(pHlp, "%s u8VTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
2235	pHlp->pfnPrintf(pHlp, "%s u1VIrqPending = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
2236	pHlp->pfnPrintf(pHlp, "%s u1VGif = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
2237	pHlp->pfnPrintf(pHlp, "%s u4VIntrPrio = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
2238	pHlp->pfnPrintf(pHlp, "%s u1IgnoreTPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
2239	pHlp->pfnPrintf(pHlp, "%s u1VIntrMasking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
2240	pHlp->pfnPrintf(pHlp, "%s u1VGifEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
2241	pHlp->pfnPrintf(pHlp, "%s u1AvicEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
2242	pHlp->pfnPrintf(pHlp, "%s u8VIntrVector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
2243	pHlp->pfnPrintf(pHlp, "%sIntShadow\n", pszPrefix);
2244	pHlp->pfnPrintf(pHlp, "%s u1IntShadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
2245	pHlp->pfnPrintf(pHlp, "%s u1GuestIntMask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
2246	pHlp->pfnPrintf(pHlp, "%su64ExitCode = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
2247	pHlp->pfnPrintf(pHlp, "%su64ExitInfo1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
2248	pHlp->pfnPrintf(pHlp, "%su64ExitInfo2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
2249	pHlp->pfnPrintf(pHlp, "%sExitIntInfo\n", pszPrefix);
2250	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
2251	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
2252	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
2253	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
2254	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
2255	pHlp->pfnPrintf(pHlp, "%sNestedPaging and SEV\n", pszPrefix);
2256	pHlp->pfnPrintf(pHlp, "%s u1NestedPaging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPaging.n.u1NestedPaging);
2257	pHlp->pfnPrintf(pHlp, "%s u1Sev = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPaging.n.u1Sev);
2258	pHlp->pfnPrintf(pHlp, "%s u1SevEs = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPaging.n.u1SevEs);
2259	pHlp->pfnPrintf(pHlp, "%sAvicBar\n", pszPrefix);
2260	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
2261	pHlp->pfnPrintf(pHlp, "%sEventInject\n", pszPrefix);
2262	pHlp->pfnPrintf(pHlp, "%s EventInject\n", pszPrefix);
2263	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
2264	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
2265	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
2266	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
2267	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
2268	pHlp->pfnPrintf(pHlp, "%su64NestedPagingCR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
2269	pHlp->pfnPrintf(pHlp, "%sLBR virtualization\n", pszPrefix);
2270	pHlp->pfnPrintf(pHlp, "%s u1LbrVirt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
2271	pHlp->pfnPrintf(pHlp, "%s u1VirtVmsaveVmload = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
2272	pHlp->pfnPrintf(pHlp, "%su32VmcbCleanBits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
2273	pHlp->pfnPrintf(pHlp, "%su64NextRIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
2274	pHlp->pfnPrintf(pHlp, "%scbInstrFetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
2275	pHlp->pfnPrintf(pHlp, "%sabInstr = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
2276	pHlp->pfnPrintf(pHlp, "%sAvicBackingPagePtr\n", pszPrefix);
2277	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
2278	pHlp->pfnPrintf(pHlp, "%sAvicLogicalTablePtr\n", pszPrefix);
2279	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
2280	pHlp->pfnPrintf(pHlp, "%sAvicPhysicalTablePtr\n", pszPrefix);
2281	pHlp->pfnPrintf(pHlp, "%s u8LastGuestCoreId = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
2282	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
2283	}
2284
2285
2286	/**
2287	* Helper for dumping the SVM VMCB selector registers.
2288	*
2289	* @param pHlp The info helper functions.
2290	* @param pSel Pointer to the SVM selector register.
2291	* @param pszName Name of the selector.
2292	* @param pszPrefix Caller specified string prefix.
2293	*/
2294	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
2295	{
2296	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
2297	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
2298	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
2299	}
2300
2301
2302	/**
2303	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
2304	*
2305	* @param pHlp The info helper functions.
2306	* @param pXdtr Pointer to the descriptor table register.
2307	* @param pszName Name of the descriptor table register.
2308	* @param pszPrefix Caller specified string prefix.
2309	*/
2310	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
2311	{
2312	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
2313	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
2314	}
2315
2316
2317	/**
2318	* Displays an SVM VMCB state-save area.
2319	*
2320	* @param pHlp The info helper functions.
2321	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
2322	* @param pszPrefix Caller specified string prefix.
2323	*/
2324	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
2325	{
2326	AssertReturnVoid(pHlp);
2327	AssertReturnVoid(pVmcbStateSave);
2328
2329	char szEFlags[80];
2330	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
2331
2332	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
2333	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
2334	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
2335	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
2336	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
2337	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
2338	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
2339	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
2340	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
2341	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
2342	pHlp->pfnPrintf(pHlp, "%su8CPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
2343	pHlp->pfnPrintf(pHlp, "%su64EFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
2344	pHlp->pfnPrintf(pHlp, "%su64CR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
2345	pHlp->pfnPrintf(pHlp, "%su64CR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
2346	pHlp->pfnPrintf(pHlp, "%su64CR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
2347	pHlp->pfnPrintf(pHlp, "%su64DR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
2348	pHlp->pfnPrintf(pHlp, "%su64DR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
2349	pHlp->pfnPrintf(pHlp, "%su64RFlags = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
2350	pHlp->pfnPrintf(pHlp, "%su64RIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
2351	pHlp->pfnPrintf(pHlp, "%su64RSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
2352	pHlp->pfnPrintf(pHlp, "%su64RAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
2353	pHlp->pfnPrintf(pHlp, "%su64STAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
2354	pHlp->pfnPrintf(pHlp, "%su64LSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
2355	pHlp->pfnPrintf(pHlp, "%su64CSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
2356	pHlp->pfnPrintf(pHlp, "%su64SFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
2357	pHlp->pfnPrintf(pHlp, "%su64KernelGSBase = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
2358	pHlp->pfnPrintf(pHlp, "%su64SysEnterCS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
2359	pHlp->pfnPrintf(pHlp, "%su64SysEnterEIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
2360	pHlp->pfnPrintf(pHlp, "%su64SysEnterESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
2361	pHlp->pfnPrintf(pHlp, "%su64CR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
2362	pHlp->pfnPrintf(pHlp, "%su64PAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
2363	pHlp->pfnPrintf(pHlp, "%su64DBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
2364	pHlp->pfnPrintf(pHlp, "%su64BR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
2365	pHlp->pfnPrintf(pHlp, "%su64BR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
2366	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPFROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
2367	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPTO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
2368	}
2369
2370
2371	/**
2372	* Display the guest's hardware-virtualization cpu state.
2373	*
2374	* @param pVM The cross context VM structure.
2375	* @param pHlp The info helper functions.
2376	* @param pszArgs Arguments, ignored.
2377	*/
2378	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2379	{
2380	RT_NOREF(pszArgs);
2381
2382	PVMCPU pVCpu = VMMGetCpu(pVM);
2383	if (!pVCpu)
2384	pVCpu = &pVM->aCpus[0];
2385
2386	/*
2387	* Figure out what to dump.
2388	*
2389	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
2390	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2391	* dump hwvirt. state when the guest CPU is executing a nested-guest.
2392	*/
2393	/** @todo perhaps make this configurable through pszArgs, depending on how much
2394	* noise we wish to accept when nested hwvirt. isn't used. */
2395	#define CPUMHWVIRTDUMP_NONE (0)
2396	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2397	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2398	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2399	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2400
2401	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2402	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2403	uint8_t const idxHwvirtState = CPUMIsGuestInSvmNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_SVM
2404	: CPUMIsGuestInVmxNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE;
2405	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2406	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2407	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2408	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
2409
2410	/*
2411	* Dump it.
2412	*/
2413	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2414
2415	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2416	{
2417	pHlp->pfnPrintf(pHlp, "fGif = %RTbool\n", pCtx->hwvirt.fGif);
2418	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2419	}
2420	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
2421	":" : "");
2422	if (fDumpState & CPUMHWVIRTDUMP_SVM)
2423	{
2424	char szEFlags[80];
2425	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
2426
2427	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2428	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2429	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2430	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2431	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
2432	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
2433	pHlp->pfnPrintf(pHlp, " HostState:\n");
2434	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2435	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2436	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2437	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2438	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2439	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2440	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2441	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
2442	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2443	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2444	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2445	pSel = &pCtx->hwvirt.svm.HostState.cs;
2446	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2447	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2448	pSel = &pCtx->hwvirt.svm.HostState.ss;
2449	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2450	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2451	pSel = &pCtx->hwvirt.svm.HostState.ds;
2452	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2453	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2454	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2455	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2456	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2457	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2458	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2459	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2460	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2461	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2462	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2463	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2464	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2465	}
2466
2467	/** @todo Intel. */
2468	#if 0
2469	if (fDumpState & CPUMHWVIRTDUMP_VMX)
2470	{
2471	}
2472	#endif
2473
2474	#undef CPUMHWVIRTDUMP_NONE
2475	#undef CPUMHWVIRTDUMP_COMMON
2476	#undef CPUMHWVIRTDUMP_SVM
2477	#undef CPUMHWVIRTDUMP_VMX
2478	#undef CPUMHWVIRTDUMP_LAST
2479	#undef CPUMHWVIRTDUMP_ALL
2480	}
2481
2482	/**
2483	* Display the current guest instruction
2484	*
2485	* @param pVM The cross context VM structure.
2486	* @param pHlp The info helper functions.
2487	* @param pszArgs Arguments, ignored.
2488	*/
2489	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2490	{
2491	NOREF(pszArgs);
2492
2493	PVMCPU pVCpu = VMMGetCpu(pVM);
2494	if (!pVCpu)
2495	pVCpu = &pVM->aCpus[0];
2496
2497	char szInstruction[256];
2498	szInstruction[0] = '\0';
2499	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2500	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2501	}
2502
2503
2504	/**
2505	* Display the hypervisor cpu state.
2506	*
2507	* @param pVM The cross context VM structure.
2508	* @param pHlp The info helper functions.
2509	* @param pszArgs Arguments, ignored.
2510	*/
2511	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2512	{
2513	PVMCPU pVCpu = VMMGetCpu(pVM);
2514	if (!pVCpu)
2515	pVCpu = &pVM->aCpus[0];
2516
2517	CPUMDUMPTYPE enmType;
2518	const char *pszComment;
2519	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2520	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2521	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2522	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2523	}
2524
2525
2526	/**
2527	* Display the host cpu state.
2528	*
2529	* @param pVM The cross context VM structure.
2530	* @param pHlp The info helper functions.
2531	* @param pszArgs Arguments, ignored.
2532	*/
2533	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2534	{
2535	CPUMDUMPTYPE enmType;
2536	const char *pszComment;
2537	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2538	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2539
2540	PVMCPU pVCpu = VMMGetCpu(pVM);
2541	if (!pVCpu)
2542	pVCpu = &pVM->aCpus[0];
2543	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2544
2545	/*
2546	* Format the EFLAGS.
2547	*/
2548	#if HC_ARCH_BITS == 32
2549	uint32_t efl = pCtx->eflags.u32;
2550	#else
2551	uint64_t efl = pCtx->rflags;
2552	#endif
2553	char szEFlags[80];
2554	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2555
2556	/*
2557	* Format the registers.
2558	*/
2559	#if HC_ARCH_BITS == 32
2560	pHlp->pfnPrintf(pHlp,
2561	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2562	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2563	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2564	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2565	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2566	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2567	,
2568	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2569	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2570	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2571	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2572	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2573	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2574	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2575	#else
2576	pHlp->pfnPrintf(pHlp,
2577	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2578	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2579	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2580	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2581	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2582	"r14=%016RX64 r15=%016RX64\n"
2583	"iopl=%d %31s\n"
2584	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2585	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2586	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2587	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2588	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2589	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2590	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2591	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2592	,
2593	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2594	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2595	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2596	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2597	pCtx->r11, pCtx->r12, pCtx->r13,
2598	pCtx->r14, pCtx->r15,
2599	X86_EFL_GET_IOPL(efl), szEFlags,
2600	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2601	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2602	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2603	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2604	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2605	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2606	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2607	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2608	#endif
2609	}
2610
2611	/**
2612	* Structure used when disassembling and instructions in DBGF.
2613	* This is used so the reader function can get the stuff it needs.
2614	*/
2615	typedef struct CPUMDISASSTATE
2616	{
2617	/** Pointer to the CPU structure. */
2618	PDISCPUSTATE pCpu;
2619	/** Pointer to the VM. */
2620	PVM pVM;
2621	/** Pointer to the VMCPU. */
2622	PVMCPU pVCpu;
2623	/** Pointer to the first byte in the segment. */
2624	RTGCUINTPTR GCPtrSegBase;
2625	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
2626	RTGCUINTPTR GCPtrSegEnd;
2627	/** The size of the segment minus 1. */
2628	RTGCUINTPTR cbSegLimit;
2629	/** Pointer to the current page - R3 Ptr. */
2630	void const *pvPageR3;
2631	/** Pointer to the current page - GC Ptr. */
2632	RTGCPTR pvPageGC;
2633	/** The lock information that PGMPhysReleasePageMappingLock needs. */
2634	PGMPAGEMAPLOCK PageMapLock;
2635	/** Whether the PageMapLock is valid or not. */
2636	bool fLocked;
2637	/** 64 bits mode or not. */
2638	bool f64Bits;
2639	} CPUMDISASSTATE, *PCPUMDISASSTATE;
2640
2641
2642	/**
2643	* @callback_method_impl{FNDISREADBYTES}
2644	*/
2645	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2646	{
2647	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2648	for (;;)
2649	{
2650	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2651
2652	/*
2653	* Need to update the page translation?
2654	*/
2655	if ( !pState->pvPageR3
2656	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2657	{
2658	int rc = VINF_SUCCESS;
2659
2660	/* translate the address */
2661	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2662	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
2663	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2664	{
2665	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2666	if (!pState->pvPageR3)
2667	rc = VERR_INVALID_POINTER;
2668	}
2669	else
2670	{
2671	/* Release mapping lock previously acquired. */
2672	if (pState->fLocked)
2673	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2674	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2675	pState->fLocked = RT_SUCCESS_NP(rc);
2676	}
2677	if (RT_FAILURE(rc))
2678	{
2679	pState->pvPageR3 = NULL;
2680	return rc;
2681	}
2682	}
2683
2684	/*
2685	* Check the segment limit.
2686	*/
2687	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2688	return VERR_OUT_OF_SELECTOR_BOUNDS;
2689
2690	/*
2691	* Calc how much we can read.
2692	*/
2693	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2694	if (!pState->f64Bits)
2695	{
2696	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2697	if (cb > cbSeg && cbSeg)
2698	cb = cbSeg;
2699	}
2700	if (cb > cbMaxRead)
2701	cb = cbMaxRead;
2702
2703	/*
2704	* Read and advance or exit.
2705	*/
2706	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2707	offInstr += (uint8_t)cb;
2708	if (cb >= cbMinRead)
2709	{
2710	pDis->cbCachedInstr = offInstr;
2711	return VINF_SUCCESS;
2712	}
2713	cbMinRead -= (uint8_t)cb;
2714	cbMaxRead -= (uint8_t)cb;
2715	}
2716	}
2717
2718
2719	/**
2720	* Disassemble an instruction and return the information in the provided structure.
2721	*
2722	* @returns VBox status code.
2723	* @param pVM The cross context VM structure.
2724	* @param pVCpu The cross context virtual CPU structure.
2725	* @param pCtx Pointer to the guest CPU context.
2726	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
2727	* @param pCpu Disassembly state.
2728	* @param pszPrefix String prefix for logging (debug only).
2729	*
2730	*/
2731	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2732	const char *pszPrefix)
2733	{
2734	CPUMDISASSTATE State;
2735	int rc;
2736
2737	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2738	State.pCpu = pCpu;
2739	State.pvPageGC = 0;
2740	State.pvPageR3 = NULL;
2741	State.pVM = pVM;
2742	State.pVCpu = pVCpu;
2743	State.fLocked = false;
2744	State.f64Bits = false;
2745
2746	/*
2747	* Get selector information.
2748	*/
2749	DISCPUMODE enmDisCpuMode;
2750	if ( (pCtx->cr0 & X86_CR0_PE)
2751	&& pCtx->eflags.Bits.u1VM == 0)
2752	{
2753	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2754	{
2755	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2756	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2757	# endif
2758	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2759	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2760	}
2761	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2762	State.GCPtrSegBase = pCtx->cs.u64Base;
2763	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2764	State.cbSegLimit = pCtx->cs.u32Limit;
2765	enmDisCpuMode = (State.f64Bits)
2766	? DISCPUMODE_64BIT
2767	: pCtx->cs.Attr.n.u1DefBig
2768	? DISCPUMODE_32BIT
2769	: DISCPUMODE_16BIT;
2770	}
2771	else
2772	{
2773	/* real or V86 mode */
2774	enmDisCpuMode = DISCPUMODE_16BIT;
2775	State.GCPtrSegBase = pCtx->cs.Sel * 16;
2776	State.GCPtrSegEnd = 0xFFFFFFFF;
2777	State.cbSegLimit = 0xFFFFFFFF;
2778	}
2779
2780	/*
2781	* Disassemble the instruction.
2782	*/
2783	uint32_t cbInstr;
2784	#ifndef LOG_ENABLED
2785	RT_NOREF_PV(pszPrefix);
2786	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2787	if (RT_SUCCESS(rc))
2788	{
2789	#else
2790	char szOutput[160];
2791	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2792	pCpu, &cbInstr, szOutput, sizeof(szOutput));
2793	if (RT_SUCCESS(rc))
2794	{
2795	/* log it */
2796	if (pszPrefix)
2797	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2798	else
2799	Log(("%s", szOutput));
2800	#endif
2801	rc = VINF_SUCCESS;
2802	}
2803	else
2804	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2805
2806	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
2807	if (State.fLocked)
2808	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2809
2810	return rc;
2811	}
2812
2813
2814
2815	/**
2816	* API for controlling a few of the CPU features found in CR4.
2817	*
2818	* Currently only X86_CR4_TSD is accepted as input.
2819	*
2820	* @returns VBox status code.
2821	*
2822	* @param pVM The cross context VM structure.
2823	* @param fOr The CR4 OR mask.
2824	* @param fAnd The CR4 AND mask.
2825	*/
2826	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2827	{
2828	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2829	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2830
2831	pVM->cpum.s.CR4.OrMask &= fAnd;
2832	pVM->cpum.s.CR4.OrMask \|= fOr;
2833
2834	return VINF_SUCCESS;
2835	}
2836
2837
2838	/**
2839	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2840	*
2841	* Only REM should ever call this function!
2842	*
2843	* @returns The changed flags.
2844	* @param pVCpu The cross context virtual CPU structure.
2845	* @param puCpl Where to return the current privilege level (CPL).
2846	*/
2847	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2848	{
2849	Assert(!pVCpu->cpum.s.fRawEntered);
2850	Assert(!pVCpu->cpum.s.fRemEntered);
2851
2852	/*
2853	* Get the CPL first.
2854	*/
2855	*puCpl = CPUMGetGuestCPL(pVCpu);
2856
2857	/*
2858	* Get and reset the flags.
2859	*/
2860	uint32_t fFlags = pVCpu->cpum.s.fChanged;
2861	pVCpu->cpum.s.fChanged = 0;
2862
2863	/** @todo change the switcher to use the fChanged flags. */
2864	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2865	{
2866	fFlags \|= CPUM_CHANGED_FPU_REM;
2867	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2868	}
2869
2870	pVCpu->cpum.s.fRemEntered = true;
2871	return fFlags;
2872	}
2873
2874
2875	/**
2876	* Leaves REM.
2877	*
2878	* @param pVCpu The cross context virtual CPU structure.
2879	* @param fNoOutOfSyncSels This is @c false if there are out of sync
2880	* registers.
2881	*/
2882	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2883	{
2884	Assert(!pVCpu->cpum.s.fRawEntered);
2885	Assert(pVCpu->cpum.s.fRemEntered);
2886
2887	RT_NOREF_PV(fNoOutOfSyncSels);
2888
2889	pVCpu->cpum.s.fRemEntered = false;
2890	}
2891
2892
2893	/**
2894	* Called when the ring-3 init phase completes.
2895	*
2896	* @returns VBox status code.
2897	* @param pVM The cross context VM structure.
2898	* @param enmWhat Which init phase.
2899	*/
2900	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2901	{
2902	switch (enmWhat)
2903	{
2904	case VMINITCOMPLETED_RING3:
2905	{
2906	/*
2907	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2908	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2909	*/
2910	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2911	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2912	{
2913	PVMCPU pVCpu = &pVM->aCpus[i];
2914	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2915	if (fSupportsLongMode)
2916	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2917	}
2918
2919	cpumR3MsrRegStats(pVM);
2920	break;
2921	}
2922
2923	default:
2924	break;
2925	}
2926	return VINF_SUCCESS;
2927	}
2928
2929
2930	/**
2931	* Called when the ring-0 init phases completed.
2932	*
2933	* @param pVM The cross context VM structure.
2934	*/
2935	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
2936	{
2937	/*
2938	* Log the cpuid.
2939	*/
2940	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
2941	RTCPUSET OnlineSet;
2942	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
2943	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
2944	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
2945	RTCPUID cCores = RTMpGetCoreCount();
2946	if (cCores)
2947	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
2948	LogRel(("*********************** CPUID dump **********************\n"));
2949	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
2950	LogRel(("\n"));
2951	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
2952	RTLogRelSetBuffering(fOldBuffered);
2953	LogRel(("****************** End of CPUID dump ********************\n"));
2954	}
2955

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 71833

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