CPUM.cpp@ 72208

Last change on this file since 72208 was 72178, checked in by vboxsync, 7 years ago
VMM: Nested hw.virt: Implemented saved-states for nested SVM. Bumps the CPUM and HM SSM versions.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 143.1 KB

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1	/* $Id: CPUM.cpp 72178 2018-05-09 16:18:56Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for CPUMCTX. */
329	static const SSMFIELD g_aCpumX87Fields[] =
330	{
331	SSMFIELD_ENTRY( X86FXSTATE, FCW),
332	SSMFIELD_ENTRY( X86FXSTATE, FSW),
333	SSMFIELD_ENTRY( X86FXSTATE, FTW),
334	SSMFIELD_ENTRY( X86FXSTATE, FOP),
335	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
336	SSMFIELD_ENTRY( X86FXSTATE, CS),
337	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
338	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
339	SSMFIELD_ENTRY( X86FXSTATE, DS),
340	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
341	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
342	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
343	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
344	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
345	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
346	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
347	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
348	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
349	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
350	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
351	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
352	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
353	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
354	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
355	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
356	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
357	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
358	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
359	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
360	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
361	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
362	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
363	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
364	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
365	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
366	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
367	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
368	SSMFIELD_ENTRY_TERM()
369	};
370
371	/** Saved state field descriptors for X86XSAVEHDR. */
372	static const SSMFIELD g_aCpumXSaveHdrFields[] =
373	{
374	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/** Saved state field descriptors for X86XSAVEYMMHI. */
379	static const SSMFIELD g_aCpumYmmHiFields[] =
380	{
381	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
382	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
383	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
384	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
385	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
386	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
387	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
388	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
389	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
390	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
391	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
392	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
393	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
394	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
395	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
396	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
397	SSMFIELD_ENTRY_TERM()
398	};
399
400	/** Saved state field descriptors for X86XSAVEBNDREGS. */
401	static const SSMFIELD g_aCpumBndRegsFields[] =
402	{
403	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
404	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
405	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
406	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
407	SSMFIELD_ENTRY_TERM()
408	};
409
410	/** Saved state field descriptors for X86XSAVEBNDCFG. */
411	static const SSMFIELD g_aCpumBndCfgFields[] =
412	{
413	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
414	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	#if 0 /** @todo */
419	/** Saved state field descriptors for X86XSAVEOPMASK. */
420	static const SSMFIELD g_aCpumOpmaskFields[] =
421	{
422	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
423	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
424	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
425	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
426	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
427	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
428	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
429	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
430	SSMFIELD_ENTRY_TERM()
431	};
432	#endif
433
434	/** Saved state field descriptors for X86XSAVEZMMHI256. */
435	static const SSMFIELD g_aCpumZmmHi256Fields[] =
436	{
437	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
438	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
439	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
440	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
441	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
442	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
443	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
444	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
445	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
446	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
447	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
448	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
449	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
450	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
451	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
452	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
453	SSMFIELD_ENTRY_TERM()
454	};
455
456	/** Saved state field descriptors for X86XSAVEZMM16HI. */
457	static const SSMFIELD g_aCpumZmm16HiFields[] =
458	{
459	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
460	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
461	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
462	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
463	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
464	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
465	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
466	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
467	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
468	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
469	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
470	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
471	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
472	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
473	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
474	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
475	SSMFIELD_ENTRY_TERM()
476	};
477
478
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumX87FieldsMem[] =
483	{
484	SSMFIELD_ENTRY( X86FXSTATE, FCW),
485	SSMFIELD_ENTRY( X86FXSTATE, FSW),
486	SSMFIELD_ENTRY( X86FXSTATE, FTW),
487	SSMFIELD_ENTRY( X86FXSTATE, FOP),
488	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
489	SSMFIELD_ENTRY( X86FXSTATE, CS),
490	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
491	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
492	SSMFIELD_ENTRY( X86FXSTATE, DS),
493	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
494	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
495	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
496	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
497	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
498	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
499	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
500	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
501	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
502	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
503	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
504	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
505	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
506	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
507	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
508	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
509	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
510	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
511	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
512	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
513	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
514	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
515	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
516	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
517	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
518	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
519	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
520	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
521	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
522	};
523
524	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
525	* registeres changed. */
526	static const SSMFIELD g_aCpumCtxFieldsMem[] =
527	{
528	SSMFIELD_ENTRY( CPUMCTX, rdi),
529	SSMFIELD_ENTRY( CPUMCTX, rsi),
530	SSMFIELD_ENTRY( CPUMCTX, rbp),
531	SSMFIELD_ENTRY( CPUMCTX, rax),
532	SSMFIELD_ENTRY( CPUMCTX, rbx),
533	SSMFIELD_ENTRY( CPUMCTX, rdx),
534	SSMFIELD_ENTRY( CPUMCTX, rcx),
535	SSMFIELD_ENTRY( CPUMCTX, rsp),
536	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
537	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
538	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
539	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
540	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
541	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
542	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
543	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
544	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
545	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
546	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
547	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
548	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
549	SSMFIELD_ENTRY( CPUMCTX, rflags),
550	SSMFIELD_ENTRY( CPUMCTX, rip),
551	SSMFIELD_ENTRY( CPUMCTX, r8),
552	SSMFIELD_ENTRY( CPUMCTX, r9),
553	SSMFIELD_ENTRY( CPUMCTX, r10),
554	SSMFIELD_ENTRY( CPUMCTX, r11),
555	SSMFIELD_ENTRY( CPUMCTX, r12),
556	SSMFIELD_ENTRY( CPUMCTX, r13),
557	SSMFIELD_ENTRY( CPUMCTX, r14),
558	SSMFIELD_ENTRY( CPUMCTX, r15),
559	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
560	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
561	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
562	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
563	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
564	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
565	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
571	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
572	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
573	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
574	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
575	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
576	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
577	SSMFIELD_ENTRY( CPUMCTX, cr0),
578	SSMFIELD_ENTRY( CPUMCTX, cr2),
579	SSMFIELD_ENTRY( CPUMCTX, cr3),
580	SSMFIELD_ENTRY( CPUMCTX, cr4),
581	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
582	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
583	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
584	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
585	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
586	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
587	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
588	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
589	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
590	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
591	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
592	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
593	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
594	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
595	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
596	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
597	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
598	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
599	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
600	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
601	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
602	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
603	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
604	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
605	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
606	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
607	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
608	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
609	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
610	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
611	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
612	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
613	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
614	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumX87FieldsV16[] =
620	{
621	SSMFIELD_ENTRY( X86FXSTATE, FCW),
622	SSMFIELD_ENTRY( X86FXSTATE, FSW),
623	SSMFIELD_ENTRY( X86FXSTATE, FTW),
624	SSMFIELD_ENTRY( X86FXSTATE, FOP),
625	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
626	SSMFIELD_ENTRY( X86FXSTATE, CS),
627	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
628	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
629	SSMFIELD_ENTRY( X86FXSTATE, DS),
630	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
631	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
632	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
633	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
634	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
635	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
636	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
637	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
638	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
639	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
640	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
641	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
642	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
643	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
644	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
645	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
646	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
647	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
648	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
649	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
650	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
651	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
652	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
653	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
654	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
655	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
656	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
657	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
658	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
659	SSMFIELD_ENTRY_TERM()
660	};
661
662	/** Saved state field descriptors for CPUMCTX_VER1_6. */
663	static const SSMFIELD g_aCpumCtxFieldsV16[] =
664	{
665	SSMFIELD_ENTRY( CPUMCTX, rdi),
666	SSMFIELD_ENTRY( CPUMCTX, rsi),
667	SSMFIELD_ENTRY( CPUMCTX, rbp),
668	SSMFIELD_ENTRY( CPUMCTX, rax),
669	SSMFIELD_ENTRY( CPUMCTX, rbx),
670	SSMFIELD_ENTRY( CPUMCTX, rdx),
671	SSMFIELD_ENTRY( CPUMCTX, rcx),
672	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
673	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
674	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
675	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
676	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
677	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
678	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
679	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
680	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
681	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
682	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
683	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
684	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
685	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
686	SSMFIELD_ENTRY( CPUMCTX, rflags),
687	SSMFIELD_ENTRY( CPUMCTX, rip),
688	SSMFIELD_ENTRY( CPUMCTX, r8),
689	SSMFIELD_ENTRY( CPUMCTX, r9),
690	SSMFIELD_ENTRY( CPUMCTX, r10),
691	SSMFIELD_ENTRY( CPUMCTX, r11),
692	SSMFIELD_ENTRY( CPUMCTX, r12),
693	SSMFIELD_ENTRY( CPUMCTX, r13),
694	SSMFIELD_ENTRY( CPUMCTX, r14),
695	SSMFIELD_ENTRY( CPUMCTX, r15),
696	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
697	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
698	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
699	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
700	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
701	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
702	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
703	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
704	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
705	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
706	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
707	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
708	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
709	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
710	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
711	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
712	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
713	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
714	SSMFIELD_ENTRY( CPUMCTX, cr0),
715	SSMFIELD_ENTRY( CPUMCTX, cr2),
716	SSMFIELD_ENTRY( CPUMCTX, cr3),
717	SSMFIELD_ENTRY( CPUMCTX, cr4),
718	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
719	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
720	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
721	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
722	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
723	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
724	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
725	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
726	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
727	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
728	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
729	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
730	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
731	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
732	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
733	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
734	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
735	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
736	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
737	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
738	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
739	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
740	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
741	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
742	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
743	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
744	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
745	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
746	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
747	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
748	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
749	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
750	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
751	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
752	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
753	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
754	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
755	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
756	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
757	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
758	SSMFIELD_ENTRY_TERM()
759	};
760
761
762	/**
763	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
764	*
765	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
766	* (last instruction pointer, last data pointer, last opcode) except when the ES
767	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
768	* clear these registers there is potential, local FPU leakage from a process
769	* using the FPU to another.
770	*
771	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
772	*
773	* @param pVM The cross context VM structure.
774	*/
775	static void cpumR3CheckLeakyFpu(PVM pVM)
776	{
777	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
778	uint32_t const u32Family = u32CpuVersion >> 8;
779	if ( u32Family >= 6 /* K7 and higher */
780	&& ASMIsAmdCpu())
781	{
782	uint32_t cExt = ASMCpuId_EAX(0x80000000);
783	if (ASMIsValidExtRange(cExt))
784	{
785	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
786	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
787	{
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
790	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
791	}
792	}
793	}
794	}
795
796
797	/**
798	* Frees memory allocated for the SVM hardware virtualization state.
799	*
800	* @param pVM The cross context VM structure.
801	*/
802	static void cpumR3FreeSvmHwVirtState(PVM pVM)
803	{
804	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
805	for (VMCPUID i = 0; i < pVM->cCpus; i++)
806	{
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
809	{
810	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
811	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
812	}
813	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
814
815	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
816	{
817	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
818	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
819	}
820
821	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
822	{
823	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
824	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
825	}
826	}
827	}
828
829
830	/**
831	* Allocates memory for the SVM hardware virtualization state.
832	*
833	* @returns VBox status code.
834	* @param pVM The cross context VM structure.
835	*/
836	static int cpumR3AllocSvmHwVirtState(PVM pVM)
837	{
838	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
839
840	int rc = VINF_SUCCESS;
841	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
842	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846
847	/*
848	* Allocate the nested-guest VMCB.
849	*/
850	SUPPAGE SupNstGstVmcbPage;
851	RT_ZERO(SupNstGstVmcbPage);
852	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
853	Assert(SVM_VMCB_PAGES == 1);
854	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
855	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
856	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
857	if (RT_FAILURE(rc))
858	{
859	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
860	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
861	break;
862	}
863	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
864
865	/*
866	* Allocate the MSRPM (MSR Permission bitmap).
867	*/
868	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
869	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
870	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
871	if (RT_FAILURE(rc))
872	{
873	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
874	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
875	SVM_MSRPM_PAGES));
876	break;
877	}
878
879	/*
880	* Allocate the IOPM (IO Permission bitmap).
881	*/
882	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
883	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
884	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
885	if (RT_FAILURE(rc))
886	{
887	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
888	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
889	SVM_IOPM_PAGES));
890	break;
891	}
892	}
893
894	/* On any failure, cleanup. */
895	if (RT_FAILURE(rc))
896	cpumR3FreeSvmHwVirtState(pVM);
897
898	return rc;
899	}
900
901
902	/**
903	* Initializes the CPUM.
904	*
905	* @returns VBox status code.
906	* @param pVM The cross context VM structure.
907	*/
908	VMMR3DECL(int) CPUMR3Init(PVM pVM)
909	{
910	LogFlow(("CPUMR3Init\n"));
911
912	/*
913	* Assert alignment, sizes and tables.
914	*/
915	AssertCompileMemberAlignment(VM, cpum.s, 32);
916	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
917	AssertCompileSizeAlignment(CPUMCTX, 64);
918	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
919	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
920	AssertCompileMemberAlignment(VM, cpum, 64);
921	AssertCompileMemberAlignment(VM, aCpus, 64);
922	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
923	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
924	#ifdef VBOX_STRICT
925	int rc2 = cpumR3MsrStrictInitChecks();
926	AssertRCReturn(rc2, rc2);
927	#endif
928
929	/*
930	* Initialize offsets.
931	*/
932
933	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
934	pVM->cpum.s.offCPUMCPU0 = RT_OFFSETOF(VM, aCpus[0].cpum) - RT_OFFSETOF(VM, cpum);
935	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
936
937
938	/* Calculate the offset from CPUMCPU to CPUM. */
939	for (VMCPUID i = 0; i < pVM->cCpus; i++)
940	{
941	PVMCPU pVCpu = &pVM->aCpus[i];
942
943	pVCpu->cpum.s.offCPUM = RT_OFFSETOF(VM, aCpus[i].cpum) - RT_OFFSETOF(VM, cpum);
944	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
945	}
946
947	/*
948	* Gather info about the host CPU.
949	*/
950	if (!ASMHasCpuId())
951	{
952	Log(("The CPU doesn't support CPUID!\n"));
953	return VERR_UNSUPPORTED_CPU;
954	}
955
956	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
957
958	PCPUMCPUIDLEAF paLeaves;
959	uint32_t cLeaves;
960	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
961	AssertLogRelRCReturn(rc, rc);
962
963	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
964	RTMemFree(paLeaves);
965	AssertLogRelRCReturn(rc, rc);
966	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
967
968	/*
969	* Check that the CPU supports the minimum features we require.
970	*/
971	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
972	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
973	if (!pVM->cpum.s.HostFeatures.fMmx)
974	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
975	if (!pVM->cpum.s.HostFeatures.fTsc)
976	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
977
978	/*
979	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
980	*/
981	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
982	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
983
984	/*
985	* Figure out which XSAVE/XRSTOR features are available on the host.
986	*/
987	uint64_t fXcr0Host = 0;
988	uint64_t fXStateHostMask = 0;
989	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
990	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
991	{
992	fXStateHostMask = fXcr0Host = ASMGetXcr0();
993	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
994	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
995	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
996	}
997	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
998	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
999	fXStateHostMask = 0;
1000	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1001	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1002
1003	/*
1004	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
1005	*/
1006	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1007	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1008	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
1009
1010	uint8_t *pbXStates;
1011	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
1012	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
1013	AssertLogRelRCReturn(rc, rc);
1014
1015	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1016	{
1017	PVMCPU pVCpu = &pVM->aCpus[i];
1018
1019	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1020	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1021	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1022	pbXStates += cbMaxXState;
1023
1024	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1025	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1026	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1027	pbXStates += cbMaxXState;
1028
1029	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1030	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1031	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1032	pbXStates += cbMaxXState;
1033
1034	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
1035	}
1036
1037	/*
1038	* Register saved state data item.
1039	*/
1040	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
1041	NULL, cpumR3LiveExec, NULL,
1042	NULL, cpumR3SaveExec, NULL,
1043	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1044	if (RT_FAILURE(rc))
1045	return rc;
1046
1047	/*
1048	* Register info handlers and registers with the debugger facility.
1049	*/
1050	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1051	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1052	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1053	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1054	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1055	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1056	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1057	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1058	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1059	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1060	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1061	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1062	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1063
1064	rc = cpumR3DbgInit(pVM);
1065	if (RT_FAILURE(rc))
1066	return rc;
1067
1068	/*
1069	* Check if we need to workaround partial/leaky FPU handling.
1070	*/
1071	cpumR3CheckLeakyFpu(pVM);
1072
1073	/*
1074	* Initialize the Guest CPUID and MSR states.
1075	*/
1076	rc = cpumR3InitCpuIdAndMsrs(pVM);
1077	if (RT_FAILURE(rc))
1078	return rc;
1079
1080	/*
1081	* Allocate memory required by the guest hardware virtualization state.
1082	*/
1083	if (pVM->cpum.ro.GuestFeatures.fSvm)
1084	{
1085	rc = cpumR3AllocSvmHwVirtState(pVM);
1086	if (RT_FAILURE(rc))
1087	return rc;
1088	}
1089
1090	/*
1091	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1092	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1093	* of processors from (cpuid(4).eax >> 26) + 1.
1094	*
1095	* Note: this code is obsolete, but let's keep it here for reference.
1096	* Purpose is valid when we artificially cap the max std id to less than 4.
1097	*
1098	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
1099	* after VMINITCOMPLETED_HM.
1100	*/
1101	if (VM_IS_RAW_MODE_ENABLED(pVM))
1102	{
1103	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1104	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1105	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1106	}
1107
1108	CPUMR3Reset(pVM);
1109	return VINF_SUCCESS;
1110	}
1111
1112
1113	/**
1114	* Applies relocations to data and code managed by this
1115	* component. This function will be called at init and
1116	* whenever the VMM need to relocate it self inside the GC.
1117	*
1118	* The CPUM will update the addresses used by the switcher.
1119	*
1120	* @param pVM The cross context VM structure.
1121	*/
1122	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1123	{
1124	LogFlow(("CPUMR3Relocate\n"));
1125
1126	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1127	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1128
1129	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1130	{
1131	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1132	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1133	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1134	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1135
1136	/* Recheck the guest DRx values in raw-mode. */
1137	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1138	}
1139	}
1140
1141
1142	/**
1143	* Terminates the CPUM.
1144	*
1145	* Termination means cleaning up and freeing all resources,
1146	* the VM it self is at this point powered off or suspended.
1147	*
1148	* @returns VBox status code.
1149	* @param pVM The cross context VM structure.
1150	*/
1151	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1152	{
1153	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1154	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1155	{
1156	PVMCPU pVCpu = &pVM->aCpus[i];
1157	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1158
1159	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1160	pVCpu->cpum.s.uMagic = 0;
1161	pCtx->dr[5] = 0;
1162	}
1163	#endif
1164
1165	if (pVM->cpum.ro.GuestFeatures.fSvm)
1166	cpumR3FreeSvmHwVirtState(pVM);
1167	return VINF_SUCCESS;
1168	}
1169
1170
1171	/**
1172	* Resets a virtual CPU.
1173	*
1174	* Used by CPUMR3Reset and CPU hot plugging.
1175	*
1176	* @param pVM The cross context VM structure.
1177	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1178	* being reset. This may differ from the current EMT.
1179	*/
1180	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1181	{
1182	/** @todo anything different for VCPU > 0? */
1183	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1184
1185	/*
1186	* Initialize everything to ZERO first.
1187	*/
1188	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1189
1190	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1191	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1192	memset(pCtx, 0, RT_OFFSETOF(CPUMCTX, pXStateR0));
1193
1194	pVCpu->cpum.s.fUseFlags = fUseFlags;
1195
1196	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1197	pCtx->eip = 0x0000fff0;
1198	pCtx->edx = 0x00000600; /* P6 processor */
1199	pCtx->eflags.Bits.u1Reserved0 = 1;
1200
1201	pCtx->cs.Sel = 0xf000;
1202	pCtx->cs.ValidSel = 0xf000;
1203	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1204	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1205	pCtx->cs.u32Limit = 0x0000ffff;
1206	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1207	pCtx->cs.Attr.n.u1Present = 1;
1208	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1209
1210	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1211	pCtx->ds.u32Limit = 0x0000ffff;
1212	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1213	pCtx->ds.Attr.n.u1Present = 1;
1214	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1215
1216	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1217	pCtx->es.u32Limit = 0x0000ffff;
1218	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1219	pCtx->es.Attr.n.u1Present = 1;
1220	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1221
1222	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1223	pCtx->fs.u32Limit = 0x0000ffff;
1224	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1225	pCtx->fs.Attr.n.u1Present = 1;
1226	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1227
1228	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1229	pCtx->gs.u32Limit = 0x0000ffff;
1230	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1231	pCtx->gs.Attr.n.u1Present = 1;
1232	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1233
1234	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1235	pCtx->ss.u32Limit = 0x0000ffff;
1236	pCtx->ss.Attr.n.u1Present = 1;
1237	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1238	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1239
1240	pCtx->idtr.cbIdt = 0xffff;
1241	pCtx->gdtr.cbGdt = 0xffff;
1242
1243	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1244	pCtx->ldtr.u32Limit = 0xffff;
1245	pCtx->ldtr.Attr.n.u1Present = 1;
1246	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1247
1248	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1249	pCtx->tr.u32Limit = 0xffff;
1250	pCtx->tr.Attr.n.u1Present = 1;
1251	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1252
1253	pCtx->dr[6] = X86_DR6_INIT_VAL;
1254	pCtx->dr[7] = X86_DR7_INIT_VAL;
1255
1256	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1257	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1258	pFpuCtx->FCW = 0x37f;
1259
1260	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1261	IA-32 Processor States Following Power-up, Reset, or INIT */
1262	pFpuCtx->MXCSR = 0x1F80;
1263	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1264
1265	pCtx->aXcr[0] = XSAVE_C_X87;
1266	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_OFFSETOF(X86XSAVEAREA, Hdr))
1267	{
1268	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1269	as we don't know what happened before. (Bother optimize later?) */
1270	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1271	}
1272
1273	/*
1274	* MSRs.
1275	*/
1276	/* Init PAT MSR */
1277	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
1278
1279	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1280	* The Intel docs don't mention it. */
1281	Assert(!pCtx->msrEFER);
1282
1283	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1284	is supposed to be here, just trying provide useful/sensible values. */
1285	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1286	if (pRange)
1287	{
1288	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1289	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1290	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1291	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1292	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1293	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1294	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1295	}
1296
1297	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1298
1299	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1300	* called from each EMT while we're getting called by CPUMR3Reset()
1301	* iteratively on the same thread. Fix later. */
1302	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1303	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1304	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1305	#endif
1306
1307
1308	/* C-state control. Guesses. */
1309	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1310	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
1311	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
1312	* functionality. The default value must be different due to incompatible write mask.
1313	*/
1314	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
1315	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
1316	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
1317	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
1318
1319	/*
1320	* Hardware virtualization state.
1321	*/
1322	pCtx->hwvirt.fGif = true;
1323
1324	/* SVM. */
1325	if (pCtx->hwvirt.svm.CTX_SUFF(pVmcb))
1326	{
1327	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1328	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1329	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1330	}
1331	}
1332
1333
1334	/**
1335	* Resets the CPU.
1336	*
1337	* @returns VINF_SUCCESS.
1338	* @param pVM The cross context VM structure.
1339	*/
1340	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1341	{
1342	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1343	{
1344	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1345
1346	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1347	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1348
1349	/* Magic marker for searching in crash dumps. */
1350	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1351	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1352	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1353	#endif
1354	}
1355	}
1356
1357
1358
1359
1360	/**
1361	* Pass 0 live exec callback.
1362	*
1363	* @returns VINF_SSM_DONT_CALL_AGAIN.
1364	* @param pVM The cross context VM structure.
1365	* @param pSSM The saved state handle.
1366	* @param uPass The pass (0).
1367	*/
1368	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1369	{
1370	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1371	cpumR3SaveCpuId(pVM, pSSM);
1372	return VINF_SSM_DONT_CALL_AGAIN;
1373	}
1374
1375
1376	/**
1377	* Execute state save operation.
1378	*
1379	* @returns VBox status code.
1380	* @param pVM The cross context VM structure.
1381	* @param pSSM SSM operation handle.
1382	*/
1383	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1384	{
1385	/*
1386	* Save.
1387	*/
1388	SSMR3PutU32(pSSM, pVM->cCpus);
1389	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1390	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1391	{
1392	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1393
1394	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1395
1396	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1397	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1398	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1399	if (pGstCtx->fXStateMask != 0)
1400	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1401	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1402	{
1403	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1404	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1405	}
1406	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1407	{
1408	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1409	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1410	}
1411	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1412	{
1413	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1414	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1415	}
1416	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1417	{
1418	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1419	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1420	}
1421	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1422	{
1423	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1424	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1425	}
1426	if (pVM->cpum.ro.GuestFeatures.fSvm)
1427	{
1428	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1429	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
1430	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
1431	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
1432	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
1433	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
1434	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
1435	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fHMCachedVmcb);
1436	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
1437	g_aSvmHwvirtHostState, NULL /* pvUser */);
1438	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
1439	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1440	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
1441	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
1442	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
1443	}
1444	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1445	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1446	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1447	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1448	}
1449
1450	cpumR3SaveCpuId(pVM, pSSM);
1451	return VINF_SUCCESS;
1452	}
1453
1454
1455	/**
1456	* @callback_method_impl{FNSSMINTLOADPREP}
1457	*/
1458	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1459	{
1460	NOREF(pSSM);
1461	pVM->cpum.s.fPendingRestore = true;
1462	return VINF_SUCCESS;
1463	}
1464
1465
1466	/**
1467	* @callback_method_impl{FNSSMINTLOADEXEC}
1468	*/
1469	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1470	{
1471	int rc; /* Only for AssertRCReturn use. */
1472
1473	/*
1474	* Validate version.
1475	*/
1476	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
1477	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1478	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1479	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1480	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1481	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
1482	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1483	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1484	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1485	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1486	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1487	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1488	{
1489	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1490	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1491	}
1492
1493	if (uPass == SSM_PASS_FINAL)
1494	{
1495	/*
1496	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1497	* really old SSM file versions.)
1498	*/
1499	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1500	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1501	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1502	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1503
1504	/*
1505	* Figure x86 and ctx field definitions to use for older states.
1506	*/
1507	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1508	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1509	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1510	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1511	{
1512	paCpumCtx1Fields = g_aCpumX87FieldsV16;
1513	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1514	}
1515	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1516	{
1517	paCpumCtx1Fields = g_aCpumX87FieldsMem;
1518	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1519	}
1520
1521	/*
1522	* The hyper state used to preceed the CPU count. Starting with
1523	* XSAVE it was moved down till after we've got the count.
1524	*/
1525	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1526	{
1527	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1528	{
1529	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1530	X86FXSTATE Ign;
1531	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1532	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1533	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1534	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1535	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1536	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1537	pVCpu->cpum.s.Hyper.rsp = uRSP;
1538	}
1539	}
1540
1541	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1542	{
1543	uint32_t cCpus;
1544	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1545	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1546	VERR_SSM_UNEXPECTED_DATA);
1547	}
1548	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1549	\|\| pVM->cCpus == 1,
1550	("cCpus=%u\n", pVM->cCpus),
1551	VERR_SSM_UNEXPECTED_DATA);
1552
1553	uint32_t cbMsrs = 0;
1554	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1555	{
1556	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1557	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1558	VERR_SSM_UNEXPECTED_DATA);
1559	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1560	VERR_SSM_UNEXPECTED_DATA);
1561	}
1562
1563	/*
1564	* Do the per-CPU restoring.
1565	*/
1566	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1567	{
1568	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1569	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1570
1571	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1572	{
1573	/*
1574	* The XSAVE saved state layout moved the hyper state down here.
1575	*/
1576	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1577	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1578	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1579	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1580	pVCpu->cpum.s.Hyper.rsp = uRSP;
1581	AssertRCReturn(rc, rc);
1582
1583	/*
1584	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1585	*/
1586	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1587	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1588	AssertRCReturn(rc, rc);
1589
1590	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1591	if (pGstCtx->fXStateMask != 0)
1592	{
1593	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1594	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1595	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1596	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1597	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1598	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1599	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1600	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1601	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1602	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1603	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1604	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1605	}
1606
1607	/* Check that the XCR0 mask is valid (invalid results in #GP). */
1608	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1609	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1610	{
1611	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
1612	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1613	VERR_CPUM_INVALID_XCR0);
1614	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1615	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1616	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1617	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1618	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1619	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1620	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1621	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1622	}
1623
1624	/* Check that the XCR1 is zero, as we don't implement it yet. */
1625	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1626
1627	/*
1628	* Restore the individual extended state components we support.
1629	*/
1630	if (pGstCtx->fXStateMask != 0)
1631	{
1632	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1633	0, g_aCpumXSaveHdrFields, NULL);
1634	AssertRCReturn(rc, rc);
1635	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1636	("bmXState=%#RX64 fXStateMask=%#RX64\n",
1637	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1638	VERR_CPUM_INVALID_XSAVE_HDR);
1639	}
1640	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1641	{
1642	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
1643	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1644	}
1645	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1646	{
1647	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
1648	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1649	}
1650	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1651	{
1652	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
1653	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1654	}
1655	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1656	{
1657	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
1658	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1659	}
1660	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1661	{
1662	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
1663	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1664	}
1665	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
1666	{
1667	if (pVM->cpum.ro.GuestFeatures.fSvm)
1668	{
1669	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1670	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
1671	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
1672	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
1673	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
1674	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
1675	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
1676	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fHMCachedVmcb);
1677	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
1678	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
1679	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
1680	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1681	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
1682	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
1683	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
1684	}
1685	}
1686	}
1687	else
1688	{
1689	/*
1690	* Pre XSAVE saved state.
1691	*/
1692	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
1693	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1694	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1695	}
1696
1697	/*
1698	* Restore a couple of flags and the MSRs.
1699	*/
1700	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
1701	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
1702
1703	rc = VINF_SUCCESS;
1704	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1705	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
1706	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
1707	{
1708	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
1709	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
1710	}
1711	AssertRCReturn(rc, rc);
1712
1713	/* REM and other may have cleared must-be-one fields in DR6 and
1714	DR7, fix these. */
1715	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
1716	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
1717	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
1718	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
1719	}
1720
1721	/* Older states does not have the internal selector register flags
1722	and valid selector value. Supply those. */
1723	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1724	{
1725	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1726	{
1727	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1728	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
1729	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1730	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
1731	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
1732	if (fValid)
1733	{
1734	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1735	{
1736	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
1737	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
1738	}
1739
1740	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1741	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1742	}
1743	else
1744	{
1745	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
1746	{
1747	paSelReg[iSelReg].fFlags = 0;
1748	paSelReg[iSelReg].ValidSel = 0;
1749	}
1750
1751	/* This might not be 104% correct, but I think it's close
1752	enough for all practical purposes... (REM always loaded
1753	LDTR registers.) */
1754	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1755	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
1756	}
1757	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
1758	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
1759	}
1760	}
1761
1762	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
1763	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
1764	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1765	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1766	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
1767
1768	/*
1769	* A quick sanity check.
1770	*/
1771	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1772	{
1773	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1774	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1775	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1776	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1777	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1778	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1779	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
1780	}
1781	}
1782
1783	pVM->cpum.s.fPendingRestore = false;
1784
1785	/*
1786	* Guest CPUIDs.
1787	*/
1788	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
1789	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
1790	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
1791	}
1792
1793
1794	/**
1795	* @callback_method_impl{FNSSMINTLOADDONE}
1796	*/
1797	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
1798	{
1799	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
1800	return VINF_SUCCESS;
1801
1802	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
1803	if (pVM->cpum.s.fPendingRestore)
1804	{
1805	LogRel(("CPUM: Missing state!\n"));
1806	return VERR_INTERNAL_ERROR_2;
1807	}
1808
1809	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
1810	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1811	{
1812	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1813
1814	/* Notify PGM of the NXE states in case they've changed. */
1815	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
1816
1817	/* During init. this is done in CPUMR3InitCompleted(). */
1818	if (fSupportsLongMode)
1819	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
1820	}
1821	return VINF_SUCCESS;
1822	}
1823
1824
1825	/**
1826	* Checks if the CPUM state restore is still pending.
1827	*
1828	* @returns true / false.
1829	* @param pVM The cross context VM structure.
1830	*/
1831	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
1832	{
1833	return pVM->cpum.s.fPendingRestore;
1834	}
1835
1836
1837	/**
1838	* Formats the EFLAGS value into mnemonics.
1839	*
1840	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
1841	* @param efl The EFLAGS value.
1842	*/
1843	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
1844	{
1845	/*
1846	* Format the flags.
1847	*/
1848	static const struct
1849	{
1850	const char pszSet; const char pszClear; uint32_t fFlag;
1851	} s_aFlags[] =
1852	{
1853	{ "vip",NULL, X86_EFL_VIP },
1854	{ "vif",NULL, X86_EFL_VIF },
1855	{ "ac", NULL, X86_EFL_AC },
1856	{ "vm", NULL, X86_EFL_VM },
1857	{ "rf", NULL, X86_EFL_RF },
1858	{ "nt", NULL, X86_EFL_NT },
1859	{ "ov", "nv", X86_EFL_OF },
1860	{ "dn", "up", X86_EFL_DF },
1861	{ "ei", "di", X86_EFL_IF },
1862	{ "tf", NULL, X86_EFL_TF },
1863	{ "nt", "pl", X86_EFL_SF },
1864	{ "nz", "zr", X86_EFL_ZF },
1865	{ "ac", "na", X86_EFL_AF },
1866	{ "po", "pe", X86_EFL_PF },
1867	{ "cy", "nc", X86_EFL_CF },
1868	};
1869	char *psz = pszEFlags;
1870	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
1871	{
1872	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
1873	if (pszAdd)
1874	{
1875	strcpy(psz, pszAdd);
1876	psz += strlen(pszAdd);
1877	*psz++ = ' ';
1878	}
1879	}
1880	psz[-1] = '\0';
1881	}
1882
1883
1884	/**
1885	* Formats a full register dump.
1886	*
1887	* @param pVM The cross context VM structure.
1888	* @param pCtx The context to format.
1889	* @param pCtxCore The context core to format.
1890	* @param pHlp Output functions.
1891	* @param enmType The dump type.
1892	* @param pszPrefix Register name prefix.
1893	*/
1894	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
1895	const char *pszPrefix)
1896	{
1897	NOREF(pVM);
1898
1899	/*
1900	* Format the EFLAGS.
1901	*/
1902	uint32_t efl = pCtxCore->eflags.u32;
1903	char szEFlags[80];
1904	cpumR3InfoFormatFlags(&szEFlags[0], efl);
1905
1906	/*
1907	* Format the registers.
1908	*/
1909	switch (enmType)
1910	{
1911	case CPUMDUMPTYPE_TERSE:
1912	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1913	pHlp->pfnPrintf(pHlp,
1914	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1915	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1916	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1917	"%sr14=%016RX64 %sr15=%016RX64\n"
1918	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1919	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1920	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1921	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1922	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1923	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1924	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1925	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1926	else
1927	pHlp->pfnPrintf(pHlp,
1928	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1929	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1930	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
1931	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1932	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1933	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1934	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
1935	break;
1936
1937	case CPUMDUMPTYPE_DEFAULT:
1938	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1939	pHlp->pfnPrintf(pHlp,
1940	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1941	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1942	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1943	"%sr14=%016RX64 %sr15=%016RX64\n"
1944	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1945	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1946	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
1947	,
1948	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1949	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1950	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1951	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1952	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1953	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1954	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1955	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1956	else
1957	pHlp->pfnPrintf(pHlp,
1958	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
1959	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
1960	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
1961	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
1962	,
1963	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
1964	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1965	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
1966	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
1967	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
1968	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
1969	break;
1970
1971	case CPUMDUMPTYPE_VERBOSE:
1972	if (CPUMIsGuestIn64BitCodeEx(pCtx))
1973	pHlp->pfnPrintf(pHlp,
1974	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
1975	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
1976	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
1977	"%sr14=%016RX64 %sr15=%016RX64\n"
1978	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
1979	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1980	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1981	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1982	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1983	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1984	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
1985	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
1986	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
1987	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
1988	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
1989	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1990	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
1991	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
1992	,
1993	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
1994	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
1995	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
1996	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
1997	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
1998	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
1999	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2000	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2001	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2002	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2003	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2004	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2005	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2006	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2007	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2008	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2009	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2010	else
2011	pHlp->pfnPrintf(pHlp,
2012	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2013	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2014	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2015	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2016	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2017	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2018	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2019	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2020	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2021	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2022	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2023	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2024	,
2025	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2026	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2027	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2028	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2029	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2030	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2031	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2032	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2033	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2034	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2035	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2036	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2037
2038	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
2039	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
2040	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
2041	if (pCtx->CTX_SUFF(pXState))
2042	{
2043	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2044	pHlp->pfnPrintf(pHlp,
2045	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2046	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2047	,
2048	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
2049	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
2050	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
2051	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
2052	);
2053	/*
2054	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
2055	* not (FP)R0-7 as Intel SDM suggests.
2056	*/
2057	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
2058	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
2059	{
2060	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
2061	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
2062	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
2063	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
2064	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
2065	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
2066	iExponent -= 16383; /* subtract bias */
2067	/** @todo This isn't entirenly correct and needs more work! */
2068	pHlp->pfnPrintf(pHlp,
2069	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
2070	pszPrefix, iST, pszPrefix, iFPR,
2071	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
2072	uTag, chSign, iInteger, u64Fraction, iExponent);
2073	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
2074	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2075	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
2076	else
2077	pHlp->pfnPrintf(pHlp, "\n");
2078	}
2079
2080	/* XMM/YMM/ZMM registers. */
2081	if (pCtx->fXStateMask & XSAVE_C_YMM)
2082	{
2083	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2084	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2085	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2086	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2087	pszPrefix, i, i < 10 ? " " : "",
2088	pYmmHiCtx->aYmmHi[i].au32[3],
2089	pYmmHiCtx->aYmmHi[i].au32[2],
2090	pYmmHiCtx->aYmmHi[i].au32[1],
2091	pYmmHiCtx->aYmmHi[i].au32[0],
2092	pFpuCtx->aXMM[i].au32[3],
2093	pFpuCtx->aXMM[i].au32[2],
2094	pFpuCtx->aXMM[i].au32[1],
2095	pFpuCtx->aXMM[i].au32[0]);
2096	else
2097	{
2098	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2099	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2100	pHlp->pfnPrintf(pHlp,
2101	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2102	pszPrefix, i, i < 10 ? " " : "",
2103	pZmmHi256->aHi256Regs[i].au32[7],
2104	pZmmHi256->aHi256Regs[i].au32[6],
2105	pZmmHi256->aHi256Regs[i].au32[5],
2106	pZmmHi256->aHi256Regs[i].au32[4],
2107	pZmmHi256->aHi256Regs[i].au32[3],
2108	pZmmHi256->aHi256Regs[i].au32[2],
2109	pZmmHi256->aHi256Regs[i].au32[1],
2110	pZmmHi256->aHi256Regs[i].au32[0],
2111	pYmmHiCtx->aYmmHi[i].au32[3],
2112	pYmmHiCtx->aYmmHi[i].au32[2],
2113	pYmmHiCtx->aYmmHi[i].au32[1],
2114	pYmmHiCtx->aYmmHi[i].au32[0],
2115	pFpuCtx->aXMM[i].au32[3],
2116	pFpuCtx->aXMM[i].au32[2],
2117	pFpuCtx->aXMM[i].au32[1],
2118	pFpuCtx->aXMM[i].au32[0]);
2119
2120	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2121	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2122	pHlp->pfnPrintf(pHlp,
2123	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2124	pszPrefix, i + 16,
2125	pZmm16Hi->aRegs[i].au32[15],
2126	pZmm16Hi->aRegs[i].au32[14],
2127	pZmm16Hi->aRegs[i].au32[13],
2128	pZmm16Hi->aRegs[i].au32[12],
2129	pZmm16Hi->aRegs[i].au32[11],
2130	pZmm16Hi->aRegs[i].au32[10],
2131	pZmm16Hi->aRegs[i].au32[9],
2132	pZmm16Hi->aRegs[i].au32[8],
2133	pZmm16Hi->aRegs[i].au32[7],
2134	pZmm16Hi->aRegs[i].au32[6],
2135	pZmm16Hi->aRegs[i].au32[5],
2136	pZmm16Hi->aRegs[i].au32[4],
2137	pZmm16Hi->aRegs[i].au32[3],
2138	pZmm16Hi->aRegs[i].au32[2],
2139	pZmm16Hi->aRegs[i].au32[1],
2140	pZmm16Hi->aRegs[i].au32[0]);
2141	}
2142	}
2143	else
2144	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2145	pHlp->pfnPrintf(pHlp,
2146	i & 1
2147	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2148	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2149	pszPrefix, i, i < 10 ? " " : "",
2150	pFpuCtx->aXMM[i].au32[3],
2151	pFpuCtx->aXMM[i].au32[2],
2152	pFpuCtx->aXMM[i].au32[1],
2153	pFpuCtx->aXMM[i].au32[0]);
2154
2155	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2156	{
2157	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2158	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2159	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2160	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2161	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2162	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2163	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2164	}
2165
2166	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2167	{
2168	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2169	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2170	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2171	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2172	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2173	}
2174
2175	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2176	{
2177	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2178	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2179	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2180	}
2181
2182	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2183	if (pFpuCtx->au32RsrvdRest[i])
2184	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2185	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_OFFSETOF(X86FXSTATE, au32RsrvdRest[i]) );
2186	}
2187
2188	pHlp->pfnPrintf(pHlp,
2189	"%sEFER =%016RX64\n"
2190	"%sPAT =%016RX64\n"
2191	"%sSTAR =%016RX64\n"
2192	"%sCSTAR =%016RX64\n"
2193	"%sLSTAR =%016RX64\n"
2194	"%sSFMASK =%016RX64\n"
2195	"%sKERNELGSBASE =%016RX64\n",
2196	pszPrefix, pCtx->msrEFER,
2197	pszPrefix, pCtx->msrPAT,
2198	pszPrefix, pCtx->msrSTAR,
2199	pszPrefix, pCtx->msrCSTAR,
2200	pszPrefix, pCtx->msrLSTAR,
2201	pszPrefix, pCtx->msrSFMASK,
2202	pszPrefix, pCtx->msrKERNELGSBASE);
2203	break;
2204	}
2205	}
2206
2207
2208	/**
2209	* Display all cpu states and any other cpum info.
2210	*
2211	* @param pVM The cross context VM structure.
2212	* @param pHlp The info helper functions.
2213	* @param pszArgs Arguments, ignored.
2214	*/
2215	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2216	{
2217	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2218	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2219	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2220	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2221	cpumR3InfoHost(pVM, pHlp, pszArgs);
2222	}
2223
2224
2225	/**
2226	* Parses the info argument.
2227	*
2228	* The argument starts with 'verbose', 'terse' or 'default' and then
2229	* continues with the comment string.
2230	*
2231	* @param pszArgs The pointer to the argument string.
2232	* @param penmType Where to store the dump type request.
2233	* @param ppszComment Where to store the pointer to the comment string.
2234	*/
2235	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2236	{
2237	if (!pszArgs)
2238	{
2239	*penmType = CPUMDUMPTYPE_DEFAULT;
2240	*ppszComment = "";
2241	}
2242	else
2243	{
2244	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2245	{
2246	pszArgs += 7;
2247	*penmType = CPUMDUMPTYPE_VERBOSE;
2248	}
2249	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2250	{
2251	pszArgs += 5;
2252	*penmType = CPUMDUMPTYPE_TERSE;
2253	}
2254	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2255	{
2256	pszArgs += 7;
2257	*penmType = CPUMDUMPTYPE_DEFAULT;
2258	}
2259	else
2260	*penmType = CPUMDUMPTYPE_DEFAULT;
2261	*ppszComment = RTStrStripL(pszArgs);
2262	}
2263	}
2264
2265
2266	/**
2267	* Display the guest cpu state.
2268	*
2269	* @param pVM The cross context VM structure.
2270	* @param pHlp The info helper functions.
2271	* @param pszArgs Arguments.
2272	*/
2273	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2274	{
2275	CPUMDUMPTYPE enmType;
2276	const char *pszComment;
2277	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2278
2279	PVMCPU pVCpu = VMMGetCpu(pVM);
2280	if (!pVCpu)
2281	pVCpu = &pVM->aCpus[0];
2282
2283	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2284
2285	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2286	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2287	}
2288
2289
2290	/**
2291	* Displays an SVM VMCB control area.
2292	*
2293	* @param pHlp The info helper functions.
2294	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
2295	* @param pszPrefix Caller specified string prefix.
2296	*/
2297	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
2298	{
2299	AssertReturnVoid(pHlp);
2300	AssertReturnVoid(pVmcbCtrl);
2301
2302	pHlp->pfnPrintf(pHlp, "%su16InterceptRdCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
2303	pHlp->pfnPrintf(pHlp, "%su16InterceptWrCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
2304	pHlp->pfnPrintf(pHlp, "%su16InterceptRdDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
2305	pHlp->pfnPrintf(pHlp, "%su16InterceptWrDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
2306	pHlp->pfnPrintf(pHlp, "%su32InterceptXcpt = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
2307	pHlp->pfnPrintf(pHlp, "%su64InterceptCtrl = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
2308	pHlp->pfnPrintf(pHlp, "%su16PauseFilterThreshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
2309	pHlp->pfnPrintf(pHlp, "%su16PauseFilterCount = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
2310	pHlp->pfnPrintf(pHlp, "%su64IOPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
2311	pHlp->pfnPrintf(pHlp, "%su64MSRPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
2312	pHlp->pfnPrintf(pHlp, "%su64TSCOffset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
2313	pHlp->pfnPrintf(pHlp, "%sTLBCtrl\n", pszPrefix);
2314	pHlp->pfnPrintf(pHlp, "%s u32ASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
2315	pHlp->pfnPrintf(pHlp, "%s u8TLBFlush = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
2316	pHlp->pfnPrintf(pHlp, "%sIntCtrl\n", pszPrefix);
2317	pHlp->pfnPrintf(pHlp, "%s u8VTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
2318	pHlp->pfnPrintf(pHlp, "%s u1VIrqPending = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
2319	pHlp->pfnPrintf(pHlp, "%s u1VGif = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
2320	pHlp->pfnPrintf(pHlp, "%s u4VIntrPrio = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
2321	pHlp->pfnPrintf(pHlp, "%s u1IgnoreTPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
2322	pHlp->pfnPrintf(pHlp, "%s u1VIntrMasking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
2323	pHlp->pfnPrintf(pHlp, "%s u1VGifEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
2324	pHlp->pfnPrintf(pHlp, "%s u1AvicEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
2325	pHlp->pfnPrintf(pHlp, "%s u8VIntrVector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
2326	pHlp->pfnPrintf(pHlp, "%sIntShadow\n", pszPrefix);
2327	pHlp->pfnPrintf(pHlp, "%s u1IntShadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
2328	pHlp->pfnPrintf(pHlp, "%s u1GuestIntMask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
2329	pHlp->pfnPrintf(pHlp, "%su64ExitCode = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
2330	pHlp->pfnPrintf(pHlp, "%su64ExitInfo1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
2331	pHlp->pfnPrintf(pHlp, "%su64ExitInfo2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
2332	pHlp->pfnPrintf(pHlp, "%sExitIntInfo\n", pszPrefix);
2333	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
2334	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
2335	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
2336	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
2337	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
2338	pHlp->pfnPrintf(pHlp, "%sNestedPaging and SEV\n", pszPrefix);
2339	pHlp->pfnPrintf(pHlp, "%s u1NestedPaging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
2340	pHlp->pfnPrintf(pHlp, "%s u1Sev = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
2341	pHlp->pfnPrintf(pHlp, "%s u1SevEs = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
2342	pHlp->pfnPrintf(pHlp, "%sAvicBar\n", pszPrefix);
2343	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
2344	pHlp->pfnPrintf(pHlp, "%sEventInject\n", pszPrefix);
2345	pHlp->pfnPrintf(pHlp, "%s EventInject\n", pszPrefix);
2346	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
2347	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
2348	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
2349	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
2350	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
2351	pHlp->pfnPrintf(pHlp, "%su64NestedPagingCR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
2352	pHlp->pfnPrintf(pHlp, "%sLBR virtualization\n", pszPrefix);
2353	pHlp->pfnPrintf(pHlp, "%s u1LbrVirt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
2354	pHlp->pfnPrintf(pHlp, "%s u1VirtVmsaveVmload = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
2355	pHlp->pfnPrintf(pHlp, "%su32VmcbCleanBits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
2356	pHlp->pfnPrintf(pHlp, "%su64NextRIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
2357	pHlp->pfnPrintf(pHlp, "%scbInstrFetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
2358	pHlp->pfnPrintf(pHlp, "%sabInstr = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
2359	pHlp->pfnPrintf(pHlp, "%sAvicBackingPagePtr\n", pszPrefix);
2360	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
2361	pHlp->pfnPrintf(pHlp, "%sAvicLogicalTablePtr\n", pszPrefix);
2362	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
2363	pHlp->pfnPrintf(pHlp, "%sAvicPhysicalTablePtr\n", pszPrefix);
2364	pHlp->pfnPrintf(pHlp, "%s u8LastGuestCoreId = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
2365	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
2366	}
2367
2368
2369	/**
2370	* Helper for dumping the SVM VMCB selector registers.
2371	*
2372	* @param pHlp The info helper functions.
2373	* @param pSel Pointer to the SVM selector register.
2374	* @param pszName Name of the selector.
2375	* @param pszPrefix Caller specified string prefix.
2376	*/
2377	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
2378	{
2379	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
2380	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
2381	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
2382	}
2383
2384
2385	/**
2386	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
2387	*
2388	* @param pHlp The info helper functions.
2389	* @param pXdtr Pointer to the descriptor table register.
2390	* @param pszName Name of the descriptor table register.
2391	* @param pszPrefix Caller specified string prefix.
2392	*/
2393	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
2394	{
2395	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
2396	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
2397	}
2398
2399
2400	/**
2401	* Displays an SVM VMCB state-save area.
2402	*
2403	* @param pHlp The info helper functions.
2404	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
2405	* @param pszPrefix Caller specified string prefix.
2406	*/
2407	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
2408	{
2409	AssertReturnVoid(pHlp);
2410	AssertReturnVoid(pVmcbStateSave);
2411
2412	char szEFlags[80];
2413	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
2414
2415	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
2416	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
2417	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
2418	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
2419	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
2420	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
2421	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
2422	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
2423	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
2424	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
2425	pHlp->pfnPrintf(pHlp, "%su8CPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
2426	pHlp->pfnPrintf(pHlp, "%su64EFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
2427	pHlp->pfnPrintf(pHlp, "%su64CR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
2428	pHlp->pfnPrintf(pHlp, "%su64CR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
2429	pHlp->pfnPrintf(pHlp, "%su64CR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
2430	pHlp->pfnPrintf(pHlp, "%su64DR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
2431	pHlp->pfnPrintf(pHlp, "%su64DR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
2432	pHlp->pfnPrintf(pHlp, "%su64RFlags = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
2433	pHlp->pfnPrintf(pHlp, "%su64RIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
2434	pHlp->pfnPrintf(pHlp, "%su64RSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
2435	pHlp->pfnPrintf(pHlp, "%su64RAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
2436	pHlp->pfnPrintf(pHlp, "%su64STAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
2437	pHlp->pfnPrintf(pHlp, "%su64LSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
2438	pHlp->pfnPrintf(pHlp, "%su64CSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
2439	pHlp->pfnPrintf(pHlp, "%su64SFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
2440	pHlp->pfnPrintf(pHlp, "%su64KernelGSBase = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
2441	pHlp->pfnPrintf(pHlp, "%su64SysEnterCS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
2442	pHlp->pfnPrintf(pHlp, "%su64SysEnterEIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
2443	pHlp->pfnPrintf(pHlp, "%su64SysEnterESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
2444	pHlp->pfnPrintf(pHlp, "%su64CR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
2445	pHlp->pfnPrintf(pHlp, "%su64PAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
2446	pHlp->pfnPrintf(pHlp, "%su64DBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
2447	pHlp->pfnPrintf(pHlp, "%su64BR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
2448	pHlp->pfnPrintf(pHlp, "%su64BR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
2449	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPFROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
2450	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPTO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
2451	}
2452
2453
2454	/**
2455	* Display the guest's hardware-virtualization cpu state.
2456	*
2457	* @param pVM The cross context VM structure.
2458	* @param pHlp The info helper functions.
2459	* @param pszArgs Arguments, ignored.
2460	*/
2461	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2462	{
2463	RT_NOREF(pszArgs);
2464
2465	PVMCPU pVCpu = VMMGetCpu(pVM);
2466	if (!pVCpu)
2467	pVCpu = &pVM->aCpus[0];
2468
2469	/*
2470	* Figure out what to dump.
2471	*
2472	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
2473	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2474	* dump hwvirt. state when the guest CPU is executing a nested-guest.
2475	*/
2476	/** @todo perhaps make this configurable through pszArgs, depending on how much
2477	* noise we wish to accept when nested hwvirt. isn't used. */
2478	#define CPUMHWVIRTDUMP_NONE (0)
2479	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2480	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2481	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2482	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2483
2484	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2485	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2486	uint8_t const idxHwvirtState = CPUMIsGuestInSvmNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_SVM
2487	: CPUMIsGuestInVmxNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE;
2488	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2489	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2490	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2491	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
2492
2493	/*
2494	* Dump it.
2495	*/
2496	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2497
2498	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2499	{
2500	pHlp->pfnPrintf(pHlp, "fGif = %RTbool\n", pCtx->hwvirt.fGif);
2501	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2502	}
2503	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
2504	":" : "");
2505	if (fDumpState & CPUMHWVIRTDUMP_SVM)
2506	{
2507	char szEFlags[80];
2508	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
2509
2510	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2511	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2512	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2513	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2514	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
2515	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
2516	pHlp->pfnPrintf(pHlp, " HostState:\n");
2517	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2518	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2519	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2520	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2521	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2522	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2523	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2524	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
2525	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2526	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2527	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2528	pSel = &pCtx->hwvirt.svm.HostState.cs;
2529	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2530	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2531	pSel = &pCtx->hwvirt.svm.HostState.ss;
2532	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2533	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2534	pSel = &pCtx->hwvirt.svm.HostState.ds;
2535	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2536	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2537	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2538	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2539	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2540	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2541	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2542	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2543	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2544	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2545	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2546	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2547	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2548	}
2549
2550	/** @todo Intel. */
2551	#if 0
2552	if (fDumpState & CPUMHWVIRTDUMP_VMX)
2553	{
2554	}
2555	#endif
2556
2557	#undef CPUMHWVIRTDUMP_NONE
2558	#undef CPUMHWVIRTDUMP_COMMON
2559	#undef CPUMHWVIRTDUMP_SVM
2560	#undef CPUMHWVIRTDUMP_VMX
2561	#undef CPUMHWVIRTDUMP_LAST
2562	#undef CPUMHWVIRTDUMP_ALL
2563	}
2564
2565	/**
2566	* Display the current guest instruction
2567	*
2568	* @param pVM The cross context VM structure.
2569	* @param pHlp The info helper functions.
2570	* @param pszArgs Arguments, ignored.
2571	*/
2572	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2573	{
2574	NOREF(pszArgs);
2575
2576	PVMCPU pVCpu = VMMGetCpu(pVM);
2577	if (!pVCpu)
2578	pVCpu = &pVM->aCpus[0];
2579
2580	char szInstruction[256];
2581	szInstruction[0] = '\0';
2582	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2583	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2584	}
2585
2586
2587	/**
2588	* Display the hypervisor cpu state.
2589	*
2590	* @param pVM The cross context VM structure.
2591	* @param pHlp The info helper functions.
2592	* @param pszArgs Arguments, ignored.
2593	*/
2594	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2595	{
2596	PVMCPU pVCpu = VMMGetCpu(pVM);
2597	if (!pVCpu)
2598	pVCpu = &pVM->aCpus[0];
2599
2600	CPUMDUMPTYPE enmType;
2601	const char *pszComment;
2602	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2603	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2604	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2605	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2606	}
2607
2608
2609	/**
2610	* Display the host cpu state.
2611	*
2612	* @param pVM The cross context VM structure.
2613	* @param pHlp The info helper functions.
2614	* @param pszArgs Arguments, ignored.
2615	*/
2616	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2617	{
2618	CPUMDUMPTYPE enmType;
2619	const char *pszComment;
2620	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2621	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2622
2623	PVMCPU pVCpu = VMMGetCpu(pVM);
2624	if (!pVCpu)
2625	pVCpu = &pVM->aCpus[0];
2626	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2627
2628	/*
2629	* Format the EFLAGS.
2630	*/
2631	#if HC_ARCH_BITS == 32
2632	uint32_t efl = pCtx->eflags.u32;
2633	#else
2634	uint64_t efl = pCtx->rflags;
2635	#endif
2636	char szEFlags[80];
2637	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2638
2639	/*
2640	* Format the registers.
2641	*/
2642	#if HC_ARCH_BITS == 32
2643	pHlp->pfnPrintf(pHlp,
2644	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
2645	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
2646	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
2647	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
2648	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
2649	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2650	,
2651	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
2652	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
2653	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2654	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
2655	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
2656	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
2657	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2658	#else
2659	pHlp->pfnPrintf(pHlp,
2660	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
2661	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
2662	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
2663	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
2664	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
2665	"r14=%016RX64 r15=%016RX64\n"
2666	"iopl=%d %31s\n"
2667	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
2668	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
2669	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
2670	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
2671	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
2672	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
2673	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
2674	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
2675	,
2676	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
2677	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
2678	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
2679	/pCtx->r8, pCtx->r9,/ pCtx->r10,
2680	pCtx->r11, pCtx->r12, pCtx->r13,
2681	pCtx->r14, pCtx->r15,
2682	X86_EFL_GET_IOPL(efl), szEFlags,
2683	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
2684	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
2685	pCtx->cr4, pCtx->ldtr, pCtx->tr,
2686	pCtx->dr0, pCtx->dr1, pCtx->dr2,
2687	pCtx->dr3, pCtx->dr6, pCtx->dr7,
2688	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
2689	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
2690	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
2691	#endif
2692	}
2693
2694	/**
2695	* Structure used when disassembling and instructions in DBGF.
2696	* This is used so the reader function can get the stuff it needs.
2697	*/
2698	typedef struct CPUMDISASSTATE
2699	{
2700	/** Pointer to the CPU structure. */
2701	PDISCPUSTATE pCpu;
2702	/** Pointer to the VM. */
2703	PVM pVM;
2704	/** Pointer to the VMCPU. */
2705	PVMCPU pVCpu;
2706	/** Pointer to the first byte in the segment. */
2707	RTGCUINTPTR GCPtrSegBase;
2708	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
2709	RTGCUINTPTR GCPtrSegEnd;
2710	/** The size of the segment minus 1. */
2711	RTGCUINTPTR cbSegLimit;
2712	/** Pointer to the current page - R3 Ptr. */
2713	void const *pvPageR3;
2714	/** Pointer to the current page - GC Ptr. */
2715	RTGCPTR pvPageGC;
2716	/** The lock information that PGMPhysReleasePageMappingLock needs. */
2717	PGMPAGEMAPLOCK PageMapLock;
2718	/** Whether the PageMapLock is valid or not. */
2719	bool fLocked;
2720	/** 64 bits mode or not. */
2721	bool f64Bits;
2722	} CPUMDISASSTATE, *PCPUMDISASSTATE;
2723
2724
2725	/**
2726	* @callback_method_impl{FNDISREADBYTES}
2727	*/
2728	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
2729	{
2730	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
2731	for (;;)
2732	{
2733	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
2734
2735	/*
2736	* Need to update the page translation?
2737	*/
2738	if ( !pState->pvPageR3
2739	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
2740	{
2741	int rc = VINF_SUCCESS;
2742
2743	/* translate the address */
2744	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
2745	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
2746	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
2747	{
2748	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
2749	if (!pState->pvPageR3)
2750	rc = VERR_INVALID_POINTER;
2751	}
2752	else
2753	{
2754	/* Release mapping lock previously acquired. */
2755	if (pState->fLocked)
2756	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
2757	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
2758	pState->fLocked = RT_SUCCESS_NP(rc);
2759	}
2760	if (RT_FAILURE(rc))
2761	{
2762	pState->pvPageR3 = NULL;
2763	return rc;
2764	}
2765	}
2766
2767	/*
2768	* Check the segment limit.
2769	*/
2770	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
2771	return VERR_OUT_OF_SELECTOR_BOUNDS;
2772
2773	/*
2774	* Calc how much we can read.
2775	*/
2776	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
2777	if (!pState->f64Bits)
2778	{
2779	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
2780	if (cb > cbSeg && cbSeg)
2781	cb = cbSeg;
2782	}
2783	if (cb > cbMaxRead)
2784	cb = cbMaxRead;
2785
2786	/*
2787	* Read and advance or exit.
2788	*/
2789	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
2790	offInstr += (uint8_t)cb;
2791	if (cb >= cbMinRead)
2792	{
2793	pDis->cbCachedInstr = offInstr;
2794	return VINF_SUCCESS;
2795	}
2796	cbMinRead -= (uint8_t)cb;
2797	cbMaxRead -= (uint8_t)cb;
2798	}
2799	}
2800
2801
2802	/**
2803	* Disassemble an instruction and return the information in the provided structure.
2804	*
2805	* @returns VBox status code.
2806	* @param pVM The cross context VM structure.
2807	* @param pVCpu The cross context virtual CPU structure.
2808	* @param pCtx Pointer to the guest CPU context.
2809	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
2810	* @param pCpu Disassembly state.
2811	* @param pszPrefix String prefix for logging (debug only).
2812	*
2813	*/
2814	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
2815	const char *pszPrefix)
2816	{
2817	CPUMDISASSTATE State;
2818	int rc;
2819
2820	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
2821	State.pCpu = pCpu;
2822	State.pvPageGC = 0;
2823	State.pvPageR3 = NULL;
2824	State.pVM = pVM;
2825	State.pVCpu = pVCpu;
2826	State.fLocked = false;
2827	State.f64Bits = false;
2828
2829	/*
2830	* Get selector information.
2831	*/
2832	DISCPUMODE enmDisCpuMode;
2833	if ( (pCtx->cr0 & X86_CR0_PE)
2834	&& pCtx->eflags.Bits.u1VM == 0)
2835	{
2836	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2837	{
2838	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
2839	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
2840	# endif
2841	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
2842	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
2843	}
2844	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
2845	State.GCPtrSegBase = pCtx->cs.u64Base;
2846	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
2847	State.cbSegLimit = pCtx->cs.u32Limit;
2848	enmDisCpuMode = (State.f64Bits)
2849	? DISCPUMODE_64BIT
2850	: pCtx->cs.Attr.n.u1DefBig
2851	? DISCPUMODE_32BIT
2852	: DISCPUMODE_16BIT;
2853	}
2854	else
2855	{
2856	/* real or V86 mode */
2857	enmDisCpuMode = DISCPUMODE_16BIT;
2858	State.GCPtrSegBase = pCtx->cs.Sel * 16;
2859	State.GCPtrSegEnd = 0xFFFFFFFF;
2860	State.cbSegLimit = 0xFFFFFFFF;
2861	}
2862
2863	/*
2864	* Disassemble the instruction.
2865	*/
2866	uint32_t cbInstr;
2867	#ifndef LOG_ENABLED
2868	RT_NOREF_PV(pszPrefix);
2869	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
2870	if (RT_SUCCESS(rc))
2871	{
2872	#else
2873	char szOutput[160];
2874	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
2875	pCpu, &cbInstr, szOutput, sizeof(szOutput));
2876	if (RT_SUCCESS(rc))
2877	{
2878	/* log it */
2879	if (pszPrefix)
2880	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
2881	else
2882	Log(("%s", szOutput));
2883	#endif
2884	rc = VINF_SUCCESS;
2885	}
2886	else
2887	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
2888
2889	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
2890	if (State.fLocked)
2891	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
2892
2893	return rc;
2894	}
2895
2896
2897
2898	/**
2899	* API for controlling a few of the CPU features found in CR4.
2900	*
2901	* Currently only X86_CR4_TSD is accepted as input.
2902	*
2903	* @returns VBox status code.
2904	*
2905	* @param pVM The cross context VM structure.
2906	* @param fOr The CR4 OR mask.
2907	* @param fAnd The CR4 AND mask.
2908	*/
2909	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
2910	{
2911	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
2912	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
2913
2914	pVM->cpum.s.CR4.OrMask &= fAnd;
2915	pVM->cpum.s.CR4.OrMask \|= fOr;
2916
2917	return VINF_SUCCESS;
2918	}
2919
2920
2921	/**
2922	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
2923	*
2924	* Only REM should ever call this function!
2925	*
2926	* @returns The changed flags.
2927	* @param pVCpu The cross context virtual CPU structure.
2928	* @param puCpl Where to return the current privilege level (CPL).
2929	*/
2930	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
2931	{
2932	Assert(!pVCpu->cpum.s.fRawEntered);
2933	Assert(!pVCpu->cpum.s.fRemEntered);
2934
2935	/*
2936	* Get the CPL first.
2937	*/
2938	*puCpl = CPUMGetGuestCPL(pVCpu);
2939
2940	/*
2941	* Get and reset the flags.
2942	*/
2943	uint32_t fFlags = pVCpu->cpum.s.fChanged;
2944	pVCpu->cpum.s.fChanged = 0;
2945
2946	/** @todo change the switcher to use the fChanged flags. */
2947	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
2948	{
2949	fFlags \|= CPUM_CHANGED_FPU_REM;
2950	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
2951	}
2952
2953	pVCpu->cpum.s.fRemEntered = true;
2954	return fFlags;
2955	}
2956
2957
2958	/**
2959	* Leaves REM.
2960	*
2961	* @param pVCpu The cross context virtual CPU structure.
2962	* @param fNoOutOfSyncSels This is @c false if there are out of sync
2963	* registers.
2964	*/
2965	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
2966	{
2967	Assert(!pVCpu->cpum.s.fRawEntered);
2968	Assert(pVCpu->cpum.s.fRemEntered);
2969
2970	RT_NOREF_PV(fNoOutOfSyncSels);
2971
2972	pVCpu->cpum.s.fRemEntered = false;
2973	}
2974
2975
2976	/**
2977	* Called when the ring-3 init phase completes.
2978	*
2979	* @returns VBox status code.
2980	* @param pVM The cross context VM structure.
2981	* @param enmWhat Which init phase.
2982	*/
2983	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2984	{
2985	switch (enmWhat)
2986	{
2987	case VMINITCOMPLETED_RING3:
2988	{
2989	/*
2990	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
2991	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
2992	*/
2993	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2994	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2995	{
2996	PVMCPU pVCpu = &pVM->aCpus[i];
2997	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
2998	if (fSupportsLongMode)
2999	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3000	}
3001
3002	cpumR3MsrRegStats(pVM);
3003	break;
3004	}
3005
3006	default:
3007	break;
3008	}
3009	return VINF_SUCCESS;
3010	}
3011
3012
3013	/**
3014	* Called when the ring-0 init phases completed.
3015	*
3016	* @param pVM The cross context VM structure.
3017	*/
3018	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
3019	{
3020	/*
3021	* Log the cpuid.
3022	*/
3023	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
3024	RTCPUSET OnlineSet;
3025	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
3026	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
3027	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
3028	RTCPUID cCores = RTMpGetCoreCount();
3029	if (cCores)
3030	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
3031	LogRel(("*********************** CPUID dump **********************\n"));
3032	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
3033	LogRel(("\n"));
3034	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
3035	RTLogRelSetBuffering(fOldBuffered);
3036	LogRel(("****************** End of CPUID dump ********************\n"));
3037	}
3038

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 72208

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