CPUM.cpp@ 73770

Last change on this file since 73770 was 73745, checked in by vboxsync, 6 years ago
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1	/* $Id: CPUM.cpp 73745 2018-08-17 18:12:20Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for CPUMCTX. */
329	static const SSMFIELD g_aCpumX87Fields[] =
330	{
331	SSMFIELD_ENTRY( X86FXSTATE, FCW),
332	SSMFIELD_ENTRY( X86FXSTATE, FSW),
333	SSMFIELD_ENTRY( X86FXSTATE, FTW),
334	SSMFIELD_ENTRY( X86FXSTATE, FOP),
335	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
336	SSMFIELD_ENTRY( X86FXSTATE, CS),
337	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
338	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
339	SSMFIELD_ENTRY( X86FXSTATE, DS),
340	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
341	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
342	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
343	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
344	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
345	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
346	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
347	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
348	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
349	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
350	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
351	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
352	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
353	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
354	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
355	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
356	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
357	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
358	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
359	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
360	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
361	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
362	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
363	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
364	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
365	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
366	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
367	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
368	SSMFIELD_ENTRY_TERM()
369	};
370
371	/** Saved state field descriptors for X86XSAVEHDR. */
372	static const SSMFIELD g_aCpumXSaveHdrFields[] =
373	{
374	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/** Saved state field descriptors for X86XSAVEYMMHI. */
379	static const SSMFIELD g_aCpumYmmHiFields[] =
380	{
381	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
382	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
383	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
384	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
385	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
386	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
387	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
388	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
389	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
390	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
391	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
392	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
393	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
394	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
395	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
396	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
397	SSMFIELD_ENTRY_TERM()
398	};
399
400	/** Saved state field descriptors for X86XSAVEBNDREGS. */
401	static const SSMFIELD g_aCpumBndRegsFields[] =
402	{
403	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
404	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
405	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
406	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
407	SSMFIELD_ENTRY_TERM()
408	};
409
410	/** Saved state field descriptors for X86XSAVEBNDCFG. */
411	static const SSMFIELD g_aCpumBndCfgFields[] =
412	{
413	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
414	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	#if 0 /** @todo */
419	/** Saved state field descriptors for X86XSAVEOPMASK. */
420	static const SSMFIELD g_aCpumOpmaskFields[] =
421	{
422	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
423	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
424	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
425	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
426	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
427	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
428	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
429	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
430	SSMFIELD_ENTRY_TERM()
431	};
432	#endif
433
434	/** Saved state field descriptors for X86XSAVEZMMHI256. */
435	static const SSMFIELD g_aCpumZmmHi256Fields[] =
436	{
437	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
438	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
439	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
440	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
441	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
442	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
443	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
444	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
445	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
446	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
447	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
448	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
449	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
450	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
451	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
452	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
453	SSMFIELD_ENTRY_TERM()
454	};
455
456	/** Saved state field descriptors for X86XSAVEZMM16HI. */
457	static const SSMFIELD g_aCpumZmm16HiFields[] =
458	{
459	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
460	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
461	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
462	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
463	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
464	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
465	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
466	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
467	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
468	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
469	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
470	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
471	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
472	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
473	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
474	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
475	SSMFIELD_ENTRY_TERM()
476	};
477
478
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumX87FieldsMem[] =
483	{
484	SSMFIELD_ENTRY( X86FXSTATE, FCW),
485	SSMFIELD_ENTRY( X86FXSTATE, FSW),
486	SSMFIELD_ENTRY( X86FXSTATE, FTW),
487	SSMFIELD_ENTRY( X86FXSTATE, FOP),
488	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
489	SSMFIELD_ENTRY( X86FXSTATE, CS),
490	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
491	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
492	SSMFIELD_ENTRY( X86FXSTATE, DS),
493	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
494	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
495	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
496	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
497	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
498	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
499	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
500	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
501	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
502	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
503	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
504	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
505	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
506	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
507	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
508	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
509	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
510	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
511	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
512	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
513	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
514	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
515	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
516	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
517	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
518	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
519	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
520	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
521	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
522	};
523
524	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
525	* registeres changed. */
526	static const SSMFIELD g_aCpumCtxFieldsMem[] =
527	{
528	SSMFIELD_ENTRY( CPUMCTX, rdi),
529	SSMFIELD_ENTRY( CPUMCTX, rsi),
530	SSMFIELD_ENTRY( CPUMCTX, rbp),
531	SSMFIELD_ENTRY( CPUMCTX, rax),
532	SSMFIELD_ENTRY( CPUMCTX, rbx),
533	SSMFIELD_ENTRY( CPUMCTX, rdx),
534	SSMFIELD_ENTRY( CPUMCTX, rcx),
535	SSMFIELD_ENTRY( CPUMCTX, rsp),
536	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
537	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
538	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
539	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
540	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
541	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
542	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
543	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
544	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
545	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
546	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
547	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
548	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
549	SSMFIELD_ENTRY( CPUMCTX, rflags),
550	SSMFIELD_ENTRY( CPUMCTX, rip),
551	SSMFIELD_ENTRY( CPUMCTX, r8),
552	SSMFIELD_ENTRY( CPUMCTX, r9),
553	SSMFIELD_ENTRY( CPUMCTX, r10),
554	SSMFIELD_ENTRY( CPUMCTX, r11),
555	SSMFIELD_ENTRY( CPUMCTX, r12),
556	SSMFIELD_ENTRY( CPUMCTX, r13),
557	SSMFIELD_ENTRY( CPUMCTX, r14),
558	SSMFIELD_ENTRY( CPUMCTX, r15),
559	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
560	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
561	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
562	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
563	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
564	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
565	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
571	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
572	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
573	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
574	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
575	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
576	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
577	SSMFIELD_ENTRY( CPUMCTX, cr0),
578	SSMFIELD_ENTRY( CPUMCTX, cr2),
579	SSMFIELD_ENTRY( CPUMCTX, cr3),
580	SSMFIELD_ENTRY( CPUMCTX, cr4),
581	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
582	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
583	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
584	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
585	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
586	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
587	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
588	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
589	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
590	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
591	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
592	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
593	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
594	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
595	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
596	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
597	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
598	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
599	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
600	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
601	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
602	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
603	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
604	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
605	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
606	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
607	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
608	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
609	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
610	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
611	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
612	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
613	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
614	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumX87FieldsV16[] =
620	{
621	SSMFIELD_ENTRY( X86FXSTATE, FCW),
622	SSMFIELD_ENTRY( X86FXSTATE, FSW),
623	SSMFIELD_ENTRY( X86FXSTATE, FTW),
624	SSMFIELD_ENTRY( X86FXSTATE, FOP),
625	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
626	SSMFIELD_ENTRY( X86FXSTATE, CS),
627	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
628	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
629	SSMFIELD_ENTRY( X86FXSTATE, DS),
630	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
631	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
632	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
633	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
634	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
635	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
636	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
637	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
638	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
639	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
640	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
641	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
642	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
643	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
644	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
645	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
646	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
647	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
648	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
649	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
650	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
651	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
652	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
653	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
654	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
655	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
656	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
657	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
658	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
659	SSMFIELD_ENTRY_TERM()
660	};
661
662	/** Saved state field descriptors for CPUMCTX_VER1_6. */
663	static const SSMFIELD g_aCpumCtxFieldsV16[] =
664	{
665	SSMFIELD_ENTRY( CPUMCTX, rdi),
666	SSMFIELD_ENTRY( CPUMCTX, rsi),
667	SSMFIELD_ENTRY( CPUMCTX, rbp),
668	SSMFIELD_ENTRY( CPUMCTX, rax),
669	SSMFIELD_ENTRY( CPUMCTX, rbx),
670	SSMFIELD_ENTRY( CPUMCTX, rdx),
671	SSMFIELD_ENTRY( CPUMCTX, rcx),
672	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
673	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
674	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
675	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
676	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
677	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
678	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
679	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
680	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
681	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
682	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
683	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
684	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
685	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
686	SSMFIELD_ENTRY( CPUMCTX, rflags),
687	SSMFIELD_ENTRY( CPUMCTX, rip),
688	SSMFIELD_ENTRY( CPUMCTX, r8),
689	SSMFIELD_ENTRY( CPUMCTX, r9),
690	SSMFIELD_ENTRY( CPUMCTX, r10),
691	SSMFIELD_ENTRY( CPUMCTX, r11),
692	SSMFIELD_ENTRY( CPUMCTX, r12),
693	SSMFIELD_ENTRY( CPUMCTX, r13),
694	SSMFIELD_ENTRY( CPUMCTX, r14),
695	SSMFIELD_ENTRY( CPUMCTX, r15),
696	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
697	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
698	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
699	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
700	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
701	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
702	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
703	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
704	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
705	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
706	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
707	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
708	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
709	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
710	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
711	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
712	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
713	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
714	SSMFIELD_ENTRY( CPUMCTX, cr0),
715	SSMFIELD_ENTRY( CPUMCTX, cr2),
716	SSMFIELD_ENTRY( CPUMCTX, cr3),
717	SSMFIELD_ENTRY( CPUMCTX, cr4),
718	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
719	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
720	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
721	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
722	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
723	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
724	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
725	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
726	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
727	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
728	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
729	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
730	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
731	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
732	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
733	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
734	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
735	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
736	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
737	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
738	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
739	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
740	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
741	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
742	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
743	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
744	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
745	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
746	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
747	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
748	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
749	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
750	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
751	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
752	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
753	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
754	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
755	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
756	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
757	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
758	SSMFIELD_ENTRY_TERM()
759	};
760
761
762	/**
763	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
764	*
765	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
766	* (last instruction pointer, last data pointer, last opcode) except when the ES
767	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
768	* clear these registers there is potential, local FPU leakage from a process
769	* using the FPU to another.
770	*
771	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
772	*
773	* @param pVM The cross context VM structure.
774	*/
775	static void cpumR3CheckLeakyFpu(PVM pVM)
776	{
777	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
778	uint32_t const u32Family = u32CpuVersion >> 8;
779	if ( u32Family >= 6 /* K7 and higher */
780	&& ASMIsAmdCpu())
781	{
782	uint32_t cExt = ASMCpuId_EAX(0x80000000);
783	if (ASMIsValidExtRange(cExt))
784	{
785	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
786	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
787	{
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
790	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
791	}
792	}
793	}
794	}
795
796
797	/**
798	* Frees memory allocated for the SVM hardware virtualization state.
799	*
800	* @param pVM The cross context VM structure.
801	*/
802	static void cpumR3FreeSvmHwVirtState(PVM pVM)
803	{
804	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
805	for (VMCPUID i = 0; i < pVM->cCpus; i++)
806	{
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
809	{
810	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
811	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
812	}
813	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
814
815	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
816	{
817	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
818	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
819	}
820
821	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
822	{
823	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
824	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
825	}
826	}
827	}
828
829
830	/**
831	* Allocates memory for the SVM hardware virtualization state.
832	*
833	* @returns VBox status code.
834	* @param pVM The cross context VM structure.
835	*/
836	static int cpumR3AllocSvmHwVirtState(PVM pVM)
837	{
838	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
839
840	int rc = VINF_SUCCESS;
841	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
842	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846
847	/*
848	* Allocate the nested-guest VMCB.
849	*/
850	SUPPAGE SupNstGstVmcbPage;
851	RT_ZERO(SupNstGstVmcbPage);
852	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
853	Assert(SVM_VMCB_PAGES == 1);
854	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
855	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
856	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
857	if (RT_FAILURE(rc))
858	{
859	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
860	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
861	break;
862	}
863	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
864
865	/*
866	* Allocate the MSRPM (MSR Permission bitmap).
867	*/
868	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
869	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
870	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
871	if (RT_FAILURE(rc))
872	{
873	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
874	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
875	SVM_MSRPM_PAGES));
876	break;
877	}
878
879	/*
880	* Allocate the IOPM (IO Permission bitmap).
881	*/
882	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
883	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
884	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
885	if (RT_FAILURE(rc))
886	{
887	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
888	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
889	SVM_IOPM_PAGES));
890	break;
891	}
892	}
893
894	/* On any failure, cleanup. */
895	if (RT_FAILURE(rc))
896	cpumR3FreeSvmHwVirtState(pVM);
897
898	return rc;
899	}
900
901
902	/**
903	* Frees memory allocated for the VMX hardware virtualization state.
904	*
905	* @param pVM The cross context VM structure.
906	*/
907	static void cpumR3FreeVmxHwVirtState(PVM pVM)
908	{
909	Assert(pVM->cpum.ro.GuestFeatures.fVmx);
910	for (VMCPUID i = 0; i < pVM->cCpus; i++)
911	{
912	PVMCPU pVCpu = &pVM->aCpus[i];
913	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3)
914	{
915	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
916	pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3 = NULL;
917	}
918	}
919	}
920
921
922	/**
923	* Allocates memory for the VMX hardware virtualization state.
924	*
925	* @returns VBox status code.
926	* @param pVM The cross context VM structure.
927	*/
928	static int cpumR3AllocVmxHwVirtState(PVM pVM)
929	{
930	int rc = VINF_SUCCESS;
931	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS\n", pVM->cCpus * VMX_V_VMCS_SIZE));
932	for (VMCPUID i = 0; i < pVM->cCpus; i++)
933	{
934	PVMCPU pVCpu = &pVM->aCpus[i];
935
936	/*
937	* Allocate the nested-guest current VMCS.
938	*/
939	SUPPAGE SupNstGstVmcsPage;
940	RT_ZERO(SupNstGstVmcsPage);
941	SupNstGstVmcsPage.Phys = NIL_RTHCPHYS;
942	Assert(VMX_V_VMCS_PAGES == 1);
943	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
944	rc = SUPR3PageAllocEx(VMX_V_VMCS_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3,
945	&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR0, &SupNstGstVmcsPage);
946	if (RT_FAILURE(rc))
947	{
948	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
949	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
950	break;
951	}
952	}
953
954	/* On any failure, cleanup. */
955	if (RT_FAILURE(rc))
956	cpumR3FreeVmxHwVirtState(pVM);
957
958	return rc;
959	}
960
961
962	/**
963	* Displays the host and guest VMX features.
964	*
965	* @param pVM The cross context VM structure.
966	* @param pHlp The info helper functions.
967	* @param pszArgs "terse", "default" or "verbose".
968	*/
969	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
970	{
971	RT_NOREF(pszArgs);
972	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
973	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
974	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
975	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA)
976	{
977	#define VMXFEATDUMP(a_szDesc, a_Var) \
978	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
979
980	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
981	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
982	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
983	/* Basic. */
984	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
985	/* Pin-based controls. */
986	VMXFEATDUMP("ExtIntExit - External interrupt VM-exit ", fVmxExtIntExit);
987	VMXFEATDUMP("NmiExit - NMI VM-exit ", fVmxNmiExit);
988	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
989	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
990	/* Processor-based controls. */
991	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
992	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
993	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
994	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
995	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
996	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
997	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
998	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
999	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1000	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1001	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1002	VMXFEATDUMP("TprShadow - TPR shadow ", fVmxTprShadow);
1003	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1004	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1005	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1006	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1007	VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag ", fVmxMonitorTrapFlag);
1008	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1009	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1010	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1011	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1012	/* Secondary processor-based controls. */
1013	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1014	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1015	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1016	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1017	VMXFEATDUMP("VirtX2Apic - Virtualize-x2APIC accesses ", fVmxVirtX2ApicAccess);
1018	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1019	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1020	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1021	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1022	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1023	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1024	/* VM-entry controls. */
1025	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1026	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1027	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER on VM-entry ", fVmxEntryLoadEferMsr);
1028	/* VM-exit controls. */
1029	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1030	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1031	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1032	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER on VM-exit ", fVmxExitSaveEferMsr);
1033	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER on VM-exit ", fVmxExitLoadEferMsr);
1034	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1035	VMXFEATDUMP("ExitStoreEferLma - Store EFER.LMA on VM-exit ", fVmxExitStoreEferLma);
1036	VMXFEATDUMP("VmwriteAll - VMWRITE to any VMCS field ", fVmxVmwriteAll);
1037	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1038	#undef VMXFEATDUMP
1039	}
1040	else
1041	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1042	}
1043
1044
1045	/**
1046	* Initializes VMX host and guest features.
1047	*
1048	* @param pVM The cross context VM structure.
1049	*
1050	* @remarks This must be called only after HM has fully initialized since it calls
1051	* into HM to retrieve VMX and related MSRs.
1052	*/
1053	static void cpumR3InitVmxCpuFeatures(PVM pVM)
1054	{
1055	/*
1056	* Init. host features.
1057	*/
1058	PCPUMFEATURES pHostFeat = &pVM->cpum.s.HostFeatures;
1059	VMXMSRS VmxMsrs;
1060	int rc = HMVmxGetHostMsrs(pVM, &VmxMsrs);
1061	if (RT_SUCCESS(rc))
1062	{
1063	/* Basic information. */
1064	pHostFeat->fVmxInsOutInfo = RT_BF_GET(VmxMsrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1065
1066	/* Pin-based VM-execution controls. */
1067	uint32_t const fPinCtls = VmxMsrs.PinCtls.n.allowed1;
1068	pHostFeat->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1069	pHostFeat->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1070	pHostFeat->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1071	pHostFeat->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1072
1073	/* Processor-based VM-execution controls. */
1074	uint32_t const fProcCtls = VmxMsrs.ProcCtls.n.allowed1;
1075	pHostFeat->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1076	pHostFeat->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1077	pHostFeat->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1078	pHostFeat->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1079	pHostFeat->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1080	pHostFeat->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1081	pHostFeat->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1082	pHostFeat->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1083	pHostFeat->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1084	pHostFeat->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1085	pHostFeat->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1086	pHostFeat->fVmxTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1087	pHostFeat->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1088	pHostFeat->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1089	pHostFeat->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1090	pHostFeat->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1091	pHostFeat->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1092	pHostFeat->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1093	pHostFeat->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1094	pHostFeat->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1095	pHostFeat->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1096
1097	/* Secondary processor-based VM-execution controls. */
1098	if (pHostFeat->fVmxSecondaryExecCtls)
1099	{
1100	uint32_t const fProcCtls2 = VmxMsrs.ProcCtls2.n.allowed1;
1101	pHostFeat->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1102	pHostFeat->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1103	pHostFeat->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1104	pHostFeat->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1105	pHostFeat->fVmxVirtX2ApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS);
1106	pHostFeat->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1107	pHostFeat->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1108	pHostFeat->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1109	pHostFeat->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1110	pHostFeat->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1111	pHostFeat->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1112	}
1113
1114	/* VM-entry controls. */
1115	uint32_t const fEntryCtls = VmxMsrs.EntryCtls.n.allowed1;
1116	pHostFeat->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1117	pHostFeat->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1118	pHostFeat->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1119
1120	/* VM-exit controls. */
1121	uint32_t const fExitCtls = VmxMsrs.ExitCtls.n.allowed1;
1122	pHostFeat->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1123	pHostFeat->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1124	pHostFeat->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1125	pHostFeat->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1126	pHostFeat->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1127	pHostFeat->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER);
1128
1129	/* Miscellaneous data. */
1130	uint32_t const fMiscData = VmxMsrs.u64Misc;
1131	pHostFeat->fVmxExitStoreEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_STORE_EFER_LMA);
1132	pHostFeat->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1133	pHostFeat->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1134	}
1135
1136	/*
1137	* Initialize the set of VMX features we emulate.
1138	* Note! Some bits might be reported as 1 always if they fall under the default1 class bits
1139	* (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1140	*/
1141	CPUMFEATURES EmuFeat;
1142	RT_ZERO(EmuFeat);
1143	EmuFeat.fVmx = 1;
1144	EmuFeat.fVmxInsOutInfo = 0;
1145	EmuFeat.fVmxExtIntExit = 1;
1146	EmuFeat.fVmxNmiExit = 1;
1147	EmuFeat.fVmxVirtNmi = 0;
1148	EmuFeat.fVmxPreemptTimer = 0;
1149	EmuFeat.fVmxIntWindowExit = 1;
1150	EmuFeat.fVmxTscOffsetting = 1;
1151	EmuFeat.fVmxHltExit = 1;
1152	EmuFeat.fVmxInvlpgExit = 1;
1153	EmuFeat.fVmxMwaitExit = 1;
1154	EmuFeat.fVmxRdpmcExit = 1;
1155	EmuFeat.fVmxRdtscExit = 1;
1156	EmuFeat.fVmxCr3LoadExit = 1;
1157	EmuFeat.fVmxCr3StoreExit = 1;
1158	EmuFeat.fVmxCr8LoadExit = 1;
1159	EmuFeat.fVmxCr8StoreExit = 1;
1160	EmuFeat.fVmxTprShadow = 0;
1161	EmuFeat.fVmxNmiWindowExit = 0;
1162	EmuFeat.fVmxMovDRxExit = 1;
1163	EmuFeat.fVmxUncondIoExit = 1;
1164	EmuFeat.fVmxUseIoBitmaps = 1;
1165	EmuFeat.fVmxMonitorTrapFlag = 0;
1166	EmuFeat.fVmxUseMsrBitmaps = 0;
1167	EmuFeat.fVmxMonitorExit = 1;
1168	EmuFeat.fVmxPauseExit = 1;
1169	EmuFeat.fVmxSecondaryExecCtls = 1;
1170	EmuFeat.fVmxVirtApicAccess = 0;
1171	EmuFeat.fVmxEpt = 0;
1172	EmuFeat.fVmxDescTableExit = 1;
1173	EmuFeat.fVmxRdtscp = 1;
1174	EmuFeat.fVmxVirtX2ApicAccess = 0;
1175	EmuFeat.fVmxVpid = 0;
1176	EmuFeat.fVmxWbinvdExit = 1;
1177	EmuFeat.fVmxUnrestrictedGuest = 0;
1178	EmuFeat.fVmxPauseLoopExit = 0;
1179	EmuFeat.fVmxInvpcid = 1;
1180	EmuFeat.fVmxVmcsShadowing = 0;
1181	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1182	EmuFeat.fVmxIa32eModeGuest = 1;
1183	EmuFeat.fVmxEntryLoadEferMsr = 1;
1184	EmuFeat.fVmxExitSaveDebugCtls = 1;
1185	EmuFeat.fVmxHostAddrSpaceSize = 1;
1186	EmuFeat.fVmxExitAckExtInt = 0;
1187	EmuFeat.fVmxExitSaveEferMsr = 1;
1188	EmuFeat.fVmxExitLoadEferMsr = 1;
1189	EmuFeat.fVmxSavePreemptTimer = 0;
1190	EmuFeat.fVmxExitStoreEferLma = 1;
1191	EmuFeat.fVmxVmwriteAll = 0;
1192	EmuFeat.fVmxEntryInjectSoftInt = 0;
1193
1194	/*
1195	* Explode guest features.
1196	*
1197	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1198	* by the hardware, hence we merge our emulated features with the host features below.
1199	*/
1200	bool const fHostSupportsVmx = pHostFeat->fVmx;
1201	AssertLogRelReturnVoid(!fHostSupportsVmx \|\| HMIsVmxSupported(pVM));
1202	PCCPUMFEATURES pBaseFeat = fHostSupportsVmx ? pHostFeat : &EmuFeat;
1203	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1204	pGuestFeat->fVmx = (pBaseFeat->fVmx & EmuFeat.fVmx );
1205	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1206	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1207	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1208	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1209	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1210	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1211	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1212	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1213	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1214	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1215	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1216	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1217	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1218	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1219	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1220	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1221	pGuestFeat->fVmxTprShadow = (pBaseFeat->fVmxTprShadow & EmuFeat.fVmxTprShadow );
1222	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1223	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1224	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1225	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1226	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1227	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1228	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1229	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1230	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1231	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1232	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1233	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1234	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1235	pGuestFeat->fVmxVirtX2ApicAccess = (pBaseFeat->fVmxVirtX2ApicAccess & EmuFeat.fVmxVirtX2ApicAccess );
1236	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1237	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1238	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1239	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1240	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1241	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1242	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1243	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1244	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr);
1245	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1246	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1247	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1248	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1249	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1250	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1251	pGuestFeat->fVmxExitStoreEferLma = (pBaseFeat->fVmxExitStoreEferLma & EmuFeat.fVmxExitStoreEferLma );
1252	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1253	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1254	}
1255
1256
1257	/**
1258	* Initializes the CPUM.
1259	*
1260	* @returns VBox status code.
1261	* @param pVM The cross context VM structure.
1262	*/
1263	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1264	{
1265	LogFlow(("CPUMR3Init\n"));
1266
1267	/*
1268	* Assert alignment, sizes and tables.
1269	*/
1270	AssertCompileMemberAlignment(VM, cpum.s, 32);
1271	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1272	AssertCompileSizeAlignment(CPUMCTX, 64);
1273	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1274	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1275	AssertCompileMemberAlignment(VM, cpum, 64);
1276	AssertCompileMemberAlignment(VM, aCpus, 64);
1277	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1278	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
1279	#ifdef VBOX_STRICT
1280	int rc2 = cpumR3MsrStrictInitChecks();
1281	AssertRCReturn(rc2, rc2);
1282	#endif
1283
1284	/*
1285	* Initialize offsets.
1286	*/
1287
1288	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
1289	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
1290	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
1291
1292
1293	/* Calculate the offset from CPUMCPU to CPUM. */
1294	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1295	{
1296	PVMCPU pVCpu = &pVM->aCpus[i];
1297
1298	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
1299	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
1300	}
1301
1302	/*
1303	* Gather info about the host CPU.
1304	*/
1305	if (!ASMHasCpuId())
1306	{
1307	Log(("The CPU doesn't support CPUID!\n"));
1308	return VERR_UNSUPPORTED_CPU;
1309	}
1310
1311	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1312
1313	PCPUMCPUIDLEAF paLeaves;
1314	uint32_t cLeaves;
1315	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1316	AssertLogRelRCReturn(rc, rc);
1317
1318	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
1319	RTMemFree(paLeaves);
1320	AssertLogRelRCReturn(rc, rc);
1321	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1322
1323	/*
1324	* Check that the CPU supports the minimum features we require.
1325	*/
1326	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
1327	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
1328	if (!pVM->cpum.s.HostFeatures.fMmx)
1329	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
1330	if (!pVM->cpum.s.HostFeatures.fTsc)
1331	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
1332
1333	/*
1334	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
1335	*/
1336	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
1337	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
1338
1339	/*
1340	* Figure out which XSAVE/XRSTOR features are available on the host.
1341	*/
1342	uint64_t fXcr0Host = 0;
1343	uint64_t fXStateHostMask = 0;
1344	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
1345	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
1346	{
1347	fXStateHostMask = fXcr0Host = ASMGetXcr0();
1348	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
1349	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
1350	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
1351	}
1352	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
1353	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
1354	fXStateHostMask = 0;
1355	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1356	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1357
1358	/*
1359	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
1360	*/
1361	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1362	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1363	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
1364
1365	uint8_t *pbXStates;
1366	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
1367	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
1368	AssertLogRelRCReturn(rc, rc);
1369
1370	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1371	{
1372	PVMCPU pVCpu = &pVM->aCpus[i];
1373
1374	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1375	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1376	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1377	pbXStates += cbMaxXState;
1378
1379	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1380	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1381	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1382	pbXStates += cbMaxXState;
1383
1384	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1385	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1386	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1387	pbXStates += cbMaxXState;
1388
1389	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
1390	}
1391
1392	/*
1393	* Register saved state data item.
1394	*/
1395	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
1396	NULL, cpumR3LiveExec, NULL,
1397	NULL, cpumR3SaveExec, NULL,
1398	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1399	if (RT_FAILURE(rc))
1400	return rc;
1401
1402	/*
1403	* Register info handlers and registers with the debugger facility.
1404	*/
1405	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1406	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1407	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1408	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1409	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1410	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1411	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1412	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1413	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1414	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1415	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1416	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1417	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1418	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
1419	&cpumR3InfoVmxFeatures);
1420
1421	rc = cpumR3DbgInit(pVM);
1422	if (RT_FAILURE(rc))
1423	return rc;
1424
1425	/*
1426	* Check if we need to workaround partial/leaky FPU handling.
1427	*/
1428	cpumR3CheckLeakyFpu(pVM);
1429
1430	/*
1431	* Initialize the Guest CPUID and MSR states.
1432	*/
1433	rc = cpumR3InitCpuIdAndMsrs(pVM);
1434	if (RT_FAILURE(rc))
1435	return rc;
1436
1437	/*
1438	* Allocate memory required by the guest hardware virtualization state.
1439	*/
1440	if (pVM->cpum.ro.GuestFeatures.fVmx)
1441	rc = cpumR3AllocVmxHwVirtState(pVM);
1442	else if (pVM->cpum.ro.GuestFeatures.fSvm)
1443	rc = cpumR3AllocSvmHwVirtState(pVM);
1444	if (RT_FAILURE(rc))
1445	return rc;
1446
1447	/*
1448	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1449	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1450	* of processors from (cpuid(4).eax >> 26) + 1.
1451	*
1452	* Note: this code is obsolete, but let's keep it here for reference.
1453	* Purpose is valid when we artificially cap the max std id to less than 4.
1454	*
1455	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
1456	* after VMINITCOMPLETED_HM.
1457	*/
1458	if (VM_IS_RAW_MODE_ENABLED(pVM))
1459	{
1460	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1461	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1462	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1463	}
1464
1465	CPUMR3Reset(pVM);
1466	return VINF_SUCCESS;
1467	}
1468
1469
1470	/**
1471	* Applies relocations to data and code managed by this
1472	* component. This function will be called at init and
1473	* whenever the VMM need to relocate it self inside the GC.
1474	*
1475	* The CPUM will update the addresses used by the switcher.
1476	*
1477	* @param pVM The cross context VM structure.
1478	*/
1479	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1480	{
1481	LogFlow(("CPUMR3Relocate\n"));
1482
1483	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1484	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1485
1486	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1487	{
1488	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1489	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1490	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1491	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1492
1493	/* Recheck the guest DRx values in raw-mode. */
1494	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1495	}
1496	}
1497
1498
1499	/**
1500	* Terminates the CPUM.
1501	*
1502	* Termination means cleaning up and freeing all resources,
1503	* the VM it self is at this point powered off or suspended.
1504	*
1505	* @returns VBox status code.
1506	* @param pVM The cross context VM structure.
1507	*/
1508	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1509	{
1510	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1511	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1512	{
1513	PVMCPU pVCpu = &pVM->aCpus[i];
1514	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1515
1516	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1517	pVCpu->cpum.s.uMagic = 0;
1518	pCtx->dr[5] = 0;
1519	}
1520	#endif
1521
1522	if (pVM->cpum.ro.GuestFeatures.fSvm)
1523	cpumR3FreeVmxHwVirtState(pVM);
1524	else if (pVM->cpum.ro.GuestFeatures.fSvm)
1525	cpumR3FreeSvmHwVirtState(pVM);
1526	return VINF_SUCCESS;
1527	}
1528
1529
1530	/**
1531	* Resets a virtual CPU.
1532	*
1533	* Used by CPUMR3Reset and CPU hot plugging.
1534	*
1535	* @param pVM The cross context VM structure.
1536	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1537	* being reset. This may differ from the current EMT.
1538	*/
1539	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1540	{
1541	/** @todo anything different for VCPU > 0? */
1542	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1543
1544	/*
1545	* Initialize everything to ZERO first.
1546	*/
1547	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1548
1549	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1550	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1551	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
1552
1553	pVCpu->cpum.s.fUseFlags = fUseFlags;
1554
1555	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1556	pCtx->eip = 0x0000fff0;
1557	pCtx->edx = 0x00000600; /* P6 processor */
1558	pCtx->eflags.Bits.u1Reserved0 = 1;
1559
1560	pCtx->cs.Sel = 0xf000;
1561	pCtx->cs.ValidSel = 0xf000;
1562	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1563	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1564	pCtx->cs.u32Limit = 0x0000ffff;
1565	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1566	pCtx->cs.Attr.n.u1Present = 1;
1567	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1568
1569	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1570	pCtx->ds.u32Limit = 0x0000ffff;
1571	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1572	pCtx->ds.Attr.n.u1Present = 1;
1573	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1574
1575	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1576	pCtx->es.u32Limit = 0x0000ffff;
1577	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1578	pCtx->es.Attr.n.u1Present = 1;
1579	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1580
1581	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1582	pCtx->fs.u32Limit = 0x0000ffff;
1583	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1584	pCtx->fs.Attr.n.u1Present = 1;
1585	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1586
1587	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1588	pCtx->gs.u32Limit = 0x0000ffff;
1589	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1590	pCtx->gs.Attr.n.u1Present = 1;
1591	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1592
1593	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1594	pCtx->ss.u32Limit = 0x0000ffff;
1595	pCtx->ss.Attr.n.u1Present = 1;
1596	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1597	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1598
1599	pCtx->idtr.cbIdt = 0xffff;
1600	pCtx->gdtr.cbGdt = 0xffff;
1601
1602	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1603	pCtx->ldtr.u32Limit = 0xffff;
1604	pCtx->ldtr.Attr.n.u1Present = 1;
1605	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1606
1607	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1608	pCtx->tr.u32Limit = 0xffff;
1609	pCtx->tr.Attr.n.u1Present = 1;
1610	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1611
1612	pCtx->dr[6] = X86_DR6_INIT_VAL;
1613	pCtx->dr[7] = X86_DR7_INIT_VAL;
1614
1615	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1616	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1617	pFpuCtx->FCW = 0x37f;
1618
1619	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1620	IA-32 Processor States Following Power-up, Reset, or INIT */
1621	pFpuCtx->MXCSR = 0x1F80;
1622	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1623
1624	pCtx->aXcr[0] = XSAVE_C_X87;
1625	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
1626	{
1627	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1628	as we don't know what happened before. (Bother optimize later?) */
1629	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1630	}
1631
1632	/*
1633	* MSRs.
1634	*/
1635	/* Init PAT MSR */
1636	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
1637
1638	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1639	* The Intel docs don't mention it. */
1640	Assert(!pCtx->msrEFER);
1641
1642	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1643	is supposed to be here, just trying provide useful/sensible values. */
1644	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1645	if (pRange)
1646	{
1647	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1648	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1649	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1650	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1651	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1652	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1653	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1654	}
1655
1656	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1657
1658	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1659	* called from each EMT while we're getting called by CPUMR3Reset()
1660	* iteratively on the same thread. Fix later. */
1661	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1662	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1663	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1664	#endif
1665
1666
1667	/* C-state control. Guesses. */
1668	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1669	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
1670	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
1671	* functionality. The default value must be different due to incompatible write mask.
1672	*/
1673	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
1674	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
1675	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
1676	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
1677
1678	/*
1679	* Hardware virtualization state.
1680	*/
1681	pCtx->hwvirt.fGif = true;
1682
1683	/* SVM. */
1684	if (pCtx->hwvirt.svm.CTX_SUFF(pVmcb))
1685	{
1686	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1687	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1688	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1689	}
1690	}
1691
1692
1693	/**
1694	* Resets the CPU.
1695	*
1696	* @returns VINF_SUCCESS.
1697	* @param pVM The cross context VM structure.
1698	*/
1699	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1700	{
1701	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1702	{
1703	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1704
1705	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1706	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1707
1708	/* Magic marker for searching in crash dumps. */
1709	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1710	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1711	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1712	#endif
1713	}
1714	}
1715
1716
1717
1718
1719	/**
1720	* Pass 0 live exec callback.
1721	*
1722	* @returns VINF_SSM_DONT_CALL_AGAIN.
1723	* @param pVM The cross context VM structure.
1724	* @param pSSM The saved state handle.
1725	* @param uPass The pass (0).
1726	*/
1727	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1728	{
1729	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1730	cpumR3SaveCpuId(pVM, pSSM);
1731	return VINF_SSM_DONT_CALL_AGAIN;
1732	}
1733
1734
1735	/**
1736	* Execute state save operation.
1737	*
1738	* @returns VBox status code.
1739	* @param pVM The cross context VM structure.
1740	* @param pSSM SSM operation handle.
1741	*/
1742	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1743	{
1744	/*
1745	* Save.
1746	*/
1747	SSMR3PutU32(pSSM, pVM->cCpus);
1748	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1749	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1750	{
1751	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1752
1753	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1754
1755	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1756	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1757	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1758	if (pGstCtx->fXStateMask != 0)
1759	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1760	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1761	{
1762	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1763	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1764	}
1765	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1766	{
1767	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1768	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1769	}
1770	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1771	{
1772	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1773	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1774	}
1775	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1776	{
1777	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1778	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1779	}
1780	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1781	{
1782	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1783	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1784	}
1785	if (pVM->cpum.ro.GuestFeatures.fSvm)
1786	{
1787	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1788	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
1789	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
1790	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
1791	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
1792	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
1793	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
1794	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
1795	g_aSvmHwvirtHostState, NULL /* pvUser */);
1796	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
1797	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1798	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
1799	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
1800	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
1801	}
1802	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1803	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1804	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1805	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1806	}
1807
1808	cpumR3SaveCpuId(pVM, pSSM);
1809	return VINF_SUCCESS;
1810	}
1811
1812
1813	/**
1814	* @callback_method_impl{FNSSMINTLOADPREP}
1815	*/
1816	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1817	{
1818	NOREF(pSSM);
1819	pVM->cpum.s.fPendingRestore = true;
1820	return VINF_SUCCESS;
1821	}
1822
1823
1824	/**
1825	* @callback_method_impl{FNSSMINTLOADEXEC}
1826	*/
1827	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1828	{
1829	int rc; /* Only for AssertRCReturn use. */
1830
1831	/*
1832	* Validate version.
1833	*/
1834	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
1835	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1836	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1837	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1838	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1839	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
1840	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1841	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1842	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1843	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1844	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1845	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1846	{
1847	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1848	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1849	}
1850
1851	if (uPass == SSM_PASS_FINAL)
1852	{
1853	/*
1854	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1855	* really old SSM file versions.)
1856	*/
1857	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1858	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1859	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1860	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1861
1862	/*
1863	* Figure x86 and ctx field definitions to use for older states.
1864	*/
1865	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1866	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1867	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1868	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1869	{
1870	paCpumCtx1Fields = g_aCpumX87FieldsV16;
1871	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1872	}
1873	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1874	{
1875	paCpumCtx1Fields = g_aCpumX87FieldsMem;
1876	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1877	}
1878
1879	/*
1880	* The hyper state used to preceed the CPU count. Starting with
1881	* XSAVE it was moved down till after we've got the count.
1882	*/
1883	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1884	{
1885	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1886	{
1887	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1888	X86FXSTATE Ign;
1889	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1890	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1891	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1892	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1893	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1894	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1895	pVCpu->cpum.s.Hyper.rsp = uRSP;
1896	}
1897	}
1898
1899	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1900	{
1901	uint32_t cCpus;
1902	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1903	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1904	VERR_SSM_UNEXPECTED_DATA);
1905	}
1906	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1907	\|\| pVM->cCpus == 1,
1908	("cCpus=%u\n", pVM->cCpus),
1909	VERR_SSM_UNEXPECTED_DATA);
1910
1911	uint32_t cbMsrs = 0;
1912	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1913	{
1914	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1915	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1916	VERR_SSM_UNEXPECTED_DATA);
1917	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1918	VERR_SSM_UNEXPECTED_DATA);
1919	}
1920
1921	/*
1922	* Do the per-CPU restoring.
1923	*/
1924	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1925	{
1926	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1927	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1928
1929	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1930	{
1931	/*
1932	* The XSAVE saved state layout moved the hyper state down here.
1933	*/
1934	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1935	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1936	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1937	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1938	pVCpu->cpum.s.Hyper.rsp = uRSP;
1939	AssertRCReturn(rc, rc);
1940
1941	/*
1942	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1943	*/
1944	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1945	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1946	AssertRCReturn(rc, rc);
1947
1948	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
1949	if (pGstCtx->fXStateMask != 0)
1950	{
1951	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
1952	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
1953	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
1954	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
1955	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
1956	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1957	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1958	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1959	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1960	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1961	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1962	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1963	}
1964
1965	/* Check that the XCR0 mask is valid (invalid results in #GP). */
1966	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
1967	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
1968	{
1969	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
1970	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
1971	VERR_CPUM_INVALID_XCR0);
1972	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
1973	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1974	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
1975	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1976	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
1977	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
1978	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
1979	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
1980	}
1981
1982	/* Check that the XCR1 is zero, as we don't implement it yet. */
1983	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
1984
1985	/*
1986	* Restore the individual extended state components we support.
1987	*/
1988	if (pGstCtx->fXStateMask != 0)
1989	{
1990	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
1991	0, g_aCpumXSaveHdrFields, NULL);
1992	AssertRCReturn(rc, rc);
1993	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
1994	("bmXState=%#RX64 fXStateMask=%#RX64\n",
1995	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
1996	VERR_CPUM_INVALID_XSAVE_HDR);
1997	}
1998	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1999	{
2000	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2001	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2002	}
2003	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2004	{
2005	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2006	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2007	}
2008	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2009	{
2010	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2011	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2012	}
2013	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2014	{
2015	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2016	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2017	}
2018	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2019	{
2020	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2021	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2022	}
2023	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2024	{
2025	if (pVM->cpum.ro.GuestFeatures.fSvm)
2026	{
2027	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2028	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2029	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2030	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2031	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2032	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2033	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2034	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2035	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2036	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2037	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2038	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2039	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2040	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2041	}
2042	}
2043	}
2044	else
2045	{
2046	/*
2047	* Pre XSAVE saved state.
2048	*/
2049	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2050	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2051	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2052	}
2053
2054	/*
2055	* Restore a couple of flags and the MSRs.
2056	*/
2057	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2058	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2059
2060	rc = VINF_SUCCESS;
2061	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2062	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2063	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2064	{
2065	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2066	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2067	}
2068	AssertRCReturn(rc, rc);
2069
2070	/* REM and other may have cleared must-be-one fields in DR6 and
2071	DR7, fix these. */
2072	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2073	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2074	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2075	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2076	}
2077
2078	/* Older states does not have the internal selector register flags
2079	and valid selector value. Supply those. */
2080	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2081	{
2082	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2083	{
2084	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2085	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2086	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2087	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2088	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2089	if (fValid)
2090	{
2091	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2092	{
2093	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2094	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2095	}
2096
2097	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2098	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2099	}
2100	else
2101	{
2102	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2103	{
2104	paSelReg[iSelReg].fFlags = 0;
2105	paSelReg[iSelReg].ValidSel = 0;
2106	}
2107
2108	/* This might not be 104% correct, but I think it's close
2109	enough for all practical purposes... (REM always loaded
2110	LDTR registers.) */
2111	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2112	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2113	}
2114	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2115	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2116	}
2117	}
2118
2119	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2120	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2121	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2122	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2123	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2124
2125	/*
2126	* A quick sanity check.
2127	*/
2128	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2129	{
2130	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2131	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2132	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2133	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2134	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2135	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2136	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2137	}
2138	}
2139
2140	pVM->cpum.s.fPendingRestore = false;
2141
2142	/*
2143	* Guest CPUIDs.
2144	*/
2145	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2146	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2147	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2148	}
2149
2150
2151	/**
2152	* @callback_method_impl{FNSSMINTLOADDONE}
2153	*/
2154	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2155	{
2156	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2157	return VINF_SUCCESS;
2158
2159	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2160	if (pVM->cpum.s.fPendingRestore)
2161	{
2162	LogRel(("CPUM: Missing state!\n"));
2163	return VERR_INTERNAL_ERROR_2;
2164	}
2165
2166	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2167	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2168	{
2169	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2170
2171	/* Notify PGM of the NXE states in case they've changed. */
2172	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2173
2174	/* During init. this is done in CPUMR3InitCompleted(). */
2175	if (fSupportsLongMode)
2176	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2177	}
2178	return VINF_SUCCESS;
2179	}
2180
2181
2182	/**
2183	* Checks if the CPUM state restore is still pending.
2184	*
2185	* @returns true / false.
2186	* @param pVM The cross context VM structure.
2187	*/
2188	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2189	{
2190	return pVM->cpum.s.fPendingRestore;
2191	}
2192
2193
2194	/**
2195	* Formats the EFLAGS value into mnemonics.
2196	*
2197	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2198	* @param efl The EFLAGS value.
2199	*/
2200	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2201	{
2202	/*
2203	* Format the flags.
2204	*/
2205	static const struct
2206	{
2207	const char pszSet; const char pszClear; uint32_t fFlag;
2208	} s_aFlags[] =
2209	{
2210	{ "vip",NULL, X86_EFL_VIP },
2211	{ "vif",NULL, X86_EFL_VIF },
2212	{ "ac", NULL, X86_EFL_AC },
2213	{ "vm", NULL, X86_EFL_VM },
2214	{ "rf", NULL, X86_EFL_RF },
2215	{ "nt", NULL, X86_EFL_NT },
2216	{ "ov", "nv", X86_EFL_OF },
2217	{ "dn", "up", X86_EFL_DF },
2218	{ "ei", "di", X86_EFL_IF },
2219	{ "tf", NULL, X86_EFL_TF },
2220	{ "nt", "pl", X86_EFL_SF },
2221	{ "nz", "zr", X86_EFL_ZF },
2222	{ "ac", "na", X86_EFL_AF },
2223	{ "po", "pe", X86_EFL_PF },
2224	{ "cy", "nc", X86_EFL_CF },
2225	};
2226	char *psz = pszEFlags;
2227	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2228	{
2229	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2230	if (pszAdd)
2231	{
2232	strcpy(psz, pszAdd);
2233	psz += strlen(pszAdd);
2234	*psz++ = ' ';
2235	}
2236	}
2237	psz[-1] = '\0';
2238	}
2239
2240
2241	/**
2242	* Formats a full register dump.
2243	*
2244	* @param pVM The cross context VM structure.
2245	* @param pCtx The context to format.
2246	* @param pCtxCore The context core to format.
2247	* @param pHlp Output functions.
2248	* @param enmType The dump type.
2249	* @param pszPrefix Register name prefix.
2250	*/
2251	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2252	const char *pszPrefix)
2253	{
2254	NOREF(pVM);
2255
2256	/*
2257	* Format the EFLAGS.
2258	*/
2259	uint32_t efl = pCtxCore->eflags.u32;
2260	char szEFlags[80];
2261	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2262
2263	/*
2264	* Format the registers.
2265	*/
2266	switch (enmType)
2267	{
2268	case CPUMDUMPTYPE_TERSE:
2269	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2270	pHlp->pfnPrintf(pHlp,
2271	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2272	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2273	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2274	"%sr14=%016RX64 %sr15=%016RX64\n"
2275	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2276	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2277	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2278	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2279	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2280	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2281	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2282	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2283	else
2284	pHlp->pfnPrintf(pHlp,
2285	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2286	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2287	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2288	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2289	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2290	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2291	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2292	break;
2293
2294	case CPUMDUMPTYPE_DEFAULT:
2295	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2296	pHlp->pfnPrintf(pHlp,
2297	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2298	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2299	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2300	"%sr14=%016RX64 %sr15=%016RX64\n"
2301	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2302	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2303	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2304	,
2305	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2306	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2307	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2308	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2309	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2310	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2311	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2312	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2313	else
2314	pHlp->pfnPrintf(pHlp,
2315	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2316	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2317	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2318	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2319	,
2320	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2321	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2322	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2323	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2324	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2325	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2326	break;
2327
2328	case CPUMDUMPTYPE_VERBOSE:
2329	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2330	pHlp->pfnPrintf(pHlp,
2331	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2332	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2333	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2334	"%sr14=%016RX64 %sr15=%016RX64\n"
2335	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2336	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2337	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2338	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2339	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2340	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2341	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2342	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2343	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2344	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2345	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2346	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2347	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2348	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2349	,
2350	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2351	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2352	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2353	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2354	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2355	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2356	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2357	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2358	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2359	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2360	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2361	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2362	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2363	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2364	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2365	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2366	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2367	else
2368	pHlp->pfnPrintf(pHlp,
2369	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2370	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2371	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2372	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2373	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2374	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2375	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2376	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2377	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2378	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2379	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2380	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2381	,
2382	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2383	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2384	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2385	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2386	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2387	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2388	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2389	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2390	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2391	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2392	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2393	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2394
2395	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
2396	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
2397	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
2398	if (pCtx->CTX_SUFF(pXState))
2399	{
2400	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2401	pHlp->pfnPrintf(pHlp,
2402	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2403	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2404	,
2405	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
2406	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
2407	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
2408	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
2409	);
2410	/*
2411	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
2412	* not (FP)R0-7 as Intel SDM suggests.
2413	*/
2414	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
2415	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
2416	{
2417	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
2418	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
2419	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
2420	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
2421	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
2422	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
2423	iExponent -= 16383; /* subtract bias */
2424	/** @todo This isn't entirenly correct and needs more work! */
2425	pHlp->pfnPrintf(pHlp,
2426	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
2427	pszPrefix, iST, pszPrefix, iFPR,
2428	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
2429	uTag, chSign, iInteger, u64Fraction, iExponent);
2430	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
2431	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2432	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
2433	else
2434	pHlp->pfnPrintf(pHlp, "\n");
2435	}
2436
2437	/* XMM/YMM/ZMM registers. */
2438	if (pCtx->fXStateMask & XSAVE_C_YMM)
2439	{
2440	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2441	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2442	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2443	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2444	pszPrefix, i, i < 10 ? " " : "",
2445	pYmmHiCtx->aYmmHi[i].au32[3],
2446	pYmmHiCtx->aYmmHi[i].au32[2],
2447	pYmmHiCtx->aYmmHi[i].au32[1],
2448	pYmmHiCtx->aYmmHi[i].au32[0],
2449	pFpuCtx->aXMM[i].au32[3],
2450	pFpuCtx->aXMM[i].au32[2],
2451	pFpuCtx->aXMM[i].au32[1],
2452	pFpuCtx->aXMM[i].au32[0]);
2453	else
2454	{
2455	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2456	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2457	pHlp->pfnPrintf(pHlp,
2458	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2459	pszPrefix, i, i < 10 ? " " : "",
2460	pZmmHi256->aHi256Regs[i].au32[7],
2461	pZmmHi256->aHi256Regs[i].au32[6],
2462	pZmmHi256->aHi256Regs[i].au32[5],
2463	pZmmHi256->aHi256Regs[i].au32[4],
2464	pZmmHi256->aHi256Regs[i].au32[3],
2465	pZmmHi256->aHi256Regs[i].au32[2],
2466	pZmmHi256->aHi256Regs[i].au32[1],
2467	pZmmHi256->aHi256Regs[i].au32[0],
2468	pYmmHiCtx->aYmmHi[i].au32[3],
2469	pYmmHiCtx->aYmmHi[i].au32[2],
2470	pYmmHiCtx->aYmmHi[i].au32[1],
2471	pYmmHiCtx->aYmmHi[i].au32[0],
2472	pFpuCtx->aXMM[i].au32[3],
2473	pFpuCtx->aXMM[i].au32[2],
2474	pFpuCtx->aXMM[i].au32[1],
2475	pFpuCtx->aXMM[i].au32[0]);
2476
2477	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2478	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2479	pHlp->pfnPrintf(pHlp,
2480	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2481	pszPrefix, i + 16,
2482	pZmm16Hi->aRegs[i].au32[15],
2483	pZmm16Hi->aRegs[i].au32[14],
2484	pZmm16Hi->aRegs[i].au32[13],
2485	pZmm16Hi->aRegs[i].au32[12],
2486	pZmm16Hi->aRegs[i].au32[11],
2487	pZmm16Hi->aRegs[i].au32[10],
2488	pZmm16Hi->aRegs[i].au32[9],
2489	pZmm16Hi->aRegs[i].au32[8],
2490	pZmm16Hi->aRegs[i].au32[7],
2491	pZmm16Hi->aRegs[i].au32[6],
2492	pZmm16Hi->aRegs[i].au32[5],
2493	pZmm16Hi->aRegs[i].au32[4],
2494	pZmm16Hi->aRegs[i].au32[3],
2495	pZmm16Hi->aRegs[i].au32[2],
2496	pZmm16Hi->aRegs[i].au32[1],
2497	pZmm16Hi->aRegs[i].au32[0]);
2498	}
2499	}
2500	else
2501	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2502	pHlp->pfnPrintf(pHlp,
2503	i & 1
2504	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2505	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2506	pszPrefix, i, i < 10 ? " " : "",
2507	pFpuCtx->aXMM[i].au32[3],
2508	pFpuCtx->aXMM[i].au32[2],
2509	pFpuCtx->aXMM[i].au32[1],
2510	pFpuCtx->aXMM[i].au32[0]);
2511
2512	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2513	{
2514	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2515	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2516	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2517	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2518	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2519	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2520	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2521	}
2522
2523	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2524	{
2525	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2526	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2527	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2528	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2529	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2530	}
2531
2532	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2533	{
2534	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2535	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2536	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2537	}
2538
2539	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2540	if (pFpuCtx->au32RsrvdRest[i])
2541	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2542	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
2543	}
2544
2545	pHlp->pfnPrintf(pHlp,
2546	"%sEFER =%016RX64\n"
2547	"%sPAT =%016RX64\n"
2548	"%sSTAR =%016RX64\n"
2549	"%sCSTAR =%016RX64\n"
2550	"%sLSTAR =%016RX64\n"
2551	"%sSFMASK =%016RX64\n"
2552	"%sKERNELGSBASE =%016RX64\n",
2553	pszPrefix, pCtx->msrEFER,
2554	pszPrefix, pCtx->msrPAT,
2555	pszPrefix, pCtx->msrSTAR,
2556	pszPrefix, pCtx->msrCSTAR,
2557	pszPrefix, pCtx->msrLSTAR,
2558	pszPrefix, pCtx->msrSFMASK,
2559	pszPrefix, pCtx->msrKERNELGSBASE);
2560	break;
2561	}
2562	}
2563
2564
2565	/**
2566	* Display all cpu states and any other cpum info.
2567	*
2568	* @param pVM The cross context VM structure.
2569	* @param pHlp The info helper functions.
2570	* @param pszArgs Arguments, ignored.
2571	*/
2572	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2573	{
2574	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2575	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2576	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2577	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2578	cpumR3InfoHost(pVM, pHlp, pszArgs);
2579	}
2580
2581
2582	/**
2583	* Parses the info argument.
2584	*
2585	* The argument starts with 'verbose', 'terse' or 'default' and then
2586	* continues with the comment string.
2587	*
2588	* @param pszArgs The pointer to the argument string.
2589	* @param penmType Where to store the dump type request.
2590	* @param ppszComment Where to store the pointer to the comment string.
2591	*/
2592	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2593	{
2594	if (!pszArgs)
2595	{
2596	*penmType = CPUMDUMPTYPE_DEFAULT;
2597	*ppszComment = "";
2598	}
2599	else
2600	{
2601	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2602	{
2603	pszArgs += 7;
2604	*penmType = CPUMDUMPTYPE_VERBOSE;
2605	}
2606	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2607	{
2608	pszArgs += 5;
2609	*penmType = CPUMDUMPTYPE_TERSE;
2610	}
2611	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2612	{
2613	pszArgs += 7;
2614	*penmType = CPUMDUMPTYPE_DEFAULT;
2615	}
2616	else
2617	*penmType = CPUMDUMPTYPE_DEFAULT;
2618	*ppszComment = RTStrStripL(pszArgs);
2619	}
2620	}
2621
2622
2623	/**
2624	* Display the guest cpu state.
2625	*
2626	* @param pVM The cross context VM structure.
2627	* @param pHlp The info helper functions.
2628	* @param pszArgs Arguments.
2629	*/
2630	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2631	{
2632	CPUMDUMPTYPE enmType;
2633	const char *pszComment;
2634	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2635
2636	PVMCPU pVCpu = VMMGetCpu(pVM);
2637	if (!pVCpu)
2638	pVCpu = &pVM->aCpus[0];
2639
2640	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2641
2642	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2643	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2644	}
2645
2646
2647	/**
2648	* Displays an SVM VMCB control area.
2649	*
2650	* @param pHlp The info helper functions.
2651	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
2652	* @param pszPrefix Caller specified string prefix.
2653	*/
2654	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
2655	{
2656	AssertReturnVoid(pHlp);
2657	AssertReturnVoid(pVmcbCtrl);
2658
2659	pHlp->pfnPrintf(pHlp, "%su16InterceptRdCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
2660	pHlp->pfnPrintf(pHlp, "%su16InterceptWrCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
2661	pHlp->pfnPrintf(pHlp, "%su16InterceptRdDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
2662	pHlp->pfnPrintf(pHlp, "%su16InterceptWrDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
2663	pHlp->pfnPrintf(pHlp, "%su32InterceptXcpt = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
2664	pHlp->pfnPrintf(pHlp, "%su64InterceptCtrl = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
2665	pHlp->pfnPrintf(pHlp, "%su16PauseFilterThreshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
2666	pHlp->pfnPrintf(pHlp, "%su16PauseFilterCount = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
2667	pHlp->pfnPrintf(pHlp, "%su64IOPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
2668	pHlp->pfnPrintf(pHlp, "%su64MSRPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
2669	pHlp->pfnPrintf(pHlp, "%su64TSCOffset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
2670	pHlp->pfnPrintf(pHlp, "%sTLBCtrl\n", pszPrefix);
2671	pHlp->pfnPrintf(pHlp, "%s u32ASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
2672	pHlp->pfnPrintf(pHlp, "%s u8TLBFlush = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
2673	pHlp->pfnPrintf(pHlp, "%sIntCtrl\n", pszPrefix);
2674	pHlp->pfnPrintf(pHlp, "%s u8VTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
2675	pHlp->pfnPrintf(pHlp, "%s u1VIrqPending = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
2676	pHlp->pfnPrintf(pHlp, "%s u1VGif = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
2677	pHlp->pfnPrintf(pHlp, "%s u4VIntrPrio = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
2678	pHlp->pfnPrintf(pHlp, "%s u1IgnoreTPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
2679	pHlp->pfnPrintf(pHlp, "%s u1VIntrMasking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
2680	pHlp->pfnPrintf(pHlp, "%s u1VGifEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
2681	pHlp->pfnPrintf(pHlp, "%s u1AvicEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
2682	pHlp->pfnPrintf(pHlp, "%s u8VIntrVector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
2683	pHlp->pfnPrintf(pHlp, "%sIntShadow\n", pszPrefix);
2684	pHlp->pfnPrintf(pHlp, "%s u1IntShadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
2685	pHlp->pfnPrintf(pHlp, "%s u1GuestIntMask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
2686	pHlp->pfnPrintf(pHlp, "%su64ExitCode = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
2687	pHlp->pfnPrintf(pHlp, "%su64ExitInfo1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
2688	pHlp->pfnPrintf(pHlp, "%su64ExitInfo2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
2689	pHlp->pfnPrintf(pHlp, "%sExitIntInfo\n", pszPrefix);
2690	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
2691	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
2692	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
2693	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
2694	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
2695	pHlp->pfnPrintf(pHlp, "%sNestedPaging and SEV\n", pszPrefix);
2696	pHlp->pfnPrintf(pHlp, "%s u1NestedPaging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
2697	pHlp->pfnPrintf(pHlp, "%s u1Sev = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
2698	pHlp->pfnPrintf(pHlp, "%s u1SevEs = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
2699	pHlp->pfnPrintf(pHlp, "%sAvicBar\n", pszPrefix);
2700	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
2701	pHlp->pfnPrintf(pHlp, "%sEventInject\n", pszPrefix);
2702	pHlp->pfnPrintf(pHlp, "%s EventInject\n", pszPrefix);
2703	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
2704	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
2705	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
2706	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
2707	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
2708	pHlp->pfnPrintf(pHlp, "%su64NestedPagingCR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
2709	pHlp->pfnPrintf(pHlp, "%sLBR virtualization\n", pszPrefix);
2710	pHlp->pfnPrintf(pHlp, "%s u1LbrVirt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
2711	pHlp->pfnPrintf(pHlp, "%s u1VirtVmsaveVmload = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
2712	pHlp->pfnPrintf(pHlp, "%su32VmcbCleanBits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
2713	pHlp->pfnPrintf(pHlp, "%su64NextRIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
2714	pHlp->pfnPrintf(pHlp, "%scbInstrFetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
2715	pHlp->pfnPrintf(pHlp, "%sabInstr = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
2716	pHlp->pfnPrintf(pHlp, "%sAvicBackingPagePtr\n", pszPrefix);
2717	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
2718	pHlp->pfnPrintf(pHlp, "%sAvicLogicalTablePtr\n", pszPrefix);
2719	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
2720	pHlp->pfnPrintf(pHlp, "%sAvicPhysicalTablePtr\n", pszPrefix);
2721	pHlp->pfnPrintf(pHlp, "%s u8LastGuestCoreId = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
2722	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
2723	}
2724
2725
2726	/**
2727	* Helper for dumping the SVM VMCB selector registers.
2728	*
2729	* @param pHlp The info helper functions.
2730	* @param pSel Pointer to the SVM selector register.
2731	* @param pszName Name of the selector.
2732	* @param pszPrefix Caller specified string prefix.
2733	*/
2734	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
2735	{
2736	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
2737	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
2738	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
2739	}
2740
2741
2742	/**
2743	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
2744	*
2745	* @param pHlp The info helper functions.
2746	* @param pXdtr Pointer to the descriptor table register.
2747	* @param pszName Name of the descriptor table register.
2748	* @param pszPrefix Caller specified string prefix.
2749	*/
2750	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
2751	{
2752	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
2753	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
2754	}
2755
2756
2757	/**
2758	* Displays an SVM VMCB state-save area.
2759	*
2760	* @param pHlp The info helper functions.
2761	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
2762	* @param pszPrefix Caller specified string prefix.
2763	*/
2764	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
2765	{
2766	AssertReturnVoid(pHlp);
2767	AssertReturnVoid(pVmcbStateSave);
2768
2769	char szEFlags[80];
2770	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
2771
2772	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
2773	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
2774	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
2775	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
2776	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
2777	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
2778	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
2779	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
2780	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
2781	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
2782	pHlp->pfnPrintf(pHlp, "%su8CPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
2783	pHlp->pfnPrintf(pHlp, "%su64EFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
2784	pHlp->pfnPrintf(pHlp, "%su64CR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
2785	pHlp->pfnPrintf(pHlp, "%su64CR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
2786	pHlp->pfnPrintf(pHlp, "%su64CR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
2787	pHlp->pfnPrintf(pHlp, "%su64DR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
2788	pHlp->pfnPrintf(pHlp, "%su64DR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
2789	pHlp->pfnPrintf(pHlp, "%su64RFlags = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
2790	pHlp->pfnPrintf(pHlp, "%su64RIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
2791	pHlp->pfnPrintf(pHlp, "%su64RSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
2792	pHlp->pfnPrintf(pHlp, "%su64RAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
2793	pHlp->pfnPrintf(pHlp, "%su64STAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
2794	pHlp->pfnPrintf(pHlp, "%su64LSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
2795	pHlp->pfnPrintf(pHlp, "%su64CSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
2796	pHlp->pfnPrintf(pHlp, "%su64SFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
2797	pHlp->pfnPrintf(pHlp, "%su64KernelGSBase = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
2798	pHlp->pfnPrintf(pHlp, "%su64SysEnterCS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
2799	pHlp->pfnPrintf(pHlp, "%su64SysEnterEIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
2800	pHlp->pfnPrintf(pHlp, "%su64SysEnterESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
2801	pHlp->pfnPrintf(pHlp, "%su64CR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
2802	pHlp->pfnPrintf(pHlp, "%su64PAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
2803	pHlp->pfnPrintf(pHlp, "%su64DBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
2804	pHlp->pfnPrintf(pHlp, "%su64BR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
2805	pHlp->pfnPrintf(pHlp, "%su64BR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
2806	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPFROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
2807	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPTO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
2808	}
2809
2810
2811	/**
2812	* Display the guest's hardware-virtualization cpu state.
2813	*
2814	* @param pVM The cross context VM structure.
2815	* @param pHlp The info helper functions.
2816	* @param pszArgs Arguments, ignored.
2817	*/
2818	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2819	{
2820	RT_NOREF(pszArgs);
2821
2822	PVMCPU pVCpu = VMMGetCpu(pVM);
2823	if (!pVCpu)
2824	pVCpu = &pVM->aCpus[0];
2825
2826	/*
2827	* Figure out what to dump.
2828	*
2829	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
2830	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2831	* dump hwvirt. state when the guest CPU is executing a nested-guest.
2832	*/
2833	/** @todo perhaps make this configurable through pszArgs, depending on how much
2834	* noise we wish to accept when nested hwvirt. isn't used. */
2835	#define CPUMHWVIRTDUMP_NONE (0)
2836	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2837	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2838	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2839	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2840
2841	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2842	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2843	bool const fSvm = pVM->cpum.ro.GuestFeatures.fSvm;
2844	bool const fVmx = pVM->cpum.ro.GuestFeatures.fVmx;
2845	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
2846	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2847	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2848	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2849	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
2850
2851	/*
2852	* Dump it.
2853	*/
2854	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2855
2856	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2857	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2858
2859	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
2860	":" : "");
2861	if (fDumpState & CPUMHWVIRTDUMP_SVM)
2862	{
2863	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
2864
2865	char szEFlags[80];
2866	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
2867	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2868	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2869	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2870	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2871	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
2872	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
2873	pHlp->pfnPrintf(pHlp, " HostState:\n");
2874	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2875	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2876	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2877	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2878	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2879	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2880	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2881	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
2882	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2883	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2884	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2885	pSel = &pCtx->hwvirt.svm.HostState.cs;
2886	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2887	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2888	pSel = &pCtx->hwvirt.svm.HostState.ss;
2889	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2890	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2891	pSel = &pCtx->hwvirt.svm.HostState.ds;
2892	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2893	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2894	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2895	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2896	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2897	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2898	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2899	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2900	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2901	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2902	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2903	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2904	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2905	}
2906
2907	if (fDumpState & CPUMHWVIRTDUMP_VMX)
2908	{
2909	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
2910	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
2911	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
2912	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
2913	pHlp->pfnPrintf(pHlp, " enmInstrDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmInstrDiag,
2914	HMVmxGetInstrDiagDesc(pCtx->hwvirt.vmx.enmInstrDiag));
2915	/** @todo NSTVMX: Dump remaining/new fields. */
2916	}
2917
2918	#undef CPUMHWVIRTDUMP_NONE
2919	#undef CPUMHWVIRTDUMP_COMMON
2920	#undef CPUMHWVIRTDUMP_SVM
2921	#undef CPUMHWVIRTDUMP_VMX
2922	#undef CPUMHWVIRTDUMP_LAST
2923	#undef CPUMHWVIRTDUMP_ALL
2924	}
2925
2926	/**
2927	* Display the current guest instruction
2928	*
2929	* @param pVM The cross context VM structure.
2930	* @param pHlp The info helper functions.
2931	* @param pszArgs Arguments, ignored.
2932	*/
2933	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2934	{
2935	NOREF(pszArgs);
2936
2937	PVMCPU pVCpu = VMMGetCpu(pVM);
2938	if (!pVCpu)
2939	pVCpu = &pVM->aCpus[0];
2940
2941	char szInstruction[256];
2942	szInstruction[0] = '\0';
2943	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2944	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
2945	}
2946
2947
2948	/**
2949	* Display the hypervisor cpu state.
2950	*
2951	* @param pVM The cross context VM structure.
2952	* @param pHlp The info helper functions.
2953	* @param pszArgs Arguments, ignored.
2954	*/
2955	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2956	{
2957	PVMCPU pVCpu = VMMGetCpu(pVM);
2958	if (!pVCpu)
2959	pVCpu = &pVM->aCpus[0];
2960
2961	CPUMDUMPTYPE enmType;
2962	const char *pszComment;
2963	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2964	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
2965	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
2966	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
2967	}
2968
2969
2970	/**
2971	* Display the host cpu state.
2972	*
2973	* @param pVM The cross context VM structure.
2974	* @param pHlp The info helper functions.
2975	* @param pszArgs Arguments, ignored.
2976	*/
2977	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2978	{
2979	CPUMDUMPTYPE enmType;
2980	const char *pszComment;
2981	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2982	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
2983
2984	PVMCPU pVCpu = VMMGetCpu(pVM);
2985	if (!pVCpu)
2986	pVCpu = &pVM->aCpus[0];
2987	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
2988
2989	/*
2990	* Format the EFLAGS.
2991	*/
2992	#if HC_ARCH_BITS == 32
2993	uint32_t efl = pCtx->eflags.u32;
2994	#else
2995	uint64_t efl = pCtx->rflags;
2996	#endif
2997	char szEFlags[80];
2998	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2999
3000	/*
3001	* Format the registers.
3002	*/
3003	#if HC_ARCH_BITS == 32
3004	pHlp->pfnPrintf(pHlp,
3005	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3006	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3007	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3008	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3009	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3010	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3011	,
3012	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
3013	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3014	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3015	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
3016	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3017	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3018	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3019	#else
3020	pHlp->pfnPrintf(pHlp,
3021	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3022	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3023	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3024	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3025	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3026	"r14=%016RX64 r15=%016RX64\n"
3027	"iopl=%d %31s\n"
3028	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3029	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3030	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
3031	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3032	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3033	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3034	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3035	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3036	,
3037	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
3038	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3039	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
3040	/pCtx->r8, pCtx->r9,/ pCtx->r10,
3041	pCtx->r11, pCtx->r12, pCtx->r13,
3042	pCtx->r14, pCtx->r15,
3043	X86_EFL_GET_IOPL(efl), szEFlags,
3044	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3045	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
3046	pCtx->cr4, pCtx->ldtr, pCtx->tr,
3047	pCtx->dr0, pCtx->dr1, pCtx->dr2,
3048	pCtx->dr3, pCtx->dr6, pCtx->dr7,
3049	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3050	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3051	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3052	#endif
3053	}
3054
3055	/**
3056	* Structure used when disassembling and instructions in DBGF.
3057	* This is used so the reader function can get the stuff it needs.
3058	*/
3059	typedef struct CPUMDISASSTATE
3060	{
3061	/** Pointer to the CPU structure. */
3062	PDISCPUSTATE pCpu;
3063	/** Pointer to the VM. */
3064	PVM pVM;
3065	/** Pointer to the VMCPU. */
3066	PVMCPU pVCpu;
3067	/** Pointer to the first byte in the segment. */
3068	RTGCUINTPTR GCPtrSegBase;
3069	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3070	RTGCUINTPTR GCPtrSegEnd;
3071	/** The size of the segment minus 1. */
3072	RTGCUINTPTR cbSegLimit;
3073	/** Pointer to the current page - R3 Ptr. */
3074	void const *pvPageR3;
3075	/** Pointer to the current page - GC Ptr. */
3076	RTGCPTR pvPageGC;
3077	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3078	PGMPAGEMAPLOCK PageMapLock;
3079	/** Whether the PageMapLock is valid or not. */
3080	bool fLocked;
3081	/** 64 bits mode or not. */
3082	bool f64Bits;
3083	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3084
3085
3086	/**
3087	* @callback_method_impl{FNDISREADBYTES}
3088	*/
3089	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3090	{
3091	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3092	for (;;)
3093	{
3094	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3095
3096	/*
3097	* Need to update the page translation?
3098	*/
3099	if ( !pState->pvPageR3
3100	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3101	{
3102	int rc = VINF_SUCCESS;
3103
3104	/* translate the address */
3105	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3106	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
3107	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
3108	{
3109	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3110	if (!pState->pvPageR3)
3111	rc = VERR_INVALID_POINTER;
3112	}
3113	else
3114	{
3115	/* Release mapping lock previously acquired. */
3116	if (pState->fLocked)
3117	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3118	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3119	pState->fLocked = RT_SUCCESS_NP(rc);
3120	}
3121	if (RT_FAILURE(rc))
3122	{
3123	pState->pvPageR3 = NULL;
3124	return rc;
3125	}
3126	}
3127
3128	/*
3129	* Check the segment limit.
3130	*/
3131	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3132	return VERR_OUT_OF_SELECTOR_BOUNDS;
3133
3134	/*
3135	* Calc how much we can read.
3136	*/
3137	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3138	if (!pState->f64Bits)
3139	{
3140	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3141	if (cb > cbSeg && cbSeg)
3142	cb = cbSeg;
3143	}
3144	if (cb > cbMaxRead)
3145	cb = cbMaxRead;
3146
3147	/*
3148	* Read and advance or exit.
3149	*/
3150	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3151	offInstr += (uint8_t)cb;
3152	if (cb >= cbMinRead)
3153	{
3154	pDis->cbCachedInstr = offInstr;
3155	return VINF_SUCCESS;
3156	}
3157	cbMinRead -= (uint8_t)cb;
3158	cbMaxRead -= (uint8_t)cb;
3159	}
3160	}
3161
3162
3163	/**
3164	* Disassemble an instruction and return the information in the provided structure.
3165	*
3166	* @returns VBox status code.
3167	* @param pVM The cross context VM structure.
3168	* @param pVCpu The cross context virtual CPU structure.
3169	* @param pCtx Pointer to the guest CPU context.
3170	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3171	* @param pCpu Disassembly state.
3172	* @param pszPrefix String prefix for logging (debug only).
3173	*
3174	*/
3175	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
3176	const char *pszPrefix)
3177	{
3178	CPUMDISASSTATE State;
3179	int rc;
3180
3181	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3182	State.pCpu = pCpu;
3183	State.pvPageGC = 0;
3184	State.pvPageR3 = NULL;
3185	State.pVM = pVM;
3186	State.pVCpu = pVCpu;
3187	State.fLocked = false;
3188	State.f64Bits = false;
3189
3190	/*
3191	* Get selector information.
3192	*/
3193	DISCPUMODE enmDisCpuMode;
3194	if ( (pCtx->cr0 & X86_CR0_PE)
3195	&& pCtx->eflags.Bits.u1VM == 0)
3196	{
3197	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3198	{
3199	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3200	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
3201	# endif
3202	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3203	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
3204	}
3205	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
3206	State.GCPtrSegBase = pCtx->cs.u64Base;
3207	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
3208	State.cbSegLimit = pCtx->cs.u32Limit;
3209	enmDisCpuMode = (State.f64Bits)
3210	? DISCPUMODE_64BIT
3211	: pCtx->cs.Attr.n.u1DefBig
3212	? DISCPUMODE_32BIT
3213	: DISCPUMODE_16BIT;
3214	}
3215	else
3216	{
3217	/* real or V86 mode */
3218	enmDisCpuMode = DISCPUMODE_16BIT;
3219	State.GCPtrSegBase = pCtx->cs.Sel * 16;
3220	State.GCPtrSegEnd = 0xFFFFFFFF;
3221	State.cbSegLimit = 0xFFFFFFFF;
3222	}
3223
3224	/*
3225	* Disassemble the instruction.
3226	*/
3227	uint32_t cbInstr;
3228	#ifndef LOG_ENABLED
3229	RT_NOREF_PV(pszPrefix);
3230	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
3231	if (RT_SUCCESS(rc))
3232	{
3233	#else
3234	char szOutput[160];
3235	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
3236	pCpu, &cbInstr, szOutput, sizeof(szOutput));
3237	if (RT_SUCCESS(rc))
3238	{
3239	/* log it */
3240	if (pszPrefix)
3241	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3242	else
3243	Log(("%s", szOutput));
3244	#endif
3245	rc = VINF_SUCCESS;
3246	}
3247	else
3248	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
3249
3250	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3251	if (State.fLocked)
3252	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3253
3254	return rc;
3255	}
3256
3257
3258
3259	/**
3260	* API for controlling a few of the CPU features found in CR4.
3261	*
3262	* Currently only X86_CR4_TSD is accepted as input.
3263	*
3264	* @returns VBox status code.
3265	*
3266	* @param pVM The cross context VM structure.
3267	* @param fOr The CR4 OR mask.
3268	* @param fAnd The CR4 AND mask.
3269	*/
3270	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3271	{
3272	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3273	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3274
3275	pVM->cpum.s.CR4.OrMask &= fAnd;
3276	pVM->cpum.s.CR4.OrMask \|= fOr;
3277
3278	return VINF_SUCCESS;
3279	}
3280
3281
3282	/**
3283	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3284	*
3285	* Only REM should ever call this function!
3286	*
3287	* @returns The changed flags.
3288	* @param pVCpu The cross context virtual CPU structure.
3289	* @param puCpl Where to return the current privilege level (CPL).
3290	*/
3291	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3292	{
3293	Assert(!pVCpu->cpum.s.fRawEntered);
3294	Assert(!pVCpu->cpum.s.fRemEntered);
3295
3296	/*
3297	* Get the CPL first.
3298	*/
3299	*puCpl = CPUMGetGuestCPL(pVCpu);
3300
3301	/*
3302	* Get and reset the flags.
3303	*/
3304	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3305	pVCpu->cpum.s.fChanged = 0;
3306
3307	/** @todo change the switcher to use the fChanged flags. */
3308	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3309	{
3310	fFlags \|= CPUM_CHANGED_FPU_REM;
3311	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3312	}
3313
3314	pVCpu->cpum.s.fRemEntered = true;
3315	return fFlags;
3316	}
3317
3318
3319	/**
3320	* Leaves REM.
3321	*
3322	* @param pVCpu The cross context virtual CPU structure.
3323	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3324	* registers.
3325	*/
3326	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3327	{
3328	Assert(!pVCpu->cpum.s.fRawEntered);
3329	Assert(pVCpu->cpum.s.fRemEntered);
3330
3331	RT_NOREF_PV(fNoOutOfSyncSels);
3332
3333	pVCpu->cpum.s.fRemEntered = false;
3334	}
3335
3336
3337	/**
3338	* Called when the ring-3 init phase completes.
3339	*
3340	* @returns VBox status code.
3341	* @param pVM The cross context VM structure.
3342	* @param enmWhat Which init phase.
3343	*/
3344	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
3345	{
3346	switch (enmWhat)
3347	{
3348	case VMINITCOMPLETED_RING3:
3349	{
3350	/*
3351	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
3352	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
3353	*/
3354	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3355	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3356	{
3357	PVMCPU pVCpu = &pVM->aCpus[i];
3358	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
3359	if (fSupportsLongMode)
3360	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3361	}
3362
3363	cpumR3MsrRegStats(pVM);
3364	break;
3365	}
3366
3367	case VMINITCOMPLETED_HM:
3368	{
3369	/*
3370	* Currently, nested VMX/SVM both derives their guest VMX/SVM CPUID bit from the host
3371	* CPUID bit. This could be later changed if we need to support nested-VMX on CPUs
3372	* that are not capable of VMX.
3373	*/
3374	if (pVM->cpum.s.GuestFeatures.fVmx)
3375	{
3376	Assert( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
3377	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
3378	cpumR3InitVmxCpuFeatures(pVM);
3379	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
3380	}
3381
3382	if (pVM->cpum.s.GuestFeatures.fVmx)
3383	LogRel(("CPUM: Enabled guest VMX support\n"));
3384	else if (pVM->cpum.s.GuestFeatures.fSvm)
3385	LogRel(("CPUM: Enabled guest SVM support\n"));
3386	break;
3387	}
3388
3389	default:
3390	break;
3391	}
3392	return VINF_SUCCESS;
3393	}
3394
3395
3396	/**
3397	* Called when the ring-0 init phases completed.
3398	*
3399	* @param pVM The cross context VM structure.
3400	*/
3401	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
3402	{
3403	/*
3404	* Log the cpuid.
3405	*/
3406	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
3407	RTCPUSET OnlineSet;
3408	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
3409	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
3410	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
3411	RTCPUID cCores = RTMpGetCoreCount();
3412	if (cCores)
3413	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
3414	LogRel(("*********************** CPUID dump **********************\n"));
3415	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
3416	LogRel(("\n"));
3417	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
3418	RTLogRelSetBuffering(fOldBuffered);
3419	LogRel(("****************** End of CPUID dump ********************\n"));
3420	}
3421

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 73770

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