CPUM.cpp@ 74043

Last change on this file since 74043 was 73870, checked in by vboxsync, 7 years ago
VMM: Nested VMX: Added VMX CPUID features for RDRAND, RDSEED and PML. Fixed incorrect VMCS field validation for guest-interrupt status.
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File size: 172.0 KB

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1	/* $Id: CPUM.cpp 73870 2018-08-24 09:39:44Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for CPUMCTX. */
329	static const SSMFIELD g_aCpumX87Fields[] =
330	{
331	SSMFIELD_ENTRY( X86FXSTATE, FCW),
332	SSMFIELD_ENTRY( X86FXSTATE, FSW),
333	SSMFIELD_ENTRY( X86FXSTATE, FTW),
334	SSMFIELD_ENTRY( X86FXSTATE, FOP),
335	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
336	SSMFIELD_ENTRY( X86FXSTATE, CS),
337	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
338	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
339	SSMFIELD_ENTRY( X86FXSTATE, DS),
340	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
341	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
342	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
343	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
344	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
345	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
346	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
347	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
348	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
349	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
350	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
351	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
352	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
353	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
354	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
355	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
356	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
357	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
358	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
359	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
360	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
361	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
362	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
363	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
364	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
365	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
366	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
367	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
368	SSMFIELD_ENTRY_TERM()
369	};
370
371	/** Saved state field descriptors for X86XSAVEHDR. */
372	static const SSMFIELD g_aCpumXSaveHdrFields[] =
373	{
374	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/** Saved state field descriptors for X86XSAVEYMMHI. */
379	static const SSMFIELD g_aCpumYmmHiFields[] =
380	{
381	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
382	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
383	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
384	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
385	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
386	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
387	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
388	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
389	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
390	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
391	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
392	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
393	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
394	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
395	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
396	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
397	SSMFIELD_ENTRY_TERM()
398	};
399
400	/** Saved state field descriptors for X86XSAVEBNDREGS. */
401	static const SSMFIELD g_aCpumBndRegsFields[] =
402	{
403	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
404	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
405	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
406	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
407	SSMFIELD_ENTRY_TERM()
408	};
409
410	/** Saved state field descriptors for X86XSAVEBNDCFG. */
411	static const SSMFIELD g_aCpumBndCfgFields[] =
412	{
413	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
414	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	#if 0 /** @todo */
419	/** Saved state field descriptors for X86XSAVEOPMASK. */
420	static const SSMFIELD g_aCpumOpmaskFields[] =
421	{
422	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
423	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
424	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
425	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
426	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
427	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
428	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
429	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
430	SSMFIELD_ENTRY_TERM()
431	};
432	#endif
433
434	/** Saved state field descriptors for X86XSAVEZMMHI256. */
435	static const SSMFIELD g_aCpumZmmHi256Fields[] =
436	{
437	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
438	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
439	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
440	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
441	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
442	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
443	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
444	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
445	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
446	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
447	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
448	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
449	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
450	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
451	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
452	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
453	SSMFIELD_ENTRY_TERM()
454	};
455
456	/** Saved state field descriptors for X86XSAVEZMM16HI. */
457	static const SSMFIELD g_aCpumZmm16HiFields[] =
458	{
459	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
460	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
461	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
462	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
463	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
464	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
465	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
466	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
467	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
468	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
469	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
470	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
471	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
472	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
473	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
474	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
475	SSMFIELD_ENTRY_TERM()
476	};
477
478
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumX87FieldsMem[] =
483	{
484	SSMFIELD_ENTRY( X86FXSTATE, FCW),
485	SSMFIELD_ENTRY( X86FXSTATE, FSW),
486	SSMFIELD_ENTRY( X86FXSTATE, FTW),
487	SSMFIELD_ENTRY( X86FXSTATE, FOP),
488	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
489	SSMFIELD_ENTRY( X86FXSTATE, CS),
490	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
491	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
492	SSMFIELD_ENTRY( X86FXSTATE, DS),
493	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
494	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
495	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
496	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
497	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
498	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
499	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
500	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
501	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
502	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
503	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
504	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
505	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
506	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
507	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
508	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
509	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
510	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
511	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
512	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
513	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
514	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
515	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
516	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
517	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
518	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
519	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
520	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
521	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
522	};
523
524	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
525	* registeres changed. */
526	static const SSMFIELD g_aCpumCtxFieldsMem[] =
527	{
528	SSMFIELD_ENTRY( CPUMCTX, rdi),
529	SSMFIELD_ENTRY( CPUMCTX, rsi),
530	SSMFIELD_ENTRY( CPUMCTX, rbp),
531	SSMFIELD_ENTRY( CPUMCTX, rax),
532	SSMFIELD_ENTRY( CPUMCTX, rbx),
533	SSMFIELD_ENTRY( CPUMCTX, rdx),
534	SSMFIELD_ENTRY( CPUMCTX, rcx),
535	SSMFIELD_ENTRY( CPUMCTX, rsp),
536	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
537	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
538	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
539	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
540	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
541	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
542	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
543	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
544	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
545	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
546	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
547	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
548	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
549	SSMFIELD_ENTRY( CPUMCTX, rflags),
550	SSMFIELD_ENTRY( CPUMCTX, rip),
551	SSMFIELD_ENTRY( CPUMCTX, r8),
552	SSMFIELD_ENTRY( CPUMCTX, r9),
553	SSMFIELD_ENTRY( CPUMCTX, r10),
554	SSMFIELD_ENTRY( CPUMCTX, r11),
555	SSMFIELD_ENTRY( CPUMCTX, r12),
556	SSMFIELD_ENTRY( CPUMCTX, r13),
557	SSMFIELD_ENTRY( CPUMCTX, r14),
558	SSMFIELD_ENTRY( CPUMCTX, r15),
559	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
560	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
561	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
562	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
563	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
564	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
565	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
571	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
572	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
573	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
574	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
575	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
576	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
577	SSMFIELD_ENTRY( CPUMCTX, cr0),
578	SSMFIELD_ENTRY( CPUMCTX, cr2),
579	SSMFIELD_ENTRY( CPUMCTX, cr3),
580	SSMFIELD_ENTRY( CPUMCTX, cr4),
581	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
582	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
583	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
584	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
585	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
586	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
587	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
588	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
589	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
590	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
591	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
592	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
593	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
594	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
595	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
596	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
597	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
598	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
599	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
600	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
601	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
602	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
603	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
604	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
605	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
606	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
607	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
608	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
609	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
610	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
611	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
612	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
613	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
614	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumX87FieldsV16[] =
620	{
621	SSMFIELD_ENTRY( X86FXSTATE, FCW),
622	SSMFIELD_ENTRY( X86FXSTATE, FSW),
623	SSMFIELD_ENTRY( X86FXSTATE, FTW),
624	SSMFIELD_ENTRY( X86FXSTATE, FOP),
625	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
626	SSMFIELD_ENTRY( X86FXSTATE, CS),
627	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
628	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
629	SSMFIELD_ENTRY( X86FXSTATE, DS),
630	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
631	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
632	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
633	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
634	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
635	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
636	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
637	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
638	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
639	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
640	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
641	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
642	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
643	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
644	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
645	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
646	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
647	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
648	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
649	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
650	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
651	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
652	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
653	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
654	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
655	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
656	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
657	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
658	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
659	SSMFIELD_ENTRY_TERM()
660	};
661
662	/** Saved state field descriptors for CPUMCTX_VER1_6. */
663	static const SSMFIELD g_aCpumCtxFieldsV16[] =
664	{
665	SSMFIELD_ENTRY( CPUMCTX, rdi),
666	SSMFIELD_ENTRY( CPUMCTX, rsi),
667	SSMFIELD_ENTRY( CPUMCTX, rbp),
668	SSMFIELD_ENTRY( CPUMCTX, rax),
669	SSMFIELD_ENTRY( CPUMCTX, rbx),
670	SSMFIELD_ENTRY( CPUMCTX, rdx),
671	SSMFIELD_ENTRY( CPUMCTX, rcx),
672	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
673	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
674	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
675	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
676	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
677	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
678	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
679	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
680	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
681	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
682	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
683	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
684	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
685	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
686	SSMFIELD_ENTRY( CPUMCTX, rflags),
687	SSMFIELD_ENTRY( CPUMCTX, rip),
688	SSMFIELD_ENTRY( CPUMCTX, r8),
689	SSMFIELD_ENTRY( CPUMCTX, r9),
690	SSMFIELD_ENTRY( CPUMCTX, r10),
691	SSMFIELD_ENTRY( CPUMCTX, r11),
692	SSMFIELD_ENTRY( CPUMCTX, r12),
693	SSMFIELD_ENTRY( CPUMCTX, r13),
694	SSMFIELD_ENTRY( CPUMCTX, r14),
695	SSMFIELD_ENTRY( CPUMCTX, r15),
696	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
697	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
698	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
699	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
700	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
701	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
702	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
703	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
704	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
705	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
706	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
707	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
708	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
709	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
710	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
711	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
712	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
713	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
714	SSMFIELD_ENTRY( CPUMCTX, cr0),
715	SSMFIELD_ENTRY( CPUMCTX, cr2),
716	SSMFIELD_ENTRY( CPUMCTX, cr3),
717	SSMFIELD_ENTRY( CPUMCTX, cr4),
718	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
719	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
720	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
721	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
722	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
723	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
724	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
725	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
726	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
727	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
728	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
729	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
730	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
731	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
732	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
733	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
734	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
735	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
736	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
737	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
738	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
739	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
740	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
741	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
742	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
743	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
744	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
745	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
746	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
747	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
748	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
749	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
750	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
751	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
752	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
753	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
754	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
755	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
756	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
757	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
758	SSMFIELD_ENTRY_TERM()
759	};
760
761
762	/**
763	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
764	*
765	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
766	* (last instruction pointer, last data pointer, last opcode) except when the ES
767	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
768	* clear these registers there is potential, local FPU leakage from a process
769	* using the FPU to another.
770	*
771	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
772	*
773	* @param pVM The cross context VM structure.
774	*/
775	static void cpumR3CheckLeakyFpu(PVM pVM)
776	{
777	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
778	uint32_t const u32Family = u32CpuVersion >> 8;
779	if ( u32Family >= 6 /* K7 and higher */
780	&& ASMIsAmdCpu())
781	{
782	uint32_t cExt = ASMCpuId_EAX(0x80000000);
783	if (ASMIsValidExtRange(cExt))
784	{
785	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
786	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
787	{
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
790	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
791	}
792	}
793	}
794	}
795
796
797	/**
798	* Frees memory allocated for the SVM hardware virtualization state.
799	*
800	* @param pVM The cross context VM structure.
801	*/
802	static void cpumR3FreeSvmHwVirtState(PVM pVM)
803	{
804	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
805	for (VMCPUID i = 0; i < pVM->cCpus; i++)
806	{
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
809	{
810	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
811	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
812	}
813	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
814
815	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
816	{
817	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
818	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
819	}
820
821	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
822	{
823	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
824	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
825	}
826	}
827	}
828
829
830	/**
831	* Allocates memory for the SVM hardware virtualization state.
832	*
833	* @returns VBox status code.
834	* @param pVM The cross context VM structure.
835	*/
836	static int cpumR3AllocSvmHwVirtState(PVM pVM)
837	{
838	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
839
840	int rc = VINF_SUCCESS;
841	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
842	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846
847	/*
848	* Allocate the nested-guest VMCB.
849	*/
850	SUPPAGE SupNstGstVmcbPage;
851	RT_ZERO(SupNstGstVmcbPage);
852	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
853	Assert(SVM_VMCB_PAGES == 1);
854	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
855	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
856	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
857	if (RT_FAILURE(rc))
858	{
859	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
860	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
861	break;
862	}
863	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
864
865	/*
866	* Allocate the MSRPM (MSR Permission bitmap).
867	*/
868	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
869	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
870	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
871	if (RT_FAILURE(rc))
872	{
873	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
874	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
875	SVM_MSRPM_PAGES));
876	break;
877	}
878
879	/*
880	* Allocate the IOPM (IO Permission bitmap).
881	*/
882	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
883	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
884	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
885	if (RT_FAILURE(rc))
886	{
887	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
888	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
889	SVM_IOPM_PAGES));
890	break;
891	}
892	}
893
894	/* On any failure, cleanup. */
895	if (RT_FAILURE(rc))
896	cpumR3FreeSvmHwVirtState(pVM);
897
898	return rc;
899	}
900
901
902	/**
903	* Frees memory allocated for the VMX hardware virtualization state.
904	*
905	* @param pVM The cross context VM structure.
906	*/
907	static void cpumR3FreeVmxHwVirtState(PVM pVM)
908	{
909	Assert(pVM->cpum.ro.GuestFeatures.fVmx);
910	for (VMCPUID i = 0; i < pVM->cCpus; i++)
911	{
912	PVMCPU pVCpu = &pVM->aCpus[i];
913	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3)
914	{
915	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
916	pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3 = NULL;
917	}
918	}
919	}
920
921
922	/**
923	* Allocates memory for the VMX hardware virtualization state.
924	*
925	* @returns VBox status code.
926	* @param pVM The cross context VM structure.
927	*/
928	static int cpumR3AllocVmxHwVirtState(PVM pVM)
929	{
930	int rc = VINF_SUCCESS;
931	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS\n", pVM->cCpus * VMX_V_VMCS_SIZE));
932	for (VMCPUID i = 0; i < pVM->cCpus; i++)
933	{
934	PVMCPU pVCpu = &pVM->aCpus[i];
935
936	/*
937	* Allocate the nested-guest current VMCS.
938	*/
939	SUPPAGE SupNstGstVmcsPage;
940	RT_ZERO(SupNstGstVmcsPage);
941	SupNstGstVmcsPage.Phys = NIL_RTHCPHYS;
942	Assert(VMX_V_VMCS_PAGES == 1);
943	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
944	rc = SUPR3PageAllocEx(VMX_V_VMCS_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3,
945	&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR0, &SupNstGstVmcsPage);
946	if (RT_FAILURE(rc))
947	{
948	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
949	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
950	break;
951	}
952	}
953
954	/* On any failure, cleanup. */
955	if (RT_FAILURE(rc))
956	cpumR3FreeVmxHwVirtState(pVM);
957
958	return rc;
959	}
960
961
962	/**
963	* Displays the host and guest VMX features.
964	*
965	* @param pVM The cross context VM structure.
966	* @param pHlp The info helper functions.
967	* @param pszArgs "terse", "default" or "verbose".
968	*/
969	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
970	{
971	RT_NOREF(pszArgs);
972	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
973	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
974	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
975	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA)
976	{
977	#define VMXFEATDUMP(a_szDesc, a_Var) \
978	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
979
980	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
981	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
982	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
983	/* Basic. */
984	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
985	/* Pin-based controls. */
986	VMXFEATDUMP("ExtIntExit - External interrupt VM-exit ", fVmxExtIntExit);
987	VMXFEATDUMP("NmiExit - NMI VM-exit ", fVmxNmiExit);
988	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
989	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
990	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
991	/* Processor-based controls. */
992	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
993	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
994	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
995	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
996	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
997	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
998	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
999	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1000	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1001	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1002	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1003	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1004	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1005	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1006	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1007	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1008	VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag ", fVmxMonitorTrapFlag);
1009	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1010	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1011	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1012	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1013	/* Secondary processor-based controls. */
1014	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1015	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1016	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1017	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1018	VMXFEATDUMP("VirtX2Apic - Virtualize-x2APIC accesses ", fVmxVirtX2ApicAccess);
1019	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1020	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1021	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1022	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1023	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1024	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1025	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1026	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1027	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1028	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1029	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1030	VMXFEATDUMP("PML - Supports Page-Modification Log (PML) ", fVmxPml);
1031	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1032	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1033	/* VM-entry controls. */
1034	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1035	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1036	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER on VM-entry ", fVmxEntryLoadEferMsr);
1037	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT on VM-entry ", fVmxEntryLoadPatMsr);
1038	/* VM-exit controls. */
1039	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1040	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1041	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1042	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT on VM-exit ", fVmxExitSavePatMsr);
1043	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT on VM-exit ", fVmxExitLoadPatMsr);
1044	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER on VM-exit ", fVmxExitSaveEferMsr);
1045	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER on VM-exit ", fVmxExitLoadEferMsr);
1046	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1047	VMXFEATDUMP("ExitStoreEferLma - Store EFER.LMA on VM-exit ", fVmxExitStoreEferLma);
1048	VMXFEATDUMP("VmwriteAll - VMWRITE to any VMCS field ", fVmxVmwriteAll);
1049	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1050	/* Miscellaneous data. */
1051	VMXFEATDUMP("ExitStoreEferLma - Inject softint. with 0-len instr. ", fVmxExitStoreEferLma);
1052	VMXFEATDUMP("VmwriteAll - Inject softint. with 0-len instr. ", fVmxVmwriteAll);
1053	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1054	#undef VMXFEATDUMP
1055	}
1056	else
1057	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1058	}
1059
1060
1061	/**
1062	* Initializes VMX host and guest features.
1063	*
1064	* @param pVM The cross context VM structure.
1065	*
1066	* @remarks This must be called only after HM has fully initialized since it calls
1067	* into HM to retrieve VMX and related MSRs.
1068	*/
1069	static void cpumR3InitVmxCpuFeatures(PVM pVM)
1070	{
1071	/*
1072	* Init. host features.
1073	*/
1074	PCPUMFEATURES pHostFeat = &pVM->cpum.s.HostFeatures;
1075	VMXMSRS VmxMsrs;
1076	int rc = HMVmxGetHostMsrs(pVM, &VmxMsrs);
1077	if (RT_SUCCESS(rc))
1078	{
1079	/* Basic information. */
1080	pHostFeat->fVmxInsOutInfo = RT_BF_GET(VmxMsrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1081
1082	/* Pin-based VM-execution controls. */
1083	uint32_t const fPinCtls = VmxMsrs.PinCtls.n.allowed1;
1084	pHostFeat->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1085	pHostFeat->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1086	pHostFeat->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1087	pHostFeat->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1088	pHostFeat->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1089
1090	/* Processor-based VM-execution controls. */
1091	uint32_t const fProcCtls = VmxMsrs.ProcCtls.n.allowed1;
1092	pHostFeat->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1093	pHostFeat->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1094	pHostFeat->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1095	pHostFeat->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1096	pHostFeat->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1097	pHostFeat->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1098	pHostFeat->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1099	pHostFeat->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1100	pHostFeat->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1101	pHostFeat->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1102	pHostFeat->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1103	pHostFeat->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1104	pHostFeat->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1105	pHostFeat->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1106	pHostFeat->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1107	pHostFeat->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1108	pHostFeat->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1109	pHostFeat->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1110	pHostFeat->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1111	pHostFeat->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1112	pHostFeat->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1113
1114	/* Secondary processor-based VM-execution controls. */
1115	if (pHostFeat->fVmxSecondaryExecCtls)
1116	{
1117	uint32_t const fProcCtls2 = VmxMsrs.ProcCtls2.n.allowed1;
1118	pHostFeat->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1119	pHostFeat->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1120	pHostFeat->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1121	pHostFeat->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1122	pHostFeat->fVmxVirtX2ApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS);
1123	pHostFeat->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1124	pHostFeat->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1125	pHostFeat->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1126	pHostFeat->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1127	pHostFeat->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1128	pHostFeat->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1129	pHostFeat->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1130	pHostFeat->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1131	pHostFeat->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1132	pHostFeat->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1133	pHostFeat->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1134	pHostFeat->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1135	pHostFeat->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1136	pHostFeat->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1137	pHostFeat->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1138	}
1139
1140	/* VM-entry controls. */
1141	uint32_t const fEntryCtls = VmxMsrs.EntryCtls.n.allowed1;
1142	pHostFeat->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1143	pHostFeat->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1144	pHostFeat->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1145	pHostFeat->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1146
1147	/* VM-exit controls. */
1148	uint32_t const fExitCtls = VmxMsrs.ExitCtls.n.allowed1;
1149	pHostFeat->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1150	pHostFeat->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1151	pHostFeat->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1152	pHostFeat->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1153	pHostFeat->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1154	pHostFeat->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1155	pHostFeat->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1156	pHostFeat->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER);
1157
1158	/* Miscellaneous data. */
1159	uint32_t const fMiscData = VmxMsrs.u64Misc;
1160	pHostFeat->fVmxExitStoreEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_STORE_EFER_LMA);
1161	pHostFeat->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1162	pHostFeat->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1163	}
1164
1165	/*
1166	* Initialize the set of VMX features we emulate.
1167	* Note! Some bits might be reported as 1 always if they fall under the default1 class bits
1168	* (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1169	*/
1170	CPUMFEATURES EmuFeat;
1171	RT_ZERO(EmuFeat);
1172	EmuFeat.fVmx = 1;
1173	EmuFeat.fVmxInsOutInfo = 0;
1174	EmuFeat.fVmxExtIntExit = 1;
1175	EmuFeat.fVmxNmiExit = 1;
1176	EmuFeat.fVmxVirtNmi = 0;
1177	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1178	EmuFeat.fVmxPostedInt = 0;
1179	EmuFeat.fVmxIntWindowExit = 1;
1180	EmuFeat.fVmxTscOffsetting = 1;
1181	EmuFeat.fVmxHltExit = 1;
1182	EmuFeat.fVmxInvlpgExit = 1;
1183	EmuFeat.fVmxMwaitExit = 1;
1184	EmuFeat.fVmxRdpmcExit = 1;
1185	EmuFeat.fVmxRdtscExit = 1;
1186	EmuFeat.fVmxCr3LoadExit = 1;
1187	EmuFeat.fVmxCr3StoreExit = 1;
1188	EmuFeat.fVmxCr8LoadExit = 1;
1189	EmuFeat.fVmxCr8StoreExit = 1;
1190	EmuFeat.fVmxUseTprShadow = 0;
1191	EmuFeat.fVmxNmiWindowExit = 0;
1192	EmuFeat.fVmxMovDRxExit = 1;
1193	EmuFeat.fVmxUncondIoExit = 1;
1194	EmuFeat.fVmxUseIoBitmaps = 1;
1195	EmuFeat.fVmxMonitorTrapFlag = 0;
1196	EmuFeat.fVmxUseMsrBitmaps = 0;
1197	EmuFeat.fVmxMonitorExit = 1;
1198	EmuFeat.fVmxPauseExit = 1;
1199	EmuFeat.fVmxSecondaryExecCtls = 1;
1200	EmuFeat.fVmxVirtApicAccess = 0;
1201	EmuFeat.fVmxEpt = 0;
1202	EmuFeat.fVmxDescTableExit = 1;
1203	EmuFeat.fVmxRdtscp = 1;
1204	EmuFeat.fVmxVirtX2ApicAccess = 0;
1205	EmuFeat.fVmxVpid = 0;
1206	EmuFeat.fVmxWbinvdExit = 1;
1207	EmuFeat.fVmxUnrestrictedGuest = 0;
1208	EmuFeat.fVmxApicRegVirt = 0;
1209	EmuFeat.fVmxVirtIntDelivery = 0;
1210	EmuFeat.fVmxPauseLoopExit = 0;
1211	EmuFeat.fVmxRdrandExit = 0;
1212	EmuFeat.fVmxInvpcid = 1;
1213	EmuFeat.fVmxVmFunc = 0;
1214	EmuFeat.fVmxVmcsShadowing = 0;
1215	EmuFeat.fVmxRdseedExit = 0;
1216	EmuFeat.fVmxPml = 0;
1217	EmuFeat.fVmxEptXcptVe = 0;
1218	EmuFeat.fVmxXsavesXrstors = 0;
1219	EmuFeat.fVmxUseTscScaling = 0;
1220	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1221	EmuFeat.fVmxIa32eModeGuest = 1;
1222	EmuFeat.fVmxEntryLoadEferMsr = 1;
1223	EmuFeat.fVmxEntryLoadPatMsr = 0;
1224	EmuFeat.fVmxExitSaveDebugCtls = 1;
1225	EmuFeat.fVmxHostAddrSpaceSize = 1;
1226	EmuFeat.fVmxExitAckExtInt = 0;
1227	EmuFeat.fVmxExitSavePatMsr = 0;
1228	EmuFeat.fVmxExitLoadPatMsr = 0;
1229	EmuFeat.fVmxExitSaveEferMsr = 1;
1230	EmuFeat.fVmxExitLoadEferMsr = 1;
1231	EmuFeat.fVmxSavePreemptTimer = 0;
1232	EmuFeat.fVmxExitStoreEferLma = 1;
1233	EmuFeat.fVmxVmwriteAll = 0;
1234	EmuFeat.fVmxEntryInjectSoftInt = 0;
1235
1236	/*
1237	* Explode guest features.
1238	*
1239	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1240	* by the hardware, hence we merge our emulated features with the host features below.
1241	*/
1242	bool const fHostSupportsVmx = pHostFeat->fVmx;
1243	AssertLogRelReturnVoid(!fHostSupportsVmx \|\| HMIsVmxSupported(pVM));
1244	PCCPUMFEATURES pBaseFeat = fHostSupportsVmx ? pHostFeat : &EmuFeat;
1245	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1246	pGuestFeat->fVmx = (pBaseFeat->fVmx & EmuFeat.fVmx );
1247	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1248	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1249	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1250	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1251	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1252	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1253	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1254	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1255	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1256	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1257	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1258	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1259	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1260	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1261	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1262	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1263	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1264	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1265	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1266	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1267	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1268	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1269	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1270	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1271	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1272	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1273	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1274	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1275	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1276	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1277	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1278	pGuestFeat->fVmxVirtX2ApicAccess = (pBaseFeat->fVmxVirtX2ApicAccess & EmuFeat.fVmxVirtX2ApicAccess );
1279	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1280	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1281	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1282	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1283	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1284	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1285	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1286	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1287	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1288	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1289	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1290	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1291	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1292	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1293	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1294	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1295	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1296	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1297	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1298	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1299	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1300	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1301	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1302	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1303	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1304	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1305	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1306	pGuestFeat->fVmxExitStoreEferLma = (pBaseFeat->fVmxExitStoreEferLma & EmuFeat.fVmxExitStoreEferLma );
1307	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1308	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1309	}
1310
1311
1312	/**
1313	* Initializes the CPUM.
1314	*
1315	* @returns VBox status code.
1316	* @param pVM The cross context VM structure.
1317	*/
1318	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1319	{
1320	LogFlow(("CPUMR3Init\n"));
1321
1322	/*
1323	* Assert alignment, sizes and tables.
1324	*/
1325	AssertCompileMemberAlignment(VM, cpum.s, 32);
1326	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1327	AssertCompileSizeAlignment(CPUMCTX, 64);
1328	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1329	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1330	AssertCompileMemberAlignment(VM, cpum, 64);
1331	AssertCompileMemberAlignment(VM, aCpus, 64);
1332	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1333	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
1334	#ifdef VBOX_STRICT
1335	int rc2 = cpumR3MsrStrictInitChecks();
1336	AssertRCReturn(rc2, rc2);
1337	#endif
1338
1339	/*
1340	* Initialize offsets.
1341	*/
1342
1343	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
1344	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
1345	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
1346
1347
1348	/* Calculate the offset from CPUMCPU to CPUM. */
1349	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1350	{
1351	PVMCPU pVCpu = &pVM->aCpus[i];
1352
1353	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
1354	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
1355	}
1356
1357	/*
1358	* Gather info about the host CPU.
1359	*/
1360	if (!ASMHasCpuId())
1361	{
1362	Log(("The CPU doesn't support CPUID!\n"));
1363	return VERR_UNSUPPORTED_CPU;
1364	}
1365
1366	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1367
1368	PCPUMCPUIDLEAF paLeaves;
1369	uint32_t cLeaves;
1370	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1371	AssertLogRelRCReturn(rc, rc);
1372
1373	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
1374	RTMemFree(paLeaves);
1375	AssertLogRelRCReturn(rc, rc);
1376	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1377
1378	/*
1379	* Check that the CPU supports the minimum features we require.
1380	*/
1381	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
1382	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
1383	if (!pVM->cpum.s.HostFeatures.fMmx)
1384	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
1385	if (!pVM->cpum.s.HostFeatures.fTsc)
1386	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
1387
1388	/*
1389	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
1390	*/
1391	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
1392	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
1393
1394	/*
1395	* Figure out which XSAVE/XRSTOR features are available on the host.
1396	*/
1397	uint64_t fXcr0Host = 0;
1398	uint64_t fXStateHostMask = 0;
1399	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
1400	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
1401	{
1402	fXStateHostMask = fXcr0Host = ASMGetXcr0();
1403	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
1404	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
1405	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
1406	}
1407	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
1408	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
1409	fXStateHostMask = 0;
1410	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1411	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1412
1413	/*
1414	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
1415	*/
1416	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1417	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1418	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
1419
1420	uint8_t *pbXStates;
1421	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
1422	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
1423	AssertLogRelRCReturn(rc, rc);
1424
1425	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1426	{
1427	PVMCPU pVCpu = &pVM->aCpus[i];
1428
1429	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1430	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1431	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1432	pbXStates += cbMaxXState;
1433
1434	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1435	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1436	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1437	pbXStates += cbMaxXState;
1438
1439	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1440	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1441	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1442	pbXStates += cbMaxXState;
1443
1444	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
1445	}
1446
1447	/*
1448	* Register saved state data item.
1449	*/
1450	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
1451	NULL, cpumR3LiveExec, NULL,
1452	NULL, cpumR3SaveExec, NULL,
1453	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1454	if (RT_FAILURE(rc))
1455	return rc;
1456
1457	/*
1458	* Register info handlers and registers with the debugger facility.
1459	*/
1460	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1461	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1462	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1463	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1464	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1465	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1466	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1467	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1468	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1469	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1470	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1471	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1472	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1473	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
1474	&cpumR3InfoVmxFeatures);
1475
1476	rc = cpumR3DbgInit(pVM);
1477	if (RT_FAILURE(rc))
1478	return rc;
1479
1480	/*
1481	* Check if we need to workaround partial/leaky FPU handling.
1482	*/
1483	cpumR3CheckLeakyFpu(pVM);
1484
1485	/*
1486	* Initialize the Guest CPUID and MSR states.
1487	*/
1488	rc = cpumR3InitCpuIdAndMsrs(pVM);
1489	if (RT_FAILURE(rc))
1490	return rc;
1491
1492	/*
1493	* Allocate memory required by the guest hardware virtualization state.
1494	*/
1495	if (pVM->cpum.ro.GuestFeatures.fVmx)
1496	rc = cpumR3AllocVmxHwVirtState(pVM);
1497	else if (pVM->cpum.ro.GuestFeatures.fSvm)
1498	rc = cpumR3AllocSvmHwVirtState(pVM);
1499	if (RT_FAILURE(rc))
1500	return rc;
1501
1502	/*
1503	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1504	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1505	* of processors from (cpuid(4).eax >> 26) + 1.
1506	*
1507	* Note: this code is obsolete, but let's keep it here for reference.
1508	* Purpose is valid when we artificially cap the max std id to less than 4.
1509	*
1510	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
1511	* after VMINITCOMPLETED_HM.
1512	*/
1513	if (VM_IS_RAW_MODE_ENABLED(pVM))
1514	{
1515	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1516	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1517	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1518	}
1519
1520	CPUMR3Reset(pVM);
1521	return VINF_SUCCESS;
1522	}
1523
1524
1525	/**
1526	* Applies relocations to data and code managed by this
1527	* component. This function will be called at init and
1528	* whenever the VMM need to relocate it self inside the GC.
1529	*
1530	* The CPUM will update the addresses used by the switcher.
1531	*
1532	* @param pVM The cross context VM structure.
1533	*/
1534	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1535	{
1536	LogFlow(("CPUMR3Relocate\n"));
1537
1538	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1539	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1540
1541	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1542	{
1543	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1544	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1545	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1546	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1547
1548	/* Recheck the guest DRx values in raw-mode. */
1549	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1550	}
1551	}
1552
1553
1554	/**
1555	* Terminates the CPUM.
1556	*
1557	* Termination means cleaning up and freeing all resources,
1558	* the VM it self is at this point powered off or suspended.
1559	*
1560	* @returns VBox status code.
1561	* @param pVM The cross context VM structure.
1562	*/
1563	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1564	{
1565	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1566	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1567	{
1568	PVMCPU pVCpu = &pVM->aCpus[i];
1569	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1570
1571	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1572	pVCpu->cpum.s.uMagic = 0;
1573	pCtx->dr[5] = 0;
1574	}
1575	#endif
1576
1577	if (pVM->cpum.ro.GuestFeatures.fSvm)
1578	cpumR3FreeVmxHwVirtState(pVM);
1579	else if (pVM->cpum.ro.GuestFeatures.fSvm)
1580	cpumR3FreeSvmHwVirtState(pVM);
1581	return VINF_SUCCESS;
1582	}
1583
1584
1585	/**
1586	* Resets a virtual CPU.
1587	*
1588	* Used by CPUMR3Reset and CPU hot plugging.
1589	*
1590	* @param pVM The cross context VM structure.
1591	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1592	* being reset. This may differ from the current EMT.
1593	*/
1594	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1595	{
1596	/** @todo anything different for VCPU > 0? */
1597	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1598
1599	/*
1600	* Initialize everything to ZERO first.
1601	*/
1602	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1603
1604	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1605	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1606	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
1607
1608	pVCpu->cpum.s.fUseFlags = fUseFlags;
1609
1610	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1611	pCtx->eip = 0x0000fff0;
1612	pCtx->edx = 0x00000600; /* P6 processor */
1613	pCtx->eflags.Bits.u1Reserved0 = 1;
1614
1615	pCtx->cs.Sel = 0xf000;
1616	pCtx->cs.ValidSel = 0xf000;
1617	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1618	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1619	pCtx->cs.u32Limit = 0x0000ffff;
1620	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1621	pCtx->cs.Attr.n.u1Present = 1;
1622	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1623
1624	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1625	pCtx->ds.u32Limit = 0x0000ffff;
1626	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1627	pCtx->ds.Attr.n.u1Present = 1;
1628	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1629
1630	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1631	pCtx->es.u32Limit = 0x0000ffff;
1632	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1633	pCtx->es.Attr.n.u1Present = 1;
1634	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1635
1636	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1637	pCtx->fs.u32Limit = 0x0000ffff;
1638	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1639	pCtx->fs.Attr.n.u1Present = 1;
1640	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1641
1642	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1643	pCtx->gs.u32Limit = 0x0000ffff;
1644	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1645	pCtx->gs.Attr.n.u1Present = 1;
1646	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1647
1648	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1649	pCtx->ss.u32Limit = 0x0000ffff;
1650	pCtx->ss.Attr.n.u1Present = 1;
1651	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1652	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1653
1654	pCtx->idtr.cbIdt = 0xffff;
1655	pCtx->gdtr.cbGdt = 0xffff;
1656
1657	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1658	pCtx->ldtr.u32Limit = 0xffff;
1659	pCtx->ldtr.Attr.n.u1Present = 1;
1660	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1661
1662	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1663	pCtx->tr.u32Limit = 0xffff;
1664	pCtx->tr.Attr.n.u1Present = 1;
1665	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1666
1667	pCtx->dr[6] = X86_DR6_INIT_VAL;
1668	pCtx->dr[7] = X86_DR7_INIT_VAL;
1669
1670	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1671	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1672	pFpuCtx->FCW = 0x37f;
1673
1674	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1675	IA-32 Processor States Following Power-up, Reset, or INIT */
1676	pFpuCtx->MXCSR = 0x1F80;
1677	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1678
1679	pCtx->aXcr[0] = XSAVE_C_X87;
1680	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
1681	{
1682	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1683	as we don't know what happened before. (Bother optimize later?) */
1684	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1685	}
1686
1687	/*
1688	* MSRs.
1689	*/
1690	/* Init PAT MSR */
1691	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
1692
1693	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1694	* The Intel docs don't mention it. */
1695	Assert(!pCtx->msrEFER);
1696
1697	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1698	is supposed to be here, just trying provide useful/sensible values. */
1699	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1700	if (pRange)
1701	{
1702	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1703	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1704	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1705	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1706	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1707	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1708	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1709	}
1710
1711	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1712
1713	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1714	* called from each EMT while we're getting called by CPUMR3Reset()
1715	* iteratively on the same thread. Fix later. */
1716	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1717	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1718	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1719	#endif
1720
1721
1722	/* C-state control. Guesses. */
1723	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1724	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
1725	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
1726	* functionality. The default value must be different due to incompatible write mask.
1727	*/
1728	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
1729	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
1730	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
1731	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
1732
1733	/*
1734	* Hardware virtualization state.
1735	*/
1736	pCtx->hwvirt.fGif = true;
1737
1738	/* SVM. */
1739	if (pCtx->hwvirt.svm.CTX_SUFF(pVmcb))
1740	{
1741	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1742	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1743	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1744	}
1745	}
1746
1747
1748	/**
1749	* Resets the CPU.
1750	*
1751	* @returns VINF_SUCCESS.
1752	* @param pVM The cross context VM structure.
1753	*/
1754	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1755	{
1756	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1757	{
1758	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1759
1760	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1761	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1762
1763	/* Magic marker for searching in crash dumps. */
1764	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1765	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1766	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1767	#endif
1768	}
1769	}
1770
1771
1772
1773
1774	/**
1775	* Pass 0 live exec callback.
1776	*
1777	* @returns VINF_SSM_DONT_CALL_AGAIN.
1778	* @param pVM The cross context VM structure.
1779	* @param pSSM The saved state handle.
1780	* @param uPass The pass (0).
1781	*/
1782	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1783	{
1784	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1785	cpumR3SaveCpuId(pVM, pSSM);
1786	return VINF_SSM_DONT_CALL_AGAIN;
1787	}
1788
1789
1790	/**
1791	* Execute state save operation.
1792	*
1793	* @returns VBox status code.
1794	* @param pVM The cross context VM structure.
1795	* @param pSSM SSM operation handle.
1796	*/
1797	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1798	{
1799	/*
1800	* Save.
1801	*/
1802	SSMR3PutU32(pSSM, pVM->cCpus);
1803	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1804	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1805	{
1806	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1807
1808	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1809
1810	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1811	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1812	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1813	if (pGstCtx->fXStateMask != 0)
1814	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1815	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1816	{
1817	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1818	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1819	}
1820	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1821	{
1822	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1823	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1824	}
1825	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1826	{
1827	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1828	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1829	}
1830	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1831	{
1832	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1833	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1834	}
1835	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1836	{
1837	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1838	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1839	}
1840	if (pVM->cpum.ro.GuestFeatures.fSvm)
1841	{
1842	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1843	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
1844	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
1845	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
1846	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
1847	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
1848	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
1849	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
1850	g_aSvmHwvirtHostState, NULL /* pvUser */);
1851	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
1852	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
1853	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
1854	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
1855	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
1856	}
1857	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
1858	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
1859	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
1860	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
1861	}
1862
1863	cpumR3SaveCpuId(pVM, pSSM);
1864	return VINF_SUCCESS;
1865	}
1866
1867
1868	/**
1869	* @callback_method_impl{FNSSMINTLOADPREP}
1870	*/
1871	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
1872	{
1873	NOREF(pSSM);
1874	pVM->cpum.s.fPendingRestore = true;
1875	return VINF_SUCCESS;
1876	}
1877
1878
1879	/**
1880	* @callback_method_impl{FNSSMINTLOADEXEC}
1881	*/
1882	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
1883	{
1884	int rc; /* Only for AssertRCReturn use. */
1885
1886	/*
1887	* Validate version.
1888	*/
1889	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
1890	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
1891	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
1892	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
1893	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
1894	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
1895	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
1896	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
1897	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
1898	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
1899	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
1900	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
1901	{
1902	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
1903	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1904	}
1905
1906	if (uPass == SSM_PASS_FINAL)
1907	{
1908	/*
1909	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
1910	* really old SSM file versions.)
1911	*/
1912	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1913	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
1914	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
1915	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
1916
1917	/*
1918	* Figure x86 and ctx field definitions to use for older states.
1919	*/
1920	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
1921	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
1922	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
1923	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
1924	{
1925	paCpumCtx1Fields = g_aCpumX87FieldsV16;
1926	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
1927	}
1928	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
1929	{
1930	paCpumCtx1Fields = g_aCpumX87FieldsMem;
1931	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
1932	}
1933
1934	/*
1935	* The hyper state used to preceed the CPU count. Starting with
1936	* XSAVE it was moved down till after we've got the count.
1937	*/
1938	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
1939	{
1940	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1941	{
1942	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1943	X86FXSTATE Ign;
1944	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
1945	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1946	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1947	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
1948	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
1949	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1950	pVCpu->cpum.s.Hyper.rsp = uRSP;
1951	}
1952	}
1953
1954	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
1955	{
1956	uint32_t cCpus;
1957	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
1958	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
1959	VERR_SSM_UNEXPECTED_DATA);
1960	}
1961	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
1962	\|\| pVM->cCpus == 1,
1963	("cCpus=%u\n", pVM->cCpus),
1964	VERR_SSM_UNEXPECTED_DATA);
1965
1966	uint32_t cbMsrs = 0;
1967	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
1968	{
1969	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
1970	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
1971	VERR_SSM_UNEXPECTED_DATA);
1972	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
1973	VERR_SSM_UNEXPECTED_DATA);
1974	}
1975
1976	/*
1977	* Do the per-CPU restoring.
1978	*/
1979	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1980	{
1981	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1982	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1983
1984	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
1985	{
1986	/*
1987	* The XSAVE saved state layout moved the hyper state down here.
1988	*/
1989	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
1990	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
1991	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1992	pVCpu->cpum.s.Hyper.cr3 = uCR3;
1993	pVCpu->cpum.s.Hyper.rsp = uRSP;
1994	AssertRCReturn(rc, rc);
1995
1996	/*
1997	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
1998	*/
1999	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2000	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2001	AssertRCReturn(rc, rc);
2002
2003	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2004	if (pGstCtx->fXStateMask != 0)
2005	{
2006	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2007	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2008	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2009	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2010	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2011	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2012	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2013	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2014	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2015	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2016	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2017	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2018	}
2019
2020	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2021	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2022	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2023	{
2024	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2025	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2026	VERR_CPUM_INVALID_XCR0);
2027	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2028	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2029	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2030	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2031	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2032	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2033	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2034	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2035	}
2036
2037	/* Check that the XCR1 is zero, as we don't implement it yet. */
2038	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2039
2040	/*
2041	* Restore the individual extended state components we support.
2042	*/
2043	if (pGstCtx->fXStateMask != 0)
2044	{
2045	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2046	0, g_aCpumXSaveHdrFields, NULL);
2047	AssertRCReturn(rc, rc);
2048	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2049	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2050	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2051	VERR_CPUM_INVALID_XSAVE_HDR);
2052	}
2053	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2054	{
2055	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2056	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2057	}
2058	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2059	{
2060	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2061	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2062	}
2063	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2064	{
2065	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2066	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2067	}
2068	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2069	{
2070	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2071	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2072	}
2073	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2074	{
2075	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2076	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2077	}
2078	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2079	{
2080	if (pVM->cpum.ro.GuestFeatures.fSvm)
2081	{
2082	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2083	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2084	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2085	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2086	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2087	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2088	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2089	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2090	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2091	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2092	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2093	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2094	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2095	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2096	}
2097	}
2098	}
2099	else
2100	{
2101	/*
2102	* Pre XSAVE saved state.
2103	*/
2104	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2105	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2106	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2107	}
2108
2109	/*
2110	* Restore a couple of flags and the MSRs.
2111	*/
2112	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2113	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2114
2115	rc = VINF_SUCCESS;
2116	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2117	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2118	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2119	{
2120	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2121	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2122	}
2123	AssertRCReturn(rc, rc);
2124
2125	/* REM and other may have cleared must-be-one fields in DR6 and
2126	DR7, fix these. */
2127	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2128	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2129	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2130	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2131	}
2132
2133	/* Older states does not have the internal selector register flags
2134	and valid selector value. Supply those. */
2135	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2136	{
2137	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2138	{
2139	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2140	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2141	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2142	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2143	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2144	if (fValid)
2145	{
2146	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2147	{
2148	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2149	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2150	}
2151
2152	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2153	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2154	}
2155	else
2156	{
2157	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2158	{
2159	paSelReg[iSelReg].fFlags = 0;
2160	paSelReg[iSelReg].ValidSel = 0;
2161	}
2162
2163	/* This might not be 104% correct, but I think it's close
2164	enough for all practical purposes... (REM always loaded
2165	LDTR registers.) */
2166	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2167	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2168	}
2169	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2170	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2171	}
2172	}
2173
2174	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2175	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2176	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2177	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2178	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2179
2180	/*
2181	* A quick sanity check.
2182	*/
2183	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2184	{
2185	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2186	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2187	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2188	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2189	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2190	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2191	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2192	}
2193	}
2194
2195	pVM->cpum.s.fPendingRestore = false;
2196
2197	/*
2198	* Guest CPUIDs.
2199	*/
2200	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2201	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2202	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2203	}
2204
2205
2206	/**
2207	* @callback_method_impl{FNSSMINTLOADDONE}
2208	*/
2209	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2210	{
2211	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2212	return VINF_SUCCESS;
2213
2214	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2215	if (pVM->cpum.s.fPendingRestore)
2216	{
2217	LogRel(("CPUM: Missing state!\n"));
2218	return VERR_INTERNAL_ERROR_2;
2219	}
2220
2221	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2222	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2223	{
2224	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2225
2226	/* Notify PGM of the NXE states in case they've changed. */
2227	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2228
2229	/* During init. this is done in CPUMR3InitCompleted(). */
2230	if (fSupportsLongMode)
2231	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2232	}
2233	return VINF_SUCCESS;
2234	}
2235
2236
2237	/**
2238	* Checks if the CPUM state restore is still pending.
2239	*
2240	* @returns true / false.
2241	* @param pVM The cross context VM structure.
2242	*/
2243	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2244	{
2245	return pVM->cpum.s.fPendingRestore;
2246	}
2247
2248
2249	/**
2250	* Formats the EFLAGS value into mnemonics.
2251	*
2252	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2253	* @param efl The EFLAGS value.
2254	*/
2255	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2256	{
2257	/*
2258	* Format the flags.
2259	*/
2260	static const struct
2261	{
2262	const char pszSet; const char pszClear; uint32_t fFlag;
2263	} s_aFlags[] =
2264	{
2265	{ "vip",NULL, X86_EFL_VIP },
2266	{ "vif",NULL, X86_EFL_VIF },
2267	{ "ac", NULL, X86_EFL_AC },
2268	{ "vm", NULL, X86_EFL_VM },
2269	{ "rf", NULL, X86_EFL_RF },
2270	{ "nt", NULL, X86_EFL_NT },
2271	{ "ov", "nv", X86_EFL_OF },
2272	{ "dn", "up", X86_EFL_DF },
2273	{ "ei", "di", X86_EFL_IF },
2274	{ "tf", NULL, X86_EFL_TF },
2275	{ "nt", "pl", X86_EFL_SF },
2276	{ "nz", "zr", X86_EFL_ZF },
2277	{ "ac", "na", X86_EFL_AF },
2278	{ "po", "pe", X86_EFL_PF },
2279	{ "cy", "nc", X86_EFL_CF },
2280	};
2281	char *psz = pszEFlags;
2282	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2283	{
2284	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2285	if (pszAdd)
2286	{
2287	strcpy(psz, pszAdd);
2288	psz += strlen(pszAdd);
2289	*psz++ = ' ';
2290	}
2291	}
2292	psz[-1] = '\0';
2293	}
2294
2295
2296	/**
2297	* Formats a full register dump.
2298	*
2299	* @param pVM The cross context VM structure.
2300	* @param pCtx The context to format.
2301	* @param pCtxCore The context core to format.
2302	* @param pHlp Output functions.
2303	* @param enmType The dump type.
2304	* @param pszPrefix Register name prefix.
2305	*/
2306	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2307	const char *pszPrefix)
2308	{
2309	NOREF(pVM);
2310
2311	/*
2312	* Format the EFLAGS.
2313	*/
2314	uint32_t efl = pCtxCore->eflags.u32;
2315	char szEFlags[80];
2316	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2317
2318	/*
2319	* Format the registers.
2320	*/
2321	switch (enmType)
2322	{
2323	case CPUMDUMPTYPE_TERSE:
2324	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2325	pHlp->pfnPrintf(pHlp,
2326	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2327	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2328	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2329	"%sr14=%016RX64 %sr15=%016RX64\n"
2330	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2331	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2332	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2333	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2334	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2335	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2336	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2337	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2338	else
2339	pHlp->pfnPrintf(pHlp,
2340	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2341	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2342	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2343	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2344	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2345	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2346	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2347	break;
2348
2349	case CPUMDUMPTYPE_DEFAULT:
2350	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2351	pHlp->pfnPrintf(pHlp,
2352	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2353	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2354	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2355	"%sr14=%016RX64 %sr15=%016RX64\n"
2356	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2357	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2358	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2359	,
2360	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2361	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2362	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2363	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2364	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2365	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2366	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2367	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2368	else
2369	pHlp->pfnPrintf(pHlp,
2370	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2371	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2372	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2373	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2374	,
2375	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2376	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2377	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2378	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2379	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2380	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2381	break;
2382
2383	case CPUMDUMPTYPE_VERBOSE:
2384	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2385	pHlp->pfnPrintf(pHlp,
2386	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2387	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2388	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2389	"%sr14=%016RX64 %sr15=%016RX64\n"
2390	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2391	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2392	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2393	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2394	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2395	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2396	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2397	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2398	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2399	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2400	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2401	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2402	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2403	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2404	,
2405	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2406	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2407	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2408	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2409	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2410	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2411	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2412	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2413	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2414	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2415	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2416	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2417	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2418	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2419	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2420	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2421	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2422	else
2423	pHlp->pfnPrintf(pHlp,
2424	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2425	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2426	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2427	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2428	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2429	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2430	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2431	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2432	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2433	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2434	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2435	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2436	,
2437	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2438	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2439	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2440	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2441	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2442	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2443	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2444	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2445	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2446	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2447	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2448	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2449
2450	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
2451	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
2452	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
2453	if (pCtx->CTX_SUFF(pXState))
2454	{
2455	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2456	pHlp->pfnPrintf(pHlp,
2457	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2458	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2459	,
2460	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
2461	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
2462	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
2463	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
2464	);
2465	/*
2466	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
2467	* not (FP)R0-7 as Intel SDM suggests.
2468	*/
2469	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
2470	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
2471	{
2472	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
2473	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
2474	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
2475	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
2476	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
2477	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
2478	iExponent -= 16383; /* subtract bias */
2479	/** @todo This isn't entirenly correct and needs more work! */
2480	pHlp->pfnPrintf(pHlp,
2481	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
2482	pszPrefix, iST, pszPrefix, iFPR,
2483	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
2484	uTag, chSign, iInteger, u64Fraction, iExponent);
2485	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
2486	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2487	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
2488	else
2489	pHlp->pfnPrintf(pHlp, "\n");
2490	}
2491
2492	/* XMM/YMM/ZMM registers. */
2493	if (pCtx->fXStateMask & XSAVE_C_YMM)
2494	{
2495	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2496	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2497	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2498	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2499	pszPrefix, i, i < 10 ? " " : "",
2500	pYmmHiCtx->aYmmHi[i].au32[3],
2501	pYmmHiCtx->aYmmHi[i].au32[2],
2502	pYmmHiCtx->aYmmHi[i].au32[1],
2503	pYmmHiCtx->aYmmHi[i].au32[0],
2504	pFpuCtx->aXMM[i].au32[3],
2505	pFpuCtx->aXMM[i].au32[2],
2506	pFpuCtx->aXMM[i].au32[1],
2507	pFpuCtx->aXMM[i].au32[0]);
2508	else
2509	{
2510	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2511	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2512	pHlp->pfnPrintf(pHlp,
2513	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2514	pszPrefix, i, i < 10 ? " " : "",
2515	pZmmHi256->aHi256Regs[i].au32[7],
2516	pZmmHi256->aHi256Regs[i].au32[6],
2517	pZmmHi256->aHi256Regs[i].au32[5],
2518	pZmmHi256->aHi256Regs[i].au32[4],
2519	pZmmHi256->aHi256Regs[i].au32[3],
2520	pZmmHi256->aHi256Regs[i].au32[2],
2521	pZmmHi256->aHi256Regs[i].au32[1],
2522	pZmmHi256->aHi256Regs[i].au32[0],
2523	pYmmHiCtx->aYmmHi[i].au32[3],
2524	pYmmHiCtx->aYmmHi[i].au32[2],
2525	pYmmHiCtx->aYmmHi[i].au32[1],
2526	pYmmHiCtx->aYmmHi[i].au32[0],
2527	pFpuCtx->aXMM[i].au32[3],
2528	pFpuCtx->aXMM[i].au32[2],
2529	pFpuCtx->aXMM[i].au32[1],
2530	pFpuCtx->aXMM[i].au32[0]);
2531
2532	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2533	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2534	pHlp->pfnPrintf(pHlp,
2535	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2536	pszPrefix, i + 16,
2537	pZmm16Hi->aRegs[i].au32[15],
2538	pZmm16Hi->aRegs[i].au32[14],
2539	pZmm16Hi->aRegs[i].au32[13],
2540	pZmm16Hi->aRegs[i].au32[12],
2541	pZmm16Hi->aRegs[i].au32[11],
2542	pZmm16Hi->aRegs[i].au32[10],
2543	pZmm16Hi->aRegs[i].au32[9],
2544	pZmm16Hi->aRegs[i].au32[8],
2545	pZmm16Hi->aRegs[i].au32[7],
2546	pZmm16Hi->aRegs[i].au32[6],
2547	pZmm16Hi->aRegs[i].au32[5],
2548	pZmm16Hi->aRegs[i].au32[4],
2549	pZmm16Hi->aRegs[i].au32[3],
2550	pZmm16Hi->aRegs[i].au32[2],
2551	pZmm16Hi->aRegs[i].au32[1],
2552	pZmm16Hi->aRegs[i].au32[0]);
2553	}
2554	}
2555	else
2556	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2557	pHlp->pfnPrintf(pHlp,
2558	i & 1
2559	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2560	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2561	pszPrefix, i, i < 10 ? " " : "",
2562	pFpuCtx->aXMM[i].au32[3],
2563	pFpuCtx->aXMM[i].au32[2],
2564	pFpuCtx->aXMM[i].au32[1],
2565	pFpuCtx->aXMM[i].au32[0]);
2566
2567	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2568	{
2569	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2570	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2571	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2572	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2573	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2574	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2575	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2576	}
2577
2578	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2579	{
2580	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2581	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2582	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2583	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2584	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2585	}
2586
2587	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2588	{
2589	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2590	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2591	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2592	}
2593
2594	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2595	if (pFpuCtx->au32RsrvdRest[i])
2596	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2597	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
2598	}
2599
2600	pHlp->pfnPrintf(pHlp,
2601	"%sEFER =%016RX64\n"
2602	"%sPAT =%016RX64\n"
2603	"%sSTAR =%016RX64\n"
2604	"%sCSTAR =%016RX64\n"
2605	"%sLSTAR =%016RX64\n"
2606	"%sSFMASK =%016RX64\n"
2607	"%sKERNELGSBASE =%016RX64\n",
2608	pszPrefix, pCtx->msrEFER,
2609	pszPrefix, pCtx->msrPAT,
2610	pszPrefix, pCtx->msrSTAR,
2611	pszPrefix, pCtx->msrCSTAR,
2612	pszPrefix, pCtx->msrLSTAR,
2613	pszPrefix, pCtx->msrSFMASK,
2614	pszPrefix, pCtx->msrKERNELGSBASE);
2615	break;
2616	}
2617	}
2618
2619
2620	/**
2621	* Display all cpu states and any other cpum info.
2622	*
2623	* @param pVM The cross context VM structure.
2624	* @param pHlp The info helper functions.
2625	* @param pszArgs Arguments, ignored.
2626	*/
2627	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2628	{
2629	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2630	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2631	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2632	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2633	cpumR3InfoHost(pVM, pHlp, pszArgs);
2634	}
2635
2636
2637	/**
2638	* Parses the info argument.
2639	*
2640	* The argument starts with 'verbose', 'terse' or 'default' and then
2641	* continues with the comment string.
2642	*
2643	* @param pszArgs The pointer to the argument string.
2644	* @param penmType Where to store the dump type request.
2645	* @param ppszComment Where to store the pointer to the comment string.
2646	*/
2647	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2648	{
2649	if (!pszArgs)
2650	{
2651	*penmType = CPUMDUMPTYPE_DEFAULT;
2652	*ppszComment = "";
2653	}
2654	else
2655	{
2656	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2657	{
2658	pszArgs += 7;
2659	*penmType = CPUMDUMPTYPE_VERBOSE;
2660	}
2661	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2662	{
2663	pszArgs += 5;
2664	*penmType = CPUMDUMPTYPE_TERSE;
2665	}
2666	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2667	{
2668	pszArgs += 7;
2669	*penmType = CPUMDUMPTYPE_DEFAULT;
2670	}
2671	else
2672	*penmType = CPUMDUMPTYPE_DEFAULT;
2673	*ppszComment = RTStrStripL(pszArgs);
2674	}
2675	}
2676
2677
2678	/**
2679	* Display the guest cpu state.
2680	*
2681	* @param pVM The cross context VM structure.
2682	* @param pHlp The info helper functions.
2683	* @param pszArgs Arguments.
2684	*/
2685	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2686	{
2687	CPUMDUMPTYPE enmType;
2688	const char *pszComment;
2689	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2690
2691	PVMCPU pVCpu = VMMGetCpu(pVM);
2692	if (!pVCpu)
2693	pVCpu = &pVM->aCpus[0];
2694
2695	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2696
2697	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2698	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2699	}
2700
2701
2702	/**
2703	* Displays an SVM VMCB control area.
2704	*
2705	* @param pHlp The info helper functions.
2706	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
2707	* @param pszPrefix Caller specified string prefix.
2708	*/
2709	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
2710	{
2711	AssertReturnVoid(pHlp);
2712	AssertReturnVoid(pVmcbCtrl);
2713
2714	pHlp->pfnPrintf(pHlp, "%su16InterceptRdCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
2715	pHlp->pfnPrintf(pHlp, "%su16InterceptWrCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
2716	pHlp->pfnPrintf(pHlp, "%su16InterceptRdDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
2717	pHlp->pfnPrintf(pHlp, "%su16InterceptWrDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
2718	pHlp->pfnPrintf(pHlp, "%su32InterceptXcpt = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
2719	pHlp->pfnPrintf(pHlp, "%su64InterceptCtrl = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
2720	pHlp->pfnPrintf(pHlp, "%su16PauseFilterThreshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
2721	pHlp->pfnPrintf(pHlp, "%su16PauseFilterCount = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
2722	pHlp->pfnPrintf(pHlp, "%su64IOPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
2723	pHlp->pfnPrintf(pHlp, "%su64MSRPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
2724	pHlp->pfnPrintf(pHlp, "%su64TSCOffset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
2725	pHlp->pfnPrintf(pHlp, "%sTLBCtrl\n", pszPrefix);
2726	pHlp->pfnPrintf(pHlp, "%s u32ASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
2727	pHlp->pfnPrintf(pHlp, "%s u8TLBFlush = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
2728	pHlp->pfnPrintf(pHlp, "%sIntCtrl\n", pszPrefix);
2729	pHlp->pfnPrintf(pHlp, "%s u8VTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
2730	pHlp->pfnPrintf(pHlp, "%s u1VIrqPending = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
2731	pHlp->pfnPrintf(pHlp, "%s u1VGif = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
2732	pHlp->pfnPrintf(pHlp, "%s u4VIntrPrio = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
2733	pHlp->pfnPrintf(pHlp, "%s u1IgnoreTPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
2734	pHlp->pfnPrintf(pHlp, "%s u1VIntrMasking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
2735	pHlp->pfnPrintf(pHlp, "%s u1VGifEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
2736	pHlp->pfnPrintf(pHlp, "%s u1AvicEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
2737	pHlp->pfnPrintf(pHlp, "%s u8VIntrVector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
2738	pHlp->pfnPrintf(pHlp, "%sIntShadow\n", pszPrefix);
2739	pHlp->pfnPrintf(pHlp, "%s u1IntShadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
2740	pHlp->pfnPrintf(pHlp, "%s u1GuestIntMask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
2741	pHlp->pfnPrintf(pHlp, "%su64ExitCode = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
2742	pHlp->pfnPrintf(pHlp, "%su64ExitInfo1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
2743	pHlp->pfnPrintf(pHlp, "%su64ExitInfo2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
2744	pHlp->pfnPrintf(pHlp, "%sExitIntInfo\n", pszPrefix);
2745	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
2746	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
2747	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
2748	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
2749	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
2750	pHlp->pfnPrintf(pHlp, "%sNestedPaging and SEV\n", pszPrefix);
2751	pHlp->pfnPrintf(pHlp, "%s u1NestedPaging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
2752	pHlp->pfnPrintf(pHlp, "%s u1Sev = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
2753	pHlp->pfnPrintf(pHlp, "%s u1SevEs = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
2754	pHlp->pfnPrintf(pHlp, "%sAvicBar\n", pszPrefix);
2755	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
2756	pHlp->pfnPrintf(pHlp, "%sEventInject\n", pszPrefix);
2757	pHlp->pfnPrintf(pHlp, "%s EventInject\n", pszPrefix);
2758	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
2759	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
2760	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
2761	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
2762	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
2763	pHlp->pfnPrintf(pHlp, "%su64NestedPagingCR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
2764	pHlp->pfnPrintf(pHlp, "%sLBR virtualization\n", pszPrefix);
2765	pHlp->pfnPrintf(pHlp, "%s u1LbrVirt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
2766	pHlp->pfnPrintf(pHlp, "%s u1VirtVmsaveVmload = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
2767	pHlp->pfnPrintf(pHlp, "%su32VmcbCleanBits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
2768	pHlp->pfnPrintf(pHlp, "%su64NextRIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
2769	pHlp->pfnPrintf(pHlp, "%scbInstrFetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
2770	pHlp->pfnPrintf(pHlp, "%sabInstr = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
2771	pHlp->pfnPrintf(pHlp, "%sAvicBackingPagePtr\n", pszPrefix);
2772	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
2773	pHlp->pfnPrintf(pHlp, "%sAvicLogicalTablePtr\n", pszPrefix);
2774	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
2775	pHlp->pfnPrintf(pHlp, "%sAvicPhysicalTablePtr\n", pszPrefix);
2776	pHlp->pfnPrintf(pHlp, "%s u8LastGuestCoreId = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
2777	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
2778	}
2779
2780
2781	/**
2782	* Helper for dumping the SVM VMCB selector registers.
2783	*
2784	* @param pHlp The info helper functions.
2785	* @param pSel Pointer to the SVM selector register.
2786	* @param pszName Name of the selector.
2787	* @param pszPrefix Caller specified string prefix.
2788	*/
2789	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
2790	{
2791	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
2792	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
2793	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
2794	}
2795
2796
2797	/**
2798	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
2799	*
2800	* @param pHlp The info helper functions.
2801	* @param pXdtr Pointer to the descriptor table register.
2802	* @param pszName Name of the descriptor table register.
2803	* @param pszPrefix Caller specified string prefix.
2804	*/
2805	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
2806	{
2807	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
2808	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
2809	}
2810
2811
2812	/**
2813	* Displays an SVM VMCB state-save area.
2814	*
2815	* @param pHlp The info helper functions.
2816	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
2817	* @param pszPrefix Caller specified string prefix.
2818	*/
2819	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
2820	{
2821	AssertReturnVoid(pHlp);
2822	AssertReturnVoid(pVmcbStateSave);
2823
2824	char szEFlags[80];
2825	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
2826
2827	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
2828	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
2829	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
2830	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
2831	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
2832	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
2833	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
2834	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
2835	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
2836	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
2837	pHlp->pfnPrintf(pHlp, "%su8CPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
2838	pHlp->pfnPrintf(pHlp, "%su64EFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
2839	pHlp->pfnPrintf(pHlp, "%su64CR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
2840	pHlp->pfnPrintf(pHlp, "%su64CR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
2841	pHlp->pfnPrintf(pHlp, "%su64CR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
2842	pHlp->pfnPrintf(pHlp, "%su64DR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
2843	pHlp->pfnPrintf(pHlp, "%su64DR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
2844	pHlp->pfnPrintf(pHlp, "%su64RFlags = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
2845	pHlp->pfnPrintf(pHlp, "%su64RIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
2846	pHlp->pfnPrintf(pHlp, "%su64RSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
2847	pHlp->pfnPrintf(pHlp, "%su64RAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
2848	pHlp->pfnPrintf(pHlp, "%su64STAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
2849	pHlp->pfnPrintf(pHlp, "%su64LSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
2850	pHlp->pfnPrintf(pHlp, "%su64CSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
2851	pHlp->pfnPrintf(pHlp, "%su64SFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
2852	pHlp->pfnPrintf(pHlp, "%su64KernelGSBase = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
2853	pHlp->pfnPrintf(pHlp, "%su64SysEnterCS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
2854	pHlp->pfnPrintf(pHlp, "%su64SysEnterEIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
2855	pHlp->pfnPrintf(pHlp, "%su64SysEnterESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
2856	pHlp->pfnPrintf(pHlp, "%su64CR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
2857	pHlp->pfnPrintf(pHlp, "%su64PAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
2858	pHlp->pfnPrintf(pHlp, "%su64DBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
2859	pHlp->pfnPrintf(pHlp, "%su64BR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
2860	pHlp->pfnPrintf(pHlp, "%su64BR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
2861	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPFROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
2862	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPTO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
2863	}
2864
2865
2866	/**
2867	* Display the guest's hardware-virtualization cpu state.
2868	*
2869	* @param pVM The cross context VM structure.
2870	* @param pHlp The info helper functions.
2871	* @param pszArgs Arguments, ignored.
2872	*/
2873	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2874	{
2875	RT_NOREF(pszArgs);
2876
2877	PVMCPU pVCpu = VMMGetCpu(pVM);
2878	if (!pVCpu)
2879	pVCpu = &pVM->aCpus[0];
2880
2881	/*
2882	* Figure out what to dump.
2883	*
2884	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
2885	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
2886	* dump hwvirt. state when the guest CPU is executing a nested-guest.
2887	*/
2888	/** @todo perhaps make this configurable through pszArgs, depending on how much
2889	* noise we wish to accept when nested hwvirt. isn't used. */
2890	#define CPUMHWVIRTDUMP_NONE (0)
2891	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
2892	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
2893	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
2894	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
2895
2896	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2897	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
2898	bool const fSvm = pVM->cpum.ro.GuestFeatures.fSvm;
2899	bool const fVmx = pVM->cpum.ro.GuestFeatures.fVmx;
2900	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
2901	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
2902	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
2903	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
2904	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
2905
2906	/*
2907	* Dump it.
2908	*/
2909	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
2910
2911	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
2912	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
2913
2914	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
2915	":" : "");
2916	if (fDumpState & CPUMHWVIRTDUMP_SVM)
2917	{
2918	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
2919
2920	char szEFlags[80];
2921	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
2922	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
2923	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
2924	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
2925	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
2926	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
2927	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
2928	pHlp->pfnPrintf(pHlp, " HostState:\n");
2929	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
2930	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
2931	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
2932	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
2933	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
2934	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
2935	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
2936	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
2937	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
2938	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2939	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2940	pSel = &pCtx->hwvirt.svm.HostState.cs;
2941	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2942	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2943	pSel = &pCtx->hwvirt.svm.HostState.ss;
2944	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2945	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2946	pSel = &pCtx->hwvirt.svm.HostState.ds;
2947	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
2948	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
2949	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
2950	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
2951	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
2952	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
2953	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
2954	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
2955	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
2956	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
2957	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
2958	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
2959	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
2960	}
2961
2962	if (fDumpState & CPUMHWVIRTDUMP_VMX)
2963	{
2964	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
2965	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
2966	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
2967	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
2968	pHlp->pfnPrintf(pHlp, " enmInstrDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmInstrDiag,
2969	HMVmxGetInstrDiagDesc(pCtx->hwvirt.vmx.enmInstrDiag));
2970	/** @todo NSTVMX: Dump remaining/new fields. */
2971	}
2972
2973	#undef CPUMHWVIRTDUMP_NONE
2974	#undef CPUMHWVIRTDUMP_COMMON
2975	#undef CPUMHWVIRTDUMP_SVM
2976	#undef CPUMHWVIRTDUMP_VMX
2977	#undef CPUMHWVIRTDUMP_LAST
2978	#undef CPUMHWVIRTDUMP_ALL
2979	}
2980
2981	/**
2982	* Display the current guest instruction
2983	*
2984	* @param pVM The cross context VM structure.
2985	* @param pHlp The info helper functions.
2986	* @param pszArgs Arguments, ignored.
2987	*/
2988	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2989	{
2990	NOREF(pszArgs);
2991
2992	PVMCPU pVCpu = VMMGetCpu(pVM);
2993	if (!pVCpu)
2994	pVCpu = &pVM->aCpus[0];
2995
2996	char szInstruction[256];
2997	szInstruction[0] = '\0';
2998	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
2999	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
3000	}
3001
3002
3003	/**
3004	* Display the hypervisor cpu state.
3005	*
3006	* @param pVM The cross context VM structure.
3007	* @param pHlp The info helper functions.
3008	* @param pszArgs Arguments, ignored.
3009	*/
3010	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3011	{
3012	PVMCPU pVCpu = VMMGetCpu(pVM);
3013	if (!pVCpu)
3014	pVCpu = &pVM->aCpus[0];
3015
3016	CPUMDUMPTYPE enmType;
3017	const char *pszComment;
3018	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3019	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3020	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3021	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3022	}
3023
3024
3025	/**
3026	* Display the host cpu state.
3027	*
3028	* @param pVM The cross context VM structure.
3029	* @param pHlp The info helper functions.
3030	* @param pszArgs Arguments, ignored.
3031	*/
3032	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3033	{
3034	CPUMDUMPTYPE enmType;
3035	const char *pszComment;
3036	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3037	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3038
3039	PVMCPU pVCpu = VMMGetCpu(pVM);
3040	if (!pVCpu)
3041	pVCpu = &pVM->aCpus[0];
3042	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
3043
3044	/*
3045	* Format the EFLAGS.
3046	*/
3047	#if HC_ARCH_BITS == 32
3048	uint32_t efl = pCtx->eflags.u32;
3049	#else
3050	uint64_t efl = pCtx->rflags;
3051	#endif
3052	char szEFlags[80];
3053	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3054
3055	/*
3056	* Format the registers.
3057	*/
3058	#if HC_ARCH_BITS == 32
3059	pHlp->pfnPrintf(pHlp,
3060	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3061	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3062	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3063	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3064	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3065	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3066	,
3067	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
3068	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3069	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3070	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
3071	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3072	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3073	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3074	#else
3075	pHlp->pfnPrintf(pHlp,
3076	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3077	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3078	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3079	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3080	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3081	"r14=%016RX64 r15=%016RX64\n"
3082	"iopl=%d %31s\n"
3083	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3084	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3085	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
3086	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3087	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3088	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3089	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3090	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3091	,
3092	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
3093	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3094	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
3095	/pCtx->r8, pCtx->r9,/ pCtx->r10,
3096	pCtx->r11, pCtx->r12, pCtx->r13,
3097	pCtx->r14, pCtx->r15,
3098	X86_EFL_GET_IOPL(efl), szEFlags,
3099	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3100	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
3101	pCtx->cr4, pCtx->ldtr, pCtx->tr,
3102	pCtx->dr0, pCtx->dr1, pCtx->dr2,
3103	pCtx->dr3, pCtx->dr6, pCtx->dr7,
3104	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3105	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3106	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3107	#endif
3108	}
3109
3110	/**
3111	* Structure used when disassembling and instructions in DBGF.
3112	* This is used so the reader function can get the stuff it needs.
3113	*/
3114	typedef struct CPUMDISASSTATE
3115	{
3116	/** Pointer to the CPU structure. */
3117	PDISCPUSTATE pCpu;
3118	/** Pointer to the VM. */
3119	PVM pVM;
3120	/** Pointer to the VMCPU. */
3121	PVMCPU pVCpu;
3122	/** Pointer to the first byte in the segment. */
3123	RTGCUINTPTR GCPtrSegBase;
3124	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3125	RTGCUINTPTR GCPtrSegEnd;
3126	/** The size of the segment minus 1. */
3127	RTGCUINTPTR cbSegLimit;
3128	/** Pointer to the current page - R3 Ptr. */
3129	void const *pvPageR3;
3130	/** Pointer to the current page - GC Ptr. */
3131	RTGCPTR pvPageGC;
3132	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3133	PGMPAGEMAPLOCK PageMapLock;
3134	/** Whether the PageMapLock is valid or not. */
3135	bool fLocked;
3136	/** 64 bits mode or not. */
3137	bool f64Bits;
3138	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3139
3140
3141	/**
3142	* @callback_method_impl{FNDISREADBYTES}
3143	*/
3144	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3145	{
3146	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3147	for (;;)
3148	{
3149	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3150
3151	/*
3152	* Need to update the page translation?
3153	*/
3154	if ( !pState->pvPageR3
3155	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3156	{
3157	int rc = VINF_SUCCESS;
3158
3159	/* translate the address */
3160	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3161	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
3162	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
3163	{
3164	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3165	if (!pState->pvPageR3)
3166	rc = VERR_INVALID_POINTER;
3167	}
3168	else
3169	{
3170	/* Release mapping lock previously acquired. */
3171	if (pState->fLocked)
3172	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3173	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3174	pState->fLocked = RT_SUCCESS_NP(rc);
3175	}
3176	if (RT_FAILURE(rc))
3177	{
3178	pState->pvPageR3 = NULL;
3179	return rc;
3180	}
3181	}
3182
3183	/*
3184	* Check the segment limit.
3185	*/
3186	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3187	return VERR_OUT_OF_SELECTOR_BOUNDS;
3188
3189	/*
3190	* Calc how much we can read.
3191	*/
3192	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3193	if (!pState->f64Bits)
3194	{
3195	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3196	if (cb > cbSeg && cbSeg)
3197	cb = cbSeg;
3198	}
3199	if (cb > cbMaxRead)
3200	cb = cbMaxRead;
3201
3202	/*
3203	* Read and advance or exit.
3204	*/
3205	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3206	offInstr += (uint8_t)cb;
3207	if (cb >= cbMinRead)
3208	{
3209	pDis->cbCachedInstr = offInstr;
3210	return VINF_SUCCESS;
3211	}
3212	cbMinRead -= (uint8_t)cb;
3213	cbMaxRead -= (uint8_t)cb;
3214	}
3215	}
3216
3217
3218	/**
3219	* Disassemble an instruction and return the information in the provided structure.
3220	*
3221	* @returns VBox status code.
3222	* @param pVM The cross context VM structure.
3223	* @param pVCpu The cross context virtual CPU structure.
3224	* @param pCtx Pointer to the guest CPU context.
3225	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3226	* @param pCpu Disassembly state.
3227	* @param pszPrefix String prefix for logging (debug only).
3228	*
3229	*/
3230	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
3231	const char *pszPrefix)
3232	{
3233	CPUMDISASSTATE State;
3234	int rc;
3235
3236	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3237	State.pCpu = pCpu;
3238	State.pvPageGC = 0;
3239	State.pvPageR3 = NULL;
3240	State.pVM = pVM;
3241	State.pVCpu = pVCpu;
3242	State.fLocked = false;
3243	State.f64Bits = false;
3244
3245	/*
3246	* Get selector information.
3247	*/
3248	DISCPUMODE enmDisCpuMode;
3249	if ( (pCtx->cr0 & X86_CR0_PE)
3250	&& pCtx->eflags.Bits.u1VM == 0)
3251	{
3252	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3253	{
3254	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3255	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
3256	# endif
3257	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3258	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
3259	}
3260	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
3261	State.GCPtrSegBase = pCtx->cs.u64Base;
3262	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
3263	State.cbSegLimit = pCtx->cs.u32Limit;
3264	enmDisCpuMode = (State.f64Bits)
3265	? DISCPUMODE_64BIT
3266	: pCtx->cs.Attr.n.u1DefBig
3267	? DISCPUMODE_32BIT
3268	: DISCPUMODE_16BIT;
3269	}
3270	else
3271	{
3272	/* real or V86 mode */
3273	enmDisCpuMode = DISCPUMODE_16BIT;
3274	State.GCPtrSegBase = pCtx->cs.Sel * 16;
3275	State.GCPtrSegEnd = 0xFFFFFFFF;
3276	State.cbSegLimit = 0xFFFFFFFF;
3277	}
3278
3279	/*
3280	* Disassemble the instruction.
3281	*/
3282	uint32_t cbInstr;
3283	#ifndef LOG_ENABLED
3284	RT_NOREF_PV(pszPrefix);
3285	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
3286	if (RT_SUCCESS(rc))
3287	{
3288	#else
3289	char szOutput[160];
3290	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
3291	pCpu, &cbInstr, szOutput, sizeof(szOutput));
3292	if (RT_SUCCESS(rc))
3293	{
3294	/* log it */
3295	if (pszPrefix)
3296	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3297	else
3298	Log(("%s", szOutput));
3299	#endif
3300	rc = VINF_SUCCESS;
3301	}
3302	else
3303	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
3304
3305	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3306	if (State.fLocked)
3307	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3308
3309	return rc;
3310	}
3311
3312
3313
3314	/**
3315	* API for controlling a few of the CPU features found in CR4.
3316	*
3317	* Currently only X86_CR4_TSD is accepted as input.
3318	*
3319	* @returns VBox status code.
3320	*
3321	* @param pVM The cross context VM structure.
3322	* @param fOr The CR4 OR mask.
3323	* @param fAnd The CR4 AND mask.
3324	*/
3325	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3326	{
3327	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3328	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3329
3330	pVM->cpum.s.CR4.OrMask &= fAnd;
3331	pVM->cpum.s.CR4.OrMask \|= fOr;
3332
3333	return VINF_SUCCESS;
3334	}
3335
3336
3337	/**
3338	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3339	*
3340	* Only REM should ever call this function!
3341	*
3342	* @returns The changed flags.
3343	* @param pVCpu The cross context virtual CPU structure.
3344	* @param puCpl Where to return the current privilege level (CPL).
3345	*/
3346	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3347	{
3348	Assert(!pVCpu->cpum.s.fRawEntered);
3349	Assert(!pVCpu->cpum.s.fRemEntered);
3350
3351	/*
3352	* Get the CPL first.
3353	*/
3354	*puCpl = CPUMGetGuestCPL(pVCpu);
3355
3356	/*
3357	* Get and reset the flags.
3358	*/
3359	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3360	pVCpu->cpum.s.fChanged = 0;
3361
3362	/** @todo change the switcher to use the fChanged flags. */
3363	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3364	{
3365	fFlags \|= CPUM_CHANGED_FPU_REM;
3366	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3367	}
3368
3369	pVCpu->cpum.s.fRemEntered = true;
3370	return fFlags;
3371	}
3372
3373
3374	/**
3375	* Leaves REM.
3376	*
3377	* @param pVCpu The cross context virtual CPU structure.
3378	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3379	* registers.
3380	*/
3381	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3382	{
3383	Assert(!pVCpu->cpum.s.fRawEntered);
3384	Assert(pVCpu->cpum.s.fRemEntered);
3385
3386	RT_NOREF_PV(fNoOutOfSyncSels);
3387
3388	pVCpu->cpum.s.fRemEntered = false;
3389	}
3390
3391
3392	/**
3393	* Called when the ring-3 init phase completes.
3394	*
3395	* @returns VBox status code.
3396	* @param pVM The cross context VM structure.
3397	* @param enmWhat Which init phase.
3398	*/
3399	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
3400	{
3401	switch (enmWhat)
3402	{
3403	case VMINITCOMPLETED_RING3:
3404	{
3405	/*
3406	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
3407	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
3408	*/
3409	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3410	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3411	{
3412	PVMCPU pVCpu = &pVM->aCpus[i];
3413	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
3414	if (fSupportsLongMode)
3415	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3416	}
3417
3418	cpumR3MsrRegStats(pVM);
3419	break;
3420	}
3421
3422	case VMINITCOMPLETED_HM:
3423	{
3424	/*
3425	* Currently, nested VMX/SVM both derives their guest VMX/SVM CPUID bit from the host
3426	* CPUID bit. This could be later changed if we need to support nested-VMX on CPUs
3427	* that are not capable of VMX.
3428	*/
3429	if (pVM->cpum.s.GuestFeatures.fVmx)
3430	{
3431	Assert( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
3432	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
3433	cpumR3InitVmxCpuFeatures(pVM);
3434	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
3435	}
3436
3437	if (pVM->cpum.s.GuestFeatures.fVmx)
3438	LogRel(("CPUM: Enabled guest VMX support\n"));
3439	else if (pVM->cpum.s.GuestFeatures.fSvm)
3440	LogRel(("CPUM: Enabled guest SVM support\n"));
3441	break;
3442	}
3443
3444	default:
3445	break;
3446	}
3447	return VINF_SUCCESS;
3448	}
3449
3450
3451	/**
3452	* Called when the ring-0 init phases completed.
3453	*
3454	* @param pVM The cross context VM structure.
3455	*/
3456	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
3457	{
3458	/*
3459	* Log the cpuid.
3460	*/
3461	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
3462	RTCPUSET OnlineSet;
3463	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
3464	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
3465	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
3466	RTCPUID cCores = RTMpGetCoreCount();
3467	if (cCores)
3468	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
3469	LogRel(("*********************** CPUID dump **********************\n"));
3470	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
3471	LogRel(("\n"));
3472	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
3473	RTLogRelSetBuffering(fOldBuffered);
3474	LogRel(("****************** End of CPUID dump ********************\n"));
3475	}
3476

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 74043

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