CPUM.cpp@ 74517

Last change on this file since 74517 was 74512, checked in by vboxsync, 7 years ago
VMM/CPUM: Nested VMX: bugref:9180 Paranoia, since our code does not check secondary processor-based controls each time it checks one of its sub-controls.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 179.1 KB

Line
1	/* $Id: CPUM.cpp 74512 2018-09-28 06:56:26Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for CPUMCTX. */
329	static const SSMFIELD g_aCpumX87Fields[] =
330	{
331	SSMFIELD_ENTRY( X86FXSTATE, FCW),
332	SSMFIELD_ENTRY( X86FXSTATE, FSW),
333	SSMFIELD_ENTRY( X86FXSTATE, FTW),
334	SSMFIELD_ENTRY( X86FXSTATE, FOP),
335	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
336	SSMFIELD_ENTRY( X86FXSTATE, CS),
337	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
338	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
339	SSMFIELD_ENTRY( X86FXSTATE, DS),
340	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
341	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
342	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
343	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
344	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
345	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
346	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
347	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
348	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
349	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
350	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
351	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
352	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
353	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
354	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
355	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
356	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
357	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
358	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
359	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
360	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
361	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
362	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
363	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
364	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
365	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
366	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
367	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
368	SSMFIELD_ENTRY_TERM()
369	};
370
371	/** Saved state field descriptors for X86XSAVEHDR. */
372	static const SSMFIELD g_aCpumXSaveHdrFields[] =
373	{
374	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
375	SSMFIELD_ENTRY_TERM()
376	};
377
378	/** Saved state field descriptors for X86XSAVEYMMHI. */
379	static const SSMFIELD g_aCpumYmmHiFields[] =
380	{
381	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
382	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
383	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
384	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
385	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
386	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
387	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
388	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
389	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
390	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
391	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
392	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
393	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
394	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
395	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
396	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
397	SSMFIELD_ENTRY_TERM()
398	};
399
400	/** Saved state field descriptors for X86XSAVEBNDREGS. */
401	static const SSMFIELD g_aCpumBndRegsFields[] =
402	{
403	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
404	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
405	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
406	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
407	SSMFIELD_ENTRY_TERM()
408	};
409
410	/** Saved state field descriptors for X86XSAVEBNDCFG. */
411	static const SSMFIELD g_aCpumBndCfgFields[] =
412	{
413	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
414	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
415	SSMFIELD_ENTRY_TERM()
416	};
417
418	#if 0 /** @todo */
419	/** Saved state field descriptors for X86XSAVEOPMASK. */
420	static const SSMFIELD g_aCpumOpmaskFields[] =
421	{
422	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
423	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
424	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
425	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
426	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
427	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
428	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
429	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
430	SSMFIELD_ENTRY_TERM()
431	};
432	#endif
433
434	/** Saved state field descriptors for X86XSAVEZMMHI256. */
435	static const SSMFIELD g_aCpumZmmHi256Fields[] =
436	{
437	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
438	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
439	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
440	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
441	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
442	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
443	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
444	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
445	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
446	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
447	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
448	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
449	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
450	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
451	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
452	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
453	SSMFIELD_ENTRY_TERM()
454	};
455
456	/** Saved state field descriptors for X86XSAVEZMM16HI. */
457	static const SSMFIELD g_aCpumZmm16HiFields[] =
458	{
459	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
460	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
461	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
462	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
463	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
464	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
465	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
466	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
467	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
468	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
469	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
470	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
471	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
472	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
473	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
474	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
475	SSMFIELD_ENTRY_TERM()
476	};
477
478
479
480	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
481	* registeres changed. */
482	static const SSMFIELD g_aCpumX87FieldsMem[] =
483	{
484	SSMFIELD_ENTRY( X86FXSTATE, FCW),
485	SSMFIELD_ENTRY( X86FXSTATE, FSW),
486	SSMFIELD_ENTRY( X86FXSTATE, FTW),
487	SSMFIELD_ENTRY( X86FXSTATE, FOP),
488	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
489	SSMFIELD_ENTRY( X86FXSTATE, CS),
490	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
491	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
492	SSMFIELD_ENTRY( X86FXSTATE, DS),
493	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
494	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
495	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
496	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
497	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
498	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
499	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
500	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
501	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
502	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
503	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
504	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
505	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
506	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
507	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
508	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
509	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
510	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
511	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
512	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
513	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
514	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
515	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
516	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
517	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
518	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
519	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
520	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
521	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
522	};
523
524	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
525	* registeres changed. */
526	static const SSMFIELD g_aCpumCtxFieldsMem[] =
527	{
528	SSMFIELD_ENTRY( CPUMCTX, rdi),
529	SSMFIELD_ENTRY( CPUMCTX, rsi),
530	SSMFIELD_ENTRY( CPUMCTX, rbp),
531	SSMFIELD_ENTRY( CPUMCTX, rax),
532	SSMFIELD_ENTRY( CPUMCTX, rbx),
533	SSMFIELD_ENTRY( CPUMCTX, rdx),
534	SSMFIELD_ENTRY( CPUMCTX, rcx),
535	SSMFIELD_ENTRY( CPUMCTX, rsp),
536	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
537	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
538	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
539	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
540	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
541	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
542	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
543	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
544	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
545	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
546	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
547	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
548	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
549	SSMFIELD_ENTRY( CPUMCTX, rflags),
550	SSMFIELD_ENTRY( CPUMCTX, rip),
551	SSMFIELD_ENTRY( CPUMCTX, r8),
552	SSMFIELD_ENTRY( CPUMCTX, r9),
553	SSMFIELD_ENTRY( CPUMCTX, r10),
554	SSMFIELD_ENTRY( CPUMCTX, r11),
555	SSMFIELD_ENTRY( CPUMCTX, r12),
556	SSMFIELD_ENTRY( CPUMCTX, r13),
557	SSMFIELD_ENTRY( CPUMCTX, r14),
558	SSMFIELD_ENTRY( CPUMCTX, r15),
559	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
560	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
561	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
562	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
563	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
564	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
565	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
566	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
567	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
568	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
569	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
570	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
571	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
572	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
573	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
574	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
575	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
576	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
577	SSMFIELD_ENTRY( CPUMCTX, cr0),
578	SSMFIELD_ENTRY( CPUMCTX, cr2),
579	SSMFIELD_ENTRY( CPUMCTX, cr3),
580	SSMFIELD_ENTRY( CPUMCTX, cr4),
581	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
582	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
583	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
584	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
585	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
586	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
587	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
588	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
589	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
590	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
591	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
592	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
593	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
594	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
595	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
596	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
597	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
598	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
599	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
600	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
601	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
602	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
603	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
604	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
605	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
606	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
607	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
608	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
609	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
610	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
611	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
612	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
613	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
614	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for CPUMCTX_VER1_6. */
619	static const SSMFIELD g_aCpumX87FieldsV16[] =
620	{
621	SSMFIELD_ENTRY( X86FXSTATE, FCW),
622	SSMFIELD_ENTRY( X86FXSTATE, FSW),
623	SSMFIELD_ENTRY( X86FXSTATE, FTW),
624	SSMFIELD_ENTRY( X86FXSTATE, FOP),
625	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
626	SSMFIELD_ENTRY( X86FXSTATE, CS),
627	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
628	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
629	SSMFIELD_ENTRY( X86FXSTATE, DS),
630	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
631	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
632	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
633	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
634	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
635	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
636	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
637	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
638	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
639	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
640	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
641	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
642	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
643	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
644	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
645	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
646	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
647	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
648	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
649	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
650	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
651	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
652	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
653	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
654	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
655	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
656	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
657	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
658	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
659	SSMFIELD_ENTRY_TERM()
660	};
661
662	/** Saved state field descriptors for CPUMCTX_VER1_6. */
663	static const SSMFIELD g_aCpumCtxFieldsV16[] =
664	{
665	SSMFIELD_ENTRY( CPUMCTX, rdi),
666	SSMFIELD_ENTRY( CPUMCTX, rsi),
667	SSMFIELD_ENTRY( CPUMCTX, rbp),
668	SSMFIELD_ENTRY( CPUMCTX, rax),
669	SSMFIELD_ENTRY( CPUMCTX, rbx),
670	SSMFIELD_ENTRY( CPUMCTX, rdx),
671	SSMFIELD_ENTRY( CPUMCTX, rcx),
672	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
673	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
674	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
675	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
676	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
677	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
678	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
679	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
680	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
681	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
682	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
683	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
684	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
685	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
686	SSMFIELD_ENTRY( CPUMCTX, rflags),
687	SSMFIELD_ENTRY( CPUMCTX, rip),
688	SSMFIELD_ENTRY( CPUMCTX, r8),
689	SSMFIELD_ENTRY( CPUMCTX, r9),
690	SSMFIELD_ENTRY( CPUMCTX, r10),
691	SSMFIELD_ENTRY( CPUMCTX, r11),
692	SSMFIELD_ENTRY( CPUMCTX, r12),
693	SSMFIELD_ENTRY( CPUMCTX, r13),
694	SSMFIELD_ENTRY( CPUMCTX, r14),
695	SSMFIELD_ENTRY( CPUMCTX, r15),
696	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
697	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
698	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
699	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
700	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
701	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
702	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
703	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
704	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
705	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
706	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
707	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
708	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
709	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
710	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
711	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
712	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
713	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
714	SSMFIELD_ENTRY( CPUMCTX, cr0),
715	SSMFIELD_ENTRY( CPUMCTX, cr2),
716	SSMFIELD_ENTRY( CPUMCTX, cr3),
717	SSMFIELD_ENTRY( CPUMCTX, cr4),
718	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
719	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
720	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
721	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
722	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
723	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
724	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
725	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
726	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
727	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
728	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
729	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
730	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
731	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
732	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
733	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
734	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
735	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
736	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
737	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
738	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
739	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
740	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
741	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
742	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
743	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
744	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
745	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
746	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
747	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
748	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
749	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
750	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
751	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
752	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
753	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
754	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
755	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
756	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
757	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
758	SSMFIELD_ENTRY_TERM()
759	};
760
761
762	/**
763	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
764	*
765	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
766	* (last instruction pointer, last data pointer, last opcode) except when the ES
767	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
768	* clear these registers there is potential, local FPU leakage from a process
769	* using the FPU to another.
770	*
771	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
772	*
773	* @param pVM The cross context VM structure.
774	*/
775	static void cpumR3CheckLeakyFpu(PVM pVM)
776	{
777	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
778	uint32_t const u32Family = u32CpuVersion >> 8;
779	if ( u32Family >= 6 /* K7 and higher */
780	&& ASMIsAmdCpu())
781	{
782	uint32_t cExt = ASMCpuId_EAX(0x80000000);
783	if (ASMIsValidExtRange(cExt))
784	{
785	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
786	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
787	{
788	for (VMCPUID i = 0; i < pVM->cCpus; i++)
789	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
790	Log(("CPUMR3Init: host CPU has leaky fxsave/fxrstor behaviour\n"));
791	}
792	}
793	}
794	}
795
796
797	/**
798	* Frees memory allocated for the SVM hardware virtualization state.
799	*
800	* @param pVM The cross context VM structure.
801	*/
802	static void cpumR3FreeSvmHwVirtState(PVM pVM)
803	{
804	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
805	for (VMCPUID i = 0; i < pVM->cCpus; i++)
806	{
807	PVMCPU pVCpu = &pVM->aCpus[i];
808	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
809	{
810	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
811	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
812	}
813	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
814
815	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
816	{
817	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
818	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
819	}
820
821	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
822	{
823	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
824	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
825	}
826	}
827	}
828
829
830	/**
831	* Allocates memory for the SVM hardware virtualization state.
832	*
833	* @returns VBox status code.
834	* @param pVM The cross context VM structure.
835	*/
836	static int cpumR3AllocSvmHwVirtState(PVM pVM)
837	{
838	Assert(pVM->cpum.ro.GuestFeatures.fSvm);
839
840	int rc = VINF_SUCCESS;
841	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
842	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
844	{
845	PVMCPU pVCpu = &pVM->aCpus[i];
846	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
847
848	/*
849	* Allocate the nested-guest VMCB.
850	*/
851	SUPPAGE SupNstGstVmcbPage;
852	RT_ZERO(SupNstGstVmcbPage);
853	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
854	Assert(SVM_VMCB_PAGES == 1);
855	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
856	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
857	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
858	if (RT_FAILURE(rc))
859	{
860	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
861	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
862	break;
863	}
864	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
865
866	/*
867	* Allocate the MSRPM (MSR Permission bitmap).
868	*/
869	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
870	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
871	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
872	if (RT_FAILURE(rc))
873	{
874	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
875	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
876	SVM_MSRPM_PAGES));
877	break;
878	}
879
880	/*
881	* Allocate the IOPM (IO Permission bitmap).
882	*/
883	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
884	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
885	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
886	if (RT_FAILURE(rc))
887	{
888	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
889	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
890	SVM_IOPM_PAGES));
891	break;
892	}
893	}
894
895	/* On any failure, cleanup. */
896	if (RT_FAILURE(rc))
897	cpumR3FreeSvmHwVirtState(pVM);
898
899	return rc;
900	}
901
902
903	/**
904	* Initializes (or re-initializes) per-VCPU SVM hardware virtualization state.
905	*
906	* @param pVCpu The cross context virtual CPU structure.
907	*/
908	DECLINLINE(void) cpumR3InitSvmHwVirtState(PVMCPU pVCpu)
909	{
910	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
911	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
912	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
913
914	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
915	pCtx->hwvirt.svm.uMsrHSavePa = 0;
916	pCtx->hwvirt.svm.uPrevPauseTick = 0;
917	}
918
919
920	/**
921	* Frees memory allocated for the VMX hardware virtualization state.
922	*
923	* @param pVM The cross context VM structure.
924	*/
925	static void cpumR3FreeVmxHwVirtState(PVM pVM)
926	{
927	Assert(pVM->cpum.ro.GuestFeatures.fVmx);
928	for (VMCPUID i = 0; i < pVM->cCpus; i++)
929	{
930	PVMCPU pVCpu = &pVM->aCpus[i];
931	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3)
932	{
933	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
934	pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3 = NULL;
935	}
936	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3)
937	{
938	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
939	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3 = NULL;
940	}
941	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3)
942	{
943	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
944	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3 = NULL;
945	}
946	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3)
947	{
948	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
949	pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
950	}
951	if (pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3)
952	{
953	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
954	pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3 = NULL;
955	}
956	}
957	}
958
959
960	/**
961	* Allocates memory for the VMX hardware virtualization state.
962	*
963	* @returns VBox status code.
964	* @param pVM The cross context VM structure.
965	*/
966	static int cpumR3AllocVmxHwVirtState(PVM pVM)
967	{
968	int rc = VINF_SUCCESS;
969	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n",
970	pVM->cCpus * ( VMX_V_VMCS_PAGES + VMX_V_VIRT_APIC_PAGES + VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * 2
971	+ VMX_V_AUTOMSR_AREA_PAGES)));
972	for (VMCPUID i = 0; i < pVM->cCpus; i++)
973	{
974	PVMCPU pVCpu = &pVM->aCpus[i];
975	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
976
977	/*
978	* Allocate the nested-guest current VMCS.
979	*/
980	Assert(VMX_V_VMCS_PAGES == 1);
981	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
982	rc = SUPR3PageAllocEx(VMX_V_VMCS_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3,
983	&pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR0, NULL /* paPages */);
984	if (RT_FAILURE(rc))
985	{
986	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pVmcsR3);
987	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
988	break;
989	}
990
991	/*
992	* Allocate the Virtual-APIC page.
993	*/
994	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3);
995	rc = SUPR3PageAllocEx(VMX_V_VIRT_APIC_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3,
996	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR0, NULL /* paPages */);
997	if (RT_FAILURE(rc))
998	{
999	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVirtApicPageR3);
1000	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's Virtual-APIC page\n", pVCpu->idCpu,
1001	VMX_V_VIRT_APIC_PAGES));
1002	break;
1003	}
1004
1005	/*
1006	* Allocate the VMREAD-bitmap.
1007	*/
1008	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3);
1009	rc = SUPR3PageAllocEx(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3,
1010	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR0, NULL /* paPages */);
1011	if (RT_FAILURE(rc))
1012	{
1013	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmreadBitmapR3);
1014	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1015	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1016	break;
1017	}
1018
1019	/*
1020	* Allocatge the VMWRITE-bitmap.
1021	*/
1022	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3);
1023	rc = SUPR3PageAllocEx(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES, 0 /* fFlags */,
1024	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3,
1025	&pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR0, NULL /* paPages */);
1026	if (RT_FAILURE(rc))
1027	{
1028	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pvVmwriteBitmapR3);
1029	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1030	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1031	break;
1032	}
1033
1034	/*
1035	* Allocate the MSR auto-load/store area.
1036	*/
1037	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3);
1038	rc = SUPR3PageAllocEx(VMX_V_AUTOMSR_AREA_PAGES, 0 /* fFlags */,
1039	(void **)&pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3,
1040	&pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR0, NULL /* paPages */);
1041	if (RT_FAILURE(rc))
1042	{
1043	Assert(!pVCpu->cpum.s.Guest.hwvirt.vmx.pAutoMsrAreaR3);
1044	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's auto-load/store MSR area\n", pVCpu->idCpu,
1045	VMX_V_AUTOMSR_AREA_PAGES));
1046	break;
1047	}
1048	}
1049
1050	/* On any failure, cleanup. */
1051	if (RT_FAILURE(rc))
1052	cpumR3FreeVmxHwVirtState(pVM);
1053
1054	return rc;
1055	}
1056
1057
1058	/**
1059	* Initializes (or re-initializes) per-VCPU VMX hardware virtualization state.
1060	*
1061	* @param pVCpu The cross context virtual CPU structure.
1062	*/
1063	DECLINLINE(void) cpumR3InitVmxHwVirtState(PVMCPU pVCpu)
1064	{
1065	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1066	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1067	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1068	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1069
1070	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1071	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_VMCS_SIZE);
1072	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1073	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1074	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1075	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1076	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1077	/* Don't reset diagnostics here. */
1078	}
1079
1080
1081	/**
1082	* Displays the host and guest VMX features.
1083	*
1084	* @param pVM The cross context VM structure.
1085	* @param pHlp The info helper functions.
1086	* @param pszArgs "terse", "default" or "verbose".
1087	*/
1088	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1089	{
1090	RT_NOREF(pszArgs);
1091	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1092	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1093	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1094	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA)
1095	{
1096	#define VMXFEATDUMP(a_szDesc, a_Var) \
1097	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1098
1099	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1100	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1101	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1102	if (!pGuestFeatures->fVmx)
1103	return;
1104	/* Basic. */
1105	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1106	/* Pin-based controls. */
1107	VMXFEATDUMP("ExtIntExit - External interrupt VM-exit ", fVmxExtIntExit);
1108	VMXFEATDUMP("NmiExit - NMI VM-exit ", fVmxNmiExit);
1109	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1110	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1111	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1112	/* Processor-based controls. */
1113	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1114	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1115	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1116	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1117	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1118	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1119	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1120	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1121	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1122	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1123	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1124	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1125	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1126	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1127	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1128	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1129	VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag ", fVmxMonitorTrapFlag);
1130	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1131	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1132	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1133	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1134	/* Secondary processor-based controls. */
1135	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1136	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1137	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1138	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1139	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1140	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1141	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1142	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1143	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1144	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1145	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1146	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1147	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1148	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1149	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1150	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1151	VMXFEATDUMP("PML - Supports Page-Modification Log (PML) ", fVmxPml);
1152	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1153	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1154	/* VM-entry controls. */
1155	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1156	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1157	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER on VM-entry ", fVmxEntryLoadEferMsr);
1158	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT on VM-entry ", fVmxEntryLoadPatMsr);
1159	/* VM-exit controls. */
1160	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1161	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1162	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1163	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT on VM-exit ", fVmxExitSavePatMsr);
1164	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT on VM-exit ", fVmxExitLoadPatMsr);
1165	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER on VM-exit ", fVmxExitSaveEferMsr);
1166	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER on VM-exit ", fVmxExitLoadEferMsr);
1167	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1168	VMXFEATDUMP("ExitStoreEferLma - Store EFER.LMA on VM-exit ", fVmxExitStoreEferLma);
1169	VMXFEATDUMP("VmwriteAll - VMWRITE to any VMCS field ", fVmxVmwriteAll);
1170	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1171	/* Miscellaneous data. */
1172	VMXFEATDUMP("ExitStoreEferLma - Inject softint. with 0-len instr. ", fVmxExitStoreEferLma);
1173	VMXFEATDUMP("VmwriteAll - Inject softint. with 0-len instr. ", fVmxVmwriteAll);
1174	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1175	#undef VMXFEATDUMP
1176	}
1177	else
1178	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1179	}
1180
1181
1182	/**
1183	* Initializes VMX host and guest features.
1184	*
1185	* @param pVM The cross context VM structure.
1186	*
1187	* @remarks This must be called only after HM has fully initialized since it calls
1188	* into HM to retrieve VMX and related MSRs.
1189	*/
1190	static void cpumR3InitVmxCpuFeatures(PVM pVM)
1191	{
1192	/*
1193	* Init. host features.
1194	*/
1195	PCPUMFEATURES pHostFeat = &pVM->cpum.s.HostFeatures;
1196	VMXMSRS VmxMsrs;
1197	int rc = HMVmxGetHostMsrs(pVM, &VmxMsrs);
1198	if (RT_SUCCESS(rc))
1199	{
1200	/* Basic information. */
1201	pHostFeat->fVmxInsOutInfo = RT_BF_GET(VmxMsrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
1202
1203	/* Pin-based VM-execution controls. */
1204	uint32_t const fPinCtls = VmxMsrs.PinCtls.n.allowed1;
1205	pHostFeat->fVmxExtIntExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
1206	pHostFeat->fVmxNmiExit = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
1207	pHostFeat->fVmxVirtNmi = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
1208	pHostFeat->fVmxPreemptTimer = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
1209	pHostFeat->fVmxPostedInt = RT_BOOL(fPinCtls & VMX_PIN_CTLS_POSTED_INT);
1210
1211	/* Processor-based VM-execution controls. */
1212	uint32_t const fProcCtls = VmxMsrs.ProcCtls.n.allowed1;
1213	pHostFeat->fVmxIntWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
1214	pHostFeat->fVmxTscOffsetting = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1215	pHostFeat->fVmxHltExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
1216	pHostFeat->fVmxInvlpgExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
1217	pHostFeat->fVmxMwaitExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
1218	pHostFeat->fVmxRdpmcExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
1219	pHostFeat->fVmxRdtscExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
1220	pHostFeat->fVmxCr3LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
1221	pHostFeat->fVmxCr3StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
1222	pHostFeat->fVmxCr8LoadExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
1223	pHostFeat->fVmxCr8StoreExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
1224	pHostFeat->fVmxUseTprShadow = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
1225	pHostFeat->fVmxNmiWindowExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1226	pHostFeat->fVmxMovDRxExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
1227	pHostFeat->fVmxUncondIoExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
1228	pHostFeat->fVmxUseIoBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
1229	pHostFeat->fVmxMonitorTrapFlag = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1230	pHostFeat->fVmxUseMsrBitmaps = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
1231	pHostFeat->fVmxMonitorExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
1232	pHostFeat->fVmxPauseExit = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
1233	pHostFeat->fVmxSecondaryExecCtls = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1234
1235	/* Secondary processor-based VM-execution controls. */
1236	if (pHostFeat->fVmxSecondaryExecCtls)
1237	{
1238	uint32_t const fProcCtls2 = VmxMsrs.ProcCtls2.n.allowed1;
1239	pHostFeat->fVmxVirtApicAccess = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1240	pHostFeat->fVmxEpt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
1241	pHostFeat->fVmxDescTableExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1242	pHostFeat->fVmxRdtscp = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
1243	pHostFeat->fVmxVirtX2ApicMode = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1244	pHostFeat->fVmxVpid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
1245	pHostFeat->fVmxWbinvdExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
1246	pHostFeat->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1247	pHostFeat->fVmxApicRegVirt = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1248	pHostFeat->fVmxVirtIntDelivery = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1249	pHostFeat->fVmxPauseLoopExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1250	pHostFeat->fVmxRdrandExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT);
1251	pHostFeat->fVmxInvpcid = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
1252	pHostFeat->fVmxVmFunc = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMFUNC);
1253	pHostFeat->fVmxVmcsShadowing = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VMCS_SHADOWING);
1254	pHostFeat->fVmxRdseedExit = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDSEED_EXIT);
1255	pHostFeat->fVmxPml = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PML);
1256	pHostFeat->fVmxEptXcptVe = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT_VE);
1257	pHostFeat->fVmxXsavesXrstors = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_XSAVES_XRSTORS);
1258	pHostFeat->fVmxUseTscScaling = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_TSC_SCALING);
1259	}
1260
1261	/* VM-entry controls. */
1262	uint32_t const fEntryCtls = VmxMsrs.EntryCtls.n.allowed1;
1263	pHostFeat->fVmxEntryLoadDebugCtls = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
1264	pHostFeat->fVmxIa32eModeGuest = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1265	pHostFeat->fVmxEntryLoadEferMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1266	pHostFeat->fVmxEntryLoadPatMsr = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1267
1268	/* VM-exit controls. */
1269	uint32_t const fExitCtls = VmxMsrs.ExitCtls.n.allowed1;
1270	pHostFeat->fVmxExitSaveDebugCtls = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
1271	pHostFeat->fVmxHostAddrSpaceSize = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1272	pHostFeat->fVmxExitAckExtInt = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
1273	pHostFeat->fVmxExitSavePatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PAT_MSR);
1274	pHostFeat->fVmxExitLoadPatMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_PAT_MSR);
1275	pHostFeat->fVmxExitSaveEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1276	pHostFeat->fVmxExitLoadEferMsr = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
1277	pHostFeat->fVmxSavePreemptTimer = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1278
1279	/* Miscellaneous data. */
1280	uint32_t const fMiscData = VmxMsrs.u64Misc;
1281	pHostFeat->fVmxExitStoreEferLma = RT_BOOL(fMiscData & VMX_MISC_EXIT_STORE_EFER_LMA);
1282	pHostFeat->fVmxVmwriteAll = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
1283	pHostFeat->fVmxEntryInjectSoftInt = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
1284	}
1285
1286	/*
1287	* Initialize the set of VMX features we emulate.
1288	* Note! Some bits might be reported as 1 always if they fall under the default1 class bits
1289	* (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1290	*/
1291	CPUMFEATURES EmuFeat;
1292	RT_ZERO(EmuFeat);
1293	EmuFeat.fVmx = 1;
1294	EmuFeat.fVmxInsOutInfo = 0;
1295	EmuFeat.fVmxExtIntExit = 1;
1296	EmuFeat.fVmxNmiExit = 1;
1297	EmuFeat.fVmxVirtNmi = 0;
1298	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1299	EmuFeat.fVmxPostedInt = 0;
1300	EmuFeat.fVmxIntWindowExit = 1;
1301	EmuFeat.fVmxTscOffsetting = 1;
1302	EmuFeat.fVmxHltExit = 1;
1303	EmuFeat.fVmxInvlpgExit = 1;
1304	EmuFeat.fVmxMwaitExit = 1;
1305	EmuFeat.fVmxRdpmcExit = 1;
1306	EmuFeat.fVmxRdtscExit = 1;
1307	EmuFeat.fVmxCr3LoadExit = 1;
1308	EmuFeat.fVmxCr3StoreExit = 1;
1309	EmuFeat.fVmxCr8LoadExit = 1;
1310	EmuFeat.fVmxCr8StoreExit = 1;
1311	EmuFeat.fVmxUseTprShadow = 0;
1312	EmuFeat.fVmxNmiWindowExit = 0;
1313	EmuFeat.fVmxMovDRxExit = 1;
1314	EmuFeat.fVmxUncondIoExit = 1;
1315	EmuFeat.fVmxUseIoBitmaps = 1;
1316	EmuFeat.fVmxMonitorTrapFlag = 0;
1317	EmuFeat.fVmxUseMsrBitmaps = 0;
1318	EmuFeat.fVmxMonitorExit = 1;
1319	EmuFeat.fVmxPauseExit = 1;
1320	EmuFeat.fVmxSecondaryExecCtls = 1;
1321	EmuFeat.fVmxVirtApicAccess = 0;
1322	EmuFeat.fVmxEpt = 0;
1323	EmuFeat.fVmxDescTableExit = 1;
1324	EmuFeat.fVmxRdtscp = 1;
1325	EmuFeat.fVmxVirtX2ApicMode = 0;
1326	EmuFeat.fVmxVpid = 0;
1327	EmuFeat.fVmxWbinvdExit = 1;
1328	EmuFeat.fVmxUnrestrictedGuest = 0;
1329	EmuFeat.fVmxApicRegVirt = 0;
1330	EmuFeat.fVmxVirtIntDelivery = 0;
1331	EmuFeat.fVmxPauseLoopExit = 0;
1332	EmuFeat.fVmxRdrandExit = 0;
1333	EmuFeat.fVmxInvpcid = 1;
1334	EmuFeat.fVmxVmFunc = 0;
1335	EmuFeat.fVmxVmcsShadowing = 0;
1336	EmuFeat.fVmxRdseedExit = 0;
1337	EmuFeat.fVmxPml = 0;
1338	EmuFeat.fVmxEptXcptVe = 0;
1339	EmuFeat.fVmxXsavesXrstors = 0;
1340	EmuFeat.fVmxUseTscScaling = 0;
1341	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1342	EmuFeat.fVmxIa32eModeGuest = 1;
1343	EmuFeat.fVmxEntryLoadEferMsr = 1;
1344	EmuFeat.fVmxEntryLoadPatMsr = 0;
1345	EmuFeat.fVmxExitSaveDebugCtls = 1;
1346	EmuFeat.fVmxHostAddrSpaceSize = 1;
1347	EmuFeat.fVmxExitAckExtInt = 0;
1348	EmuFeat.fVmxExitSavePatMsr = 0;
1349	EmuFeat.fVmxExitLoadPatMsr = 0;
1350	EmuFeat.fVmxExitSaveEferMsr = 1;
1351	EmuFeat.fVmxExitLoadEferMsr = 1;
1352	EmuFeat.fVmxSavePreemptTimer = 0;
1353	EmuFeat.fVmxExitStoreEferLma = 1;
1354	EmuFeat.fVmxVmwriteAll = 0;
1355	EmuFeat.fVmxEntryInjectSoftInt = 0;
1356
1357	/*
1358	* Explode guest features.
1359	*
1360	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1361	* by the hardware, hence we merge our emulated features with the host features below.
1362	*/
1363	bool const fHostSupportsVmx = pHostFeat->fVmx;
1364	AssertLogRelReturnVoid(!fHostSupportsVmx \|\| HMIsVmxSupported(pVM));
1365	PCCPUMFEATURES pBaseFeat = fHostSupportsVmx ? pHostFeat : &EmuFeat;
1366	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1367	pGuestFeat->fVmx = (pBaseFeat->fVmx & EmuFeat.fVmx );
1368	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1369	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1370	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1371	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1372	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1373	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1374	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1375	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1376	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1377	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1378	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1379	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1380	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1381	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1382	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1383	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1384	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1385	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1386	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1387	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1388	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1389	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1390	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1391	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1392	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1393	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1394	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1395	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1396	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1397	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1398	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1399	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1400	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1401	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1402	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1403	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1404	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1405	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1406	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1407	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1408	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1409	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1410	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1411	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1412	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1413	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1414	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1415	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1416	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1417	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1418	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1419	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1420	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1421	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1422	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1423	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1424	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1425	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1426	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1427	pGuestFeat->fVmxExitStoreEferLma = (pBaseFeat->fVmxExitStoreEferLma & EmuFeat.fVmxExitStoreEferLma );
1428	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1429	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1430
1431	/* Paranoia. */
1432	if (!pGuestFeat->fVmxSecondaryExecCtls)
1433	{
1434	Assert(!pGuestFeat->fVmxVirtApicAccess);
1435	Assert(!pGuestFeat->fVmxEpt);
1436	Assert(!pGuestFeat->fVmxDescTableExit);
1437	Assert(!pGuestFeat->fVmxRdtscp);
1438	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1439	Assert(!pGuestFeat->fVmxVpid);
1440	Assert(!pGuestFeat->fVmxWbinvdExit);
1441	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1442	Assert(!pGuestFeat->fVmxApicRegVirt);
1443	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1444	Assert(!pGuestFeat->fVmxPauseLoopExit);
1445	Assert(!pGuestFeat->fVmxRdrandExit);
1446	Assert(!pGuestFeat->fVmxInvpcid);
1447	Assert(!pGuestFeat->fVmxVmFunc);
1448	Assert(!pGuestFeat->fVmxVmcsShadowing);
1449	Assert(!pGuestFeat->fVmxRdseedExit);
1450	Assert(!pGuestFeat->fVmxPml);
1451	Assert(!pGuestFeat->fVmxEptXcptVe);
1452	Assert(!pGuestFeat->fVmxXsavesXrstors);
1453	Assert(!pGuestFeat->fVmxUseTscScaling);
1454	}
1455	}
1456
1457
1458	/**
1459	* Initializes the CPUM.
1460	*
1461	* @returns VBox status code.
1462	* @param pVM The cross context VM structure.
1463	*/
1464	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1465	{
1466	LogFlow(("CPUMR3Init\n"));
1467
1468	/*
1469	* Assert alignment, sizes and tables.
1470	*/
1471	AssertCompileMemberAlignment(VM, cpum.s, 32);
1472	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1473	AssertCompileSizeAlignment(CPUMCTX, 64);
1474	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1475	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1476	AssertCompileMemberAlignment(VM, cpum, 64);
1477	AssertCompileMemberAlignment(VM, aCpus, 64);
1478	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1479	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
1480	#ifdef VBOX_STRICT
1481	int rc2 = cpumR3MsrStrictInitChecks();
1482	AssertRCReturn(rc2, rc2);
1483	#endif
1484
1485	/*
1486	* Initialize offsets.
1487	*/
1488
1489	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
1490	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
1491	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
1492
1493
1494	/* Calculate the offset from CPUMCPU to CPUM. */
1495	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1496	{
1497	PVMCPU pVCpu = &pVM->aCpus[i];
1498
1499	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
1500	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
1501	}
1502
1503	/*
1504	* Gather info about the host CPU.
1505	*/
1506	if (!ASMHasCpuId())
1507	{
1508	Log(("The CPU doesn't support CPUID!\n"));
1509	return VERR_UNSUPPORTED_CPU;
1510	}
1511
1512	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1513
1514	PCPUMCPUIDLEAF paLeaves;
1515	uint32_t cLeaves;
1516	int rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1517	AssertLogRelRCReturn(rc, rc);
1518
1519	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &pVM->cpum.s.HostFeatures);
1520	RTMemFree(paLeaves);
1521	AssertLogRelRCReturn(rc, rc);
1522	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1523
1524	/*
1525	* Check that the CPU supports the minimum features we require.
1526	*/
1527	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
1528	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
1529	if (!pVM->cpum.s.HostFeatures.fMmx)
1530	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
1531	if (!pVM->cpum.s.HostFeatures.fTsc)
1532	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
1533
1534	/*
1535	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
1536	*/
1537	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
1538	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
1539
1540	/*
1541	* Figure out which XSAVE/XRSTOR features are available on the host.
1542	*/
1543	uint64_t fXcr0Host = 0;
1544	uint64_t fXStateHostMask = 0;
1545	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
1546	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
1547	{
1548	fXStateHostMask = fXcr0Host = ASMGetXcr0();
1549	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
1550	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
1551	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
1552	}
1553	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
1554	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
1555	fXStateHostMask = 0;
1556	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1557	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1558
1559	/*
1560	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
1561	*/
1562	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1563	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1564	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
1565
1566	uint8_t *pbXStates;
1567	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
1568	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
1569	AssertLogRelRCReturn(rc, rc);
1570
1571	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1572	{
1573	PVMCPU pVCpu = &pVM->aCpus[i];
1574
1575	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1576	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1577	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1578	pbXStates += cbMaxXState;
1579
1580	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1581	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1582	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1583	pbXStates += cbMaxXState;
1584
1585	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
1586	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
1587	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
1588	pbXStates += cbMaxXState;
1589
1590	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
1591	}
1592
1593	/*
1594	* Register saved state data item.
1595	*/
1596	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
1597	NULL, cpumR3LiveExec, NULL,
1598	NULL, cpumR3SaveExec, NULL,
1599	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1600	if (RT_FAILURE(rc))
1601	return rc;
1602
1603	/*
1604	* Register info handlers and registers with the debugger facility.
1605	*/
1606	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
1607	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
1608	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
1609	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
1610	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
1611	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
1612	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
1613	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
1614	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
1615	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
1616	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
1617	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
1618	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
1619	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
1620	&cpumR3InfoVmxFeatures);
1621
1622	rc = cpumR3DbgInit(pVM);
1623	if (RT_FAILURE(rc))
1624	return rc;
1625
1626	/*
1627	* Check if we need to workaround partial/leaky FPU handling.
1628	*/
1629	cpumR3CheckLeakyFpu(pVM);
1630
1631	/*
1632	* Initialize the Guest CPUID and MSR states.
1633	*/
1634	rc = cpumR3InitCpuIdAndMsrs(pVM);
1635	if (RT_FAILURE(rc))
1636	return rc;
1637
1638	/*
1639	* Allocate memory required by the guest hardware virtualization state.
1640	*/
1641	if (pVM->cpum.ro.GuestFeatures.fVmx)
1642	rc = cpumR3AllocVmxHwVirtState(pVM);
1643	else if (pVM->cpum.ro.GuestFeatures.fSvm)
1644	rc = cpumR3AllocSvmHwVirtState(pVM);
1645	else
1646	Assert(pVM->aCpus[0].cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
1647	if (RT_FAILURE(rc))
1648	return rc;
1649
1650	/*
1651	* Initialize guest hardware virtualization state.
1652	*/
1653	CPUMHWVIRT const enmHwvirt = pVM->aCpus[0].cpum.s.Guest.hwvirt.enmHwvirt;
1654	if (enmHwvirt == CPUMHWVIRT_VMX)
1655	{
1656	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1657	cpumR3InitVmxHwVirtState(&pVM->aCpus[i]);
1658	}
1659	else if (enmHwvirt == CPUMHWVIRT_SVM)
1660	{
1661	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1662	cpumR3InitSvmHwVirtState(&pVM->aCpus[i]);
1663	}
1664
1665	/*
1666	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
1667	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
1668	* of processors from (cpuid(4).eax >> 26) + 1.
1669	*
1670	* Note: this code is obsolete, but let's keep it here for reference.
1671	* Purpose is valid when we artificially cap the max std id to less than 4.
1672	*
1673	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
1674	* after VMINITCOMPLETED_HM.
1675	*/
1676	if (VM_IS_RAW_MODE_ENABLED(pVM))
1677	{
1678	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
1679	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
1680	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
1681	}
1682
1683	CPUMR3Reset(pVM);
1684	return VINF_SUCCESS;
1685	}
1686
1687
1688	/**
1689	* Applies relocations to data and code managed by this
1690	* component. This function will be called at init and
1691	* whenever the VMM need to relocate it self inside the GC.
1692	*
1693	* The CPUM will update the addresses used by the switcher.
1694	*
1695	* @param pVM The cross context VM structure.
1696	*/
1697	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
1698	{
1699	LogFlow(("CPUMR3Relocate\n"));
1700
1701	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
1702	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
1703
1704	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1705	{
1706	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1707	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
1708	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
1709	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
1710
1711	/* Recheck the guest DRx values in raw-mode. */
1712	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
1713	}
1714	}
1715
1716
1717	/**
1718	* Terminates the CPUM.
1719	*
1720	* Termination means cleaning up and freeing all resources,
1721	* the VM it self is at this point powered off or suspended.
1722	*
1723	* @returns VBox status code.
1724	* @param pVM The cross context VM structure.
1725	*/
1726	VMMR3DECL(int) CPUMR3Term(PVM pVM)
1727	{
1728	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1729	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1730	{
1731	PVMCPU pVCpu = &pVM->aCpus[i];
1732	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1733
1734	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
1735	pVCpu->cpum.s.uMagic = 0;
1736	pCtx->dr[5] = 0;
1737	}
1738	#endif
1739
1740	if (pVM->cpum.ro.GuestFeatures.fSvm)
1741	cpumR3FreeVmxHwVirtState(pVM);
1742	else if (pVM->cpum.ro.GuestFeatures.fSvm)
1743	cpumR3FreeSvmHwVirtState(pVM);
1744	return VINF_SUCCESS;
1745	}
1746
1747
1748	/**
1749	* Resets a virtual CPU.
1750	*
1751	* Used by CPUMR3Reset and CPU hot plugging.
1752	*
1753	* @param pVM The cross context VM structure.
1754	* @param pVCpu The cross context virtual CPU structure of the CPU that is
1755	* being reset. This may differ from the current EMT.
1756	*/
1757	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
1758	{
1759	/** @todo anything different for VCPU > 0? */
1760	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1761
1762	/*
1763	* Initialize everything to ZERO first.
1764	*/
1765	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
1766
1767	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
1768	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
1769	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
1770
1771	pVCpu->cpum.s.fUseFlags = fUseFlags;
1772
1773	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
1774	pCtx->eip = 0x0000fff0;
1775	pCtx->edx = 0x00000600; /* P6 processor */
1776	pCtx->eflags.Bits.u1Reserved0 = 1;
1777
1778	pCtx->cs.Sel = 0xf000;
1779	pCtx->cs.ValidSel = 0xf000;
1780	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
1781	pCtx->cs.u64Base = UINT64_C(0xffff0000);
1782	pCtx->cs.u32Limit = 0x0000ffff;
1783	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
1784	pCtx->cs.Attr.n.u1Present = 1;
1785	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
1786
1787	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
1788	pCtx->ds.u32Limit = 0x0000ffff;
1789	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
1790	pCtx->ds.Attr.n.u1Present = 1;
1791	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1792
1793	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
1794	pCtx->es.u32Limit = 0x0000ffff;
1795	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
1796	pCtx->es.Attr.n.u1Present = 1;
1797	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1798
1799	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
1800	pCtx->fs.u32Limit = 0x0000ffff;
1801	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
1802	pCtx->fs.Attr.n.u1Present = 1;
1803	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1804
1805	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
1806	pCtx->gs.u32Limit = 0x0000ffff;
1807	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
1808	pCtx->gs.Attr.n.u1Present = 1;
1809	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1810
1811	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
1812	pCtx->ss.u32Limit = 0x0000ffff;
1813	pCtx->ss.Attr.n.u1Present = 1;
1814	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
1815	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
1816
1817	pCtx->idtr.cbIdt = 0xffff;
1818	pCtx->gdtr.cbGdt = 0xffff;
1819
1820	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
1821	pCtx->ldtr.u32Limit = 0xffff;
1822	pCtx->ldtr.Attr.n.u1Present = 1;
1823	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
1824
1825	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
1826	pCtx->tr.u32Limit = 0xffff;
1827	pCtx->tr.Attr.n.u1Present = 1;
1828	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
1829
1830	pCtx->dr[6] = X86_DR6_INIT_VAL;
1831	pCtx->dr[7] = X86_DR7_INIT_VAL;
1832
1833	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
1834	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
1835	pFpuCtx->FCW = 0x37f;
1836
1837	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
1838	IA-32 Processor States Following Power-up, Reset, or INIT */
1839	pFpuCtx->MXCSR = 0x1F80;
1840	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
1841
1842	pCtx->aXcr[0] = XSAVE_C_X87;
1843	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
1844	{
1845	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
1846	as we don't know what happened before. (Bother optimize later?) */
1847	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
1848	}
1849
1850	/*
1851	* MSRs.
1852	*/
1853	/* Init PAT MSR */
1854	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
1855
1856	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
1857	* The Intel docs don't mention it. */
1858	Assert(!pCtx->msrEFER);
1859
1860	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
1861	is supposed to be here, just trying provide useful/sensible values. */
1862	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
1863	if (pRange)
1864	{
1865	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1866	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
1867	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
1868	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
1869	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
1870	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
1871	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
1872	}
1873
1874	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
1875
1876	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
1877	* called from each EMT while we're getting called by CPUMR3Reset()
1878	* iteratively on the same thread. Fix later. */
1879	#if 0 /** @todo r=bird: This we will do in TM, not here. */
1880	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
1881	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
1882	#endif
1883
1884
1885	/* C-state control. Guesses. */
1886	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
1887	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
1888	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
1889	* functionality. The default value must be different due to incompatible write mask.
1890	*/
1891	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
1892	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
1893	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
1894	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
1895
1896	/*
1897	* Hardware virtualization state.
1898	*/
1899	pCtx->hwvirt.fGif = true;
1900	Assert(!pVM->cpum.ro.GuestFeatures.fVmx \|\| !pVM->cpum.ro.GuestFeatures.fSvm); /* Paranoia. */
1901	if (pVM->cpum.ro.GuestFeatures.fVmx)
1902	cpumR3InitVmxHwVirtState(pVCpu);
1903	else if (pVM->cpum.ro.GuestFeatures.fSvm)
1904	cpumR3InitSvmHwVirtState(pVCpu);
1905	}
1906
1907
1908	/**
1909	* Resets the CPU.
1910	*
1911	* @returns VINF_SUCCESS.
1912	* @param pVM The cross context VM structure.
1913	*/
1914	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
1915	{
1916	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1917	{
1918	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
1919
1920	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1921	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
1922
1923	/* Magic marker for searching in crash dumps. */
1924	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
1925	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1926	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
1927	#endif
1928	}
1929	}
1930
1931
1932
1933
1934	/**
1935	* Pass 0 live exec callback.
1936	*
1937	* @returns VINF_SSM_DONT_CALL_AGAIN.
1938	* @param pVM The cross context VM structure.
1939	* @param pSSM The saved state handle.
1940	* @param uPass The pass (0).
1941	*/
1942	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
1943	{
1944	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
1945	cpumR3SaveCpuId(pVM, pSSM);
1946	return VINF_SSM_DONT_CALL_AGAIN;
1947	}
1948
1949
1950	/**
1951	* Execute state save operation.
1952	*
1953	* @returns VBox status code.
1954	* @param pVM The cross context VM structure.
1955	* @param pSSM SSM operation handle.
1956	*/
1957	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
1958	{
1959	/*
1960	* Save.
1961	*/
1962	SSMR3PutU32(pSSM, pVM->cCpus);
1963	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
1964	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1965	{
1966	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1967
1968	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
1969
1970	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
1971	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
1972	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
1973	if (pGstCtx->fXStateMask != 0)
1974	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
1975	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
1976	{
1977	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
1978	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
1979	}
1980	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
1981	{
1982	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
1983	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
1984	}
1985	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
1986	{
1987	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
1988	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
1989	}
1990	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
1991	{
1992	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
1993	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
1994	}
1995	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
1996	{
1997	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
1998	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
1999	}
2000	if (pVM->cpum.ro.GuestFeatures.fSvm)
2001	{
2002	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2003	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2004	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2005	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2006	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2007	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2008	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2009	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2010	g_aSvmHwvirtHostState, NULL /* pvUser */);
2011	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2012	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2013	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2014	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2015	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2016	}
2017	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2018	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2019	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2020	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2021	}
2022
2023	cpumR3SaveCpuId(pVM, pSSM);
2024	return VINF_SUCCESS;
2025	}
2026
2027
2028	/**
2029	* @callback_method_impl{FNSSMINTLOADPREP}
2030	*/
2031	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2032	{
2033	NOREF(pSSM);
2034	pVM->cpum.s.fPendingRestore = true;
2035	return VINF_SUCCESS;
2036	}
2037
2038
2039	/**
2040	* @callback_method_impl{FNSSMINTLOADEXEC}
2041	*/
2042	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2043	{
2044	int rc; /* Only for AssertRCReturn use. */
2045
2046	/*
2047	* Validate version.
2048	*/
2049	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2050	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2051	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2052	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2053	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2054	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2055	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2056	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2057	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2058	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2059	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2060	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2061	{
2062	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2063	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2064	}
2065
2066	if (uPass == SSM_PASS_FINAL)
2067	{
2068	/*
2069	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2070	* really old SSM file versions.)
2071	*/
2072	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2073	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2074	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2075	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2076
2077	/*
2078	* Figure x86 and ctx field definitions to use for older states.
2079	*/
2080	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2081	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2082	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2083	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2084	{
2085	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2086	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2087	}
2088	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2089	{
2090	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2091	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2092	}
2093
2094	/*
2095	* The hyper state used to preceed the CPU count. Starting with
2096	* XSAVE it was moved down till after we've got the count.
2097	*/
2098	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2099	{
2100	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2101	{
2102	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2103	X86FXSTATE Ign;
2104	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2105	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2106	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2107	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
2108	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2109	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2110	pVCpu->cpum.s.Hyper.rsp = uRSP;
2111	}
2112	}
2113
2114	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2115	{
2116	uint32_t cCpus;
2117	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2118	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2119	VERR_SSM_UNEXPECTED_DATA);
2120	}
2121	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2122	\|\| pVM->cCpus == 1,
2123	("cCpus=%u\n", pVM->cCpus),
2124	VERR_SSM_UNEXPECTED_DATA);
2125
2126	uint32_t cbMsrs = 0;
2127	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2128	{
2129	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2130	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2131	VERR_SSM_UNEXPECTED_DATA);
2132	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2133	VERR_SSM_UNEXPECTED_DATA);
2134	}
2135
2136	/*
2137	* Do the per-CPU restoring.
2138	*/
2139	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2140	{
2141	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2142	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2143
2144	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2145	{
2146	/*
2147	* The XSAVE saved state layout moved the hyper state down here.
2148	*/
2149	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2150	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2151	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2152	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2153	pVCpu->cpum.s.Hyper.rsp = uRSP;
2154	AssertRCReturn(rc, rc);
2155
2156	/*
2157	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2158	*/
2159	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2160	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2161	AssertRCReturn(rc, rc);
2162
2163	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2164	if (pGstCtx->fXStateMask != 0)
2165	{
2166	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2167	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2168	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2169	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2170	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2171	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2172	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2173	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2174	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2175	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2176	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2177	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2178	}
2179
2180	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2181	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2182	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2183	{
2184	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2185	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2186	VERR_CPUM_INVALID_XCR0);
2187	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2188	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2189	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2190	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2191	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2192	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2193	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2194	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2195	}
2196
2197	/* Check that the XCR1 is zero, as we don't implement it yet. */
2198	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2199
2200	/*
2201	* Restore the individual extended state components we support.
2202	*/
2203	if (pGstCtx->fXStateMask != 0)
2204	{
2205	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2206	0, g_aCpumXSaveHdrFields, NULL);
2207	AssertRCReturn(rc, rc);
2208	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2209	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2210	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2211	VERR_CPUM_INVALID_XSAVE_HDR);
2212	}
2213	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2214	{
2215	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2216	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2217	}
2218	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2219	{
2220	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2221	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2222	}
2223	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2224	{
2225	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2226	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2227	}
2228	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2229	{
2230	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2231	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2232	}
2233	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2234	{
2235	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2236	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2237	}
2238	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2239	{
2240	if (pVM->cpum.ro.GuestFeatures.fSvm)
2241	{
2242	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2243	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2244	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2245	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2246	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2247	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2248	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2249	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2250	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2251	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2252	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2253	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2254	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2255	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2256	}
2257	}
2258	}
2259	else
2260	{
2261	/*
2262	* Pre XSAVE saved state.
2263	*/
2264	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2265	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2266	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2267	}
2268
2269	/*
2270	* Restore a couple of flags and the MSRs.
2271	*/
2272	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2273	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2274
2275	rc = VINF_SUCCESS;
2276	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2277	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2278	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2279	{
2280	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2281	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2282	}
2283	AssertRCReturn(rc, rc);
2284
2285	/* REM and other may have cleared must-be-one fields in DR6 and
2286	DR7, fix these. */
2287	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2288	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2289	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2290	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2291	}
2292
2293	/* Older states does not have the internal selector register flags
2294	and valid selector value. Supply those. */
2295	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2296	{
2297	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2298	{
2299	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2300	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2301	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2302	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2303	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2304	if (fValid)
2305	{
2306	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2307	{
2308	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2309	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2310	}
2311
2312	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2313	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2314	}
2315	else
2316	{
2317	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2318	{
2319	paSelReg[iSelReg].fFlags = 0;
2320	paSelReg[iSelReg].ValidSel = 0;
2321	}
2322
2323	/* This might not be 104% correct, but I think it's close
2324	enough for all practical purposes... (REM always loaded
2325	LDTR registers.) */
2326	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2327	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2328	}
2329	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2330	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2331	}
2332	}
2333
2334	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2335	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2336	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2337	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2338	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2339
2340	/*
2341	* A quick sanity check.
2342	*/
2343	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2344	{
2345	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2346	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2347	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2348	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2349	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2350	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2351	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2352	}
2353	}
2354
2355	pVM->cpum.s.fPendingRestore = false;
2356
2357	/*
2358	* Guest CPUIDs.
2359	*/
2360	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2361	return cpumR3LoadCpuId(pVM, pSSM, uVersion);
2362	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2363	}
2364
2365
2366	/**
2367	* @callback_method_impl{FNSSMINTLOADDONE}
2368	*/
2369	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2370	{
2371	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2372	return VINF_SUCCESS;
2373
2374	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2375	if (pVM->cpum.s.fPendingRestore)
2376	{
2377	LogRel(("CPUM: Missing state!\n"));
2378	return VERR_INTERNAL_ERROR_2;
2379	}
2380
2381	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2382	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2383	{
2384	PVMCPU pVCpu = &pVM->aCpus[idCpu];
2385
2386	/* Notify PGM of the NXE states in case they've changed. */
2387	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2388
2389	/* During init. this is done in CPUMR3InitCompleted(). */
2390	if (fSupportsLongMode)
2391	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2392	}
2393	return VINF_SUCCESS;
2394	}
2395
2396
2397	/**
2398	* Checks if the CPUM state restore is still pending.
2399	*
2400	* @returns true / false.
2401	* @param pVM The cross context VM structure.
2402	*/
2403	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2404	{
2405	return pVM->cpum.s.fPendingRestore;
2406	}
2407
2408
2409	/**
2410	* Formats the EFLAGS value into mnemonics.
2411	*
2412	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2413	* @param efl The EFLAGS value.
2414	*/
2415	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2416	{
2417	/*
2418	* Format the flags.
2419	*/
2420	static const struct
2421	{
2422	const char pszSet; const char pszClear; uint32_t fFlag;
2423	} s_aFlags[] =
2424	{
2425	{ "vip",NULL, X86_EFL_VIP },
2426	{ "vif",NULL, X86_EFL_VIF },
2427	{ "ac", NULL, X86_EFL_AC },
2428	{ "vm", NULL, X86_EFL_VM },
2429	{ "rf", NULL, X86_EFL_RF },
2430	{ "nt", NULL, X86_EFL_NT },
2431	{ "ov", "nv", X86_EFL_OF },
2432	{ "dn", "up", X86_EFL_DF },
2433	{ "ei", "di", X86_EFL_IF },
2434	{ "tf", NULL, X86_EFL_TF },
2435	{ "nt", "pl", X86_EFL_SF },
2436	{ "nz", "zr", X86_EFL_ZF },
2437	{ "ac", "na", X86_EFL_AF },
2438	{ "po", "pe", X86_EFL_PF },
2439	{ "cy", "nc", X86_EFL_CF },
2440	};
2441	char *psz = pszEFlags;
2442	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2443	{
2444	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2445	if (pszAdd)
2446	{
2447	strcpy(psz, pszAdd);
2448	psz += strlen(pszAdd);
2449	*psz++ = ' ';
2450	}
2451	}
2452	psz[-1] = '\0';
2453	}
2454
2455
2456	/**
2457	* Formats a full register dump.
2458	*
2459	* @param pVM The cross context VM structure.
2460	* @param pCtx The context to format.
2461	* @param pCtxCore The context core to format.
2462	* @param pHlp Output functions.
2463	* @param enmType The dump type.
2464	* @param pszPrefix Register name prefix.
2465	*/
2466	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2467	const char *pszPrefix)
2468	{
2469	NOREF(pVM);
2470
2471	/*
2472	* Format the EFLAGS.
2473	*/
2474	uint32_t efl = pCtxCore->eflags.u32;
2475	char szEFlags[80];
2476	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2477
2478	/*
2479	* Format the registers.
2480	*/
2481	switch (enmType)
2482	{
2483	case CPUMDUMPTYPE_TERSE:
2484	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2485	pHlp->pfnPrintf(pHlp,
2486	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2487	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2488	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2489	"%sr14=%016RX64 %sr15=%016RX64\n"
2490	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2491	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2492	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2493	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2494	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2495	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2496	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2497	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2498	else
2499	pHlp->pfnPrintf(pHlp,
2500	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2501	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2502	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2503	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2504	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2505	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2506	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
2507	break;
2508
2509	case CPUMDUMPTYPE_DEFAULT:
2510	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2511	pHlp->pfnPrintf(pHlp,
2512	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2513	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2514	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2515	"%sr14=%016RX64 %sr15=%016RX64\n"
2516	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2517	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2518	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
2519	,
2520	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2521	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2522	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2523	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2524	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2525	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2526	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2527	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2528	else
2529	pHlp->pfnPrintf(pHlp,
2530	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2531	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2532	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
2533	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
2534	,
2535	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2536	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2537	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2538	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
2539	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2540	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
2541	break;
2542
2543	case CPUMDUMPTYPE_VERBOSE:
2544	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2545	pHlp->pfnPrintf(pHlp,
2546	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2547	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2548	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2549	"%sr14=%016RX64 %sr15=%016RX64\n"
2550	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2551	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2552	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2553	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2554	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2555	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2556	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
2557	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
2558	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
2559	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
2560	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2561	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2562	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2563	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
2564	,
2565	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2566	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2567	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2568	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2569	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
2570	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
2571	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
2572	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
2573	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
2574	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
2575	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2576	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2577	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2578	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2579	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2580	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2581	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2582	else
2583	pHlp->pfnPrintf(pHlp,
2584	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
2585	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
2586	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
2587	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
2588	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
2589	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
2590	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
2591	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
2592	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
2593	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2594	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
2595	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
2596	,
2597	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
2598	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2599	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
2600	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
2601	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
2602	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
2603	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
2604	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
2605	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
2606	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
2607	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
2608	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
2609
2610	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
2611	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
2612	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
2613	if (pCtx->CTX_SUFF(pXState))
2614	{
2615	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
2616	pHlp->pfnPrintf(pHlp,
2617	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
2618	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
2619	,
2620	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
2621	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
2622	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
2623	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
2624	);
2625	/*
2626	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
2627	* not (FP)R0-7 as Intel SDM suggests.
2628	*/
2629	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
2630	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
2631	{
2632	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
2633	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
2634	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
2635	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
2636	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
2637	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
2638	iExponent -= 16383; /* subtract bias */
2639	/** @todo This isn't entirenly correct and needs more work! */
2640	pHlp->pfnPrintf(pHlp,
2641	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
2642	pszPrefix, iST, pszPrefix, iFPR,
2643	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
2644	uTag, chSign, iInteger, u64Fraction, iExponent);
2645	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
2646	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
2647	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
2648	else
2649	pHlp->pfnPrintf(pHlp, "\n");
2650	}
2651
2652	/* XMM/YMM/ZMM registers. */
2653	if (pCtx->fXStateMask & XSAVE_C_YMM)
2654	{
2655	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2656	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
2657	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2658	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2659	pszPrefix, i, i < 10 ? " " : "",
2660	pYmmHiCtx->aYmmHi[i].au32[3],
2661	pYmmHiCtx->aYmmHi[i].au32[2],
2662	pYmmHiCtx->aYmmHi[i].au32[1],
2663	pYmmHiCtx->aYmmHi[i].au32[0],
2664	pFpuCtx->aXMM[i].au32[3],
2665	pFpuCtx->aXMM[i].au32[2],
2666	pFpuCtx->aXMM[i].au32[1],
2667	pFpuCtx->aXMM[i].au32[0]);
2668	else
2669	{
2670	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2671	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2672	pHlp->pfnPrintf(pHlp,
2673	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2674	pszPrefix, i, i < 10 ? " " : "",
2675	pZmmHi256->aHi256Regs[i].au32[7],
2676	pZmmHi256->aHi256Regs[i].au32[6],
2677	pZmmHi256->aHi256Regs[i].au32[5],
2678	pZmmHi256->aHi256Regs[i].au32[4],
2679	pZmmHi256->aHi256Regs[i].au32[3],
2680	pZmmHi256->aHi256Regs[i].au32[2],
2681	pZmmHi256->aHi256Regs[i].au32[1],
2682	pZmmHi256->aHi256Regs[i].au32[0],
2683	pYmmHiCtx->aYmmHi[i].au32[3],
2684	pYmmHiCtx->aYmmHi[i].au32[2],
2685	pYmmHiCtx->aYmmHi[i].au32[1],
2686	pYmmHiCtx->aYmmHi[i].au32[0],
2687	pFpuCtx->aXMM[i].au32[3],
2688	pFpuCtx->aXMM[i].au32[2],
2689	pFpuCtx->aXMM[i].au32[1],
2690	pFpuCtx->aXMM[i].au32[0]);
2691
2692	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2693	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
2694	pHlp->pfnPrintf(pHlp,
2695	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
2696	pszPrefix, i + 16,
2697	pZmm16Hi->aRegs[i].au32[15],
2698	pZmm16Hi->aRegs[i].au32[14],
2699	pZmm16Hi->aRegs[i].au32[13],
2700	pZmm16Hi->aRegs[i].au32[12],
2701	pZmm16Hi->aRegs[i].au32[11],
2702	pZmm16Hi->aRegs[i].au32[10],
2703	pZmm16Hi->aRegs[i].au32[9],
2704	pZmm16Hi->aRegs[i].au32[8],
2705	pZmm16Hi->aRegs[i].au32[7],
2706	pZmm16Hi->aRegs[i].au32[6],
2707	pZmm16Hi->aRegs[i].au32[5],
2708	pZmm16Hi->aRegs[i].au32[4],
2709	pZmm16Hi->aRegs[i].au32[3],
2710	pZmm16Hi->aRegs[i].au32[2],
2711	pZmm16Hi->aRegs[i].au32[1],
2712	pZmm16Hi->aRegs[i].au32[0]);
2713	}
2714	}
2715	else
2716	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
2717	pHlp->pfnPrintf(pHlp,
2718	i & 1
2719	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
2720	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
2721	pszPrefix, i, i < 10 ? " " : "",
2722	pFpuCtx->aXMM[i].au32[3],
2723	pFpuCtx->aXMM[i].au32[2],
2724	pFpuCtx->aXMM[i].au32[1],
2725	pFpuCtx->aXMM[i].au32[0]);
2726
2727	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
2728	{
2729	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
2730	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
2731	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
2732	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
2733	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
2734	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
2735	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
2736	}
2737
2738	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
2739	{
2740	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2741	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
2742	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
2743	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
2744	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
2745	}
2746
2747	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
2748	{
2749	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2750	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
2751	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
2752	}
2753
2754	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
2755	if (pFpuCtx->au32RsrvdRest[i])
2756	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
2757	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
2758	}
2759
2760	pHlp->pfnPrintf(pHlp,
2761	"%sEFER =%016RX64\n"
2762	"%sPAT =%016RX64\n"
2763	"%sSTAR =%016RX64\n"
2764	"%sCSTAR =%016RX64\n"
2765	"%sLSTAR =%016RX64\n"
2766	"%sSFMASK =%016RX64\n"
2767	"%sKERNELGSBASE =%016RX64\n",
2768	pszPrefix, pCtx->msrEFER,
2769	pszPrefix, pCtx->msrPAT,
2770	pszPrefix, pCtx->msrSTAR,
2771	pszPrefix, pCtx->msrCSTAR,
2772	pszPrefix, pCtx->msrLSTAR,
2773	pszPrefix, pCtx->msrSFMASK,
2774	pszPrefix, pCtx->msrKERNELGSBASE);
2775	break;
2776	}
2777	}
2778
2779
2780	/**
2781	* Display all cpu states and any other cpum info.
2782	*
2783	* @param pVM The cross context VM structure.
2784	* @param pHlp The info helper functions.
2785	* @param pszArgs Arguments, ignored.
2786	*/
2787	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2788	{
2789	cpumR3InfoGuest(pVM, pHlp, pszArgs);
2790	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
2791	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
2792	cpumR3InfoHyper(pVM, pHlp, pszArgs);
2793	cpumR3InfoHost(pVM, pHlp, pszArgs);
2794	}
2795
2796
2797	/**
2798	* Parses the info argument.
2799	*
2800	* The argument starts with 'verbose', 'terse' or 'default' and then
2801	* continues with the comment string.
2802	*
2803	* @param pszArgs The pointer to the argument string.
2804	* @param penmType Where to store the dump type request.
2805	* @param ppszComment Where to store the pointer to the comment string.
2806	*/
2807	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
2808	{
2809	if (!pszArgs)
2810	{
2811	*penmType = CPUMDUMPTYPE_DEFAULT;
2812	*ppszComment = "";
2813	}
2814	else
2815	{
2816	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
2817	{
2818	pszArgs += 7;
2819	*penmType = CPUMDUMPTYPE_VERBOSE;
2820	}
2821	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
2822	{
2823	pszArgs += 5;
2824	*penmType = CPUMDUMPTYPE_TERSE;
2825	}
2826	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
2827	{
2828	pszArgs += 7;
2829	*penmType = CPUMDUMPTYPE_DEFAULT;
2830	}
2831	else
2832	*penmType = CPUMDUMPTYPE_DEFAULT;
2833	*ppszComment = RTStrStripL(pszArgs);
2834	}
2835	}
2836
2837
2838	/**
2839	* Display the guest cpu state.
2840	*
2841	* @param pVM The cross context VM structure.
2842	* @param pHlp The info helper functions.
2843	* @param pszArgs Arguments.
2844	*/
2845	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2846	{
2847	CPUMDUMPTYPE enmType;
2848	const char *pszComment;
2849	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
2850
2851	PVMCPU pVCpu = VMMGetCpu(pVM);
2852	if (!pVCpu)
2853	pVCpu = &pVM->aCpus[0];
2854
2855	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
2856
2857	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2858	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
2859	}
2860
2861
2862	/**
2863	* Displays an SVM VMCB control area.
2864	*
2865	* @param pHlp The info helper functions.
2866	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
2867	* @param pszPrefix Caller specified string prefix.
2868	*/
2869	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
2870	{
2871	AssertReturnVoid(pHlp);
2872	AssertReturnVoid(pVmcbCtrl);
2873
2874	pHlp->pfnPrintf(pHlp, "%su16InterceptRdCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
2875	pHlp->pfnPrintf(pHlp, "%su16InterceptWrCRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
2876	pHlp->pfnPrintf(pHlp, "%su16InterceptRdDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
2877	pHlp->pfnPrintf(pHlp, "%su16InterceptWrDRx = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
2878	pHlp->pfnPrintf(pHlp, "%su32InterceptXcpt = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
2879	pHlp->pfnPrintf(pHlp, "%su64InterceptCtrl = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
2880	pHlp->pfnPrintf(pHlp, "%su16PauseFilterThreshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
2881	pHlp->pfnPrintf(pHlp, "%su16PauseFilterCount = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
2882	pHlp->pfnPrintf(pHlp, "%su64IOPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
2883	pHlp->pfnPrintf(pHlp, "%su64MSRPMPhysAddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
2884	pHlp->pfnPrintf(pHlp, "%su64TSCOffset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
2885	pHlp->pfnPrintf(pHlp, "%sTLBCtrl\n", pszPrefix);
2886	pHlp->pfnPrintf(pHlp, "%s u32ASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
2887	pHlp->pfnPrintf(pHlp, "%s u8TLBFlush = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
2888	pHlp->pfnPrintf(pHlp, "%sIntCtrl\n", pszPrefix);
2889	pHlp->pfnPrintf(pHlp, "%s u8VTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
2890	pHlp->pfnPrintf(pHlp, "%s u1VIrqPending = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
2891	pHlp->pfnPrintf(pHlp, "%s u1VGif = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
2892	pHlp->pfnPrintf(pHlp, "%s u4VIntrPrio = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
2893	pHlp->pfnPrintf(pHlp, "%s u1IgnoreTPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
2894	pHlp->pfnPrintf(pHlp, "%s u1VIntrMasking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
2895	pHlp->pfnPrintf(pHlp, "%s u1VGifEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
2896	pHlp->pfnPrintf(pHlp, "%s u1AvicEnable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
2897	pHlp->pfnPrintf(pHlp, "%s u8VIntrVector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
2898	pHlp->pfnPrintf(pHlp, "%sIntShadow\n", pszPrefix);
2899	pHlp->pfnPrintf(pHlp, "%s u1IntShadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
2900	pHlp->pfnPrintf(pHlp, "%s u1GuestIntMask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
2901	pHlp->pfnPrintf(pHlp, "%su64ExitCode = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
2902	pHlp->pfnPrintf(pHlp, "%su64ExitInfo1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
2903	pHlp->pfnPrintf(pHlp, "%su64ExitInfo2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
2904	pHlp->pfnPrintf(pHlp, "%sExitIntInfo\n", pszPrefix);
2905	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
2906	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
2907	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
2908	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
2909	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
2910	pHlp->pfnPrintf(pHlp, "%sNestedPaging and SEV\n", pszPrefix);
2911	pHlp->pfnPrintf(pHlp, "%s u1NestedPaging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
2912	pHlp->pfnPrintf(pHlp, "%s u1Sev = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
2913	pHlp->pfnPrintf(pHlp, "%s u1SevEs = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
2914	pHlp->pfnPrintf(pHlp, "%sAvicBar\n", pszPrefix);
2915	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
2916	pHlp->pfnPrintf(pHlp, "%sEventInject\n", pszPrefix);
2917	pHlp->pfnPrintf(pHlp, "%s EventInject\n", pszPrefix);
2918	pHlp->pfnPrintf(pHlp, "%s u8Vector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
2919	pHlp->pfnPrintf(pHlp, "%s u3Type = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
2920	pHlp->pfnPrintf(pHlp, "%s u1ErrorCodeValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
2921	pHlp->pfnPrintf(pHlp, "%s u1Valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
2922	pHlp->pfnPrintf(pHlp, "%s u32ErrorCode = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
2923	pHlp->pfnPrintf(pHlp, "%su64NestedPagingCR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
2924	pHlp->pfnPrintf(pHlp, "%sLBR virtualization\n", pszPrefix);
2925	pHlp->pfnPrintf(pHlp, "%s u1LbrVirt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
2926	pHlp->pfnPrintf(pHlp, "%s u1VirtVmsaveVmload = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
2927	pHlp->pfnPrintf(pHlp, "%su32VmcbCleanBits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
2928	pHlp->pfnPrintf(pHlp, "%su64NextRIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
2929	pHlp->pfnPrintf(pHlp, "%scbInstrFetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
2930	pHlp->pfnPrintf(pHlp, "%sabInstr = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
2931	pHlp->pfnPrintf(pHlp, "%sAvicBackingPagePtr\n", pszPrefix);
2932	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
2933	pHlp->pfnPrintf(pHlp, "%sAvicLogicalTablePtr\n", pszPrefix);
2934	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
2935	pHlp->pfnPrintf(pHlp, "%sAvicPhysicalTablePtr\n", pszPrefix);
2936	pHlp->pfnPrintf(pHlp, "%s u8LastGuestCoreId = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
2937	pHlp->pfnPrintf(pHlp, "%s u40Addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
2938	}
2939
2940
2941	/**
2942	* Helper for dumping the SVM VMCB selector registers.
2943	*
2944	* @param pHlp The info helper functions.
2945	* @param pSel Pointer to the SVM selector register.
2946	* @param pszName Name of the selector.
2947	* @param pszPrefix Caller specified string prefix.
2948	*/
2949	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
2950	{
2951	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
2952	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
2953	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
2954	}
2955
2956
2957	/**
2958	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
2959	*
2960	* @param pHlp The info helper functions.
2961	* @param pXdtr Pointer to the descriptor table register.
2962	* @param pszName Name of the descriptor table register.
2963	* @param pszPrefix Caller specified string prefix.
2964	*/
2965	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
2966	{
2967	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
2968	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
2969	}
2970
2971
2972	/**
2973	* Displays an SVM VMCB state-save area.
2974	*
2975	* @param pHlp The info helper functions.
2976	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
2977	* @param pszPrefix Caller specified string prefix.
2978	*/
2979	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
2980	{
2981	AssertReturnVoid(pHlp);
2982	AssertReturnVoid(pVmcbStateSave);
2983
2984	char szEFlags[80];
2985	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
2986
2987	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
2988	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
2989	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
2990	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
2991	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
2992	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
2993	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
2994	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
2995	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
2996	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
2997	pHlp->pfnPrintf(pHlp, "%su8CPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
2998	pHlp->pfnPrintf(pHlp, "%su64EFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
2999	pHlp->pfnPrintf(pHlp, "%su64CR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3000	pHlp->pfnPrintf(pHlp, "%su64CR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3001	pHlp->pfnPrintf(pHlp, "%su64CR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3002	pHlp->pfnPrintf(pHlp, "%su64DR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3003	pHlp->pfnPrintf(pHlp, "%su64DR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3004	pHlp->pfnPrintf(pHlp, "%su64RFlags = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3005	pHlp->pfnPrintf(pHlp, "%su64RIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3006	pHlp->pfnPrintf(pHlp, "%su64RSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3007	pHlp->pfnPrintf(pHlp, "%su64RAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3008	pHlp->pfnPrintf(pHlp, "%su64STAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3009	pHlp->pfnPrintf(pHlp, "%su64LSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3010	pHlp->pfnPrintf(pHlp, "%su64CSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3011	pHlp->pfnPrintf(pHlp, "%su64SFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3012	pHlp->pfnPrintf(pHlp, "%su64KernelGSBase = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3013	pHlp->pfnPrintf(pHlp, "%su64SysEnterCS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3014	pHlp->pfnPrintf(pHlp, "%su64SysEnterEIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3015	pHlp->pfnPrintf(pHlp, "%su64SysEnterESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3016	pHlp->pfnPrintf(pHlp, "%su64CR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3017	pHlp->pfnPrintf(pHlp, "%su64PAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3018	pHlp->pfnPrintf(pHlp, "%su64DBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3019	pHlp->pfnPrintf(pHlp, "%su64BR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3020	pHlp->pfnPrintf(pHlp, "%su64BR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3021	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPFROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3022	pHlp->pfnPrintf(pHlp, "%su64LASTEXCPTO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3023	}
3024
3025
3026	/**
3027	* Display the guest's hardware-virtualization cpu state.
3028	*
3029	* @param pVM The cross context VM structure.
3030	* @param pHlp The info helper functions.
3031	* @param pszArgs Arguments, ignored.
3032	*/
3033	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3034	{
3035	RT_NOREF(pszArgs);
3036
3037	PVMCPU pVCpu = VMMGetCpu(pVM);
3038	if (!pVCpu)
3039	pVCpu = &pVM->aCpus[0];
3040
3041	/*
3042	* Figure out what to dump.
3043	*
3044	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
3045	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
3046	* dump hwvirt. state when the guest CPU is executing a nested-guest.
3047	*/
3048	/** @todo perhaps make this configurable through pszArgs, depending on how much
3049	* noise we wish to accept when nested hwvirt. isn't used. */
3050	#define CPUMHWVIRTDUMP_NONE (0)
3051	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
3052	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
3053	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
3054	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
3055
3056	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3057	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
3058	bool const fSvm = pVM->cpum.ro.GuestFeatures.fSvm;
3059	bool const fVmx = pVM->cpum.ro.GuestFeatures.fVmx;
3060	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
3061	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
3062	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
3063	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
3064	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
3065
3066	/*
3067	* Dump it.
3068	*/
3069	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3070
3071	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
3072	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3073
3074	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
3075	":" : "");
3076	if (fDumpState & CPUMHWVIRTDUMP_SVM)
3077	{
3078	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
3079
3080	char szEFlags[80];
3081	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
3082	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
3083	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
3084	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
3085	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
3086	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
3087	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
3088	pHlp->pfnPrintf(pHlp, " HostState:\n");
3089	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
3090	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
3091	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
3092	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
3093	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
3094	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
3095	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
3096	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
3097	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
3098	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3099	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3100	pSel = &pCtx->hwvirt.svm.HostState.cs;
3101	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3102	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3103	pSel = &pCtx->hwvirt.svm.HostState.ss;
3104	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3105	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3106	pSel = &pCtx->hwvirt.svm.HostState.ds;
3107	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3108	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
3109	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
3110	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
3111	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
3112	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
3113	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
3114	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
3115	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
3116	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
3117	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
3118	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
3119	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
3120	}
3121
3122	if (fDumpState & CPUMHWVIRTDUMP_VMX)
3123	{
3124	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
3125	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
3126	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
3127	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMVmxGetDiagDesc(pCtx->hwvirt.vmx.enmDiag));
3128	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, HMVmxGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
3129	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
3130	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
3131	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
3132	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
3133
3134	/** @todo NSTVMX: Dump remaining/new fields. */
3135	}
3136
3137	#undef CPUMHWVIRTDUMP_NONE
3138	#undef CPUMHWVIRTDUMP_COMMON
3139	#undef CPUMHWVIRTDUMP_SVM
3140	#undef CPUMHWVIRTDUMP_VMX
3141	#undef CPUMHWVIRTDUMP_LAST
3142	#undef CPUMHWVIRTDUMP_ALL
3143	}
3144
3145	/**
3146	* Display the current guest instruction
3147	*
3148	* @param pVM The cross context VM structure.
3149	* @param pHlp The info helper functions.
3150	* @param pszArgs Arguments, ignored.
3151	*/
3152	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3153	{
3154	NOREF(pszArgs);
3155
3156	PVMCPU pVCpu = VMMGetCpu(pVM);
3157	if (!pVCpu)
3158	pVCpu = &pVM->aCpus[0];
3159
3160	char szInstruction[256];
3161	szInstruction[0] = '\0';
3162	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3163	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
3164	}
3165
3166
3167	/**
3168	* Display the hypervisor cpu state.
3169	*
3170	* @param pVM The cross context VM structure.
3171	* @param pHlp The info helper functions.
3172	* @param pszArgs Arguments, ignored.
3173	*/
3174	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3175	{
3176	PVMCPU pVCpu = VMMGetCpu(pVM);
3177	if (!pVCpu)
3178	pVCpu = &pVM->aCpus[0];
3179
3180	CPUMDUMPTYPE enmType;
3181	const char *pszComment;
3182	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3183	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3184	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
3185	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3186	}
3187
3188
3189	/**
3190	* Display the host cpu state.
3191	*
3192	* @param pVM The cross context VM structure.
3193	* @param pHlp The info helper functions.
3194	* @param pszArgs Arguments, ignored.
3195	*/
3196	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3197	{
3198	CPUMDUMPTYPE enmType;
3199	const char *pszComment;
3200	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3201	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3202
3203	PVMCPU pVCpu = VMMGetCpu(pVM);
3204	if (!pVCpu)
3205	pVCpu = &pVM->aCpus[0];
3206	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
3207
3208	/*
3209	* Format the EFLAGS.
3210	*/
3211	#if HC_ARCH_BITS == 32
3212	uint32_t efl = pCtx->eflags.u32;
3213	#else
3214	uint64_t efl = pCtx->rflags;
3215	#endif
3216	char szEFlags[80];
3217	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3218
3219	/*
3220	* Format the registers.
3221	*/
3222	#if HC_ARCH_BITS == 32
3223	pHlp->pfnPrintf(pHlp,
3224	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
3225	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
3226	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
3227	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
3228	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
3229	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3230	,
3231	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
3232	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
3233	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3234	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
3235	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
3236	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
3237	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3238	#else
3239	pHlp->pfnPrintf(pHlp,
3240	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3241	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3242	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3243	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3244	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
3245	"r14=%016RX64 r15=%016RX64\n"
3246	"iopl=%d %31s\n"
3247	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
3248	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
3249	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
3250	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
3251	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
3252	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
3253	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
3254	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
3255	,
3256	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
3257	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
3258	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
3259	/pCtx->r8, pCtx->r9,/ pCtx->r10,
3260	pCtx->r11, pCtx->r12, pCtx->r13,
3261	pCtx->r14, pCtx->r15,
3262	X86_EFL_GET_IOPL(efl), szEFlags,
3263	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
3264	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
3265	pCtx->cr4, pCtx->ldtr, pCtx->tr,
3266	pCtx->dr0, pCtx->dr1, pCtx->dr2,
3267	pCtx->dr3, pCtx->dr6, pCtx->dr7,
3268	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
3269	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
3270	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
3271	#endif
3272	}
3273
3274	/**
3275	* Structure used when disassembling and instructions in DBGF.
3276	* This is used so the reader function can get the stuff it needs.
3277	*/
3278	typedef struct CPUMDISASSTATE
3279	{
3280	/** Pointer to the CPU structure. */
3281	PDISCPUSTATE pCpu;
3282	/** Pointer to the VM. */
3283	PVM pVM;
3284	/** Pointer to the VMCPU. */
3285	PVMCPU pVCpu;
3286	/** Pointer to the first byte in the segment. */
3287	RTGCUINTPTR GCPtrSegBase;
3288	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
3289	RTGCUINTPTR GCPtrSegEnd;
3290	/** The size of the segment minus 1. */
3291	RTGCUINTPTR cbSegLimit;
3292	/** Pointer to the current page - R3 Ptr. */
3293	void const *pvPageR3;
3294	/** Pointer to the current page - GC Ptr. */
3295	RTGCPTR pvPageGC;
3296	/** The lock information that PGMPhysReleasePageMappingLock needs. */
3297	PGMPAGEMAPLOCK PageMapLock;
3298	/** Whether the PageMapLock is valid or not. */
3299	bool fLocked;
3300	/** 64 bits mode or not. */
3301	bool f64Bits;
3302	} CPUMDISASSTATE, *PCPUMDISASSTATE;
3303
3304
3305	/**
3306	* @callback_method_impl{FNDISREADBYTES}
3307	*/
3308	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
3309	{
3310	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
3311	for (;;)
3312	{
3313	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
3314
3315	/*
3316	* Need to update the page translation?
3317	*/
3318	if ( !pState->pvPageR3
3319	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
3320	{
3321	int rc = VINF_SUCCESS;
3322
3323	/* translate the address */
3324	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
3325	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
3326	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
3327	{
3328	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
3329	if (!pState->pvPageR3)
3330	rc = VERR_INVALID_POINTER;
3331	}
3332	else
3333	{
3334	/* Release mapping lock previously acquired. */
3335	if (pState->fLocked)
3336	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
3337	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
3338	pState->fLocked = RT_SUCCESS_NP(rc);
3339	}
3340	if (RT_FAILURE(rc))
3341	{
3342	pState->pvPageR3 = NULL;
3343	return rc;
3344	}
3345	}
3346
3347	/*
3348	* Check the segment limit.
3349	*/
3350	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
3351	return VERR_OUT_OF_SELECTOR_BOUNDS;
3352
3353	/*
3354	* Calc how much we can read.
3355	*/
3356	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
3357	if (!pState->f64Bits)
3358	{
3359	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
3360	if (cb > cbSeg && cbSeg)
3361	cb = cbSeg;
3362	}
3363	if (cb > cbMaxRead)
3364	cb = cbMaxRead;
3365
3366	/*
3367	* Read and advance or exit.
3368	*/
3369	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
3370	offInstr += (uint8_t)cb;
3371	if (cb >= cbMinRead)
3372	{
3373	pDis->cbCachedInstr = offInstr;
3374	return VINF_SUCCESS;
3375	}
3376	cbMinRead -= (uint8_t)cb;
3377	cbMaxRead -= (uint8_t)cb;
3378	}
3379	}
3380
3381
3382	/**
3383	* Disassemble an instruction and return the information in the provided structure.
3384	*
3385	* @returns VBox status code.
3386	* @param pVM The cross context VM structure.
3387	* @param pVCpu The cross context virtual CPU structure.
3388	* @param pCtx Pointer to the guest CPU context.
3389	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
3390	* @param pCpu Disassembly state.
3391	* @param pszPrefix String prefix for logging (debug only).
3392	*
3393	*/
3394	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
3395	const char *pszPrefix)
3396	{
3397	CPUMDISASSTATE State;
3398	int rc;
3399
3400	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
3401	State.pCpu = pCpu;
3402	State.pvPageGC = 0;
3403	State.pvPageR3 = NULL;
3404	State.pVM = pVM;
3405	State.pVCpu = pVCpu;
3406	State.fLocked = false;
3407	State.f64Bits = false;
3408
3409	/*
3410	* Get selector information.
3411	*/
3412	DISCPUMODE enmDisCpuMode;
3413	if ( (pCtx->cr0 & X86_CR0_PE)
3414	&& pCtx->eflags.Bits.u1VM == 0)
3415	{
3416	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3417	{
3418	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
3419	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
3420	# endif
3421	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
3422	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
3423	}
3424	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
3425	State.GCPtrSegBase = pCtx->cs.u64Base;
3426	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
3427	State.cbSegLimit = pCtx->cs.u32Limit;
3428	enmDisCpuMode = (State.f64Bits)
3429	? DISCPUMODE_64BIT
3430	: pCtx->cs.Attr.n.u1DefBig
3431	? DISCPUMODE_32BIT
3432	: DISCPUMODE_16BIT;
3433	}
3434	else
3435	{
3436	/* real or V86 mode */
3437	enmDisCpuMode = DISCPUMODE_16BIT;
3438	State.GCPtrSegBase = pCtx->cs.Sel * 16;
3439	State.GCPtrSegEnd = 0xFFFFFFFF;
3440	State.cbSegLimit = 0xFFFFFFFF;
3441	}
3442
3443	/*
3444	* Disassemble the instruction.
3445	*/
3446	uint32_t cbInstr;
3447	#ifndef LOG_ENABLED
3448	RT_NOREF_PV(pszPrefix);
3449	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
3450	if (RT_SUCCESS(rc))
3451	{
3452	#else
3453	char szOutput[160];
3454	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
3455	pCpu, &cbInstr, szOutput, sizeof(szOutput));
3456	if (RT_SUCCESS(rc))
3457	{
3458	/* log it */
3459	if (pszPrefix)
3460	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
3461	else
3462	Log(("%s", szOutput));
3463	#endif
3464	rc = VINF_SUCCESS;
3465	}
3466	else
3467	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
3468
3469	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
3470	if (State.fLocked)
3471	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
3472
3473	return rc;
3474	}
3475
3476
3477
3478	/**
3479	* API for controlling a few of the CPU features found in CR4.
3480	*
3481	* Currently only X86_CR4_TSD is accepted as input.
3482	*
3483	* @returns VBox status code.
3484	*
3485	* @param pVM The cross context VM structure.
3486	* @param fOr The CR4 OR mask.
3487	* @param fAnd The CR4 AND mask.
3488	*/
3489	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
3490	{
3491	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
3492	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
3493
3494	pVM->cpum.s.CR4.OrMask &= fAnd;
3495	pVM->cpum.s.CR4.OrMask \|= fOr;
3496
3497	return VINF_SUCCESS;
3498	}
3499
3500
3501	/**
3502	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
3503	*
3504	* Only REM should ever call this function!
3505	*
3506	* @returns The changed flags.
3507	* @param pVCpu The cross context virtual CPU structure.
3508	* @param puCpl Where to return the current privilege level (CPL).
3509	*/
3510	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
3511	{
3512	Assert(!pVCpu->cpum.s.fRawEntered);
3513	Assert(!pVCpu->cpum.s.fRemEntered);
3514
3515	/*
3516	* Get the CPL first.
3517	*/
3518	*puCpl = CPUMGetGuestCPL(pVCpu);
3519
3520	/*
3521	* Get and reset the flags.
3522	*/
3523	uint32_t fFlags = pVCpu->cpum.s.fChanged;
3524	pVCpu->cpum.s.fChanged = 0;
3525
3526	/** @todo change the switcher to use the fChanged flags. */
3527	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
3528	{
3529	fFlags \|= CPUM_CHANGED_FPU_REM;
3530	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
3531	}
3532
3533	pVCpu->cpum.s.fRemEntered = true;
3534	return fFlags;
3535	}
3536
3537
3538	/**
3539	* Leaves REM.
3540	*
3541	* @param pVCpu The cross context virtual CPU structure.
3542	* @param fNoOutOfSyncSels This is @c false if there are out of sync
3543	* registers.
3544	*/
3545	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
3546	{
3547	Assert(!pVCpu->cpum.s.fRawEntered);
3548	Assert(pVCpu->cpum.s.fRemEntered);
3549
3550	RT_NOREF_PV(fNoOutOfSyncSels);
3551
3552	pVCpu->cpum.s.fRemEntered = false;
3553	}
3554
3555
3556	/**
3557	* Called when the ring-3 init phase completes.
3558	*
3559	* @returns VBox status code.
3560	* @param pVM The cross context VM structure.
3561	* @param enmWhat Which init phase.
3562	*/
3563	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
3564	{
3565	switch (enmWhat)
3566	{
3567	case VMINITCOMPLETED_RING3:
3568	{
3569	/*
3570	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
3571	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
3572	*/
3573	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3574	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3575	{
3576	PVMCPU pVCpu = &pVM->aCpus[i];
3577	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
3578	if (fSupportsLongMode)
3579	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3580	}
3581
3582	cpumR3MsrRegStats(pVM);
3583	break;
3584	}
3585
3586	case VMINITCOMPLETED_HM:
3587	{
3588	/*
3589	* Currently, nested VMX/SVM both derives their guest VMX/SVM CPUID bit from the host
3590	* CPUID bit. This could be later changed if we need to support nested-VMX on CPUs
3591	* that are not capable of VMX.
3592	*/
3593	if (pVM->cpum.s.GuestFeatures.fVmx)
3594	{
3595	Assert( pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
3596	\|\| pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
3597	cpumR3InitVmxCpuFeatures(pVM);
3598	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
3599	}
3600
3601	if (pVM->cpum.s.GuestFeatures.fVmx)
3602	LogRel(("CPUM: Enabled guest VMX support\n"));
3603	else if (pVM->cpum.s.GuestFeatures.fSvm)
3604	LogRel(("CPUM: Enabled guest SVM support\n"));
3605	break;
3606	}
3607
3608	default:
3609	break;
3610	}
3611	return VINF_SUCCESS;
3612	}
3613
3614
3615	/**
3616	* Called when the ring-0 init phases completed.
3617	*
3618	* @param pVM The cross context VM structure.
3619	*/
3620	VMMR3DECL(void) CPUMR3LogCpuIds(PVM pVM)
3621	{
3622	/*
3623	* Log the cpuid.
3624	*/
3625	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
3626	RTCPUSET OnlineSet;
3627	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
3628	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
3629	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
3630	RTCPUID cCores = RTMpGetCoreCount();
3631	if (cCores)
3632	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
3633	LogRel(("*********************** CPUID dump **********************\n"));
3634	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
3635	LogRel(("\n"));
3636	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
3637	RTLogRelSetBuffering(fOldBuffered);
3638	LogRel(("****************** End of CPUID dump ********************\n"));
3639	}
3640

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 74517

Download in other formats: