CPUM.cpp@ 78327

Last change on this file since 78327 was 78220, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Hardware-assisted nested VT-x infrastructure changes and VM-entry implementation.
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1	/* $Id: CPUM.cpp 78220 2019-04-20 04:08:44Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/patm.h>
120	#include <VBox/vmm/hm.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
339	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
340	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
341	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
342
343	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
344	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
345	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
346	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
347	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
348	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
349	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
350	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
351	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
352	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
353	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1[8]),
354
355	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
356	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
357	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
358	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
359	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
360	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
361	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
362	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
363
364	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
365	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
366	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
367	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
369	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
370	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
371	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
373	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
374	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
378	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
379	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
380	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
381	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
382	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
383
384	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
385	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
386	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
387	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
388	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
389	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
390	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
391	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
392	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
393
394	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
395	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
396	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
397	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
398	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
399	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
400	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
401	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
402	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
403	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
404	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
405	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
406	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
407	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
408	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
409	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
410	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
411	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
412	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
413	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
414	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
415	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
416	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
417	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
418
419	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
420	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
421
422	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
423	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
424	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
425	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
426	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
427	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
428	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
429	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
430	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
431	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
432	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
433	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
434	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
435	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
436	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
437	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
438	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
439	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
440	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
441	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
442	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
443	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
444	SSMFIELD_ENTRY( VMXVVMCS, u64XssBitmap),
445	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEnclsBitmap),
446	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
447	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
448
449	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
450	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
451
452	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
453	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
454	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
455	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
456	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
457	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
458	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
459	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
460	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
461	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
462	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
463
464	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
465	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
466	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
467	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
468
469	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
470	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
471	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
472	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
473	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
474	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
475	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
476	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
477	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved4),
478
479	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
480	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
481	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
482	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
483	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
484	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
485	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved5),
486
487	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
488	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
489	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
490	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
491	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
492	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
493	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
494	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
495	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
496	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
497	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
498	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
503	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
504	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpt),
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
507	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved6),
508
509	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
510	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
511	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
512	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
513	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
514	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
515	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
518	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
519	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
520	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
521	SSMFIELD_ENTRY( VMXVVMCS, au64Reserved7),
522	SSMFIELD_ENTRY_TERM()
523	};
524
525	/** Saved state field descriptors for CPUMCTX. */
526	static const SSMFIELD g_aCpumX87Fields[] =
527	{
528	SSMFIELD_ENTRY( X86FXSTATE, FCW),
529	SSMFIELD_ENTRY( X86FXSTATE, FSW),
530	SSMFIELD_ENTRY( X86FXSTATE, FTW),
531	SSMFIELD_ENTRY( X86FXSTATE, FOP),
532	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
533	SSMFIELD_ENTRY( X86FXSTATE, CS),
534	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
535	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
536	SSMFIELD_ENTRY( X86FXSTATE, DS),
537	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
538	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
539	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
540	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
541	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
542	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
543	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
544	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
545	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
546	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
547	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
548	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
549	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
550	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
551	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
552	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
553	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
554	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
555	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
556	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
557	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
558	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
559	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
560	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
561	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
562	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
564	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
565	SSMFIELD_ENTRY_TERM()
566	};
567
568	/** Saved state field descriptors for X86XSAVEHDR. */
569	static const SSMFIELD g_aCpumXSaveHdrFields[] =
570	{
571	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
572	SSMFIELD_ENTRY_TERM()
573	};
574
575	/** Saved state field descriptors for X86XSAVEYMMHI. */
576	static const SSMFIELD g_aCpumYmmHiFields[] =
577	{
578	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
579	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
580	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
581	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
582	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
583	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
584	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
585	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
586	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
587	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
588	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
589	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
590	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
591	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
592	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
594	SSMFIELD_ENTRY_TERM()
595	};
596
597	/** Saved state field descriptors for X86XSAVEBNDREGS. */
598	static const SSMFIELD g_aCpumBndRegsFields[] =
599	{
600	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
601	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
602	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
603	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
604	SSMFIELD_ENTRY_TERM()
605	};
606
607	/** Saved state field descriptors for X86XSAVEBNDCFG. */
608	static const SSMFIELD g_aCpumBndCfgFields[] =
609	{
610	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
611	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
612	SSMFIELD_ENTRY_TERM()
613	};
614
615	#if 0 /** @todo */
616	/** Saved state field descriptors for X86XSAVEOPMASK. */
617	static const SSMFIELD g_aCpumOpmaskFields[] =
618	{
619	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
620	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
621	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
622	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
623	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
624	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
625	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
626	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
627	SSMFIELD_ENTRY_TERM()
628	};
629	#endif
630
631	/** Saved state field descriptors for X86XSAVEZMMHI256. */
632	static const SSMFIELD g_aCpumZmmHi256Fields[] =
633	{
634	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
635	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
636	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
637	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
638	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
639	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
640	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
641	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
642	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
643	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
644	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
645	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
646	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
647	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
648	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
650	SSMFIELD_ENTRY_TERM()
651	};
652
653	/** Saved state field descriptors for X86XSAVEZMM16HI. */
654	static const SSMFIELD g_aCpumZmm16HiFields[] =
655	{
656	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
657	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
658	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
659	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
660	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
661	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
662	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
663	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
664	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
665	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
666	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
667	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
668	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
669	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
670	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
672	SSMFIELD_ENTRY_TERM()
673	};
674
675
676
677	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
678	* registeres changed. */
679	static const SSMFIELD g_aCpumX87FieldsMem[] =
680	{
681	SSMFIELD_ENTRY( X86FXSTATE, FCW),
682	SSMFIELD_ENTRY( X86FXSTATE, FSW),
683	SSMFIELD_ENTRY( X86FXSTATE, FTW),
684	SSMFIELD_ENTRY( X86FXSTATE, FOP),
685	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
686	SSMFIELD_ENTRY( X86FXSTATE, CS),
687	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
688	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
689	SSMFIELD_ENTRY( X86FXSTATE, DS),
690	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
691	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
692	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
693	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
694	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
695	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
696	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
697	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
698	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
699	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
700	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
701	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
702	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
703	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
704	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
705	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
706	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
707	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
708	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
709	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
710	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
711	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
712	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
713	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
714	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
715	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
717	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
718	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
719	};
720
721	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
722	* registeres changed. */
723	static const SSMFIELD g_aCpumCtxFieldsMem[] =
724	{
725	SSMFIELD_ENTRY( CPUMCTX, rdi),
726	SSMFIELD_ENTRY( CPUMCTX, rsi),
727	SSMFIELD_ENTRY( CPUMCTX, rbp),
728	SSMFIELD_ENTRY( CPUMCTX, rax),
729	SSMFIELD_ENTRY( CPUMCTX, rbx),
730	SSMFIELD_ENTRY( CPUMCTX, rdx),
731	SSMFIELD_ENTRY( CPUMCTX, rcx),
732	SSMFIELD_ENTRY( CPUMCTX, rsp),
733	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
734	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
735	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
736	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
737	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
738	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
739	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
740	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
741	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
742	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
743	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
744	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
745	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
746	SSMFIELD_ENTRY( CPUMCTX, rflags),
747	SSMFIELD_ENTRY( CPUMCTX, rip),
748	SSMFIELD_ENTRY( CPUMCTX, r8),
749	SSMFIELD_ENTRY( CPUMCTX, r9),
750	SSMFIELD_ENTRY( CPUMCTX, r10),
751	SSMFIELD_ENTRY( CPUMCTX, r11),
752	SSMFIELD_ENTRY( CPUMCTX, r12),
753	SSMFIELD_ENTRY( CPUMCTX, r13),
754	SSMFIELD_ENTRY( CPUMCTX, r14),
755	SSMFIELD_ENTRY( CPUMCTX, r15),
756	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
757	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
758	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
759	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
760	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
761	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
762	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
763	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
764	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
765	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
766	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
767	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
768	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
769	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
770	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
771	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
772	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
773	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
774	SSMFIELD_ENTRY( CPUMCTX, cr0),
775	SSMFIELD_ENTRY( CPUMCTX, cr2),
776	SSMFIELD_ENTRY( CPUMCTX, cr3),
777	SSMFIELD_ENTRY( CPUMCTX, cr4),
778	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
779	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
780	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
781	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
782	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
783	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
784	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
785	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
786	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
787	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
788	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
789	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
790	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
791	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
792	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
793	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
794	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
795	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
796	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
797	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
798	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
799	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
800	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
801	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
802	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
803	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
804	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
805	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
806	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
807	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
808	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
809	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
810	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
811	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
812	SSMFIELD_ENTRY_TERM()
813	};
814
815	/** Saved state field descriptors for CPUMCTX_VER1_6. */
816	static const SSMFIELD g_aCpumX87FieldsV16[] =
817	{
818	SSMFIELD_ENTRY( X86FXSTATE, FCW),
819	SSMFIELD_ENTRY( X86FXSTATE, FSW),
820	SSMFIELD_ENTRY( X86FXSTATE, FTW),
821	SSMFIELD_ENTRY( X86FXSTATE, FOP),
822	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
823	SSMFIELD_ENTRY( X86FXSTATE, CS),
824	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
825	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
826	SSMFIELD_ENTRY( X86FXSTATE, DS),
827	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
828	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
829	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
830	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
831	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
832	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
833	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
834	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
835	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
836	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
837	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
838	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
839	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
840	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
841	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
842	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
843	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
844	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
845	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
846	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
847	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
848	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
849	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
850	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
851	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
852	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
854	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
855	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
856	SSMFIELD_ENTRY_TERM()
857	};
858
859	/** Saved state field descriptors for CPUMCTX_VER1_6. */
860	static const SSMFIELD g_aCpumCtxFieldsV16[] =
861	{
862	SSMFIELD_ENTRY( CPUMCTX, rdi),
863	SSMFIELD_ENTRY( CPUMCTX, rsi),
864	SSMFIELD_ENTRY( CPUMCTX, rbp),
865	SSMFIELD_ENTRY( CPUMCTX, rax),
866	SSMFIELD_ENTRY( CPUMCTX, rbx),
867	SSMFIELD_ENTRY( CPUMCTX, rdx),
868	SSMFIELD_ENTRY( CPUMCTX, rcx),
869	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
870	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
871	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
872	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
873	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
874	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
875	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
876	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
877	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
878	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
879	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
880	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
881	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
882	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
883	SSMFIELD_ENTRY( CPUMCTX, rflags),
884	SSMFIELD_ENTRY( CPUMCTX, rip),
885	SSMFIELD_ENTRY( CPUMCTX, r8),
886	SSMFIELD_ENTRY( CPUMCTX, r9),
887	SSMFIELD_ENTRY( CPUMCTX, r10),
888	SSMFIELD_ENTRY( CPUMCTX, r11),
889	SSMFIELD_ENTRY( CPUMCTX, r12),
890	SSMFIELD_ENTRY( CPUMCTX, r13),
891	SSMFIELD_ENTRY( CPUMCTX, r14),
892	SSMFIELD_ENTRY( CPUMCTX, r15),
893	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
894	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
895	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
896	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
897	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
898	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
899	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
900	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
901	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
902	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
903	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
904	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
905	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
906	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
907	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
908	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
909	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
910	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
911	SSMFIELD_ENTRY( CPUMCTX, cr0),
912	SSMFIELD_ENTRY( CPUMCTX, cr2),
913	SSMFIELD_ENTRY( CPUMCTX, cr3),
914	SSMFIELD_ENTRY( CPUMCTX, cr4),
915	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
916	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
917	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
918	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
919	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
920	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
921	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
922	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
923	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
924	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
925	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
926	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
927	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
928	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
929	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
930	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
931	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
932	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
933	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
934	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
935	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
936	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
937	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
938	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
939	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
940	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
941	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
942	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
943	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
944	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
945	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
946	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
947	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
948	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
949	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
950	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
951	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
952	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
953	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
954	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
955	SSMFIELD_ENTRY_TERM()
956	};
957
958
959	/**
960	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
961	*
962	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
963	* (last instruction pointer, last data pointer, last opcode) except when the ES
964	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
965	* clear these registers there is potential, local FPU leakage from a process
966	* using the FPU to another.
967	*
968	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
969	*
970	* @param pVM The cross context VM structure.
971	*/
972	static void cpumR3CheckLeakyFpu(PVM pVM)
973	{
974	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
975	uint32_t const u32Family = u32CpuVersion >> 8;
976	if ( u32Family >= 6 /* K7 and higher */
977	&& ASMIsAmdCpu())
978	{
979	uint32_t cExt = ASMCpuId_EAX(0x80000000);
980	if (ASMIsValidExtRange(cExt))
981	{
982	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
983	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
984	{
985	for (VMCPUID i = 0; i < pVM->cCpus; i++)
986	pVM->aCpus[i].cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
987	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
988	}
989	}
990	}
991	}
992
993
994	/**
995	* Frees memory allocated for the SVM hardware virtualization state.
996	*
997	* @param pVM The cross context VM structure.
998	*/
999	static void cpumR3FreeSvmHwVirtState(PVM pVM)
1000	{
1001	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1002	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1003	{
1004	PVMCPU pVCpu = &pVM->aCpus[i];
1005	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
1006	{
1007	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
1008	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
1009	}
1010	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
1011
1012	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
1013	{
1014	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
1015	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
1016	}
1017
1018	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
1019	{
1020	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
1021	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
1022	}
1023	}
1024	}
1025
1026
1027	/**
1028	* Allocates memory for the SVM hardware virtualization state.
1029	*
1030	* @returns VBox status code.
1031	* @param pVM The cross context VM structure.
1032	*/
1033	static int cpumR3AllocSvmHwVirtState(PVM pVM)
1034	{
1035	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1036
1037	int rc = VINF_SUCCESS;
1038	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
1039	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
1040	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1041	{
1042	PVMCPU pVCpu = &pVM->aCpus[i];
1043	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1044
1045	/*
1046	* Allocate the nested-guest VMCB.
1047	*/
1048	SUPPAGE SupNstGstVmcbPage;
1049	RT_ZERO(SupNstGstVmcbPage);
1050	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
1051	Assert(SVM_VMCB_PAGES == 1);
1052	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1053	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
1054	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
1055	if (RT_FAILURE(rc))
1056	{
1057	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1058	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
1059	break;
1060	}
1061	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
1062
1063	/*
1064	* Allocate the MSRPM (MSR Permission bitmap).
1065	*/
1066	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1067	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
1068	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
1069	if (RT_FAILURE(rc))
1070	{
1071	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1072	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
1073	SVM_MSRPM_PAGES));
1074	break;
1075	}
1076
1077	/*
1078	* Allocate the IOPM (IO Permission bitmap).
1079	*/
1080	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1081	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
1082	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
1083	if (RT_FAILURE(rc))
1084	{
1085	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1086	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
1087	SVM_IOPM_PAGES));
1088	break;
1089	}
1090	}
1091
1092	/* On any failure, cleanup. */
1093	if (RT_FAILURE(rc))
1094	cpumR3FreeSvmHwVirtState(pVM);
1095
1096	return rc;
1097	}
1098
1099
1100	/**
1101	* Resets per-VCPU SVM hardware virtualization state.
1102	*
1103	* @param pVCpu The cross context virtual CPU structure.
1104	*/
1105	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1106	{
1107	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1108	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1109	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1110
1111	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1112	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1113	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1114	}
1115
1116
1117	/**
1118	* Frees memory allocated for the VMX hardware virtualization state.
1119	*
1120	* @param pVM The cross context VM structure.
1121	*/
1122	static void cpumR3FreeVmxHwVirtState(PVM pVM)
1123	{
1124	Assert(pVM->cpum.s.GuestFeatures.fVmx);
1125	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1126	{
1127	PVMCPU pVCpu = &pVM->aCpus[i];
1128	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1129
1130	if (pCtx->hwvirt.vmx.pVmcsR3)
1131	{
1132	SUPR3ContFree(pCtx->hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
1133	pCtx->hwvirt.vmx.pVmcsR3 = NULL;
1134	}
1135	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1136	{
1137	SUPR3ContFree(pCtx->hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
1138	pCtx->hwvirt.vmx.pShadowVmcsR3 = NULL;
1139	}
1140	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1141	{
1142	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1143	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = NULL;
1144	}
1145	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1146	{
1147	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1148	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
1149	}
1150	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1151	{
1152	SUPR3ContFree(pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1153	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = NULL;
1154	}
1155	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1156	{
1157	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1158	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = NULL;
1159	}
1160	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1161	{
1162	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1163	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = NULL;
1164	}
1165	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1166	{
1167	SUPR3ContFree(pCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
1168	pCtx->hwvirt.vmx.pvMsrBitmapR3 = NULL;
1169	}
1170	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1171	{
1172	SUPR3ContFree(pCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1173	pCtx->hwvirt.vmx.pvIoBitmapR3 = NULL;
1174	}
1175	}
1176	}
1177
1178
1179	/**
1180	* Allocates memory for the VMX hardware virtualization state.
1181	*
1182	* @returns VBox status code.
1183	* @param pVM The cross context VM structure.
1184	*/
1185	static int cpumR3AllocVmxHwVirtState(PVM pVM)
1186	{
1187	int rc = VINF_SUCCESS;
1188	uint32_t const cPages = (2 * VMX_V_VMCS_PAGES)
1189	+ VMX_V_VIRT_APIC_PAGES
1190	+ (2 * VMX_V_VMREAD_VMWRITE_BITMAP_SIZE)
1191	+ (3 * VMX_V_AUTOMSR_AREA_SIZE)
1192	+ VMX_V_MSR_BITMAP_SIZE
1193	+ (VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1194	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n", pVM->cCpus * cPages));
1195	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1196	{
1197	PVMCPU pVCpu = &pVM->aCpus[i];
1198	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1199	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1200
1201	/*
1202	* Allocate the nested-guest current VMCS.
1203	*/
1204	Assert(VMX_V_VMCS_PAGES == 1);
1205	pCtx->hwvirt.vmx.pVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1206	&pCtx->hwvirt.vmx.pVmcsR0,
1207	&pCtx->hwvirt.vmx.HCPhysVmcs);
1208	if (pCtx->hwvirt.vmx.pVmcsR3)
1209	{ /* likely */ }
1210	else
1211	{
1212	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1213	break;
1214	}
1215
1216	/*
1217	* Allocate the nested-guest shadow VMCS.
1218	*/
1219	Assert(VMX_V_VMCS_PAGES == 1);
1220	pCtx->hwvirt.vmx.pShadowVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1221	&pCtx->hwvirt.vmx.pShadowVmcsR0,
1222	&pCtx->hwvirt.vmx.HCPhysShadowVmcs);
1223	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1224	{ /* likely */ }
1225	else
1226	{
1227	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1228	break;
1229	}
1230
1231	/*
1232	* Allocate the VMREAD-bitmap.
1233	*/
1234	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1235	&pCtx->hwvirt.vmx.pvVmreadBitmapR0,
1236	&pCtx->hwvirt.vmx.HCPhysVmreadBitmap);
1237	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1238	{ /* likely */ }
1239	else
1240	{
1241	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1242	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1243	break;
1244	}
1245
1246	/*
1247	* Allocatge the VMWRITE-bitmap.
1248	*/
1249	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1250	&pCtx->hwvirt.vmx.pvVmwriteBitmapR0,
1251	&pCtx->hwvirt.vmx.HCPhysVmwriteBitmap);
1252	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1253	{ /* likely */ }
1254	else
1255	{
1256	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1257	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1258	break;
1259	}
1260
1261	/*
1262	* Allocate the VM-entry MSR-load area.
1263	*/
1264	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1265	&pCtx->hwvirt.vmx.pEntryMsrLoadAreaR0,
1266	&pCtx->hwvirt.vmx.HCPhysEntryMsrLoadArea);
1267	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1268	{ /* likely */ }
1269	else
1270	{
1271	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-entry MSR-load area\n", pVCpu->idCpu,
1272	VMX_V_AUTOMSR_AREA_PAGES));
1273	break;
1274	}
1275
1276	/*
1277	* Allocate the VM-exit MSR-store area.
1278	*/
1279	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1280	&pCtx->hwvirt.vmx.pExitMsrStoreAreaR0,
1281	&pCtx->hwvirt.vmx.HCPhysExitMsrStoreArea);
1282	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1283	{ /* likely */ }
1284	else
1285	{
1286	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-store area\n", pVCpu->idCpu,
1287	VMX_V_AUTOMSR_AREA_PAGES));
1288	break;
1289	}
1290
1291	/*
1292	* Allocate the VM-exit MSR-load area.
1293	*/
1294	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1295	&pCtx->hwvirt.vmx.pExitMsrLoadAreaR0,
1296	&pCtx->hwvirt.vmx.HCPhysExitMsrLoadArea);
1297	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1298	{ /* likely */ }
1299	else
1300	{
1301	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-load area\n", pVCpu->idCpu,
1302	VMX_V_AUTOMSR_AREA_PAGES));
1303	break;
1304	}
1305
1306	/*
1307	* Allocate the MSR bitmap.
1308	*/
1309	pCtx->hwvirt.vmx.pvMsrBitmapR3 = SUPR3ContAlloc(VMX_V_MSR_BITMAP_PAGES,
1310	&pCtx->hwvirt.vmx.pvMsrBitmapR0,
1311	&pCtx->hwvirt.vmx.HCPhysMsrBitmap);
1312	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1313	{ /* likely */ }
1314	else
1315	{
1316	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1317	VMX_V_MSR_BITMAP_PAGES));
1318	break;
1319	}
1320
1321	/*
1322	* Allocate the I/O bitmaps (A and B).
1323	*/
1324	pCtx->hwvirt.vmx.pvIoBitmapR3 = SUPR3ContAlloc(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES,
1325	&pCtx->hwvirt.vmx.pvIoBitmapR0,
1326	&pCtx->hwvirt.vmx.HCPhysIoBitmap);
1327	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1328	{ /* likely */ }
1329	else
1330	{
1331	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1332	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1333	break;
1334	}
1335
1336	/*
1337	* Zero out all allocated pages (should compress well for saved-state).
1338	*/
1339	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1340	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_VMCS_SIZE);
1341	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmreadBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1342	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1343	memset(pCtx->hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1344	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1345	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1346	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvMsrBitmap), 0, VMX_V_MSR_BITMAP_SIZE);
1347	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap), 0, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1348	}
1349
1350	/* On any failure, cleanup. */
1351	if (RT_FAILURE(rc))
1352	cpumR3FreeVmxHwVirtState(pVM);
1353
1354	return rc;
1355	}
1356
1357
1358	/**
1359	* Resets per-VCPU VMX hardware virtualization state.
1360	*
1361	* @param pVCpu The cross context virtual CPU structure.
1362	*/
1363	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1364	{
1365	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1366	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1367	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1368	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1369
1370	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1371	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_VMCS_SIZE);
1372	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1373	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1374	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1375	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1376	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1377	/* Don't reset diagnostics here. */
1378	}
1379
1380
1381	/**
1382	* Displays the host and guest VMX features.
1383	*
1384	* @param pVM The cross context VM structure.
1385	* @param pHlp The info helper functions.
1386	* @param pszArgs "terse", "default" or "verbose".
1387	*/
1388	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1389	{
1390	RT_NOREF(pszArgs);
1391	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1392	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1393	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1394	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1395	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1396	{
1397	#define VMXFEATDUMP(a_szDesc, a_Var) \
1398	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1399
1400	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1401	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1402	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1403	/* Basic. */
1404	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1405	/* Pin-based controls. */
1406	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1407	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1408	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1409	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1410	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1411	/* Processor-based controls. */
1412	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1413	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1414	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1415	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1416	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1417	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1418	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1419	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1420	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1421	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1422	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1423	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1424	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1425	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1426	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1427	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1428	VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag ", fVmxMonitorTrapFlag);
1429	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1430	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1431	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1432	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1433	/* Secondary processor-based controls. */
1434	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1435	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1436	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1437	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1438	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1439	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1440	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1441	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1442	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1443	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1444	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1445	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1446	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1447	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1448	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1449	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1450	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1451	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1452	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1453	/* VM-entry controls. */
1454	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1455	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1456	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1457	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1458	/* VM-exit controls. */
1459	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1460	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1461	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1462	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1463	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1464	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1465	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1466	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1467	/* Miscellaneous data. */
1468	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1469	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1470	VMXFEATDUMP("VmwriteAll - Write allowed to read-only VMCS fields ", fVmxVmwriteAll);
1471	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1472	#undef VMXFEATDUMP
1473	}
1474	else
1475	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1476	}
1477
1478
1479	/**
1480	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1481	* or NEM) is allowed.
1482	*
1483	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1484	* otherwise.
1485	* @param pVM The cross context VM structure.
1486	*/
1487	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1488	{
1489	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1490	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1491	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1492	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1493	return true;
1494	#else
1495	NOREF(pVM);
1496	#endif
1497	return false;
1498	}
1499
1500
1501	/**
1502	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1503	*
1504	* @param pVM The cross context VM structure.
1505	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1506	* and no hardware-assisted nested-guest execution is
1507	* possible for this VM.
1508	* @param pGuestFeatures The guest features to use (only VMX features are
1509	* accessed).
1510	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1511	*
1512	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1513	*/
1514	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1515	{
1516	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1517
1518	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1519	Assert(pGuestFeatures->fVmx);
1520
1521	/*
1522	* We don't support the following MSRs yet:
1523	* - True Pin-based VM-execution controls.
1524	* - True Processor-based VM-execution controls.
1525	* - True VM-entry VM-execution controls.
1526	* - True VM-exit VM-execution controls.
1527	* - EPT/VPID capabilities.
1528	*/
1529
1530	/* Feature control. */
1531	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1532
1533	/* Basic information. */
1534	{
1535	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1536	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1537	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1538	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1539	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1540	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1541	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1542	pGuestVmxMsrs->u64Basic = u64Basic;
1543	}
1544
1545	/* Pin-based VM-execution controls. */
1546	{
1547	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1548	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1549	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1550	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1551	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1552	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1553	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1554	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1555	fAllowed0, fAllowed1, fFeatures));
1556	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1557	}
1558
1559	/* Processor-based VM-execution controls. */
1560	{
1561	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1562	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1563	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1564	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1565	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1566	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1567	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1568	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1569	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1570	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1571	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1572	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1573	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1574	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1575	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1576	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1577	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1578	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1579	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1580	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1581	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1582	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1583	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1584	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1585	fAllowed1, fFeatures));
1586	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1587	}
1588
1589	/* Secondary processor-based VM-execution controls. */
1590	if (pGuestFeatures->fVmxSecondaryExecCtls)
1591	{
1592	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1593	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1594	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1595	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1596	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1597	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1598	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1599	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1600	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1601	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1602	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1603	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1604	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1605	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1606	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1607	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1608	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1609	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1610	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1611	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1612	uint32_t const fAllowed0 = 0;
1613	uint32_t const fAllowed1 = fFeatures;
1614	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1615	}
1616
1617	/* VM-exit controls. */
1618	{
1619	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1620	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1621	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1622	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1623	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1624	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1625	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1626	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1627	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1628	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1629	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1630	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1631	fAllowed1, fFeatures));
1632	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1633	}
1634
1635	/* VM-entry controls. */
1636	{
1637	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1638	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1639	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1640	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1641	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1642	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1643	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1644	fAllowed1, fFeatures));
1645	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1646	}
1647
1648	/* Miscellaneous data. */
1649	{
1650	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1651
1652	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1653	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1654	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1655	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1656	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1657	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1658	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1659	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1660	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1661	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1662	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1663	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1664	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1665	}
1666
1667	/* CR0 Fixed-0. */
1668	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX: VMX_V_CR0_FIXED0;
1669
1670	/* CR0 Fixed-1. */
1671	{
1672	/*
1673	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1674	* This is different from CR4 fixed-1 bits which are reported as per the
1675	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1676	*/
1677	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1678	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| VMX_V_CR0_FIXED0; /* Make sure the CR0 MB1 bits are not clear. */
1679	}
1680
1681	/* CR4 Fixed-0. */
1682	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1683
1684	/* CR4 Fixed-1. */
1685	{
1686	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1687	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| VMX_V_CR4_FIXED0; /* Make sure the CR4 MB1 bits are not clear. */
1688	}
1689
1690	/* VMCS Enumeration. */
1691	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1692
1693	/* VM Functions. */
1694	if (pGuestFeatures->fVmxVmFunc)
1695	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1696	}
1697
1698
1699	/**
1700	* Checks whether the given guest CPU VMX features are compatible with the provided
1701	* base features.
1702	*
1703	* @returns @c true if compatible, @c false otherwise.
1704	* @param pVM The cross context VM structure.
1705	* @param pBase The base VMX CPU features.
1706	* @param pGst The guest VMX CPU features.
1707	*
1708	* @remarks Only VMX feature bits are examined.
1709	*/
1710	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1711	{
1712	if (cpumR3IsHwAssistNstGstExecAllowed(pVM))
1713	{
1714	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1715	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1716	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1717	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1718	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1719	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1720	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1721	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1722	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1723	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1724	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1725	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1726	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1727	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1728	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1729	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1730	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1731	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1732	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1733	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1734	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1735	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1736	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1737	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1738	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1739	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1740	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1741	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1742	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1743	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1744	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1745	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1746
1747	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1748	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1749	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1750	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1751	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1752	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1753	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1754	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1755	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1756	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1757	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1758	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1759	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1760	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1761	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1762	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1763	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1764	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1765	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1766	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1767	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1768	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1769	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1770	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1771	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1772	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1773	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1774	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1775	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1776	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1777	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1778	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1779
1780	if ((fBase \| fGst) != fBase)
1781	{
1782	LogRel(("CPUM: Host VMX features are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64\n",
1783	fBase, fGst));
1784	return false;
1785	}
1786	return true;
1787	}
1788	return true;
1789	}
1790
1791
1792	/**
1793	* Initializes VMX guest features and MSRs.
1794	*
1795	* @param pVM The cross context VM structure.
1796	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1797	* and no hardware-assisted nested-guest execution is
1798	* possible for this VM.
1799	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1800	*/
1801	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1802	{
1803	Assert(pVM);
1804	Assert(pGuestVmxMsrs);
1805
1806	/*
1807	* Initialize the set of VMX features we emulate.
1808	*
1809	* Note! Some bits might be reported as 1 always if they fall under the
1810	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1811	*/
1812	CPUMFEATURES EmuFeat;
1813	RT_ZERO(EmuFeat);
1814	EmuFeat.fVmx = 1;
1815	EmuFeat.fVmxInsOutInfo = 0;
1816	EmuFeat.fVmxExtIntExit = 1;
1817	EmuFeat.fVmxNmiExit = 1;
1818	EmuFeat.fVmxVirtNmi = 0;
1819	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1820	EmuFeat.fVmxPostedInt = 0;
1821	EmuFeat.fVmxIntWindowExit = 1;
1822	EmuFeat.fVmxTscOffsetting = 1;
1823	EmuFeat.fVmxHltExit = 1;
1824	EmuFeat.fVmxInvlpgExit = 1;
1825	EmuFeat.fVmxMwaitExit = 1;
1826	EmuFeat.fVmxRdpmcExit = 1;
1827	EmuFeat.fVmxRdtscExit = 1;
1828	EmuFeat.fVmxCr3LoadExit = 1;
1829	EmuFeat.fVmxCr3StoreExit = 1;
1830	EmuFeat.fVmxCr8LoadExit = 1;
1831	EmuFeat.fVmxCr8StoreExit = 1;
1832	EmuFeat.fVmxUseTprShadow = 0;
1833	EmuFeat.fVmxNmiWindowExit = 0;
1834	EmuFeat.fVmxMovDRxExit = 1;
1835	EmuFeat.fVmxUncondIoExit = 1;
1836	EmuFeat.fVmxUseIoBitmaps = 1;
1837	EmuFeat.fVmxMonitorTrapFlag = 0;
1838	EmuFeat.fVmxUseMsrBitmaps = 1;
1839	EmuFeat.fVmxMonitorExit = 1;
1840	EmuFeat.fVmxPauseExit = 1;
1841	EmuFeat.fVmxSecondaryExecCtls = 1;
1842	EmuFeat.fVmxVirtApicAccess = 0;
1843	EmuFeat.fVmxEpt = 0;
1844	EmuFeat.fVmxDescTableExit = 1;
1845	EmuFeat.fVmxRdtscp = 1;
1846	EmuFeat.fVmxVirtX2ApicMode = 0;
1847	EmuFeat.fVmxVpid = 0;
1848	EmuFeat.fVmxWbinvdExit = 1;
1849	EmuFeat.fVmxUnrestrictedGuest = 0;
1850	EmuFeat.fVmxApicRegVirt = 0;
1851	EmuFeat.fVmxVirtIntDelivery = 0;
1852	EmuFeat.fVmxPauseLoopExit = 0;
1853	EmuFeat.fVmxRdrandExit = 0;
1854	EmuFeat.fVmxInvpcid = 1;
1855	EmuFeat.fVmxVmFunc = 0;
1856	EmuFeat.fVmxVmcsShadowing = 0;
1857	EmuFeat.fVmxRdseedExit = 0;
1858	EmuFeat.fVmxPml = 0;
1859	EmuFeat.fVmxEptXcptVe = 0;
1860	EmuFeat.fVmxXsavesXrstors = 0;
1861	EmuFeat.fVmxUseTscScaling = 0;
1862	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1863	EmuFeat.fVmxIa32eModeGuest = 1;
1864	EmuFeat.fVmxEntryLoadEferMsr = 1;
1865	EmuFeat.fVmxEntryLoadPatMsr = 0;
1866	EmuFeat.fVmxExitSaveDebugCtls = 1;
1867	EmuFeat.fVmxHostAddrSpaceSize = 1;
1868	EmuFeat.fVmxExitAckExtInt = 0;
1869	EmuFeat.fVmxExitSavePatMsr = 0;
1870	EmuFeat.fVmxExitLoadPatMsr = 0;
1871	EmuFeat.fVmxExitSaveEferMsr = 1;
1872	EmuFeat.fVmxExitLoadEferMsr = 1;
1873	EmuFeat.fVmxSavePreemptTimer = 0;
1874	EmuFeat.fVmxExitSaveEferLma = 1;
1875	EmuFeat.fVmxIntelPt = 0;
1876	EmuFeat.fVmxVmwriteAll = 0;
1877	EmuFeat.fVmxEntryInjectSoftInt = 0;
1878
1879	/*
1880	* Merge guest features.
1881	*
1882	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1883	* by the hardware, hence we merge our emulated features with the host features below.
1884	*/
1885	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1886	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1887	Assert(pBaseFeat->fVmx);
1888	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1889	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1890	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1891	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1892	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1893	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1894	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1895	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1896	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1897	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1898	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1899	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1900	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1901	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1902	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1903	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1904	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1905	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1906	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1907	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1908	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1909	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1910	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1911	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1912	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1913	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1914	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1915	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1916	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1917	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1918	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1919	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1920	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1921	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1922	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1923	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1924	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1925	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1926	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1927	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1928	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1929	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1930	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1931	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1932	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1933	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1934	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1935	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1936	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1937	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1938	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1939	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1940	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1941	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1942	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1943	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1944	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1945	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1946	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1947	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1948	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1949	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1950	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1951
1952	/* Paranoia. */
1953	if (!pGuestFeat->fVmxSecondaryExecCtls)
1954	{
1955	Assert(!pGuestFeat->fVmxVirtApicAccess);
1956	Assert(!pGuestFeat->fVmxEpt);
1957	Assert(!pGuestFeat->fVmxDescTableExit);
1958	Assert(!pGuestFeat->fVmxRdtscp);
1959	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1960	Assert(!pGuestFeat->fVmxVpid);
1961	Assert(!pGuestFeat->fVmxWbinvdExit);
1962	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1963	Assert(!pGuestFeat->fVmxApicRegVirt);
1964	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1965	Assert(!pGuestFeat->fVmxPauseLoopExit);
1966	Assert(!pGuestFeat->fVmxRdrandExit);
1967	Assert(!pGuestFeat->fVmxInvpcid);
1968	Assert(!pGuestFeat->fVmxVmFunc);
1969	Assert(!pGuestFeat->fVmxVmcsShadowing);
1970	Assert(!pGuestFeat->fVmxRdseedExit);
1971	Assert(!pGuestFeat->fVmxPml);
1972	Assert(!pGuestFeat->fVmxEptXcptVe);
1973	Assert(!pGuestFeat->fVmxXsavesXrstors);
1974	Assert(!pGuestFeat->fVmxUseTscScaling);
1975	}
1976	if (pGuestFeat->fVmxUnrestrictedGuest)
1977	{
1978	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1979	Assert(pGuestFeat->fVmxExitSaveEferLma);
1980	}
1981
1982	/*
1983	* Finally initialize the VMX guest MSRs.
1984	*/
1985	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1986	}
1987
1988
1989	/**
1990	* Gets the host hardware-virtualization MSRs.
1991	*
1992	* @returns VBox status code.
1993	* @param pMsrs Where to store the MSRs.
1994	*/
1995	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1996	{
1997	Assert(pMsrs);
1998
1999	uint32_t fCaps = 0;
2000	int rc = SUPR3QueryVTCaps(&fCaps);
2001	if (RT_SUCCESS(rc))
2002	{
2003	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2004	{
2005	SUPHWVIRTMSRS HwvirtMsrs;
2006	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2007	if (RT_SUCCESS(rc))
2008	{
2009	if (fCaps & SUPVTCAPS_VT_X)
2010	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2011	else
2012	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2013	return VINF_SUCCESS;
2014	}
2015
2016	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2017	return rc;
2018	}
2019	else
2020	{
2021	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2022	return VERR_INTERNAL_ERROR_5;
2023	}
2024	}
2025	else
2026	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2027
2028	return VINF_SUCCESS;
2029	}
2030
2031
2032	/**
2033	* Initializes the CPUM.
2034	*
2035	* @returns VBox status code.
2036	* @param pVM The cross context VM structure.
2037	*/
2038	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2039	{
2040	LogFlow(("CPUMR3Init\n"));
2041
2042	/*
2043	* Assert alignment, sizes and tables.
2044	*/
2045	AssertCompileMemberAlignment(VM, cpum.s, 32);
2046	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2047	AssertCompileSizeAlignment(CPUMCTX, 64);
2048	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2049	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2050	AssertCompileMemberAlignment(VM, cpum, 64);
2051	AssertCompileMemberAlignment(VM, aCpus, 64);
2052	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2053	AssertCompileMemberSizeAlignment(VM, aCpus[0].cpum.s, 64);
2054	#ifdef VBOX_STRICT
2055	int rc2 = cpumR3MsrStrictInitChecks();
2056	AssertRCReturn(rc2, rc2);
2057	#endif
2058
2059	/*
2060	* Initialize offsets.
2061	*/
2062
2063	/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
2064	pVM->cpum.s.offCPUMCPU0 = RT_UOFFSETOF(VM, aCpus[0].cpum) - RT_UOFFSETOF(VM, cpum);
2065	Assert((uintptr_t)&pVM->cpum + pVM->cpum.s.offCPUMCPU0 == (uintptr_t)&pVM->aCpus[0].cpum);
2066
2067
2068	/* Calculate the offset from CPUMCPU to CPUM. */
2069	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2070	{
2071	PVMCPU pVCpu = &pVM->aCpus[i];
2072
2073	pVCpu->cpum.s.offCPUM = RT_UOFFSETOF_DYN(VM, aCpus[i].cpum) - RT_UOFFSETOF(VM, cpum);
2074	Assert((uintptr_t)&pVCpu->cpum - pVCpu->cpum.s.offCPUM == (uintptr_t)&pVM->cpum);
2075	}
2076
2077	/*
2078	* Gather info about the host CPU.
2079	*/
2080	if (!ASMHasCpuId())
2081	{
2082	LogRel(("The CPU doesn't support CPUID!\n"));
2083	return VERR_UNSUPPORTED_CPU;
2084	}
2085
2086	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2087
2088	CPUMMSRS HostMsrs;
2089	RT_ZERO(HostMsrs);
2090	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2091	AssertLogRelRCReturn(rc, rc);
2092
2093	PCPUMCPUIDLEAF paLeaves;
2094	uint32_t cLeaves;
2095	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
2096	AssertLogRelRCReturn(rc, rc);
2097
2098	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
2099	RTMemFree(paLeaves);
2100	AssertLogRelRCReturn(rc, rc);
2101	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2102
2103	/*
2104	* Check that the CPU supports the minimum features we require.
2105	*/
2106	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2107	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2108	if (!pVM->cpum.s.HostFeatures.fMmx)
2109	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2110	if (!pVM->cpum.s.HostFeatures.fTsc)
2111	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2112
2113	/*
2114	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2115	*/
2116	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2117	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2118
2119	/*
2120	* Figure out which XSAVE/XRSTOR features are available on the host.
2121	*/
2122	uint64_t fXcr0Host = 0;
2123	uint64_t fXStateHostMask = 0;
2124	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2125	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2126	{
2127	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2128	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2129	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2130	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2131	}
2132	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2133	if (VM_IS_RAW_MODE_ENABLED(pVM)) /* For raw-mode, we only use XSAVE/XRSTOR when the guest starts using it (CPUID/CR4 visibility). */
2134	fXStateHostMask = 0;
2135	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2136	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2137
2138	/*
2139	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
2140	*/
2141	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2142	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2143	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
2144
2145	uint8_t *pbXStates;
2146	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 3 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
2147	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
2148	AssertLogRelRCReturn(rc, rc);
2149
2150	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2151	{
2152	PVMCPU pVCpu = &pVM->aCpus[i];
2153
2154	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2155	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2156	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
2157	pbXStates += cbMaxXState;
2158
2159	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2160	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2161	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
2162	pbXStates += cbMaxXState;
2163
2164	pVCpu->cpum.s.Hyper.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2165	pVCpu->cpum.s.Hyper.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2166	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToR0(pVM, pbXStates);
2167	pbXStates += cbMaxXState;
2168
2169	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2170	}
2171
2172	/*
2173	* Register saved state data item.
2174	*/
2175	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2176	NULL, cpumR3LiveExec, NULL,
2177	NULL, cpumR3SaveExec, NULL,
2178	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2179	if (RT_FAILURE(rc))
2180	return rc;
2181
2182	/*
2183	* Register info handlers and registers with the debugger facility.
2184	*/
2185	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2186	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2187	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2188	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2189	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2190	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2191	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2192	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2193	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2194	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2195	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2196	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2197	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2198	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2199	&cpumR3InfoVmxFeatures);
2200
2201	rc = cpumR3DbgInit(pVM);
2202	if (RT_FAILURE(rc))
2203	return rc;
2204
2205	/*
2206	* Check if we need to workaround partial/leaky FPU handling.
2207	*/
2208	cpumR3CheckLeakyFpu(pVM);
2209
2210	/*
2211	* Initialize the Guest CPUID and MSR states.
2212	*/
2213	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2214	if (RT_FAILURE(rc))
2215	return rc;
2216
2217	/*
2218	* Allocate memory required by the guest hardware-virtualization structures.
2219	* This must be done after initializing CPUID/MSR features as we access the
2220	* the VMX/SVM guest features below.
2221	*/
2222	if (pVM->cpum.s.GuestFeatures.fVmx)
2223	rc = cpumR3AllocVmxHwVirtState(pVM);
2224	else if (pVM->cpum.s.GuestFeatures.fSvm)
2225	rc = cpumR3AllocSvmHwVirtState(pVM);
2226	else
2227	Assert(pVM->aCpus[0].cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2228	if (RT_FAILURE(rc))
2229	return rc;
2230
2231	/*
2232	* Workaround for missing cpuid(0) patches when leaf 4 returns GuestInfo.DefCpuId:
2233	* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
2234	* of processors from (cpuid(4).eax >> 26) + 1.
2235	*
2236	* Note: this code is obsolete, but let's keep it here for reference.
2237	* Purpose is valid when we artificially cap the max std id to less than 4.
2238	*
2239	* Note: This used to be a separate function CPUMR3SetHwVirt that was called
2240	* after VMINITCOMPLETED_HM.
2241	*/
2242	if (VM_IS_RAW_MODE_ENABLED(pVM))
2243	{
2244	Assert( (pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax & UINT32_C(0xffffc000)) == 0
2245	\|\| pVM->cpum.s.aGuestCpuIdPatmStd[0].uEax < 0x4);
2246	pVM->cpum.s.aGuestCpuIdPatmStd[4].uEax &= UINT32_C(0x00003fff);
2247	}
2248
2249	CPUMR3Reset(pVM);
2250	return VINF_SUCCESS;
2251	}
2252
2253
2254	/**
2255	* Applies relocations to data and code managed by this
2256	* component. This function will be called at init and
2257	* whenever the VMM need to relocate it self inside the GC.
2258	*
2259	* The CPUM will update the addresses used by the switcher.
2260	*
2261	* @param pVM The cross context VM structure.
2262	*/
2263	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2264	{
2265	LogFlow(("CPUMR3Relocate\n"));
2266
2267	pVM->cpum.s.GuestInfo.paMsrRangesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paMsrRangesR3);
2268	pVM->cpum.s.GuestInfo.paCpuIdLeavesRC = MMHyperR3ToRC(pVM, pVM->cpum.s.GuestInfo.paCpuIdLeavesR3);
2269
2270	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2271	{
2272	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2273	pVCpu->cpum.s.Guest.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Guest.pXStateR3);
2274	pVCpu->cpum.s.Host.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Host.pXStateR3);
2275	pVCpu->cpum.s.Hyper.pXStateRC = MMHyperR3ToRC(pVM, pVCpu->cpum.s.Hyper.pXStateR3); /** @todo remove me */
2276
2277	/* Recheck the guest DRx values in raw-mode. */
2278	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX, false);
2279	}
2280	}
2281
2282
2283	/**
2284	* Terminates the CPUM.
2285	*
2286	* Termination means cleaning up and freeing all resources,
2287	* the VM it self is at this point powered off or suspended.
2288	*
2289	* @returns VBox status code.
2290	* @param pVM The cross context VM structure.
2291	*/
2292	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2293	{
2294	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2295	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2296	{
2297	PVMCPU pVCpu = &pVM->aCpus[i];
2298	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2299
2300	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2301	pVCpu->cpum.s.uMagic = 0;
2302	pCtx->dr[5] = 0;
2303	}
2304	#endif
2305
2306	if (pVM->cpum.s.GuestFeatures.fVmx)
2307	cpumR3FreeVmxHwVirtState(pVM);
2308	else if (pVM->cpum.s.GuestFeatures.fSvm)
2309	cpumR3FreeSvmHwVirtState(pVM);
2310	return VINF_SUCCESS;
2311	}
2312
2313
2314	/**
2315	* Resets a virtual CPU.
2316	*
2317	* Used by CPUMR3Reset and CPU hot plugging.
2318	*
2319	* @param pVM The cross context VM structure.
2320	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2321	* being reset. This may differ from the current EMT.
2322	*/
2323	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2324	{
2325	/** @todo anything different for VCPU > 0? */
2326	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2327
2328	/*
2329	* Initialize everything to ZERO first.
2330	*/
2331	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2332
2333	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
2334	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateRC));
2335	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
2336
2337	pVCpu->cpum.s.fUseFlags = fUseFlags;
2338
2339	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2340	pCtx->eip = 0x0000fff0;
2341	pCtx->edx = 0x00000600; /* P6 processor */
2342	pCtx->eflags.Bits.u1Reserved0 = 1;
2343
2344	pCtx->cs.Sel = 0xf000;
2345	pCtx->cs.ValidSel = 0xf000;
2346	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2347	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2348	pCtx->cs.u32Limit = 0x0000ffff;
2349	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2350	pCtx->cs.Attr.n.u1Present = 1;
2351	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2352
2353	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2354	pCtx->ds.u32Limit = 0x0000ffff;
2355	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2356	pCtx->ds.Attr.n.u1Present = 1;
2357	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2358
2359	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2360	pCtx->es.u32Limit = 0x0000ffff;
2361	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2362	pCtx->es.Attr.n.u1Present = 1;
2363	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2364
2365	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2366	pCtx->fs.u32Limit = 0x0000ffff;
2367	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2368	pCtx->fs.Attr.n.u1Present = 1;
2369	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2370
2371	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2372	pCtx->gs.u32Limit = 0x0000ffff;
2373	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2374	pCtx->gs.Attr.n.u1Present = 1;
2375	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2376
2377	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2378	pCtx->ss.u32Limit = 0x0000ffff;
2379	pCtx->ss.Attr.n.u1Present = 1;
2380	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2381	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2382
2383	pCtx->idtr.cbIdt = 0xffff;
2384	pCtx->gdtr.cbGdt = 0xffff;
2385
2386	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2387	pCtx->ldtr.u32Limit = 0xffff;
2388	pCtx->ldtr.Attr.n.u1Present = 1;
2389	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2390
2391	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2392	pCtx->tr.u32Limit = 0xffff;
2393	pCtx->tr.Attr.n.u1Present = 1;
2394	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2395
2396	pCtx->dr[6] = X86_DR6_INIT_VAL;
2397	pCtx->dr[7] = X86_DR7_INIT_VAL;
2398
2399	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
2400	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2401	pFpuCtx->FCW = 0x37f;
2402
2403	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2404	IA-32 Processor States Following Power-up, Reset, or INIT */
2405	pFpuCtx->MXCSR = 0x1F80;
2406	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2407
2408	pCtx->aXcr[0] = XSAVE_C_X87;
2409	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2410	{
2411	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2412	as we don't know what happened before. (Bother optimize later?) */
2413	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2414	}
2415
2416	/*
2417	* MSRs.
2418	*/
2419	/* Init PAT MSR */
2420	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2421
2422	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2423	* The Intel docs don't mention it. */
2424	Assert(!pCtx->msrEFER);
2425
2426	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2427	is supposed to be here, just trying provide useful/sensible values. */
2428	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2429	if (pRange)
2430	{
2431	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2432	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2433	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2434	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2435	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2436	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2437	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2438	}
2439
2440	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2441
2442	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2443	* called from each EMT while we're getting called by CPUMR3Reset()
2444	* iteratively on the same thread. Fix later. */
2445	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2446	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2447	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2448	#endif
2449
2450
2451	/* C-state control. Guesses. */
2452	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2453	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2454	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2455	* functionality. The default value must be different due to incompatible write mask.
2456	*/
2457	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2458	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2459	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2460	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2461
2462	/*
2463	* Hardware virtualization state.
2464	*/
2465	CPUMSetGuestGif(pCtx, true);
2466	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2467	if (pVM->cpum.s.GuestFeatures.fVmx)
2468	cpumR3ResetVmxHwVirtState(pVCpu);
2469	else if (pVM->cpum.s.GuestFeatures.fSvm)
2470	cpumR3ResetSvmHwVirtState(pVCpu);
2471	}
2472
2473
2474	/**
2475	* Resets the CPU.
2476	*
2477	* @returns VINF_SUCCESS.
2478	* @param pVM The cross context VM structure.
2479	*/
2480	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2481	{
2482	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2483	{
2484	CPUMR3ResetCpu(pVM, &pVM->aCpus[i]);
2485
2486	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2487	PCPUMCTX pCtx = &pVM->aCpus[i].cpum.s.Guest;
2488
2489	/* Magic marker for searching in crash dumps. */
2490	strcpy((char *)pVM->aCpus[i].cpum.s.aMagic, "CPUMCPU Magic");
2491	pVM->aCpus[i].cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2492	pCtx->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2493	#endif
2494	}
2495	}
2496
2497
2498
2499
2500	/**
2501	* Pass 0 live exec callback.
2502	*
2503	* @returns VINF_SSM_DONT_CALL_AGAIN.
2504	* @param pVM The cross context VM structure.
2505	* @param pSSM The saved state handle.
2506	* @param uPass The pass (0).
2507	*/
2508	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2509	{
2510	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2511	cpumR3SaveCpuId(pVM, pSSM);
2512	return VINF_SSM_DONT_CALL_AGAIN;
2513	}
2514
2515
2516	/**
2517	* Execute state save operation.
2518	*
2519	* @returns VBox status code.
2520	* @param pVM The cross context VM structure.
2521	* @param pSSM SSM operation handle.
2522	*/
2523	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2524	{
2525	/*
2526	* Save.
2527	*/
2528	SSMR3PutU32(pSSM, pVM->cCpus);
2529	SSMR3PutU32(pSSM, sizeof(pVM->aCpus[0].cpum.s.GuestMsrs.msr));
2530	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2531	{
2532	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2533
2534	SSMR3PutStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2535
2536	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2537	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2538	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2539	if (pGstCtx->fXStateMask != 0)
2540	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2541	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2542	{
2543	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2544	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2545	}
2546	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2547	{
2548	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2549	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2550	}
2551	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2552	{
2553	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2554	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2555	}
2556	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2557	{
2558	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2559	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2560	}
2561	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2562	{
2563	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2564	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2565	}
2566	if (pVM->cpum.s.GuestFeatures.fSvm)
2567	{
2568	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2569	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2570	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2571	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2572	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2573	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2574	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2575	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2576	g_aSvmHwvirtHostState, NULL /* pvUser */);
2577	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2578	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2579	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2580	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2581	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2582	}
2583	if (pVM->cpum.s.GuestFeatures.fVmx)
2584	{
2585	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2586	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2587	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2588	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2589	SSMR3PutU32(pSSM, (uint32_t)pGstCtx->hwvirt.vmx.enmDiag);
2590	SSMR3PutU32(pSSM, (uint32_t)pGstCtx->hwvirt.vmx.enmAbort);
2591	SSMR3PutU32(pSSM, pGstCtx->hwvirt.vmx.uAbortAux);
2592	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2593	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2594	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2595	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2596	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2597	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2598	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2599	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2600	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2601	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2602	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2603	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2604	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2605	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2606	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2607	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2608	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2609	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2610	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2611	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2612	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2613	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2614	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2615	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2616	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2617	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2618	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2619	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2620	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2621	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2622	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2623	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2624	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2625	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2626	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2627	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2628	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2629	}
2630	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2631	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2632	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2633	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2634	}
2635
2636	cpumR3SaveCpuId(pVM, pSSM);
2637	return VINF_SUCCESS;
2638	}
2639
2640
2641	/**
2642	* @callback_method_impl{FNSSMINTLOADPREP}
2643	*/
2644	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2645	{
2646	NOREF(pSSM);
2647	pVM->cpum.s.fPendingRestore = true;
2648	return VINF_SUCCESS;
2649	}
2650
2651
2652	/**
2653	* @callback_method_impl{FNSSMINTLOADEXEC}
2654	*/
2655	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2656	{
2657	int rc; /* Only for AssertRCReturn use. */
2658
2659	/*
2660	* Validate version.
2661	*/
2662	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
2663	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2664	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2665	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2666	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2667	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2668	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2669	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2670	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2671	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2672	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2673	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2674	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2675	{
2676	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2677	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2678	}
2679
2680	if (uPass == SSM_PASS_FINAL)
2681	{
2682	/*
2683	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2684	* really old SSM file versions.)
2685	*/
2686	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2687	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2688	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2689	SSMR3HandleSetGCPtrSize(pSSM, HC_ARCH_BITS == 32 ? sizeof(RTGCPTR32) : sizeof(RTGCPTR));
2690
2691	/*
2692	* Figure x86 and ctx field definitions to use for older states.
2693	*/
2694	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2695	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2696	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2697	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2698	{
2699	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2700	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2701	}
2702	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2703	{
2704	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2705	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2706	}
2707
2708	/*
2709	* The hyper state used to preceed the CPU count. Starting with
2710	* XSAVE it was moved down till after we've got the count.
2711	*/
2712	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2713	{
2714	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2715	{
2716	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2717	X86FXSTATE Ign;
2718	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2719	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2720	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2721	SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper),
2722	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2723	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2724	pVCpu->cpum.s.Hyper.rsp = uRSP;
2725	}
2726	}
2727
2728	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2729	{
2730	uint32_t cCpus;
2731	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2732	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2733	VERR_SSM_UNEXPECTED_DATA);
2734	}
2735	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2736	\|\| pVM->cCpus == 1,
2737	("cCpus=%u\n", pVM->cCpus),
2738	VERR_SSM_UNEXPECTED_DATA);
2739
2740	uint32_t cbMsrs = 0;
2741	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2742	{
2743	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2744	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2745	VERR_SSM_UNEXPECTED_DATA);
2746	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2747	VERR_SSM_UNEXPECTED_DATA);
2748	}
2749
2750	/*
2751	* Do the per-CPU restoring.
2752	*/
2753	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2754	{
2755	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2756	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2757
2758	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2759	{
2760	/*
2761	* The XSAVE saved state layout moved the hyper state down here.
2762	*/
2763	uint64_t uCR3 = pVCpu->cpum.s.Hyper.cr3;
2764	uint64_t uRSP = pVCpu->cpum.s.Hyper.rsp; /* see VMMR3Relocate(). */
2765	rc = SSMR3GetStructEx(pSSM, &pVCpu->cpum.s.Hyper, sizeof(pVCpu->cpum.s.Hyper), 0, g_aCpumCtxFields, NULL);
2766	pVCpu->cpum.s.Hyper.cr3 = uCR3;
2767	pVCpu->cpum.s.Hyper.rsp = uRSP;
2768	AssertRCReturn(rc, rc);
2769
2770	/*
2771	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2772	*/
2773	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2774	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2775	AssertRCReturn(rc, rc);
2776
2777	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2778	if (pGstCtx->fXStateMask != 0)
2779	{
2780	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2781	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2782	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2783	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2784	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2785	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2786	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2787	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2788	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2789	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2790	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2791	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2792	}
2793
2794	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2795	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2796	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2797	{
2798	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2799	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2800	VERR_CPUM_INVALID_XCR0);
2801	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2802	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2803	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2804	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2805	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2806	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2807	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2808	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2809	}
2810
2811	/* Check that the XCR1 is zero, as we don't implement it yet. */
2812	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2813
2814	/*
2815	* Restore the individual extended state components we support.
2816	*/
2817	if (pGstCtx->fXStateMask != 0)
2818	{
2819	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2820	0, g_aCpumXSaveHdrFields, NULL);
2821	AssertRCReturn(rc, rc);
2822	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2823	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2824	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2825	VERR_CPUM_INVALID_XSAVE_HDR);
2826	}
2827	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2828	{
2829	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2830	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2831	}
2832	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2833	{
2834	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2835	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2836	}
2837	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2838	{
2839	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2840	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2841	}
2842	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2843	{
2844	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2845	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2846	}
2847	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2848	{
2849	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2850	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2851	}
2852	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2853	{
2854	if (pVM->cpum.s.GuestFeatures.fSvm)
2855	{
2856	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2857	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2858	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2859	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2860	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2861	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2862	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2863	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2864	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2865	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2866	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2867	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2868	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2869	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2870	}
2871	}
2872	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM)
2873	{
2874	if (pVM->cpum.s.GuestFeatures.fVmx)
2875	{
2876	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2877	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2878	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2879	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2880	SSMR3GetU32(pSSM, (uint32_t *)&pGstCtx->hwvirt.vmx.enmDiag);
2881	SSMR3GetU32(pSSM, (uint32_t *)&pGstCtx->hwvirt.vmx.enmAbort);
2882	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.vmx.uAbortAux);
2883	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2884	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2885	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2886	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2887	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2888	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2889	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2890	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2891	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2892	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2893	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2894	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2895	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2896	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2897	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2898	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2899	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2900	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2901	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2902	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2903	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2904	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2905	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2906	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2907	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2908	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2909	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2910	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2911	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2912	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2913	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2914	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2915	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2916	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2917	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2918	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2919	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2920	}
2921	}
2922	}
2923	else
2924	{
2925	/*
2926	* Pre XSAVE saved state.
2927	*/
2928	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2929	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2930	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2931	}
2932
2933	/*
2934	* Restore a couple of flags and the MSRs.
2935	*/
2936	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2937	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2938
2939	rc = VINF_SUCCESS;
2940	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2941	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2942	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2943	{
2944	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2945	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2946	}
2947	AssertRCReturn(rc, rc);
2948
2949	/* REM and other may have cleared must-be-one fields in DR6 and
2950	DR7, fix these. */
2951	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2952	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2953	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2954	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2955	}
2956
2957	/* Older states does not have the internal selector register flags
2958	and valid selector value. Supply those. */
2959	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2960	{
2961	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2962	{
2963	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2964	bool const fValid = !VM_IS_RAW_MODE_ENABLED(pVM)
2965	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2966	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2967	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2968	if (fValid)
2969	{
2970	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2971	{
2972	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2973	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2974	}
2975
2976	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2977	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2978	}
2979	else
2980	{
2981	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2982	{
2983	paSelReg[iSelReg].fFlags = 0;
2984	paSelReg[iSelReg].ValidSel = 0;
2985	}
2986
2987	/* This might not be 104% correct, but I think it's close
2988	enough for all practical purposes... (REM always loaded
2989	LDTR registers.) */
2990	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2991	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2992	}
2993	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2994	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2995	}
2996	}
2997
2998	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2999	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3000	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3001	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3002	pVM->aCpus[iCpu].cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3003
3004	/*
3005	* A quick sanity check.
3006	*/
3007	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
3008	{
3009	PVMCPU pVCpu = &pVM->aCpus[iCpu];
3010	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3011	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3012	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3013	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3014	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3015	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3016	}
3017	}
3018
3019	pVM->cpum.s.fPendingRestore = false;
3020
3021	/*
3022	* Guest CPUIDs (and VMX MSR features).
3023	*/
3024	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3025	{
3026	CPUMMSRS GuestMsrs;
3027	RT_ZERO(GuestMsrs);
3028
3029	CPUMFEATURES BaseFeatures;
3030	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3031	if (fVmxGstFeat)
3032	{
3033	/*
3034	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3035	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3036	* here so we can compare them for compatibility after exploding guest features.
3037	*/
3038	BaseFeatures = pVM->cpum.s.GuestFeatures;
3039
3040	/* Use the VMX MSR features from the saved state while exploding guest features. */
3041	GuestMsrs.hwvirt.vmx = pVM->aCpus[0].cpum.s.Guest.hwvirt.vmx.Msrs;
3042	}
3043
3044	/* Load CPUID and explode guest features. */
3045	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3046	if (fVmxGstFeat)
3047	{
3048	/*
3049	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3050	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3051	* VMX features presented to the guest.
3052	*/
3053	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3054	if (!fIsCompat)
3055	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3056	}
3057	return rc;
3058	}
3059	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3060	}
3061
3062
3063	/**
3064	* @callback_method_impl{FNSSMINTLOADDONE}
3065	*/
3066	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3067	{
3068	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3069	return VINF_SUCCESS;
3070
3071	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3072	if (pVM->cpum.s.fPendingRestore)
3073	{
3074	LogRel(("CPUM: Missing state!\n"));
3075	return VERR_INTERNAL_ERROR_2;
3076	}
3077
3078	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3079	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3080	{
3081	PVMCPU pVCpu = &pVM->aCpus[idCpu];
3082
3083	/* Notify PGM of the NXE states in case they've changed. */
3084	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3085
3086	/* During init. this is done in CPUMR3InitCompleted(). */
3087	if (fSupportsLongMode)
3088	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3089	}
3090	return VINF_SUCCESS;
3091	}
3092
3093
3094	/**
3095	* Checks if the CPUM state restore is still pending.
3096	*
3097	* @returns true / false.
3098	* @param pVM The cross context VM structure.
3099	*/
3100	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3101	{
3102	return pVM->cpum.s.fPendingRestore;
3103	}
3104
3105
3106	/**
3107	* Formats the EFLAGS value into mnemonics.
3108	*
3109	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3110	* @param efl The EFLAGS value.
3111	*/
3112	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3113	{
3114	/*
3115	* Format the flags.
3116	*/
3117	static const struct
3118	{
3119	const char pszSet; const char pszClear; uint32_t fFlag;
3120	} s_aFlags[] =
3121	{
3122	{ "vip",NULL, X86_EFL_VIP },
3123	{ "vif",NULL, X86_EFL_VIF },
3124	{ "ac", NULL, X86_EFL_AC },
3125	{ "vm", NULL, X86_EFL_VM },
3126	{ "rf", NULL, X86_EFL_RF },
3127	{ "nt", NULL, X86_EFL_NT },
3128	{ "ov", "nv", X86_EFL_OF },
3129	{ "dn", "up", X86_EFL_DF },
3130	{ "ei", "di", X86_EFL_IF },
3131	{ "tf", NULL, X86_EFL_TF },
3132	{ "nt", "pl", X86_EFL_SF },
3133	{ "nz", "zr", X86_EFL_ZF },
3134	{ "ac", "na", X86_EFL_AF },
3135	{ "po", "pe", X86_EFL_PF },
3136	{ "cy", "nc", X86_EFL_CF },
3137	};
3138	char *psz = pszEFlags;
3139	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3140	{
3141	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3142	if (pszAdd)
3143	{
3144	strcpy(psz, pszAdd);
3145	psz += strlen(pszAdd);
3146	*psz++ = ' ';
3147	}
3148	}
3149	psz[-1] = '\0';
3150	}
3151
3152
3153	/**
3154	* Formats a full register dump.
3155	*
3156	* @param pVM The cross context VM structure.
3157	* @param pCtx The context to format.
3158	* @param pCtxCore The context core to format.
3159	* @param pHlp Output functions.
3160	* @param enmType The dump type.
3161	* @param pszPrefix Register name prefix.
3162	*/
3163	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3164	const char *pszPrefix)
3165	{
3166	NOREF(pVM);
3167
3168	/*
3169	* Format the EFLAGS.
3170	*/
3171	uint32_t efl = pCtxCore->eflags.u32;
3172	char szEFlags[80];
3173	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3174
3175	/*
3176	* Format the registers.
3177	*/
3178	switch (enmType)
3179	{
3180	case CPUMDUMPTYPE_TERSE:
3181	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3182	pHlp->pfnPrintf(pHlp,
3183	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3184	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3185	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3186	"%sr14=%016RX64 %sr15=%016RX64\n"
3187	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3188	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3189	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3190	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3191	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3192	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3193	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3194	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3195	else
3196	pHlp->pfnPrintf(pHlp,
3197	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3198	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3199	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3200	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3201	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3202	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3203	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3204	break;
3205
3206	case CPUMDUMPTYPE_DEFAULT:
3207	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3208	pHlp->pfnPrintf(pHlp,
3209	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3210	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3211	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3212	"%sr14=%016RX64 %sr15=%016RX64\n"
3213	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3214	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3215	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3216	,
3217	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3218	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3219	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3220	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3221	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3222	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3223	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3224	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3225	else
3226	pHlp->pfnPrintf(pHlp,
3227	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3228	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3229	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3230	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3231	,
3232	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3233	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3234	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3235	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3236	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3237	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3238	break;
3239
3240	case CPUMDUMPTYPE_VERBOSE:
3241	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3242	pHlp->pfnPrintf(pHlp,
3243	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3244	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3245	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3246	"%sr14=%016RX64 %sr15=%016RX64\n"
3247	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3248	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3249	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3250	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3251	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3252	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3253	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3254	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3255	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3256	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3257	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3258	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3259	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3260	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3261	,
3262	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3263	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3264	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3265	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3266	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3267	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3268	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3269	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3270	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3271	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3272	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3273	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3274	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3275	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3276	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3277	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3278	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3279	else
3280	pHlp->pfnPrintf(pHlp,
3281	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3282	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3283	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3284	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3285	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3286	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3287	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3288	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3289	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3290	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3291	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3292	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3293	,
3294	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3295	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3296	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3297	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3298	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3299	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3300	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3301	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3302	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3303	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3304	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3305	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3306
3307	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3308	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3309	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3310	if (pCtx->CTX_SUFF(pXState))
3311	{
3312	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
3313	pHlp->pfnPrintf(pHlp,
3314	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3315	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3316	,
3317	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3318	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3319	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3320	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3321	);
3322	/*
3323	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3324	* not (FP)R0-7 as Intel SDM suggests.
3325	*/
3326	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3327	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3328	{
3329	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3330	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3331	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3332	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3333	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3334	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3335	iExponent -= 16383; /* subtract bias */
3336	/** @todo This isn't entirenly correct and needs more work! */
3337	pHlp->pfnPrintf(pHlp,
3338	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3339	pszPrefix, iST, pszPrefix, iFPR,
3340	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3341	uTag, chSign, iInteger, u64Fraction, iExponent);
3342	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3343	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3344	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3345	else
3346	pHlp->pfnPrintf(pHlp, "\n");
3347	}
3348
3349	/* XMM/YMM/ZMM registers. */
3350	if (pCtx->fXStateMask & XSAVE_C_YMM)
3351	{
3352	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3353	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3354	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3355	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3356	pszPrefix, i, i < 10 ? " " : "",
3357	pYmmHiCtx->aYmmHi[i].au32[3],
3358	pYmmHiCtx->aYmmHi[i].au32[2],
3359	pYmmHiCtx->aYmmHi[i].au32[1],
3360	pYmmHiCtx->aYmmHi[i].au32[0],
3361	pFpuCtx->aXMM[i].au32[3],
3362	pFpuCtx->aXMM[i].au32[2],
3363	pFpuCtx->aXMM[i].au32[1],
3364	pFpuCtx->aXMM[i].au32[0]);
3365	else
3366	{
3367	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3368	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3369	pHlp->pfnPrintf(pHlp,
3370	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3371	pszPrefix, i, i < 10 ? " " : "",
3372	pZmmHi256->aHi256Regs[i].au32[7],
3373	pZmmHi256->aHi256Regs[i].au32[6],
3374	pZmmHi256->aHi256Regs[i].au32[5],
3375	pZmmHi256->aHi256Regs[i].au32[4],
3376	pZmmHi256->aHi256Regs[i].au32[3],
3377	pZmmHi256->aHi256Regs[i].au32[2],
3378	pZmmHi256->aHi256Regs[i].au32[1],
3379	pZmmHi256->aHi256Regs[i].au32[0],
3380	pYmmHiCtx->aYmmHi[i].au32[3],
3381	pYmmHiCtx->aYmmHi[i].au32[2],
3382	pYmmHiCtx->aYmmHi[i].au32[1],
3383	pYmmHiCtx->aYmmHi[i].au32[0],
3384	pFpuCtx->aXMM[i].au32[3],
3385	pFpuCtx->aXMM[i].au32[2],
3386	pFpuCtx->aXMM[i].au32[1],
3387	pFpuCtx->aXMM[i].au32[0]);
3388
3389	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3390	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3391	pHlp->pfnPrintf(pHlp,
3392	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3393	pszPrefix, i + 16,
3394	pZmm16Hi->aRegs[i].au32[15],
3395	pZmm16Hi->aRegs[i].au32[14],
3396	pZmm16Hi->aRegs[i].au32[13],
3397	pZmm16Hi->aRegs[i].au32[12],
3398	pZmm16Hi->aRegs[i].au32[11],
3399	pZmm16Hi->aRegs[i].au32[10],
3400	pZmm16Hi->aRegs[i].au32[9],
3401	pZmm16Hi->aRegs[i].au32[8],
3402	pZmm16Hi->aRegs[i].au32[7],
3403	pZmm16Hi->aRegs[i].au32[6],
3404	pZmm16Hi->aRegs[i].au32[5],
3405	pZmm16Hi->aRegs[i].au32[4],
3406	pZmm16Hi->aRegs[i].au32[3],
3407	pZmm16Hi->aRegs[i].au32[2],
3408	pZmm16Hi->aRegs[i].au32[1],
3409	pZmm16Hi->aRegs[i].au32[0]);
3410	}
3411	}
3412	else
3413	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3414	pHlp->pfnPrintf(pHlp,
3415	i & 1
3416	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3417	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3418	pszPrefix, i, i < 10 ? " " : "",
3419	pFpuCtx->aXMM[i].au32[3],
3420	pFpuCtx->aXMM[i].au32[2],
3421	pFpuCtx->aXMM[i].au32[1],
3422	pFpuCtx->aXMM[i].au32[0]);
3423
3424	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3425	{
3426	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3427	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3428	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3429	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3430	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3431	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3432	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3433	}
3434
3435	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3436	{
3437	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3438	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3439	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3440	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3441	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3442	}
3443
3444	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3445	{
3446	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3447	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3448	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3449	}
3450
3451	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3452	if (pFpuCtx->au32RsrvdRest[i])
3453	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3454	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3455	}
3456
3457	pHlp->pfnPrintf(pHlp,
3458	"%sEFER =%016RX64\n"
3459	"%sPAT =%016RX64\n"
3460	"%sSTAR =%016RX64\n"
3461	"%sCSTAR =%016RX64\n"
3462	"%sLSTAR =%016RX64\n"
3463	"%sSFMASK =%016RX64\n"
3464	"%sKERNELGSBASE =%016RX64\n",
3465	pszPrefix, pCtx->msrEFER,
3466	pszPrefix, pCtx->msrPAT,
3467	pszPrefix, pCtx->msrSTAR,
3468	pszPrefix, pCtx->msrCSTAR,
3469	pszPrefix, pCtx->msrLSTAR,
3470	pszPrefix, pCtx->msrSFMASK,
3471	pszPrefix, pCtx->msrKERNELGSBASE);
3472	break;
3473	}
3474	}
3475
3476
3477	/**
3478	* Display all cpu states and any other cpum info.
3479	*
3480	* @param pVM The cross context VM structure.
3481	* @param pHlp The info helper functions.
3482	* @param pszArgs Arguments, ignored.
3483	*/
3484	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3485	{
3486	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3487	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3488	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3489	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3490	cpumR3InfoHost(pVM, pHlp, pszArgs);
3491	}
3492
3493
3494	/**
3495	* Parses the info argument.
3496	*
3497	* The argument starts with 'verbose', 'terse' or 'default' and then
3498	* continues with the comment string.
3499	*
3500	* @param pszArgs The pointer to the argument string.
3501	* @param penmType Where to store the dump type request.
3502	* @param ppszComment Where to store the pointer to the comment string.
3503	*/
3504	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3505	{
3506	if (!pszArgs)
3507	{
3508	*penmType = CPUMDUMPTYPE_DEFAULT;
3509	*ppszComment = "";
3510	}
3511	else
3512	{
3513	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3514	{
3515	pszArgs += 7;
3516	*penmType = CPUMDUMPTYPE_VERBOSE;
3517	}
3518	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3519	{
3520	pszArgs += 5;
3521	*penmType = CPUMDUMPTYPE_TERSE;
3522	}
3523	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3524	{
3525	pszArgs += 7;
3526	*penmType = CPUMDUMPTYPE_DEFAULT;
3527	}
3528	else
3529	*penmType = CPUMDUMPTYPE_DEFAULT;
3530	*ppszComment = RTStrStripL(pszArgs);
3531	}
3532	}
3533
3534
3535	/**
3536	* Display the guest cpu state.
3537	*
3538	* @param pVM The cross context VM structure.
3539	* @param pHlp The info helper functions.
3540	* @param pszArgs Arguments.
3541	*/
3542	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3543	{
3544	CPUMDUMPTYPE enmType;
3545	const char *pszComment;
3546	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3547
3548	PVMCPU pVCpu = VMMGetCpu(pVM);
3549	if (!pVCpu)
3550	pVCpu = &pVM->aCpus[0];
3551
3552	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3553
3554	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3555	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3556	}
3557
3558
3559	/**
3560	* Displays an SVM VMCB control area.
3561	*
3562	* @param pHlp The info helper functions.
3563	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3564	* @param pszPrefix Caller specified string prefix.
3565	*/
3566	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3567	{
3568	AssertReturnVoid(pHlp);
3569	AssertReturnVoid(pVmcbCtrl);
3570
3571	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3572	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3573	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3574	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3575	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3576	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3577	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3578	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3579	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3580	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3581	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3582	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3583	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3584	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3585	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3586	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3587	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3588	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3589	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3590	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3591	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3592	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3593	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3594	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3595	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3596	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3597	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3598	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3599	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3600	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3601	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3602	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3603	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3604	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3605	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3606	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3607	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3608	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3609	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3610	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3611	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3612	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3613	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3614	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3615	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3616	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3617	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3618	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3619	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3620	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3621	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3622	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3623	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3624	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3625	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3626	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3627	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3628	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3629	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3630	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3631	}
3632
3633
3634	/**
3635	* Helper for dumping the SVM VMCB selector registers.
3636	*
3637	* @param pHlp The info helper functions.
3638	* @param pSel Pointer to the SVM selector register.
3639	* @param pszName Name of the selector.
3640	* @param pszPrefix Caller specified string prefix.
3641	*/
3642	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3643	{
3644	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3645	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3646	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3647	}
3648
3649
3650	/**
3651	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3652	*
3653	* @param pHlp The info helper functions.
3654	* @param pXdtr Pointer to the descriptor table register.
3655	* @param pszName Name of the descriptor table register.
3656	* @param pszPrefix Caller specified string prefix.
3657	*/
3658	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3659	{
3660	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3661	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3662	}
3663
3664
3665	/**
3666	* Displays an SVM VMCB state-save area.
3667	*
3668	* @param pHlp The info helper functions.
3669	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3670	* @param pszPrefix Caller specified string prefix.
3671	*/
3672	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3673	{
3674	AssertReturnVoid(pHlp);
3675	AssertReturnVoid(pVmcbStateSave);
3676
3677	char szEFlags[80];
3678	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3679
3680	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3681	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3682	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3683	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3684	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3685	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3686	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3687	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3688	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3689	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3690	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3691	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3692	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3693	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3694	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3695	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3696	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3697	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3698	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3699	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3700	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3701	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3702	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3703	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3704	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3705	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3706	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3707	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3708	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3709	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3710	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3711	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3712	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3713	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3714	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3715	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3716	}
3717
3718
3719	/**
3720	* Displays a virtual-VMCS.
3721	*
3722	* @param pHlp The info helper functions.
3723	* @param pVmcs Pointer to a virtual VMCS.
3724	* @param pszPrefix Caller specified string prefix.
3725	*/
3726	static void cpumR3InfoVmxVmcs(PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3727	{
3728	AssertReturnVoid(pHlp);
3729	AssertReturnVoid(pVmcs);
3730
3731	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3732	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3733	do { \
3734	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3735	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3736	} while (0)
3737
3738	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3739	do { \
3740	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3741	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3742	} while (0)
3743
3744	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3745	do { \
3746	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3747	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3748	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3749	} while (0)
3750
3751	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3752	do { \
3753	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3754	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3755	} while (0)
3756
3757	/* Header. */
3758	{
3759	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3760	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3761	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, HMGetVmxAbortDesc(pVmcs->enmVmxAbort));
3762	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, HMGetVmxVmcsStateDesc(pVmcs->fVmcsState));
3763	}
3764
3765	/* Control fields. */
3766	{
3767	/* 16-bit. */
3768	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3769	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3770	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3771	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3772
3773	/* 32-bit. */
3774	pHlp->pfnPrintf(pHlp, " %sPinCtls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3775	pHlp->pfnPrintf(pHlp, " %sProcCtls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3776	pHlp->pfnPrintf(pHlp, " %sProcCtls2 = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3777	pHlp->pfnPrintf(pHlp, " %sExitCtls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3778	pHlp->pfnPrintf(pHlp, " %sEntryCtls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3779	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3780	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3781	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3782	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3783	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3784	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3785	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3786	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3787	{
3788	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3789	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3790	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3791	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxEntryIntInfoTypeDesc(uType));
3792	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3793	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3794	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3795	}
3796	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3797	pHlp->pfnPrintf(pHlp, " %sVM-entry instruction len = %u bytes\n", pszPrefix, pVmcs->u32EntryInstrLen);
3798	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3799	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3800	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3801
3802	/* 64-bit. */
3803	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3804	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3805	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3806	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3807	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3808	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3809	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3810	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3811	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3812	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3813	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3814	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3815	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3816	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3817	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3818	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3819	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3820	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3821	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3822	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3823	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3824	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3825	pHlp->pfnPrintf(pHlp, " %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u);
3826	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEnclsBitmap.u);
3827	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3828
3829	/* Natural width. */
3830	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3831	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3832	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3833	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3834	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3835	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3836	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3837	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3838	}
3839
3840	/* Guest state. */
3841	{
3842	char szEFlags[80];
3843	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3844	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3845
3846	/* 16-bit. */
3847	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "cs", pszPrefix);
3848	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "ss", pszPrefix);
3849	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "es", pszPrefix);
3850	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "ds", pszPrefix);
3851	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "fs", pszPrefix);
3852	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "gs", pszPrefix);
3853	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "ldtr", pszPrefix);
3854	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "tr", pszPrefix);
3855	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3856	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3857	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3858	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3859
3860	/* 32-bit. */
3861	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3862	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3863	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3864	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3865	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3866
3867	/* 64-bit. */
3868	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3869	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3870	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3871	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3872	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3873	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3874	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3875	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3876	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3877	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3878
3879	/* Natural width. */
3880	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3881	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3882	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3883	pHlp->pfnPrintf(pHlp, " %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3884	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3885	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3886	pHlp->pfnPrintf(pHlp, " %srflags = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3887	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpt.u);
3888	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3889	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3890	}
3891
3892	/* Host state. */
3893	{
3894	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3895
3896	/* 16-bit. */
3897	pHlp->pfnPrintf(pHlp, " %scs = %#RX16\n", pszPrefix, pVmcs->HostCs);
3898	pHlp->pfnPrintf(pHlp, " %sss = %#RX16\n", pszPrefix, pVmcs->HostSs);
3899	pHlp->pfnPrintf(pHlp, " %sds = %#RX16\n", pszPrefix, pVmcs->HostDs);
3900	pHlp->pfnPrintf(pHlp, " %ses = %#RX16\n", pszPrefix, pVmcs->HostEs);
3901	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "fs", pszPrefix);
3902	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "gs", pszPrefix);
3903	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "tr", pszPrefix);
3904	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3905	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3906
3907	/* 32-bit. */
3908	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3909
3910	/* 64-bit. */
3911	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3912	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3913	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3914
3915	/* Natural width. */
3916	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3917	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3918	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3919	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3920	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3921	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3922	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3923	}
3924
3925	/* Read-only fields. */
3926	{
3927	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3928
3929	/* 16-bit (none currently). */
3930
3931	/* 32-bit. */
3932	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3933	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3934	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3935	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3936	{
3937	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3938	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3939	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3940	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxExitIntInfoTypeDesc(uType));
3941	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3942	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3943	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3944	}
3945	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3946	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3947	{
3948	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3949	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3950	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3951	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, HMGetVmxIdtVectoringInfoTypeDesc(uType));
3952	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3953	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3954	}
3955	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3956	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u bytes\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3957	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3958
3959	/* 64-bit. */
3960	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3961
3962	/* Natural width. */
3963	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3964	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3965	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3966	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3967	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3968	}
3969
3970	#undef CPUMVMX_DUMP_HOST_XDTR
3971	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3972	#undef CPUMVMX_DUMP_GUEST_SEGREG
3973	#undef CPUMVMX_DUMP_GUEST_XDTR
3974	}
3975
3976
3977	/**
3978	* Display the guest's hardware-virtualization cpu state.
3979	*
3980	* @param pVM The cross context VM structure.
3981	* @param pHlp The info helper functions.
3982	* @param pszArgs Arguments, ignored.
3983	*/
3984	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3985	{
3986	RT_NOREF(pszArgs);
3987
3988	PVMCPU pVCpu = VMMGetCpu(pVM);
3989	if (!pVCpu)
3990	pVCpu = &pVM->aCpus[0];
3991
3992	/*
3993	* Figure out what to dump.
3994	*
3995	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
3996	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
3997	* dump hwvirt. state when the guest CPU is executing a nested-guest.
3998	*/
3999	/** @todo perhaps make this configurable through pszArgs, depending on how much
4000	* noise we wish to accept when nested hwvirt. isn't used. */
4001	#define CPUMHWVIRTDUMP_NONE (0)
4002	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
4003	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
4004	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
4005	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
4006
4007	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4008	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
4009	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4010	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4011	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
4012	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
4013	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
4014	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
4015	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
4016
4017	/*
4018	* Dump it.
4019	*/
4020	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4021
4022	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
4023	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
4024
4025	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
4026	":" : "");
4027	if (fDumpState & CPUMHWVIRTDUMP_SVM)
4028	{
4029	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4030
4031	char szEFlags[80];
4032	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4033	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4034	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4035	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4036	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
4037	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4038	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
4039	pHlp->pfnPrintf(pHlp, " HostState:\n");
4040	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4041	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4042	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4043	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4044	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4045	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4046	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4047	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4048	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
4049	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4050	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4051	pSel = &pCtx->hwvirt.svm.HostState.cs;
4052	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4053	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4054	pSel = &pCtx->hwvirt.svm.HostState.ss;
4055	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4056	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4057	pSel = &pCtx->hwvirt.svm.HostState.ds;
4058	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4059	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4060	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4061	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4062	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4063	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4064	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4065	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4066	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4067	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
4068	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
4069	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
4070	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
4071	}
4072
4073	if (fDumpState & CPUMHWVIRTDUMP_VMX)
4074	{
4075	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4076	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4077	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4078	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4079	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, HMGetVmxAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4080	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4081	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4082	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4083	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4084	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4085	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4086	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4087	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4088	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4089	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4090	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4091	cpumR3InfoVmxVmcs(pHlp, pCtx->hwvirt.vmx.pVmcsR3, " " /* pszPrefix */);
4092	}
4093
4094	#undef CPUMHWVIRTDUMP_NONE
4095	#undef CPUMHWVIRTDUMP_COMMON
4096	#undef CPUMHWVIRTDUMP_SVM
4097	#undef CPUMHWVIRTDUMP_VMX
4098	#undef CPUMHWVIRTDUMP_LAST
4099	#undef CPUMHWVIRTDUMP_ALL
4100	}
4101
4102	/**
4103	* Display the current guest instruction
4104	*
4105	* @param pVM The cross context VM structure.
4106	* @param pHlp The info helper functions.
4107	* @param pszArgs Arguments, ignored.
4108	*/
4109	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4110	{
4111	NOREF(pszArgs);
4112
4113	PVMCPU pVCpu = VMMGetCpu(pVM);
4114	if (!pVCpu)
4115	pVCpu = &pVM->aCpus[0];
4116
4117	char szInstruction[256];
4118	szInstruction[0] = '\0';
4119	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4120	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4121	}
4122
4123
4124	/**
4125	* Display the hypervisor cpu state.
4126	*
4127	* @param pVM The cross context VM structure.
4128	* @param pHlp The info helper functions.
4129	* @param pszArgs Arguments, ignored.
4130	*/
4131	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4132	{
4133	PVMCPU pVCpu = VMMGetCpu(pVM);
4134	if (!pVCpu)
4135	pVCpu = &pVM->aCpus[0];
4136
4137	CPUMDUMPTYPE enmType;
4138	const char *pszComment;
4139	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4140	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4141	cpumR3InfoOne(pVM, &pVCpu->cpum.s.Hyper, CPUMCTX2CORE(&pVCpu->cpum.s.Hyper), pHlp, enmType, ".");
4142	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4143	}
4144
4145
4146	/**
4147	* Display the host cpu state.
4148	*
4149	* @param pVM The cross context VM structure.
4150	* @param pHlp The info helper functions.
4151	* @param pszArgs Arguments, ignored.
4152	*/
4153	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4154	{
4155	CPUMDUMPTYPE enmType;
4156	const char *pszComment;
4157	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4158	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4159
4160	PVMCPU pVCpu = VMMGetCpu(pVM);
4161	if (!pVCpu)
4162	pVCpu = &pVM->aCpus[0];
4163	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4164
4165	/*
4166	* Format the EFLAGS.
4167	*/
4168	#if HC_ARCH_BITS == 32
4169	uint32_t efl = pCtx->eflags.u32;
4170	#else
4171	uint64_t efl = pCtx->rflags;
4172	#endif
4173	char szEFlags[80];
4174	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4175
4176	/*
4177	* Format the registers.
4178	*/
4179	#if HC_ARCH_BITS == 32
4180	pHlp->pfnPrintf(pHlp,
4181	"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
4182	"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
4183	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
4184	"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
4185	"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
4186	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4187	,
4188	/pCtx->eax,/ pCtx->ebx, /pCtx->ecx, pCtx->edx,/ pCtx->esi, pCtx->edi,
4189	/pCtx->eip,/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
4190	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4191	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3, pCtx->cr4,
4192	pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
4193	(uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->ldtr,
4194	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
4195	#else
4196	pHlp->pfnPrintf(pHlp,
4197	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4198	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4199	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4200	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4201	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4202	"r14=%016RX64 r15=%016RX64\n"
4203	"iopl=%d %31s\n"
4204	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4205	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4206	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4207	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4208	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4209	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4210	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4211	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4212	,
4213	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4214	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4215	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4216	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4217	pCtx->r11, pCtx->r12, pCtx->r13,
4218	pCtx->r14, pCtx->r15,
4219	X86_EFL_GET_IOPL(efl), szEFlags,
4220	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4221	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4222	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4223	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4224	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4225	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4226	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4227	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4228	#endif
4229	}
4230
4231	/**
4232	* Structure used when disassembling and instructions in DBGF.
4233	* This is used so the reader function can get the stuff it needs.
4234	*/
4235	typedef struct CPUMDISASSTATE
4236	{
4237	/** Pointer to the CPU structure. */
4238	PDISCPUSTATE pCpu;
4239	/** Pointer to the VM. */
4240	PVM pVM;
4241	/** Pointer to the VMCPU. */
4242	PVMCPU pVCpu;
4243	/** Pointer to the first byte in the segment. */
4244	RTGCUINTPTR GCPtrSegBase;
4245	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4246	RTGCUINTPTR GCPtrSegEnd;
4247	/** The size of the segment minus 1. */
4248	RTGCUINTPTR cbSegLimit;
4249	/** Pointer to the current page - R3 Ptr. */
4250	void const *pvPageR3;
4251	/** Pointer to the current page - GC Ptr. */
4252	RTGCPTR pvPageGC;
4253	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4254	PGMPAGEMAPLOCK PageMapLock;
4255	/** Whether the PageMapLock is valid or not. */
4256	bool fLocked;
4257	/** 64 bits mode or not. */
4258	bool f64Bits;
4259	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4260
4261
4262	/**
4263	* @callback_method_impl{FNDISREADBYTES}
4264	*/
4265	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4266	{
4267	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4268	for (;;)
4269	{
4270	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4271
4272	/*
4273	* Need to update the page translation?
4274	*/
4275	if ( !pState->pvPageR3
4276	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4277	{
4278	int rc = VINF_SUCCESS;
4279
4280	/* translate the address */
4281	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4282	if ( VM_IS_RAW_MODE_ENABLED(pState->pVM)
4283	&& MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
4284	{
4285	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
4286	if (!pState->pvPageR3)
4287	rc = VERR_INVALID_POINTER;
4288	}
4289	else
4290	{
4291	/* Release mapping lock previously acquired. */
4292	if (pState->fLocked)
4293	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4294	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4295	pState->fLocked = RT_SUCCESS_NP(rc);
4296	}
4297	if (RT_FAILURE(rc))
4298	{
4299	pState->pvPageR3 = NULL;
4300	return rc;
4301	}
4302	}
4303
4304	/*
4305	* Check the segment limit.
4306	*/
4307	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4308	return VERR_OUT_OF_SELECTOR_BOUNDS;
4309
4310	/*
4311	* Calc how much we can read.
4312	*/
4313	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4314	if (!pState->f64Bits)
4315	{
4316	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4317	if (cb > cbSeg && cbSeg)
4318	cb = cbSeg;
4319	}
4320	if (cb > cbMaxRead)
4321	cb = cbMaxRead;
4322
4323	/*
4324	* Read and advance or exit.
4325	*/
4326	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4327	offInstr += (uint8_t)cb;
4328	if (cb >= cbMinRead)
4329	{
4330	pDis->cbCachedInstr = offInstr;
4331	return VINF_SUCCESS;
4332	}
4333	cbMinRead -= (uint8_t)cb;
4334	cbMaxRead -= (uint8_t)cb;
4335	}
4336	}
4337
4338
4339	/**
4340	* Disassemble an instruction and return the information in the provided structure.
4341	*
4342	* @returns VBox status code.
4343	* @param pVM The cross context VM structure.
4344	* @param pVCpu The cross context virtual CPU structure.
4345	* @param pCtx Pointer to the guest CPU context.
4346	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4347	* @param pCpu Disassembly state.
4348	* @param pszPrefix String prefix for logging (debug only).
4349	*
4350	*/
4351	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4352	const char *pszPrefix)
4353	{
4354	CPUMDISASSTATE State;
4355	int rc;
4356
4357	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4358	State.pCpu = pCpu;
4359	State.pvPageGC = 0;
4360	State.pvPageR3 = NULL;
4361	State.pVM = pVM;
4362	State.pVCpu = pVCpu;
4363	State.fLocked = false;
4364	State.f64Bits = false;
4365
4366	/*
4367	* Get selector information.
4368	*/
4369	DISCPUMODE enmDisCpuMode;
4370	if ( (pCtx->cr0 & X86_CR0_PE)
4371	&& pCtx->eflags.Bits.u1VM == 0)
4372	{
4373	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4374	{
4375	# ifdef VBOX_WITH_RAW_MODE_NOT_R0
4376	CPUMGuestLazyLoadHiddenSelectorReg(pVCpu, &pCtx->cs);
4377	# endif
4378	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4379	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4380	}
4381	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4382	State.GCPtrSegBase = pCtx->cs.u64Base;
4383	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4384	State.cbSegLimit = pCtx->cs.u32Limit;
4385	enmDisCpuMode = (State.f64Bits)
4386	? DISCPUMODE_64BIT
4387	: pCtx->cs.Attr.n.u1DefBig
4388	? DISCPUMODE_32BIT
4389	: DISCPUMODE_16BIT;
4390	}
4391	else
4392	{
4393	/* real or V86 mode */
4394	enmDisCpuMode = DISCPUMODE_16BIT;
4395	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4396	State.GCPtrSegEnd = 0xFFFFFFFF;
4397	State.cbSegLimit = 0xFFFFFFFF;
4398	}
4399
4400	/*
4401	* Disassemble the instruction.
4402	*/
4403	uint32_t cbInstr;
4404	#ifndef LOG_ENABLED
4405	RT_NOREF_PV(pszPrefix);
4406	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4407	if (RT_SUCCESS(rc))
4408	{
4409	#else
4410	char szOutput[160];
4411	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4412	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4413	if (RT_SUCCESS(rc))
4414	{
4415	/* log it */
4416	if (pszPrefix)
4417	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4418	else
4419	Log(("%s", szOutput));
4420	#endif
4421	rc = VINF_SUCCESS;
4422	}
4423	else
4424	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4425
4426	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4427	if (State.fLocked)
4428	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4429
4430	return rc;
4431	}
4432
4433
4434
4435	/**
4436	* API for controlling a few of the CPU features found in CR4.
4437	*
4438	* Currently only X86_CR4_TSD is accepted as input.
4439	*
4440	* @returns VBox status code.
4441	*
4442	* @param pVM The cross context VM structure.
4443	* @param fOr The CR4 OR mask.
4444	* @param fAnd The CR4 AND mask.
4445	*/
4446	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4447	{
4448	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4449	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4450
4451	pVM->cpum.s.CR4.OrMask &= fAnd;
4452	pVM->cpum.s.CR4.OrMask \|= fOr;
4453
4454	return VINF_SUCCESS;
4455	}
4456
4457
4458	/**
4459	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4460	*
4461	* Only REM should ever call this function!
4462	*
4463	* @returns The changed flags.
4464	* @param pVCpu The cross context virtual CPU structure.
4465	* @param puCpl Where to return the current privilege level (CPL).
4466	*/
4467	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4468	{
4469	Assert(!pVCpu->cpum.s.fRawEntered);
4470	Assert(!pVCpu->cpum.s.fRemEntered);
4471
4472	/*
4473	* Get the CPL first.
4474	*/
4475	*puCpl = CPUMGetGuestCPL(pVCpu);
4476
4477	/*
4478	* Get and reset the flags.
4479	*/
4480	uint32_t fFlags = pVCpu->cpum.s.fChanged;
4481	pVCpu->cpum.s.fChanged = 0;
4482
4483	/** @todo change the switcher to use the fChanged flags. */
4484	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4485	{
4486	fFlags \|= CPUM_CHANGED_FPU_REM;
4487	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4488	}
4489
4490	pVCpu->cpum.s.fRemEntered = true;
4491	return fFlags;
4492	}
4493
4494
4495	/**
4496	* Leaves REM.
4497	*
4498	* @param pVCpu The cross context virtual CPU structure.
4499	* @param fNoOutOfSyncSels This is @c false if there are out of sync
4500	* registers.
4501	*/
4502	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4503	{
4504	Assert(!pVCpu->cpum.s.fRawEntered);
4505	Assert(pVCpu->cpum.s.fRemEntered);
4506
4507	RT_NOREF_PV(fNoOutOfSyncSels);
4508
4509	pVCpu->cpum.s.fRemEntered = false;
4510	}
4511
4512
4513	/**
4514	* Called when the ring-3 init phase completes.
4515	*
4516	* @returns VBox status code.
4517	* @param pVM The cross context VM structure.
4518	* @param enmWhat Which init phase.
4519	*/
4520	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4521	{
4522	switch (enmWhat)
4523	{
4524	case VMINITCOMPLETED_RING3:
4525	{
4526	/*
4527	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4528	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4529	*/
4530	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4531	for (VMCPUID i = 0; i < pVM->cCpus; i++)
4532	{
4533	PVMCPU pVCpu = &pVM->aCpus[i];
4534	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4535	if (fSupportsLongMode)
4536	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4537	}
4538
4539	/* Register statistic counters for MSRs. */
4540	cpumR3MsrRegStats(pVM);
4541	break;
4542	}
4543
4544	default:
4545	break;
4546	}
4547	return VINF_SUCCESS;
4548	}
4549
4550
4551	/**
4552	* Called when the ring-0 init phases completed.
4553	*
4554	* @param pVM The cross context VM structure.
4555	*/
4556	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4557	{
4558	/*
4559	* Enable log buffering as we're going to log a lot of lines.
4560	*/
4561	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4562
4563	/*
4564	* Log the cpuid.
4565	*/
4566	RTCPUSET OnlineSet;
4567	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4568	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4569	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4570	RTCPUID cCores = RTMpGetCoreCount();
4571	if (cCores)
4572	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4573	LogRel(("*********************** CPUID dump **********************\n"));
4574	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4575	LogRel(("\n"));
4576	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4577	LogRel(("****************** End of CPUID dump ********************\n"));
4578
4579	/*
4580	* Log VT-x extended features.
4581	*
4582	* SVM features are currently all covered under CPUID so there is nothing
4583	* to do here for SVM.
4584	*/
4585	if (pVM->cpum.s.HostFeatures.fVmx)
4586	{
4587	LogRel(("********************* VT-x features *********************\n"));
4588	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4589	LogRel(("\n"));
4590	LogRel(("***************** End of VT-x features ******************\n"));
4591	}
4592
4593	/*
4594	* Restore the log buffering state to what it was previously.
4595	*/
4596	RTLogRelSetBuffering(fOldBuffered);
4597	}
4598

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 78327

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