CPUM.cpp@ 80387

Last change on this file since 80387 was 80387, checked in by vboxsync, 5 years ago
VMM: Nested VMX: bugref:9180 Renamed u64GuestPendingDbgXcpt to u64GuestPendingDbgXcpts to better match the spec.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 237.6 KB

Line
1	/* $Id: CPUM.cpp 80387 2019-08-22 14:44:42Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/hm.h>
120	#include <VBox/vmm/hmvmxinline.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
339	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
340	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
341	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
342
343	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
344	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
345	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
346	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
347	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
348	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
349	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
350	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
351	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
352	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
353	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
354
355	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
356	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
357	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
358	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
359	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
360	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
361	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
362	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
363
364	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
365	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
366	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
367	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
369	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
370	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
371	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
373	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
374	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
378	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
379	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
380	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
381	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
382	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
383
384	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
385	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
386	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
387	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
388	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
389	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
390	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
391	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
392	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
393
394	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
395	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
396	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
397	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
398	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
399	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
400	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
401	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
402	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
403	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
404	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
405	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
406	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
407	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
408	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
409	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
410	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
411	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
412	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
413	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
414	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
415	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
416	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
417	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
418
419	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
420	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
421
422	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
423	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
424	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
425	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
426	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
427	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
428	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
429	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
430	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
431	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
432	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
433	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
434	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
435	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
436	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
437	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
438	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
439	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
440	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
441	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
442	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
443	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
444	SSMFIELD_ENTRY( VMXVVMCS, u64XssBitmap),
445	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsBitmap),
446	SSMFIELD_ENTRY( VMXVVMCS, u64SpptPtr),
447	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
448	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
449
450	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
451	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
452
453	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
454	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
455	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
456	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
457	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
458	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
459	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
460	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
461	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
462	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
463	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
464	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
465
466	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
467	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
468	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
469	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
470
471	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
472	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
473	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
474	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
475	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
476	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
477	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
478	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
479	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
480
481	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
482	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
483	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
484	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
485	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
486	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
487	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
488
489	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
490	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
491	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
492	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
493	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
494	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
495	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
496	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
497	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
498	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
503	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
504	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
509	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
510
511	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
512	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
513	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
514	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
515	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
519	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
520	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
521	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
522	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
523	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
524	SSMFIELD_ENTRY_TERM()
525	};
526
527	/** Saved state field descriptors for CPUMCTX. */
528	static const SSMFIELD g_aCpumX87Fields[] =
529	{
530	SSMFIELD_ENTRY( X86FXSTATE, FCW),
531	SSMFIELD_ENTRY( X86FXSTATE, FSW),
532	SSMFIELD_ENTRY( X86FXSTATE, FTW),
533	SSMFIELD_ENTRY( X86FXSTATE, FOP),
534	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
535	SSMFIELD_ENTRY( X86FXSTATE, CS),
536	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
537	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
538	SSMFIELD_ENTRY( X86FXSTATE, DS),
539	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
540	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
541	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
542	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
543	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
544	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
545	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
546	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
547	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
548	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
549	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
550	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
551	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
552	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
553	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
554	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
555	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
556	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
557	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
558	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
559	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
560	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
561	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
562	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
564	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
565	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
566	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
567	SSMFIELD_ENTRY_TERM()
568	};
569
570	/** Saved state field descriptors for X86XSAVEHDR. */
571	static const SSMFIELD g_aCpumXSaveHdrFields[] =
572	{
573	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
574	SSMFIELD_ENTRY_TERM()
575	};
576
577	/** Saved state field descriptors for X86XSAVEYMMHI. */
578	static const SSMFIELD g_aCpumYmmHiFields[] =
579	{
580	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
581	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
582	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
583	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
584	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
585	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
586	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
587	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
588	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
589	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
590	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
591	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
592	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
594	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
595	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
596	SSMFIELD_ENTRY_TERM()
597	};
598
599	/** Saved state field descriptors for X86XSAVEBNDREGS. */
600	static const SSMFIELD g_aCpumBndRegsFields[] =
601	{
602	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
603	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
604	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
605	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
606	SSMFIELD_ENTRY_TERM()
607	};
608
609	/** Saved state field descriptors for X86XSAVEBNDCFG. */
610	static const SSMFIELD g_aCpumBndCfgFields[] =
611	{
612	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
613	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
614	SSMFIELD_ENTRY_TERM()
615	};
616
617	#if 0 /** @todo */
618	/** Saved state field descriptors for X86XSAVEOPMASK. */
619	static const SSMFIELD g_aCpumOpmaskFields[] =
620	{
621	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
622	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
623	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
624	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
625	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
626	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
627	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
628	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
629	SSMFIELD_ENTRY_TERM()
630	};
631	#endif
632
633	/** Saved state field descriptors for X86XSAVEZMMHI256. */
634	static const SSMFIELD g_aCpumZmmHi256Fields[] =
635	{
636	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
637	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
638	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
639	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
640	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
641	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
642	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
643	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
644	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
645	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
646	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
647	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
648	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
650	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
651	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
652	SSMFIELD_ENTRY_TERM()
653	};
654
655	/** Saved state field descriptors for X86XSAVEZMM16HI. */
656	static const SSMFIELD g_aCpumZmm16HiFields[] =
657	{
658	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
659	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
660	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
661	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
662	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
663	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
664	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
665	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
666	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
667	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
668	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
669	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
670	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
672	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
673	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
674	SSMFIELD_ENTRY_TERM()
675	};
676
677
678
679	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
680	* registeres changed. */
681	static const SSMFIELD g_aCpumX87FieldsMem[] =
682	{
683	SSMFIELD_ENTRY( X86FXSTATE, FCW),
684	SSMFIELD_ENTRY( X86FXSTATE, FSW),
685	SSMFIELD_ENTRY( X86FXSTATE, FTW),
686	SSMFIELD_ENTRY( X86FXSTATE, FOP),
687	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
688	SSMFIELD_ENTRY( X86FXSTATE, CS),
689	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
690	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
691	SSMFIELD_ENTRY( X86FXSTATE, DS),
692	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
693	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
694	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
695	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
696	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
697	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
698	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
699	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
700	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
701	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
702	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
703	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
704	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
705	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
706	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
707	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
708	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
709	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
710	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
711	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
712	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
713	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
714	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
715	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
717	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
718	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
719	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
720	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
721	};
722
723	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
724	* registeres changed. */
725	static const SSMFIELD g_aCpumCtxFieldsMem[] =
726	{
727	SSMFIELD_ENTRY( CPUMCTX, rdi),
728	SSMFIELD_ENTRY( CPUMCTX, rsi),
729	SSMFIELD_ENTRY( CPUMCTX, rbp),
730	SSMFIELD_ENTRY( CPUMCTX, rax),
731	SSMFIELD_ENTRY( CPUMCTX, rbx),
732	SSMFIELD_ENTRY( CPUMCTX, rdx),
733	SSMFIELD_ENTRY( CPUMCTX, rcx),
734	SSMFIELD_ENTRY( CPUMCTX, rsp),
735	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
736	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
737	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
738	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
739	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
740	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
741	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
742	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
743	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
744	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
745	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
746	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
747	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
748	SSMFIELD_ENTRY( CPUMCTX, rflags),
749	SSMFIELD_ENTRY( CPUMCTX, rip),
750	SSMFIELD_ENTRY( CPUMCTX, r8),
751	SSMFIELD_ENTRY( CPUMCTX, r9),
752	SSMFIELD_ENTRY( CPUMCTX, r10),
753	SSMFIELD_ENTRY( CPUMCTX, r11),
754	SSMFIELD_ENTRY( CPUMCTX, r12),
755	SSMFIELD_ENTRY( CPUMCTX, r13),
756	SSMFIELD_ENTRY( CPUMCTX, r14),
757	SSMFIELD_ENTRY( CPUMCTX, r15),
758	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
759	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
760	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
761	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
762	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
763	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
764	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
765	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
766	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
767	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
768	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
769	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
770	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
771	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
772	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
773	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
774	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
775	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
776	SSMFIELD_ENTRY( CPUMCTX, cr0),
777	SSMFIELD_ENTRY( CPUMCTX, cr2),
778	SSMFIELD_ENTRY( CPUMCTX, cr3),
779	SSMFIELD_ENTRY( CPUMCTX, cr4),
780	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
781	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
782	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
783	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
784	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
785	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
786	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
787	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
788	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
789	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
790	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
791	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
792	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
793	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
794	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
795	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
796	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
797	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
798	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
799	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
800	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
801	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
802	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
803	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
804	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
805	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
806	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
807	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
808	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
809	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
810	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
811	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
812	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
813	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
814	SSMFIELD_ENTRY_TERM()
815	};
816
817	/** Saved state field descriptors for CPUMCTX_VER1_6. */
818	static const SSMFIELD g_aCpumX87FieldsV16[] =
819	{
820	SSMFIELD_ENTRY( X86FXSTATE, FCW),
821	SSMFIELD_ENTRY( X86FXSTATE, FSW),
822	SSMFIELD_ENTRY( X86FXSTATE, FTW),
823	SSMFIELD_ENTRY( X86FXSTATE, FOP),
824	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
825	SSMFIELD_ENTRY( X86FXSTATE, CS),
826	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
827	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
828	SSMFIELD_ENTRY( X86FXSTATE, DS),
829	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
830	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
831	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
832	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
833	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
834	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
835	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
836	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
837	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
838	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
839	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
840	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
841	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
842	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
843	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
844	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
845	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
846	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
847	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
848	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
849	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
850	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
851	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
852	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
854	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
855	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
856	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
857	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
858	SSMFIELD_ENTRY_TERM()
859	};
860
861	/** Saved state field descriptors for CPUMCTX_VER1_6. */
862	static const SSMFIELD g_aCpumCtxFieldsV16[] =
863	{
864	SSMFIELD_ENTRY( CPUMCTX, rdi),
865	SSMFIELD_ENTRY( CPUMCTX, rsi),
866	SSMFIELD_ENTRY( CPUMCTX, rbp),
867	SSMFIELD_ENTRY( CPUMCTX, rax),
868	SSMFIELD_ENTRY( CPUMCTX, rbx),
869	SSMFIELD_ENTRY( CPUMCTX, rdx),
870	SSMFIELD_ENTRY( CPUMCTX, rcx),
871	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
872	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
873	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
874	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
875	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
876	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
877	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
878	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
879	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
880	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
881	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
882	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
883	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
884	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
885	SSMFIELD_ENTRY( CPUMCTX, rflags),
886	SSMFIELD_ENTRY( CPUMCTX, rip),
887	SSMFIELD_ENTRY( CPUMCTX, r8),
888	SSMFIELD_ENTRY( CPUMCTX, r9),
889	SSMFIELD_ENTRY( CPUMCTX, r10),
890	SSMFIELD_ENTRY( CPUMCTX, r11),
891	SSMFIELD_ENTRY( CPUMCTX, r12),
892	SSMFIELD_ENTRY( CPUMCTX, r13),
893	SSMFIELD_ENTRY( CPUMCTX, r14),
894	SSMFIELD_ENTRY( CPUMCTX, r15),
895	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
896	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
897	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
898	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
899	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
900	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
901	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
902	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
903	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
904	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
905	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
906	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
907	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
908	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
909	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
910	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
911	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
912	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
913	SSMFIELD_ENTRY( CPUMCTX, cr0),
914	SSMFIELD_ENTRY( CPUMCTX, cr2),
915	SSMFIELD_ENTRY( CPUMCTX, cr3),
916	SSMFIELD_ENTRY( CPUMCTX, cr4),
917	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
918	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
919	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
920	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
921	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
922	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
923	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
924	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
925	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
926	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
927	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
928	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
929	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
930	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
931	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
932	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
933	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
934	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
935	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
936	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
937	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
938	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
939	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
940	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
941	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
942	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
943	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
944	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
945	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
946	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
947	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
948	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
949	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
950	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
951	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
952	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
953	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
954	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
955	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
956	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
957	SSMFIELD_ENTRY_TERM()
958	};
959
960
961	/**
962	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
963	*
964	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
965	* (last instruction pointer, last data pointer, last opcode) except when the ES
966	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
967	* clear these registers there is potential, local FPU leakage from a process
968	* using the FPU to another.
969	*
970	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
971	*
972	* @param pVM The cross context VM structure.
973	*/
974	static void cpumR3CheckLeakyFpu(PVM pVM)
975	{
976	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
977	uint32_t const u32Family = u32CpuVersion >> 8;
978	if ( u32Family >= 6 /* K7 and higher */
979	&& ASMIsAmdCpu())
980	{
981	uint32_t cExt = ASMCpuId_EAX(0x80000000);
982	if (ASMIsValidExtRange(cExt))
983	{
984	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
985	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
986	{
987	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
988	{
989	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
990	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
991	}
992	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
993	}
994	}
995	}
996	}
997
998
999	/**
1000	* Frees memory allocated for the SVM hardware virtualization state.
1001	*
1002	* @param pVM The cross context VM structure.
1003	*/
1004	static void cpumR3FreeSvmHwVirtState(PVM pVM)
1005	{
1006	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1007	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1008	{
1009	PVMCPU pVCpu = pVM->apCpusR3[i];
1010	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
1011	{
1012	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
1013	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
1014	}
1015	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
1016
1017	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
1018	{
1019	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
1020	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
1021	}
1022
1023	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
1024	{
1025	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
1026	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
1027	}
1028	}
1029	}
1030
1031
1032	/**
1033	* Allocates memory for the SVM hardware virtualization state.
1034	*
1035	* @returns VBox status code.
1036	* @param pVM The cross context VM structure.
1037	*/
1038	static int cpumR3AllocSvmHwVirtState(PVM pVM)
1039	{
1040	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1041
1042	int rc = VINF_SUCCESS;
1043	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
1044	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
1045	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1046	{
1047	PVMCPU pVCpu = pVM->apCpusR3[i];
1048	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1049
1050	/*
1051	* Allocate the nested-guest VMCB.
1052	*/
1053	SUPPAGE SupNstGstVmcbPage;
1054	RT_ZERO(SupNstGstVmcbPage);
1055	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
1056	Assert(SVM_VMCB_PAGES == 1);
1057	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1058	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
1059	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
1060	if (RT_FAILURE(rc))
1061	{
1062	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1063	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
1064	break;
1065	}
1066	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
1067
1068	/*
1069	* Allocate the MSRPM (MSR Permission bitmap).
1070	*/
1071	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1072	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
1073	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
1074	if (RT_FAILURE(rc))
1075	{
1076	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1077	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
1078	SVM_MSRPM_PAGES));
1079	break;
1080	}
1081
1082	/*
1083	* Allocate the IOPM (IO Permission bitmap).
1084	*/
1085	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1086	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
1087	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
1088	if (RT_FAILURE(rc))
1089	{
1090	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1091	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
1092	SVM_IOPM_PAGES));
1093	break;
1094	}
1095	}
1096
1097	/* On any failure, cleanup. */
1098	if (RT_FAILURE(rc))
1099	cpumR3FreeSvmHwVirtState(pVM);
1100
1101	return rc;
1102	}
1103
1104
1105	/**
1106	* Resets per-VCPU SVM hardware virtualization state.
1107	*
1108	* @param pVCpu The cross context virtual CPU structure.
1109	*/
1110	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1111	{
1112	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1113	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1114	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1115
1116	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1117	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1118	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1119	}
1120
1121
1122	/**
1123	* Frees memory allocated for the VMX hardware virtualization state.
1124	*
1125	* @param pVM The cross context VM structure.
1126	*/
1127	static void cpumR3FreeVmxHwVirtState(PVM pVM)
1128	{
1129	Assert(pVM->cpum.s.GuestFeatures.fVmx);
1130	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1131	{
1132	PVMCPU pVCpu = pVM->apCpusR3[i];
1133	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1134
1135	if (pCtx->hwvirt.vmx.pVmcsR3)
1136	{
1137	SUPR3ContFree(pCtx->hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
1138	pCtx->hwvirt.vmx.pVmcsR3 = NULL;
1139	}
1140	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1141	{
1142	SUPR3ContFree(pCtx->hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
1143	pCtx->hwvirt.vmx.pShadowVmcsR3 = NULL;
1144	}
1145	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1146	{
1147	SUPR3ContFree(pCtx->hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
1148	pCtx->hwvirt.vmx.pvVirtApicPageR3 = NULL;
1149	}
1150	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1151	{
1152	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1153	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = NULL;
1154	}
1155	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1156	{
1157	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1158	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
1159	}
1160	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1161	{
1162	SUPR3ContFree(pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1163	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = NULL;
1164	}
1165	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1166	{
1167	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1168	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = NULL;
1169	}
1170	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1171	{
1172	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1173	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = NULL;
1174	}
1175	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1176	{
1177	SUPR3ContFree(pCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
1178	pCtx->hwvirt.vmx.pvMsrBitmapR3 = NULL;
1179	}
1180	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1181	{
1182	SUPR3ContFree(pCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1183	pCtx->hwvirt.vmx.pvIoBitmapR3 = NULL;
1184	}
1185	}
1186	}
1187
1188
1189	/**
1190	* Allocates memory for the VMX hardware virtualization state.
1191	*
1192	* @returns VBox status code.
1193	* @param pVM The cross context VM structure.
1194	*/
1195	static int cpumR3AllocVmxHwVirtState(PVM pVM)
1196	{
1197	int rc = VINF_SUCCESS;
1198	uint32_t const cPages = VMX_V_VMCS_PAGES
1199	+ VMX_V_SHADOW_VMCS_PAGES
1200	+ VMX_V_VIRT_APIC_PAGES
1201	+ (2 * VMX_V_VMREAD_VMWRITE_BITMAP_PAGES)
1202	+ (3 * VMX_V_AUTOMSR_AREA_PAGES)
1203	+ VMX_V_MSR_BITMAP_PAGES
1204	+ (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1205	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n", pVM->cCpus * cPages));
1206	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1207	{
1208	PVMCPU pVCpu = pVM->apCpusR3[i];
1209	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1210	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1211
1212	/*
1213	* Allocate the nested-guest current VMCS.
1214	*/
1215	pCtx->hwvirt.vmx.pVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1216	&pCtx->hwvirt.vmx.pVmcsR0,
1217	&pCtx->hwvirt.vmx.HCPhysVmcs);
1218	if (pCtx->hwvirt.vmx.pVmcsR3)
1219	{ /* likely */ }
1220	else
1221	{
1222	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1223	break;
1224	}
1225
1226	/*
1227	* Allocate the nested-guest shadow VMCS.
1228	*/
1229	pCtx->hwvirt.vmx.pShadowVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1230	&pCtx->hwvirt.vmx.pShadowVmcsR0,
1231	&pCtx->hwvirt.vmx.HCPhysShadowVmcs);
1232	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1233	{ /* likely */ }
1234	else
1235	{
1236	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1237	break;
1238	}
1239
1240	/*
1241	* Allocate the virtual-APIC page.
1242	*/
1243	pCtx->hwvirt.vmx.pvVirtApicPageR3 = SUPR3ContAlloc(VMX_V_VIRT_APIC_PAGES,
1244	&pCtx->hwvirt.vmx.pvVirtApicPageR0,
1245	&pCtx->hwvirt.vmx.HCPhysVirtApicPage);
1246	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1247	{ /* likely */ }
1248	else
1249	{
1250	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's virtual-APIC page\n", pVCpu->idCpu,
1251	VMX_V_VIRT_APIC_PAGES));
1252	break;
1253	}
1254
1255	/*
1256	* Allocate the VMREAD-bitmap.
1257	*/
1258	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1259	&pCtx->hwvirt.vmx.pvVmreadBitmapR0,
1260	&pCtx->hwvirt.vmx.HCPhysVmreadBitmap);
1261	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1262	{ /* likely */ }
1263	else
1264	{
1265	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1266	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1267	break;
1268	}
1269
1270	/*
1271	* Allocatge the VMWRITE-bitmap.
1272	*/
1273	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1274	&pCtx->hwvirt.vmx.pvVmwriteBitmapR0,
1275	&pCtx->hwvirt.vmx.HCPhysVmwriteBitmap);
1276	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1277	{ /* likely */ }
1278	else
1279	{
1280	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1281	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1282	break;
1283	}
1284
1285	/*
1286	* Allocate the VM-entry MSR-load area.
1287	*/
1288	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1289	&pCtx->hwvirt.vmx.pEntryMsrLoadAreaR0,
1290	&pCtx->hwvirt.vmx.HCPhysEntryMsrLoadArea);
1291	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1292	{ /* likely */ }
1293	else
1294	{
1295	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-entry MSR-load area\n", pVCpu->idCpu,
1296	VMX_V_AUTOMSR_AREA_PAGES));
1297	break;
1298	}
1299
1300	/*
1301	* Allocate the VM-exit MSR-store area.
1302	*/
1303	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1304	&pCtx->hwvirt.vmx.pExitMsrStoreAreaR0,
1305	&pCtx->hwvirt.vmx.HCPhysExitMsrStoreArea);
1306	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1307	{ /* likely */ }
1308	else
1309	{
1310	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-store area\n", pVCpu->idCpu,
1311	VMX_V_AUTOMSR_AREA_PAGES));
1312	break;
1313	}
1314
1315	/*
1316	* Allocate the VM-exit MSR-load area.
1317	*/
1318	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1319	&pCtx->hwvirt.vmx.pExitMsrLoadAreaR0,
1320	&pCtx->hwvirt.vmx.HCPhysExitMsrLoadArea);
1321	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1322	{ /* likely */ }
1323	else
1324	{
1325	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-load area\n", pVCpu->idCpu,
1326	VMX_V_AUTOMSR_AREA_PAGES));
1327	break;
1328	}
1329
1330	/*
1331	* Allocate the MSR bitmap.
1332	*/
1333	pCtx->hwvirt.vmx.pvMsrBitmapR3 = SUPR3ContAlloc(VMX_V_MSR_BITMAP_PAGES,
1334	&pCtx->hwvirt.vmx.pvMsrBitmapR0,
1335	&pCtx->hwvirt.vmx.HCPhysMsrBitmap);
1336	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1337	{ /* likely */ }
1338	else
1339	{
1340	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1341	VMX_V_MSR_BITMAP_PAGES));
1342	break;
1343	}
1344
1345	/*
1346	* Allocate the I/O bitmaps (A and B).
1347	*/
1348	pCtx->hwvirt.vmx.pvIoBitmapR3 = SUPR3ContAlloc(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES,
1349	&pCtx->hwvirt.vmx.pvIoBitmapR0,
1350	&pCtx->hwvirt.vmx.HCPhysIoBitmap);
1351	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1352	{ /* likely */ }
1353	else
1354	{
1355	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1356	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1357	break;
1358	}
1359
1360	/*
1361	* Zero out all allocated pages (should compress well for saved-state).
1362	*/
1363	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1364	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1365	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVirtApicPage), 0, VMX_V_VIRT_APIC_SIZE);
1366	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmreadBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1367	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1368	memset(pCtx->hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1369	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1370	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1371	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvMsrBitmap), 0, VMX_V_MSR_BITMAP_SIZE);
1372	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap), 0, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1373	}
1374
1375	/* On any failure, cleanup. */
1376	if (RT_FAILURE(rc))
1377	cpumR3FreeVmxHwVirtState(pVM);
1378
1379	return rc;
1380	}
1381
1382
1383	/**
1384	* Resets per-VCPU VMX hardware virtualization state.
1385	*
1386	* @param pVCpu The cross context virtual CPU structure.
1387	*/
1388	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1389	{
1390	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1391	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1392	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1393	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1394
1395	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1396	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1397	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1398	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1399	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1400	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1401	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1402	/* Don't reset diagnostics here. */
1403	}
1404
1405
1406	/**
1407	* Displays the host and guest VMX features.
1408	*
1409	* @param pVM The cross context VM structure.
1410	* @param pHlp The info helper functions.
1411	* @param pszArgs "terse", "default" or "verbose".
1412	*/
1413	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1414	{
1415	RT_NOREF(pszArgs);
1416	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1417	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1418	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1419	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1420	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1421	{
1422	#define VMXFEATDUMP(a_szDesc, a_Var) \
1423	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1424
1425	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1426	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1427	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1428	/* Basic. */
1429	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1430	/* Pin-based controls. */
1431	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1432	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1433	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1434	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1435	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1436	/* Processor-based controls. */
1437	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1438	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1439	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1440	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1441	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1442	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1443	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1444	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1445	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1446	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1447	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1448	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1449	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1450	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1451	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1452	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1453	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1454	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1455	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1456	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1457	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1458	/* Secondary processor-based controls. */
1459	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1460	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1461	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1462	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1463	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1464	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1465	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1466	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1467	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1468	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1469	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1470	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1471	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1472	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1473	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1474	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1475	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1476	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1477	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1478	/* VM-entry controls. */
1479	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1480	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1481	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1482	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1483	/* VM-exit controls. */
1484	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1485	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1486	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1487	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1488	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1489	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1490	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1491	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1492	/* Miscellaneous data. */
1493	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1494	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1495	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1496	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1497	#undef VMXFEATDUMP
1498	}
1499	else
1500	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1501	}
1502
1503
1504	/**
1505	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1506	* or NEM) is allowed.
1507	*
1508	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1509	* otherwise.
1510	* @param pVM The cross context VM structure.
1511	*/
1512	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1513	{
1514	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1515	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1516	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1517	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1518	return true;
1519	#else
1520	NOREF(pVM);
1521	#endif
1522	return false;
1523	}
1524
1525
1526	/**
1527	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1528	*
1529	* @param pVM The cross context VM structure.
1530	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1531	* and no hardware-assisted nested-guest execution is
1532	* possible for this VM.
1533	* @param pGuestFeatures The guest features to use (only VMX features are
1534	* accessed).
1535	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1536	*
1537	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1538	*/
1539	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1540	{
1541	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1542
1543	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1544	Assert(pGuestFeatures->fVmx);
1545
1546	/*
1547	* We don't support the following MSRs yet:
1548	* - True Pin-based VM-execution controls.
1549	* - True Processor-based VM-execution controls.
1550	* - True VM-entry VM-execution controls.
1551	* - True VM-exit VM-execution controls.
1552	*/
1553
1554	/* Feature control. */
1555	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1556
1557	/* Basic information. */
1558	{
1559	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1560	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1561	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1562	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1563	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1564	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1565	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1566	pGuestVmxMsrs->u64Basic = u64Basic;
1567	}
1568
1569	/* Pin-based VM-execution controls. */
1570	{
1571	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1572	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1573	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1574	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1575	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1576	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1577	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1578	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1579	fAllowed0, fAllowed1, fFeatures));
1580	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1581	}
1582
1583	/* Processor-based VM-execution controls. */
1584	{
1585	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1586	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1587	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1588	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1589	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1590	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1591	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1592	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1593	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1594	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1595	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1596	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1597	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1598	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1599	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1600	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1601	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1602	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1603	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1604	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1605	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1606	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1607	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1608	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1609	fAllowed1, fFeatures));
1610	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1611	}
1612
1613	/* Secondary processor-based VM-execution controls. */
1614	if (pGuestFeatures->fVmxSecondaryExecCtls)
1615	{
1616	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1617	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1618	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1619	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1620	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1621	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1622	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1623	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1624	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1625	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1626	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1627	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1628	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1629	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1630	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1631	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1632	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1633	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1634	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1635	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1636	uint32_t const fAllowed0 = 0;
1637	uint32_t const fAllowed1 = fFeatures;
1638	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1639	}
1640
1641	/* VM-exit controls. */
1642	{
1643	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1644	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1645	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1646	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1647	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1648	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1649	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1650	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1651	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1652	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1653	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1654	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1655	fAllowed1, fFeatures));
1656	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1657	}
1658
1659	/* VM-entry controls. */
1660	{
1661	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1662	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1663	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1664	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1665	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1666	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1667	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1668	fAllowed1, fFeatures));
1669	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1670	}
1671
1672	/* Miscellaneous data. */
1673	{
1674	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1675
1676	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1677	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1678	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1679	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1680	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1681	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1682	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1683	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1684	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1685	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1686	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1687	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1688	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1689	}
1690
1691	/* CR0 Fixed-0. */
1692	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1693
1694	/* CR0 Fixed-1. */
1695	{
1696	/*
1697	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1698	* This is different from CR4 fixed-1 bits which are reported as per the
1699	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1700	*/
1701	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1702	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1703	}
1704
1705	/* CR4 Fixed-0. */
1706	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1707
1708	/* CR4 Fixed-1. */
1709	{
1710	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1711	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1712	}
1713
1714	/* VMCS Enumeration. */
1715	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1716
1717	/* VPID and EPT Capabilities. */
1718	{
1719	/*
1720	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1721	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1722	* when INVVPID instruction is supported just to be more compatible with guest
1723	* hypervisors that may make assumptions by only looking at this MSR even though they
1724	* are technically supposed to refer to bit 37 of MSR_IA32_VMX_PROC_CTLS2 first.
1725	*
1726	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1727	* See Intel spec. 30.3 "VMX Instructions".
1728	*/
1729	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1730	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1731	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & 1)
1732	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & 1)
1733	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & 1);
1734	}
1735
1736	/* VM Functions. */
1737	if (pGuestFeatures->fVmxVmFunc)
1738	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1739	}
1740
1741
1742	/**
1743	* Checks whether the given guest CPU VMX features are compatible with the provided
1744	* base features.
1745	*
1746	* @returns @c true if compatible, @c false otherwise.
1747	* @param pVM The cross context VM structure.
1748	* @param pBase The base VMX CPU features.
1749	* @param pGst The guest VMX CPU features.
1750	*
1751	* @remarks Only VMX feature bits are examined.
1752	*/
1753	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1754	{
1755	if (cpumR3IsHwAssistNstGstExecAllowed(pVM))
1756	{
1757	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1758	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1759	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1760	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1761	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1762	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1763	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1764	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1765	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1766	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1767	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1768	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1769	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1770	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1771	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1772	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1773	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1774	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1775	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1776	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1777	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1778	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1779	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1780	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1781	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1782	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1783	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1784	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1785	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1786	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1787	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1788	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1789
1790	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1791	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1792	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1793	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1794	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1795	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1796	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1797	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1798	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1799	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1800	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1801	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1802	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1803	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1804	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1805	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1806	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1807	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1808	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1809	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1810	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1811	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1812	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1813	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1814	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1815	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1816	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1817	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1818	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1819	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1820	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1821	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1822
1823	if ((fBase \| fGst) != fBase)
1824	{
1825	uint64_t const fDiff = fBase ^ fGst;
1826	LogRel(("CPUM: VMX features now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1827	fBase, fGst, fDiff));
1828	return false;
1829	}
1830	return true;
1831	}
1832	return true;
1833	}
1834
1835
1836	/**
1837	* Initializes VMX guest features and MSRs.
1838	*
1839	* @param pVM The cross context VM structure.
1840	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1841	* and no hardware-assisted nested-guest execution is
1842	* possible for this VM.
1843	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1844	*/
1845	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1846	{
1847	Assert(pVM);
1848	Assert(pGuestVmxMsrs);
1849
1850	/*
1851	* Initialize the set of VMX features we emulate.
1852	*
1853	* Note! Some bits might be reported as 1 always if they fall under the
1854	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1855	*/
1856	CPUMFEATURES EmuFeat;
1857	RT_ZERO(EmuFeat);
1858	EmuFeat.fVmx = 1;
1859	EmuFeat.fVmxInsOutInfo = 1;
1860	EmuFeat.fVmxExtIntExit = 1;
1861	EmuFeat.fVmxNmiExit = 1;
1862	EmuFeat.fVmxVirtNmi = 0;
1863	EmuFeat.fVmxPreemptTimer = 0; /** @todo NSTVMX: enable this. */
1864	EmuFeat.fVmxPostedInt = 0;
1865	EmuFeat.fVmxIntWindowExit = 1;
1866	EmuFeat.fVmxTscOffsetting = 1;
1867	EmuFeat.fVmxHltExit = 1;
1868	EmuFeat.fVmxInvlpgExit = 1;
1869	EmuFeat.fVmxMwaitExit = 1;
1870	EmuFeat.fVmxRdpmcExit = 1;
1871	EmuFeat.fVmxRdtscExit = 1;
1872	EmuFeat.fVmxCr3LoadExit = 1;
1873	EmuFeat.fVmxCr3StoreExit = 1;
1874	EmuFeat.fVmxCr8LoadExit = 1;
1875	EmuFeat.fVmxCr8StoreExit = 1;
1876	EmuFeat.fVmxUseTprShadow = 1;
1877	EmuFeat.fVmxNmiWindowExit = 0;
1878	EmuFeat.fVmxMovDRxExit = 1;
1879	EmuFeat.fVmxUncondIoExit = 1;
1880	EmuFeat.fVmxUseIoBitmaps = 1;
1881	EmuFeat.fVmxMonitorTrapFlag = 0;
1882	EmuFeat.fVmxUseMsrBitmaps = 1;
1883	EmuFeat.fVmxMonitorExit = 1;
1884	EmuFeat.fVmxPauseExit = 1;
1885	EmuFeat.fVmxSecondaryExecCtls = 1;
1886	EmuFeat.fVmxVirtApicAccess = 1;
1887	EmuFeat.fVmxEpt = 0; /* Cannot be disabled if unrestricted guest is enabled. */
1888	EmuFeat.fVmxDescTableExit = 1;
1889	EmuFeat.fVmxRdtscp = 1;
1890	EmuFeat.fVmxVirtX2ApicMode = 0;
1891	EmuFeat.fVmxVpid = 0; /** @todo NSTVMX: enable this. */
1892	EmuFeat.fVmxWbinvdExit = 1;
1893	EmuFeat.fVmxUnrestrictedGuest = 0;
1894	EmuFeat.fVmxApicRegVirt = 0;
1895	EmuFeat.fVmxVirtIntDelivery = 0;
1896	EmuFeat.fVmxPauseLoopExit = 0;
1897	EmuFeat.fVmxRdrandExit = 0;
1898	EmuFeat.fVmxInvpcid = 1;
1899	EmuFeat.fVmxVmFunc = 0;
1900	EmuFeat.fVmxVmcsShadowing = 0;
1901	EmuFeat.fVmxRdseedExit = 0;
1902	EmuFeat.fVmxPml = 0;
1903	EmuFeat.fVmxEptXcptVe = 0;
1904	EmuFeat.fVmxXsavesXrstors = 0;
1905	EmuFeat.fVmxUseTscScaling = 0;
1906	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1907	EmuFeat.fVmxIa32eModeGuest = 1;
1908	EmuFeat.fVmxEntryLoadEferMsr = 1;
1909	EmuFeat.fVmxEntryLoadPatMsr = 0;
1910	EmuFeat.fVmxExitSaveDebugCtls = 1;
1911	EmuFeat.fVmxHostAddrSpaceSize = 1;
1912	EmuFeat.fVmxExitAckExtInt = 0;
1913	EmuFeat.fVmxExitSavePatMsr = 0;
1914	EmuFeat.fVmxExitLoadPatMsr = 0;
1915	EmuFeat.fVmxExitSaveEferMsr = 1;
1916	EmuFeat.fVmxExitLoadEferMsr = 1;
1917	EmuFeat.fVmxSavePreemptTimer = 0;
1918	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1919	EmuFeat.fVmxIntelPt = 0;
1920	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1921	EmuFeat.fVmxEntryInjectSoftInt = 1;
1922
1923	/*
1924	* Merge guest features.
1925	*
1926	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1927	* by the hardware, hence we merge our emulated features with the host features below.
1928	*/
1929	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1930	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1931	Assert(pBaseFeat->fVmx);
1932	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1933	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1934	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1935	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1936	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1937	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1938	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1939	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1940	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1941	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1942	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1943	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1944	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1945	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1946	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1947	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1948	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1949	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1950	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1951	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1952	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1953	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1954	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1955	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1956	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1957	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1958	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1959	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1960	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1961	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1962	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1963	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1964	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1965	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1966	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1967	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1968	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1969	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1970	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1971	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1972	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1973	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1974	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1975	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1976	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1977	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1978	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1979	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1980	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1981	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1982	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1983	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1984	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1985	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1986	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1987	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1988	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1989	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1990	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1991	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1992	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1993	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1994	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1995
1996	/* Paranoia. */
1997	if (!pGuestFeat->fVmxSecondaryExecCtls)
1998	{
1999	Assert(!pGuestFeat->fVmxVirtApicAccess);
2000	Assert(!pGuestFeat->fVmxEpt);
2001	Assert(!pGuestFeat->fVmxDescTableExit);
2002	Assert(!pGuestFeat->fVmxRdtscp);
2003	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
2004	Assert(!pGuestFeat->fVmxVpid);
2005	Assert(!pGuestFeat->fVmxWbinvdExit);
2006	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
2007	Assert(!pGuestFeat->fVmxApicRegVirt);
2008	Assert(!pGuestFeat->fVmxVirtIntDelivery);
2009	Assert(!pGuestFeat->fVmxPauseLoopExit);
2010	Assert(!pGuestFeat->fVmxRdrandExit);
2011	Assert(!pGuestFeat->fVmxInvpcid);
2012	Assert(!pGuestFeat->fVmxVmFunc);
2013	Assert(!pGuestFeat->fVmxVmcsShadowing);
2014	Assert(!pGuestFeat->fVmxRdseedExit);
2015	Assert(!pGuestFeat->fVmxPml);
2016	Assert(!pGuestFeat->fVmxEptXcptVe);
2017	Assert(!pGuestFeat->fVmxXsavesXrstors);
2018	Assert(!pGuestFeat->fVmxUseTscScaling);
2019	}
2020	if (pGuestFeat->fVmxUnrestrictedGuest)
2021	{
2022	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2023	Assert(pGuestFeat->fVmxExitSaveEferLma);
2024	}
2025
2026	/*
2027	* Finally initialize the VMX guest MSRs.
2028	*/
2029	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2030	}
2031
2032
2033	/**
2034	* Gets the host hardware-virtualization MSRs.
2035	*
2036	* @returns VBox status code.
2037	* @param pMsrs Where to store the MSRs.
2038	*/
2039	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2040	{
2041	Assert(pMsrs);
2042
2043	uint32_t fCaps = 0;
2044	int rc = SUPR3QueryVTCaps(&fCaps);
2045	if (RT_SUCCESS(rc))
2046	{
2047	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2048	{
2049	SUPHWVIRTMSRS HwvirtMsrs;
2050	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2051	if (RT_SUCCESS(rc))
2052	{
2053	if (fCaps & SUPVTCAPS_VT_X)
2054	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2055	else
2056	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2057	return VINF_SUCCESS;
2058	}
2059
2060	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2061	return rc;
2062	}
2063	else
2064	{
2065	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2066	return VERR_INTERNAL_ERROR_5;
2067	}
2068	}
2069	else
2070	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2071
2072	return VINF_SUCCESS;
2073	}
2074
2075
2076	/**
2077	* Initializes the CPUM.
2078	*
2079	* @returns VBox status code.
2080	* @param pVM The cross context VM structure.
2081	*/
2082	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2083	{
2084	LogFlow(("CPUMR3Init\n"));
2085
2086	/*
2087	* Assert alignment, sizes and tables.
2088	*/
2089	AssertCompileMemberAlignment(VM, cpum.s, 32);
2090	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2091	AssertCompileSizeAlignment(CPUMCTX, 64);
2092	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2093	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2094	AssertCompileMemberAlignment(VM, cpum, 64);
2095	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2096	#ifdef VBOX_STRICT
2097	int rc2 = cpumR3MsrStrictInitChecks();
2098	AssertRCReturn(rc2, rc2);
2099	#endif
2100
2101	/*
2102	* Gather info about the host CPU.
2103	*/
2104	if (!ASMHasCpuId())
2105	{
2106	LogRel(("The CPU doesn't support CPUID!\n"));
2107	return VERR_UNSUPPORTED_CPU;
2108	}
2109
2110	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2111
2112	CPUMMSRS HostMsrs;
2113	RT_ZERO(HostMsrs);
2114	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2115	AssertLogRelRCReturn(rc, rc);
2116
2117	PCPUMCPUIDLEAF paLeaves;
2118	uint32_t cLeaves;
2119	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
2120	AssertLogRelRCReturn(rc, rc);
2121
2122	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
2123	RTMemFree(paLeaves);
2124	AssertLogRelRCReturn(rc, rc);
2125	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2126
2127	/*
2128	* Check that the CPU supports the minimum features we require.
2129	*/
2130	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2131	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2132	if (!pVM->cpum.s.HostFeatures.fMmx)
2133	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2134	if (!pVM->cpum.s.HostFeatures.fTsc)
2135	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2136
2137	/*
2138	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2139	*/
2140	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2141	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2142
2143	/*
2144	* Figure out which XSAVE/XRSTOR features are available on the host.
2145	*/
2146	uint64_t fXcr0Host = 0;
2147	uint64_t fXStateHostMask = 0;
2148	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2149	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2150	{
2151	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2152	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2153	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2154	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2155	}
2156	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2157	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2158	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2159
2160	/*
2161	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
2162	*/
2163	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2164	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2165	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
2166
2167	uint8_t *pbXStates;
2168	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * 2 * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
2169	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
2170	AssertLogRelRCReturn(rc, rc);
2171
2172	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2173	{
2174	PVMCPU pVCpu = pVM->apCpusR3[i];
2175
2176	pVCpu->cpum.s.Guest.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2177	pVCpu->cpum.s.Guest.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2178	pbXStates += cbMaxXState;
2179
2180	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2181	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2182	pbXStates += cbMaxXState;
2183
2184	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2185	}
2186
2187	/*
2188	* Register saved state data item.
2189	*/
2190	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2191	NULL, cpumR3LiveExec, NULL,
2192	NULL, cpumR3SaveExec, NULL,
2193	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2194	if (RT_FAILURE(rc))
2195	return rc;
2196
2197	/*
2198	* Register info handlers and registers with the debugger facility.
2199	*/
2200	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2201	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2202	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2203	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2204	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2205	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2206	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2207	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2208	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2209	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2210	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2211	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2212	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2213	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2214	&cpumR3InfoVmxFeatures);
2215
2216	rc = cpumR3DbgInit(pVM);
2217	if (RT_FAILURE(rc))
2218	return rc;
2219
2220	/*
2221	* Check if we need to workaround partial/leaky FPU handling.
2222	*/
2223	cpumR3CheckLeakyFpu(pVM);
2224
2225	/*
2226	* Initialize the Guest CPUID and MSR states.
2227	*/
2228	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2229	if (RT_FAILURE(rc))
2230	return rc;
2231
2232	/*
2233	* Allocate memory required by the guest hardware-virtualization structures.
2234	* This must be done after initializing CPUID/MSR features as we access the
2235	* the VMX/SVM guest features below.
2236	*/
2237	if (pVM->cpum.s.GuestFeatures.fVmx)
2238	rc = cpumR3AllocVmxHwVirtState(pVM);
2239	else if (pVM->cpum.s.GuestFeatures.fSvm)
2240	rc = cpumR3AllocSvmHwVirtState(pVM);
2241	else
2242	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2243	if (RT_FAILURE(rc))
2244	return rc;
2245
2246	CPUMR3Reset(pVM);
2247	return VINF_SUCCESS;
2248	}
2249
2250
2251	/**
2252	* Applies relocations to data and code managed by this
2253	* component. This function will be called at init and
2254	* whenever the VMM need to relocate it self inside the GC.
2255	*
2256	* The CPUM will update the addresses used by the switcher.
2257	*
2258	* @param pVM The cross context VM structure.
2259	*/
2260	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2261	{
2262	RT_NOREF(pVM);
2263	}
2264
2265
2266	/**
2267	* Terminates the CPUM.
2268	*
2269	* Termination means cleaning up and freeing all resources,
2270	* the VM it self is at this point powered off or suspended.
2271	*
2272	* @returns VBox status code.
2273	* @param pVM The cross context VM structure.
2274	*/
2275	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2276	{
2277	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2278	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2279	{
2280	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2281	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2282	pVCpu->cpum.s.uMagic = 0;
2283	pvCpu->cpum.s.Guest.dr[5] = 0;
2284	}
2285	#endif
2286
2287	if (pVM->cpum.s.GuestFeatures.fVmx)
2288	cpumR3FreeVmxHwVirtState(pVM);
2289	else if (pVM->cpum.s.GuestFeatures.fSvm)
2290	cpumR3FreeSvmHwVirtState(pVM);
2291	return VINF_SUCCESS;
2292	}
2293
2294
2295	/**
2296	* Resets a virtual CPU.
2297	*
2298	* Used by CPUMR3Reset and CPU hot plugging.
2299	*
2300	* @param pVM The cross context VM structure.
2301	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2302	* being reset. This may differ from the current EMT.
2303	*/
2304	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2305	{
2306	/** @todo anything different for VCPU > 0? */
2307	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2308
2309	/*
2310	* Initialize everything to ZERO first.
2311	*/
2312	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2313
2314	AssertCompile(RTASSERT_OFFSET_OF(CPUMCTX, pXStateR0) < RTASSERT_OFFSET_OF(CPUMCTX, pXStateR3));
2315	memset(pCtx, 0, RT_UOFFSETOF(CPUMCTX, pXStateR0));
2316
2317	pVCpu->cpum.s.fUseFlags = fUseFlags;
2318
2319	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2320	pCtx->eip = 0x0000fff0;
2321	pCtx->edx = 0x00000600; /* P6 processor */
2322	pCtx->eflags.Bits.u1Reserved0 = 1;
2323
2324	pCtx->cs.Sel = 0xf000;
2325	pCtx->cs.ValidSel = 0xf000;
2326	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2327	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2328	pCtx->cs.u32Limit = 0x0000ffff;
2329	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2330	pCtx->cs.Attr.n.u1Present = 1;
2331	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2332
2333	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2334	pCtx->ds.u32Limit = 0x0000ffff;
2335	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2336	pCtx->ds.Attr.n.u1Present = 1;
2337	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2338
2339	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2340	pCtx->es.u32Limit = 0x0000ffff;
2341	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2342	pCtx->es.Attr.n.u1Present = 1;
2343	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2344
2345	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2346	pCtx->fs.u32Limit = 0x0000ffff;
2347	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2348	pCtx->fs.Attr.n.u1Present = 1;
2349	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2350
2351	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2352	pCtx->gs.u32Limit = 0x0000ffff;
2353	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2354	pCtx->gs.Attr.n.u1Present = 1;
2355	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2356
2357	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2358	pCtx->ss.u32Limit = 0x0000ffff;
2359	pCtx->ss.Attr.n.u1Present = 1;
2360	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2361	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2362
2363	pCtx->idtr.cbIdt = 0xffff;
2364	pCtx->gdtr.cbGdt = 0xffff;
2365
2366	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2367	pCtx->ldtr.u32Limit = 0xffff;
2368	pCtx->ldtr.Attr.n.u1Present = 1;
2369	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2370
2371	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2372	pCtx->tr.u32Limit = 0xffff;
2373	pCtx->tr.Attr.n.u1Present = 1;
2374	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2375
2376	pCtx->dr[6] = X86_DR6_INIT_VAL;
2377	pCtx->dr[7] = X86_DR7_INIT_VAL;
2378
2379	PX86FXSTATE pFpuCtx = &pCtx->pXStateR3->x87; AssertReleaseMsg(RT_VALID_PTR(pFpuCtx), ("%p\n", pFpuCtx));
2380	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2381	pFpuCtx->FCW = 0x37f;
2382
2383	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2384	IA-32 Processor States Following Power-up, Reset, or INIT */
2385	pFpuCtx->MXCSR = 0x1F80;
2386	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2387
2388	pCtx->aXcr[0] = XSAVE_C_X87;
2389	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2390	{
2391	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2392	as we don't know what happened before. (Bother optimize later?) */
2393	pCtx->pXStateR3->Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2394	}
2395
2396	/*
2397	* MSRs.
2398	*/
2399	/* Init PAT MSR */
2400	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2401
2402	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2403	* The Intel docs don't mention it. */
2404	Assert(!pCtx->msrEFER);
2405
2406	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2407	is supposed to be here, just trying provide useful/sensible values. */
2408	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2409	if (pRange)
2410	{
2411	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2412	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2413	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2414	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2415	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2416	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2417	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2418	}
2419
2420	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2421
2422	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2423	* called from each EMT while we're getting called by CPUMR3Reset()
2424	* iteratively on the same thread. Fix later. */
2425	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2426	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2427	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2428	#endif
2429
2430
2431	/* C-state control. Guesses. */
2432	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2433	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2434	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2435	* functionality. The default value must be different due to incompatible write mask.
2436	*/
2437	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2438	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2439	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2440	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2441
2442	/*
2443	* Hardware virtualization state.
2444	*/
2445	CPUMSetGuestGif(pCtx, true);
2446	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2447	if (pVM->cpum.s.GuestFeatures.fVmx)
2448	cpumR3ResetVmxHwVirtState(pVCpu);
2449	else if (pVM->cpum.s.GuestFeatures.fSvm)
2450	cpumR3ResetSvmHwVirtState(pVCpu);
2451	}
2452
2453
2454	/**
2455	* Resets the CPU.
2456	*
2457	* @returns VINF_SUCCESS.
2458	* @param pVM The cross context VM structure.
2459	*/
2460	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2461	{
2462	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2463	{
2464	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2465	CPUMR3ResetCpu(pVM, pVCpu);
2466
2467	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2468
2469	/* Magic marker for searching in crash dumps. */
2470	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2471	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2472	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2473	#endif
2474	}
2475	}
2476
2477
2478
2479
2480	/**
2481	* Pass 0 live exec callback.
2482	*
2483	* @returns VINF_SSM_DONT_CALL_AGAIN.
2484	* @param pVM The cross context VM structure.
2485	* @param pSSM The saved state handle.
2486	* @param uPass The pass (0).
2487	*/
2488	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2489	{
2490	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2491	cpumR3SaveCpuId(pVM, pSSM);
2492	return VINF_SSM_DONT_CALL_AGAIN;
2493	}
2494
2495
2496	/**
2497	* Execute state save operation.
2498	*
2499	* @returns VBox status code.
2500	* @param pVM The cross context VM structure.
2501	* @param pSSM SSM operation handle.
2502	*/
2503	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2504	{
2505	/*
2506	* Save.
2507	*/
2508	SSMR3PutU32(pSSM, pVM->cCpus);
2509	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2510	CPUMCTX DummyHyperCtx;
2511	RT_ZERO(DummyHyperCtx);
2512	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2513	{
2514	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2515
2516	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2517
2518	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2519	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2520	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2521	if (pGstCtx->fXStateMask != 0)
2522	SSMR3PutStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2523	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2524	{
2525	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2526	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2527	}
2528	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2529	{
2530	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2531	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2532	}
2533	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2534	{
2535	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2536	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2537	}
2538	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2539	{
2540	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2541	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2542	}
2543	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2544	{
2545	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2546	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2547	}
2548	if (pVM->cpum.s.GuestFeatures.fSvm)
2549	{
2550	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2551	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2552	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2553	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2554	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2555	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2556	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2557	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2558	g_aSvmHwvirtHostState, NULL /* pvUser */);
2559	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2560	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2561	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2562	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2563	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2564	}
2565	if (pVM->cpum.s.GuestFeatures.fVmx)
2566	{
2567	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2568	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2569	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2570	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2571	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2572	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2573	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2574	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2575	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2576	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2577	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2578	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2579	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2580	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2581	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2582	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2583	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2584	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2585	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2586	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2587	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2588	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2589	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2590	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2591	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2592	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2593	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2594	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2595	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2596	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2597	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2598	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2599	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2600	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2601	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2602	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2603	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2604	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2605	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2606	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2607	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2608	}
2609	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2610	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2611	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2612	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2613	}
2614
2615	cpumR3SaveCpuId(pVM, pSSM);
2616	return VINF_SUCCESS;
2617	}
2618
2619
2620	/**
2621	* @callback_method_impl{FNSSMINTLOADPREP}
2622	*/
2623	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2624	{
2625	NOREF(pSSM);
2626	pVM->cpum.s.fPendingRestore = true;
2627	return VINF_SUCCESS;
2628	}
2629
2630
2631	/**
2632	* @callback_method_impl{FNSSMINTLOADEXEC}
2633	*/
2634	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2635	{
2636	int rc; /* Only for AssertRCReturn use. */
2637
2638	/*
2639	* Validate version.
2640	*/
2641	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
2642	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2643	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2644	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2645	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2646	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2647	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2648	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2649	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2650	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2651	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2652	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2653	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2654	{
2655	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2656	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2657	}
2658
2659	if (uPass == SSM_PASS_FINAL)
2660	{
2661	/*
2662	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2663	* really old SSM file versions.)
2664	*/
2665	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2666	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2667	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2668	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2669
2670	/*
2671	* Figure x86 and ctx field definitions to use for older states.
2672	*/
2673	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2674	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2675	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2676	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2677	{
2678	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2679	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2680	}
2681	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2682	{
2683	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2684	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2685	}
2686
2687	/*
2688	* The hyper state used to preceed the CPU count. Starting with
2689	* XSAVE it was moved down till after we've got the count.
2690	*/
2691	CPUMCTX HyperCtxIgnored;
2692	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2693	{
2694	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2695	{
2696	X86FXSTATE Ign;
2697	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2698	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2699	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2700	}
2701	}
2702
2703	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2704	{
2705	uint32_t cCpus;
2706	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2707	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2708	VERR_SSM_UNEXPECTED_DATA);
2709	}
2710	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2711	\|\| pVM->cCpus == 1,
2712	("cCpus=%u\n", pVM->cCpus),
2713	VERR_SSM_UNEXPECTED_DATA);
2714
2715	uint32_t cbMsrs = 0;
2716	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2717	{
2718	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2719	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2720	VERR_SSM_UNEXPECTED_DATA);
2721	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2722	VERR_SSM_UNEXPECTED_DATA);
2723	}
2724
2725	/*
2726	* Do the per-CPU restoring.
2727	*/
2728	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2729	{
2730	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2731	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2732
2733	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2734	{
2735	/*
2736	* The XSAVE saved state layout moved the hyper state down here.
2737	*/
2738	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2739	AssertRCReturn(rc, rc);
2740
2741	/*
2742	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2743	*/
2744	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2745	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87), 0, g_aCpumX87Fields, NULL);
2746	AssertRCReturn(rc, rc);
2747
2748	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2749	if (pGstCtx->fXStateMask != 0)
2750	{
2751	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2752	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2753	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2754	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2755	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2756	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2757	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2758	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2759	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2760	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2761	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2762	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2763	}
2764
2765	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2766	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2767	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2768	{
2769	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2770	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2771	VERR_CPUM_INVALID_XCR0);
2772	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2773	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2774	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2775	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2776	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2777	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2778	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2779	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2780	}
2781
2782	/* Check that the XCR1 is zero, as we don't implement it yet. */
2783	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2784
2785	/*
2786	* Restore the individual extended state components we support.
2787	*/
2788	if (pGstCtx->fXStateMask != 0)
2789	{
2790	rc = SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->Hdr, sizeof(pGstCtx->pXStateR3->Hdr),
2791	0, g_aCpumXSaveHdrFields, NULL);
2792	AssertRCReturn(rc, rc);
2793	AssertLogRelMsgReturn(!(pGstCtx->pXStateR3->Hdr.bmXState & ~pGstCtx->fXStateMask),
2794	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2795	pGstCtx->pXStateR3->Hdr.bmXState, pGstCtx->fXStateMask),
2796	VERR_CPUM_INVALID_XSAVE_HDR);
2797	}
2798	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2799	{
2800	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2801	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2802	}
2803	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2804	{
2805	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2806	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2807	}
2808	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2809	{
2810	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2811	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2812	}
2813	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2814	{
2815	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2816	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2817	}
2818	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2819	{
2820	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2821	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2822	}
2823	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2824	{
2825	if (pVM->cpum.s.GuestFeatures.fSvm)
2826	{
2827	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2828	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2829	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2830	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2831	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2832	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2833	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2834	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2835	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2836	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2837	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2838	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2839	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2840	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2841	}
2842	}
2843	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM)
2844	{
2845	if (pVM->cpum.s.GuestFeatures.fVmx)
2846	{
2847	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2848	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2849	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2850	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2851	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2852	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2853	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2854	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2855	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2856	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2857	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2858	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2859	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2860	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2861	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2862	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2863	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2864	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2865	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2866	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2867	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2868	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2869	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2870	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2871	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2872	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2873	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2874	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2875	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2876	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2877	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2878	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2879	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2880	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2881	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2882	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2883	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2884	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2885	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2886	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2887	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2888	}
2889	}
2890	}
2891	else
2892	{
2893	/*
2894	* Pre XSAVE saved state.
2895	*/
2896	SSMR3GetStructEx(pSSM, &pGstCtx->pXStateR3->x87, sizeof(pGstCtx->pXStateR3->x87),
2897	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2898	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2899	}
2900
2901	/*
2902	* Restore a couple of flags and the MSRs.
2903	*/
2904	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fUseFlags);
2905	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2906
2907	rc = VINF_SUCCESS;
2908	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2909	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2910	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2911	{
2912	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2913	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2914	}
2915	AssertRCReturn(rc, rc);
2916
2917	/* REM and other may have cleared must-be-one fields in DR6 and
2918	DR7, fix these. */
2919	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2920	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2921	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2922	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2923	}
2924
2925	/* Older states does not have the internal selector register flags
2926	and valid selector value. Supply those. */
2927	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2928	{
2929	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2930	{
2931	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2932	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2933	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2934	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2935	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2936	if (fValid)
2937	{
2938	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2939	{
2940	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2941	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2942	}
2943
2944	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2945	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2946	}
2947	else
2948	{
2949	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2950	{
2951	paSelReg[iSelReg].fFlags = 0;
2952	paSelReg[iSelReg].ValidSel = 0;
2953	}
2954
2955	/* This might not be 104% correct, but I think it's close
2956	enough for all practical purposes... (REM always loaded
2957	LDTR registers.) */
2958	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2959	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2960	}
2961	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2962	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2963	}
2964	}
2965
2966	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2967	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2968	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2969	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2970	{
2971	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2972	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2973	}
2974
2975	/*
2976	* A quick sanity check.
2977	*/
2978	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2979	{
2980	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2981	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2982	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2983	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2984	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2985	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2986	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2987	}
2988	}
2989
2990	pVM->cpum.s.fPendingRestore = false;
2991
2992	/*
2993	* Guest CPUIDs (and VMX MSR features).
2994	*/
2995	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2996	{
2997	CPUMMSRS GuestMsrs;
2998	RT_ZERO(GuestMsrs);
2999
3000	CPUMFEATURES BaseFeatures;
3001	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3002	if (fVmxGstFeat)
3003	{
3004	/*
3005	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3006	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3007	* here so we can compare them for compatibility after exploding guest features.
3008	*/
3009	BaseFeatures = pVM->cpum.s.GuestFeatures;
3010
3011	/* Use the VMX MSR features from the saved state while exploding guest features. */
3012	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3013	}
3014
3015	/* Load CPUID and explode guest features. */
3016	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3017	if (fVmxGstFeat)
3018	{
3019	/*
3020	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3021	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3022	* VMX features presented to the guest.
3023	*/
3024	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3025	if (!fIsCompat)
3026	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3027	}
3028	return rc;
3029	}
3030	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3031	}
3032
3033
3034	/**
3035	* @callback_method_impl{FNSSMINTLOADDONE}
3036	*/
3037	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3038	{
3039	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3040	return VINF_SUCCESS;
3041
3042	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3043	if (pVM->cpum.s.fPendingRestore)
3044	{
3045	LogRel(("CPUM: Missing state!\n"));
3046	return VERR_INTERNAL_ERROR_2;
3047	}
3048
3049	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3050	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3051	{
3052	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3053
3054	/* Notify PGM of the NXE states in case they've changed. */
3055	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3056
3057	/* During init. this is done in CPUMR3InitCompleted(). */
3058	if (fSupportsLongMode)
3059	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3060	}
3061	return VINF_SUCCESS;
3062	}
3063
3064
3065	/**
3066	* Checks if the CPUM state restore is still pending.
3067	*
3068	* @returns true / false.
3069	* @param pVM The cross context VM structure.
3070	*/
3071	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3072	{
3073	return pVM->cpum.s.fPendingRestore;
3074	}
3075
3076
3077	/**
3078	* Formats the EFLAGS value into mnemonics.
3079	*
3080	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3081	* @param efl The EFLAGS value.
3082	*/
3083	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3084	{
3085	/*
3086	* Format the flags.
3087	*/
3088	static const struct
3089	{
3090	const char pszSet; const char pszClear; uint32_t fFlag;
3091	} s_aFlags[] =
3092	{
3093	{ "vip",NULL, X86_EFL_VIP },
3094	{ "vif",NULL, X86_EFL_VIF },
3095	{ "ac", NULL, X86_EFL_AC },
3096	{ "vm", NULL, X86_EFL_VM },
3097	{ "rf", NULL, X86_EFL_RF },
3098	{ "nt", NULL, X86_EFL_NT },
3099	{ "ov", "nv", X86_EFL_OF },
3100	{ "dn", "up", X86_EFL_DF },
3101	{ "ei", "di", X86_EFL_IF },
3102	{ "tf", NULL, X86_EFL_TF },
3103	{ "nt", "pl", X86_EFL_SF },
3104	{ "nz", "zr", X86_EFL_ZF },
3105	{ "ac", "na", X86_EFL_AF },
3106	{ "po", "pe", X86_EFL_PF },
3107	{ "cy", "nc", X86_EFL_CF },
3108	};
3109	char *psz = pszEFlags;
3110	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3111	{
3112	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3113	if (pszAdd)
3114	{
3115	strcpy(psz, pszAdd);
3116	psz += strlen(pszAdd);
3117	*psz++ = ' ';
3118	}
3119	}
3120	psz[-1] = '\0';
3121	}
3122
3123
3124	/**
3125	* Formats a full register dump.
3126	*
3127	* @param pVM The cross context VM structure.
3128	* @param pCtx The context to format.
3129	* @param pCtxCore The context core to format.
3130	* @param pHlp Output functions.
3131	* @param enmType The dump type.
3132	* @param pszPrefix Register name prefix.
3133	*/
3134	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3135	const char *pszPrefix)
3136	{
3137	NOREF(pVM);
3138
3139	/*
3140	* Format the EFLAGS.
3141	*/
3142	uint32_t efl = pCtxCore->eflags.u32;
3143	char szEFlags[80];
3144	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3145
3146	/*
3147	* Format the registers.
3148	*/
3149	switch (enmType)
3150	{
3151	case CPUMDUMPTYPE_TERSE:
3152	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3153	pHlp->pfnPrintf(pHlp,
3154	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3155	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3156	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3157	"%sr14=%016RX64 %sr15=%016RX64\n"
3158	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3159	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3160	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3161	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3162	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3163	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3164	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3165	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3166	else
3167	pHlp->pfnPrintf(pHlp,
3168	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3169	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3170	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3171	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3172	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3173	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3174	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3175	break;
3176
3177	case CPUMDUMPTYPE_DEFAULT:
3178	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3179	pHlp->pfnPrintf(pHlp,
3180	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3181	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3182	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3183	"%sr14=%016RX64 %sr15=%016RX64\n"
3184	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3185	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3186	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3187	,
3188	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3189	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3190	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3191	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3192	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3193	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3194	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3195	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3196	else
3197	pHlp->pfnPrintf(pHlp,
3198	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3199	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3200	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3201	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3202	,
3203	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3204	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3205	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3206	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3207	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3208	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3209	break;
3210
3211	case CPUMDUMPTYPE_VERBOSE:
3212	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3213	pHlp->pfnPrintf(pHlp,
3214	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3215	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3216	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3217	"%sr14=%016RX64 %sr15=%016RX64\n"
3218	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3219	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3220	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3221	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3222	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3223	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3224	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3225	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3226	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3227	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3228	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3229	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3230	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3231	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3232	,
3233	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3234	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3235	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3236	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3237	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3238	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3239	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3240	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3241	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3242	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3243	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3244	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3245	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3246	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3247	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3248	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3249	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3250	else
3251	pHlp->pfnPrintf(pHlp,
3252	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3253	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3254	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3255	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3256	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3257	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3258	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3259	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3260	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3261	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3262	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3263	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3264	,
3265	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3266	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3267	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3268	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3269	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3270	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3271	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3272	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3273	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3274	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3275	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3276	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3277
3278	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3279	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3280	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3281	if (pCtx->CTX_SUFF(pXState))
3282	{
3283	PX86FXSTATE pFpuCtx = &pCtx->CTX_SUFF(pXState)->x87;
3284	pHlp->pfnPrintf(pHlp,
3285	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3286	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3287	,
3288	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3289	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3290	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3291	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3292	);
3293	/*
3294	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3295	* not (FP)R0-7 as Intel SDM suggests.
3296	*/
3297	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3298	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3299	{
3300	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3301	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3302	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3303	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3304	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3305	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3306	iExponent -= 16383; /* subtract bias */
3307	/** @todo This isn't entirenly correct and needs more work! */
3308	pHlp->pfnPrintf(pHlp,
3309	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3310	pszPrefix, iST, pszPrefix, iFPR,
3311	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3312	uTag, chSign, iInteger, u64Fraction, iExponent);
3313	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3314	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3315	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3316	else
3317	pHlp->pfnPrintf(pHlp, "\n");
3318	}
3319
3320	/* XMM/YMM/ZMM registers. */
3321	if (pCtx->fXStateMask & XSAVE_C_YMM)
3322	{
3323	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3324	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3325	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3326	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3327	pszPrefix, i, i < 10 ? " " : "",
3328	pYmmHiCtx->aYmmHi[i].au32[3],
3329	pYmmHiCtx->aYmmHi[i].au32[2],
3330	pYmmHiCtx->aYmmHi[i].au32[1],
3331	pYmmHiCtx->aYmmHi[i].au32[0],
3332	pFpuCtx->aXMM[i].au32[3],
3333	pFpuCtx->aXMM[i].au32[2],
3334	pFpuCtx->aXMM[i].au32[1],
3335	pFpuCtx->aXMM[i].au32[0]);
3336	else
3337	{
3338	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3339	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3340	pHlp->pfnPrintf(pHlp,
3341	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3342	pszPrefix, i, i < 10 ? " " : "",
3343	pZmmHi256->aHi256Regs[i].au32[7],
3344	pZmmHi256->aHi256Regs[i].au32[6],
3345	pZmmHi256->aHi256Regs[i].au32[5],
3346	pZmmHi256->aHi256Regs[i].au32[4],
3347	pZmmHi256->aHi256Regs[i].au32[3],
3348	pZmmHi256->aHi256Regs[i].au32[2],
3349	pZmmHi256->aHi256Regs[i].au32[1],
3350	pZmmHi256->aHi256Regs[i].au32[0],
3351	pYmmHiCtx->aYmmHi[i].au32[3],
3352	pYmmHiCtx->aYmmHi[i].au32[2],
3353	pYmmHiCtx->aYmmHi[i].au32[1],
3354	pYmmHiCtx->aYmmHi[i].au32[0],
3355	pFpuCtx->aXMM[i].au32[3],
3356	pFpuCtx->aXMM[i].au32[2],
3357	pFpuCtx->aXMM[i].au32[1],
3358	pFpuCtx->aXMM[i].au32[0]);
3359
3360	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3361	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3362	pHlp->pfnPrintf(pHlp,
3363	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3364	pszPrefix, i + 16,
3365	pZmm16Hi->aRegs[i].au32[15],
3366	pZmm16Hi->aRegs[i].au32[14],
3367	pZmm16Hi->aRegs[i].au32[13],
3368	pZmm16Hi->aRegs[i].au32[12],
3369	pZmm16Hi->aRegs[i].au32[11],
3370	pZmm16Hi->aRegs[i].au32[10],
3371	pZmm16Hi->aRegs[i].au32[9],
3372	pZmm16Hi->aRegs[i].au32[8],
3373	pZmm16Hi->aRegs[i].au32[7],
3374	pZmm16Hi->aRegs[i].au32[6],
3375	pZmm16Hi->aRegs[i].au32[5],
3376	pZmm16Hi->aRegs[i].au32[4],
3377	pZmm16Hi->aRegs[i].au32[3],
3378	pZmm16Hi->aRegs[i].au32[2],
3379	pZmm16Hi->aRegs[i].au32[1],
3380	pZmm16Hi->aRegs[i].au32[0]);
3381	}
3382	}
3383	else
3384	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3385	pHlp->pfnPrintf(pHlp,
3386	i & 1
3387	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3388	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3389	pszPrefix, i, i < 10 ? " " : "",
3390	pFpuCtx->aXMM[i].au32[3],
3391	pFpuCtx->aXMM[i].au32[2],
3392	pFpuCtx->aXMM[i].au32[1],
3393	pFpuCtx->aXMM[i].au32[0]);
3394
3395	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3396	{
3397	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3398	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3399	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3400	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3401	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3402	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3403	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3404	}
3405
3406	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3407	{
3408	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3409	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3410	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3411	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3412	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3413	}
3414
3415	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3416	{
3417	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3418	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3419	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3420	}
3421
3422	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3423	if (pFpuCtx->au32RsrvdRest[i])
3424	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3425	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3426	}
3427
3428	pHlp->pfnPrintf(pHlp,
3429	"%sEFER =%016RX64\n"
3430	"%sPAT =%016RX64\n"
3431	"%sSTAR =%016RX64\n"
3432	"%sCSTAR =%016RX64\n"
3433	"%sLSTAR =%016RX64\n"
3434	"%sSFMASK =%016RX64\n"
3435	"%sKERNELGSBASE =%016RX64\n",
3436	pszPrefix, pCtx->msrEFER,
3437	pszPrefix, pCtx->msrPAT,
3438	pszPrefix, pCtx->msrSTAR,
3439	pszPrefix, pCtx->msrCSTAR,
3440	pszPrefix, pCtx->msrLSTAR,
3441	pszPrefix, pCtx->msrSFMASK,
3442	pszPrefix, pCtx->msrKERNELGSBASE);
3443	break;
3444	}
3445	}
3446
3447
3448	/**
3449	* Display all cpu states and any other cpum info.
3450	*
3451	* @param pVM The cross context VM structure.
3452	* @param pHlp The info helper functions.
3453	* @param pszArgs Arguments, ignored.
3454	*/
3455	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3456	{
3457	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3458	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3459	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3460	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3461	cpumR3InfoHost(pVM, pHlp, pszArgs);
3462	}
3463
3464
3465	/**
3466	* Parses the info argument.
3467	*
3468	* The argument starts with 'verbose', 'terse' or 'default' and then
3469	* continues with the comment string.
3470	*
3471	* @param pszArgs The pointer to the argument string.
3472	* @param penmType Where to store the dump type request.
3473	* @param ppszComment Where to store the pointer to the comment string.
3474	*/
3475	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3476	{
3477	if (!pszArgs)
3478	{
3479	*penmType = CPUMDUMPTYPE_DEFAULT;
3480	*ppszComment = "";
3481	}
3482	else
3483	{
3484	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3485	{
3486	pszArgs += 7;
3487	*penmType = CPUMDUMPTYPE_VERBOSE;
3488	}
3489	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3490	{
3491	pszArgs += 5;
3492	*penmType = CPUMDUMPTYPE_TERSE;
3493	}
3494	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3495	{
3496	pszArgs += 7;
3497	*penmType = CPUMDUMPTYPE_DEFAULT;
3498	}
3499	else
3500	*penmType = CPUMDUMPTYPE_DEFAULT;
3501	*ppszComment = RTStrStripL(pszArgs);
3502	}
3503	}
3504
3505
3506	/**
3507	* Display the guest cpu state.
3508	*
3509	* @param pVM The cross context VM structure.
3510	* @param pHlp The info helper functions.
3511	* @param pszArgs Arguments.
3512	*/
3513	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3514	{
3515	CPUMDUMPTYPE enmType;
3516	const char *pszComment;
3517	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3518
3519	PVMCPU pVCpu = VMMGetCpu(pVM);
3520	if (!pVCpu)
3521	pVCpu = pVM->apCpusR3[0];
3522
3523	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3524
3525	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3526	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3527	}
3528
3529
3530	/**
3531	* Displays an SVM VMCB control area.
3532	*
3533	* @param pHlp The info helper functions.
3534	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3535	* @param pszPrefix Caller specified string prefix.
3536	*/
3537	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3538	{
3539	AssertReturnVoid(pHlp);
3540	AssertReturnVoid(pVmcbCtrl);
3541
3542	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3543	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3544	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3545	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3546	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3547	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3548	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3549	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3550	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3551	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3552	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3553	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3554	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3555	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3556	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3557	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3558	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3559	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3560	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3561	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3562	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3563	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3564	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3565	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3566	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3567	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3568	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3569	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3570	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3571	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3572	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3573	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3574	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3575	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3576	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3577	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3578	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3579	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3580	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3581	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3582	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3583	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3584	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3585	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3586	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3587	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3588	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3589	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3590	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3591	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3592	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3593	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3594	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3595	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3596	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3597	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3598	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3599	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3600	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3601	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3602	}
3603
3604
3605	/**
3606	* Helper for dumping the SVM VMCB selector registers.
3607	*
3608	* @param pHlp The info helper functions.
3609	* @param pSel Pointer to the SVM selector register.
3610	* @param pszName Name of the selector.
3611	* @param pszPrefix Caller specified string prefix.
3612	*/
3613	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3614	{
3615	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3616	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3617	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3618	}
3619
3620
3621	/**
3622	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3623	*
3624	* @param pHlp The info helper functions.
3625	* @param pXdtr Pointer to the descriptor table register.
3626	* @param pszName Name of the descriptor table register.
3627	* @param pszPrefix Caller specified string prefix.
3628	*/
3629	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3630	{
3631	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3632	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3633	}
3634
3635
3636	/**
3637	* Displays an SVM VMCB state-save area.
3638	*
3639	* @param pHlp The info helper functions.
3640	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3641	* @param pszPrefix Caller specified string prefix.
3642	*/
3643	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3644	{
3645	AssertReturnVoid(pHlp);
3646	AssertReturnVoid(pVmcbStateSave);
3647
3648	char szEFlags[80];
3649	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3650
3651	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3652	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3653	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3654	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3655	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3656	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3657	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3658	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3659	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3660	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3661	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3662	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3663	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3664	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3665	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3666	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3667	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3668	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3669	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3670	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3671	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3672	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3673	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3674	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3675	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3676	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3677	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3678	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3679	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3680	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3681	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3682	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3683	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3684	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3685	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3686	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3687	}
3688
3689
3690	/**
3691	* Displays a virtual-VMCS.
3692	*
3693	* @param pVCpu The cross context virtual CPU structure.
3694	* @param pHlp The info helper functions.
3695	* @param pVmcs Pointer to a virtual VMCS.
3696	* @param pszPrefix Caller specified string prefix.
3697	*/
3698	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3699	{
3700	AssertReturnVoid(pHlp);
3701	AssertReturnVoid(pVmcs);
3702
3703	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3704	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3705	do { \
3706	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3707	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3708	} while (0)
3709
3710	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3711	do { \
3712	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3713	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3714	} while (0)
3715
3716	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3717	do { \
3718	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3719	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3720	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3721	} while (0)
3722
3723	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3724	do { \
3725	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3726	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3727	} while (0)
3728
3729	/* Header. */
3730	{
3731	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3732	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3733	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3734	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3735	}
3736
3737	/* Control fields. */
3738	{
3739	/* 16-bit. */
3740	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3741	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3742	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3743	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3744
3745	/* 32-bit. */
3746	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3747	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3748	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3749	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3750	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3751	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3752	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3753	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3754	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3755	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3756	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3757	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3758	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3759	{
3760	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3761	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3762	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3763	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3764	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3765	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3766	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3767	}
3768	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3769	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3770	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3771	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3772	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3773
3774	/* 64-bit. */
3775	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3776	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3777	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3778	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3779	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3780	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3781	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3782	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3783	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3784	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3785	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3786	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3787	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3788	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3789	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3790	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3791	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3792	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 addr = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3793	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3794	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3795	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3796	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3797	pHlp->pfnPrintf(pHlp, " %sXSS-bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssBitmap.u);
3798	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsBitmap.u);
3799	pHlp->pfnPrintf(pHlp, " %sSPPT ptr = %#RX64\n", pszPrefix, pVmcs->u64SpptPtr.u);
3800	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3801
3802	/* Natural width. */
3803	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3804	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3805	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3806	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3807	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3808	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3809	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3810	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3811	}
3812
3813	/* Guest state. */
3814	{
3815	char szEFlags[80];
3816	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3817	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3818
3819	/* 16-bit. */
3820	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "cs", pszPrefix);
3821	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "ss", pszPrefix);
3822	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "es", pszPrefix);
3823	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "ds", pszPrefix);
3824	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "fs", pszPrefix);
3825	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "gs", pszPrefix);
3826	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "ldtr", pszPrefix);
3827	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "tr", pszPrefix);
3828	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3829	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3830	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3831	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3832
3833	/* 32-bit. */
3834	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3835	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3836	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3837	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3838	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3839
3840	/* 64-bit. */
3841	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3842	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3843	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3844	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3845	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3846	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3847	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3848	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3849	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3850	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3851	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3852
3853	/* Natural width. */
3854	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3855	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3856	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3857	pHlp->pfnPrintf(pHlp, " %sdr7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3858	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3859	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3860	pHlp->pfnPrintf(pHlp, " %srflags = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3861	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3862	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3863	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3864	}
3865
3866	/* Host state. */
3867	{
3868	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3869
3870	/* 16-bit. */
3871	pHlp->pfnPrintf(pHlp, " %scs = %#RX16\n", pszPrefix, pVmcs->HostCs);
3872	pHlp->pfnPrintf(pHlp, " %sss = %#RX16\n", pszPrefix, pVmcs->HostSs);
3873	pHlp->pfnPrintf(pHlp, " %sds = %#RX16\n", pszPrefix, pVmcs->HostDs);
3874	pHlp->pfnPrintf(pHlp, " %ses = %#RX16\n", pszPrefix, pVmcs->HostEs);
3875	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "fs", pszPrefix);
3876	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "gs", pszPrefix);
3877	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "tr", pszPrefix);
3878	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "gdtr", pszPrefix);
3879	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "idtr", pszPrefix);
3880
3881	/* 32-bit. */
3882	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3883
3884	/* 64-bit. */
3885	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3886	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3887	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3888
3889	/* Natural width. */
3890	pHlp->pfnPrintf(pHlp, " %scr0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3891	pHlp->pfnPrintf(pHlp, " %scr3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3892	pHlp->pfnPrintf(pHlp, " %scr4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3893	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3894	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3895	pHlp->pfnPrintf(pHlp, " %srsp = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3896	pHlp->pfnPrintf(pHlp, " %srip = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3897	}
3898
3899	/* Read-only fields. */
3900	{
3901	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3902
3903	/* 16-bit (none currently). */
3904
3905	/* 32-bit. */
3906	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3907	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3908	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3909	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3910	{
3911	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3912	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3913	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3914	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3915	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3916	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3917	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3918	}
3919	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3920	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3921	{
3922	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3923	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3924	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3925	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3926	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3927	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3928	}
3929	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3930	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3931	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3932
3933	/* 64-bit. */
3934	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3935
3936	/* Natural width. */
3937	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3938	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3939	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3940	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3941	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3942	}
3943
3944	#ifdef DEBUG_ramshankar
3945	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3946	{
3947	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3948	Assert(pvPage);
3949	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3950	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3951	if (RT_SUCCESS(rc))
3952	{
3953	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3954	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3955	pHlp->pfnPrintf(pHlp, "\n");
3956	}
3957	RTMemTmpFree(pvPage);
3958	}
3959	#else
3960	NOREF(pVCpu);
3961	#endif
3962
3963	#undef CPUMVMX_DUMP_HOST_XDTR
3964	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3965	#undef CPUMVMX_DUMP_GUEST_SEGREG
3966	#undef CPUMVMX_DUMP_GUEST_XDTR
3967	}
3968
3969
3970	/**
3971	* Display the guest's hardware-virtualization cpu state.
3972	*
3973	* @param pVM The cross context VM structure.
3974	* @param pHlp The info helper functions.
3975	* @param pszArgs Arguments, ignored.
3976	*/
3977	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3978	{
3979	RT_NOREF(pszArgs);
3980
3981	PVMCPU pVCpu = VMMGetCpu(pVM);
3982	if (!pVCpu)
3983	pVCpu = pVM->apCpusR3[0];
3984
3985	/*
3986	* Figure out what to dump.
3987	*
3988	* In the future we may need to dump everything whether or not we're actively in nested-guest mode
3989	* or not, hence the reason why we use a mask to determine what needs dumping. Currently, we only
3990	* dump hwvirt. state when the guest CPU is executing a nested-guest.
3991	*/
3992	/** @todo perhaps make this configurable through pszArgs, depending on how much
3993	* noise we wish to accept when nested hwvirt. isn't used. */
3994	#define CPUMHWVIRTDUMP_NONE (0)
3995	#define CPUMHWVIRTDUMP_SVM RT_BIT(0)
3996	#define CPUMHWVIRTDUMP_VMX RT_BIT(1)
3997	#define CPUMHWVIRTDUMP_COMMON RT_BIT(2)
3998	#define CPUMHWVIRTDUMP_LAST CPUMHWVIRTDUMP_VMX
3999
4000	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4001	static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
4002	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4003	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4004	uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
4005	AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
4006	Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
4007	const char *pcszHwvirtMode = s_aHwvirtModes[idxHwvirtState];
4008	uint32_t fDumpState = idxHwvirtState \| CPUMHWVIRTDUMP_COMMON;
4009
4010	/*
4011	* Dump it.
4012	*/
4013	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4014
4015	if (fDumpState & CPUMHWVIRTDUMP_COMMON)
4016	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
4017
4018	pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM \| CPUMHWVIRTDUMP_VMX)) ?
4019	":" : "");
4020	if (fDumpState & CPUMHWVIRTDUMP_SVM)
4021	{
4022	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4023
4024	char szEFlags[80];
4025	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4026	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4027	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4028	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4029	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
4030	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4031	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
4032	pHlp->pfnPrintf(pHlp, " HostState:\n");
4033	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4034	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4035	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4036	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4037	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4038	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4039	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4040	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4041	PCPUMSELREG pSel = &pCtx->hwvirt.svm.HostState.es;
4042	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4043	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4044	pSel = &pCtx->hwvirt.svm.HostState.cs;
4045	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4046	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4047	pSel = &pCtx->hwvirt.svm.HostState.ss;
4048	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4049	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4050	pSel = &pCtx->hwvirt.svm.HostState.ds;
4051	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4052	pSel->Sel, pSel->u64Base, pSel->u32Limit, pSel->Attr.u);
4053	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4054	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4055	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4056	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4057	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4058	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4059	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4060	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
4061	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
4062	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
4063	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
4064	}
4065
4066	if (fDumpState & CPUMHWVIRTDUMP_VMX)
4067	{
4068	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4069	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4070	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4071	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4072	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4073	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4074	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4075	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4076	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4077	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4078	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4079	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4080	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4081	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4082	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4083	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4084	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4085	cpumR3InfoVmxVmcs(pVCpu, pHlp, pCtx->hwvirt.vmx.pVmcsR3, " " /* pszPrefix */);
4086	}
4087
4088	#undef CPUMHWVIRTDUMP_NONE
4089	#undef CPUMHWVIRTDUMP_COMMON
4090	#undef CPUMHWVIRTDUMP_SVM
4091	#undef CPUMHWVIRTDUMP_VMX
4092	#undef CPUMHWVIRTDUMP_LAST
4093	#undef CPUMHWVIRTDUMP_ALL
4094	}
4095
4096	/**
4097	* Display the current guest instruction
4098	*
4099	* @param pVM The cross context VM structure.
4100	* @param pHlp The info helper functions.
4101	* @param pszArgs Arguments, ignored.
4102	*/
4103	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4104	{
4105	NOREF(pszArgs);
4106
4107	PVMCPU pVCpu = VMMGetCpu(pVM);
4108	if (!pVCpu)
4109	pVCpu = pVM->apCpusR3[0];
4110
4111	char szInstruction[256];
4112	szInstruction[0] = '\0';
4113	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4114	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4115	}
4116
4117
4118	/**
4119	* Display the hypervisor cpu state.
4120	*
4121	* @param pVM The cross context VM structure.
4122	* @param pHlp The info helper functions.
4123	* @param pszArgs Arguments, ignored.
4124	*/
4125	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4126	{
4127	PVMCPU pVCpu = VMMGetCpu(pVM);
4128	if (!pVCpu)
4129	pVCpu = pVM->apCpusR3[0];
4130
4131	CPUMDUMPTYPE enmType;
4132	const char *pszComment;
4133	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4134	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4135
4136	pHlp->pfnPrintf(pHlp,
4137	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4138	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4139	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4140	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4141	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4142	}
4143
4144
4145	/**
4146	* Display the host cpu state.
4147	*
4148	* @param pVM The cross context VM structure.
4149	* @param pHlp The info helper functions.
4150	* @param pszArgs Arguments, ignored.
4151	*/
4152	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4153	{
4154	CPUMDUMPTYPE enmType;
4155	const char *pszComment;
4156	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4157	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4158
4159	PVMCPU pVCpu = VMMGetCpu(pVM);
4160	if (!pVCpu)
4161	pVCpu = pVM->apCpusR3[0];
4162	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4163
4164	/*
4165	* Format the EFLAGS.
4166	*/
4167	uint64_t efl = pCtx->rflags;
4168	char szEFlags[80];
4169	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4170
4171	/*
4172	* Format the registers.
4173	*/
4174	pHlp->pfnPrintf(pHlp,
4175	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4176	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4177	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4178	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4179	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4180	"r14=%016RX64 r15=%016RX64\n"
4181	"iopl=%d %31s\n"
4182	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4183	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4184	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4185	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4186	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4187	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4188	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4189	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4190	,
4191	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4192	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4193	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4194	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4195	pCtx->r11, pCtx->r12, pCtx->r13,
4196	pCtx->r14, pCtx->r15,
4197	X86_EFL_GET_IOPL(efl), szEFlags,
4198	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4199	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4200	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4201	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4202	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4203	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4204	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4205	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4206	}
4207
4208	/**
4209	* Structure used when disassembling and instructions in DBGF.
4210	* This is used so the reader function can get the stuff it needs.
4211	*/
4212	typedef struct CPUMDISASSTATE
4213	{
4214	/** Pointer to the CPU structure. */
4215	PDISCPUSTATE pCpu;
4216	/** Pointer to the VM. */
4217	PVM pVM;
4218	/** Pointer to the VMCPU. */
4219	PVMCPU pVCpu;
4220	/** Pointer to the first byte in the segment. */
4221	RTGCUINTPTR GCPtrSegBase;
4222	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4223	RTGCUINTPTR GCPtrSegEnd;
4224	/** The size of the segment minus 1. */
4225	RTGCUINTPTR cbSegLimit;
4226	/** Pointer to the current page - R3 Ptr. */
4227	void const *pvPageR3;
4228	/** Pointer to the current page - GC Ptr. */
4229	RTGCPTR pvPageGC;
4230	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4231	PGMPAGEMAPLOCK PageMapLock;
4232	/** Whether the PageMapLock is valid or not. */
4233	bool fLocked;
4234	/** 64 bits mode or not. */
4235	bool f64Bits;
4236	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4237
4238
4239	/**
4240	* @callback_method_impl{FNDISREADBYTES}
4241	*/
4242	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4243	{
4244	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4245	for (;;)
4246	{
4247	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4248
4249	/*
4250	* Need to update the page translation?
4251	*/
4252	if ( !pState->pvPageR3
4253	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4254	{
4255	/* translate the address */
4256	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4257
4258	/* Release mapping lock previously acquired. */
4259	if (pState->fLocked)
4260	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4261	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4262	if (RT_SUCCESS(rc))
4263	pState->fLocked = true;
4264	else
4265	{
4266	pState->fLocked = false;
4267	pState->pvPageR3 = NULL;
4268	return rc;
4269	}
4270	}
4271
4272	/*
4273	* Check the segment limit.
4274	*/
4275	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4276	return VERR_OUT_OF_SELECTOR_BOUNDS;
4277
4278	/*
4279	* Calc how much we can read.
4280	*/
4281	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4282	if (!pState->f64Bits)
4283	{
4284	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4285	if (cb > cbSeg && cbSeg)
4286	cb = cbSeg;
4287	}
4288	if (cb > cbMaxRead)
4289	cb = cbMaxRead;
4290
4291	/*
4292	* Read and advance or exit.
4293	*/
4294	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4295	offInstr += (uint8_t)cb;
4296	if (cb >= cbMinRead)
4297	{
4298	pDis->cbCachedInstr = offInstr;
4299	return VINF_SUCCESS;
4300	}
4301	cbMinRead -= (uint8_t)cb;
4302	cbMaxRead -= (uint8_t)cb;
4303	}
4304	}
4305
4306
4307	/**
4308	* Disassemble an instruction and return the information in the provided structure.
4309	*
4310	* @returns VBox status code.
4311	* @param pVM The cross context VM structure.
4312	* @param pVCpu The cross context virtual CPU structure.
4313	* @param pCtx Pointer to the guest CPU context.
4314	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4315	* @param pCpu Disassembly state.
4316	* @param pszPrefix String prefix for logging (debug only).
4317	*
4318	*/
4319	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4320	const char *pszPrefix)
4321	{
4322	CPUMDISASSTATE State;
4323	int rc;
4324
4325	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4326	State.pCpu = pCpu;
4327	State.pvPageGC = 0;
4328	State.pvPageR3 = NULL;
4329	State.pVM = pVM;
4330	State.pVCpu = pVCpu;
4331	State.fLocked = false;
4332	State.f64Bits = false;
4333
4334	/*
4335	* Get selector information.
4336	*/
4337	DISCPUMODE enmDisCpuMode;
4338	if ( (pCtx->cr0 & X86_CR0_PE)
4339	&& pCtx->eflags.Bits.u1VM == 0)
4340	{
4341	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4342	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4343	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4344	State.GCPtrSegBase = pCtx->cs.u64Base;
4345	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4346	State.cbSegLimit = pCtx->cs.u32Limit;
4347	enmDisCpuMode = (State.f64Bits)
4348	? DISCPUMODE_64BIT
4349	: pCtx->cs.Attr.n.u1DefBig
4350	? DISCPUMODE_32BIT
4351	: DISCPUMODE_16BIT;
4352	}
4353	else
4354	{
4355	/* real or V86 mode */
4356	enmDisCpuMode = DISCPUMODE_16BIT;
4357	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4358	State.GCPtrSegEnd = 0xFFFFFFFF;
4359	State.cbSegLimit = 0xFFFFFFFF;
4360	}
4361
4362	/*
4363	* Disassemble the instruction.
4364	*/
4365	uint32_t cbInstr;
4366	#ifndef LOG_ENABLED
4367	RT_NOREF_PV(pszPrefix);
4368	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4369	if (RT_SUCCESS(rc))
4370	{
4371	#else
4372	char szOutput[160];
4373	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4374	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4375	if (RT_SUCCESS(rc))
4376	{
4377	/* log it */
4378	if (pszPrefix)
4379	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4380	else
4381	Log(("%s", szOutput));
4382	#endif
4383	rc = VINF_SUCCESS;
4384	}
4385	else
4386	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4387
4388	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4389	if (State.fLocked)
4390	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4391
4392	return rc;
4393	}
4394
4395
4396
4397	/**
4398	* API for controlling a few of the CPU features found in CR4.
4399	*
4400	* Currently only X86_CR4_TSD is accepted as input.
4401	*
4402	* @returns VBox status code.
4403	*
4404	* @param pVM The cross context VM structure.
4405	* @param fOr The CR4 OR mask.
4406	* @param fAnd The CR4 AND mask.
4407	*/
4408	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4409	{
4410	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4411	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4412
4413	pVM->cpum.s.CR4.OrMask &= fAnd;
4414	pVM->cpum.s.CR4.OrMask \|= fOr;
4415
4416	return VINF_SUCCESS;
4417	}
4418
4419
4420	/**
4421	* Enters REM, gets and resets the changed flags (CPUM_CHANGED_*).
4422	*
4423	* Only REM should ever call this function!
4424	*
4425	* @returns The changed flags.
4426	* @param pVCpu The cross context virtual CPU structure.
4427	* @param puCpl Where to return the current privilege level (CPL).
4428	*/
4429	VMMR3DECL(uint32_t) CPUMR3RemEnter(PVMCPU pVCpu, uint32_t *puCpl)
4430	{
4431	Assert(!pVCpu->cpum.s.fRemEntered);
4432
4433	/*
4434	* Get the CPL first.
4435	*/
4436	*puCpl = CPUMGetGuestCPL(pVCpu);
4437
4438	/*
4439	* Get and reset the flags.
4440	*/
4441	uint32_t fFlags = pVCpu->cpum.s.fChanged;
4442	pVCpu->cpum.s.fChanged = 0;
4443
4444	/** @todo change the switcher to use the fChanged flags. */
4445	if (pVCpu->cpum.s.fUseFlags & CPUM_USED_FPU_SINCE_REM)
4446	{
4447	fFlags \|= CPUM_CHANGED_FPU_REM;
4448	pVCpu->cpum.s.fUseFlags &= ~CPUM_USED_FPU_SINCE_REM;
4449	}
4450
4451	pVCpu->cpum.s.fRemEntered = true;
4452	return fFlags;
4453	}
4454
4455
4456	/**
4457	* Leaves REM.
4458	*
4459	* @param pVCpu The cross context virtual CPU structure.
4460	* @param fNoOutOfSyncSels This is @c false if there are out of sync
4461	* registers.
4462	*/
4463	VMMR3DECL(void) CPUMR3RemLeave(PVMCPU pVCpu, bool fNoOutOfSyncSels)
4464	{
4465	Assert(pVCpu->cpum.s.fRemEntered);
4466
4467	RT_NOREF_PV(fNoOutOfSyncSels);
4468
4469	pVCpu->cpum.s.fRemEntered = false;
4470	}
4471
4472
4473	/**
4474	* Called when the ring-3 init phase completes.
4475	*
4476	* @returns VBox status code.
4477	* @param pVM The cross context VM structure.
4478	* @param enmWhat Which init phase.
4479	*/
4480	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4481	{
4482	switch (enmWhat)
4483	{
4484	case VMINITCOMPLETED_RING3:
4485	{
4486	/*
4487	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4488	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4489	*/
4490	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4491	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4492	{
4493	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4494
4495	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4496	if (fSupportsLongMode)
4497	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4498	}
4499
4500	/* Register statistic counters for MSRs. */
4501	cpumR3MsrRegStats(pVM);
4502	break;
4503	}
4504
4505	default:
4506	break;
4507	}
4508	return VINF_SUCCESS;
4509	}
4510
4511
4512	/**
4513	* Called when the ring-0 init phases completed.
4514	*
4515	* @param pVM The cross context VM structure.
4516	*/
4517	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4518	{
4519	/*
4520	* Enable log buffering as we're going to log a lot of lines.
4521	*/
4522	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4523
4524	/*
4525	* Log the cpuid.
4526	*/
4527	RTCPUSET OnlineSet;
4528	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4529	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4530	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4531	RTCPUID cCores = RTMpGetCoreCount();
4532	if (cCores)
4533	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4534	LogRel(("*********************** CPUID dump **********************\n"));
4535	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4536	LogRel(("\n"));
4537	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4538	LogRel(("****************** End of CPUID dump ********************\n"));
4539
4540	/*
4541	* Log VT-x extended features.
4542	*
4543	* SVM features are currently all covered under CPUID so there is nothing
4544	* to do here for SVM.
4545	*/
4546	if (pVM->cpum.s.HostFeatures.fVmx)
4547	{
4548	LogRel(("********************* VT-x features *********************\n"));
4549	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4550	LogRel(("\n"));
4551	LogRel(("***************** End of VT-x features ******************\n"));
4552	}
4553
4554	/*
4555	* Restore the log buffering state to what it was previously.
4556	*/
4557	RTLogRelSetBuffering(fOldBuffered);
4558	}
4559

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 80387

Download in other formats: