CPUM.cpp@ 91281

Last change on this file since 91281 was 91281, checked in by vboxsync, 4 years ago
VMM/CPUM,++: Moved the guest's extended state (XState) from the hyper heap and into CPUMCTX. bugref:10093
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1	/* $Id: CPUM.cpp 91281 2021-09-16 13:32:18Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/hm.h>
120	#include <VBox/vmm/hmvmxinline.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
339
340	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
341	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
342	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
343	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
344	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
345	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
346	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
347	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
348	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
349
350	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
351	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
352
353	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
354	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
355	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
356	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
357	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
358	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
360
361	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
362	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
363	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
364	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
365
366	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
367	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
369	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
370	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
371	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
373	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
374	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
378	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
379	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
380	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
381	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
382	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
383	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
384	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
385
386	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
387	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
388	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
389	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
390	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
391	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
392	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
393	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
394	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
395	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
396	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
397	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
398	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
399	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
400	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
401	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
402	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
403	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
404	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
405	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
406	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
407	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
408	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
409	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
410	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
411	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
412	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
413	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
414	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
415
416	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
417	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
418	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
419	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
420	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
421	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
422	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
423	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
424	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
425
426	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
427	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
428	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
429	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
430	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
431	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
432	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
433	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
434
435	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
436	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
437
438	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
439	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
440	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
441	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
442	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
443
444	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
445	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
446	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
447	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
448	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
449	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
450	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
451	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
452	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
453	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
454	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
455	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
456	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
457	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
458	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
459	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
460
461	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
462	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
463	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
464	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
465	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
466	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
467	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
468	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
469	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
470	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
471	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
472
473	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
474	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
475	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
476	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
477	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
478	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
479	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
480	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
481	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
482	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
483	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
484	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
485	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
486	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
487	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
488	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
489	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
490	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
491	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
492	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
493	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
494	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
495	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
496	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
497
498	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
503	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
504	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
509	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
510	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
511
512	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
513	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
514	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
515	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
519	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
520	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
521	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
532	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
533	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
534	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
535	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
536
537	SSMFIELD_ENTRY_TERM()
538	};
539
540	/** Saved state field descriptors for CPUMCTX. */
541	static const SSMFIELD g_aCpumX87Fields[] =
542	{
543	SSMFIELD_ENTRY( X86FXSTATE, FCW),
544	SSMFIELD_ENTRY( X86FXSTATE, FSW),
545	SSMFIELD_ENTRY( X86FXSTATE, FTW),
546	SSMFIELD_ENTRY( X86FXSTATE, FOP),
547	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
548	SSMFIELD_ENTRY( X86FXSTATE, CS),
549	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
550	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
551	SSMFIELD_ENTRY( X86FXSTATE, DS),
552	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
553	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
554	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
555	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
556	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
557	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
558	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
559	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
560	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
561	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
562	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
564	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
565	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
566	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
567	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
568	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
569	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
570	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
571	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
572	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
573	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
574	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
575	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
576	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
577	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
578	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
579	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
580	SSMFIELD_ENTRY_TERM()
581	};
582
583	/** Saved state field descriptors for X86XSAVEHDR. */
584	static const SSMFIELD g_aCpumXSaveHdrFields[] =
585	{
586	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
587	SSMFIELD_ENTRY_TERM()
588	};
589
590	/** Saved state field descriptors for X86XSAVEYMMHI. */
591	static const SSMFIELD g_aCpumYmmHiFields[] =
592	{
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
594	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
595	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
596	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
597	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
598	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
599	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
600	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
601	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
602	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
603	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
604	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
605	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
606	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
607	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
608	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
609	SSMFIELD_ENTRY_TERM()
610	};
611
612	/** Saved state field descriptors for X86XSAVEBNDREGS. */
613	static const SSMFIELD g_aCpumBndRegsFields[] =
614	{
615	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
616	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
617	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
618	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
619	SSMFIELD_ENTRY_TERM()
620	};
621
622	/** Saved state field descriptors for X86XSAVEBNDCFG. */
623	static const SSMFIELD g_aCpumBndCfgFields[] =
624	{
625	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
626	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
627	SSMFIELD_ENTRY_TERM()
628	};
629
630	#if 0 /** @todo */
631	/** Saved state field descriptors for X86XSAVEOPMASK. */
632	static const SSMFIELD g_aCpumOpmaskFields[] =
633	{
634	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
635	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
636	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
637	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
638	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
639	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
640	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
641	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
642	SSMFIELD_ENTRY_TERM()
643	};
644	#endif
645
646	/** Saved state field descriptors for X86XSAVEZMMHI256. */
647	static const SSMFIELD g_aCpumZmmHi256Fields[] =
648	{
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
650	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
651	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
652	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
653	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
654	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
655	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
656	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
657	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
658	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
659	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
660	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
661	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
662	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
663	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
664	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
665	SSMFIELD_ENTRY_TERM()
666	};
667
668	/** Saved state field descriptors for X86XSAVEZMM16HI. */
669	static const SSMFIELD g_aCpumZmm16HiFields[] =
670	{
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
672	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
673	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
674	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
675	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
676	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
677	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
678	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
679	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
680	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
681	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
682	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
683	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
684	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
685	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
686	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
687	SSMFIELD_ENTRY_TERM()
688	};
689
690
691
692	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
693	* registeres changed. */
694	static const SSMFIELD g_aCpumX87FieldsMem[] =
695	{
696	SSMFIELD_ENTRY( X86FXSTATE, FCW),
697	SSMFIELD_ENTRY( X86FXSTATE, FSW),
698	SSMFIELD_ENTRY( X86FXSTATE, FTW),
699	SSMFIELD_ENTRY( X86FXSTATE, FOP),
700	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
701	SSMFIELD_ENTRY( X86FXSTATE, CS),
702	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
703	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
704	SSMFIELD_ENTRY( X86FXSTATE, DS),
705	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
706	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
707	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
708	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
709	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
710	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
711	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
712	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
713	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
714	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
715	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
717	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
718	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
719	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
720	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
721	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
722	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
723	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
724	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
725	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
726	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
727	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
728	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
729	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
730	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
731	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
732	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
733	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
734	};
735
736	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
737	* registeres changed. */
738	static const SSMFIELD g_aCpumCtxFieldsMem[] =
739	{
740	SSMFIELD_ENTRY( CPUMCTX, rdi),
741	SSMFIELD_ENTRY( CPUMCTX, rsi),
742	SSMFIELD_ENTRY( CPUMCTX, rbp),
743	SSMFIELD_ENTRY( CPUMCTX, rax),
744	SSMFIELD_ENTRY( CPUMCTX, rbx),
745	SSMFIELD_ENTRY( CPUMCTX, rdx),
746	SSMFIELD_ENTRY( CPUMCTX, rcx),
747	SSMFIELD_ENTRY( CPUMCTX, rsp),
748	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
749	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
750	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
751	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
752	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
753	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
754	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
755	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
756	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
757	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
758	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
759	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
760	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
761	SSMFIELD_ENTRY( CPUMCTX, rflags),
762	SSMFIELD_ENTRY( CPUMCTX, rip),
763	SSMFIELD_ENTRY( CPUMCTX, r8),
764	SSMFIELD_ENTRY( CPUMCTX, r9),
765	SSMFIELD_ENTRY( CPUMCTX, r10),
766	SSMFIELD_ENTRY( CPUMCTX, r11),
767	SSMFIELD_ENTRY( CPUMCTX, r12),
768	SSMFIELD_ENTRY( CPUMCTX, r13),
769	SSMFIELD_ENTRY( CPUMCTX, r14),
770	SSMFIELD_ENTRY( CPUMCTX, r15),
771	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
772	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
773	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
774	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
775	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
776	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
777	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
778	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
779	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
780	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
781	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
782	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
783	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
784	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
785	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
786	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
787	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
788	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
789	SSMFIELD_ENTRY( CPUMCTX, cr0),
790	SSMFIELD_ENTRY( CPUMCTX, cr2),
791	SSMFIELD_ENTRY( CPUMCTX, cr3),
792	SSMFIELD_ENTRY( CPUMCTX, cr4),
793	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
794	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
795	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
796	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
797	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
798	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
799	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
800	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
801	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
802	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
803	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
804	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
805	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
806	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
807	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
808	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
809	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
810	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
811	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
812	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
813	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
814	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
815	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
816	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
817	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
818	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
819	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
820	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
821	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
822	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
823	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
824	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
825	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
826	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
827	SSMFIELD_ENTRY_TERM()
828	};
829
830	/** Saved state field descriptors for CPUMCTX_VER1_6. */
831	static const SSMFIELD g_aCpumX87FieldsV16[] =
832	{
833	SSMFIELD_ENTRY( X86FXSTATE, FCW),
834	SSMFIELD_ENTRY( X86FXSTATE, FSW),
835	SSMFIELD_ENTRY( X86FXSTATE, FTW),
836	SSMFIELD_ENTRY( X86FXSTATE, FOP),
837	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
838	SSMFIELD_ENTRY( X86FXSTATE, CS),
839	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
840	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
841	SSMFIELD_ENTRY( X86FXSTATE, DS),
842	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
843	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
844	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
845	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
846	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
847	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
848	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
849	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
850	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
851	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
852	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
854	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
855	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
856	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
857	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
858	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
859	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
860	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
861	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
862	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
863	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
864	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
865	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
866	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
867	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
868	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
869	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
870	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
871	SSMFIELD_ENTRY_TERM()
872	};
873
874	/** Saved state field descriptors for CPUMCTX_VER1_6. */
875	static const SSMFIELD g_aCpumCtxFieldsV16[] =
876	{
877	SSMFIELD_ENTRY( CPUMCTX, rdi),
878	SSMFIELD_ENTRY( CPUMCTX, rsi),
879	SSMFIELD_ENTRY( CPUMCTX, rbp),
880	SSMFIELD_ENTRY( CPUMCTX, rax),
881	SSMFIELD_ENTRY( CPUMCTX, rbx),
882	SSMFIELD_ENTRY( CPUMCTX, rdx),
883	SSMFIELD_ENTRY( CPUMCTX, rcx),
884	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
885	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
886	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
887	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
888	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
889	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
890	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
891	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
892	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
893	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
894	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
895	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
896	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
897	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
898	SSMFIELD_ENTRY( CPUMCTX, rflags),
899	SSMFIELD_ENTRY( CPUMCTX, rip),
900	SSMFIELD_ENTRY( CPUMCTX, r8),
901	SSMFIELD_ENTRY( CPUMCTX, r9),
902	SSMFIELD_ENTRY( CPUMCTX, r10),
903	SSMFIELD_ENTRY( CPUMCTX, r11),
904	SSMFIELD_ENTRY( CPUMCTX, r12),
905	SSMFIELD_ENTRY( CPUMCTX, r13),
906	SSMFIELD_ENTRY( CPUMCTX, r14),
907	SSMFIELD_ENTRY( CPUMCTX, r15),
908	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
909	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
910	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
911	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
912	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
913	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
914	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
915	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
916	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
917	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
918	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
919	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
920	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
921	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
922	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
923	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
924	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
925	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
926	SSMFIELD_ENTRY( CPUMCTX, cr0),
927	SSMFIELD_ENTRY( CPUMCTX, cr2),
928	SSMFIELD_ENTRY( CPUMCTX, cr3),
929	SSMFIELD_ENTRY( CPUMCTX, cr4),
930	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
931	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
932	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
933	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
934	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
935	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
936	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
937	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
938	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
939	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
940	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
941	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
942	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
943	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
944	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
945	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
946	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
947	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
948	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
949	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
950	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
951	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
952	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
953	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
954	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
955	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
956	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
957	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
958	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
959	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
960	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
961	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
962	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
963	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
964	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
965	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
966	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
967	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
968	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
969	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
970	SSMFIELD_ENTRY_TERM()
971	};
972
973
974	/**
975	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
976	*
977	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
978	* (last instruction pointer, last data pointer, last opcode) except when the ES
979	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
980	* clear these registers there is potential, local FPU leakage from a process
981	* using the FPU to another.
982	*
983	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
984	*
985	* @param pVM The cross context VM structure.
986	*/
987	static void cpumR3CheckLeakyFpu(PVM pVM)
988	{
989	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
990	uint32_t const u32Family = u32CpuVersion >> 8;
991	if ( u32Family >= 6 /* K7 and higher */
992	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
993	{
994	uint32_t cExt = ASMCpuId_EAX(0x80000000);
995	if (ASMIsValidExtRange(cExt))
996	{
997	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
998	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
999	{
1000	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1001	{
1002	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1003	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1004	}
1005	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1006	}
1007	}
1008	}
1009	}
1010
1011
1012	/**
1013	* Frees memory allocated for the SVM hardware virtualization state.
1014	*
1015	* @param pVM The cross context VM structure.
1016	*/
1017	static void cpumR3FreeSvmHwVirtState(PVM pVM)
1018	{
1019	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1020	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1021	{
1022	PVMCPU pVCpu = pVM->apCpusR3[i];
1023	if (pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3)
1024	{
1025	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES);
1026	pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3 = NULL;
1027	}
1028	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = NIL_RTHCPHYS;
1029
1030	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3)
1031	{
1032	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES);
1033	pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3 = NULL;
1034	}
1035
1036	if (pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3)
1037	{
1038	SUPR3PageFreeEx(pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES);
1039	pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3 = NULL;
1040	}
1041	}
1042	}
1043
1044
1045	/**
1046	* Allocates memory for the SVM hardware virtualization state.
1047	*
1048	* @returns VBox status code.
1049	* @param pVM The cross context VM structure.
1050	*/
1051	static int cpumR3AllocSvmHwVirtState(PVM pVM)
1052	{
1053	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1054
1055	int rc = VINF_SUCCESS;
1056	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
1057	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
1058	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1059	{
1060	PVMCPU pVCpu = pVM->apCpusR3[i];
1061	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1062
1063	/*
1064	* Allocate the nested-guest VMCB.
1065	*/
1066	SUPPAGE SupNstGstVmcbPage;
1067	RT_ZERO(SupNstGstVmcbPage);
1068	SupNstGstVmcbPage.Phys = NIL_RTHCPHYS;
1069	Assert(SVM_VMCB_PAGES == 1);
1070	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1071	rc = SUPR3PageAllocEx(SVM_VMCB_PAGES, 0 /* fFlags /, (void *)&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3,
1072	&pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR0, &SupNstGstVmcbPage);
1073	if (RT_FAILURE(rc))
1074	{
1075	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pVmcbR3);
1076	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCB\n", pVCpu->idCpu, SVM_VMCB_PAGES));
1077	break;
1078	}
1079	pVCpu->cpum.s.Guest.hwvirt.svm.HCPhysVmcb = SupNstGstVmcbPage.Phys;
1080
1081	/*
1082	* Allocate the MSRPM (MSR Permission bitmap).
1083	*
1084	* This need not be physically contiguous pages because we use the one from
1085	* HMPHYSCPU while executing the nested-guest using hardware-assisted SVM.
1086	* This one is just used for caching the bitmap from guest physical memory.
1087	*/
1088	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1089	rc = SUPR3PageAllocEx(SVM_MSRPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3,
1090	&pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR0, NULL /* paPages */);
1091	if (RT_FAILURE(rc))
1092	{
1093	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvMsrBitmapR3);
1094	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR permission bitmap\n", pVCpu->idCpu,
1095	SVM_MSRPM_PAGES));
1096	break;
1097	}
1098
1099	/*
1100	* Allocate the IOPM (IO Permission bitmap).
1101	*
1102	* This need not be physically contiguous pages because we re-use the ring-0
1103	* allocated IOPM while executing the nested-guest using hardware-assisted SVM
1104	* because it's identical (we trap all IO accesses).
1105	*
1106	* This one is just used for caching the IOPM from guest physical memory in
1107	* case the guest hypervisor allows direct access to some IO ports.
1108	*/
1109	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1110	rc = SUPR3PageAllocEx(SVM_IOPM_PAGES, 0 /* fFlags */, &pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3,
1111	&pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR0, NULL /* paPages */);
1112	if (RT_FAILURE(rc))
1113	{
1114	Assert(!pVCpu->cpum.s.Guest.hwvirt.svm.pvIoBitmapR3);
1115	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's IO permission bitmap\n", pVCpu->idCpu,
1116	SVM_IOPM_PAGES));
1117	break;
1118	}
1119	}
1120
1121	/* On any failure, cleanup. */
1122	if (RT_FAILURE(rc))
1123	cpumR3FreeSvmHwVirtState(pVM);
1124
1125	return rc;
1126	}
1127
1128
1129	/**
1130	* Resets per-VCPU SVM hardware virtualization state.
1131	*
1132	* @param pVCpu The cross context virtual CPU structure.
1133	*/
1134	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1135	{
1136	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1137	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1138	Assert(pCtx->hwvirt.svm.CTX_SUFF(pVmcb));
1139
1140	memset(pCtx->hwvirt.svm.CTX_SUFF(pVmcb), 0, SVM_VMCB_PAGES << PAGE_SHIFT);
1141	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1142	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1143	}
1144
1145
1146	/**
1147	* Frees memory allocated for the VMX hardware virtualization state.
1148	*
1149	* @param pVM The cross context VM structure.
1150	*/
1151	static void cpumR3FreeVmxHwVirtState(PVM pVM)
1152	{
1153	Assert(pVM->cpum.s.GuestFeatures.fVmx);
1154	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1155	{
1156	PVMCPU pVCpu = pVM->apCpusR3[i];
1157	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1158
1159	if (pCtx->hwvirt.vmx.pVmcsR3)
1160	{
1161	SUPR3ContFree(pCtx->hwvirt.vmx.pVmcsR3, VMX_V_VMCS_PAGES);
1162	pCtx->hwvirt.vmx.pVmcsR3 = NULL;
1163	}
1164	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1165	{
1166	SUPR3ContFree(pCtx->hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
1167	pCtx->hwvirt.vmx.pShadowVmcsR3 = NULL;
1168	}
1169	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1170	{
1171	SUPR3ContFree(pCtx->hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
1172	pCtx->hwvirt.vmx.pvVirtApicPageR3 = NULL;
1173	}
1174	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1175	{
1176	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1177	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = NULL;
1178	}
1179	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1180	{
1181	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1182	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
1183	}
1184	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1185	{
1186	SUPR3ContFree(pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1187	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = NULL;
1188	}
1189	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1190	{
1191	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1192	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = NULL;
1193	}
1194	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1195	{
1196	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1197	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = NULL;
1198	}
1199	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1200	{
1201	SUPR3ContFree(pCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
1202	pCtx->hwvirt.vmx.pvMsrBitmapR3 = NULL;
1203	}
1204	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1205	{
1206	SUPR3ContFree(pCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1207	pCtx->hwvirt.vmx.pvIoBitmapR3 = NULL;
1208	}
1209	}
1210	}
1211
1212
1213	/**
1214	* Allocates memory for the VMX hardware virtualization state.
1215	*
1216	* @returns VBox status code.
1217	* @param pVM The cross context VM structure.
1218	*/
1219	static int cpumR3AllocVmxHwVirtState(PVM pVM)
1220	{
1221	int rc = VINF_SUCCESS;
1222	uint32_t const cPages = VMX_V_VMCS_PAGES
1223	+ VMX_V_SHADOW_VMCS_PAGES
1224	+ VMX_V_VIRT_APIC_PAGES
1225	+ (2 * VMX_V_VMREAD_VMWRITE_BITMAP_PAGES)
1226	+ (3 * VMX_V_AUTOMSR_AREA_PAGES)
1227	+ VMX_V_MSR_BITMAP_PAGES
1228	+ (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1229	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n", pVM->cCpus * cPages));
1230	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1231	{
1232	PVMCPU pVCpu = pVM->apCpusR3[i];
1233	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1234	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1235
1236	/*
1237	* Allocate the nested-guest current VMCS.
1238	*/
1239	pCtx->hwvirt.vmx.pVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1240	&pCtx->hwvirt.vmx.pVmcsR0,
1241	&pCtx->hwvirt.vmx.HCPhysVmcs);
1242	if (pCtx->hwvirt.vmx.pVmcsR3)
1243	{ /* likely */ }
1244	else
1245	{
1246	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1247	break;
1248	}
1249
1250	/*
1251	* Allocate the nested-guest shadow VMCS.
1252	*/
1253	pCtx->hwvirt.vmx.pShadowVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES,
1254	&pCtx->hwvirt.vmx.pShadowVmcsR0,
1255	&pCtx->hwvirt.vmx.HCPhysShadowVmcs);
1256	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1257	{ /* likely */ }
1258	else
1259	{
1260	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1261	break;
1262	}
1263
1264	/*
1265	* Allocate the virtual-APIC page.
1266	*/
1267	pCtx->hwvirt.vmx.pvVirtApicPageR3 = SUPR3ContAlloc(VMX_V_VIRT_APIC_PAGES,
1268	&pCtx->hwvirt.vmx.pvVirtApicPageR0,
1269	&pCtx->hwvirt.vmx.HCPhysVirtApicPage);
1270	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1271	{ /* likely */ }
1272	else
1273	{
1274	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's virtual-APIC page\n", pVCpu->idCpu,
1275	VMX_V_VIRT_APIC_PAGES));
1276	break;
1277	}
1278
1279	/*
1280	* Allocate the VMREAD-bitmap.
1281	*/
1282	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1283	&pCtx->hwvirt.vmx.pvVmreadBitmapR0,
1284	&pCtx->hwvirt.vmx.HCPhysVmreadBitmap);
1285	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1286	{ /* likely */ }
1287	else
1288	{
1289	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1290	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1291	break;
1292	}
1293
1294	/*
1295	* Allocatge the VMWRITE-bitmap.
1296	*/
1297	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1298	&pCtx->hwvirt.vmx.pvVmwriteBitmapR0,
1299	&pCtx->hwvirt.vmx.HCPhysVmwriteBitmap);
1300	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1301	{ /* likely */ }
1302	else
1303	{
1304	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1305	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1306	break;
1307	}
1308
1309	/*
1310	* Allocate the VM-entry MSR-load area.
1311	*/
1312	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1313	&pCtx->hwvirt.vmx.pEntryMsrLoadAreaR0,
1314	&pCtx->hwvirt.vmx.HCPhysEntryMsrLoadArea);
1315	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1316	{ /* likely */ }
1317	else
1318	{
1319	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-entry MSR-load area\n", pVCpu->idCpu,
1320	VMX_V_AUTOMSR_AREA_PAGES));
1321	break;
1322	}
1323
1324	/*
1325	* Allocate the VM-exit MSR-store area.
1326	*/
1327	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1328	&pCtx->hwvirt.vmx.pExitMsrStoreAreaR0,
1329	&pCtx->hwvirt.vmx.HCPhysExitMsrStoreArea);
1330	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1331	{ /* likely */ }
1332	else
1333	{
1334	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-store area\n", pVCpu->idCpu,
1335	VMX_V_AUTOMSR_AREA_PAGES));
1336	break;
1337	}
1338
1339	/*
1340	* Allocate the VM-exit MSR-load area.
1341	*/
1342	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1343	&pCtx->hwvirt.vmx.pExitMsrLoadAreaR0,
1344	&pCtx->hwvirt.vmx.HCPhysExitMsrLoadArea);
1345	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1346	{ /* likely */ }
1347	else
1348	{
1349	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-load area\n", pVCpu->idCpu,
1350	VMX_V_AUTOMSR_AREA_PAGES));
1351	break;
1352	}
1353
1354	/*
1355	* Allocate the MSR bitmap.
1356	*/
1357	pCtx->hwvirt.vmx.pvMsrBitmapR3 = SUPR3ContAlloc(VMX_V_MSR_BITMAP_PAGES,
1358	&pCtx->hwvirt.vmx.pvMsrBitmapR0,
1359	&pCtx->hwvirt.vmx.HCPhysMsrBitmap);
1360	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1361	{ /* likely */ }
1362	else
1363	{
1364	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1365	VMX_V_MSR_BITMAP_PAGES));
1366	break;
1367	}
1368
1369	/*
1370	* Allocate the I/O bitmaps (A and B).
1371	*/
1372	pCtx->hwvirt.vmx.pvIoBitmapR3 = SUPR3ContAlloc(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES,
1373	&pCtx->hwvirt.vmx.pvIoBitmapR0,
1374	&pCtx->hwvirt.vmx.HCPhysIoBitmap);
1375	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1376	{ /* likely */ }
1377	else
1378	{
1379	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1380	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1381	break;
1382	}
1383
1384	/*
1385	* Zero out all allocated pages (should compress well for saved-state).
1386	*/
1387	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1388	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1389	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVirtApicPage), 0, VMX_V_VIRT_APIC_SIZE);
1390	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmreadBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1391	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1392	memset(pCtx->hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1393	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1394	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1395	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvMsrBitmap), 0, VMX_V_MSR_BITMAP_SIZE);
1396	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap), 0, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1397	}
1398
1399	/* On any failure, cleanup. */
1400	if (RT_FAILURE(rc))
1401	cpumR3FreeVmxHwVirtState(pVM);
1402
1403	return rc;
1404	}
1405
1406
1407	/**
1408	* Resets per-VCPU VMX hardware virtualization state.
1409	*
1410	* @param pVCpu The cross context virtual CPU structure.
1411	*/
1412	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1413	{
1414	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1415	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1416	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
1417	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1418
1419	memset(pCtx->hwvirt.vmx.CTX_SUFF(pVmcs), 0, VMX_V_VMCS_SIZE);
1420	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1421	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1422	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1423	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1424	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1425	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1426	/* Don't reset diagnostics here. */
1427
1428	/* Stop any VMX-preemption timer. */
1429	CPUMStopGuestVmxPremptTimer(pVCpu);
1430
1431	/* Clear all nested-guest FFs. */
1432	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1433	}
1434
1435
1436	/**
1437	* Displays the host and guest VMX features.
1438	*
1439	* @param pVM The cross context VM structure.
1440	* @param pHlp The info helper functions.
1441	* @param pszArgs "terse", "default" or "verbose".
1442	*/
1443	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1444	{
1445	RT_NOREF(pszArgs);
1446	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1447	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1448	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1449	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1450	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1451	{
1452	#define VMXFEATDUMP(a_szDesc, a_Var) \
1453	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1454
1455	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1456	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1457	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1458	/* Basic. */
1459	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1460	/* Pin-based controls. */
1461	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1462	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1463	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1464	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1465	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1466	/* Processor-based controls. */
1467	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1468	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1469	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1470	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1471	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1472	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1473	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1474	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1475	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1476	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1477	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1478	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1479	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1480	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1481	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1482	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1483	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1484	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1485	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1486	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1487	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1488	/* Secondary processor-based controls. */
1489	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1490	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1491	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1492	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1493	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1494	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1495	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1496	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1497	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1498	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1499	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1500	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1501	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1502	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1503	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1504	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1505	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1506	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1507	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1508	/* VM-entry controls. */
1509	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1510	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1511	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1512	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1513	/* VM-exit controls. */
1514	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1515	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1516	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1517	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1518	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1519	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1520	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1521	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1522	/* Miscellaneous data. */
1523	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1524	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1525	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1526	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1527	#undef VMXFEATDUMP
1528	}
1529	else
1530	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1531	}
1532
1533
1534	/**
1535	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1536	* or NEM) is allowed.
1537	*
1538	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1539	* otherwise.
1540	* @param pVM The cross context VM structure.
1541	*/
1542	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1543	{
1544	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1545	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1546	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1547	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1548	return true;
1549	#else
1550	NOREF(pVM);
1551	#endif
1552	return false;
1553	}
1554
1555
1556	/**
1557	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1558	*
1559	* @param pVM The cross context VM structure.
1560	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1561	* and no hardware-assisted nested-guest execution is
1562	* possible for this VM.
1563	* @param pGuestFeatures The guest features to use (only VMX features are
1564	* accessed).
1565	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1566	*
1567	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1568	*/
1569	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1570	{
1571	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1572
1573	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1574	Assert(pGuestFeatures->fVmx);
1575
1576	/*
1577	* We don't support the following MSRs yet:
1578	* - True Pin-based VM-execution controls.
1579	* - True Processor-based VM-execution controls.
1580	* - True VM-entry VM-execution controls.
1581	* - True VM-exit VM-execution controls.
1582	*/
1583
1584	/* Feature control. */
1585	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1586
1587	/* Basic information. */
1588	{
1589	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1590	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1591	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1592	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1593	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1594	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1595	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1596	pGuestVmxMsrs->u64Basic = u64Basic;
1597	}
1598
1599	/* Pin-based VM-execution controls. */
1600	{
1601	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1602	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1603	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1604	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1605	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1606	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1607	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1608	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1609	fAllowed0, fAllowed1, fFeatures));
1610	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1611	}
1612
1613	/* Processor-based VM-execution controls. */
1614	{
1615	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1616	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1617	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1618	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1619	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1620	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1621	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1622	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1623	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1624	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1625	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1626	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1627	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1628	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1629	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1630	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1631	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1632	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1633	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1634	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1635	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1636	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1637	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1638	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1639	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1640	fAllowed1, fFeatures));
1641	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1642	}
1643
1644	/* Secondary processor-based VM-execution controls. */
1645	if (pGuestFeatures->fVmxSecondaryExecCtls)
1646	{
1647	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1648	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1649	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1650	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1651	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1652	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1653	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1654	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1655	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1656	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1657	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1658	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1659	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1660	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1661	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1662	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1663	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1664	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1665	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1666	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1667	uint32_t const fAllowed0 = 0;
1668	uint32_t const fAllowed1 = fFeatures;
1669	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1670	}
1671
1672	/* Tertiary processor-based VM-execution controls. */
1673	if (pGuestFeatures->fVmxTertiaryExecCtls)
1674	{
1675	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1676	}
1677
1678	/* VM-exit controls. */
1679	{
1680	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1681	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1682	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1683	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1684	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1685	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1686	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1687	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1688	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1689	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1690	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1691	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1692	fAllowed1, fFeatures));
1693	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1694	}
1695
1696	/* VM-entry controls. */
1697	{
1698	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1699	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1700	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1701	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1702	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1703	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1704	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1705	fAllowed1, fFeatures));
1706	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1707	}
1708
1709	/* Miscellaneous data. */
1710	{
1711	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1712
1713	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1714	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1715	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1716	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1717	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1718	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1719	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1720	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1721	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1722	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1723	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1724	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1725	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1726	}
1727
1728	/* CR0 Fixed-0. */
1729	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1730
1731	/* CR0 Fixed-1. */
1732	{
1733	/*
1734	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1735	* This is different from CR4 fixed-1 bits which are reported as per the
1736	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1737	*/
1738	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1739	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1740	}
1741
1742	/* CR4 Fixed-0. */
1743	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1744
1745	/* CR4 Fixed-1. */
1746	{
1747	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1748	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1749	}
1750
1751	/* VMCS Enumeration. */
1752	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1753
1754	/* VPID and EPT Capabilities. */
1755	if (pGuestFeatures->fVmxEpt)
1756	{
1757	/*
1758	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1759	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1760	* when INVVPID instruction is supported just to be more compatible with guest
1761	* hypervisors that may make assumptions by only looking at this MSR even though they
1762	* are technically supposed to refer to bit 37 of MSR_IA32_VMX_PROC_CTLS2 first.
1763	*
1764	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1765	* See Intel spec. 30.3 "VMX Instructions".
1766	*/
1767	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1768	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1769
1770	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_RWX_X_ONLY);
1771	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1772	uint8_t const fEptMemUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_UC);
1773	uint8_t const fEptMemWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_WB);
1774	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1775	uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G);
1776	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1777	uint8_t const fEptAccDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1778	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1779	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1780	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1781	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1782	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1783	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1784	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_RWX_X_ONLY, fExecOnly)
1785	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1786	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EMT_UC, fEptMemUc)
1787	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EMT_WB, fEptMemWb)
1788	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1789	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage)
1790	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1791	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY, fEptAccDirty)
1792	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT, 0)
1793	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1794	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1795	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1796	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1797	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1798	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1799	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1800	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1801	}
1802
1803	/* VM Functions. */
1804	if (pGuestFeatures->fVmxVmFunc)
1805	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1806	}
1807
1808
1809	/**
1810	* Checks whether the given guest CPU VMX features are compatible with the provided
1811	* base features.
1812	*
1813	* @returns @c true if compatible, @c false otherwise.
1814	* @param pVM The cross context VM structure.
1815	* @param pBase The base VMX CPU features.
1816	* @param pGst The guest VMX CPU features.
1817	*
1818	* @remarks Only VMX feature bits are examined.
1819	*/
1820	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1821	{
1822	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1823	return false;
1824
1825	/* Check first set of feature bits. */
1826	{
1827	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1828	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1829	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1830	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1831	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1832	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1833	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1834	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1835	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1836	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1837	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1838	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1839	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1840	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1841	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1842	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1843	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1844	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1845	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1846	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1847	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1848	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1849	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1850	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1851	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1852	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1853	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1854	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1855	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1856	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1857	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1858	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1859
1860	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1861	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1862	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1863	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1864	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1865	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1866	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1867	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1868	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1869	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1870	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1871	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1872	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1873	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1874	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1875	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1876	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1877	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1878	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1879	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1880	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1881	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1882	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1883	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1884	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1885	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1886	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1887	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1888	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1889	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1890	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1891	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1892
1893	if ((fBase \| fGst) != fBase)
1894	{
1895	uint64_t const fDiff = fBase ^ fGst;
1896	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1897	fBase, fGst, fDiff));
1898	return false;
1899	}
1900	}
1901
1902	/* Check second set of feature bits. */
1903	{
1904	uint64_t const fBase = ((uint64_t)pBase->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pBase->fVmxLoadIwKeyExit << 1);
1905	uint64_t const fGst = ((uint64_t)pGst->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pGst->fVmxLoadIwKeyExit << 1);
1906	if ((fBase \| fGst) != fBase)
1907	{
1908	uint64_t const fDiff = fBase ^ fGst;
1909	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1910	fBase, fGst, fDiff));
1911	return false;
1912	}
1913	}
1914
1915	return true;
1916	}
1917
1918
1919	/**
1920	* Initializes VMX guest features and MSRs.
1921	*
1922	* @param pVM The cross context VM structure.
1923	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1924	* and no hardware-assisted nested-guest execution is
1925	* possible for this VM.
1926	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1927	*/
1928	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1929	{
1930	Assert(pVM);
1931	Assert(pGuestVmxMsrs);
1932
1933	/*
1934	* While it would be nice to check this earlier while initializing fNestedVmxEpt
1935	* but we would not have enumearted host features then, so do it at least now.
1936	*/
1937	if ( !pVM->cpum.s.HostFeatures.fNoExecute
1938	&& pVM->cpum.s.fNestedVmxEpt)
1939	{
1940	LogRel(("CPUM: Warning! EPT not exposed to the guest since NX isn't available on the host.\n"));
1941	pVM->cpum.s.fNestedVmxEpt = false;
1942	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1943	}
1944
1945	/*
1946	* Initialize the set of VMX features we emulate.
1947	*
1948	* Note! Some bits might be reported as 1 always if they fall under the
1949	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1950	*/
1951	CPUMFEATURES EmuFeat;
1952	RT_ZERO(EmuFeat);
1953	EmuFeat.fVmx = 1;
1954	EmuFeat.fVmxInsOutInfo = 1;
1955	EmuFeat.fVmxExtIntExit = 1;
1956	EmuFeat.fVmxNmiExit = 1;
1957	EmuFeat.fVmxVirtNmi = 1;
1958	EmuFeat.fVmxPreemptTimer = 0; /* pVM->cpum.s.fNestedVmxPreemptTimer -- Currently disabled on purpose, see @bugref{9180#c108}. */
1959	EmuFeat.fVmxPostedInt = 0;
1960	EmuFeat.fVmxIntWindowExit = 1;
1961	EmuFeat.fVmxTscOffsetting = 1;
1962	EmuFeat.fVmxHltExit = 1;
1963	EmuFeat.fVmxInvlpgExit = 1;
1964	EmuFeat.fVmxMwaitExit = 1;
1965	EmuFeat.fVmxRdpmcExit = 1;
1966	EmuFeat.fVmxRdtscExit = 1;
1967	EmuFeat.fVmxCr3LoadExit = 1;
1968	EmuFeat.fVmxCr3StoreExit = 1;
1969	EmuFeat.fVmxTertiaryExecCtls = 0;
1970	EmuFeat.fVmxCr8LoadExit = 1;
1971	EmuFeat.fVmxCr8StoreExit = 1;
1972	EmuFeat.fVmxUseTprShadow = 1;
1973	EmuFeat.fVmxNmiWindowExit = 0;
1974	EmuFeat.fVmxMovDRxExit = 1;
1975	EmuFeat.fVmxUncondIoExit = 1;
1976	EmuFeat.fVmxUseIoBitmaps = 1;
1977	EmuFeat.fVmxMonitorTrapFlag = 0;
1978	EmuFeat.fVmxUseMsrBitmaps = 1;
1979	EmuFeat.fVmxMonitorExit = 1;
1980	EmuFeat.fVmxPauseExit = 1;
1981	EmuFeat.fVmxSecondaryExecCtls = 1;
1982	EmuFeat.fVmxVirtApicAccess = 1;
1983	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1984	EmuFeat.fVmxDescTableExit = 1;
1985	EmuFeat.fVmxRdtscp = 1;
1986	EmuFeat.fVmxVirtX2ApicMode = 0;
1987	EmuFeat.fVmxVpid = EmuFeat.fVmxEpt;
1988	EmuFeat.fVmxWbinvdExit = 1;
1989	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1990	EmuFeat.fVmxApicRegVirt = 0;
1991	EmuFeat.fVmxVirtIntDelivery = 0;
1992	EmuFeat.fVmxPauseLoopExit = 0;
1993	EmuFeat.fVmxRdrandExit = 0;
1994	EmuFeat.fVmxInvpcid = 1;
1995	EmuFeat.fVmxVmFunc = 0;
1996	EmuFeat.fVmxVmcsShadowing = 0;
1997	EmuFeat.fVmxRdseedExit = 0;
1998	EmuFeat.fVmxPml = 0;
1999	EmuFeat.fVmxEptXcptVe = 0;
2000	EmuFeat.fVmxXsavesXrstors = 0;
2001	EmuFeat.fVmxUseTscScaling = 0;
2002	EmuFeat.fVmxLoadIwKeyExit = 0;
2003	EmuFeat.fVmxEntryLoadDebugCtls = 1;
2004	EmuFeat.fVmxIa32eModeGuest = 1;
2005	EmuFeat.fVmxEntryLoadEferMsr = 1;
2006	EmuFeat.fVmxEntryLoadPatMsr = 0;
2007	EmuFeat.fVmxExitSaveDebugCtls = 1;
2008	EmuFeat.fVmxHostAddrSpaceSize = 1;
2009	EmuFeat.fVmxExitAckExtInt = 1;
2010	EmuFeat.fVmxExitSavePatMsr = 0;
2011	EmuFeat.fVmxExitLoadPatMsr = 0;
2012	EmuFeat.fVmxExitSaveEferMsr = 1;
2013	EmuFeat.fVmxExitLoadEferMsr = 1;
2014	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
2015	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
2016	EmuFeat.fVmxIntelPt = 0;
2017	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
2018	EmuFeat.fVmxEntryInjectSoftInt = 1;
2019
2020	/*
2021	* Merge guest features.
2022	*
2023	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
2024	* by the hardware, hence we merge our emulated features with the host features below.
2025	*/
2026	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
2027	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
2028	Assert(pBaseFeat->fVmx);
2029	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
2030	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
2031	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
2032	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
2033	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
2034	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
2035	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
2036	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
2037	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
2038	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
2039	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
2040	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
2041	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
2042	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
2043	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
2044	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
2045	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
2046	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
2047	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
2048	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
2049	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
2050	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
2051	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
2052	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
2053	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
2054	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
2055	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
2056	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
2057	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
2058	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
2059	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
2060	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
2061	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
2062	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
2063	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
2064	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
2065	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
2066	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
2067	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
2068	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
2069	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
2070	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
2071	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
2072	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
2073	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
2074	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
2075	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
2076	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
2077	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
2078	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
2079	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
2080	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
2081	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
2082	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
2083	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
2084	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
2085	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
2086	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
2087	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
2088	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
2089	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
2090	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
2091	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
2092	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
2093	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
2094
2095	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
2096	if ( pGuestFeat->fVmxPreemptTimer
2097	&& HMIsSubjectToVmxPreemptTimerErratum())
2098	{
2099	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
2100	pGuestFeat->fVmxPreemptTimer = 0;
2101	pGuestFeat->fVmxSavePreemptTimer = 0;
2102	}
2103
2104	/* Sanity checking. */
2105	if (!pGuestFeat->fVmxSecondaryExecCtls)
2106	{
2107	Assert(!pGuestFeat->fVmxVirtApicAccess);
2108	Assert(!pGuestFeat->fVmxEpt);
2109	Assert(!pGuestFeat->fVmxDescTableExit);
2110	Assert(!pGuestFeat->fVmxRdtscp);
2111	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
2112	Assert(!pGuestFeat->fVmxVpid);
2113	Assert(!pGuestFeat->fVmxWbinvdExit);
2114	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
2115	Assert(!pGuestFeat->fVmxApicRegVirt);
2116	Assert(!pGuestFeat->fVmxVirtIntDelivery);
2117	Assert(!pGuestFeat->fVmxPauseLoopExit);
2118	Assert(!pGuestFeat->fVmxRdrandExit);
2119	Assert(!pGuestFeat->fVmxInvpcid);
2120	Assert(!pGuestFeat->fVmxVmFunc);
2121	Assert(!pGuestFeat->fVmxVmcsShadowing);
2122	Assert(!pGuestFeat->fVmxRdseedExit);
2123	Assert(!pGuestFeat->fVmxPml);
2124	Assert(!pGuestFeat->fVmxEptXcptVe);
2125	Assert(!pGuestFeat->fVmxXsavesXrstors);
2126	Assert(!pGuestFeat->fVmxUseTscScaling);
2127	}
2128	else if (pGuestFeat->fVmxUnrestrictedGuest)
2129	{
2130	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2131	Assert(pGuestFeat->fVmxExitSaveEferLma);
2132	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
2133	Assert(pGuestFeat->fVmxEpt);
2134	}
2135
2136	if (!pGuestFeat->fVmxTertiaryExecCtls)
2137	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
2138
2139	/*
2140	* Finally initialize the VMX guest MSRs.
2141	*/
2142	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2143	}
2144
2145
2146	/**
2147	* Gets the host hardware-virtualization MSRs.
2148	*
2149	* @returns VBox status code.
2150	* @param pMsrs Where to store the MSRs.
2151	*/
2152	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2153	{
2154	Assert(pMsrs);
2155
2156	uint32_t fCaps = 0;
2157	int rc = SUPR3QueryVTCaps(&fCaps);
2158	if (RT_SUCCESS(rc))
2159	{
2160	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2161	{
2162	SUPHWVIRTMSRS HwvirtMsrs;
2163	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2164	if (RT_SUCCESS(rc))
2165	{
2166	if (fCaps & SUPVTCAPS_VT_X)
2167	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2168	else
2169	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2170	return VINF_SUCCESS;
2171	}
2172
2173	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2174	return rc;
2175	}
2176
2177	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2178	return VERR_INTERNAL_ERROR_5;
2179	}
2180	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2181	return VINF_SUCCESS;
2182	}
2183
2184
2185	/**
2186	* @callback_method_impl{FNTMTIMERINT,
2187	* Callback that fires when the nested VMX-preemption timer expired.}
2188	*/
2189	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2190	{
2191	RT_NOREF(pVM, hTimer);
2192	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2193	AssertPtr(pVCpu);
2194	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2195	}
2196
2197
2198	/**
2199	* Initializes the CPUM.
2200	*
2201	* @returns VBox status code.
2202	* @param pVM The cross context VM structure.
2203	*/
2204	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2205	{
2206	LogFlow(("CPUMR3Init\n"));
2207
2208	/*
2209	* Assert alignment, sizes and tables.
2210	*/
2211	AssertCompileMemberAlignment(VM, cpum.s, 32);
2212	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2213	AssertCompileSizeAlignment(CPUMCTX, 64);
2214	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2215	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2216	AssertCompileMemberAlignment(VM, cpum, 64);
2217	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2218	#ifdef VBOX_STRICT
2219	int rc2 = cpumR3MsrStrictInitChecks();
2220	AssertRCReturn(rc2, rc2);
2221	#endif
2222
2223	/*
2224	* Gather info about the host CPU.
2225	*/
2226	if (!ASMHasCpuId())
2227	{
2228	LogRel(("The CPU doesn't support CPUID!\n"));
2229	return VERR_UNSUPPORTED_CPU;
2230	}
2231
2232	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2233
2234	CPUMMSRS HostMsrs;
2235	RT_ZERO(HostMsrs);
2236	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2237	AssertLogRelRCReturn(rc, rc);
2238
2239	PCPUMCPUIDLEAF paLeaves;
2240	uint32_t cLeaves;
2241	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
2242	AssertLogRelRCReturn(rc, rc);
2243
2244	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
2245	RTMemFree(paLeaves);
2246	AssertLogRelRCReturn(rc, rc);
2247	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2248
2249	/*
2250	* Check that the CPU supports the minimum features we require.
2251	*/
2252	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2253	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2254	if (!pVM->cpum.s.HostFeatures.fMmx)
2255	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2256	if (!pVM->cpum.s.HostFeatures.fTsc)
2257	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2258
2259	/*
2260	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2261	*/
2262	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2263	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2264
2265	/*
2266	* Figure out which XSAVE/XRSTOR features are available on the host.
2267	*/
2268	uint64_t fXcr0Host = 0;
2269	uint64_t fXStateHostMask = 0;
2270	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2271	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2272	{
2273	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2274	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2275	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2276	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2277	}
2278	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2279	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2280	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2281
2282	/*
2283	* Allocate memory for the extended CPU state and initialize the host XSAVE/XRSTOR mask.
2284	*/
2285	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2286	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2287	AssertLogRelReturn(cbMaxXState >= sizeof(X86FXSTATE) && cbMaxXState <= _8K, VERR_CPUM_IPE_2);
2288
2289	uint8_t *pbXStates;
2290	rc = MMR3HyperAllocOnceNoRelEx(pVM, cbMaxXState * pVM->cCpus, PAGE_SIZE, MM_TAG_CPUM_CTX,
2291	MMHYPER_AONR_FLAGS_KERNEL_MAPPING, (void **)&pbXStates);
2292	AssertLogRelRCReturn(rc, rc);
2293
2294	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2295	{
2296	PVMCPU pVCpu = pVM->apCpusR3[i];
2297
2298	pVCpu->cpum.s.Host.pXStateR3 = (PX86XSAVEAREA)pbXStates;
2299	pVCpu->cpum.s.Host.pXStateR0 = MMHyperR3ToR0(pVM, pbXStates);
2300	pbXStates += cbMaxXState;
2301
2302	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2303
2304	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2305	}
2306
2307	/*
2308	* Register saved state data item.
2309	*/
2310	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2311	NULL, cpumR3LiveExec, NULL,
2312	NULL, cpumR3SaveExec, NULL,
2313	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2314	if (RT_FAILURE(rc))
2315	return rc;
2316
2317	/*
2318	* Register info handlers and registers with the debugger facility.
2319	*/
2320	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2321	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2322	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2323	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2324	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2325	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2326	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2327	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2328	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2329	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2330	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2331	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2332	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2333	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2334	&cpumR3InfoVmxFeatures);
2335
2336	rc = cpumR3DbgInit(pVM);
2337	if (RT_FAILURE(rc))
2338	return rc;
2339
2340	/*
2341	* Check if we need to workaround partial/leaky FPU handling.
2342	*/
2343	cpumR3CheckLeakyFpu(pVM);
2344
2345	/*
2346	* Initialize the Guest CPUID and MSR states.
2347	*/
2348	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2349	if (RT_FAILURE(rc))
2350	return rc;
2351
2352	/*
2353	* Allocate memory required by the guest hardware-virtualization structures.
2354	* This must be done after initializing CPUID/MSR features as we access the
2355	* the VMX/SVM guest features below.
2356	*
2357	* In the case of nested VT-x, we also need to create the per-VCPU
2358	* VMX preemption timers.
2359	*/
2360	if (pVM->cpum.s.GuestFeatures.fVmx)
2361	rc = cpumR3AllocVmxHwVirtState(pVM);
2362	else if (pVM->cpum.s.GuestFeatures.fSvm)
2363	rc = cpumR3AllocSvmHwVirtState(pVM);
2364	else
2365	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2366	if (RT_FAILURE(rc))
2367	return rc;
2368
2369	CPUMR3Reset(pVM);
2370	return VINF_SUCCESS;
2371	}
2372
2373
2374	/**
2375	* Applies relocations to data and code managed by this
2376	* component. This function will be called at init and
2377	* whenever the VMM need to relocate it self inside the GC.
2378	*
2379	* The CPUM will update the addresses used by the switcher.
2380	*
2381	* @param pVM The cross context VM structure.
2382	*/
2383	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2384	{
2385	RT_NOREF(pVM);
2386	}
2387
2388
2389	/**
2390	* Terminates the CPUM.
2391	*
2392	* Termination means cleaning up and freeing all resources,
2393	* the VM it self is at this point powered off or suspended.
2394	*
2395	* @returns VBox status code.
2396	* @param pVM The cross context VM structure.
2397	*/
2398	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2399	{
2400	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2401	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2402	{
2403	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2404	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2405	pVCpu->cpum.s.uMagic = 0;
2406	pvCpu->cpum.s.Guest.dr[5] = 0;
2407	}
2408	#endif
2409
2410	if (pVM->cpum.s.GuestFeatures.fVmx)
2411	{
2412	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2413	{
2414	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2415	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2416	{
2417	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2418	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2419	}
2420	}
2421
2422	cpumR3FreeVmxHwVirtState(pVM);
2423	}
2424	else if (pVM->cpum.s.GuestFeatures.fSvm)
2425	cpumR3FreeSvmHwVirtState(pVM);
2426	return VINF_SUCCESS;
2427	}
2428
2429
2430	/**
2431	* Resets a virtual CPU.
2432	*
2433	* Used by CPUMR3Reset and CPU hot plugging.
2434	*
2435	* @param pVM The cross context VM structure.
2436	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2437	* being reset. This may differ from the current EMT.
2438	*/
2439	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2440	{
2441	/** @todo anything different for VCPU > 0? */
2442	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2443
2444	/*
2445	* Initialize everything to ZERO first.
2446	*/
2447	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2448
2449	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2450
2451	pVCpu->cpum.s.fUseFlags = fUseFlags;
2452
2453	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2454	pCtx->eip = 0x0000fff0;
2455	pCtx->edx = 0x00000600; /* P6 processor */
2456	pCtx->eflags.Bits.u1Reserved0 = 1;
2457
2458	pCtx->cs.Sel = 0xf000;
2459	pCtx->cs.ValidSel = 0xf000;
2460	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2461	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2462	pCtx->cs.u32Limit = 0x0000ffff;
2463	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2464	pCtx->cs.Attr.n.u1Present = 1;
2465	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2466
2467	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2468	pCtx->ds.u32Limit = 0x0000ffff;
2469	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2470	pCtx->ds.Attr.n.u1Present = 1;
2471	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2472
2473	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2474	pCtx->es.u32Limit = 0x0000ffff;
2475	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2476	pCtx->es.Attr.n.u1Present = 1;
2477	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2478
2479	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2480	pCtx->fs.u32Limit = 0x0000ffff;
2481	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2482	pCtx->fs.Attr.n.u1Present = 1;
2483	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2484
2485	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2486	pCtx->gs.u32Limit = 0x0000ffff;
2487	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2488	pCtx->gs.Attr.n.u1Present = 1;
2489	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2490
2491	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2492	pCtx->ss.u32Limit = 0x0000ffff;
2493	pCtx->ss.Attr.n.u1Present = 1;
2494	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2495	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2496
2497	pCtx->idtr.cbIdt = 0xffff;
2498	pCtx->gdtr.cbGdt = 0xffff;
2499
2500	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2501	pCtx->ldtr.u32Limit = 0xffff;
2502	pCtx->ldtr.Attr.n.u1Present = 1;
2503	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2504
2505	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2506	pCtx->tr.u32Limit = 0xffff;
2507	pCtx->tr.Attr.n.u1Present = 1;
2508	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2509
2510	pCtx->dr[6] = X86_DR6_INIT_VAL;
2511	pCtx->dr[7] = X86_DR7_INIT_VAL;
2512
2513	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2514	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2515	pFpuCtx->FCW = 0x37f;
2516
2517	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2518	IA-32 Processor States Following Power-up, Reset, or INIT */
2519	pFpuCtx->MXCSR = 0x1F80;
2520	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2521
2522	pCtx->aXcr[0] = XSAVE_C_X87;
2523	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2524	{
2525	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2526	as we don't know what happened before. (Bother optimize later?) */
2527	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2528	}
2529
2530	/*
2531	* MSRs.
2532	*/
2533	/* Init PAT MSR */
2534	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2535
2536	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2537	* The Intel docs don't mention it. */
2538	Assert(!pCtx->msrEFER);
2539
2540	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2541	is supposed to be here, just trying provide useful/sensible values. */
2542	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2543	if (pRange)
2544	{
2545	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2546	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2547	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2548	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2549	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2550	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2551	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2552	}
2553
2554	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2555
2556	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2557	* called from each EMT while we're getting called by CPUMR3Reset()
2558	* iteratively on the same thread. Fix later. */
2559	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2560	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2561	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2562	#endif
2563
2564
2565	/* C-state control. Guesses. */
2566	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2567	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2568	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2569	* functionality. The default value must be different due to incompatible write mask.
2570	*/
2571	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2572	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2573	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2574	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2575
2576	/*
2577	* Hardware virtualization state.
2578	*/
2579	CPUMSetGuestGif(pCtx, true);
2580	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2581	if (pVM->cpum.s.GuestFeatures.fVmx)
2582	cpumR3ResetVmxHwVirtState(pVCpu);
2583	else if (pVM->cpum.s.GuestFeatures.fSvm)
2584	cpumR3ResetSvmHwVirtState(pVCpu);
2585	}
2586
2587
2588	/**
2589	* Resets the CPU.
2590	*
2591	* @returns VINF_SUCCESS.
2592	* @param pVM The cross context VM structure.
2593	*/
2594	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2595	{
2596	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2597	{
2598	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2599	CPUMR3ResetCpu(pVM, pVCpu);
2600
2601	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2602
2603	/* Magic marker for searching in crash dumps. */
2604	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2605	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2606	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2607	#endif
2608	}
2609	}
2610
2611
2612
2613
2614	/**
2615	* Pass 0 live exec callback.
2616	*
2617	* @returns VINF_SSM_DONT_CALL_AGAIN.
2618	* @param pVM The cross context VM structure.
2619	* @param pSSM The saved state handle.
2620	* @param uPass The pass (0).
2621	*/
2622	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2623	{
2624	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2625	cpumR3SaveCpuId(pVM, pSSM);
2626	return VINF_SSM_DONT_CALL_AGAIN;
2627	}
2628
2629
2630	/**
2631	* Execute state save operation.
2632	*
2633	* @returns VBox status code.
2634	* @param pVM The cross context VM structure.
2635	* @param pSSM SSM operation handle.
2636	*/
2637	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2638	{
2639	/*
2640	* Save.
2641	*/
2642	SSMR3PutU32(pSSM, pVM->cCpus);
2643	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2644	CPUMCTX DummyHyperCtx;
2645	RT_ZERO(DummyHyperCtx);
2646	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2647	{
2648	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2649
2650	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2651
2652	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2653	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2654	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2655	if (pGstCtx->fXStateMask != 0)
2656	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2657	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2658	{
2659	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2660	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2661	}
2662	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2663	{
2664	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2665	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2666	}
2667	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2668	{
2669	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2670	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2671	}
2672	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2673	{
2674	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2675	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2676	}
2677	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2678	{
2679	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2680	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2681	}
2682	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2683	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2684	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2685	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2686	if (pVM->cpum.s.GuestFeatures.fSvm)
2687	{
2688	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2689	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2690	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2691	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2692	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2693	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2694	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2695	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2696	g_aSvmHwvirtHostState, NULL /* pvUser */);
2697	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2698	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2699	SSMR3PutMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2700	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2701	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2702	}
2703	if (pVM->cpum.s.GuestFeatures.fVmx)
2704	{
2705	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2706	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2707	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2708	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2709	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2710	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2711	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2712	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2713	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2714	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2715	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2716	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2717	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2718	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2719	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2720	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2721	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2722	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2723	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2724	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2725	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2726	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2727	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2728	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2729	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2730	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2731	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2732	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2733	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2734	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2735	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2736	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2737	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2738	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2739	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2740	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2741	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2742	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2743	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2744	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2745	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2746	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2747	}
2748	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2749	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2750	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2751	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2752	}
2753
2754	cpumR3SaveCpuId(pVM, pSSM);
2755	return VINF_SUCCESS;
2756	}
2757
2758
2759	/**
2760	* @callback_method_impl{FNSSMINTLOADPREP}
2761	*/
2762	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2763	{
2764	NOREF(pSSM);
2765	pVM->cpum.s.fPendingRestore = true;
2766	return VINF_SUCCESS;
2767	}
2768
2769
2770	/**
2771	* @callback_method_impl{FNSSMINTLOADEXEC}
2772	*/
2773	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2774	{
2775	int rc; /* Only for AssertRCReturn use. */
2776
2777	/*
2778	* Validate version.
2779	*/
2780	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2781	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2782	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2783	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2784	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2785	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2786	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2787	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2788	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2789	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2790	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2791	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2792	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2793	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2794	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2795	{
2796	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2797	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2798	}
2799
2800	if (uPass == SSM_PASS_FINAL)
2801	{
2802	/*
2803	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2804	* really old SSM file versions.)
2805	*/
2806	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2807	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2808	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2809	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2810
2811	/*
2812	* Figure x86 and ctx field definitions to use for older states.
2813	*/
2814	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2815	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2816	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2817	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2818	{
2819	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2820	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2821	}
2822	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2823	{
2824	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2825	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2826	}
2827
2828	/*
2829	* The hyper state used to preceed the CPU count. Starting with
2830	* XSAVE it was moved down till after we've got the count.
2831	*/
2832	CPUMCTX HyperCtxIgnored;
2833	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2834	{
2835	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2836	{
2837	X86FXSTATE Ign;
2838	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2839	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2840	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2841	}
2842	}
2843
2844	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2845	{
2846	uint32_t cCpus;
2847	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2848	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2849	VERR_SSM_UNEXPECTED_DATA);
2850	}
2851	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2852	\|\| pVM->cCpus == 1,
2853	("cCpus=%u\n", pVM->cCpus),
2854	VERR_SSM_UNEXPECTED_DATA);
2855
2856	uint32_t cbMsrs = 0;
2857	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2858	{
2859	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2860	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2861	VERR_SSM_UNEXPECTED_DATA);
2862	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2863	VERR_SSM_UNEXPECTED_DATA);
2864	}
2865
2866	/*
2867	* Do the per-CPU restoring.
2868	*/
2869	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2870	{
2871	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2872	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2873
2874	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2875	{
2876	/*
2877	* The XSAVE saved state layout moved the hyper state down here.
2878	*/
2879	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2880	AssertRCReturn(rc, rc);
2881
2882	/*
2883	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2884	*/
2885	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2886	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2887	AssertRCReturn(rc, rc);
2888
2889	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2890	if (pGstCtx->fXStateMask != 0)
2891	{
2892	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2893	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2894	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2895	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2896	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2897	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2898	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2899	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2900	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2901	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2902	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2903	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2904	}
2905
2906	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2907	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2908	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2909	{
2910	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2911	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2912	VERR_CPUM_INVALID_XCR0);
2913	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2914	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2915	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2916	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2917	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2918	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2919	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2920	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2921	}
2922
2923	/* Check that the XCR1 is zero, as we don't implement it yet. */
2924	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2925
2926	/*
2927	* Restore the individual extended state components we support.
2928	*/
2929	if (pGstCtx->fXStateMask != 0)
2930	{
2931	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2932	0, g_aCpumXSaveHdrFields, NULL);
2933	AssertRCReturn(rc, rc);
2934	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2935	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2936	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2937	VERR_CPUM_INVALID_XSAVE_HDR);
2938	}
2939	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2940	{
2941	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2942	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2943	}
2944	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2945	{
2946	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2947	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2948	}
2949	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2950	{
2951	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2952	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2953	}
2954	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2955	{
2956	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2957	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2958	}
2959	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2960	{
2961	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2962	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2963	}
2964	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2965	{
2966	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2967	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2968	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2969	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2970	}
2971	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2972	{
2973	if (pVM->cpum.s.GuestFeatures.fSvm)
2974	{
2975	Assert(pGstCtx->hwvirt.svm.CTX_SUFF(pVmcb));
2976	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2977	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2978	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2979	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2980	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2981	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2982	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2983	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2984	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pVmcbR3, SVM_VMCB_PAGES << X86_PAGE_4K_SHIFT);
2985	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvMsrBitmapR3, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
2986	SSMR3GetMem(pSSM, pGstCtx->hwvirt.svm.pvIoBitmapR3, SVM_IOPM_PAGES << X86_PAGE_4K_SHIFT);
2987	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2988	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2989	}
2990	}
2991	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2992	{
2993	if (pVM->cpum.s.GuestFeatures.fVmx)
2994	{
2995	Assert(pGstCtx->hwvirt.vmx.CTX_SUFF(pVmcs));
2996	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2997	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2998	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2999	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
3000	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
3001	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
3002	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
3003	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
3004	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
3005	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
3006	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
3007	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
3008	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
3009	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
3010	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
3011	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
3012	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
3013	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
3014	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
3015	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
3016	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
3017	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
3018	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
3019	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
3020	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
3021	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
3022	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
3023	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
3024	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
3025	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
3026	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
3027	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
3028	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
3029	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
3030	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
3031	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
3032	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
3033	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
3034	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
3035	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
3036	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
3037	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
3038	}
3039	}
3040	}
3041	else
3042	{
3043	/*
3044	* Pre XSAVE saved state.
3045	*/
3046	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
3047	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
3048	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
3049	}
3050
3051	/*
3052	* Restore a couple of flags and the MSRs.
3053	*/
3054	uint32_t fIgnoredUsedFlags = 0;
3055	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
3056	AssertRCReturn(rc, rc);
3057	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
3058
3059	rc = VINF_SUCCESS;
3060	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
3061	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
3062	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
3063	{
3064	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
3065	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
3066	}
3067	AssertRCReturn(rc, rc);
3068
3069	/* REM and other may have cleared must-be-one fields in DR6 and
3070	DR7, fix these. */
3071	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
3072	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
3073	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
3074	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
3075	}
3076
3077	/* Older states does not have the internal selector register flags
3078	and valid selector value. Supply those. */
3079	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3080	{
3081	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3082	{
3083	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3084	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
3085	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3086	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
3087	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
3088	if (fValid)
3089	{
3090	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3091	{
3092	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
3093	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
3094	}
3095
3096	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3097	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3098	}
3099	else
3100	{
3101	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3102	{
3103	paSelReg[iSelReg].fFlags = 0;
3104	paSelReg[iSelReg].ValidSel = 0;
3105	}
3106
3107	/* This might not be 104% correct, but I think it's close
3108	enough for all practical purposes... (REM always loaded
3109	LDTR registers.) */
3110	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3111	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3112	}
3113	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
3114	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
3115	}
3116	}
3117
3118	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
3119	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3120	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3121	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3122	{
3123	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3124	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3125	}
3126
3127	/*
3128	* A quick sanity check.
3129	*/
3130	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3131	{
3132	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3133	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3134	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3135	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3136	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3137	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3138	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3139	}
3140	}
3141
3142	pVM->cpum.s.fPendingRestore = false;
3143
3144	/*
3145	* Guest CPUIDs (and VMX MSR features).
3146	*/
3147	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3148	{
3149	CPUMMSRS GuestMsrs;
3150	RT_ZERO(GuestMsrs);
3151
3152	CPUMFEATURES BaseFeatures;
3153	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3154	if (fVmxGstFeat)
3155	{
3156	/*
3157	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3158	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3159	* here so we can compare them for compatibility after exploding guest features.
3160	*/
3161	BaseFeatures = pVM->cpum.s.GuestFeatures;
3162
3163	/* Use the VMX MSR features from the saved state while exploding guest features. */
3164	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3165	}
3166
3167	/* Load CPUID and explode guest features. */
3168	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3169	if (fVmxGstFeat)
3170	{
3171	/*
3172	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3173	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3174	* VMX features presented to the guest.
3175	*/
3176	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3177	if (!fIsCompat)
3178	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3179	}
3180	return rc;
3181	}
3182	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3183	}
3184
3185
3186	/**
3187	* @callback_method_impl{FNSSMINTLOADDONE}
3188	*/
3189	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3190	{
3191	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3192	return VINF_SUCCESS;
3193
3194	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3195	if (pVM->cpum.s.fPendingRestore)
3196	{
3197	LogRel(("CPUM: Missing state!\n"));
3198	return VERR_INTERNAL_ERROR_2;
3199	}
3200
3201	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3202	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3203	{
3204	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3205
3206	/* Notify PGM of the NXE states in case they've changed. */
3207	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3208
3209	/* During init. this is done in CPUMR3InitCompleted(). */
3210	if (fSupportsLongMode)
3211	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3212
3213	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3214	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3215	}
3216	return VINF_SUCCESS;
3217	}
3218
3219
3220	/**
3221	* Checks if the CPUM state restore is still pending.
3222	*
3223	* @returns true / false.
3224	* @param pVM The cross context VM structure.
3225	*/
3226	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3227	{
3228	return pVM->cpum.s.fPendingRestore;
3229	}
3230
3231
3232	/**
3233	* Formats the EFLAGS value into mnemonics.
3234	*
3235	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3236	* @param efl The EFLAGS value.
3237	*/
3238	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3239	{
3240	/*
3241	* Format the flags.
3242	*/
3243	static const struct
3244	{
3245	const char pszSet; const char pszClear; uint32_t fFlag;
3246	} s_aFlags[] =
3247	{
3248	{ "vip",NULL, X86_EFL_VIP },
3249	{ "vif",NULL, X86_EFL_VIF },
3250	{ "ac", NULL, X86_EFL_AC },
3251	{ "vm", NULL, X86_EFL_VM },
3252	{ "rf", NULL, X86_EFL_RF },
3253	{ "nt", NULL, X86_EFL_NT },
3254	{ "ov", "nv", X86_EFL_OF },
3255	{ "dn", "up", X86_EFL_DF },
3256	{ "ei", "di", X86_EFL_IF },
3257	{ "tf", NULL, X86_EFL_TF },
3258	{ "nt", "pl", X86_EFL_SF },
3259	{ "nz", "zr", X86_EFL_ZF },
3260	{ "ac", "na", X86_EFL_AF },
3261	{ "po", "pe", X86_EFL_PF },
3262	{ "cy", "nc", X86_EFL_CF },
3263	};
3264	char *psz = pszEFlags;
3265	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3266	{
3267	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3268	if (pszAdd)
3269	{
3270	strcpy(psz, pszAdd);
3271	psz += strlen(pszAdd);
3272	*psz++ = ' ';
3273	}
3274	}
3275	psz[-1] = '\0';
3276	}
3277
3278
3279	/**
3280	* Formats a full register dump.
3281	*
3282	* @param pVM The cross context VM structure.
3283	* @param pCtx The context to format.
3284	* @param pCtxCore The context core to format.
3285	* @param pHlp Output functions.
3286	* @param enmType The dump type.
3287	* @param pszPrefix Register name prefix.
3288	*/
3289	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3290	const char *pszPrefix)
3291	{
3292	NOREF(pVM);
3293
3294	/*
3295	* Format the EFLAGS.
3296	*/
3297	uint32_t efl = pCtxCore->eflags.u32;
3298	char szEFlags[80];
3299	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3300
3301	/*
3302	* Format the registers.
3303	*/
3304	switch (enmType)
3305	{
3306	case CPUMDUMPTYPE_TERSE:
3307	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3308	pHlp->pfnPrintf(pHlp,
3309	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3310	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3311	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3312	"%sr14=%016RX64 %sr15=%016RX64\n"
3313	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3314	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3315	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3316	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3317	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3318	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3319	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3320	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3321	else
3322	pHlp->pfnPrintf(pHlp,
3323	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3324	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3325	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3326	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3327	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3328	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3329	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3330	break;
3331
3332	case CPUMDUMPTYPE_DEFAULT:
3333	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3334	pHlp->pfnPrintf(pHlp,
3335	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3336	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3337	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3338	"%sr14=%016RX64 %sr15=%016RX64\n"
3339	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3340	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3341	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3342	,
3343	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3344	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3345	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3346	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3347	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3348	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3349	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3350	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3351	else
3352	pHlp->pfnPrintf(pHlp,
3353	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3354	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3355	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3356	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3357	,
3358	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3359	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3360	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3361	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3362	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3363	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3364	break;
3365
3366	case CPUMDUMPTYPE_VERBOSE:
3367	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3368	pHlp->pfnPrintf(pHlp,
3369	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3370	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3371	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3372	"%sr14=%016RX64 %sr15=%016RX64\n"
3373	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3374	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3375	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3376	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3377	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3378	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3379	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3380	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3381	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3382	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3383	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3384	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3385	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3386	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3387	,
3388	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3389	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3390	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3391	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3392	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3393	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3394	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3395	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3396	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3397	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3398	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3399	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3400	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3401	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3402	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3403	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3404	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3405	else
3406	pHlp->pfnPrintf(pHlp,
3407	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3408	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3409	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3410	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3411	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3412	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3413	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3414	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3415	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3416	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3417	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3418	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3419	,
3420	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3421	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3422	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3423	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3424	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3425	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3426	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3427	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3428	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3429	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3430	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3431	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3432
3433	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3434	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3435	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3436	{
3437	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3438	pHlp->pfnPrintf(pHlp,
3439	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3440	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3441	,
3442	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3443	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3444	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3445	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3446	);
3447	/*
3448	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3449	* not (FP)R0-7 as Intel SDM suggests.
3450	*/
3451	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3452	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3453	{
3454	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3455	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3456	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3457	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3458	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3459	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3460	iExponent -= 16383; /* subtract bias */
3461	/** @todo This isn't entirenly correct and needs more work! */
3462	pHlp->pfnPrintf(pHlp,
3463	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3464	pszPrefix, iST, pszPrefix, iFPR,
3465	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3466	uTag, chSign, iInteger, u64Fraction, iExponent);
3467	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3468	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3469	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3470	else
3471	pHlp->pfnPrintf(pHlp, "\n");
3472	}
3473
3474	/* XMM/YMM/ZMM registers. */
3475	if (pCtx->fXStateMask & XSAVE_C_YMM)
3476	{
3477	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3478	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3479	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3480	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3481	pszPrefix, i, i < 10 ? " " : "",
3482	pYmmHiCtx->aYmmHi[i].au32[3],
3483	pYmmHiCtx->aYmmHi[i].au32[2],
3484	pYmmHiCtx->aYmmHi[i].au32[1],
3485	pYmmHiCtx->aYmmHi[i].au32[0],
3486	pFpuCtx->aXMM[i].au32[3],
3487	pFpuCtx->aXMM[i].au32[2],
3488	pFpuCtx->aXMM[i].au32[1],
3489	pFpuCtx->aXMM[i].au32[0]);
3490	else
3491	{
3492	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3493	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3494	pHlp->pfnPrintf(pHlp,
3495	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3496	pszPrefix, i, i < 10 ? " " : "",
3497	pZmmHi256->aHi256Regs[i].au32[7],
3498	pZmmHi256->aHi256Regs[i].au32[6],
3499	pZmmHi256->aHi256Regs[i].au32[5],
3500	pZmmHi256->aHi256Regs[i].au32[4],
3501	pZmmHi256->aHi256Regs[i].au32[3],
3502	pZmmHi256->aHi256Regs[i].au32[2],
3503	pZmmHi256->aHi256Regs[i].au32[1],
3504	pZmmHi256->aHi256Regs[i].au32[0],
3505	pYmmHiCtx->aYmmHi[i].au32[3],
3506	pYmmHiCtx->aYmmHi[i].au32[2],
3507	pYmmHiCtx->aYmmHi[i].au32[1],
3508	pYmmHiCtx->aYmmHi[i].au32[0],
3509	pFpuCtx->aXMM[i].au32[3],
3510	pFpuCtx->aXMM[i].au32[2],
3511	pFpuCtx->aXMM[i].au32[1],
3512	pFpuCtx->aXMM[i].au32[0]);
3513
3514	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3515	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3516	pHlp->pfnPrintf(pHlp,
3517	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3518	pszPrefix, i + 16,
3519	pZmm16Hi->aRegs[i].au32[15],
3520	pZmm16Hi->aRegs[i].au32[14],
3521	pZmm16Hi->aRegs[i].au32[13],
3522	pZmm16Hi->aRegs[i].au32[12],
3523	pZmm16Hi->aRegs[i].au32[11],
3524	pZmm16Hi->aRegs[i].au32[10],
3525	pZmm16Hi->aRegs[i].au32[9],
3526	pZmm16Hi->aRegs[i].au32[8],
3527	pZmm16Hi->aRegs[i].au32[7],
3528	pZmm16Hi->aRegs[i].au32[6],
3529	pZmm16Hi->aRegs[i].au32[5],
3530	pZmm16Hi->aRegs[i].au32[4],
3531	pZmm16Hi->aRegs[i].au32[3],
3532	pZmm16Hi->aRegs[i].au32[2],
3533	pZmm16Hi->aRegs[i].au32[1],
3534	pZmm16Hi->aRegs[i].au32[0]);
3535	}
3536	}
3537	else
3538	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3539	pHlp->pfnPrintf(pHlp,
3540	i & 1
3541	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3542	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3543	pszPrefix, i, i < 10 ? " " : "",
3544	pFpuCtx->aXMM[i].au32[3],
3545	pFpuCtx->aXMM[i].au32[2],
3546	pFpuCtx->aXMM[i].au32[1],
3547	pFpuCtx->aXMM[i].au32[0]);
3548
3549	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3550	{
3551	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3552	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3553	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3554	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3555	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3556	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3557	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3558	}
3559
3560	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3561	{
3562	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3563	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3564	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3565	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3566	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3567	}
3568
3569	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3570	{
3571	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3572	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3573	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3574	}
3575
3576	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3577	if (pFpuCtx->au32RsrvdRest[i])
3578	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3579	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3580	}
3581
3582	pHlp->pfnPrintf(pHlp,
3583	"%sEFER =%016RX64\n"
3584	"%sPAT =%016RX64\n"
3585	"%sSTAR =%016RX64\n"
3586	"%sCSTAR =%016RX64\n"
3587	"%sLSTAR =%016RX64\n"
3588	"%sSFMASK =%016RX64\n"
3589	"%sKERNELGSBASE =%016RX64\n",
3590	pszPrefix, pCtx->msrEFER,
3591	pszPrefix, pCtx->msrPAT,
3592	pszPrefix, pCtx->msrSTAR,
3593	pszPrefix, pCtx->msrCSTAR,
3594	pszPrefix, pCtx->msrLSTAR,
3595	pszPrefix, pCtx->msrSFMASK,
3596	pszPrefix, pCtx->msrKERNELGSBASE);
3597
3598	if (CPUMIsGuestInPAEModeEx(pCtx))
3599	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3600	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3601	break;
3602	}
3603	}
3604
3605
3606	/**
3607	* Display all cpu states and any other cpum info.
3608	*
3609	* @param pVM The cross context VM structure.
3610	* @param pHlp The info helper functions.
3611	* @param pszArgs Arguments, ignored.
3612	*/
3613	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3614	{
3615	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3616	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3617	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3618	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3619	cpumR3InfoHost(pVM, pHlp, pszArgs);
3620	}
3621
3622
3623	/**
3624	* Parses the info argument.
3625	*
3626	* The argument starts with 'verbose', 'terse' or 'default' and then
3627	* continues with the comment string.
3628	*
3629	* @param pszArgs The pointer to the argument string.
3630	* @param penmType Where to store the dump type request.
3631	* @param ppszComment Where to store the pointer to the comment string.
3632	*/
3633	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3634	{
3635	if (!pszArgs)
3636	{
3637	*penmType = CPUMDUMPTYPE_DEFAULT;
3638	*ppszComment = "";
3639	}
3640	else
3641	{
3642	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3643	{
3644	pszArgs += 7;
3645	*penmType = CPUMDUMPTYPE_VERBOSE;
3646	}
3647	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3648	{
3649	pszArgs += 5;
3650	*penmType = CPUMDUMPTYPE_TERSE;
3651	}
3652	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3653	{
3654	pszArgs += 7;
3655	*penmType = CPUMDUMPTYPE_DEFAULT;
3656	}
3657	else
3658	*penmType = CPUMDUMPTYPE_DEFAULT;
3659	*ppszComment = RTStrStripL(pszArgs);
3660	}
3661	}
3662
3663
3664	/**
3665	* Display the guest cpu state.
3666	*
3667	* @param pVM The cross context VM structure.
3668	* @param pHlp The info helper functions.
3669	* @param pszArgs Arguments.
3670	*/
3671	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3672	{
3673	CPUMDUMPTYPE enmType;
3674	const char *pszComment;
3675	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3676
3677	PVMCPU pVCpu = VMMGetCpu(pVM);
3678	if (!pVCpu)
3679	pVCpu = pVM->apCpusR3[0];
3680
3681	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3682
3683	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3684	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3685	}
3686
3687
3688	/**
3689	* Displays an SVM VMCB control area.
3690	*
3691	* @param pHlp The info helper functions.
3692	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3693	* @param pszPrefix Caller specified string prefix.
3694	*/
3695	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3696	{
3697	AssertReturnVoid(pHlp);
3698	AssertReturnVoid(pVmcbCtrl);
3699
3700	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3701	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3702	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3703	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3704	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3705	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3706	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3707	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3708	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3709	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3710	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3711	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3712	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3713	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3714	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3715	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3716	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3717	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3718	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3719	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3720	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3721	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3722	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3723	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3724	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3725	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3726	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3727	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3728	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3729	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3730	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3731	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3732	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3733	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3734	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3735	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3736	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3737	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3738	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3739	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3740	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3741	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3742	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3743	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3744	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3745	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3746	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3747	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3748	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3749	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3750	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3751	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3752	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3753	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3754	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3755	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3756	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3757	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3758	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3759	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3760	}
3761
3762
3763	/**
3764	* Helper for dumping the SVM VMCB selector registers.
3765	*
3766	* @param pHlp The info helper functions.
3767	* @param pSel Pointer to the SVM selector register.
3768	* @param pszName Name of the selector.
3769	* @param pszPrefix Caller specified string prefix.
3770	*/
3771	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3772	{
3773	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3774	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3775	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3776	}
3777
3778
3779	/**
3780	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3781	*
3782	* @param pHlp The info helper functions.
3783	* @param pXdtr Pointer to the descriptor table register.
3784	* @param pszName Name of the descriptor table register.
3785	* @param pszPrefix Caller specified string prefix.
3786	*/
3787	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3788	{
3789	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3790	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3791	}
3792
3793
3794	/**
3795	* Displays an SVM VMCB state-save area.
3796	*
3797	* @param pHlp The info helper functions.
3798	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3799	* @param pszPrefix Caller specified string prefix.
3800	*/
3801	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3802	{
3803	AssertReturnVoid(pHlp);
3804	AssertReturnVoid(pVmcbStateSave);
3805
3806	char szEFlags[80];
3807	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3808
3809	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3810	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3811	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3812	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3813	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3814	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3815	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3816	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3817	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3818	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3819	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3820	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3821	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3822	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3823	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3824	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3825	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3826	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3827	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3828	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3829	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3830	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3831	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3832	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3833	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3834	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3835	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3836	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3837	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3838	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3839	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3840	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3841	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3842	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3843	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3844	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3845	}
3846
3847
3848	/**
3849	* Displays a virtual-VMCS.
3850	*
3851	* @param pVCpu The cross context virtual CPU structure.
3852	* @param pHlp The info helper functions.
3853	* @param pVmcs Pointer to a virtual VMCS.
3854	* @param pszPrefix Caller specified string prefix.
3855	*/
3856	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3857	{
3858	AssertReturnVoid(pHlp);
3859	AssertReturnVoid(pVmcs);
3860
3861	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3862	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3863	do { \
3864	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3865	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3866	} while (0)
3867
3868	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3869	do { \
3870	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3871	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3872	} while (0)
3873
3874	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3875	do { \
3876	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3877	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3878	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3879	} while (0)
3880
3881	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3882	do { \
3883	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3884	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3885	} while (0)
3886
3887	/* Header. */
3888	{
3889	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3890	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3891	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3892	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3893	}
3894
3895	/* Control fields. */
3896	{
3897	/* 16-bit. */
3898	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3899	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3900	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3901	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3902
3903	/* 32-bit. */
3904	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3905	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3906	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3907	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3908	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3909	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3910	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3911	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3912	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3913	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3914	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3915	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3916	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3917	{
3918	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3919	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3920	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3921	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3922	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3923	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3924	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3925	}
3926	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3927	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3928	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3929	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3930	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3931
3932	/* 64-bit. */
3933	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3934	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3935	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3936	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3937	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3938	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3939	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3940	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3941	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3942	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3943	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3944	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3945	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3946	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3947	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3948	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3949	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3950	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3951	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3952	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3953	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3954	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3955	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3956	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3957	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3958	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3959	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3960	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3961
3962	/* Natural width. */
3963	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3964	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3965	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3966	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3967	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3968	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3969	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3970	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3971	}
3972
3973	/* Guest state. */
3974	{
3975	char szEFlags[80];
3976	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3977	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3978
3979	/* 16-bit. */
3980	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3981	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3982	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3983	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3984	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3985	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3986	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3987	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3988	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3989	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3990	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3991	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3992
3993	/* 32-bit. */
3994	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3995	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3996	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3997	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3998	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3999
4000	/* 64-bit. */
4001	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
4002	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
4003	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
4004	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
4005	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
4006	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
4007	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
4008	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
4009	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
4010	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
4011	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
4012	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
4013
4014	/* Natural width. */
4015	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
4016	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
4017	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
4018	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
4019	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
4020	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
4021	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
4022	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
4023	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
4024	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
4025	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
4026	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
4027	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
4028	}
4029
4030	/* Host state. */
4031	{
4032	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
4033
4034	/* 16-bit. */
4035	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
4036	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
4037	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
4038	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
4039	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
4040	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
4041	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
4042	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
4043	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
4044
4045	/* 32-bit. */
4046	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
4047
4048	/* 64-bit. */
4049	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
4050	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
4051	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
4052	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
4053
4054	/* Natural width. */
4055	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
4056	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
4057	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
4058	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
4059	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
4060	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
4061	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
4062	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
4063	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
4064	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
4065
4066	}
4067
4068	/* Read-only fields. */
4069	{
4070	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
4071
4072	/* 16-bit (none currently). */
4073
4074	/* 32-bit. */
4075	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
4076	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
4077	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
4078	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
4079	{
4080	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
4081	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
4082	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
4083	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
4084	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
4085	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4086	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4087	}
4088	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
4089	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
4090	{
4091	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
4092	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
4093	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
4094	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
4095	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
4096	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
4097	}
4098	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
4099	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
4100	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
4101
4102	/* 64-bit. */
4103	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
4104
4105	/* Natural width. */
4106	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
4107	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
4108	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
4109	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
4110	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
4111	}
4112
4113	#ifdef DEBUG_ramshankar
4114	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4115	{
4116	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
4117	Assert(pvPage);
4118	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4119	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
4120	if (RT_SUCCESS(rc))
4121	{
4122	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
4123	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4124	pHlp->pfnPrintf(pHlp, "\n");
4125	}
4126	RTMemTmpFree(pvPage);
4127	}
4128	#else
4129	NOREF(pVCpu);
4130	#endif
4131
4132	#undef CPUMVMX_DUMP_HOST_XDTR
4133	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4134	#undef CPUMVMX_DUMP_GUEST_SEGREG
4135	#undef CPUMVMX_DUMP_GUEST_XDTR
4136	}
4137
4138
4139	/**
4140	* Display the guest's hardware-virtualization cpu state.
4141	*
4142	* @param pVM The cross context VM structure.
4143	* @param pHlp The info helper functions.
4144	* @param pszArgs Arguments, ignored.
4145	*/
4146	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4147	{
4148	RT_NOREF(pszArgs);
4149
4150	PVMCPU pVCpu = VMMGetCpu(pVM);
4151	if (!pVCpu)
4152	pVCpu = pVM->apCpusR3[0];
4153
4154	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4155	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4156	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4157
4158	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4159	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
4160	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4161
4162	if (fSvm)
4163	{
4164	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4165	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4166
4167	char szEFlags[80];
4168	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4169	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4170	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4171	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4172	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.pVmcbR3->ctrl, " " /* pszPrefix */);
4173	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4174	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.pVmcbR3->guest, " " /* pszPrefix */);
4175	pHlp->pfnPrintf(pHlp, " HostState:\n");
4176	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4177	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4178	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4179	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4180	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4181	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4182	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4183	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4184	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4185	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4186	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4187	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4188	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4189	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4190	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4191	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4192	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4193	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4194	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4195	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4196	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4197	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4198	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4199	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4200	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4201	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4202	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4203	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR3 = %p\n", pCtx->hwvirt.svm.pvMsrBitmapR3);
4204	pHlp->pfnPrintf(pHlp, " pvMsrBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvMsrBitmapR0);
4205	pHlp->pfnPrintf(pHlp, " pvIoBitmapR3 = %p\n", pCtx->hwvirt.svm.pvIoBitmapR3);
4206	pHlp->pfnPrintf(pHlp, " pvIoBitmapR0 = %RKv\n", pCtx->hwvirt.svm.pvIoBitmapR0);
4207	}
4208	else if (fVmx)
4209	{
4210	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4211	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4212	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4213	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4214	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4215	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4216	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4217	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4218	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4219	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4220	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4221	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4222	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4223	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4224	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4225	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4226	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4227	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4228	cpumR3InfoVmxVmcs(pVCpu, pHlp, pCtx->hwvirt.vmx.pVmcsR3, " " /* pszPrefix */);
4229	}
4230	else
4231	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4232
4233	#undef CPUMHWVIRTDUMP_NONE
4234	#undef CPUMHWVIRTDUMP_COMMON
4235	#undef CPUMHWVIRTDUMP_SVM
4236	#undef CPUMHWVIRTDUMP_VMX
4237	#undef CPUMHWVIRTDUMP_LAST
4238	#undef CPUMHWVIRTDUMP_ALL
4239	}
4240
4241	/**
4242	* Display the current guest instruction
4243	*
4244	* @param pVM The cross context VM structure.
4245	* @param pHlp The info helper functions.
4246	* @param pszArgs Arguments, ignored.
4247	*/
4248	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4249	{
4250	NOREF(pszArgs);
4251
4252	PVMCPU pVCpu = VMMGetCpu(pVM);
4253	if (!pVCpu)
4254	pVCpu = pVM->apCpusR3[0];
4255
4256	char szInstruction[256];
4257	szInstruction[0] = '\0';
4258	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4259	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4260	}
4261
4262
4263	/**
4264	* Display the hypervisor cpu state.
4265	*
4266	* @param pVM The cross context VM structure.
4267	* @param pHlp The info helper functions.
4268	* @param pszArgs Arguments, ignored.
4269	*/
4270	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4271	{
4272	PVMCPU pVCpu = VMMGetCpu(pVM);
4273	if (!pVCpu)
4274	pVCpu = pVM->apCpusR3[0];
4275
4276	CPUMDUMPTYPE enmType;
4277	const char *pszComment;
4278	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4279	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4280
4281	pHlp->pfnPrintf(pHlp,
4282	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4283	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4284	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4285	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4286	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4287	}
4288
4289
4290	/**
4291	* Display the host cpu state.
4292	*
4293	* @param pVM The cross context VM structure.
4294	* @param pHlp The info helper functions.
4295	* @param pszArgs Arguments, ignored.
4296	*/
4297	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4298	{
4299	CPUMDUMPTYPE enmType;
4300	const char *pszComment;
4301	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4302	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4303
4304	PVMCPU pVCpu = VMMGetCpu(pVM);
4305	if (!pVCpu)
4306	pVCpu = pVM->apCpusR3[0];
4307	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4308
4309	/*
4310	* Format the EFLAGS.
4311	*/
4312	uint64_t efl = pCtx->rflags;
4313	char szEFlags[80];
4314	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4315
4316	/*
4317	* Format the registers.
4318	*/
4319	pHlp->pfnPrintf(pHlp,
4320	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4321	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4322	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4323	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4324	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4325	"r14=%016RX64 r15=%016RX64\n"
4326	"iopl=%d %31s\n"
4327	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4328	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4329	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4330	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4331	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4332	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4333	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4334	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4335	,
4336	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4337	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4338	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4339	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4340	pCtx->r11, pCtx->r12, pCtx->r13,
4341	pCtx->r14, pCtx->r15,
4342	X86_EFL_GET_IOPL(efl), szEFlags,
4343	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4344	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4345	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4346	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4347	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4348	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4349	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4350	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4351	}
4352
4353	/**
4354	* Structure used when disassembling and instructions in DBGF.
4355	* This is used so the reader function can get the stuff it needs.
4356	*/
4357	typedef struct CPUMDISASSTATE
4358	{
4359	/** Pointer to the CPU structure. */
4360	PDISCPUSTATE pCpu;
4361	/** Pointer to the VM. */
4362	PVM pVM;
4363	/** Pointer to the VMCPU. */
4364	PVMCPU pVCpu;
4365	/** Pointer to the first byte in the segment. */
4366	RTGCUINTPTR GCPtrSegBase;
4367	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4368	RTGCUINTPTR GCPtrSegEnd;
4369	/** The size of the segment minus 1. */
4370	RTGCUINTPTR cbSegLimit;
4371	/** Pointer to the current page - R3 Ptr. */
4372	void const *pvPageR3;
4373	/** Pointer to the current page - GC Ptr. */
4374	RTGCPTR pvPageGC;
4375	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4376	PGMPAGEMAPLOCK PageMapLock;
4377	/** Whether the PageMapLock is valid or not. */
4378	bool fLocked;
4379	/** 64 bits mode or not. */
4380	bool f64Bits;
4381	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4382
4383
4384	/**
4385	* @callback_method_impl{FNDISREADBYTES}
4386	*/
4387	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4388	{
4389	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4390	for (;;)
4391	{
4392	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4393
4394	/*
4395	* Need to update the page translation?
4396	*/
4397	if ( !pState->pvPageR3
4398	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4399	{
4400	/* translate the address */
4401	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4402
4403	/* Release mapping lock previously acquired. */
4404	if (pState->fLocked)
4405	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4406	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4407	if (RT_SUCCESS(rc))
4408	pState->fLocked = true;
4409	else
4410	{
4411	pState->fLocked = false;
4412	pState->pvPageR3 = NULL;
4413	return rc;
4414	}
4415	}
4416
4417	/*
4418	* Check the segment limit.
4419	*/
4420	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4421	return VERR_OUT_OF_SELECTOR_BOUNDS;
4422
4423	/*
4424	* Calc how much we can read.
4425	*/
4426	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4427	if (!pState->f64Bits)
4428	{
4429	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4430	if (cb > cbSeg && cbSeg)
4431	cb = cbSeg;
4432	}
4433	if (cb > cbMaxRead)
4434	cb = cbMaxRead;
4435
4436	/*
4437	* Read and advance or exit.
4438	*/
4439	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4440	offInstr += (uint8_t)cb;
4441	if (cb >= cbMinRead)
4442	{
4443	pDis->cbCachedInstr = offInstr;
4444	return VINF_SUCCESS;
4445	}
4446	cbMinRead -= (uint8_t)cb;
4447	cbMaxRead -= (uint8_t)cb;
4448	}
4449	}
4450
4451
4452	/**
4453	* Disassemble an instruction and return the information in the provided structure.
4454	*
4455	* @returns VBox status code.
4456	* @param pVM The cross context VM structure.
4457	* @param pVCpu The cross context virtual CPU structure.
4458	* @param pCtx Pointer to the guest CPU context.
4459	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4460	* @param pCpu Disassembly state.
4461	* @param pszPrefix String prefix for logging (debug only).
4462	*
4463	*/
4464	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4465	const char *pszPrefix)
4466	{
4467	CPUMDISASSTATE State;
4468	int rc;
4469
4470	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4471	State.pCpu = pCpu;
4472	State.pvPageGC = 0;
4473	State.pvPageR3 = NULL;
4474	State.pVM = pVM;
4475	State.pVCpu = pVCpu;
4476	State.fLocked = false;
4477	State.f64Bits = false;
4478
4479	/*
4480	* Get selector information.
4481	*/
4482	DISCPUMODE enmDisCpuMode;
4483	if ( (pCtx->cr0 & X86_CR0_PE)
4484	&& pCtx->eflags.Bits.u1VM == 0)
4485	{
4486	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4487	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4488	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4489	State.GCPtrSegBase = pCtx->cs.u64Base;
4490	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4491	State.cbSegLimit = pCtx->cs.u32Limit;
4492	enmDisCpuMode = (State.f64Bits)
4493	? DISCPUMODE_64BIT
4494	: pCtx->cs.Attr.n.u1DefBig
4495	? DISCPUMODE_32BIT
4496	: DISCPUMODE_16BIT;
4497	}
4498	else
4499	{
4500	/* real or V86 mode */
4501	enmDisCpuMode = DISCPUMODE_16BIT;
4502	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4503	State.GCPtrSegEnd = 0xFFFFFFFF;
4504	State.cbSegLimit = 0xFFFFFFFF;
4505	}
4506
4507	/*
4508	* Disassemble the instruction.
4509	*/
4510	uint32_t cbInstr;
4511	#ifndef LOG_ENABLED
4512	RT_NOREF_PV(pszPrefix);
4513	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4514	if (RT_SUCCESS(rc))
4515	{
4516	#else
4517	char szOutput[160];
4518	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4519	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4520	if (RT_SUCCESS(rc))
4521	{
4522	/* log it */
4523	if (pszPrefix)
4524	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4525	else
4526	Log(("%s", szOutput));
4527	#endif
4528	rc = VINF_SUCCESS;
4529	}
4530	else
4531	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4532
4533	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4534	if (State.fLocked)
4535	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4536
4537	return rc;
4538	}
4539
4540
4541
4542	/**
4543	* API for controlling a few of the CPU features found in CR4.
4544	*
4545	* Currently only X86_CR4_TSD is accepted as input.
4546	*
4547	* @returns VBox status code.
4548	*
4549	* @param pVM The cross context VM structure.
4550	* @param fOr The CR4 OR mask.
4551	* @param fAnd The CR4 AND mask.
4552	*/
4553	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4554	{
4555	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4556	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4557
4558	pVM->cpum.s.CR4.OrMask &= fAnd;
4559	pVM->cpum.s.CR4.OrMask \|= fOr;
4560
4561	return VINF_SUCCESS;
4562	}
4563
4564
4565	/**
4566	* Called when the ring-3 init phase completes.
4567	*
4568	* @returns VBox status code.
4569	* @param pVM The cross context VM structure.
4570	* @param enmWhat Which init phase.
4571	*/
4572	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4573	{
4574	switch (enmWhat)
4575	{
4576	case VMINITCOMPLETED_RING3:
4577	{
4578	/*
4579	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4580	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4581	*/
4582	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4583	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4584	{
4585	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4586
4587	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4588	if (fSupportsLongMode)
4589	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4590	}
4591
4592	/* Register statistic counters for MSRs. */
4593	cpumR3MsrRegStats(pVM);
4594
4595	/* Create VMX-preemption timer for nested guests if required. Must be
4596	done here as CPUM is initialized before TM. */
4597	if (pVM->cpum.s.GuestFeatures.fVmx)
4598	{
4599	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4600	{
4601	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4602	char szName[32];
4603	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4604	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4605	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4606	AssertLogRelRCReturn(rc, rc);
4607	}
4608	}
4609	break;
4610	}
4611
4612	default:
4613	break;
4614	}
4615	return VINF_SUCCESS;
4616	}
4617
4618
4619	/**
4620	* Called when the ring-0 init phases completed.
4621	*
4622	* @param pVM The cross context VM structure.
4623	*/
4624	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4625	{
4626	/*
4627	* Enable log buffering as we're going to log a lot of lines.
4628	*/
4629	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4630
4631	/*
4632	* Log the cpuid.
4633	*/
4634	RTCPUSET OnlineSet;
4635	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4636	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4637	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4638	RTCPUID cCores = RTMpGetCoreCount();
4639	if (cCores)
4640	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4641	LogRel(("*********************** CPUID dump **********************\n"));
4642	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4643	LogRel(("\n"));
4644	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4645	LogRel(("****************** End of CPUID dump ********************\n"));
4646
4647	/*
4648	* Log VT-x extended features.
4649	*
4650	* SVM features are currently all covered under CPUID so there is nothing
4651	* to do here for SVM.
4652	*/
4653	if (pVM->cpum.s.HostFeatures.fVmx)
4654	{
4655	LogRel(("********************* VT-x features *********************\n"));
4656	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4657	LogRel(("\n"));
4658	LogRel(("***************** End of VT-x features ******************\n"));
4659	}
4660
4661	/*
4662	* Restore the log buffering state to what it was previously.
4663	*/
4664	RTLogRelSetBuffering(fOldBuffered);
4665	}
4666

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 91281

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