CPUM.cpp@ 91297

Last change on this file since 91297 was 91297, checked in by vboxsync, 3 years ago
VMM/CPUM,++: Moved the nested VT-X VMCS allocation into CPUMCTX. bugref:10093
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1	/* $Id: CPUM.cpp 91297 2021-09-17 11:51:23Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/hm.h>
120	#include <VBox/vmm/hmvmxinline.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
339
340	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
341	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
342	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
343	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
344	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
345	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
346	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
347	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
348	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
349
350	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
351	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
352
353	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
354	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
355	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
356	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
357	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
358	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
360
361	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
362	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
363	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
364	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
365
366	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
367	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
369	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
370	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
371	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
373	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
374	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
378	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
379	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
380	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
381	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
382	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
383	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
384	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
385
386	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
387	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
388	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
389	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
390	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
391	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
392	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
393	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
394	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
395	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
396	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
397	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
398	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
399	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
400	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
401	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
402	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
403	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
404	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
405	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
406	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
407	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
408	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
409	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
410	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
411	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
412	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
413	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
414	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
415
416	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
417	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
418	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
419	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
420	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
421	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
422	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
423	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
424	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
425
426	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
427	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
428	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
429	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
430	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
431	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
432	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
433	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
434
435	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
436	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
437
438	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
439	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
440	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
441	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
442	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
443
444	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
445	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
446	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
447	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
448	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
449	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
450	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
451	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
452	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
453	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
454	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
455	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
456	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
457	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
458	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
459	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
460
461	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
462	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
463	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
464	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
465	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
466	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
467	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
468	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
469	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
470	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
471	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
472
473	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
474	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
475	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
476	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
477	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
478	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
479	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
480	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
481	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
482	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
483	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
484	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
485	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
486	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
487	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
488	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
489	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
490	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
491	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
492	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
493	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
494	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
495	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
496	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
497
498	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
503	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
504	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
509	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
510	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
511
512	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
513	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
514	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
515	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
519	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
520	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
521	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
532	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
533	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
534	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
535	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
536
537	SSMFIELD_ENTRY_TERM()
538	};
539
540	/** Saved state field descriptors for CPUMCTX. */
541	static const SSMFIELD g_aCpumX87Fields[] =
542	{
543	SSMFIELD_ENTRY( X86FXSTATE, FCW),
544	SSMFIELD_ENTRY( X86FXSTATE, FSW),
545	SSMFIELD_ENTRY( X86FXSTATE, FTW),
546	SSMFIELD_ENTRY( X86FXSTATE, FOP),
547	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
548	SSMFIELD_ENTRY( X86FXSTATE, CS),
549	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
550	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
551	SSMFIELD_ENTRY( X86FXSTATE, DS),
552	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
553	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
554	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
555	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
556	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
557	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
558	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
559	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
560	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
561	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
562	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
564	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
565	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
566	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
567	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
568	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
569	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
570	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
571	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
572	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
573	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
574	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
575	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
576	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
577	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
578	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
579	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
580	SSMFIELD_ENTRY_TERM()
581	};
582
583	/** Saved state field descriptors for X86XSAVEHDR. */
584	static const SSMFIELD g_aCpumXSaveHdrFields[] =
585	{
586	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
587	SSMFIELD_ENTRY_TERM()
588	};
589
590	/** Saved state field descriptors for X86XSAVEYMMHI. */
591	static const SSMFIELD g_aCpumYmmHiFields[] =
592	{
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
594	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
595	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
596	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
597	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
598	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
599	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
600	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
601	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
602	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
603	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
604	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
605	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
606	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
607	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
608	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
609	SSMFIELD_ENTRY_TERM()
610	};
611
612	/** Saved state field descriptors for X86XSAVEBNDREGS. */
613	static const SSMFIELD g_aCpumBndRegsFields[] =
614	{
615	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
616	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
617	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
618	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
619	SSMFIELD_ENTRY_TERM()
620	};
621
622	/** Saved state field descriptors for X86XSAVEBNDCFG. */
623	static const SSMFIELD g_aCpumBndCfgFields[] =
624	{
625	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
626	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
627	SSMFIELD_ENTRY_TERM()
628	};
629
630	#if 0 /** @todo */
631	/** Saved state field descriptors for X86XSAVEOPMASK. */
632	static const SSMFIELD g_aCpumOpmaskFields[] =
633	{
634	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
635	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
636	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
637	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
638	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
639	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
640	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
641	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
642	SSMFIELD_ENTRY_TERM()
643	};
644	#endif
645
646	/** Saved state field descriptors for X86XSAVEZMMHI256. */
647	static const SSMFIELD g_aCpumZmmHi256Fields[] =
648	{
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
650	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
651	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
652	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
653	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
654	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
655	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
656	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
657	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
658	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
659	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
660	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
661	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
662	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
663	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
664	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
665	SSMFIELD_ENTRY_TERM()
666	};
667
668	/** Saved state field descriptors for X86XSAVEZMM16HI. */
669	static const SSMFIELD g_aCpumZmm16HiFields[] =
670	{
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
672	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
673	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
674	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
675	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
676	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
677	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
678	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
679	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
680	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
681	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
682	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
683	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
684	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
685	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
686	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
687	SSMFIELD_ENTRY_TERM()
688	};
689
690
691
692	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
693	* registeres changed. */
694	static const SSMFIELD g_aCpumX87FieldsMem[] =
695	{
696	SSMFIELD_ENTRY( X86FXSTATE, FCW),
697	SSMFIELD_ENTRY( X86FXSTATE, FSW),
698	SSMFIELD_ENTRY( X86FXSTATE, FTW),
699	SSMFIELD_ENTRY( X86FXSTATE, FOP),
700	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
701	SSMFIELD_ENTRY( X86FXSTATE, CS),
702	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
703	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
704	SSMFIELD_ENTRY( X86FXSTATE, DS),
705	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
706	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
707	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
708	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
709	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
710	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
711	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
712	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
713	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
714	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
715	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
717	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
718	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
719	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
720	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
721	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
722	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
723	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
724	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
725	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
726	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
727	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
728	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
729	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
730	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
731	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
732	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
733	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
734	};
735
736	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
737	* registeres changed. */
738	static const SSMFIELD g_aCpumCtxFieldsMem[] =
739	{
740	SSMFIELD_ENTRY( CPUMCTX, rdi),
741	SSMFIELD_ENTRY( CPUMCTX, rsi),
742	SSMFIELD_ENTRY( CPUMCTX, rbp),
743	SSMFIELD_ENTRY( CPUMCTX, rax),
744	SSMFIELD_ENTRY( CPUMCTX, rbx),
745	SSMFIELD_ENTRY( CPUMCTX, rdx),
746	SSMFIELD_ENTRY( CPUMCTX, rcx),
747	SSMFIELD_ENTRY( CPUMCTX, rsp),
748	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
749	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
750	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
751	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
752	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
753	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
754	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
755	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
756	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
757	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
758	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
759	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
760	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
761	SSMFIELD_ENTRY( CPUMCTX, rflags),
762	SSMFIELD_ENTRY( CPUMCTX, rip),
763	SSMFIELD_ENTRY( CPUMCTX, r8),
764	SSMFIELD_ENTRY( CPUMCTX, r9),
765	SSMFIELD_ENTRY( CPUMCTX, r10),
766	SSMFIELD_ENTRY( CPUMCTX, r11),
767	SSMFIELD_ENTRY( CPUMCTX, r12),
768	SSMFIELD_ENTRY( CPUMCTX, r13),
769	SSMFIELD_ENTRY( CPUMCTX, r14),
770	SSMFIELD_ENTRY( CPUMCTX, r15),
771	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
772	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
773	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
774	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
775	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
776	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
777	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
778	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
779	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
780	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
781	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
782	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
783	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
784	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
785	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
786	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
787	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
788	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
789	SSMFIELD_ENTRY( CPUMCTX, cr0),
790	SSMFIELD_ENTRY( CPUMCTX, cr2),
791	SSMFIELD_ENTRY( CPUMCTX, cr3),
792	SSMFIELD_ENTRY( CPUMCTX, cr4),
793	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
794	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
795	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
796	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
797	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
798	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
799	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
800	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
801	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
802	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
803	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
804	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
805	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
806	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
807	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
808	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
809	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
810	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
811	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
812	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
813	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
814	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
815	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
816	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
817	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
818	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
819	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
820	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
821	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
822	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
823	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
824	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
825	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
826	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
827	SSMFIELD_ENTRY_TERM()
828	};
829
830	/** Saved state field descriptors for CPUMCTX_VER1_6. */
831	static const SSMFIELD g_aCpumX87FieldsV16[] =
832	{
833	SSMFIELD_ENTRY( X86FXSTATE, FCW),
834	SSMFIELD_ENTRY( X86FXSTATE, FSW),
835	SSMFIELD_ENTRY( X86FXSTATE, FTW),
836	SSMFIELD_ENTRY( X86FXSTATE, FOP),
837	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
838	SSMFIELD_ENTRY( X86FXSTATE, CS),
839	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
840	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
841	SSMFIELD_ENTRY( X86FXSTATE, DS),
842	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
843	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
844	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
845	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
846	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
847	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
848	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
849	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
850	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
851	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
852	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
854	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
855	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
856	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
857	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
858	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
859	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
860	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
861	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
862	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
863	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
864	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
865	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
866	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
867	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
868	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
869	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
870	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
871	SSMFIELD_ENTRY_TERM()
872	};
873
874	/** Saved state field descriptors for CPUMCTX_VER1_6. */
875	static const SSMFIELD g_aCpumCtxFieldsV16[] =
876	{
877	SSMFIELD_ENTRY( CPUMCTX, rdi),
878	SSMFIELD_ENTRY( CPUMCTX, rsi),
879	SSMFIELD_ENTRY( CPUMCTX, rbp),
880	SSMFIELD_ENTRY( CPUMCTX, rax),
881	SSMFIELD_ENTRY( CPUMCTX, rbx),
882	SSMFIELD_ENTRY( CPUMCTX, rdx),
883	SSMFIELD_ENTRY( CPUMCTX, rcx),
884	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
885	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
886	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
887	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
888	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
889	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
890	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
891	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
892	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
893	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
894	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
895	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
896	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
897	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
898	SSMFIELD_ENTRY( CPUMCTX, rflags),
899	SSMFIELD_ENTRY( CPUMCTX, rip),
900	SSMFIELD_ENTRY( CPUMCTX, r8),
901	SSMFIELD_ENTRY( CPUMCTX, r9),
902	SSMFIELD_ENTRY( CPUMCTX, r10),
903	SSMFIELD_ENTRY( CPUMCTX, r11),
904	SSMFIELD_ENTRY( CPUMCTX, r12),
905	SSMFIELD_ENTRY( CPUMCTX, r13),
906	SSMFIELD_ENTRY( CPUMCTX, r14),
907	SSMFIELD_ENTRY( CPUMCTX, r15),
908	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
909	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
910	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
911	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
912	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
913	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
914	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
915	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
916	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
917	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
918	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
919	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
920	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
921	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
922	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
923	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
924	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
925	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
926	SSMFIELD_ENTRY( CPUMCTX, cr0),
927	SSMFIELD_ENTRY( CPUMCTX, cr2),
928	SSMFIELD_ENTRY( CPUMCTX, cr3),
929	SSMFIELD_ENTRY( CPUMCTX, cr4),
930	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
931	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
932	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
933	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
934	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
935	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
936	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
937	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
938	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
939	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
940	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
941	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
942	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
943	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
944	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
945	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
946	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
947	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
948	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
949	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
950	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
951	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
952	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
953	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
954	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
955	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
956	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
957	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
958	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
959	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
960	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
961	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
962	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
963	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
964	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
965	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
966	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
967	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
968	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
969	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
970	SSMFIELD_ENTRY_TERM()
971	};
972
973
974	/**
975	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
976	*
977	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
978	* (last instruction pointer, last data pointer, last opcode) except when the ES
979	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
980	* clear these registers there is potential, local FPU leakage from a process
981	* using the FPU to another.
982	*
983	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
984	*
985	* @param pVM The cross context VM structure.
986	*/
987	static void cpumR3CheckLeakyFpu(PVM pVM)
988	{
989	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
990	uint32_t const u32Family = u32CpuVersion >> 8;
991	if ( u32Family >= 6 /* K7 and higher */
992	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
993	{
994	uint32_t cExt = ASMCpuId_EAX(0x80000000);
995	if (ASMIsValidExtRange(cExt))
996	{
997	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
998	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
999	{
1000	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1001	{
1002	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1003	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1004	}
1005	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1006	}
1007	}
1008	}
1009	}
1010
1011
1012	/**
1013	* Initialize SVM hardware virtualization state (used to allocate it).
1014	*
1015	* @param pVM The cross context VM structure.
1016	*/
1017	static void cpumR3InitSvmHwVirtState(PVM pVM)
1018	{
1019	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1020
1021	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
1022	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
1023	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1024	{
1025	PVMCPU pVCpu = pVM->apCpusR3[i];
1026	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1027
1028	AssertCompile(SVM_VMCB_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.Vmcb));
1029	AssertCompile(SVM_MSRPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abMsrBitmap));
1030	AssertCompile(SVM_IOPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abIoBitmap));
1031	}
1032	}
1033
1034
1035	/**
1036	* Resets per-VCPU SVM hardware virtualization state.
1037	*
1038	* @param pVCpu The cross context virtual CPU structure.
1039	*/
1040	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1041	{
1042	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1043	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1044
1045	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1046	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1047	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1048	}
1049
1050
1051	/**
1052	* Frees memory allocated for the VMX hardware virtualization state.
1053	*
1054	* @param pVM The cross context VM structure.
1055	*/
1056	static void cpumR3FreeVmxHwVirtState(PVM pVM)
1057	{
1058	Assert(pVM->cpum.s.GuestFeatures.fVmx);
1059	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1060	{
1061	PVMCPU pVCpu = pVM->apCpusR3[i];
1062	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1063
1064	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1065	{
1066	SUPR3ContFree(pCtx->hwvirt.vmx.pShadowVmcsR3, VMX_V_VMCS_PAGES);
1067	pCtx->hwvirt.vmx.pShadowVmcsR3 = NULL;
1068	}
1069	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1070	{
1071	SUPR3ContFree(pCtx->hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
1072	pCtx->hwvirt.vmx.pvVirtApicPageR3 = NULL;
1073	}
1074	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1075	{
1076	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1077	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = NULL;
1078	}
1079	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1080	{
1081	SUPR3ContFree(pCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_PAGES);
1082	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = NULL;
1083	}
1084	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1085	{
1086	SUPR3ContFree(pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1087	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = NULL;
1088	}
1089	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1090	{
1091	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1092	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = NULL;
1093	}
1094	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1095	{
1096	SUPR3ContFree(pCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_PAGES);
1097	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = NULL;
1098	}
1099	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1100	{
1101	SUPR3ContFree(pCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
1102	pCtx->hwvirt.vmx.pvMsrBitmapR3 = NULL;
1103	}
1104	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1105	{
1106	SUPR3ContFree(pCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1107	pCtx->hwvirt.vmx.pvIoBitmapR3 = NULL;
1108	}
1109	}
1110	}
1111
1112
1113	/**
1114	* Allocates memory for the VMX hardware virtualization state.
1115	*
1116	* @returns VBox status code.
1117	* @param pVM The cross context VM structure.
1118	*/
1119	static int cpumR3AllocVmxHwVirtState(PVM pVM)
1120	{
1121	int rc = VINF_SUCCESS;
1122	uint32_t const cPages = VMX_V_VMCS_PAGES
1123	+ VMX_V_SHADOW_VMCS_PAGES
1124	+ VMX_V_VIRT_APIC_PAGES
1125	+ (2 * VMX_V_VMREAD_VMWRITE_BITMAP_PAGES)
1126	+ (3 * VMX_V_AUTOMSR_AREA_PAGES)
1127	+ VMX_V_MSR_BITMAP_PAGES
1128	+ (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1129	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n", pVM->cCpus * cPages));
1130	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1131	{
1132	PVMCPU pVCpu = pVM->apCpusR3[i];
1133	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1134	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1135
1136	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1137
1138	/*
1139	* Allocate the nested-guest shadow VMCS.
1140	*/
1141	pCtx->hwvirt.vmx.pShadowVmcsR3 = (PVMXVVMCS)SUPR3ContAlloc(VMX_V_VMCS_PAGES, &pCtx->hwvirt.vmx.pShadowVmcsR0, NULL);
1142	if (pCtx->hwvirt.vmx.pShadowVmcsR3)
1143	{ /* likely */ }
1144	else
1145	{
1146	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's shadow VMCS\n", pVCpu->idCpu, VMX_V_VMCS_PAGES));
1147	break;
1148	}
1149
1150	/*
1151	* Allocate the virtual-APIC page.
1152	*/
1153	pCtx->hwvirt.vmx.pvVirtApicPageR3 = SUPR3ContAlloc(VMX_V_VIRT_APIC_PAGES,
1154	&pCtx->hwvirt.vmx.pvVirtApicPageR0,
1155	&pCtx->hwvirt.vmx.HCPhysVirtApicPage);
1156	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1157	{ /* likely */ }
1158	else
1159	{
1160	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's virtual-APIC page\n", pVCpu->idCpu,
1161	VMX_V_VIRT_APIC_PAGES));
1162	break;
1163	}
1164
1165	/*
1166	* Allocate the VMREAD-bitmap.
1167	*/
1168	pCtx->hwvirt.vmx.pvVmreadBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1169	&pCtx->hwvirt.vmx.pvVmreadBitmapR0, NULL);
1170	if (pCtx->hwvirt.vmx.pvVmreadBitmapR3)
1171	{ /* likely */ }
1172	else
1173	{
1174	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMREAD-bitmap\n", pVCpu->idCpu,
1175	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1176	break;
1177	}
1178
1179	/*
1180	* Allocatge the VMWRITE-bitmap.
1181	*/
1182	pCtx->hwvirt.vmx.pvVmwriteBitmapR3 = SUPR3ContAlloc(VMX_V_VMREAD_VMWRITE_BITMAP_PAGES,
1183	&pCtx->hwvirt.vmx.pvVmwriteBitmapR0, NULL);
1184	if (pCtx->hwvirt.vmx.pvVmwriteBitmapR3)
1185	{ /* likely */ }
1186	else
1187	{
1188	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VMWRITE-bitmap\n", pVCpu->idCpu,
1189	VMX_V_VMREAD_VMWRITE_BITMAP_PAGES));
1190	break;
1191	}
1192
1193	/*
1194	* Allocate the VM-entry MSR-load area.
1195	*/
1196	pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1197	&pCtx->hwvirt.vmx.pEntryMsrLoadAreaR0, NULL);
1198	if (pCtx->hwvirt.vmx.pEntryMsrLoadAreaR3)
1199	{ /* likely */ }
1200	else
1201	{
1202	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-entry MSR-load area\n", pVCpu->idCpu,
1203	VMX_V_AUTOMSR_AREA_PAGES));
1204	break;
1205	}
1206
1207	/*
1208	* Allocate the VM-exit MSR-store area.
1209	*/
1210	pCtx->hwvirt.vmx.pExitMsrStoreAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1211	&pCtx->hwvirt.vmx.pExitMsrStoreAreaR0, NULL);
1212	if (pCtx->hwvirt.vmx.pExitMsrStoreAreaR3)
1213	{ /* likely */ }
1214	else
1215	{
1216	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-store area\n", pVCpu->idCpu,
1217	VMX_V_AUTOMSR_AREA_PAGES));
1218	break;
1219	}
1220
1221	/*
1222	* Allocate the VM-exit MSR-load area.
1223	*/
1224	pCtx->hwvirt.vmx.pExitMsrLoadAreaR3 = (PVMXAUTOMSR)SUPR3ContAlloc(VMX_V_AUTOMSR_AREA_PAGES,
1225	&pCtx->hwvirt.vmx.pExitMsrLoadAreaR0, NULL);
1226	if (pCtx->hwvirt.vmx.pExitMsrLoadAreaR3)
1227	{ /* likely */ }
1228	else
1229	{
1230	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's VM-exit MSR-load area\n", pVCpu->idCpu,
1231	VMX_V_AUTOMSR_AREA_PAGES));
1232	break;
1233	}
1234
1235	/*
1236	* Allocate the MSR bitmap.
1237	*/
1238	pCtx->hwvirt.vmx.pvMsrBitmapR3 = SUPR3ContAlloc(VMX_V_MSR_BITMAP_PAGES, &pCtx->hwvirt.vmx.pvMsrBitmapR0, NULL);
1239	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1240	{ /* likely */ }
1241	else
1242	{
1243	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1244	VMX_V_MSR_BITMAP_PAGES));
1245	break;
1246	}
1247
1248	/*
1249	* Allocate the I/O bitmaps (A and B).
1250	*/
1251	pCtx->hwvirt.vmx.pvIoBitmapR3 = SUPR3ContAlloc(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES,
1252	&pCtx->hwvirt.vmx.pvIoBitmapR0, NULL);
1253	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1254	{ /* likely */ }
1255	else
1256	{
1257	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1258	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1259	break;
1260	}
1261
1262	/*
1263	* Zero out all allocated pages (should compress well for saved-state).
1264	*/
1265	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1266	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1267	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVirtApicPage), 0, VMX_V_VIRT_APIC_SIZE);
1268	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmreadBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1269	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVmwriteBitmap), 0, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1270	memset(pCtx->hwvirt.vmx.CTX_SUFF(pEntryMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1271	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrStoreArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1272	memset(pCtx->hwvirt.vmx.CTX_SUFF(pExitMsrLoadArea), 0, VMX_V_AUTOMSR_AREA_SIZE);
1273	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvMsrBitmap), 0, VMX_V_MSR_BITMAP_SIZE);
1274	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap), 0, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1275	}
1276
1277	/* On any failure, cleanup. */
1278	if (RT_FAILURE(rc))
1279	cpumR3FreeVmxHwVirtState(pVM);
1280
1281	return rc;
1282	}
1283
1284
1285	/**
1286	* Resets per-VCPU VMX hardware virtualization state.
1287	*
1288	* @param pVCpu The cross context virtual CPU structure.
1289	*/
1290	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1291	{
1292	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1293	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1294	Assert(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs));
1295
1296	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1297	memset(pCtx->hwvirt.vmx.CTX_SUFF(pShadowVmcs), 0, VMX_V_SHADOW_VMCS_SIZE);
1298	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1299	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1300	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1301	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1302	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1303	/* Don't reset diagnostics here. */
1304
1305	/* Stop any VMX-preemption timer. */
1306	CPUMStopGuestVmxPremptTimer(pVCpu);
1307
1308	/* Clear all nested-guest FFs. */
1309	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1310	}
1311
1312
1313	/**
1314	* Displays the host and guest VMX features.
1315	*
1316	* @param pVM The cross context VM structure.
1317	* @param pHlp The info helper functions.
1318	* @param pszArgs "terse", "default" or "verbose".
1319	*/
1320	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1321	{
1322	RT_NOREF(pszArgs);
1323	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1324	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1325	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1326	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1327	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1328	{
1329	#define VMXFEATDUMP(a_szDesc, a_Var) \
1330	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1331
1332	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1333	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1334	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1335	/* Basic. */
1336	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1337	/* Pin-based controls. */
1338	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1339	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1340	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1341	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1342	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1343	/* Processor-based controls. */
1344	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1345	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1346	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1347	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1348	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1349	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1350	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1351	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1352	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1353	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1354	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1355	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1356	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1357	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1358	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1359	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1360	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1361	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1362	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1363	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1364	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1365	/* Secondary processor-based controls. */
1366	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1367	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1368	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1369	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1370	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1371	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1372	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1373	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1374	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1375	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1376	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1377	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1378	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1379	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1380	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1381	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1382	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1383	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1384	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1385	/* VM-entry controls. */
1386	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1387	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1388	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1389	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1390	/* VM-exit controls. */
1391	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1392	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1393	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1394	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1395	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1396	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1397	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1398	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1399	/* Miscellaneous data. */
1400	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1401	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1402	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1403	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1404	#undef VMXFEATDUMP
1405	}
1406	else
1407	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1408	}
1409
1410
1411	/**
1412	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1413	* or NEM) is allowed.
1414	*
1415	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1416	* otherwise.
1417	* @param pVM The cross context VM structure.
1418	*/
1419	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1420	{
1421	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1422	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1423	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1424	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1425	return true;
1426	#else
1427	NOREF(pVM);
1428	#endif
1429	return false;
1430	}
1431
1432
1433	/**
1434	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1435	*
1436	* @param pVM The cross context VM structure.
1437	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1438	* and no hardware-assisted nested-guest execution is
1439	* possible for this VM.
1440	* @param pGuestFeatures The guest features to use (only VMX features are
1441	* accessed).
1442	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1443	*
1444	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1445	*/
1446	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1447	{
1448	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1449
1450	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1451	Assert(pGuestFeatures->fVmx);
1452
1453	/*
1454	* We don't support the following MSRs yet:
1455	* - True Pin-based VM-execution controls.
1456	* - True Processor-based VM-execution controls.
1457	* - True VM-entry VM-execution controls.
1458	* - True VM-exit VM-execution controls.
1459	*/
1460
1461	/* Feature control. */
1462	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1463
1464	/* Basic information. */
1465	{
1466	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1467	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1468	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1469	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1470	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1471	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1472	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1473	pGuestVmxMsrs->u64Basic = u64Basic;
1474	}
1475
1476	/* Pin-based VM-execution controls. */
1477	{
1478	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1479	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1480	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1481	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1482	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1483	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1484	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1485	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1486	fAllowed0, fAllowed1, fFeatures));
1487	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1488	}
1489
1490	/* Processor-based VM-execution controls. */
1491	{
1492	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1493	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1494	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1495	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1496	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1497	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1498	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1499	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1500	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1501	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1502	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1503	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1504	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1505	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1506	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1507	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1508	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1509	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1510	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1511	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1512	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1513	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1514	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1515	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1516	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1517	fAllowed1, fFeatures));
1518	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1519	}
1520
1521	/* Secondary processor-based VM-execution controls. */
1522	if (pGuestFeatures->fVmxSecondaryExecCtls)
1523	{
1524	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1525	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1526	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1527	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1528	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1529	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1530	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1531	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1532	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1533	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1534	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1535	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1536	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1537	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1538	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1539	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1540	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1541	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1542	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1543	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1544	uint32_t const fAllowed0 = 0;
1545	uint32_t const fAllowed1 = fFeatures;
1546	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1547	}
1548
1549	/* Tertiary processor-based VM-execution controls. */
1550	if (pGuestFeatures->fVmxTertiaryExecCtls)
1551	{
1552	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1553	}
1554
1555	/* VM-exit controls. */
1556	{
1557	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1558	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1559	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1560	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1561	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1562	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1563	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1564	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1565	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1566	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1567	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1568	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1569	fAllowed1, fFeatures));
1570	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1571	}
1572
1573	/* VM-entry controls. */
1574	{
1575	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1576	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1577	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1578	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1579	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1580	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1581	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1582	fAllowed1, fFeatures));
1583	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1584	}
1585
1586	/* Miscellaneous data. */
1587	{
1588	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1589
1590	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1591	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1592	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1593	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1594	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1595	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1596	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1597	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1598	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1599	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1600	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1601	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1602	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1603	}
1604
1605	/* CR0 Fixed-0. */
1606	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1607
1608	/* CR0 Fixed-1. */
1609	{
1610	/*
1611	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1612	* This is different from CR4 fixed-1 bits which are reported as per the
1613	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1614	*/
1615	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1616	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1617	}
1618
1619	/* CR4 Fixed-0. */
1620	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1621
1622	/* CR4 Fixed-1. */
1623	{
1624	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1625	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1626	}
1627
1628	/* VMCS Enumeration. */
1629	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1630
1631	/* VPID and EPT Capabilities. */
1632	if (pGuestFeatures->fVmxEpt)
1633	{
1634	/*
1635	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1636	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1637	* when INVVPID instruction is supported just to be more compatible with guest
1638	* hypervisors that may make assumptions by only looking at this MSR even though they
1639	* are technically supposed to refer to bit 37 of MSR_IA32_VMX_PROC_CTLS2 first.
1640	*
1641	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1642	* See Intel spec. 30.3 "VMX Instructions".
1643	*/
1644	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1645	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1646
1647	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_RWX_X_ONLY);
1648	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1649	uint8_t const fEptMemUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_UC);
1650	uint8_t const fEptMemWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_WB);
1651	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1652	uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G);
1653	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1654	uint8_t const fEptAccDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1655	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1656	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1657	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1658	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1659	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1660	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1661	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_RWX_X_ONLY, fExecOnly)
1662	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1663	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EMT_UC, fEptMemUc)
1664	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EMT_WB, fEptMemWb)
1665	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1666	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage)
1667	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1668	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY, fEptAccDirty)
1669	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT, 0)
1670	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1671	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1672	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1673	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1674	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1675	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1676	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1677	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1678	}
1679
1680	/* VM Functions. */
1681	if (pGuestFeatures->fVmxVmFunc)
1682	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1683	}
1684
1685
1686	/**
1687	* Checks whether the given guest CPU VMX features are compatible with the provided
1688	* base features.
1689	*
1690	* @returns @c true if compatible, @c false otherwise.
1691	* @param pVM The cross context VM structure.
1692	* @param pBase The base VMX CPU features.
1693	* @param pGst The guest VMX CPU features.
1694	*
1695	* @remarks Only VMX feature bits are examined.
1696	*/
1697	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1698	{
1699	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1700	return false;
1701
1702	/* Check first set of feature bits. */
1703	{
1704	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1705	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1706	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1707	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1708	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1709	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1710	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1711	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1712	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1713	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1714	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1715	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1716	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1717	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1718	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1719	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1720	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1721	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1722	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1723	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1724	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1725	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1726	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1727	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1728	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1729	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1730	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1731	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1732	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1733	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1734	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1735	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1736
1737	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1738	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1739	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1740	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1741	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1742	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1743	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1744	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1745	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1746	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1747	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1748	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1749	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1750	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1751	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1752	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1753	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1754	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1755	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1756	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1757	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1758	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1759	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1760	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1761	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1762	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1763	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1764	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1765	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1766	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1767	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1768	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1769
1770	if ((fBase \| fGst) != fBase)
1771	{
1772	uint64_t const fDiff = fBase ^ fGst;
1773	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1774	fBase, fGst, fDiff));
1775	return false;
1776	}
1777	}
1778
1779	/* Check second set of feature bits. */
1780	{
1781	uint64_t const fBase = ((uint64_t)pBase->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pBase->fVmxLoadIwKeyExit << 1);
1782	uint64_t const fGst = ((uint64_t)pGst->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pGst->fVmxLoadIwKeyExit << 1);
1783	if ((fBase \| fGst) != fBase)
1784	{
1785	uint64_t const fDiff = fBase ^ fGst;
1786	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1787	fBase, fGst, fDiff));
1788	return false;
1789	}
1790	}
1791
1792	return true;
1793	}
1794
1795
1796	/**
1797	* Initializes VMX guest features and MSRs.
1798	*
1799	* @param pVM The cross context VM structure.
1800	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1801	* and no hardware-assisted nested-guest execution is
1802	* possible for this VM.
1803	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1804	*/
1805	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1806	{
1807	Assert(pVM);
1808	Assert(pGuestVmxMsrs);
1809
1810	/*
1811	* While it would be nice to check this earlier while initializing fNestedVmxEpt
1812	* but we would not have enumearted host features then, so do it at least now.
1813	*/
1814	if ( !pVM->cpum.s.HostFeatures.fNoExecute
1815	&& pVM->cpum.s.fNestedVmxEpt)
1816	{
1817	LogRel(("CPUM: Warning! EPT not exposed to the guest since NX isn't available on the host.\n"));
1818	pVM->cpum.s.fNestedVmxEpt = false;
1819	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1820	}
1821
1822	/*
1823	* Initialize the set of VMX features we emulate.
1824	*
1825	* Note! Some bits might be reported as 1 always if they fall under the
1826	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1827	*/
1828	CPUMFEATURES EmuFeat;
1829	RT_ZERO(EmuFeat);
1830	EmuFeat.fVmx = 1;
1831	EmuFeat.fVmxInsOutInfo = 1;
1832	EmuFeat.fVmxExtIntExit = 1;
1833	EmuFeat.fVmxNmiExit = 1;
1834	EmuFeat.fVmxVirtNmi = 1;
1835	EmuFeat.fVmxPreemptTimer = 0; /* pVM->cpum.s.fNestedVmxPreemptTimer -- Currently disabled on purpose, see @bugref{9180#c108}. */
1836	EmuFeat.fVmxPostedInt = 0;
1837	EmuFeat.fVmxIntWindowExit = 1;
1838	EmuFeat.fVmxTscOffsetting = 1;
1839	EmuFeat.fVmxHltExit = 1;
1840	EmuFeat.fVmxInvlpgExit = 1;
1841	EmuFeat.fVmxMwaitExit = 1;
1842	EmuFeat.fVmxRdpmcExit = 1;
1843	EmuFeat.fVmxRdtscExit = 1;
1844	EmuFeat.fVmxCr3LoadExit = 1;
1845	EmuFeat.fVmxCr3StoreExit = 1;
1846	EmuFeat.fVmxTertiaryExecCtls = 0;
1847	EmuFeat.fVmxCr8LoadExit = 1;
1848	EmuFeat.fVmxCr8StoreExit = 1;
1849	EmuFeat.fVmxUseTprShadow = 1;
1850	EmuFeat.fVmxNmiWindowExit = 0;
1851	EmuFeat.fVmxMovDRxExit = 1;
1852	EmuFeat.fVmxUncondIoExit = 1;
1853	EmuFeat.fVmxUseIoBitmaps = 1;
1854	EmuFeat.fVmxMonitorTrapFlag = 0;
1855	EmuFeat.fVmxUseMsrBitmaps = 1;
1856	EmuFeat.fVmxMonitorExit = 1;
1857	EmuFeat.fVmxPauseExit = 1;
1858	EmuFeat.fVmxSecondaryExecCtls = 1;
1859	EmuFeat.fVmxVirtApicAccess = 1;
1860	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1861	EmuFeat.fVmxDescTableExit = 1;
1862	EmuFeat.fVmxRdtscp = 1;
1863	EmuFeat.fVmxVirtX2ApicMode = 0;
1864	EmuFeat.fVmxVpid = EmuFeat.fVmxEpt;
1865	EmuFeat.fVmxWbinvdExit = 1;
1866	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1867	EmuFeat.fVmxApicRegVirt = 0;
1868	EmuFeat.fVmxVirtIntDelivery = 0;
1869	EmuFeat.fVmxPauseLoopExit = 0;
1870	EmuFeat.fVmxRdrandExit = 0;
1871	EmuFeat.fVmxInvpcid = 1;
1872	EmuFeat.fVmxVmFunc = 0;
1873	EmuFeat.fVmxVmcsShadowing = 0;
1874	EmuFeat.fVmxRdseedExit = 0;
1875	EmuFeat.fVmxPml = 0;
1876	EmuFeat.fVmxEptXcptVe = 0;
1877	EmuFeat.fVmxXsavesXrstors = 0;
1878	EmuFeat.fVmxUseTscScaling = 0;
1879	EmuFeat.fVmxLoadIwKeyExit = 0;
1880	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1881	EmuFeat.fVmxIa32eModeGuest = 1;
1882	EmuFeat.fVmxEntryLoadEferMsr = 1;
1883	EmuFeat.fVmxEntryLoadPatMsr = 0;
1884	EmuFeat.fVmxExitSaveDebugCtls = 1;
1885	EmuFeat.fVmxHostAddrSpaceSize = 1;
1886	EmuFeat.fVmxExitAckExtInt = 1;
1887	EmuFeat.fVmxExitSavePatMsr = 0;
1888	EmuFeat.fVmxExitLoadPatMsr = 0;
1889	EmuFeat.fVmxExitSaveEferMsr = 1;
1890	EmuFeat.fVmxExitLoadEferMsr = 1;
1891	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1892	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1893	EmuFeat.fVmxIntelPt = 0;
1894	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1895	EmuFeat.fVmxEntryInjectSoftInt = 1;
1896
1897	/*
1898	* Merge guest features.
1899	*
1900	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1901	* by the hardware, hence we merge our emulated features with the host features below.
1902	*/
1903	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1904	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1905	Assert(pBaseFeat->fVmx);
1906	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1907	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1908	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1909	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1910	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1911	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1912	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1913	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1914	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1915	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1916	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1917	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1918	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1919	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1920	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1921	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1922	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1923	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1924	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1925	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1926	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1927	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1928	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1929	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1930	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1931	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1932	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1933	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1934	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1935	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1936	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1937	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1938	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1939	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1940	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1941	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1942	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1943	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1944	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1945	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1946	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1947	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1948	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1949	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1950	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1951	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1952	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1953	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1954	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1955	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1956	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1957	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1958	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1959	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1960	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1961	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1962	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1963	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1964	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1965	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1966	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1967	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1968	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1969	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1970	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1971
1972	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1973	if ( pGuestFeat->fVmxPreemptTimer
1974	&& HMIsSubjectToVmxPreemptTimerErratum())
1975	{
1976	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1977	pGuestFeat->fVmxPreemptTimer = 0;
1978	pGuestFeat->fVmxSavePreemptTimer = 0;
1979	}
1980
1981	/* Sanity checking. */
1982	if (!pGuestFeat->fVmxSecondaryExecCtls)
1983	{
1984	Assert(!pGuestFeat->fVmxVirtApicAccess);
1985	Assert(!pGuestFeat->fVmxEpt);
1986	Assert(!pGuestFeat->fVmxDescTableExit);
1987	Assert(!pGuestFeat->fVmxRdtscp);
1988	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1989	Assert(!pGuestFeat->fVmxVpid);
1990	Assert(!pGuestFeat->fVmxWbinvdExit);
1991	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1992	Assert(!pGuestFeat->fVmxApicRegVirt);
1993	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1994	Assert(!pGuestFeat->fVmxPauseLoopExit);
1995	Assert(!pGuestFeat->fVmxRdrandExit);
1996	Assert(!pGuestFeat->fVmxInvpcid);
1997	Assert(!pGuestFeat->fVmxVmFunc);
1998	Assert(!pGuestFeat->fVmxVmcsShadowing);
1999	Assert(!pGuestFeat->fVmxRdseedExit);
2000	Assert(!pGuestFeat->fVmxPml);
2001	Assert(!pGuestFeat->fVmxEptXcptVe);
2002	Assert(!pGuestFeat->fVmxXsavesXrstors);
2003	Assert(!pGuestFeat->fVmxUseTscScaling);
2004	}
2005	else if (pGuestFeat->fVmxUnrestrictedGuest)
2006	{
2007	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2008	Assert(pGuestFeat->fVmxExitSaveEferLma);
2009	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
2010	Assert(pGuestFeat->fVmxEpt);
2011	}
2012
2013	if (!pGuestFeat->fVmxTertiaryExecCtls)
2014	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
2015
2016	/*
2017	* Finally initialize the VMX guest MSRs.
2018	*/
2019	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2020	}
2021
2022
2023	/**
2024	* Gets the host hardware-virtualization MSRs.
2025	*
2026	* @returns VBox status code.
2027	* @param pMsrs Where to store the MSRs.
2028	*/
2029	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2030	{
2031	Assert(pMsrs);
2032
2033	uint32_t fCaps = 0;
2034	int rc = SUPR3QueryVTCaps(&fCaps);
2035	if (RT_SUCCESS(rc))
2036	{
2037	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2038	{
2039	SUPHWVIRTMSRS HwvirtMsrs;
2040	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2041	if (RT_SUCCESS(rc))
2042	{
2043	if (fCaps & SUPVTCAPS_VT_X)
2044	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2045	else
2046	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2047	return VINF_SUCCESS;
2048	}
2049
2050	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2051	return rc;
2052	}
2053
2054	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2055	return VERR_INTERNAL_ERROR_5;
2056	}
2057	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2058	return VINF_SUCCESS;
2059	}
2060
2061
2062	/**
2063	* @callback_method_impl{FNTMTIMERINT,
2064	* Callback that fires when the nested VMX-preemption timer expired.}
2065	*/
2066	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2067	{
2068	RT_NOREF(pVM, hTimer);
2069	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2070	AssertPtr(pVCpu);
2071	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2072	}
2073
2074
2075	/**
2076	* Initializes the CPUM.
2077	*
2078	* @returns VBox status code.
2079	* @param pVM The cross context VM structure.
2080	*/
2081	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2082	{
2083	LogFlow(("CPUMR3Init\n"));
2084
2085	/*
2086	* Assert alignment, sizes and tables.
2087	*/
2088	AssertCompileMemberAlignment(VM, cpum.s, 32);
2089	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2090	AssertCompileSizeAlignment(CPUMCTX, 64);
2091	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2092	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2093	AssertCompileMemberAlignment(VM, cpum, 64);
2094	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2095	#ifdef VBOX_STRICT
2096	int rc2 = cpumR3MsrStrictInitChecks();
2097	AssertRCReturn(rc2, rc2);
2098	#endif
2099
2100	/*
2101	* Gather info about the host CPU.
2102	*/
2103	if (!ASMHasCpuId())
2104	{
2105	LogRel(("The CPU doesn't support CPUID!\n"));
2106	return VERR_UNSUPPORTED_CPU;
2107	}
2108
2109	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2110
2111	CPUMMSRS HostMsrs;
2112	RT_ZERO(HostMsrs);
2113	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2114	AssertLogRelRCReturn(rc, rc);
2115
2116	PCPUMCPUIDLEAF paLeaves;
2117	uint32_t cLeaves;
2118	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
2119	AssertLogRelRCReturn(rc, rc);
2120
2121	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
2122	RTMemFree(paLeaves);
2123	AssertLogRelRCReturn(rc, rc);
2124	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2125
2126	/*
2127	* Check that the CPU supports the minimum features we require.
2128	*/
2129	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2130	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2131	if (!pVM->cpum.s.HostFeatures.fMmx)
2132	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2133	if (!pVM->cpum.s.HostFeatures.fTsc)
2134	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2135
2136	/*
2137	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2138	*/
2139	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2140	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2141
2142	/*
2143	* Figure out which XSAVE/XRSTOR features are available on the host.
2144	*/
2145	uint64_t fXcr0Host = 0;
2146	uint64_t fXStateHostMask = 0;
2147	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2148	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2149	{
2150	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2151	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2152	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2153	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2154	}
2155	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2156	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2157	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2158
2159	/*
2160	* Initialize the host XSAVE/XRSTOR mask.
2161	*/
2162	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2163	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2164	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2165	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2166	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2167	, VERR_CPUM_IPE_2);
2168
2169	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2170	{
2171	PVMCPU pVCpu = pVM->apCpusR3[i];
2172
2173	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2174	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2175	}
2176
2177	/*
2178	* Register saved state data item.
2179	*/
2180	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2181	NULL, cpumR3LiveExec, NULL,
2182	NULL, cpumR3SaveExec, NULL,
2183	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2184	if (RT_FAILURE(rc))
2185	return rc;
2186
2187	/*
2188	* Register info handlers and registers with the debugger facility.
2189	*/
2190	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2191	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2192	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2193	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2194	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2195	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2196	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2197	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2198	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2199	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2200	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2201	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2202	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2203	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2204	&cpumR3InfoVmxFeatures);
2205
2206	rc = cpumR3DbgInit(pVM);
2207	if (RT_FAILURE(rc))
2208	return rc;
2209
2210	/*
2211	* Check if we need to workaround partial/leaky FPU handling.
2212	*/
2213	cpumR3CheckLeakyFpu(pVM);
2214
2215	/*
2216	* Initialize the Guest CPUID and MSR states.
2217	*/
2218	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2219	if (RT_FAILURE(rc))
2220	return rc;
2221
2222	/*
2223	* Allocate memory required by the guest hardware-virtualization structures.
2224	* This must be done after initializing CPUID/MSR features as we access the
2225	* the VMX/SVM guest features below.
2226	*
2227	* In the case of nested VT-x, we also need to create the per-VCPU
2228	* VMX preemption timers.
2229	*/
2230	if (pVM->cpum.s.GuestFeatures.fVmx)
2231	rc = cpumR3AllocVmxHwVirtState(pVM);
2232	else if (pVM->cpum.s.GuestFeatures.fSvm)
2233	cpumR3InitSvmHwVirtState(pVM);
2234	else
2235	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2236	if (RT_FAILURE(rc))
2237	return rc;
2238
2239	CPUMR3Reset(pVM);
2240	return VINF_SUCCESS;
2241	}
2242
2243
2244	/**
2245	* Applies relocations to data and code managed by this
2246	* component. This function will be called at init and
2247	* whenever the VMM need to relocate it self inside the GC.
2248	*
2249	* The CPUM will update the addresses used by the switcher.
2250	*
2251	* @param pVM The cross context VM structure.
2252	*/
2253	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2254	{
2255	RT_NOREF(pVM);
2256	}
2257
2258
2259	/**
2260	* Terminates the CPUM.
2261	*
2262	* Termination means cleaning up and freeing all resources,
2263	* the VM it self is at this point powered off or suspended.
2264	*
2265	* @returns VBox status code.
2266	* @param pVM The cross context VM structure.
2267	*/
2268	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2269	{
2270	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2271	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2272	{
2273	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2274	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2275	pVCpu->cpum.s.uMagic = 0;
2276	pvCpu->cpum.s.Guest.dr[5] = 0;
2277	}
2278	#endif
2279
2280	if (pVM->cpum.s.GuestFeatures.fVmx)
2281	{
2282	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2283	{
2284	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2285	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2286	{
2287	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2288	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2289	}
2290	}
2291
2292	cpumR3FreeVmxHwVirtState(pVM);
2293	}
2294	return VINF_SUCCESS;
2295	}
2296
2297
2298	/**
2299	* Resets a virtual CPU.
2300	*
2301	* Used by CPUMR3Reset and CPU hot plugging.
2302	*
2303	* @param pVM The cross context VM structure.
2304	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2305	* being reset. This may differ from the current EMT.
2306	*/
2307	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2308	{
2309	/** @todo anything different for VCPU > 0? */
2310	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2311
2312	/*
2313	* Initialize everything to ZERO first.
2314	*/
2315	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2316
2317	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2318
2319	pVCpu->cpum.s.fUseFlags = fUseFlags;
2320
2321	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2322	pCtx->eip = 0x0000fff0;
2323	pCtx->edx = 0x00000600; /* P6 processor */
2324	pCtx->eflags.Bits.u1Reserved0 = 1;
2325
2326	pCtx->cs.Sel = 0xf000;
2327	pCtx->cs.ValidSel = 0xf000;
2328	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2329	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2330	pCtx->cs.u32Limit = 0x0000ffff;
2331	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2332	pCtx->cs.Attr.n.u1Present = 1;
2333	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2334
2335	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2336	pCtx->ds.u32Limit = 0x0000ffff;
2337	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2338	pCtx->ds.Attr.n.u1Present = 1;
2339	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2340
2341	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2342	pCtx->es.u32Limit = 0x0000ffff;
2343	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2344	pCtx->es.Attr.n.u1Present = 1;
2345	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2346
2347	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2348	pCtx->fs.u32Limit = 0x0000ffff;
2349	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2350	pCtx->fs.Attr.n.u1Present = 1;
2351	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2352
2353	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2354	pCtx->gs.u32Limit = 0x0000ffff;
2355	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2356	pCtx->gs.Attr.n.u1Present = 1;
2357	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2358
2359	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2360	pCtx->ss.u32Limit = 0x0000ffff;
2361	pCtx->ss.Attr.n.u1Present = 1;
2362	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2363	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2364
2365	pCtx->idtr.cbIdt = 0xffff;
2366	pCtx->gdtr.cbGdt = 0xffff;
2367
2368	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2369	pCtx->ldtr.u32Limit = 0xffff;
2370	pCtx->ldtr.Attr.n.u1Present = 1;
2371	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2372
2373	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2374	pCtx->tr.u32Limit = 0xffff;
2375	pCtx->tr.Attr.n.u1Present = 1;
2376	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2377
2378	pCtx->dr[6] = X86_DR6_INIT_VAL;
2379	pCtx->dr[7] = X86_DR7_INIT_VAL;
2380
2381	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2382	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2383	pFpuCtx->FCW = 0x37f;
2384
2385	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2386	IA-32 Processor States Following Power-up, Reset, or INIT */
2387	pFpuCtx->MXCSR = 0x1F80;
2388	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2389
2390	pCtx->aXcr[0] = XSAVE_C_X87;
2391	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2392	{
2393	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2394	as we don't know what happened before. (Bother optimize later?) */
2395	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2396	}
2397
2398	/*
2399	* MSRs.
2400	*/
2401	/* Init PAT MSR */
2402	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2403
2404	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2405	* The Intel docs don't mention it. */
2406	Assert(!pCtx->msrEFER);
2407
2408	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2409	is supposed to be here, just trying provide useful/sensible values. */
2410	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2411	if (pRange)
2412	{
2413	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2414	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2415	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2416	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2417	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2418	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2419	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2420	}
2421
2422	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2423
2424	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2425	* called from each EMT while we're getting called by CPUMR3Reset()
2426	* iteratively on the same thread. Fix later. */
2427	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2428	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2429	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2430	#endif
2431
2432
2433	/* C-state control. Guesses. */
2434	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2435	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2436	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2437	* functionality. The default value must be different due to incompatible write mask.
2438	*/
2439	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2440	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2441	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2442	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2443
2444	/*
2445	* Hardware virtualization state.
2446	*/
2447	CPUMSetGuestGif(pCtx, true);
2448	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2449	if (pVM->cpum.s.GuestFeatures.fVmx)
2450	cpumR3ResetVmxHwVirtState(pVCpu);
2451	else if (pVM->cpum.s.GuestFeatures.fSvm)
2452	cpumR3ResetSvmHwVirtState(pVCpu);
2453	}
2454
2455
2456	/**
2457	* Resets the CPU.
2458	*
2459	* @returns VINF_SUCCESS.
2460	* @param pVM The cross context VM structure.
2461	*/
2462	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2463	{
2464	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2465	{
2466	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2467	CPUMR3ResetCpu(pVM, pVCpu);
2468
2469	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2470
2471	/* Magic marker for searching in crash dumps. */
2472	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2473	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2474	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2475	#endif
2476	}
2477	}
2478
2479
2480
2481
2482	/**
2483	* Pass 0 live exec callback.
2484	*
2485	* @returns VINF_SSM_DONT_CALL_AGAIN.
2486	* @param pVM The cross context VM structure.
2487	* @param pSSM The saved state handle.
2488	* @param uPass The pass (0).
2489	*/
2490	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2491	{
2492	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2493	cpumR3SaveCpuId(pVM, pSSM);
2494	return VINF_SSM_DONT_CALL_AGAIN;
2495	}
2496
2497
2498	/**
2499	* Execute state save operation.
2500	*
2501	* @returns VBox status code.
2502	* @param pVM The cross context VM structure.
2503	* @param pSSM SSM operation handle.
2504	*/
2505	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2506	{
2507	/*
2508	* Save.
2509	*/
2510	SSMR3PutU32(pSSM, pVM->cCpus);
2511	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2512	CPUMCTX DummyHyperCtx;
2513	RT_ZERO(DummyHyperCtx);
2514	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2515	{
2516	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2517
2518	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2519
2520	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2521	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2522	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2523	if (pGstCtx->fXStateMask != 0)
2524	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2525	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2526	{
2527	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2528	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2529	}
2530	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2531	{
2532	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2533	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2534	}
2535	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2536	{
2537	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2538	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2539	}
2540	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2541	{
2542	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2543	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2544	}
2545	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2546	{
2547	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2548	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2549	}
2550	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2551	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2552	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2553	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2554	if (pVM->cpum.s.GuestFeatures.fSvm)
2555	{
2556	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2557	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2558	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2559	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2560	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2561	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2562	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2563	g_aSvmHwvirtHostState, NULL /* pvUser */);
2564	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2565	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2566	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2567	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2568	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2569	}
2570	if (pVM->cpum.s.GuestFeatures.fVmx)
2571	{
2572	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2573	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2574	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2575	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2576	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2577	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2578	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2579	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2580	SSMR3PutStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2581	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2582	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2583	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2584	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2585	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2586	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2587	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2588	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2589	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2590	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2591	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2592	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2593	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2594	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2595	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2596	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2597	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2598	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2599	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2600	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2601	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2602	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2603	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2604	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2605	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2606	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2607	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2608	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2609	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2610	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2611	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2612	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2613	}
2614	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2615	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2616	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2617	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2618	}
2619
2620	cpumR3SaveCpuId(pVM, pSSM);
2621	return VINF_SUCCESS;
2622	}
2623
2624
2625	/**
2626	* @callback_method_impl{FNSSMINTLOADPREP}
2627	*/
2628	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2629	{
2630	NOREF(pSSM);
2631	pVM->cpum.s.fPendingRestore = true;
2632	return VINF_SUCCESS;
2633	}
2634
2635
2636	/**
2637	* @callback_method_impl{FNSSMINTLOADEXEC}
2638	*/
2639	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2640	{
2641	int rc; /* Only for AssertRCReturn use. */
2642
2643	/*
2644	* Validate version.
2645	*/
2646	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2647	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2648	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2649	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2650	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2651	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2652	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2653	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2654	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2655	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2656	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2657	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2658	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2659	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2660	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2661	{
2662	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2663	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2664	}
2665
2666	if (uPass == SSM_PASS_FINAL)
2667	{
2668	/*
2669	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2670	* really old SSM file versions.)
2671	*/
2672	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2673	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2674	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2675	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2676
2677	/*
2678	* Figure x86 and ctx field definitions to use for older states.
2679	*/
2680	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2681	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2682	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2683	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2684	{
2685	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2686	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2687	}
2688	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2689	{
2690	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2691	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2692	}
2693
2694	/*
2695	* The hyper state used to preceed the CPU count. Starting with
2696	* XSAVE it was moved down till after we've got the count.
2697	*/
2698	CPUMCTX HyperCtxIgnored;
2699	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2700	{
2701	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2702	{
2703	X86FXSTATE Ign;
2704	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2705	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2706	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2707	}
2708	}
2709
2710	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2711	{
2712	uint32_t cCpus;
2713	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2714	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2715	VERR_SSM_UNEXPECTED_DATA);
2716	}
2717	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2718	\|\| pVM->cCpus == 1,
2719	("cCpus=%u\n", pVM->cCpus),
2720	VERR_SSM_UNEXPECTED_DATA);
2721
2722	uint32_t cbMsrs = 0;
2723	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2724	{
2725	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2726	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2727	VERR_SSM_UNEXPECTED_DATA);
2728	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2729	VERR_SSM_UNEXPECTED_DATA);
2730	}
2731
2732	/*
2733	* Do the per-CPU restoring.
2734	*/
2735	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2736	{
2737	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2738	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2739
2740	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2741	{
2742	/*
2743	* The XSAVE saved state layout moved the hyper state down here.
2744	*/
2745	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2746	AssertRCReturn(rc, rc);
2747
2748	/*
2749	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2750	*/
2751	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2752	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2753	AssertRCReturn(rc, rc);
2754
2755	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2756	if (pGstCtx->fXStateMask != 0)
2757	{
2758	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2759	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2760	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2761	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2762	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2763	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2764	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2765	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2766	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2767	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2768	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2769	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2770	}
2771
2772	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2773	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2774	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2775	{
2776	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2777	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2778	VERR_CPUM_INVALID_XCR0);
2779	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2780	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2781	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2782	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2783	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2784	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2785	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2786	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2787	}
2788
2789	/* Check that the XCR1 is zero, as we don't implement it yet. */
2790	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2791
2792	/*
2793	* Restore the individual extended state components we support.
2794	*/
2795	if (pGstCtx->fXStateMask != 0)
2796	{
2797	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2798	0, g_aCpumXSaveHdrFields, NULL);
2799	AssertRCReturn(rc, rc);
2800	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2801	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2802	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2803	VERR_CPUM_INVALID_XSAVE_HDR);
2804	}
2805	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2806	{
2807	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2808	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2809	}
2810	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2811	{
2812	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2813	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2814	}
2815	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2816	{
2817	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2818	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2819	}
2820	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2821	{
2822	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2823	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2824	}
2825	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2826	{
2827	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2828	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2829	}
2830	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2831	{
2832	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2833	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2834	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2835	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2836	}
2837	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2838	{
2839	if (pVM->cpum.s.GuestFeatures.fSvm)
2840	{
2841	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2842	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2843	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2844	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2845	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2846	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2847	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2848	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2849	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2850	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2851	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2852	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2853	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2854	}
2855	}
2856	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2857	{
2858	if (pVM->cpum.s.GuestFeatures.fVmx)
2859	{
2860	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2861	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2862	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2863	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2864	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2865	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2866	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2867	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2868	0, g_aVmxHwvirtVmcs, NULL);
2869	SSMR3GetStructEx(pSSM, pGstCtx->hwvirt.vmx.pShadowVmcsR3, sizeof(VMXVVMCS), 0, g_aVmxHwvirtVmcs, NULL);
2870	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmreadBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2871	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvVmwriteBitmapR3, VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
2872	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pEntryMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2873	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrStoreAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2874	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pExitMsrLoadAreaR3, VMX_V_AUTOMSR_AREA_SIZE);
2875	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2876	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2877	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2878	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2879	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2880	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2881	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2882	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2883	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2884	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2885	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2886	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2887	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2888	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2889	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2890	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2891	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2892	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2893	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2894	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2895	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2896	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2897	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2898	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2899	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2900	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2901	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2902	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2903	}
2904	}
2905	}
2906	else
2907	{
2908	/*
2909	* Pre XSAVE saved state.
2910	*/
2911	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2912	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2913	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2914	}
2915
2916	/*
2917	* Restore a couple of flags and the MSRs.
2918	*/
2919	uint32_t fIgnoredUsedFlags = 0;
2920	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2921	AssertRCReturn(rc, rc);
2922	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2923
2924	rc = VINF_SUCCESS;
2925	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2926	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2927	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2928	{
2929	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2930	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2931	}
2932	AssertRCReturn(rc, rc);
2933
2934	/* REM and other may have cleared must-be-one fields in DR6 and
2935	DR7, fix these. */
2936	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2937	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2938	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2939	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2940	}
2941
2942	/* Older states does not have the internal selector register flags
2943	and valid selector value. Supply those. */
2944	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2945	{
2946	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2947	{
2948	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2949	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2950	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2951	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2952	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2953	if (fValid)
2954	{
2955	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2956	{
2957	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2958	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2959	}
2960
2961	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2962	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2963	}
2964	else
2965	{
2966	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2967	{
2968	paSelReg[iSelReg].fFlags = 0;
2969	paSelReg[iSelReg].ValidSel = 0;
2970	}
2971
2972	/* This might not be 104% correct, but I think it's close
2973	enough for all practical purposes... (REM always loaded
2974	LDTR registers.) */
2975	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2976	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2977	}
2978	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2979	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2980	}
2981	}
2982
2983	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2984	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2985	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2986	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2987	{
2988	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2989	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2990	}
2991
2992	/*
2993	* A quick sanity check.
2994	*/
2995	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2996	{
2997	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2998	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2999	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3000	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3001	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3002	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3003	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3004	}
3005	}
3006
3007	pVM->cpum.s.fPendingRestore = false;
3008
3009	/*
3010	* Guest CPUIDs (and VMX MSR features).
3011	*/
3012	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3013	{
3014	CPUMMSRS GuestMsrs;
3015	RT_ZERO(GuestMsrs);
3016
3017	CPUMFEATURES BaseFeatures;
3018	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3019	if (fVmxGstFeat)
3020	{
3021	/*
3022	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3023	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3024	* here so we can compare them for compatibility after exploding guest features.
3025	*/
3026	BaseFeatures = pVM->cpum.s.GuestFeatures;
3027
3028	/* Use the VMX MSR features from the saved state while exploding guest features. */
3029	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3030	}
3031
3032	/* Load CPUID and explode guest features. */
3033	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3034	if (fVmxGstFeat)
3035	{
3036	/*
3037	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3038	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3039	* VMX features presented to the guest.
3040	*/
3041	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3042	if (!fIsCompat)
3043	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3044	}
3045	return rc;
3046	}
3047	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3048	}
3049
3050
3051	/**
3052	* @callback_method_impl{FNSSMINTLOADDONE}
3053	*/
3054	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3055	{
3056	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3057	return VINF_SUCCESS;
3058
3059	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3060	if (pVM->cpum.s.fPendingRestore)
3061	{
3062	LogRel(("CPUM: Missing state!\n"));
3063	return VERR_INTERNAL_ERROR_2;
3064	}
3065
3066	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3067	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3068	{
3069	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3070
3071	/* Notify PGM of the NXE states in case they've changed. */
3072	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3073
3074	/* During init. this is done in CPUMR3InitCompleted(). */
3075	if (fSupportsLongMode)
3076	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3077
3078	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3079	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3080	}
3081	return VINF_SUCCESS;
3082	}
3083
3084
3085	/**
3086	* Checks if the CPUM state restore is still pending.
3087	*
3088	* @returns true / false.
3089	* @param pVM The cross context VM structure.
3090	*/
3091	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3092	{
3093	return pVM->cpum.s.fPendingRestore;
3094	}
3095
3096
3097	/**
3098	* Formats the EFLAGS value into mnemonics.
3099	*
3100	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3101	* @param efl The EFLAGS value.
3102	*/
3103	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3104	{
3105	/*
3106	* Format the flags.
3107	*/
3108	static const struct
3109	{
3110	const char pszSet; const char pszClear; uint32_t fFlag;
3111	} s_aFlags[] =
3112	{
3113	{ "vip",NULL, X86_EFL_VIP },
3114	{ "vif",NULL, X86_EFL_VIF },
3115	{ "ac", NULL, X86_EFL_AC },
3116	{ "vm", NULL, X86_EFL_VM },
3117	{ "rf", NULL, X86_EFL_RF },
3118	{ "nt", NULL, X86_EFL_NT },
3119	{ "ov", "nv", X86_EFL_OF },
3120	{ "dn", "up", X86_EFL_DF },
3121	{ "ei", "di", X86_EFL_IF },
3122	{ "tf", NULL, X86_EFL_TF },
3123	{ "nt", "pl", X86_EFL_SF },
3124	{ "nz", "zr", X86_EFL_ZF },
3125	{ "ac", "na", X86_EFL_AF },
3126	{ "po", "pe", X86_EFL_PF },
3127	{ "cy", "nc", X86_EFL_CF },
3128	};
3129	char *psz = pszEFlags;
3130	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3131	{
3132	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3133	if (pszAdd)
3134	{
3135	strcpy(psz, pszAdd);
3136	psz += strlen(pszAdd);
3137	*psz++ = ' ';
3138	}
3139	}
3140	psz[-1] = '\0';
3141	}
3142
3143
3144	/**
3145	* Formats a full register dump.
3146	*
3147	* @param pVM The cross context VM structure.
3148	* @param pCtx The context to format.
3149	* @param pCtxCore The context core to format.
3150	* @param pHlp Output functions.
3151	* @param enmType The dump type.
3152	* @param pszPrefix Register name prefix.
3153	*/
3154	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3155	const char *pszPrefix)
3156	{
3157	NOREF(pVM);
3158
3159	/*
3160	* Format the EFLAGS.
3161	*/
3162	uint32_t efl = pCtxCore->eflags.u32;
3163	char szEFlags[80];
3164	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3165
3166	/*
3167	* Format the registers.
3168	*/
3169	switch (enmType)
3170	{
3171	case CPUMDUMPTYPE_TERSE:
3172	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3173	pHlp->pfnPrintf(pHlp,
3174	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3175	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3176	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3177	"%sr14=%016RX64 %sr15=%016RX64\n"
3178	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3179	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3180	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3181	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3182	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3183	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3184	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3185	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3186	else
3187	pHlp->pfnPrintf(pHlp,
3188	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3189	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3190	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3191	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3192	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3193	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3194	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3195	break;
3196
3197	case CPUMDUMPTYPE_DEFAULT:
3198	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3199	pHlp->pfnPrintf(pHlp,
3200	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3201	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3202	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3203	"%sr14=%016RX64 %sr15=%016RX64\n"
3204	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3205	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3206	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3207	,
3208	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3209	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3210	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3211	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3212	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3213	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3214	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3215	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3216	else
3217	pHlp->pfnPrintf(pHlp,
3218	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3219	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3220	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3221	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3222	,
3223	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3224	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3225	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3226	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3227	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3228	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3229	break;
3230
3231	case CPUMDUMPTYPE_VERBOSE:
3232	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3233	pHlp->pfnPrintf(pHlp,
3234	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3235	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3236	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3237	"%sr14=%016RX64 %sr15=%016RX64\n"
3238	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3239	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3240	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3241	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3242	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3243	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3244	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3245	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3246	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3247	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3248	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3249	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3250	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3251	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3252	,
3253	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3254	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3255	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3256	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3257	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3258	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3259	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3260	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3261	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3262	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3263	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3264	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3265	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3266	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3267	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3268	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3269	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3270	else
3271	pHlp->pfnPrintf(pHlp,
3272	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3273	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3274	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3275	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3276	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3277	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3278	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3279	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3280	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3281	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3282	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3283	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3284	,
3285	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3286	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3287	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3288	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3289	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3290	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3291	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3292	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3293	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3294	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3295	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3296	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3297
3298	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3299	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3300	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3301	{
3302	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3303	pHlp->pfnPrintf(pHlp,
3304	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3305	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3306	,
3307	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3308	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3309	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3310	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3311	);
3312	/*
3313	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3314	* not (FP)R0-7 as Intel SDM suggests.
3315	*/
3316	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3317	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3318	{
3319	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3320	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3321	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3322	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3323	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3324	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3325	iExponent -= 16383; /* subtract bias */
3326	/** @todo This isn't entirenly correct and needs more work! */
3327	pHlp->pfnPrintf(pHlp,
3328	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3329	pszPrefix, iST, pszPrefix, iFPR,
3330	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3331	uTag, chSign, iInteger, u64Fraction, iExponent);
3332	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3333	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3334	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3335	else
3336	pHlp->pfnPrintf(pHlp, "\n");
3337	}
3338
3339	/* XMM/YMM/ZMM registers. */
3340	if (pCtx->fXStateMask & XSAVE_C_YMM)
3341	{
3342	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3343	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3344	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3345	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3346	pszPrefix, i, i < 10 ? " " : "",
3347	pYmmHiCtx->aYmmHi[i].au32[3],
3348	pYmmHiCtx->aYmmHi[i].au32[2],
3349	pYmmHiCtx->aYmmHi[i].au32[1],
3350	pYmmHiCtx->aYmmHi[i].au32[0],
3351	pFpuCtx->aXMM[i].au32[3],
3352	pFpuCtx->aXMM[i].au32[2],
3353	pFpuCtx->aXMM[i].au32[1],
3354	pFpuCtx->aXMM[i].au32[0]);
3355	else
3356	{
3357	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3358	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3359	pHlp->pfnPrintf(pHlp,
3360	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3361	pszPrefix, i, i < 10 ? " " : "",
3362	pZmmHi256->aHi256Regs[i].au32[7],
3363	pZmmHi256->aHi256Regs[i].au32[6],
3364	pZmmHi256->aHi256Regs[i].au32[5],
3365	pZmmHi256->aHi256Regs[i].au32[4],
3366	pZmmHi256->aHi256Regs[i].au32[3],
3367	pZmmHi256->aHi256Regs[i].au32[2],
3368	pZmmHi256->aHi256Regs[i].au32[1],
3369	pZmmHi256->aHi256Regs[i].au32[0],
3370	pYmmHiCtx->aYmmHi[i].au32[3],
3371	pYmmHiCtx->aYmmHi[i].au32[2],
3372	pYmmHiCtx->aYmmHi[i].au32[1],
3373	pYmmHiCtx->aYmmHi[i].au32[0],
3374	pFpuCtx->aXMM[i].au32[3],
3375	pFpuCtx->aXMM[i].au32[2],
3376	pFpuCtx->aXMM[i].au32[1],
3377	pFpuCtx->aXMM[i].au32[0]);
3378
3379	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3380	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3381	pHlp->pfnPrintf(pHlp,
3382	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3383	pszPrefix, i + 16,
3384	pZmm16Hi->aRegs[i].au32[15],
3385	pZmm16Hi->aRegs[i].au32[14],
3386	pZmm16Hi->aRegs[i].au32[13],
3387	pZmm16Hi->aRegs[i].au32[12],
3388	pZmm16Hi->aRegs[i].au32[11],
3389	pZmm16Hi->aRegs[i].au32[10],
3390	pZmm16Hi->aRegs[i].au32[9],
3391	pZmm16Hi->aRegs[i].au32[8],
3392	pZmm16Hi->aRegs[i].au32[7],
3393	pZmm16Hi->aRegs[i].au32[6],
3394	pZmm16Hi->aRegs[i].au32[5],
3395	pZmm16Hi->aRegs[i].au32[4],
3396	pZmm16Hi->aRegs[i].au32[3],
3397	pZmm16Hi->aRegs[i].au32[2],
3398	pZmm16Hi->aRegs[i].au32[1],
3399	pZmm16Hi->aRegs[i].au32[0]);
3400	}
3401	}
3402	else
3403	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3404	pHlp->pfnPrintf(pHlp,
3405	i & 1
3406	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3407	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3408	pszPrefix, i, i < 10 ? " " : "",
3409	pFpuCtx->aXMM[i].au32[3],
3410	pFpuCtx->aXMM[i].au32[2],
3411	pFpuCtx->aXMM[i].au32[1],
3412	pFpuCtx->aXMM[i].au32[0]);
3413
3414	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3415	{
3416	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3417	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3418	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3419	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3420	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3421	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3422	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3423	}
3424
3425	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3426	{
3427	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3428	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3429	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3430	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3431	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3432	}
3433
3434	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3435	{
3436	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3437	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3438	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3439	}
3440
3441	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3442	if (pFpuCtx->au32RsrvdRest[i])
3443	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3444	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3445	}
3446
3447	pHlp->pfnPrintf(pHlp,
3448	"%sEFER =%016RX64\n"
3449	"%sPAT =%016RX64\n"
3450	"%sSTAR =%016RX64\n"
3451	"%sCSTAR =%016RX64\n"
3452	"%sLSTAR =%016RX64\n"
3453	"%sSFMASK =%016RX64\n"
3454	"%sKERNELGSBASE =%016RX64\n",
3455	pszPrefix, pCtx->msrEFER,
3456	pszPrefix, pCtx->msrPAT,
3457	pszPrefix, pCtx->msrSTAR,
3458	pszPrefix, pCtx->msrCSTAR,
3459	pszPrefix, pCtx->msrLSTAR,
3460	pszPrefix, pCtx->msrSFMASK,
3461	pszPrefix, pCtx->msrKERNELGSBASE);
3462
3463	if (CPUMIsGuestInPAEModeEx(pCtx))
3464	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3465	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3466	break;
3467	}
3468	}
3469
3470
3471	/**
3472	* Display all cpu states and any other cpum info.
3473	*
3474	* @param pVM The cross context VM structure.
3475	* @param pHlp The info helper functions.
3476	* @param pszArgs Arguments, ignored.
3477	*/
3478	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3479	{
3480	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3481	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3482	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3483	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3484	cpumR3InfoHost(pVM, pHlp, pszArgs);
3485	}
3486
3487
3488	/**
3489	* Parses the info argument.
3490	*
3491	* The argument starts with 'verbose', 'terse' or 'default' and then
3492	* continues with the comment string.
3493	*
3494	* @param pszArgs The pointer to the argument string.
3495	* @param penmType Where to store the dump type request.
3496	* @param ppszComment Where to store the pointer to the comment string.
3497	*/
3498	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3499	{
3500	if (!pszArgs)
3501	{
3502	*penmType = CPUMDUMPTYPE_DEFAULT;
3503	*ppszComment = "";
3504	}
3505	else
3506	{
3507	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3508	{
3509	pszArgs += 7;
3510	*penmType = CPUMDUMPTYPE_VERBOSE;
3511	}
3512	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3513	{
3514	pszArgs += 5;
3515	*penmType = CPUMDUMPTYPE_TERSE;
3516	}
3517	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3518	{
3519	pszArgs += 7;
3520	*penmType = CPUMDUMPTYPE_DEFAULT;
3521	}
3522	else
3523	*penmType = CPUMDUMPTYPE_DEFAULT;
3524	*ppszComment = RTStrStripL(pszArgs);
3525	}
3526	}
3527
3528
3529	/**
3530	* Display the guest cpu state.
3531	*
3532	* @param pVM The cross context VM structure.
3533	* @param pHlp The info helper functions.
3534	* @param pszArgs Arguments.
3535	*/
3536	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3537	{
3538	CPUMDUMPTYPE enmType;
3539	const char *pszComment;
3540	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3541
3542	PVMCPU pVCpu = VMMGetCpu(pVM);
3543	if (!pVCpu)
3544	pVCpu = pVM->apCpusR3[0];
3545
3546	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3547
3548	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3549	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3550	}
3551
3552
3553	/**
3554	* Displays an SVM VMCB control area.
3555	*
3556	* @param pHlp The info helper functions.
3557	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3558	* @param pszPrefix Caller specified string prefix.
3559	*/
3560	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3561	{
3562	AssertReturnVoid(pHlp);
3563	AssertReturnVoid(pVmcbCtrl);
3564
3565	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3566	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3567	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3568	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3569	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3570	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3571	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3572	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3573	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3574	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3575	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3576	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3577	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3578	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3579	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3580	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3581	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3582	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3583	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3584	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3585	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3586	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3587	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3588	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3589	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3590	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3591	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3592	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3593	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3594	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3595	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3596	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3597	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3598	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3599	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3600	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3601	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3602	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3603	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3604	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3605	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3606	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3607	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3608	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3609	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3610	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3611	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3612	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3613	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3614	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3615	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3616	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3617	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3618	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3619	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3620	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3621	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3622	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3623	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3624	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3625	}
3626
3627
3628	/**
3629	* Helper for dumping the SVM VMCB selector registers.
3630	*
3631	* @param pHlp The info helper functions.
3632	* @param pSel Pointer to the SVM selector register.
3633	* @param pszName Name of the selector.
3634	* @param pszPrefix Caller specified string prefix.
3635	*/
3636	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3637	{
3638	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3639	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3640	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3641	}
3642
3643
3644	/**
3645	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3646	*
3647	* @param pHlp The info helper functions.
3648	* @param pXdtr Pointer to the descriptor table register.
3649	* @param pszName Name of the descriptor table register.
3650	* @param pszPrefix Caller specified string prefix.
3651	*/
3652	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3653	{
3654	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3655	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3656	}
3657
3658
3659	/**
3660	* Displays an SVM VMCB state-save area.
3661	*
3662	* @param pHlp The info helper functions.
3663	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3664	* @param pszPrefix Caller specified string prefix.
3665	*/
3666	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3667	{
3668	AssertReturnVoid(pHlp);
3669	AssertReturnVoid(pVmcbStateSave);
3670
3671	char szEFlags[80];
3672	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3673
3674	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3675	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3676	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3677	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3678	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3679	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3680	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3681	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3682	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3683	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3684	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3685	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3686	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3687	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3688	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3689	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3690	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3691	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3692	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3693	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3694	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3695	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3696	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3697	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3698	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3699	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3700	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3701	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3702	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3703	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3704	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3705	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3706	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3707	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3708	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3709	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3710	}
3711
3712
3713	/**
3714	* Displays a virtual-VMCS.
3715	*
3716	* @param pVCpu The cross context virtual CPU structure.
3717	* @param pHlp The info helper functions.
3718	* @param pVmcs Pointer to a virtual VMCS.
3719	* @param pszPrefix Caller specified string prefix.
3720	*/
3721	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3722	{
3723	AssertReturnVoid(pHlp);
3724	AssertReturnVoid(pVmcs);
3725
3726	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3727	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3728	do { \
3729	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3730	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3731	} while (0)
3732
3733	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3734	do { \
3735	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3736	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3737	} while (0)
3738
3739	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3740	do { \
3741	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3742	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3743	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3744	} while (0)
3745
3746	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3747	do { \
3748	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3749	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3750	} while (0)
3751
3752	/* Header. */
3753	{
3754	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3755	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3756	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3757	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3758	}
3759
3760	/* Control fields. */
3761	{
3762	/* 16-bit. */
3763	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3764	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3765	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3766	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3767
3768	/* 32-bit. */
3769	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3770	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3771	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3772	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3773	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3774	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3775	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3776	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3777	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3778	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3779	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3780	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3781	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3782	{
3783	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3784	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3785	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3786	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3787	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3788	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3789	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3790	}
3791	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3792	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3793	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3794	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3795	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3796
3797	/* 64-bit. */
3798	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3799	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3800	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3801	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3802	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3803	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3804	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3805	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3806	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3807	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3808	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3809	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3810	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3811	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3812	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3813	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3814	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3815	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3816	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3817	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3818	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3819	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3820	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3821	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3822	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3823	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3824	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3825	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3826
3827	/* Natural width. */
3828	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3829	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3830	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3831	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3832	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3833	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3834	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3835	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3836	}
3837
3838	/* Guest state. */
3839	{
3840	char szEFlags[80];
3841	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3842	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3843
3844	/* 16-bit. */
3845	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3846	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3847	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3848	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3849	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3850	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3851	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3852	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3853	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3854	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3855	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3856	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3857
3858	/* 32-bit. */
3859	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3860	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3861	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3862	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3863	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3864
3865	/* 64-bit. */
3866	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3867	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3868	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3869	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3870	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3871	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3872	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3873	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3874	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3875	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3876	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3877	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3878
3879	/* Natural width. */
3880	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3881	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3882	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3883	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3884	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3885	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3886	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3887	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3888	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3889	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3890	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3891	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3892	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3893	}
3894
3895	/* Host state. */
3896	{
3897	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3898
3899	/* 16-bit. */
3900	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3901	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3902	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3903	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3904	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3905	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3906	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3907	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3908	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3909
3910	/* 32-bit. */
3911	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3912
3913	/* 64-bit. */
3914	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3915	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3916	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3917	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3918
3919	/* Natural width. */
3920	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3921	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3922	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3923	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3924	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3925	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3926	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3927	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3928	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3929	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3930
3931	}
3932
3933	/* Read-only fields. */
3934	{
3935	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3936
3937	/* 16-bit (none currently). */
3938
3939	/* 32-bit. */
3940	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3941	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3942	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3943	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3944	{
3945	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3946	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3947	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3948	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3949	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3950	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3951	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3952	}
3953	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3954	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3955	{
3956	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3957	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3958	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3959	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3960	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3961	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3962	}
3963	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3964	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3965	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3966
3967	/* 64-bit. */
3968	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3969
3970	/* Natural width. */
3971	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3972	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3973	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3974	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3975	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3976	}
3977
3978	#ifdef DEBUG_ramshankar
3979	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3980	{
3981	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3982	Assert(pvPage);
3983	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3984	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3985	if (RT_SUCCESS(rc))
3986	{
3987	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3988	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3989	pHlp->pfnPrintf(pHlp, "\n");
3990	}
3991	RTMemTmpFree(pvPage);
3992	}
3993	#else
3994	NOREF(pVCpu);
3995	#endif
3996
3997	#undef CPUMVMX_DUMP_HOST_XDTR
3998	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3999	#undef CPUMVMX_DUMP_GUEST_SEGREG
4000	#undef CPUMVMX_DUMP_GUEST_XDTR
4001	}
4002
4003
4004	/**
4005	* Display the guest's hardware-virtualization cpu state.
4006	*
4007	* @param pVM The cross context VM structure.
4008	* @param pHlp The info helper functions.
4009	* @param pszArgs Arguments, ignored.
4010	*/
4011	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4012	{
4013	RT_NOREF(pszArgs);
4014
4015	PVMCPU pVCpu = VMMGetCpu(pVM);
4016	if (!pVCpu)
4017	pVCpu = pVM->apCpusR3[0];
4018
4019	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4020	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4021	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4022
4023	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4024	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
4025	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4026
4027	if (fSvm)
4028	{
4029	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4030	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4031
4032	char szEFlags[80];
4033	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4034	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4035	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4036	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4037	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4038	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4039	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4040	pHlp->pfnPrintf(pHlp, " HostState:\n");
4041	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4042	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4043	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4044	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4045	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4046	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4047	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4048	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4049	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4050	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4051	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4052	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4053	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4054	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4055	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4056	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4057	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4058	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4059	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4060	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4061	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4062	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4063	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4064	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4065	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4066	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4067	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4068	}
4069	else if (fVmx)
4070	{
4071	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4072	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4073	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4074	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4075	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4076	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4077	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4078	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4079	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4080	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4081	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4082	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4083	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4084	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4085	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4086	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4087	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4088	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4089	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4090	}
4091	else
4092	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4093
4094	#undef CPUMHWVIRTDUMP_NONE
4095	#undef CPUMHWVIRTDUMP_COMMON
4096	#undef CPUMHWVIRTDUMP_SVM
4097	#undef CPUMHWVIRTDUMP_VMX
4098	#undef CPUMHWVIRTDUMP_LAST
4099	#undef CPUMHWVIRTDUMP_ALL
4100	}
4101
4102	/**
4103	* Display the current guest instruction
4104	*
4105	* @param pVM The cross context VM structure.
4106	* @param pHlp The info helper functions.
4107	* @param pszArgs Arguments, ignored.
4108	*/
4109	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4110	{
4111	NOREF(pszArgs);
4112
4113	PVMCPU pVCpu = VMMGetCpu(pVM);
4114	if (!pVCpu)
4115	pVCpu = pVM->apCpusR3[0];
4116
4117	char szInstruction[256];
4118	szInstruction[0] = '\0';
4119	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4120	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4121	}
4122
4123
4124	/**
4125	* Display the hypervisor cpu state.
4126	*
4127	* @param pVM The cross context VM structure.
4128	* @param pHlp The info helper functions.
4129	* @param pszArgs Arguments, ignored.
4130	*/
4131	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4132	{
4133	PVMCPU pVCpu = VMMGetCpu(pVM);
4134	if (!pVCpu)
4135	pVCpu = pVM->apCpusR3[0];
4136
4137	CPUMDUMPTYPE enmType;
4138	const char *pszComment;
4139	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4140	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4141
4142	pHlp->pfnPrintf(pHlp,
4143	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4144	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4145	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4146	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4147	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4148	}
4149
4150
4151	/**
4152	* Display the host cpu state.
4153	*
4154	* @param pVM The cross context VM structure.
4155	* @param pHlp The info helper functions.
4156	* @param pszArgs Arguments, ignored.
4157	*/
4158	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4159	{
4160	CPUMDUMPTYPE enmType;
4161	const char *pszComment;
4162	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4163	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4164
4165	PVMCPU pVCpu = VMMGetCpu(pVM);
4166	if (!pVCpu)
4167	pVCpu = pVM->apCpusR3[0];
4168	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4169
4170	/*
4171	* Format the EFLAGS.
4172	*/
4173	uint64_t efl = pCtx->rflags;
4174	char szEFlags[80];
4175	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4176
4177	/*
4178	* Format the registers.
4179	*/
4180	pHlp->pfnPrintf(pHlp,
4181	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4182	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4183	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4184	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4185	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4186	"r14=%016RX64 r15=%016RX64\n"
4187	"iopl=%d %31s\n"
4188	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4189	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4190	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4191	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4192	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4193	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4194	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4195	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4196	,
4197	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4198	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4199	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4200	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4201	pCtx->r11, pCtx->r12, pCtx->r13,
4202	pCtx->r14, pCtx->r15,
4203	X86_EFL_GET_IOPL(efl), szEFlags,
4204	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4205	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4206	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4207	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4208	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4209	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4210	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4211	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4212	}
4213
4214	/**
4215	* Structure used when disassembling and instructions in DBGF.
4216	* This is used so the reader function can get the stuff it needs.
4217	*/
4218	typedef struct CPUMDISASSTATE
4219	{
4220	/** Pointer to the CPU structure. */
4221	PDISCPUSTATE pCpu;
4222	/** Pointer to the VM. */
4223	PVM pVM;
4224	/** Pointer to the VMCPU. */
4225	PVMCPU pVCpu;
4226	/** Pointer to the first byte in the segment. */
4227	RTGCUINTPTR GCPtrSegBase;
4228	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4229	RTGCUINTPTR GCPtrSegEnd;
4230	/** The size of the segment minus 1. */
4231	RTGCUINTPTR cbSegLimit;
4232	/** Pointer to the current page - R3 Ptr. */
4233	void const *pvPageR3;
4234	/** Pointer to the current page - GC Ptr. */
4235	RTGCPTR pvPageGC;
4236	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4237	PGMPAGEMAPLOCK PageMapLock;
4238	/** Whether the PageMapLock is valid or not. */
4239	bool fLocked;
4240	/** 64 bits mode or not. */
4241	bool f64Bits;
4242	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4243
4244
4245	/**
4246	* @callback_method_impl{FNDISREADBYTES}
4247	*/
4248	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4249	{
4250	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4251	for (;;)
4252	{
4253	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4254
4255	/*
4256	* Need to update the page translation?
4257	*/
4258	if ( !pState->pvPageR3
4259	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4260	{
4261	/* translate the address */
4262	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4263
4264	/* Release mapping lock previously acquired. */
4265	if (pState->fLocked)
4266	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4267	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4268	if (RT_SUCCESS(rc))
4269	pState->fLocked = true;
4270	else
4271	{
4272	pState->fLocked = false;
4273	pState->pvPageR3 = NULL;
4274	return rc;
4275	}
4276	}
4277
4278	/*
4279	* Check the segment limit.
4280	*/
4281	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4282	return VERR_OUT_OF_SELECTOR_BOUNDS;
4283
4284	/*
4285	* Calc how much we can read.
4286	*/
4287	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4288	if (!pState->f64Bits)
4289	{
4290	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4291	if (cb > cbSeg && cbSeg)
4292	cb = cbSeg;
4293	}
4294	if (cb > cbMaxRead)
4295	cb = cbMaxRead;
4296
4297	/*
4298	* Read and advance or exit.
4299	*/
4300	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4301	offInstr += (uint8_t)cb;
4302	if (cb >= cbMinRead)
4303	{
4304	pDis->cbCachedInstr = offInstr;
4305	return VINF_SUCCESS;
4306	}
4307	cbMinRead -= (uint8_t)cb;
4308	cbMaxRead -= (uint8_t)cb;
4309	}
4310	}
4311
4312
4313	/**
4314	* Disassemble an instruction and return the information in the provided structure.
4315	*
4316	* @returns VBox status code.
4317	* @param pVM The cross context VM structure.
4318	* @param pVCpu The cross context virtual CPU structure.
4319	* @param pCtx Pointer to the guest CPU context.
4320	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4321	* @param pCpu Disassembly state.
4322	* @param pszPrefix String prefix for logging (debug only).
4323	*
4324	*/
4325	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4326	const char *pszPrefix)
4327	{
4328	CPUMDISASSTATE State;
4329	int rc;
4330
4331	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4332	State.pCpu = pCpu;
4333	State.pvPageGC = 0;
4334	State.pvPageR3 = NULL;
4335	State.pVM = pVM;
4336	State.pVCpu = pVCpu;
4337	State.fLocked = false;
4338	State.f64Bits = false;
4339
4340	/*
4341	* Get selector information.
4342	*/
4343	DISCPUMODE enmDisCpuMode;
4344	if ( (pCtx->cr0 & X86_CR0_PE)
4345	&& pCtx->eflags.Bits.u1VM == 0)
4346	{
4347	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4348	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4349	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4350	State.GCPtrSegBase = pCtx->cs.u64Base;
4351	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4352	State.cbSegLimit = pCtx->cs.u32Limit;
4353	enmDisCpuMode = (State.f64Bits)
4354	? DISCPUMODE_64BIT
4355	: pCtx->cs.Attr.n.u1DefBig
4356	? DISCPUMODE_32BIT
4357	: DISCPUMODE_16BIT;
4358	}
4359	else
4360	{
4361	/* real or V86 mode */
4362	enmDisCpuMode = DISCPUMODE_16BIT;
4363	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4364	State.GCPtrSegEnd = 0xFFFFFFFF;
4365	State.cbSegLimit = 0xFFFFFFFF;
4366	}
4367
4368	/*
4369	* Disassemble the instruction.
4370	*/
4371	uint32_t cbInstr;
4372	#ifndef LOG_ENABLED
4373	RT_NOREF_PV(pszPrefix);
4374	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4375	if (RT_SUCCESS(rc))
4376	{
4377	#else
4378	char szOutput[160];
4379	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4380	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4381	if (RT_SUCCESS(rc))
4382	{
4383	/* log it */
4384	if (pszPrefix)
4385	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4386	else
4387	Log(("%s", szOutput));
4388	#endif
4389	rc = VINF_SUCCESS;
4390	}
4391	else
4392	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4393
4394	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4395	if (State.fLocked)
4396	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4397
4398	return rc;
4399	}
4400
4401
4402
4403	/**
4404	* API for controlling a few of the CPU features found in CR4.
4405	*
4406	* Currently only X86_CR4_TSD is accepted as input.
4407	*
4408	* @returns VBox status code.
4409	*
4410	* @param pVM The cross context VM structure.
4411	* @param fOr The CR4 OR mask.
4412	* @param fAnd The CR4 AND mask.
4413	*/
4414	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4415	{
4416	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4417	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4418
4419	pVM->cpum.s.CR4.OrMask &= fAnd;
4420	pVM->cpum.s.CR4.OrMask \|= fOr;
4421
4422	return VINF_SUCCESS;
4423	}
4424
4425
4426	/**
4427	* Called when the ring-3 init phase completes.
4428	*
4429	* @returns VBox status code.
4430	* @param pVM The cross context VM structure.
4431	* @param enmWhat Which init phase.
4432	*/
4433	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4434	{
4435	switch (enmWhat)
4436	{
4437	case VMINITCOMPLETED_RING3:
4438	{
4439	/*
4440	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4441	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4442	*/
4443	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4444	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4445	{
4446	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4447
4448	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4449	if (fSupportsLongMode)
4450	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4451	}
4452
4453	/* Register statistic counters for MSRs. */
4454	cpumR3MsrRegStats(pVM);
4455
4456	/* Create VMX-preemption timer for nested guests if required. Must be
4457	done here as CPUM is initialized before TM. */
4458	if (pVM->cpum.s.GuestFeatures.fVmx)
4459	{
4460	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4461	{
4462	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4463	char szName[32];
4464	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4465	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4466	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4467	AssertLogRelRCReturn(rc, rc);
4468	}
4469	}
4470	break;
4471	}
4472
4473	default:
4474	break;
4475	}
4476	return VINF_SUCCESS;
4477	}
4478
4479
4480	/**
4481	* Called when the ring-0 init phases completed.
4482	*
4483	* @param pVM The cross context VM structure.
4484	*/
4485	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4486	{
4487	/*
4488	* Enable log buffering as we're going to log a lot of lines.
4489	*/
4490	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4491
4492	/*
4493	* Log the cpuid.
4494	*/
4495	RTCPUSET OnlineSet;
4496	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4497	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4498	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4499	RTCPUID cCores = RTMpGetCoreCount();
4500	if (cCores)
4501	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4502	LogRel(("*********************** CPUID dump **********************\n"));
4503	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4504	LogRel(("\n"));
4505	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4506	LogRel(("****************** End of CPUID dump ********************\n"));
4507
4508	/*
4509	* Log VT-x extended features.
4510	*
4511	* SVM features are currently all covered under CPUID so there is nothing
4512	* to do here for SVM.
4513	*/
4514	if (pVM->cpum.s.HostFeatures.fVmx)
4515	{
4516	LogRel(("********************* VT-x features *********************\n"));
4517	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4518	LogRel(("\n"));
4519	LogRel(("***************** End of VT-x features ******************\n"));
4520	}
4521
4522	/*
4523	* Restore the log buffering state to what it was previously.
4524	*/
4525	RTLogRelSetBuffering(fOldBuffered);
4526	}
4527

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 91297

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