CPUM.cpp@ 91301

Last change on this file since 91301 was 91301, checked in by vboxsync, 4 years ago
VMM/CPUM,++: Moved the nested VT-X MSR load & store bitmap allocations into CPUMCTX. bugref:10093
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File size: 237.1 KB

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1	/* $Id: CPUM.cpp 91301 2021-09-17 13:38:24Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/hm.h>
120	#include <VBox/vmm/hmvmxinline.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
339
340	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
341	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
342	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
343	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
344	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
345	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
346	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
347	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
348	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
349
350	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
351	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
352
353	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
354	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
355	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
356	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
357	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
358	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
360
361	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
362	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
363	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
364	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
365
366	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
367	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
369	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
370	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
371	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
373	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
374	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
378	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
379	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
380	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
381	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
382	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
383	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
384	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
385
386	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
387	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
388	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
389	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
390	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
391	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
392	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
393	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
394	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
395	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
396	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
397	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
398	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
399	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
400	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
401	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
402	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
403	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
404	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
405	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
406	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
407	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
408	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
409	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
410	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
411	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
412	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
413	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
414	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
415
416	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
417	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
418	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
419	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
420	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
421	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
422	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
423	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
424	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
425
426	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
427	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
428	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
429	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
430	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
431	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
432	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
433	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
434
435	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
436	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
437
438	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
439	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
440	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
441	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
442	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
443
444	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
445	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
446	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
447	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
448	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
449	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
450	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
451	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
452	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
453	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
454	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
455	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
456	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
457	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
458	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
459	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
460
461	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
462	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
463	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
464	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
465	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
466	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
467	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
468	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
469	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
470	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
471	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
472
473	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
474	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
475	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
476	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
477	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
478	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
479	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
480	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
481	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
482	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
483	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
484	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
485	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
486	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
487	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
488	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
489	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
490	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
491	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
492	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
493	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
494	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
495	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
496	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
497
498	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
503	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
504	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
509	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
510	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
511
512	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
513	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
514	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
515	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
519	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
520	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
521	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
532	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
533	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
534	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
535	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
536
537	SSMFIELD_ENTRY_TERM()
538	};
539
540	/** Saved state field descriptors for CPUMCTX. */
541	static const SSMFIELD g_aCpumX87Fields[] =
542	{
543	SSMFIELD_ENTRY( X86FXSTATE, FCW),
544	SSMFIELD_ENTRY( X86FXSTATE, FSW),
545	SSMFIELD_ENTRY( X86FXSTATE, FTW),
546	SSMFIELD_ENTRY( X86FXSTATE, FOP),
547	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
548	SSMFIELD_ENTRY( X86FXSTATE, CS),
549	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
550	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
551	SSMFIELD_ENTRY( X86FXSTATE, DS),
552	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
553	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
554	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
555	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
556	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
557	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
558	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
559	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
560	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
561	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
562	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
564	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
565	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
566	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
567	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
568	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
569	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
570	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
571	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
572	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
573	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
574	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
575	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
576	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
577	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
578	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
579	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
580	SSMFIELD_ENTRY_TERM()
581	};
582
583	/** Saved state field descriptors for X86XSAVEHDR. */
584	static const SSMFIELD g_aCpumXSaveHdrFields[] =
585	{
586	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
587	SSMFIELD_ENTRY_TERM()
588	};
589
590	/** Saved state field descriptors for X86XSAVEYMMHI. */
591	static const SSMFIELD g_aCpumYmmHiFields[] =
592	{
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
594	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
595	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
596	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
597	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
598	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
599	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
600	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
601	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
602	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
603	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
604	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
605	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
606	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
607	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
608	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
609	SSMFIELD_ENTRY_TERM()
610	};
611
612	/** Saved state field descriptors for X86XSAVEBNDREGS. */
613	static const SSMFIELD g_aCpumBndRegsFields[] =
614	{
615	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
616	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
617	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
618	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
619	SSMFIELD_ENTRY_TERM()
620	};
621
622	/** Saved state field descriptors for X86XSAVEBNDCFG. */
623	static const SSMFIELD g_aCpumBndCfgFields[] =
624	{
625	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
626	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
627	SSMFIELD_ENTRY_TERM()
628	};
629
630	#if 0 /** @todo */
631	/** Saved state field descriptors for X86XSAVEOPMASK. */
632	static const SSMFIELD g_aCpumOpmaskFields[] =
633	{
634	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
635	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
636	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
637	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
638	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
639	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
640	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
641	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
642	SSMFIELD_ENTRY_TERM()
643	};
644	#endif
645
646	/** Saved state field descriptors for X86XSAVEZMMHI256. */
647	static const SSMFIELD g_aCpumZmmHi256Fields[] =
648	{
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
650	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
651	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
652	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
653	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
654	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
655	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
656	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
657	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
658	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
659	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
660	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
661	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
662	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
663	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
664	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
665	SSMFIELD_ENTRY_TERM()
666	};
667
668	/** Saved state field descriptors for X86XSAVEZMM16HI. */
669	static const SSMFIELD g_aCpumZmm16HiFields[] =
670	{
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
672	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
673	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
674	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
675	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
676	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
677	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
678	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
679	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
680	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
681	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
682	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
683	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
684	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
685	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
686	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
687	SSMFIELD_ENTRY_TERM()
688	};
689
690
691
692	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
693	* registeres changed. */
694	static const SSMFIELD g_aCpumX87FieldsMem[] =
695	{
696	SSMFIELD_ENTRY( X86FXSTATE, FCW),
697	SSMFIELD_ENTRY( X86FXSTATE, FSW),
698	SSMFIELD_ENTRY( X86FXSTATE, FTW),
699	SSMFIELD_ENTRY( X86FXSTATE, FOP),
700	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
701	SSMFIELD_ENTRY( X86FXSTATE, CS),
702	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
703	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
704	SSMFIELD_ENTRY( X86FXSTATE, DS),
705	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
706	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
707	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
708	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
709	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
710	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
711	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
712	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
713	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
714	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
715	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
717	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
718	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
719	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
720	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
721	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
722	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
723	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
724	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
725	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
726	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
727	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
728	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
729	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
730	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
731	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
732	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
733	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
734	};
735
736	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
737	* registeres changed. */
738	static const SSMFIELD g_aCpumCtxFieldsMem[] =
739	{
740	SSMFIELD_ENTRY( CPUMCTX, rdi),
741	SSMFIELD_ENTRY( CPUMCTX, rsi),
742	SSMFIELD_ENTRY( CPUMCTX, rbp),
743	SSMFIELD_ENTRY( CPUMCTX, rax),
744	SSMFIELD_ENTRY( CPUMCTX, rbx),
745	SSMFIELD_ENTRY( CPUMCTX, rdx),
746	SSMFIELD_ENTRY( CPUMCTX, rcx),
747	SSMFIELD_ENTRY( CPUMCTX, rsp),
748	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
749	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
750	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
751	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
752	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
753	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
754	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
755	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
756	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
757	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
758	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
759	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
760	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
761	SSMFIELD_ENTRY( CPUMCTX, rflags),
762	SSMFIELD_ENTRY( CPUMCTX, rip),
763	SSMFIELD_ENTRY( CPUMCTX, r8),
764	SSMFIELD_ENTRY( CPUMCTX, r9),
765	SSMFIELD_ENTRY( CPUMCTX, r10),
766	SSMFIELD_ENTRY( CPUMCTX, r11),
767	SSMFIELD_ENTRY( CPUMCTX, r12),
768	SSMFIELD_ENTRY( CPUMCTX, r13),
769	SSMFIELD_ENTRY( CPUMCTX, r14),
770	SSMFIELD_ENTRY( CPUMCTX, r15),
771	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
772	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
773	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
774	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
775	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
776	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
777	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
778	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
779	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
780	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
781	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
782	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
783	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
784	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
785	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
786	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
787	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
788	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
789	SSMFIELD_ENTRY( CPUMCTX, cr0),
790	SSMFIELD_ENTRY( CPUMCTX, cr2),
791	SSMFIELD_ENTRY( CPUMCTX, cr3),
792	SSMFIELD_ENTRY( CPUMCTX, cr4),
793	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
794	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
795	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
796	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
797	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
798	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
799	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
800	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
801	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
802	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
803	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
804	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
805	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
806	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
807	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
808	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
809	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
810	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
811	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
812	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
813	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
814	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
815	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
816	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
817	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
818	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
819	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
820	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
821	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
822	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
823	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
824	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
825	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
826	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
827	SSMFIELD_ENTRY_TERM()
828	};
829
830	/** Saved state field descriptors for CPUMCTX_VER1_6. */
831	static const SSMFIELD g_aCpumX87FieldsV16[] =
832	{
833	SSMFIELD_ENTRY( X86FXSTATE, FCW),
834	SSMFIELD_ENTRY( X86FXSTATE, FSW),
835	SSMFIELD_ENTRY( X86FXSTATE, FTW),
836	SSMFIELD_ENTRY( X86FXSTATE, FOP),
837	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
838	SSMFIELD_ENTRY( X86FXSTATE, CS),
839	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
840	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
841	SSMFIELD_ENTRY( X86FXSTATE, DS),
842	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
843	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
844	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
845	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
846	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
847	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
848	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
849	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
850	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
851	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
852	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
854	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
855	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
856	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
857	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
858	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
859	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
860	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
861	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
862	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
863	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
864	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
865	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
866	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
867	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
868	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
869	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
870	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
871	SSMFIELD_ENTRY_TERM()
872	};
873
874	/** Saved state field descriptors for CPUMCTX_VER1_6. */
875	static const SSMFIELD g_aCpumCtxFieldsV16[] =
876	{
877	SSMFIELD_ENTRY( CPUMCTX, rdi),
878	SSMFIELD_ENTRY( CPUMCTX, rsi),
879	SSMFIELD_ENTRY( CPUMCTX, rbp),
880	SSMFIELD_ENTRY( CPUMCTX, rax),
881	SSMFIELD_ENTRY( CPUMCTX, rbx),
882	SSMFIELD_ENTRY( CPUMCTX, rdx),
883	SSMFIELD_ENTRY( CPUMCTX, rcx),
884	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
885	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
886	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
887	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
888	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
889	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
890	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
891	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
892	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
893	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
894	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
895	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
896	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
897	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
898	SSMFIELD_ENTRY( CPUMCTX, rflags),
899	SSMFIELD_ENTRY( CPUMCTX, rip),
900	SSMFIELD_ENTRY( CPUMCTX, r8),
901	SSMFIELD_ENTRY( CPUMCTX, r9),
902	SSMFIELD_ENTRY( CPUMCTX, r10),
903	SSMFIELD_ENTRY( CPUMCTX, r11),
904	SSMFIELD_ENTRY( CPUMCTX, r12),
905	SSMFIELD_ENTRY( CPUMCTX, r13),
906	SSMFIELD_ENTRY( CPUMCTX, r14),
907	SSMFIELD_ENTRY( CPUMCTX, r15),
908	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
909	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
910	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
911	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
912	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
913	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
914	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
915	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
916	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
917	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
918	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
919	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
920	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
921	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
922	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
923	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
924	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
925	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
926	SSMFIELD_ENTRY( CPUMCTX, cr0),
927	SSMFIELD_ENTRY( CPUMCTX, cr2),
928	SSMFIELD_ENTRY( CPUMCTX, cr3),
929	SSMFIELD_ENTRY( CPUMCTX, cr4),
930	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
931	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
932	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
933	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
934	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
935	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
936	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
937	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
938	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
939	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
940	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
941	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
942	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
943	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
944	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
945	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
946	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
947	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
948	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
949	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
950	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
951	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
952	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
953	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
954	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
955	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
956	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
957	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
958	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
959	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
960	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
961	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
962	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
963	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
964	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
965	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
966	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
967	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
968	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
969	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
970	SSMFIELD_ENTRY_TERM()
971	};
972
973
974	/**
975	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
976	*
977	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
978	* (last instruction pointer, last data pointer, last opcode) except when the ES
979	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
980	* clear these registers there is potential, local FPU leakage from a process
981	* using the FPU to another.
982	*
983	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
984	*
985	* @param pVM The cross context VM structure.
986	*/
987	static void cpumR3CheckLeakyFpu(PVM pVM)
988	{
989	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
990	uint32_t const u32Family = u32CpuVersion >> 8;
991	if ( u32Family >= 6 /* K7 and higher */
992	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
993	{
994	uint32_t cExt = ASMCpuId_EAX(0x80000000);
995	if (ASMIsValidExtRange(cExt))
996	{
997	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
998	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
999	{
1000	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1001	{
1002	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1003	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1004	}
1005	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1006	}
1007	}
1008	}
1009	}
1010
1011
1012	/**
1013	* Initialize SVM hardware virtualization state (used to allocate it).
1014	*
1015	* @param pVM The cross context VM structure.
1016	*/
1017	static void cpumR3InitSvmHwVirtState(PVM pVM)
1018	{
1019	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1020
1021	LogRel(("CPUM: Allocating %u pages for the nested-guest SVM MSR and IO permission bitmaps\n",
1022	pVM->cCpus * (SVM_MSRPM_PAGES + SVM_IOPM_PAGES)));
1023	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1024	{
1025	PVMCPU pVCpu = pVM->apCpusR3[i];
1026	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1027
1028	AssertCompile(SVM_VMCB_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.Vmcb));
1029	AssertCompile(SVM_MSRPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abMsrBitmap));
1030	AssertCompile(SVM_IOPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abIoBitmap));
1031	}
1032	}
1033
1034
1035	/**
1036	* Resets per-VCPU SVM hardware virtualization state.
1037	*
1038	* @param pVCpu The cross context virtual CPU structure.
1039	*/
1040	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1041	{
1042	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1043	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1044
1045	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1046	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1047	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1048	}
1049
1050
1051	/**
1052	* Frees memory allocated for the VMX hardware virtualization state.
1053	*
1054	* @param pVM The cross context VM structure.
1055	*/
1056	static void cpumR3FreeVmxHwVirtState(PVM pVM)
1057	{
1058	Assert(pVM->cpum.s.GuestFeatures.fVmx);
1059	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1060	{
1061	PVMCPU pVCpu = pVM->apCpusR3[i];
1062	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1063
1064	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1065	{
1066	SUPR3ContFree(pCtx->hwvirt.vmx.pvVirtApicPageR3, VMX_V_VIRT_APIC_PAGES);
1067	pCtx->hwvirt.vmx.pvVirtApicPageR3 = NULL;
1068	}
1069	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1070	{
1071	SUPR3ContFree(pCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_PAGES);
1072	pCtx->hwvirt.vmx.pvMsrBitmapR3 = NULL;
1073	}
1074	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1075	{
1076	SUPR3ContFree(pCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1077	pCtx->hwvirt.vmx.pvIoBitmapR3 = NULL;
1078	}
1079	}
1080	}
1081
1082
1083	/**
1084	* Allocates memory for the VMX hardware virtualization state.
1085	*
1086	* @returns VBox status code.
1087	* @param pVM The cross context VM structure.
1088	*/
1089	static int cpumR3AllocVmxHwVirtState(PVM pVM)
1090	{
1091	int rc = VINF_SUCCESS;
1092	uint32_t const cPages = VMX_V_VMCS_PAGES
1093	+ VMX_V_SHADOW_VMCS_PAGES
1094	+ VMX_V_VIRT_APIC_PAGES
1095	+ (2 * VMX_V_VMREAD_VMWRITE_BITMAP_PAGES)
1096	+ (3 * VMX_V_AUTOMSR_AREA_PAGES)
1097	+ VMX_V_MSR_BITMAP_PAGES
1098	+ (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES);
1099	LogRel(("CPUM: Allocating %u pages for the nested-guest VMCS and related structures\n", pVM->cCpus * cPages));
1100	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1101	{
1102	PVMCPU pVCpu = pVM->apCpusR3[i];
1103	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1104	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1105
1106	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1107	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1108	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1109	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1110	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1111	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1112	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1113	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1114	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1115	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1116	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1117	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1118	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1119	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1120
1121	/*
1122	* Allocate the virtual-APIC page.
1123	*/
1124	pCtx->hwvirt.vmx.pvVirtApicPageR3 = SUPR3ContAlloc(VMX_V_VIRT_APIC_PAGES,
1125	&pCtx->hwvirt.vmx.pvVirtApicPageR0,
1126	&pCtx->hwvirt.vmx.HCPhysVirtApicPage);
1127	if (pCtx->hwvirt.vmx.pvVirtApicPageR3)
1128	{ /* likely */ }
1129	else
1130	{
1131	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's virtual-APIC page\n", pVCpu->idCpu,
1132	VMX_V_VIRT_APIC_PAGES));
1133	break;
1134	}
1135
1136	/*
1137	* Allocate the MSR bitmap.
1138	*/
1139	pCtx->hwvirt.vmx.pvMsrBitmapR3 = SUPR3ContAlloc(VMX_V_MSR_BITMAP_PAGES, &pCtx->hwvirt.vmx.pvMsrBitmapR0, NULL);
1140	if (pCtx->hwvirt.vmx.pvMsrBitmapR3)
1141	{ /* likely */ }
1142	else
1143	{
1144	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's MSR bitmap\n", pVCpu->idCpu,
1145	VMX_V_MSR_BITMAP_PAGES));
1146	break;
1147	}
1148
1149	/*
1150	* Allocate the I/O bitmaps (A and B).
1151	*/
1152	pCtx->hwvirt.vmx.pvIoBitmapR3 = SUPR3ContAlloc(VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES,
1153	&pCtx->hwvirt.vmx.pvIoBitmapR0, NULL);
1154	if (pCtx->hwvirt.vmx.pvIoBitmapR3)
1155	{ /* likely */ }
1156	else
1157	{
1158	LogRel(("CPUM%u: Failed to alloc %u pages for the nested-guest's I/O bitmaps\n", pVCpu->idCpu,
1159	VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES));
1160	break;
1161	}
1162
1163	/*
1164	* Zero out all allocated pages (should compress well for saved-state).
1165	*/
1166	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1167	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1168	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1169	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1170	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1171	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1172	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1173	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvMsrBitmap), 0, VMX_V_MSR_BITMAP_SIZE);
1174	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvIoBitmap), 0, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1175	memset(pCtx->hwvirt.vmx.CTX_SUFF(pvVirtApicPage), 0, VMX_V_VIRT_APIC_SIZE);
1176	}
1177
1178	/* On any failure, cleanup. */
1179	if (RT_FAILURE(rc))
1180	cpumR3FreeVmxHwVirtState(pVM);
1181
1182	return rc;
1183	}
1184
1185
1186	/**
1187	* Resets per-VCPU VMX hardware virtualization state.
1188	*
1189	* @param pVCpu The cross context virtual CPU structure.
1190	*/
1191	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1192	{
1193	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1194	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1195
1196	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1197	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1198	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1199	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1200	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1201	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1202	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1203	/* Don't reset diagnostics here. */
1204
1205	/* Stop any VMX-preemption timer. */
1206	CPUMStopGuestVmxPremptTimer(pVCpu);
1207
1208	/* Clear all nested-guest FFs. */
1209	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1210	}
1211
1212
1213	/**
1214	* Displays the host and guest VMX features.
1215	*
1216	* @param pVM The cross context VM structure.
1217	* @param pHlp The info helper functions.
1218	* @param pszArgs "terse", "default" or "verbose".
1219	*/
1220	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1221	{
1222	RT_NOREF(pszArgs);
1223	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1224	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1225	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1226	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1227	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1228	{
1229	#define VMXFEATDUMP(a_szDesc, a_Var) \
1230	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1231
1232	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1233	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1234	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1235	/* Basic. */
1236	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1237	/* Pin-based controls. */
1238	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1239	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1240	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1241	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1242	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1243	/* Processor-based controls. */
1244	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1245	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1246	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1247	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1248	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1249	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1250	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1251	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1252	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1253	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1254	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1255	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1256	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1257	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1258	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1259	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1260	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1261	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1262	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1263	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1264	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1265	/* Secondary processor-based controls. */
1266	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1267	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1268	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1269	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1270	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1271	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1272	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1273	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1274	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1275	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1276	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1277	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1278	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1279	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1280	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1281	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1282	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1283	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1284	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1285	/* VM-entry controls. */
1286	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1287	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1288	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1289	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1290	/* VM-exit controls. */
1291	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1292	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1293	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1294	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1295	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1296	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1297	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1298	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1299	/* Miscellaneous data. */
1300	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1301	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1302	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1303	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1304	#undef VMXFEATDUMP
1305	}
1306	else
1307	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1308	}
1309
1310
1311	/**
1312	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1313	* or NEM) is allowed.
1314	*
1315	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1316	* otherwise.
1317	* @param pVM The cross context VM structure.
1318	*/
1319	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1320	{
1321	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1322	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1323	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1324	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1325	return true;
1326	#else
1327	NOREF(pVM);
1328	#endif
1329	return false;
1330	}
1331
1332
1333	/**
1334	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1335	*
1336	* @param pVM The cross context VM structure.
1337	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1338	* and no hardware-assisted nested-guest execution is
1339	* possible for this VM.
1340	* @param pGuestFeatures The guest features to use (only VMX features are
1341	* accessed).
1342	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1343	*
1344	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1345	*/
1346	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1347	{
1348	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1349
1350	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1351	Assert(pGuestFeatures->fVmx);
1352
1353	/*
1354	* We don't support the following MSRs yet:
1355	* - True Pin-based VM-execution controls.
1356	* - True Processor-based VM-execution controls.
1357	* - True VM-entry VM-execution controls.
1358	* - True VM-exit VM-execution controls.
1359	*/
1360
1361	/* Feature control. */
1362	pGuestVmxMsrs->u64FeatCtrl = MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON;
1363
1364	/* Basic information. */
1365	{
1366	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1367	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1368	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1369	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1370	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1371	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1372	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1373	pGuestVmxMsrs->u64Basic = u64Basic;
1374	}
1375
1376	/* Pin-based VM-execution controls. */
1377	{
1378	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1379	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1380	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1381	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1382	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1383	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1384	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1385	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1386	fAllowed0, fAllowed1, fFeatures));
1387	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1388	}
1389
1390	/* Processor-based VM-execution controls. */
1391	{
1392	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1393	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1394	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1395	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1396	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1397	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1398	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1399	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1400	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1401	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1402	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1403	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1404	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1405	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1406	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1407	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1408	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1409	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1410	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1411	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1412	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1413	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1414	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1415	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1416	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1417	fAllowed1, fFeatures));
1418	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1419	}
1420
1421	/* Secondary processor-based VM-execution controls. */
1422	if (pGuestFeatures->fVmxSecondaryExecCtls)
1423	{
1424	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1425	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1426	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1427	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1428	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1429	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1430	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1431	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1432	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1433	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1434	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1435	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1436	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1437	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1438	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1439	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1440	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1441	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1442	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1443	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1444	uint32_t const fAllowed0 = 0;
1445	uint32_t const fAllowed1 = fFeatures;
1446	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1447	}
1448
1449	/* Tertiary processor-based VM-execution controls. */
1450	if (pGuestFeatures->fVmxTertiaryExecCtls)
1451	{
1452	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1453	}
1454
1455	/* VM-exit controls. */
1456	{
1457	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1458	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1459	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1460	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1461	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1462	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1463	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1464	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1465	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1466	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1467	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1468	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1469	fAllowed1, fFeatures));
1470	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1471	}
1472
1473	/* VM-entry controls. */
1474	{
1475	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1476	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1477	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1478	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1479	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1480	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1481	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1482	fAllowed1, fFeatures));
1483	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1484	}
1485
1486	/* Miscellaneous data. */
1487	{
1488	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1489
1490	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1491	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1492	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1493	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1494	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1495	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1496	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1497	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1498	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1499	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1500	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1501	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1502	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1503	}
1504
1505	/* CR0 Fixed-0. */
1506	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1507
1508	/* CR0 Fixed-1. */
1509	{
1510	/*
1511	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1512	* This is different from CR4 fixed-1 bits which are reported as per the
1513	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1514	*/
1515	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1516	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1517	}
1518
1519	/* CR4 Fixed-0. */
1520	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1521
1522	/* CR4 Fixed-1. */
1523	{
1524	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1525	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1526	}
1527
1528	/* VMCS Enumeration. */
1529	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1530
1531	/* VPID and EPT Capabilities. */
1532	if (pGuestFeatures->fVmxEpt)
1533	{
1534	/*
1535	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1536	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1537	* when INVVPID instruction is supported just to be more compatible with guest
1538	* hypervisors that may make assumptions by only looking at this MSR even though they
1539	* are technically supposed to refer to bit 37 of MSR_IA32_VMX_PROC_CTLS2 first.
1540	*
1541	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1542	* See Intel spec. 30.3 "VMX Instructions".
1543	*/
1544	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1545	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1546
1547	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_RWX_X_ONLY);
1548	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1549	uint8_t const fEptMemUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_UC);
1550	uint8_t const fEptMemWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EMT_WB);
1551	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1552	uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G);
1553	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1554	uint8_t const fEptAccDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1555	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1556	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1557	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1558	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1559	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1560	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1561	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_RWX_X_ONLY, fExecOnly)
1562	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1563	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EMT_UC, fEptMemUc)
1564	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EMT_WB, fEptMemWb)
1565	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1566	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage)
1567	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1568	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EPT_ACCESS_DIRTY, fEptAccDirty)
1569	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT, 0)
1570	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1571	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1572	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1573	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1574	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1575	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1576	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1577	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1578	}
1579
1580	/* VM Functions. */
1581	if (pGuestFeatures->fVmxVmFunc)
1582	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1583	}
1584
1585
1586	/**
1587	* Checks whether the given guest CPU VMX features are compatible with the provided
1588	* base features.
1589	*
1590	* @returns @c true if compatible, @c false otherwise.
1591	* @param pVM The cross context VM structure.
1592	* @param pBase The base VMX CPU features.
1593	* @param pGst The guest VMX CPU features.
1594	*
1595	* @remarks Only VMX feature bits are examined.
1596	*/
1597	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1598	{
1599	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1600	return false;
1601
1602	/* Check first set of feature bits. */
1603	{
1604	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1605	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1606	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1607	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1608	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1609	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1610	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1611	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1612	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1613	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1614	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1615	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1616	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1617	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1618	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1619	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1620	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1621	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1622	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1623	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1624	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1625	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1626	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1627	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1628	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1629	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1630	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1631	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1632	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1633	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1634	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1635	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1636
1637	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1638	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1639	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1640	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1641	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1642	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1643	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1644	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1645	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1646	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1647	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1648	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1649	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1650	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1651	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1652	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1653	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1654	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1655	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1656	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1657	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1658	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1659	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1660	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1661	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1662	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1663	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1664	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1665	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1666	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1667	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1668	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1669
1670	if ((fBase \| fGst) != fBase)
1671	{
1672	uint64_t const fDiff = fBase ^ fGst;
1673	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1674	fBase, fGst, fDiff));
1675	return false;
1676	}
1677	}
1678
1679	/* Check second set of feature bits. */
1680	{
1681	uint64_t const fBase = ((uint64_t)pBase->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pBase->fVmxLoadIwKeyExit << 1);
1682	uint64_t const fGst = ((uint64_t)pGst->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pGst->fVmxLoadIwKeyExit << 1);
1683	if ((fBase \| fGst) != fBase)
1684	{
1685	uint64_t const fDiff = fBase ^ fGst;
1686	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1687	fBase, fGst, fDiff));
1688	return false;
1689	}
1690	}
1691
1692	return true;
1693	}
1694
1695
1696	/**
1697	* Initializes VMX guest features and MSRs.
1698	*
1699	* @param pVM The cross context VM structure.
1700	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1701	* and no hardware-assisted nested-guest execution is
1702	* possible for this VM.
1703	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1704	*/
1705	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1706	{
1707	Assert(pVM);
1708	Assert(pGuestVmxMsrs);
1709
1710	/*
1711	* While it would be nice to check this earlier while initializing fNestedVmxEpt
1712	* but we would not have enumearted host features then, so do it at least now.
1713	*/
1714	if ( !pVM->cpum.s.HostFeatures.fNoExecute
1715	&& pVM->cpum.s.fNestedVmxEpt)
1716	{
1717	LogRel(("CPUM: Warning! EPT not exposed to the guest since NX isn't available on the host.\n"));
1718	pVM->cpum.s.fNestedVmxEpt = false;
1719	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1720	}
1721
1722	/*
1723	* Initialize the set of VMX features we emulate.
1724	*
1725	* Note! Some bits might be reported as 1 always if they fall under the
1726	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1727	*/
1728	CPUMFEATURES EmuFeat;
1729	RT_ZERO(EmuFeat);
1730	EmuFeat.fVmx = 1;
1731	EmuFeat.fVmxInsOutInfo = 1;
1732	EmuFeat.fVmxExtIntExit = 1;
1733	EmuFeat.fVmxNmiExit = 1;
1734	EmuFeat.fVmxVirtNmi = 1;
1735	EmuFeat.fVmxPreemptTimer = 0; /* pVM->cpum.s.fNestedVmxPreemptTimer -- Currently disabled on purpose, see @bugref{9180#c108}. */
1736	EmuFeat.fVmxPostedInt = 0;
1737	EmuFeat.fVmxIntWindowExit = 1;
1738	EmuFeat.fVmxTscOffsetting = 1;
1739	EmuFeat.fVmxHltExit = 1;
1740	EmuFeat.fVmxInvlpgExit = 1;
1741	EmuFeat.fVmxMwaitExit = 1;
1742	EmuFeat.fVmxRdpmcExit = 1;
1743	EmuFeat.fVmxRdtscExit = 1;
1744	EmuFeat.fVmxCr3LoadExit = 1;
1745	EmuFeat.fVmxCr3StoreExit = 1;
1746	EmuFeat.fVmxTertiaryExecCtls = 0;
1747	EmuFeat.fVmxCr8LoadExit = 1;
1748	EmuFeat.fVmxCr8StoreExit = 1;
1749	EmuFeat.fVmxUseTprShadow = 1;
1750	EmuFeat.fVmxNmiWindowExit = 0;
1751	EmuFeat.fVmxMovDRxExit = 1;
1752	EmuFeat.fVmxUncondIoExit = 1;
1753	EmuFeat.fVmxUseIoBitmaps = 1;
1754	EmuFeat.fVmxMonitorTrapFlag = 0;
1755	EmuFeat.fVmxUseMsrBitmaps = 1;
1756	EmuFeat.fVmxMonitorExit = 1;
1757	EmuFeat.fVmxPauseExit = 1;
1758	EmuFeat.fVmxSecondaryExecCtls = 1;
1759	EmuFeat.fVmxVirtApicAccess = 1;
1760	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1761	EmuFeat.fVmxDescTableExit = 1;
1762	EmuFeat.fVmxRdtscp = 1;
1763	EmuFeat.fVmxVirtX2ApicMode = 0;
1764	EmuFeat.fVmxVpid = EmuFeat.fVmxEpt;
1765	EmuFeat.fVmxWbinvdExit = 1;
1766	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1767	EmuFeat.fVmxApicRegVirt = 0;
1768	EmuFeat.fVmxVirtIntDelivery = 0;
1769	EmuFeat.fVmxPauseLoopExit = 0;
1770	EmuFeat.fVmxRdrandExit = 0;
1771	EmuFeat.fVmxInvpcid = 1;
1772	EmuFeat.fVmxVmFunc = 0;
1773	EmuFeat.fVmxVmcsShadowing = 0;
1774	EmuFeat.fVmxRdseedExit = 0;
1775	EmuFeat.fVmxPml = 0;
1776	EmuFeat.fVmxEptXcptVe = 0;
1777	EmuFeat.fVmxXsavesXrstors = 0;
1778	EmuFeat.fVmxUseTscScaling = 0;
1779	EmuFeat.fVmxLoadIwKeyExit = 0;
1780	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1781	EmuFeat.fVmxIa32eModeGuest = 1;
1782	EmuFeat.fVmxEntryLoadEferMsr = 1;
1783	EmuFeat.fVmxEntryLoadPatMsr = 0;
1784	EmuFeat.fVmxExitSaveDebugCtls = 1;
1785	EmuFeat.fVmxHostAddrSpaceSize = 1;
1786	EmuFeat.fVmxExitAckExtInt = 1;
1787	EmuFeat.fVmxExitSavePatMsr = 0;
1788	EmuFeat.fVmxExitLoadPatMsr = 0;
1789	EmuFeat.fVmxExitSaveEferMsr = 1;
1790	EmuFeat.fVmxExitLoadEferMsr = 1;
1791	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1792	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1793	EmuFeat.fVmxIntelPt = 0;
1794	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1795	EmuFeat.fVmxEntryInjectSoftInt = 1;
1796
1797	/*
1798	* Merge guest features.
1799	*
1800	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1801	* by the hardware, hence we merge our emulated features with the host features below.
1802	*/
1803	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1804	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1805	Assert(pBaseFeat->fVmx);
1806	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1807	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1808	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1809	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1810	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1811	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1812	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1813	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1814	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1815	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1816	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1817	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1818	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1819	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1820	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1821	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1822	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1823	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1824	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1825	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1826	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1827	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1828	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1829	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1830	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1831	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1832	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1833	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1834	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1835	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1836	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1837	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1838	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1839	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1840	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1841	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1842	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1843	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1844	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1845	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1846	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1847	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1848	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1849	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1850	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1851	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1852	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1853	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1854	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1855	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1856	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1857	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1858	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1859	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1860	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1861	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1862	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1863	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1864	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1865	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1866	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1867	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1868	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1869	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1870	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1871
1872	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1873	if ( pGuestFeat->fVmxPreemptTimer
1874	&& HMIsSubjectToVmxPreemptTimerErratum())
1875	{
1876	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1877	pGuestFeat->fVmxPreemptTimer = 0;
1878	pGuestFeat->fVmxSavePreemptTimer = 0;
1879	}
1880
1881	/* Sanity checking. */
1882	if (!pGuestFeat->fVmxSecondaryExecCtls)
1883	{
1884	Assert(!pGuestFeat->fVmxVirtApicAccess);
1885	Assert(!pGuestFeat->fVmxEpt);
1886	Assert(!pGuestFeat->fVmxDescTableExit);
1887	Assert(!pGuestFeat->fVmxRdtscp);
1888	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1889	Assert(!pGuestFeat->fVmxVpid);
1890	Assert(!pGuestFeat->fVmxWbinvdExit);
1891	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1892	Assert(!pGuestFeat->fVmxApicRegVirt);
1893	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1894	Assert(!pGuestFeat->fVmxPauseLoopExit);
1895	Assert(!pGuestFeat->fVmxRdrandExit);
1896	Assert(!pGuestFeat->fVmxInvpcid);
1897	Assert(!pGuestFeat->fVmxVmFunc);
1898	Assert(!pGuestFeat->fVmxVmcsShadowing);
1899	Assert(!pGuestFeat->fVmxRdseedExit);
1900	Assert(!pGuestFeat->fVmxPml);
1901	Assert(!pGuestFeat->fVmxEptXcptVe);
1902	Assert(!pGuestFeat->fVmxXsavesXrstors);
1903	Assert(!pGuestFeat->fVmxUseTscScaling);
1904	}
1905	else if (pGuestFeat->fVmxUnrestrictedGuest)
1906	{
1907	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1908	Assert(pGuestFeat->fVmxExitSaveEferLma);
1909	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1910	Assert(pGuestFeat->fVmxEpt);
1911	}
1912
1913	if (!pGuestFeat->fVmxTertiaryExecCtls)
1914	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1915
1916	/*
1917	* Finally initialize the VMX guest MSRs.
1918	*/
1919	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1920	}
1921
1922
1923	/**
1924	* Gets the host hardware-virtualization MSRs.
1925	*
1926	* @returns VBox status code.
1927	* @param pMsrs Where to store the MSRs.
1928	*/
1929	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1930	{
1931	Assert(pMsrs);
1932
1933	uint32_t fCaps = 0;
1934	int rc = SUPR3QueryVTCaps(&fCaps);
1935	if (RT_SUCCESS(rc))
1936	{
1937	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
1938	{
1939	SUPHWVIRTMSRS HwvirtMsrs;
1940	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
1941	if (RT_SUCCESS(rc))
1942	{
1943	if (fCaps & SUPVTCAPS_VT_X)
1944	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
1945	else
1946	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
1947	return VINF_SUCCESS;
1948	}
1949
1950	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
1951	return rc;
1952	}
1953
1954	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
1955	return VERR_INTERNAL_ERROR_5;
1956	}
1957	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
1958	return VINF_SUCCESS;
1959	}
1960
1961
1962	/**
1963	* @callback_method_impl{FNTMTIMERINT,
1964	* Callback that fires when the nested VMX-preemption timer expired.}
1965	*/
1966	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
1967	{
1968	RT_NOREF(pVM, hTimer);
1969	PVMCPU pVCpu = (PVMCPUR3)pvUser;
1970	AssertPtr(pVCpu);
1971	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
1972	}
1973
1974
1975	/**
1976	* Initializes the CPUM.
1977	*
1978	* @returns VBox status code.
1979	* @param pVM The cross context VM structure.
1980	*/
1981	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1982	{
1983	LogFlow(("CPUMR3Init\n"));
1984
1985	/*
1986	* Assert alignment, sizes and tables.
1987	*/
1988	AssertCompileMemberAlignment(VM, cpum.s, 32);
1989	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1990	AssertCompileSizeAlignment(CPUMCTX, 64);
1991	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1992	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1993	AssertCompileMemberAlignment(VM, cpum, 64);
1994	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1995	#ifdef VBOX_STRICT
1996	int rc2 = cpumR3MsrStrictInitChecks();
1997	AssertRCReturn(rc2, rc2);
1998	#endif
1999
2000	/*
2001	* Gather info about the host CPU.
2002	*/
2003	if (!ASMHasCpuId())
2004	{
2005	LogRel(("The CPU doesn't support CPUID!\n"));
2006	return VERR_UNSUPPORTED_CPU;
2007	}
2008
2009	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2010
2011	CPUMMSRS HostMsrs;
2012	RT_ZERO(HostMsrs);
2013	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2014	AssertLogRelRCReturn(rc, rc);
2015
2016	PCPUMCPUIDLEAF paLeaves;
2017	uint32_t cLeaves;
2018	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
2019	AssertLogRelRCReturn(rc, rc);
2020
2021	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
2022	RTMemFree(paLeaves);
2023	AssertLogRelRCReturn(rc, rc);
2024	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2025
2026	/*
2027	* Check that the CPU supports the minimum features we require.
2028	*/
2029	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2030	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2031	if (!pVM->cpum.s.HostFeatures.fMmx)
2032	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2033	if (!pVM->cpum.s.HostFeatures.fTsc)
2034	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2035
2036	/*
2037	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2038	*/
2039	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2040	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2041
2042	/*
2043	* Figure out which XSAVE/XRSTOR features are available on the host.
2044	*/
2045	uint64_t fXcr0Host = 0;
2046	uint64_t fXStateHostMask = 0;
2047	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2048	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2049	{
2050	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2051	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2052	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2053	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2054	}
2055	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2056	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2057	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2058
2059	/*
2060	* Initialize the host XSAVE/XRSTOR mask.
2061	*/
2062	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2063	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2064	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2065	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2066	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2067	, VERR_CPUM_IPE_2);
2068
2069	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2070	{
2071	PVMCPU pVCpu = pVM->apCpusR3[i];
2072
2073	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2074	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2075	}
2076
2077	/*
2078	* Register saved state data item.
2079	*/
2080	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2081	NULL, cpumR3LiveExec, NULL,
2082	NULL, cpumR3SaveExec, NULL,
2083	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2084	if (RT_FAILURE(rc))
2085	return rc;
2086
2087	/*
2088	* Register info handlers and registers with the debugger facility.
2089	*/
2090	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2091	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2092	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2093	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2094	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2095	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2096	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2097	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2098	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2099	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2100	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2101	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2102	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2103	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2104	&cpumR3InfoVmxFeatures);
2105
2106	rc = cpumR3DbgInit(pVM);
2107	if (RT_FAILURE(rc))
2108	return rc;
2109
2110	/*
2111	* Check if we need to workaround partial/leaky FPU handling.
2112	*/
2113	cpumR3CheckLeakyFpu(pVM);
2114
2115	/*
2116	* Initialize the Guest CPUID and MSR states.
2117	*/
2118	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2119	if (RT_FAILURE(rc))
2120	return rc;
2121
2122	/*
2123	* Allocate memory required by the guest hardware-virtualization structures.
2124	* This must be done after initializing CPUID/MSR features as we access the
2125	* the VMX/SVM guest features below.
2126	*
2127	* In the case of nested VT-x, we also need to create the per-VCPU
2128	* VMX preemption timers.
2129	*/
2130	if (pVM->cpum.s.GuestFeatures.fVmx)
2131	rc = cpumR3AllocVmxHwVirtState(pVM);
2132	else if (pVM->cpum.s.GuestFeatures.fSvm)
2133	cpumR3InitSvmHwVirtState(pVM);
2134	else
2135	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2136	if (RT_FAILURE(rc))
2137	return rc;
2138
2139	CPUMR3Reset(pVM);
2140	return VINF_SUCCESS;
2141	}
2142
2143
2144	/**
2145	* Applies relocations to data and code managed by this
2146	* component. This function will be called at init and
2147	* whenever the VMM need to relocate it self inside the GC.
2148	*
2149	* The CPUM will update the addresses used by the switcher.
2150	*
2151	* @param pVM The cross context VM structure.
2152	*/
2153	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2154	{
2155	RT_NOREF(pVM);
2156	}
2157
2158
2159	/**
2160	* Terminates the CPUM.
2161	*
2162	* Termination means cleaning up and freeing all resources,
2163	* the VM it self is at this point powered off or suspended.
2164	*
2165	* @returns VBox status code.
2166	* @param pVM The cross context VM structure.
2167	*/
2168	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2169	{
2170	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2171	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2172	{
2173	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2174	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2175	pVCpu->cpum.s.uMagic = 0;
2176	pvCpu->cpum.s.Guest.dr[5] = 0;
2177	}
2178	#endif
2179
2180	if (pVM->cpum.s.GuestFeatures.fVmx)
2181	{
2182	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2183	{
2184	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2185	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2186	{
2187	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2188	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2189	}
2190	}
2191
2192	cpumR3FreeVmxHwVirtState(pVM);
2193	}
2194	return VINF_SUCCESS;
2195	}
2196
2197
2198	/**
2199	* Resets a virtual CPU.
2200	*
2201	* Used by CPUMR3Reset and CPU hot plugging.
2202	*
2203	* @param pVM The cross context VM structure.
2204	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2205	* being reset. This may differ from the current EMT.
2206	*/
2207	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2208	{
2209	/** @todo anything different for VCPU > 0? */
2210	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2211
2212	/*
2213	* Initialize everything to ZERO first.
2214	*/
2215	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2216
2217	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2218
2219	pVCpu->cpum.s.fUseFlags = fUseFlags;
2220
2221	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2222	pCtx->eip = 0x0000fff0;
2223	pCtx->edx = 0x00000600; /* P6 processor */
2224	pCtx->eflags.Bits.u1Reserved0 = 1;
2225
2226	pCtx->cs.Sel = 0xf000;
2227	pCtx->cs.ValidSel = 0xf000;
2228	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2229	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2230	pCtx->cs.u32Limit = 0x0000ffff;
2231	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2232	pCtx->cs.Attr.n.u1Present = 1;
2233	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2234
2235	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2236	pCtx->ds.u32Limit = 0x0000ffff;
2237	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2238	pCtx->ds.Attr.n.u1Present = 1;
2239	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2240
2241	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2242	pCtx->es.u32Limit = 0x0000ffff;
2243	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2244	pCtx->es.Attr.n.u1Present = 1;
2245	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2246
2247	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2248	pCtx->fs.u32Limit = 0x0000ffff;
2249	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2250	pCtx->fs.Attr.n.u1Present = 1;
2251	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2252
2253	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2254	pCtx->gs.u32Limit = 0x0000ffff;
2255	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2256	pCtx->gs.Attr.n.u1Present = 1;
2257	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2258
2259	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2260	pCtx->ss.u32Limit = 0x0000ffff;
2261	pCtx->ss.Attr.n.u1Present = 1;
2262	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2263	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2264
2265	pCtx->idtr.cbIdt = 0xffff;
2266	pCtx->gdtr.cbGdt = 0xffff;
2267
2268	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2269	pCtx->ldtr.u32Limit = 0xffff;
2270	pCtx->ldtr.Attr.n.u1Present = 1;
2271	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2272
2273	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2274	pCtx->tr.u32Limit = 0xffff;
2275	pCtx->tr.Attr.n.u1Present = 1;
2276	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2277
2278	pCtx->dr[6] = X86_DR6_INIT_VAL;
2279	pCtx->dr[7] = X86_DR7_INIT_VAL;
2280
2281	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2282	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2283	pFpuCtx->FCW = 0x37f;
2284
2285	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2286	IA-32 Processor States Following Power-up, Reset, or INIT */
2287	pFpuCtx->MXCSR = 0x1F80;
2288	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2289
2290	pCtx->aXcr[0] = XSAVE_C_X87;
2291	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2292	{
2293	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2294	as we don't know what happened before. (Bother optimize later?) */
2295	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2296	}
2297
2298	/*
2299	* MSRs.
2300	*/
2301	/* Init PAT MSR */
2302	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2303
2304	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2305	* The Intel docs don't mention it. */
2306	Assert(!pCtx->msrEFER);
2307
2308	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2309	is supposed to be here, just trying provide useful/sensible values. */
2310	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2311	if (pRange)
2312	{
2313	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2314	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2315	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2316	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2317	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2318	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2319	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2320	}
2321
2322	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2323
2324	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2325	* called from each EMT while we're getting called by CPUMR3Reset()
2326	* iteratively on the same thread. Fix later. */
2327	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2328	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2329	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2330	#endif
2331
2332
2333	/* C-state control. Guesses. */
2334	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2335	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2336	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2337	* functionality. The default value must be different due to incompatible write mask.
2338	*/
2339	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2340	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2341	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2342	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2343
2344	/*
2345	* Hardware virtualization state.
2346	*/
2347	CPUMSetGuestGif(pCtx, true);
2348	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2349	if (pVM->cpum.s.GuestFeatures.fVmx)
2350	cpumR3ResetVmxHwVirtState(pVCpu);
2351	else if (pVM->cpum.s.GuestFeatures.fSvm)
2352	cpumR3ResetSvmHwVirtState(pVCpu);
2353	}
2354
2355
2356	/**
2357	* Resets the CPU.
2358	*
2359	* @returns VINF_SUCCESS.
2360	* @param pVM The cross context VM structure.
2361	*/
2362	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2363	{
2364	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2365	{
2366	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2367	CPUMR3ResetCpu(pVM, pVCpu);
2368
2369	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2370
2371	/* Magic marker for searching in crash dumps. */
2372	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2373	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2374	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2375	#endif
2376	}
2377	}
2378
2379
2380
2381
2382	/**
2383	* Pass 0 live exec callback.
2384	*
2385	* @returns VINF_SSM_DONT_CALL_AGAIN.
2386	* @param pVM The cross context VM structure.
2387	* @param pSSM The saved state handle.
2388	* @param uPass The pass (0).
2389	*/
2390	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2391	{
2392	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2393	cpumR3SaveCpuId(pVM, pSSM);
2394	return VINF_SSM_DONT_CALL_AGAIN;
2395	}
2396
2397
2398	/**
2399	* Execute state save operation.
2400	*
2401	* @returns VBox status code.
2402	* @param pVM The cross context VM structure.
2403	* @param pSSM SSM operation handle.
2404	*/
2405	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2406	{
2407	/*
2408	* Save.
2409	*/
2410	SSMR3PutU32(pSSM, pVM->cCpus);
2411	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2412	CPUMCTX DummyHyperCtx;
2413	RT_ZERO(DummyHyperCtx);
2414	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2415	{
2416	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2417
2418	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2419
2420	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2421	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2422	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2423	if (pGstCtx->fXStateMask != 0)
2424	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2425	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2426	{
2427	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2428	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2429	}
2430	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2431	{
2432	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2433	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2434	}
2435	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2436	{
2437	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2438	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2439	}
2440	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2441	{
2442	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2443	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2444	}
2445	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2446	{
2447	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2448	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2449	}
2450	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2451	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2452	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2453	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2454	if (pVM->cpum.s.GuestFeatures.fSvm)
2455	{
2456	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2457	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2458	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2459	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2460	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2461	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2462	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2463	g_aSvmHwvirtHostState, NULL /* pvUser */);
2464	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2465	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2466	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2467	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2468	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2469	}
2470	if (pVM->cpum.s.GuestFeatures.fVmx)
2471	{
2472	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2473	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2474	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2475	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2476	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2477	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2478	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2479	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2480	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2481	0, g_aVmxHwvirtVmcs, NULL);
2482	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2483	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2484	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2485	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2486	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2487	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2488	SSMR3PutMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2489	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2490	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2491	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2492	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2493	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2494	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2495	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2496	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2497	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2498	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2499	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2500	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2501	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2502	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2503	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2504	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2505	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2506	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2507	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2508	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2509	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2510	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2511	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2512	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2513	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2514	}
2515	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2516	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2517	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2518	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2519	}
2520
2521	cpumR3SaveCpuId(pVM, pSSM);
2522	return VINF_SUCCESS;
2523	}
2524
2525
2526	/**
2527	* @callback_method_impl{FNSSMINTLOADPREP}
2528	*/
2529	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2530	{
2531	NOREF(pSSM);
2532	pVM->cpum.s.fPendingRestore = true;
2533	return VINF_SUCCESS;
2534	}
2535
2536
2537	/**
2538	* @callback_method_impl{FNSSMINTLOADEXEC}
2539	*/
2540	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2541	{
2542	int rc; /* Only for AssertRCReturn use. */
2543
2544	/*
2545	* Validate version.
2546	*/
2547	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2548	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2549	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2550	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2551	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2552	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2553	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2554	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2555	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2556	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2557	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2558	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2559	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2560	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2561	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2562	{
2563	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2564	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2565	}
2566
2567	if (uPass == SSM_PASS_FINAL)
2568	{
2569	/*
2570	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2571	* really old SSM file versions.)
2572	*/
2573	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2574	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2575	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2576	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2577
2578	/*
2579	* Figure x86 and ctx field definitions to use for older states.
2580	*/
2581	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2582	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2583	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2584	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2585	{
2586	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2587	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2588	}
2589	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2590	{
2591	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2592	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2593	}
2594
2595	/*
2596	* The hyper state used to preceed the CPU count. Starting with
2597	* XSAVE it was moved down till after we've got the count.
2598	*/
2599	CPUMCTX HyperCtxIgnored;
2600	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2601	{
2602	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2603	{
2604	X86FXSTATE Ign;
2605	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2606	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2607	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2608	}
2609	}
2610
2611	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2612	{
2613	uint32_t cCpus;
2614	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2615	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2616	VERR_SSM_UNEXPECTED_DATA);
2617	}
2618	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2619	\|\| pVM->cCpus == 1,
2620	("cCpus=%u\n", pVM->cCpus),
2621	VERR_SSM_UNEXPECTED_DATA);
2622
2623	uint32_t cbMsrs = 0;
2624	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2625	{
2626	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2627	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2628	VERR_SSM_UNEXPECTED_DATA);
2629	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2630	VERR_SSM_UNEXPECTED_DATA);
2631	}
2632
2633	/*
2634	* Do the per-CPU restoring.
2635	*/
2636	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2637	{
2638	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2639	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2640
2641	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2642	{
2643	/*
2644	* The XSAVE saved state layout moved the hyper state down here.
2645	*/
2646	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2647	AssertRCReturn(rc, rc);
2648
2649	/*
2650	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2651	*/
2652	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2653	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2654	AssertRCReturn(rc, rc);
2655
2656	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2657	if (pGstCtx->fXStateMask != 0)
2658	{
2659	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2660	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2661	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2662	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2663	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2664	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2665	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2666	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2667	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2668	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2669	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2670	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2671	}
2672
2673	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2674	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2675	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2676	{
2677	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2678	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2679	VERR_CPUM_INVALID_XCR0);
2680	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2681	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2682	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2683	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2684	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2685	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2686	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2687	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2688	}
2689
2690	/* Check that the XCR1 is zero, as we don't implement it yet. */
2691	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2692
2693	/*
2694	* Restore the individual extended state components we support.
2695	*/
2696	if (pGstCtx->fXStateMask != 0)
2697	{
2698	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2699	0, g_aCpumXSaveHdrFields, NULL);
2700	AssertRCReturn(rc, rc);
2701	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2702	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2703	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2704	VERR_CPUM_INVALID_XSAVE_HDR);
2705	}
2706	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2707	{
2708	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2709	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2710	}
2711	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2712	{
2713	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2714	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2715	}
2716	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2717	{
2718	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2719	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2720	}
2721	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2722	{
2723	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2724	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2725	}
2726	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2727	{
2728	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2729	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2730	}
2731	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2732	{
2733	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2734	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2735	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2736	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2737	}
2738	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2739	{
2740	if (pVM->cpum.s.GuestFeatures.fSvm)
2741	{
2742	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2743	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2744	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2745	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2746	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2747	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2748	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2749	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2750	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2751	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2752	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2753	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2754	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2755	}
2756	}
2757	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2758	{
2759	if (pVM->cpum.s.GuestFeatures.fVmx)
2760	{
2761	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2762	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2763	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2764	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2765	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2766	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2767	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2768	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2769	0, g_aVmxHwvirtVmcs, NULL);
2770	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2771	0, g_aVmxHwvirtVmcs, NULL);
2772	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2773	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2774	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2775	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2776	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2777	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvMsrBitmapR3, VMX_V_MSR_BITMAP_SIZE);
2778	SSMR3GetMem(pSSM, pGstCtx->hwvirt.vmx.pvIoBitmapR3, VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
2779	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2780	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2781	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2782	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2783	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2784	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64FeatCtrl);
2785	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2786	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2787	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2788	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2789	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2790	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2791	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2792	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2793	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2794	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2795	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2796	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2797	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2798	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2799	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2800	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2801	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2802	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2803	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2804	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2805	}
2806	}
2807	}
2808	else
2809	{
2810	/*
2811	* Pre XSAVE saved state.
2812	*/
2813	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2814	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2815	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2816	}
2817
2818	/*
2819	* Restore a couple of flags and the MSRs.
2820	*/
2821	uint32_t fIgnoredUsedFlags = 0;
2822	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2823	AssertRCReturn(rc, rc);
2824	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2825
2826	rc = VINF_SUCCESS;
2827	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2828	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2829	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2830	{
2831	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2832	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2833	}
2834	AssertRCReturn(rc, rc);
2835
2836	/* REM and other may have cleared must-be-one fields in DR6 and
2837	DR7, fix these. */
2838	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2839	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2840	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2841	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2842	}
2843
2844	/* Older states does not have the internal selector register flags
2845	and valid selector value. Supply those. */
2846	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2847	{
2848	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2849	{
2850	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2851	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2852	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2853	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2854	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2855	if (fValid)
2856	{
2857	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2858	{
2859	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2860	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2861	}
2862
2863	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2864	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2865	}
2866	else
2867	{
2868	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2869	{
2870	paSelReg[iSelReg].fFlags = 0;
2871	paSelReg[iSelReg].ValidSel = 0;
2872	}
2873
2874	/* This might not be 104% correct, but I think it's close
2875	enough for all practical purposes... (REM always loaded
2876	LDTR registers.) */
2877	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2878	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2879	}
2880	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2881	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2882	}
2883	}
2884
2885	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2886	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2887	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2888	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2889	{
2890	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2891	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2892	}
2893
2894	/*
2895	* A quick sanity check.
2896	*/
2897	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2898	{
2899	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2900	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2901	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2902	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2903	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2904	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2905	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2906	}
2907	}
2908
2909	pVM->cpum.s.fPendingRestore = false;
2910
2911	/*
2912	* Guest CPUIDs (and VMX MSR features).
2913	*/
2914	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2915	{
2916	CPUMMSRS GuestMsrs;
2917	RT_ZERO(GuestMsrs);
2918
2919	CPUMFEATURES BaseFeatures;
2920	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
2921	if (fVmxGstFeat)
2922	{
2923	/*
2924	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
2925	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
2926	* here so we can compare them for compatibility after exploding guest features.
2927	*/
2928	BaseFeatures = pVM->cpum.s.GuestFeatures;
2929
2930	/* Use the VMX MSR features from the saved state while exploding guest features. */
2931	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
2932	}
2933
2934	/* Load CPUID and explode guest features. */
2935	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
2936	if (fVmxGstFeat)
2937	{
2938	/*
2939	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
2940	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
2941	* VMX features presented to the guest.
2942	*/
2943	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
2944	if (!fIsCompat)
2945	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
2946	}
2947	return rc;
2948	}
2949	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2950	}
2951
2952
2953	/**
2954	* @callback_method_impl{FNSSMINTLOADDONE}
2955	*/
2956	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2957	{
2958	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2959	return VINF_SUCCESS;
2960
2961	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2962	if (pVM->cpum.s.fPendingRestore)
2963	{
2964	LogRel(("CPUM: Missing state!\n"));
2965	return VERR_INTERNAL_ERROR_2;
2966	}
2967
2968	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2969	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2970	{
2971	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2972
2973	/* Notify PGM of the NXE states in case they've changed. */
2974	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2975
2976	/* During init. this is done in CPUMR3InitCompleted(). */
2977	if (fSupportsLongMode)
2978	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2979
2980	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
2981	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
2982	}
2983	return VINF_SUCCESS;
2984	}
2985
2986
2987	/**
2988	* Checks if the CPUM state restore is still pending.
2989	*
2990	* @returns true / false.
2991	* @param pVM The cross context VM structure.
2992	*/
2993	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2994	{
2995	return pVM->cpum.s.fPendingRestore;
2996	}
2997
2998
2999	/**
3000	* Formats the EFLAGS value into mnemonics.
3001	*
3002	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3003	* @param efl The EFLAGS value.
3004	*/
3005	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3006	{
3007	/*
3008	* Format the flags.
3009	*/
3010	static const struct
3011	{
3012	const char pszSet; const char pszClear; uint32_t fFlag;
3013	} s_aFlags[] =
3014	{
3015	{ "vip",NULL, X86_EFL_VIP },
3016	{ "vif",NULL, X86_EFL_VIF },
3017	{ "ac", NULL, X86_EFL_AC },
3018	{ "vm", NULL, X86_EFL_VM },
3019	{ "rf", NULL, X86_EFL_RF },
3020	{ "nt", NULL, X86_EFL_NT },
3021	{ "ov", "nv", X86_EFL_OF },
3022	{ "dn", "up", X86_EFL_DF },
3023	{ "ei", "di", X86_EFL_IF },
3024	{ "tf", NULL, X86_EFL_TF },
3025	{ "nt", "pl", X86_EFL_SF },
3026	{ "nz", "zr", X86_EFL_ZF },
3027	{ "ac", "na", X86_EFL_AF },
3028	{ "po", "pe", X86_EFL_PF },
3029	{ "cy", "nc", X86_EFL_CF },
3030	};
3031	char *psz = pszEFlags;
3032	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3033	{
3034	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3035	if (pszAdd)
3036	{
3037	strcpy(psz, pszAdd);
3038	psz += strlen(pszAdd);
3039	*psz++ = ' ';
3040	}
3041	}
3042	psz[-1] = '\0';
3043	}
3044
3045
3046	/**
3047	* Formats a full register dump.
3048	*
3049	* @param pVM The cross context VM structure.
3050	* @param pCtx The context to format.
3051	* @param pCtxCore The context core to format.
3052	* @param pHlp Output functions.
3053	* @param enmType The dump type.
3054	* @param pszPrefix Register name prefix.
3055	*/
3056	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
3057	const char *pszPrefix)
3058	{
3059	NOREF(pVM);
3060
3061	/*
3062	* Format the EFLAGS.
3063	*/
3064	uint32_t efl = pCtxCore->eflags.u32;
3065	char szEFlags[80];
3066	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3067
3068	/*
3069	* Format the registers.
3070	*/
3071	switch (enmType)
3072	{
3073	case CPUMDUMPTYPE_TERSE:
3074	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3075	pHlp->pfnPrintf(pHlp,
3076	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3077	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3078	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3079	"%sr14=%016RX64 %sr15=%016RX64\n"
3080	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3081	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3082	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3083	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3084	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3085	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3086	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3087	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3088	else
3089	pHlp->pfnPrintf(pHlp,
3090	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3091	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3092	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3093	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3094	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3095	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3096	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3097	break;
3098
3099	case CPUMDUMPTYPE_DEFAULT:
3100	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3101	pHlp->pfnPrintf(pHlp,
3102	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3103	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3104	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3105	"%sr14=%016RX64 %sr15=%016RX64\n"
3106	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3107	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3108	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3109	,
3110	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3111	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3112	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3113	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3114	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3115	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3116	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3117	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3118	else
3119	pHlp->pfnPrintf(pHlp,
3120	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3121	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3122	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3123	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3124	,
3125	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3126	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3127	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3128	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3129	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3130	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3131	break;
3132
3133	case CPUMDUMPTYPE_VERBOSE:
3134	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3135	pHlp->pfnPrintf(pHlp,
3136	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3137	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3138	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3139	"%sr14=%016RX64 %sr15=%016RX64\n"
3140	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3141	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3142	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3143	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3144	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3145	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3146	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3147	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3148	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3149	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3150	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3151	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3152	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3153	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3154	,
3155	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3156	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3157	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3158	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3159	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3160	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3161	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3162	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3163	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3164	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3165	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3166	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3167	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3168	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3169	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3170	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3171	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3172	else
3173	pHlp->pfnPrintf(pHlp,
3174	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3175	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3176	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3177	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3178	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3179	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3180	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3181	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3182	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3183	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3184	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3185	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3186	,
3187	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3188	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3189	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3190	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3191	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3192	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3193	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3194	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3195	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3196	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3197	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3198	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3199
3200	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3201	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3202	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3203	{
3204	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3205	pHlp->pfnPrintf(pHlp,
3206	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3207	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3208	,
3209	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3210	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3211	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3212	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3213	);
3214	/*
3215	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3216	* not (FP)R0-7 as Intel SDM suggests.
3217	*/
3218	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3219	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3220	{
3221	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3222	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3223	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3224	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3225	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3226	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3227	iExponent -= 16383; /* subtract bias */
3228	/** @todo This isn't entirenly correct and needs more work! */
3229	pHlp->pfnPrintf(pHlp,
3230	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3231	pszPrefix, iST, pszPrefix, iFPR,
3232	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3233	uTag, chSign, iInteger, u64Fraction, iExponent);
3234	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3235	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3236	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3237	else
3238	pHlp->pfnPrintf(pHlp, "\n");
3239	}
3240
3241	/* XMM/YMM/ZMM registers. */
3242	if (pCtx->fXStateMask & XSAVE_C_YMM)
3243	{
3244	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3245	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3246	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3247	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3248	pszPrefix, i, i < 10 ? " " : "",
3249	pYmmHiCtx->aYmmHi[i].au32[3],
3250	pYmmHiCtx->aYmmHi[i].au32[2],
3251	pYmmHiCtx->aYmmHi[i].au32[1],
3252	pYmmHiCtx->aYmmHi[i].au32[0],
3253	pFpuCtx->aXMM[i].au32[3],
3254	pFpuCtx->aXMM[i].au32[2],
3255	pFpuCtx->aXMM[i].au32[1],
3256	pFpuCtx->aXMM[i].au32[0]);
3257	else
3258	{
3259	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3260	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3261	pHlp->pfnPrintf(pHlp,
3262	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3263	pszPrefix, i, i < 10 ? " " : "",
3264	pZmmHi256->aHi256Regs[i].au32[7],
3265	pZmmHi256->aHi256Regs[i].au32[6],
3266	pZmmHi256->aHi256Regs[i].au32[5],
3267	pZmmHi256->aHi256Regs[i].au32[4],
3268	pZmmHi256->aHi256Regs[i].au32[3],
3269	pZmmHi256->aHi256Regs[i].au32[2],
3270	pZmmHi256->aHi256Regs[i].au32[1],
3271	pZmmHi256->aHi256Regs[i].au32[0],
3272	pYmmHiCtx->aYmmHi[i].au32[3],
3273	pYmmHiCtx->aYmmHi[i].au32[2],
3274	pYmmHiCtx->aYmmHi[i].au32[1],
3275	pYmmHiCtx->aYmmHi[i].au32[0],
3276	pFpuCtx->aXMM[i].au32[3],
3277	pFpuCtx->aXMM[i].au32[2],
3278	pFpuCtx->aXMM[i].au32[1],
3279	pFpuCtx->aXMM[i].au32[0]);
3280
3281	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3282	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3283	pHlp->pfnPrintf(pHlp,
3284	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3285	pszPrefix, i + 16,
3286	pZmm16Hi->aRegs[i].au32[15],
3287	pZmm16Hi->aRegs[i].au32[14],
3288	pZmm16Hi->aRegs[i].au32[13],
3289	pZmm16Hi->aRegs[i].au32[12],
3290	pZmm16Hi->aRegs[i].au32[11],
3291	pZmm16Hi->aRegs[i].au32[10],
3292	pZmm16Hi->aRegs[i].au32[9],
3293	pZmm16Hi->aRegs[i].au32[8],
3294	pZmm16Hi->aRegs[i].au32[7],
3295	pZmm16Hi->aRegs[i].au32[6],
3296	pZmm16Hi->aRegs[i].au32[5],
3297	pZmm16Hi->aRegs[i].au32[4],
3298	pZmm16Hi->aRegs[i].au32[3],
3299	pZmm16Hi->aRegs[i].au32[2],
3300	pZmm16Hi->aRegs[i].au32[1],
3301	pZmm16Hi->aRegs[i].au32[0]);
3302	}
3303	}
3304	else
3305	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3306	pHlp->pfnPrintf(pHlp,
3307	i & 1
3308	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3309	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3310	pszPrefix, i, i < 10 ? " " : "",
3311	pFpuCtx->aXMM[i].au32[3],
3312	pFpuCtx->aXMM[i].au32[2],
3313	pFpuCtx->aXMM[i].au32[1],
3314	pFpuCtx->aXMM[i].au32[0]);
3315
3316	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3317	{
3318	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3319	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3320	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3321	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3322	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3323	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3324	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3325	}
3326
3327	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3328	{
3329	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3330	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3331	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3332	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3333	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3334	}
3335
3336	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3337	{
3338	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3339	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3340	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3341	}
3342
3343	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3344	if (pFpuCtx->au32RsrvdRest[i])
3345	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3346	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3347	}
3348
3349	pHlp->pfnPrintf(pHlp,
3350	"%sEFER =%016RX64\n"
3351	"%sPAT =%016RX64\n"
3352	"%sSTAR =%016RX64\n"
3353	"%sCSTAR =%016RX64\n"
3354	"%sLSTAR =%016RX64\n"
3355	"%sSFMASK =%016RX64\n"
3356	"%sKERNELGSBASE =%016RX64\n",
3357	pszPrefix, pCtx->msrEFER,
3358	pszPrefix, pCtx->msrPAT,
3359	pszPrefix, pCtx->msrSTAR,
3360	pszPrefix, pCtx->msrCSTAR,
3361	pszPrefix, pCtx->msrLSTAR,
3362	pszPrefix, pCtx->msrSFMASK,
3363	pszPrefix, pCtx->msrKERNELGSBASE);
3364
3365	if (CPUMIsGuestInPAEModeEx(pCtx))
3366	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3367	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3368	break;
3369	}
3370	}
3371
3372
3373	/**
3374	* Display all cpu states and any other cpum info.
3375	*
3376	* @param pVM The cross context VM structure.
3377	* @param pHlp The info helper functions.
3378	* @param pszArgs Arguments, ignored.
3379	*/
3380	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3381	{
3382	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3383	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3384	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3385	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3386	cpumR3InfoHost(pVM, pHlp, pszArgs);
3387	}
3388
3389
3390	/**
3391	* Parses the info argument.
3392	*
3393	* The argument starts with 'verbose', 'terse' or 'default' and then
3394	* continues with the comment string.
3395	*
3396	* @param pszArgs The pointer to the argument string.
3397	* @param penmType Where to store the dump type request.
3398	* @param ppszComment Where to store the pointer to the comment string.
3399	*/
3400	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3401	{
3402	if (!pszArgs)
3403	{
3404	*penmType = CPUMDUMPTYPE_DEFAULT;
3405	*ppszComment = "";
3406	}
3407	else
3408	{
3409	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3410	{
3411	pszArgs += 7;
3412	*penmType = CPUMDUMPTYPE_VERBOSE;
3413	}
3414	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3415	{
3416	pszArgs += 5;
3417	*penmType = CPUMDUMPTYPE_TERSE;
3418	}
3419	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3420	{
3421	pszArgs += 7;
3422	*penmType = CPUMDUMPTYPE_DEFAULT;
3423	}
3424	else
3425	*penmType = CPUMDUMPTYPE_DEFAULT;
3426	*ppszComment = RTStrStripL(pszArgs);
3427	}
3428	}
3429
3430
3431	/**
3432	* Display the guest cpu state.
3433	*
3434	* @param pVM The cross context VM structure.
3435	* @param pHlp The info helper functions.
3436	* @param pszArgs Arguments.
3437	*/
3438	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3439	{
3440	CPUMDUMPTYPE enmType;
3441	const char *pszComment;
3442	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3443
3444	PVMCPU pVCpu = VMMGetCpu(pVM);
3445	if (!pVCpu)
3446	pVCpu = pVM->apCpusR3[0];
3447
3448	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3449
3450	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3451	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3452	}
3453
3454
3455	/**
3456	* Displays an SVM VMCB control area.
3457	*
3458	* @param pHlp The info helper functions.
3459	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3460	* @param pszPrefix Caller specified string prefix.
3461	*/
3462	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3463	{
3464	AssertReturnVoid(pHlp);
3465	AssertReturnVoid(pVmcbCtrl);
3466
3467	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3468	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3469	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3470	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3471	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3472	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3473	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3474	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3475	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3476	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3477	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3478	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3479	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3480	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3481	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3482	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3483	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3484	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3485	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3486	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3487	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3488	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3489	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3490	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3491	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3492	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3493	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3494	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3495	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3496	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3497	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3498	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3499	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3500	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3501	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3502	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3503	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3504	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3505	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3506	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3507	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3508	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3509	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3510	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3511	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3512	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3513	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3514	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3515	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3516	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3517	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3518	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3519	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3520	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3521	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3522	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3523	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3524	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3525	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3526	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3527	}
3528
3529
3530	/**
3531	* Helper for dumping the SVM VMCB selector registers.
3532	*
3533	* @param pHlp The info helper functions.
3534	* @param pSel Pointer to the SVM selector register.
3535	* @param pszName Name of the selector.
3536	* @param pszPrefix Caller specified string prefix.
3537	*/
3538	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3539	{
3540	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3541	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3542	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3543	}
3544
3545
3546	/**
3547	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3548	*
3549	* @param pHlp The info helper functions.
3550	* @param pXdtr Pointer to the descriptor table register.
3551	* @param pszName Name of the descriptor table register.
3552	* @param pszPrefix Caller specified string prefix.
3553	*/
3554	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3555	{
3556	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3557	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3558	}
3559
3560
3561	/**
3562	* Displays an SVM VMCB state-save area.
3563	*
3564	* @param pHlp The info helper functions.
3565	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3566	* @param pszPrefix Caller specified string prefix.
3567	*/
3568	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3569	{
3570	AssertReturnVoid(pHlp);
3571	AssertReturnVoid(pVmcbStateSave);
3572
3573	char szEFlags[80];
3574	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3575
3576	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3577	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3578	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3579	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3580	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3581	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3582	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3583	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3584	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3585	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3586	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3587	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3588	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3589	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3590	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3591	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3592	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3593	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3594	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3595	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3596	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3597	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3598	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3599	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3600	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3601	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3602	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3603	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3604	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3605	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3606	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3607	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3608	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3609	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3610	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3611	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3612	}
3613
3614
3615	/**
3616	* Displays a virtual-VMCS.
3617	*
3618	* @param pVCpu The cross context virtual CPU structure.
3619	* @param pHlp The info helper functions.
3620	* @param pVmcs Pointer to a virtual VMCS.
3621	* @param pszPrefix Caller specified string prefix.
3622	*/
3623	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3624	{
3625	AssertReturnVoid(pHlp);
3626	AssertReturnVoid(pVmcs);
3627
3628	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3629	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3630	do { \
3631	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3632	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3633	} while (0)
3634
3635	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3636	do { \
3637	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3638	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3639	} while (0)
3640
3641	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3642	do { \
3643	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3644	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3645	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3646	} while (0)
3647
3648	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3649	do { \
3650	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3651	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3652	} while (0)
3653
3654	/* Header. */
3655	{
3656	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3657	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3658	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3659	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3660	}
3661
3662	/* Control fields. */
3663	{
3664	/* 16-bit. */
3665	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3666	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3667	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3668	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3669
3670	/* 32-bit. */
3671	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3672	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3673	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3674	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3675	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3676	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3677	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3678	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3679	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3680	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3681	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3682	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3683	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3684	{
3685	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3686	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3687	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3688	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3689	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3690	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3691	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3692	}
3693	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3694	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3695	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3696	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3697	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3698
3699	/* 64-bit. */
3700	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3701	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3702	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3703	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3704	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3705	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3706	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3707	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3708	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3709	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3710	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3711	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3712	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3713	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3714	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3715	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3716	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3717	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3718	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3719	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3720	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3721	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3722	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3723	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3724	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3725	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3726	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3727	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3728
3729	/* Natural width. */
3730	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3731	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3732	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3733	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3734	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3735	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3736	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3737	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3738	}
3739
3740	/* Guest state. */
3741	{
3742	char szEFlags[80];
3743	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3744	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3745
3746	/* 16-bit. */
3747	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3748	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3749	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3750	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3751	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3752	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3753	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3754	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3755	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3756	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3757	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3758	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3759
3760	/* 32-bit. */
3761	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3762	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3763	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3764	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3765	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3766
3767	/* 64-bit. */
3768	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3769	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3770	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3771	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3772	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3773	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3774	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3775	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3776	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3777	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3778	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3779	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3780
3781	/* Natural width. */
3782	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3783	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3784	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3785	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3786	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3787	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3788	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3789	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3790	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3791	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3792	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3793	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3794	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3795	}
3796
3797	/* Host state. */
3798	{
3799	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3800
3801	/* 16-bit. */
3802	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3803	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3804	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3805	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3806	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3807	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3808	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3809	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3810	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3811
3812	/* 32-bit. */
3813	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3814
3815	/* 64-bit. */
3816	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3817	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3818	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3819	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3820
3821	/* Natural width. */
3822	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3823	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3824	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3825	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3826	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3827	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3828	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3829	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3830	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3831	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3832
3833	}
3834
3835	/* Read-only fields. */
3836	{
3837	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3838
3839	/* 16-bit (none currently). */
3840
3841	/* 32-bit. */
3842	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3843	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3844	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3845	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3846	{
3847	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3848	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3849	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3850	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3851	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3852	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3853	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3854	}
3855	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3856	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3857	{
3858	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3859	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3860	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3861	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3862	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3863	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3864	}
3865	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3866	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3867	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3868
3869	/* 64-bit. */
3870	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3871
3872	/* Natural width. */
3873	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3874	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3875	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3876	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3877	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3878	}
3879
3880	#ifdef DEBUG_ramshankar
3881	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3882	{
3883	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3884	Assert(pvPage);
3885	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3886	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3887	if (RT_SUCCESS(rc))
3888	{
3889	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3890	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3891	pHlp->pfnPrintf(pHlp, "\n");
3892	}
3893	RTMemTmpFree(pvPage);
3894	}
3895	#else
3896	NOREF(pVCpu);
3897	#endif
3898
3899	#undef CPUMVMX_DUMP_HOST_XDTR
3900	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3901	#undef CPUMVMX_DUMP_GUEST_SEGREG
3902	#undef CPUMVMX_DUMP_GUEST_XDTR
3903	}
3904
3905
3906	/**
3907	* Display the guest's hardware-virtualization cpu state.
3908	*
3909	* @param pVM The cross context VM structure.
3910	* @param pHlp The info helper functions.
3911	* @param pszArgs Arguments, ignored.
3912	*/
3913	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3914	{
3915	RT_NOREF(pszArgs);
3916
3917	PVMCPU pVCpu = VMMGetCpu(pVM);
3918	if (!pVCpu)
3919	pVCpu = pVM->apCpusR3[0];
3920
3921	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3922	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
3923	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
3924
3925	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3926	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3927	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
3928
3929	if (fSvm)
3930	{
3931	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
3932	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
3933
3934	char szEFlags[80];
3935	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
3936	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
3937	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
3938	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
3939	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
3940	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
3941	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
3942	pHlp->pfnPrintf(pHlp, " HostState:\n");
3943	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
3944	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
3945	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
3946	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
3947	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
3948	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
3949	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
3950	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
3951	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
3952	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3953	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
3954	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
3955	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3956	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
3957	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
3958	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3959	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
3960	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
3961	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3962	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
3963	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
3964	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
3965	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
3966	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
3967	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
3968	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
3969	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
3970	}
3971	else if (fVmx)
3972	{
3973	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
3974	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
3975	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
3976	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
3977	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
3978	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
3979	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
3980	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
3981	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
3982	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
3983	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
3984	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
3985	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
3986	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
3987	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
3988	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
3989	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
3990	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
3991	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
3992	}
3993	else
3994	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
3995
3996	#undef CPUMHWVIRTDUMP_NONE
3997	#undef CPUMHWVIRTDUMP_COMMON
3998	#undef CPUMHWVIRTDUMP_SVM
3999	#undef CPUMHWVIRTDUMP_VMX
4000	#undef CPUMHWVIRTDUMP_LAST
4001	#undef CPUMHWVIRTDUMP_ALL
4002	}
4003
4004	/**
4005	* Display the current guest instruction
4006	*
4007	* @param pVM The cross context VM structure.
4008	* @param pHlp The info helper functions.
4009	* @param pszArgs Arguments, ignored.
4010	*/
4011	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4012	{
4013	NOREF(pszArgs);
4014
4015	PVMCPU pVCpu = VMMGetCpu(pVM);
4016	if (!pVCpu)
4017	pVCpu = pVM->apCpusR3[0];
4018
4019	char szInstruction[256];
4020	szInstruction[0] = '\0';
4021	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4022	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4023	}
4024
4025
4026	/**
4027	* Display the hypervisor cpu state.
4028	*
4029	* @param pVM The cross context VM structure.
4030	* @param pHlp The info helper functions.
4031	* @param pszArgs Arguments, ignored.
4032	*/
4033	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4034	{
4035	PVMCPU pVCpu = VMMGetCpu(pVM);
4036	if (!pVCpu)
4037	pVCpu = pVM->apCpusR3[0];
4038
4039	CPUMDUMPTYPE enmType;
4040	const char *pszComment;
4041	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4042	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4043
4044	pHlp->pfnPrintf(pHlp,
4045	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4046	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4047	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4048	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4049	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4050	}
4051
4052
4053	/**
4054	* Display the host cpu state.
4055	*
4056	* @param pVM The cross context VM structure.
4057	* @param pHlp The info helper functions.
4058	* @param pszArgs Arguments, ignored.
4059	*/
4060	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4061	{
4062	CPUMDUMPTYPE enmType;
4063	const char *pszComment;
4064	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4065	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4066
4067	PVMCPU pVCpu = VMMGetCpu(pVM);
4068	if (!pVCpu)
4069	pVCpu = pVM->apCpusR3[0];
4070	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4071
4072	/*
4073	* Format the EFLAGS.
4074	*/
4075	uint64_t efl = pCtx->rflags;
4076	char szEFlags[80];
4077	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4078
4079	/*
4080	* Format the registers.
4081	*/
4082	pHlp->pfnPrintf(pHlp,
4083	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4084	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4085	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4086	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4087	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4088	"r14=%016RX64 r15=%016RX64\n"
4089	"iopl=%d %31s\n"
4090	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4091	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4092	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4093	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4094	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4095	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4096	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4097	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4098	,
4099	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4100	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4101	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4102	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4103	pCtx->r11, pCtx->r12, pCtx->r13,
4104	pCtx->r14, pCtx->r15,
4105	X86_EFL_GET_IOPL(efl), szEFlags,
4106	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4107	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4108	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4109	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4110	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4111	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4112	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4113	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4114	}
4115
4116	/**
4117	* Structure used when disassembling and instructions in DBGF.
4118	* This is used so the reader function can get the stuff it needs.
4119	*/
4120	typedef struct CPUMDISASSTATE
4121	{
4122	/** Pointer to the CPU structure. */
4123	PDISCPUSTATE pCpu;
4124	/** Pointer to the VM. */
4125	PVM pVM;
4126	/** Pointer to the VMCPU. */
4127	PVMCPU pVCpu;
4128	/** Pointer to the first byte in the segment. */
4129	RTGCUINTPTR GCPtrSegBase;
4130	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4131	RTGCUINTPTR GCPtrSegEnd;
4132	/** The size of the segment minus 1. */
4133	RTGCUINTPTR cbSegLimit;
4134	/** Pointer to the current page - R3 Ptr. */
4135	void const *pvPageR3;
4136	/** Pointer to the current page - GC Ptr. */
4137	RTGCPTR pvPageGC;
4138	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4139	PGMPAGEMAPLOCK PageMapLock;
4140	/** Whether the PageMapLock is valid or not. */
4141	bool fLocked;
4142	/** 64 bits mode or not. */
4143	bool f64Bits;
4144	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4145
4146
4147	/**
4148	* @callback_method_impl{FNDISREADBYTES}
4149	*/
4150	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4151	{
4152	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4153	for (;;)
4154	{
4155	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4156
4157	/*
4158	* Need to update the page translation?
4159	*/
4160	if ( !pState->pvPageR3
4161	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4162	{
4163	/* translate the address */
4164	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4165
4166	/* Release mapping lock previously acquired. */
4167	if (pState->fLocked)
4168	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4169	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4170	if (RT_SUCCESS(rc))
4171	pState->fLocked = true;
4172	else
4173	{
4174	pState->fLocked = false;
4175	pState->pvPageR3 = NULL;
4176	return rc;
4177	}
4178	}
4179
4180	/*
4181	* Check the segment limit.
4182	*/
4183	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4184	return VERR_OUT_OF_SELECTOR_BOUNDS;
4185
4186	/*
4187	* Calc how much we can read.
4188	*/
4189	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4190	if (!pState->f64Bits)
4191	{
4192	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4193	if (cb > cbSeg && cbSeg)
4194	cb = cbSeg;
4195	}
4196	if (cb > cbMaxRead)
4197	cb = cbMaxRead;
4198
4199	/*
4200	* Read and advance or exit.
4201	*/
4202	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4203	offInstr += (uint8_t)cb;
4204	if (cb >= cbMinRead)
4205	{
4206	pDis->cbCachedInstr = offInstr;
4207	return VINF_SUCCESS;
4208	}
4209	cbMinRead -= (uint8_t)cb;
4210	cbMaxRead -= (uint8_t)cb;
4211	}
4212	}
4213
4214
4215	/**
4216	* Disassemble an instruction and return the information in the provided structure.
4217	*
4218	* @returns VBox status code.
4219	* @param pVM The cross context VM structure.
4220	* @param pVCpu The cross context virtual CPU structure.
4221	* @param pCtx Pointer to the guest CPU context.
4222	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4223	* @param pCpu Disassembly state.
4224	* @param pszPrefix String prefix for logging (debug only).
4225	*
4226	*/
4227	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4228	const char *pszPrefix)
4229	{
4230	CPUMDISASSTATE State;
4231	int rc;
4232
4233	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4234	State.pCpu = pCpu;
4235	State.pvPageGC = 0;
4236	State.pvPageR3 = NULL;
4237	State.pVM = pVM;
4238	State.pVCpu = pVCpu;
4239	State.fLocked = false;
4240	State.f64Bits = false;
4241
4242	/*
4243	* Get selector information.
4244	*/
4245	DISCPUMODE enmDisCpuMode;
4246	if ( (pCtx->cr0 & X86_CR0_PE)
4247	&& pCtx->eflags.Bits.u1VM == 0)
4248	{
4249	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4250	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4251	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4252	State.GCPtrSegBase = pCtx->cs.u64Base;
4253	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4254	State.cbSegLimit = pCtx->cs.u32Limit;
4255	enmDisCpuMode = (State.f64Bits)
4256	? DISCPUMODE_64BIT
4257	: pCtx->cs.Attr.n.u1DefBig
4258	? DISCPUMODE_32BIT
4259	: DISCPUMODE_16BIT;
4260	}
4261	else
4262	{
4263	/* real or V86 mode */
4264	enmDisCpuMode = DISCPUMODE_16BIT;
4265	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4266	State.GCPtrSegEnd = 0xFFFFFFFF;
4267	State.cbSegLimit = 0xFFFFFFFF;
4268	}
4269
4270	/*
4271	* Disassemble the instruction.
4272	*/
4273	uint32_t cbInstr;
4274	#ifndef LOG_ENABLED
4275	RT_NOREF_PV(pszPrefix);
4276	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4277	if (RT_SUCCESS(rc))
4278	{
4279	#else
4280	char szOutput[160];
4281	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4282	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4283	if (RT_SUCCESS(rc))
4284	{
4285	/* log it */
4286	if (pszPrefix)
4287	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4288	else
4289	Log(("%s", szOutput));
4290	#endif
4291	rc = VINF_SUCCESS;
4292	}
4293	else
4294	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4295
4296	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4297	if (State.fLocked)
4298	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4299
4300	return rc;
4301	}
4302
4303
4304
4305	/**
4306	* API for controlling a few of the CPU features found in CR4.
4307	*
4308	* Currently only X86_CR4_TSD is accepted as input.
4309	*
4310	* @returns VBox status code.
4311	*
4312	* @param pVM The cross context VM structure.
4313	* @param fOr The CR4 OR mask.
4314	* @param fAnd The CR4 AND mask.
4315	*/
4316	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4317	{
4318	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4319	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4320
4321	pVM->cpum.s.CR4.OrMask &= fAnd;
4322	pVM->cpum.s.CR4.OrMask \|= fOr;
4323
4324	return VINF_SUCCESS;
4325	}
4326
4327
4328	/**
4329	* Called when the ring-3 init phase completes.
4330	*
4331	* @returns VBox status code.
4332	* @param pVM The cross context VM structure.
4333	* @param enmWhat Which init phase.
4334	*/
4335	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4336	{
4337	switch (enmWhat)
4338	{
4339	case VMINITCOMPLETED_RING3:
4340	{
4341	/*
4342	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4343	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4344	*/
4345	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4346	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4347	{
4348	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4349
4350	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4351	if (fSupportsLongMode)
4352	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4353	}
4354
4355	/* Register statistic counters for MSRs. */
4356	cpumR3MsrRegStats(pVM);
4357
4358	/* Create VMX-preemption timer for nested guests if required. Must be
4359	done here as CPUM is initialized before TM. */
4360	if (pVM->cpum.s.GuestFeatures.fVmx)
4361	{
4362	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4363	{
4364	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4365	char szName[32];
4366	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4367	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4368	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4369	AssertLogRelRCReturn(rc, rc);
4370	}
4371	}
4372	break;
4373	}
4374
4375	default:
4376	break;
4377	}
4378	return VINF_SUCCESS;
4379	}
4380
4381
4382	/**
4383	* Called when the ring-0 init phases completed.
4384	*
4385	* @param pVM The cross context VM structure.
4386	*/
4387	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4388	{
4389	/*
4390	* Enable log buffering as we're going to log a lot of lines.
4391	*/
4392	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4393
4394	/*
4395	* Log the cpuid.
4396	*/
4397	RTCPUSET OnlineSet;
4398	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4399	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4400	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4401	RTCPUID cCores = RTMpGetCoreCount();
4402	if (cCores)
4403	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4404	LogRel(("*********************** CPUID dump **********************\n"));
4405	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4406	LogRel(("\n"));
4407	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4408	LogRel(("****************** End of CPUID dump ********************\n"));
4409
4410	/*
4411	* Log VT-x extended features.
4412	*
4413	* SVM features are currently all covered under CPUID so there is nothing
4414	* to do here for SVM.
4415	*/
4416	if (pVM->cpum.s.HostFeatures.fVmx)
4417	{
4418	LogRel(("********************* VT-x features *********************\n"));
4419	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4420	LogRel(("\n"));
4421	LogRel(("***************** End of VT-x features ******************\n"));
4422	}
4423
4424	/*
4425	* Restore the log buffering state to what it was previously.
4426	*/
4427	RTLogRelSetBuffering(fOldBuffered);
4428	}
4429

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 91301

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