CPUM.cpp@ 91358

Last change on this file since 91358 was 91358, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 More consistent naming of EPT/VPID caps.
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1	/* $Id: CPUM.cpp 91358 2021-09-24 09:49:20Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_cpum CPUM - CPU Monitor / Manager
19	*
20	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
21	* also responsible for lazy FPU handling and some of the context loading
22	* in raw mode.
23	*
24	* There are three CPU contexts, the most important one is the guest one (GC).
25	* When running in raw-mode (RC) there is a special hyper context for the VMM
26	* part that floats around inside the guest address space. When running in
27	* raw-mode, CPUM also maintains a host context for saving and restoring
28	* registers across world switches. This latter is done in cooperation with the
29	* world switcher (@see pg_vmm).
30	*
31	* @see grp_cpum
32	*
33	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
34	*
35	* TODO: proper write up, currently just some notes.
36	*
37	* The ring-0 FPU handling per OS:
38	*
39	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
40	* convention (Visual C++ doesn't seem to have a way to disable
41	* generating such code either), so CR0.TS/EM are always zero from what I
42	* can tell. We are also forced to always load/save the guest XMM0-XMM15
43	* registers when entering/leaving guest context. Interrupt handlers
44	* using FPU/SSE will offically have call save and restore functions
45	* exported by the kernel, if the really really have to use the state.
46	*
47	* - 32-bit windows does lazy FPU handling, I think, probably including
48	* lazying saving. The Windows Internals book states that it's a bad
49	* idea to use the FPU in kernel space. However, it looks like it will
50	* restore the FPU state of the current thread in case of a kernel \#NM.
51	* Interrupt handlers should be same as for 64-bit.
52	*
53	* - Darwin allows taking \#NM in kernel space, restoring current thread's
54	* state if I read the code correctly. It saves the FPU state of the
55	* outgoing thread, and uses CR0.TS to lazily load the state of the
56	* incoming one. No idea yet how the FPU is treated by interrupt
57	* handlers, i.e. whether they are allowed to disable the state or
58	* something.
59	*
60	* - Linux also allows \#NM in kernel space (don't know since when), and
61	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
62	* loads the incoming unless configured to agressivly load it. Interrupt
63	* handlers can ask whether they're allowed to use the FPU, and may
64	* freely trash the state if Linux thinks it has saved the thread's state
65	* already. This is a problem.
66	*
67	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
68	* context. When switching threads, the kernel will save the state of
69	* the outgoing thread and lazy load the incoming one using CR0.TS.
70	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
71	* to do stuff, HAT are among the users. The routines there will
72	* manually clear CR0.TS and save the XMM registers they use only if
73	* CR0.TS was zero upon entry. They will skip it when not, because as
74	* mentioned above, the FPU state is saved when switching away from a
75	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
76	* preserve. This is a problem if we restore CR0.TS to 1 after loading
77	* the guest state.
78	*
79	* - FreeBSD - no idea yet.
80	*
81	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
82	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
83	* FPU states.
84	*
85	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
86	* saving and restoring the host and guest states. The motivation for this
87	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
88	*
89	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
90	* state and only restore it once we've restore the host FPU state. This has the
91	* accidental side effect of triggering Solaris to preserve XMM registers in
92	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
93	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
94	*
95	*
96	* @section sec_cpum_logging Logging Level Assignments.
97	*
98	* Following log level assignments:
99	* - Log6 is used for FPU state management.
100	* - Log7 is used for FPU state actualization.
101	*
102	*/
103
104
105	/*********************************************************************************************************************************
106	* Header Files *
107	*********************************************************************************************************************************/
108	#define LOG_GROUP LOG_GROUP_CPUM
109	#include <VBox/vmm/cpum.h>
110	#include <VBox/vmm/cpumdis.h>
111	#include <VBox/vmm/cpumctx-v1_6.h>
112	#include <VBox/vmm/pgm.h>
113	#include <VBox/vmm/apic.h>
114	#include <VBox/vmm/mm.h>
115	#include <VBox/vmm/em.h>
116	#include <VBox/vmm/iem.h>
117	#include <VBox/vmm/selm.h>
118	#include <VBox/vmm/dbgf.h>
119	#include <VBox/vmm/hm.h>
120	#include <VBox/vmm/hmvmxinline.h>
121	#include <VBox/vmm/ssm.h>
122	#include "CPUMInternal.h"
123	#include <VBox/vmm/vm.h>
124
125	#include <VBox/param.h>
126	#include <VBox/dis.h>
127	#include <VBox/err.h>
128	#include <VBox/log.h>
129	#include <iprt/asm-amd64-x86.h>
130	#include <iprt/assert.h>
131	#include <iprt/cpuset.h>
132	#include <iprt/mem.h>
133	#include <iprt/mp.h>
134	#include <iprt/string.h>
135
136
137	/*********************************************************************************************************************************
138	* Defined Constants And Macros *
139	*********************************************************************************************************************************/
140	/**
141	* This was used in the saved state up to the early life of version 14.
142	*
143	* It indicates that we may have some out-of-sync hidden segement registers.
144	* It is only relevant for raw-mode.
145	*/
146	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
147
148
149	/*********************************************************************************************************************************
150	* Structures and Typedefs *
151	*********************************************************************************************************************************/
152
153	/**
154	* What kind of cpu info dump to perform.
155	*/
156	typedef enum CPUMDUMPTYPE
157	{
158	CPUMDUMPTYPE_TERSE,
159	CPUMDUMPTYPE_DEFAULT,
160	CPUMDUMPTYPE_VERBOSE
161	} CPUMDUMPTYPE;
162	/** Pointer to a cpu info dump type. */
163	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
164
165
166	/*********************************************************************************************************************************
167	* Internal Functions *
168	*********************************************************************************************************************************/
169	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
170	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
171	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
172	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
173	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
174	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
175	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
176	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
177	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
178	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
179	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
180
181
182	/*********************************************************************************************************************************
183	* Global Variables *
184	*********************************************************************************************************************************/
185	/** Saved state field descriptors for CPUMCTX. */
186	static const SSMFIELD g_aCpumCtxFields[] =
187	{
188	SSMFIELD_ENTRY( CPUMCTX, rdi),
189	SSMFIELD_ENTRY( CPUMCTX, rsi),
190	SSMFIELD_ENTRY( CPUMCTX, rbp),
191	SSMFIELD_ENTRY( CPUMCTX, rax),
192	SSMFIELD_ENTRY( CPUMCTX, rbx),
193	SSMFIELD_ENTRY( CPUMCTX, rdx),
194	SSMFIELD_ENTRY( CPUMCTX, rcx),
195	SSMFIELD_ENTRY( CPUMCTX, rsp),
196	SSMFIELD_ENTRY( CPUMCTX, rflags),
197	SSMFIELD_ENTRY( CPUMCTX, rip),
198	SSMFIELD_ENTRY( CPUMCTX, r8),
199	SSMFIELD_ENTRY( CPUMCTX, r9),
200	SSMFIELD_ENTRY( CPUMCTX, r10),
201	SSMFIELD_ENTRY( CPUMCTX, r11),
202	SSMFIELD_ENTRY( CPUMCTX, r12),
203	SSMFIELD_ENTRY( CPUMCTX, r13),
204	SSMFIELD_ENTRY( CPUMCTX, r14),
205	SSMFIELD_ENTRY( CPUMCTX, r15),
206	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
207	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
208	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
209	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
210	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
211	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
212	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
213	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
214	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
215	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
216	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
217	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
218	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
219	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
220	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
221	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
222	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
223	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
224	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
225	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
226	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
227	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
228	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
229	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
230	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, cr0),
243	SSMFIELD_ENTRY( CPUMCTX, cr2),
244	SSMFIELD_ENTRY( CPUMCTX, cr3),
245	SSMFIELD_ENTRY( CPUMCTX, cr4),
246	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
247	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
248	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
249	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
250	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
251	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
252	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
253	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
254	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
255	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
256	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
257	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
258	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
259	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
260	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
261	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
262	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
263	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
264	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
265	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
266	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
267	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
268	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
269	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
270	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
271	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
272	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
273	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
274	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
275	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
276	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
277	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
278	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
279	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
280	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
281	SSMFIELD_ENTRY_TERM()
282	};
283
284	/** Saved state field descriptors for SVM nested hardware-virtualization
285	* Host State. */
286	static const SSMFIELD g_aSvmHwvirtHostState[] =
287	{
288	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
289	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
290	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
291	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
292	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
293	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
294	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
295	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
296	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
297	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
298	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
299	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
300	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
301	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
302	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
303	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
304	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
305	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
306	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
307	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
308	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
309	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
310	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
311	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
312	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
324	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
325	SSMFIELD_ENTRY_TERM()
326	};
327
328	/** Saved state field descriptors for VMX nested hardware-virtualization
329	* VMCS. */
330	static const SSMFIELD g_aVmxHwvirtVmcs[] =
331	{
332	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
333	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
334	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
335	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
336	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
337
338	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
339
340	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
341	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
342	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
343	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
344	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
345	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
346	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
347	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
348	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
349
350	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
351	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
352
353	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
354	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
355	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
356	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
357	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
358	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
360
361	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
362	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
363	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
364	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
365
366	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
367	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
368	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
369	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
370	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
371	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
372	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
373	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
374	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
375	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
376	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
377	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
378	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
379	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
380	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
381	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
382	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
383	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
384	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
385
386	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
387	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
388	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
389	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
390	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
391	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
392	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
393	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
394	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
395	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
396	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
397	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
398	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
399	SSMFIELD_ENTRY( VMXVVMCS, u64EptpPtr),
400	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
401	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
402	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
403	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
404	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
405	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
406	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
407	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
408	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
409	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
410	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
411	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
412	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
413	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
414	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
415
416	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
417	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
418	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
419	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
420	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
421	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
422	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
423	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
424	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
425
426	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
427	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
428	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
429	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
430	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
431	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
432	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
433	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
434
435	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
436	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
437
438	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
439	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
440	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
441	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
442	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
443
444	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
445	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
446	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
447	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
448	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
449	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
450	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
451	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
452	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
453	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
454	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
455	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
456	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
457	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
458	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
459	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
460
461	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
462	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
463	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
464	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
465	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
466	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
467	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
468	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
469	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
470	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
471	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
472
473	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
474	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
475	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
476	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
477	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
478	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
479	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
480	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
481	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
482	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
483	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
484	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
485	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
486	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
487	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
488	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
489	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
490	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
491	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
492	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
493	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
494	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
495	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
496	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
497
498	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
499	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
500	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
501	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
502	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
503	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
504	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
505	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
506	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
507	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
508	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
509	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
510	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
511
512	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
513	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
514	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
515	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
516	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
517	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
518	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
519	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
520	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
521	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
522	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
523	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
524	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
525	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
526	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
532	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
533	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
534	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
535	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
536
537	SSMFIELD_ENTRY_TERM()
538	};
539
540	/** Saved state field descriptors for CPUMCTX. */
541	static const SSMFIELD g_aCpumX87Fields[] =
542	{
543	SSMFIELD_ENTRY( X86FXSTATE, FCW),
544	SSMFIELD_ENTRY( X86FXSTATE, FSW),
545	SSMFIELD_ENTRY( X86FXSTATE, FTW),
546	SSMFIELD_ENTRY( X86FXSTATE, FOP),
547	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
548	SSMFIELD_ENTRY( X86FXSTATE, CS),
549	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
550	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
551	SSMFIELD_ENTRY( X86FXSTATE, DS),
552	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
553	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
554	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
555	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
556	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
557	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
558	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
559	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
560	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
561	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
562	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
563	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
564	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
565	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
566	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
567	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
568	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
569	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
570	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
571	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
572	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
573	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
574	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
575	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
576	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
577	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
578	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
579	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
580	SSMFIELD_ENTRY_TERM()
581	};
582
583	/** Saved state field descriptors for X86XSAVEHDR. */
584	static const SSMFIELD g_aCpumXSaveHdrFields[] =
585	{
586	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
587	SSMFIELD_ENTRY_TERM()
588	};
589
590	/** Saved state field descriptors for X86XSAVEYMMHI. */
591	static const SSMFIELD g_aCpumYmmHiFields[] =
592	{
593	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
594	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
595	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
596	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
597	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
598	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
599	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
600	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
601	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
602	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
603	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
604	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
605	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
606	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
607	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
608	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
609	SSMFIELD_ENTRY_TERM()
610	};
611
612	/** Saved state field descriptors for X86XSAVEBNDREGS. */
613	static const SSMFIELD g_aCpumBndRegsFields[] =
614	{
615	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
616	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
617	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
618	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
619	SSMFIELD_ENTRY_TERM()
620	};
621
622	/** Saved state field descriptors for X86XSAVEBNDCFG. */
623	static const SSMFIELD g_aCpumBndCfgFields[] =
624	{
625	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
626	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
627	SSMFIELD_ENTRY_TERM()
628	};
629
630	#if 0 /** @todo */
631	/** Saved state field descriptors for X86XSAVEOPMASK. */
632	static const SSMFIELD g_aCpumOpmaskFields[] =
633	{
634	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
635	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
636	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
637	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
638	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
639	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
640	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
641	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
642	SSMFIELD_ENTRY_TERM()
643	};
644	#endif
645
646	/** Saved state field descriptors for X86XSAVEZMMHI256. */
647	static const SSMFIELD g_aCpumZmmHi256Fields[] =
648	{
649	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
650	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
651	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
652	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
653	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
654	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
655	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
656	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
657	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
658	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
659	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
660	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
661	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
662	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
663	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
664	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
665	SSMFIELD_ENTRY_TERM()
666	};
667
668	/** Saved state field descriptors for X86XSAVEZMM16HI. */
669	static const SSMFIELD g_aCpumZmm16HiFields[] =
670	{
671	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
672	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
673	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
674	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
675	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
676	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
677	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
678	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
679	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
680	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
681	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
682	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
683	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
684	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
685	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
686	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
687	SSMFIELD_ENTRY_TERM()
688	};
689
690
691
692	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
693	* registeres changed. */
694	static const SSMFIELD g_aCpumX87FieldsMem[] =
695	{
696	SSMFIELD_ENTRY( X86FXSTATE, FCW),
697	SSMFIELD_ENTRY( X86FXSTATE, FSW),
698	SSMFIELD_ENTRY( X86FXSTATE, FTW),
699	SSMFIELD_ENTRY( X86FXSTATE, FOP),
700	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
701	SSMFIELD_ENTRY( X86FXSTATE, CS),
702	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
703	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
704	SSMFIELD_ENTRY( X86FXSTATE, DS),
705	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
706	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
707	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
708	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
709	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
710	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
711	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
712	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
713	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
714	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
715	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
716	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
717	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
718	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
719	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
720	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
721	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
722	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
723	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
724	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
725	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
726	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
727	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
728	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
729	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
730	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
731	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
732	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
733	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
734	};
735
736	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
737	* registeres changed. */
738	static const SSMFIELD g_aCpumCtxFieldsMem[] =
739	{
740	SSMFIELD_ENTRY( CPUMCTX, rdi),
741	SSMFIELD_ENTRY( CPUMCTX, rsi),
742	SSMFIELD_ENTRY( CPUMCTX, rbp),
743	SSMFIELD_ENTRY( CPUMCTX, rax),
744	SSMFIELD_ENTRY( CPUMCTX, rbx),
745	SSMFIELD_ENTRY( CPUMCTX, rdx),
746	SSMFIELD_ENTRY( CPUMCTX, rcx),
747	SSMFIELD_ENTRY( CPUMCTX, rsp),
748	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
749	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
750	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
751	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
752	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
753	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
754	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
755	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
756	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
757	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
758	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
759	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
760	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
761	SSMFIELD_ENTRY( CPUMCTX, rflags),
762	SSMFIELD_ENTRY( CPUMCTX, rip),
763	SSMFIELD_ENTRY( CPUMCTX, r8),
764	SSMFIELD_ENTRY( CPUMCTX, r9),
765	SSMFIELD_ENTRY( CPUMCTX, r10),
766	SSMFIELD_ENTRY( CPUMCTX, r11),
767	SSMFIELD_ENTRY( CPUMCTX, r12),
768	SSMFIELD_ENTRY( CPUMCTX, r13),
769	SSMFIELD_ENTRY( CPUMCTX, r14),
770	SSMFIELD_ENTRY( CPUMCTX, r15),
771	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
772	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
773	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
774	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
775	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
776	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
777	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
778	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
779	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
780	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
781	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
782	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
783	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
784	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
785	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
786	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
787	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
788	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
789	SSMFIELD_ENTRY( CPUMCTX, cr0),
790	SSMFIELD_ENTRY( CPUMCTX, cr2),
791	SSMFIELD_ENTRY( CPUMCTX, cr3),
792	SSMFIELD_ENTRY( CPUMCTX, cr4),
793	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
794	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
795	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
796	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
797	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
798	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
799	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
800	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
801	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
802	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
803	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
804	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
805	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
806	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
807	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
808	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
809	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
810	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
811	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
812	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
813	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
814	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
815	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
816	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
817	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
818	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
819	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
820	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
821	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
822	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
823	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
824	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
825	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
826	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
827	SSMFIELD_ENTRY_TERM()
828	};
829
830	/** Saved state field descriptors for CPUMCTX_VER1_6. */
831	static const SSMFIELD g_aCpumX87FieldsV16[] =
832	{
833	SSMFIELD_ENTRY( X86FXSTATE, FCW),
834	SSMFIELD_ENTRY( X86FXSTATE, FSW),
835	SSMFIELD_ENTRY( X86FXSTATE, FTW),
836	SSMFIELD_ENTRY( X86FXSTATE, FOP),
837	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
838	SSMFIELD_ENTRY( X86FXSTATE, CS),
839	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
840	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
841	SSMFIELD_ENTRY( X86FXSTATE, DS),
842	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
843	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
844	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
845	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
846	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
847	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
848	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
849	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
850	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
851	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
852	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
853	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
854	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
855	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
856	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
857	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
858	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
859	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
860	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
861	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
862	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
863	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
864	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
865	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
866	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
867	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
868	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
869	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
870	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
871	SSMFIELD_ENTRY_TERM()
872	};
873
874	/** Saved state field descriptors for CPUMCTX_VER1_6. */
875	static const SSMFIELD g_aCpumCtxFieldsV16[] =
876	{
877	SSMFIELD_ENTRY( CPUMCTX, rdi),
878	SSMFIELD_ENTRY( CPUMCTX, rsi),
879	SSMFIELD_ENTRY( CPUMCTX, rbp),
880	SSMFIELD_ENTRY( CPUMCTX, rax),
881	SSMFIELD_ENTRY( CPUMCTX, rbx),
882	SSMFIELD_ENTRY( CPUMCTX, rdx),
883	SSMFIELD_ENTRY( CPUMCTX, rcx),
884	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
885	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
886	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
887	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
888	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
889	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
890	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
891	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
892	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
893	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
894	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
895	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
896	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
897	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
898	SSMFIELD_ENTRY( CPUMCTX, rflags),
899	SSMFIELD_ENTRY( CPUMCTX, rip),
900	SSMFIELD_ENTRY( CPUMCTX, r8),
901	SSMFIELD_ENTRY( CPUMCTX, r9),
902	SSMFIELD_ENTRY( CPUMCTX, r10),
903	SSMFIELD_ENTRY( CPUMCTX, r11),
904	SSMFIELD_ENTRY( CPUMCTX, r12),
905	SSMFIELD_ENTRY( CPUMCTX, r13),
906	SSMFIELD_ENTRY( CPUMCTX, r14),
907	SSMFIELD_ENTRY( CPUMCTX, r15),
908	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
909	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
910	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
911	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
912	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
913	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
914	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
915	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
916	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
917	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
918	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
919	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
920	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
921	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
922	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
923	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
924	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
925	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
926	SSMFIELD_ENTRY( CPUMCTX, cr0),
927	SSMFIELD_ENTRY( CPUMCTX, cr2),
928	SSMFIELD_ENTRY( CPUMCTX, cr3),
929	SSMFIELD_ENTRY( CPUMCTX, cr4),
930	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
931	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
932	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
933	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
934	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
935	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
936	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
937	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
938	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
939	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
940	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
941	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
942	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
943	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
944	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
945	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
946	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
947	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
948	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
949	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
950	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
951	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
952	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
953	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
954	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
955	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
956	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
957	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
958	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
959	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
960	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
961	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
962	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
963	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
964	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
965	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
966	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
967	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
968	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
969	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
970	SSMFIELD_ENTRY_TERM()
971	};
972
973
974	/**
975	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
976	*
977	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
978	* (last instruction pointer, last data pointer, last opcode) except when the ES
979	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
980	* clear these registers there is potential, local FPU leakage from a process
981	* using the FPU to another.
982	*
983	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
984	*
985	* @param pVM The cross context VM structure.
986	*/
987	static void cpumR3CheckLeakyFpu(PVM pVM)
988	{
989	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
990	uint32_t const u32Family = u32CpuVersion >> 8;
991	if ( u32Family >= 6 /* K7 and higher */
992	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
993	{
994	uint32_t cExt = ASMCpuId_EAX(0x80000000);
995	if (ASMIsValidExtRange(cExt))
996	{
997	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
998	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
999	{
1000	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1001	{
1002	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1003	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1004	}
1005	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1006	}
1007	}
1008	}
1009	}
1010
1011
1012	/**
1013	* Initialize SVM hardware virtualization state (used to allocate it).
1014	*
1015	* @param pVM The cross context VM structure.
1016	*/
1017	static void cpumR3InitSvmHwVirtState(PVM pVM)
1018	{
1019	Assert(pVM->cpum.s.GuestFeatures.fSvm);
1020
1021	LogRel(("CPUM: AMD-V nested-guest init\n"));
1022	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1023	{
1024	PVMCPU pVCpu = pVM->apCpusR3[i];
1025	pVCpu->cpum.s.Guest.hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1026
1027	AssertCompile(SVM_VMCB_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.Vmcb));
1028	AssertCompile(SVM_MSRPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abMsrBitmap));
1029	AssertCompile(SVM_IOPM_PAGES * X86_PAGE_SIZE == sizeof(pVCpu->cpum.s.Guest.hwvirt.svm.abIoBitmap));
1030	}
1031	}
1032
1033
1034	/**
1035	* Resets per-VCPU SVM hardware virtualization state.
1036	*
1037	* @param pVCpu The cross context virtual CPU structure.
1038	*/
1039	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1040	{
1041	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1042	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1043
1044	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1045	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1046	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1047	}
1048
1049
1050	/**
1051	* Allocates memory for the VMX hardware virtualization state.
1052	*
1053	* @param pVM The cross context VM structure.
1054	*/
1055	static void cpumR3InitVmxHwVirtState(PVM pVM)
1056	{
1057	LogRel(("CPUM: VT-x nested-guest init\n"));
1058	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1059	{
1060	PVMCPU pVCpu = pVM->apCpusR3[i];
1061	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1062
1063	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1064
1065	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1066	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1067	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1068	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1069	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1070	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1071	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1072	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1073	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1074	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1075	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1076	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1077	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1078	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1079	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1080	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1081	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1082	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1083	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_PAGES * X86_PAGE_SIZE);
1084	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVirtApicPage) == VMX_V_VIRT_APIC_SIZE);
1085
1086	/*
1087	* Zero out all allocated pages (should compress well for saved-state).
1088	*/
1089	/** @todo r=bird: this is and always was unnecessary - they are already zeroed. */
1090	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1091	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1092	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1093	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1094	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1095	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1096	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1097	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1098	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1099	RT_ZERO(pCtx->hwvirt.vmx.abVirtApicPage);
1100	}
1101	}
1102
1103
1104	/**
1105	* Resets per-VCPU VMX hardware virtualization state.
1106	*
1107	* @param pVCpu The cross context virtual CPU structure.
1108	*/
1109	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1110	{
1111	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1112	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1113
1114	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1115	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1116	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1117	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1118	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1119	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1120	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1121	/* Don't reset diagnostics here. */
1122
1123	/* Stop any VMX-preemption timer. */
1124	CPUMStopGuestVmxPremptTimer(pVCpu);
1125
1126	/* Clear all nested-guest FFs. */
1127	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1128	}
1129
1130
1131	/**
1132	* Displays the host and guest VMX features.
1133	*
1134	* @param pVM The cross context VM structure.
1135	* @param pHlp The info helper functions.
1136	* @param pszArgs "terse", "default" or "verbose".
1137	*/
1138	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1139	{
1140	RT_NOREF(pszArgs);
1141	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1142	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1143	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1144	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1145	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1146	{
1147	#define VMXFEATDUMP(a_szDesc, a_Var) \
1148	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1149
1150	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1151	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1152	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1153	/* Basic. */
1154	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1155	/* Pin-based controls. */
1156	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1157	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1158	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1159	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1160	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1161	/* Processor-based controls. */
1162	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1163	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1164	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1165	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1166	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1167	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1168	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1169	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1170	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1171	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1172	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1173	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1174	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1175	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1176	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1177	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1178	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1179	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1180	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1181	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1182	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1183	/* Secondary processor-based controls. */
1184	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1185	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1186	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1187	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1188	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1189	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1190	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1191	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1192	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1193	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1194	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1195	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1196	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1197	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1198	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1199	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1200	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1201	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1202	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1203	/* VM-entry controls. */
1204	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1205	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1206	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1207	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1208	/* VM-exit controls. */
1209	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1210	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1211	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1212	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1213	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1214	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1215	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1216	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1217	/* Miscellaneous data. */
1218	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1219	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxIntelPt);
1220	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1221	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1222	#undef VMXFEATDUMP
1223	}
1224	else
1225	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1226	}
1227
1228
1229	/**
1230	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1231	* or NEM) is allowed.
1232	*
1233	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1234	* otherwise.
1235	* @param pVM The cross context VM structure.
1236	*/
1237	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1238	{
1239	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1240	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1241	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1242	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1243	return true;
1244	#else
1245	NOREF(pVM);
1246	#endif
1247	return false;
1248	}
1249
1250
1251	/**
1252	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1253	*
1254	* @param pVM The cross context VM structure.
1255	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1256	* and no hardware-assisted nested-guest execution is
1257	* possible for this VM.
1258	* @param pGuestFeatures The guest features to use (only VMX features are
1259	* accessed).
1260	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1261	*
1262	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1263	*/
1264	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1265	{
1266	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1267
1268	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1269	Assert(pGuestFeatures->fVmx);
1270
1271	/*
1272	* We don't support the following MSRs yet:
1273	* - True Pin-based VM-execution controls.
1274	* - True Processor-based VM-execution controls.
1275	* - True VM-entry VM-execution controls.
1276	* - True VM-exit VM-execution controls.
1277	*/
1278
1279	/* Basic information. */
1280	{
1281	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1282	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1283	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1284	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1285	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1286	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1287	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, 0 );
1288	pGuestVmxMsrs->u64Basic = u64Basic;
1289	}
1290
1291	/* Pin-based VM-execution controls. */
1292	{
1293	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1294	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1295	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1296	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1297	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1298	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1299	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1300	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1301	fAllowed0, fAllowed1, fFeatures));
1302	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1303	}
1304
1305	/* Processor-based VM-execution controls. */
1306	{
1307	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1308	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1309	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1310	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1311	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1312	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1313	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1314	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1315	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1316	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1317	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1318	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1319	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1320	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1321	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1322	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1323	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1324	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1325	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1326	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1327	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1328	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1329	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1330	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1331	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1332	fAllowed1, fFeatures));
1333	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1334	}
1335
1336	/* Secondary processor-based VM-execution controls. */
1337	if (pGuestFeatures->fVmxSecondaryExecCtls)
1338	{
1339	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1340	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1341	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1342	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1343	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1344	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1345	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1346	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
1347	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1348	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1349	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1350	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1351	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1352	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1353	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1354	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1355	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1356	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1357	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1358	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT );
1359	uint32_t const fAllowed0 = 0;
1360	uint32_t const fAllowed1 = fFeatures;
1361	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1362	}
1363
1364	/* Tertiary processor-based VM-execution controls. */
1365	if (pGuestFeatures->fVmxTertiaryExecCtls)
1366	{
1367	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1368	}
1369
1370	/* VM-exit controls. */
1371	{
1372	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1373	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1374	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1375	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1376	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1377	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1378	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1379	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT );
1380	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1381	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1382	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1383	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1384	fAllowed1, fFeatures));
1385	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1386	}
1387
1388	/* VM-entry controls. */
1389	{
1390	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1391	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1392	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1393	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1394	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1395	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1396	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1397	fAllowed1, fFeatures));
1398	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1399	}
1400
1401	/* Miscellaneous data. */
1402	{
1403	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1404
1405	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1406	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1407	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1408	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1409	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1410	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxIntelPt )
1411	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1412	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1413	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1414	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1415	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1416	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1417	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1418	}
1419
1420	/* CR0 Fixed-0. */
1421	pGuestVmxMsrs->u64Cr0Fixed0 = pGuestFeatures->fVmxUnrestrictedGuest ? VMX_V_CR0_FIXED0_UX : VMX_V_CR0_FIXED0;
1422
1423	/* CR0 Fixed-1. */
1424	{
1425	/*
1426	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1427	* This is different from CR4 fixed-1 bits which are reported as per the
1428	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1429	*/
1430	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : 0xffffffff;
1431	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1432	}
1433
1434	/* CR4 Fixed-0. */
1435	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1436
1437	/* CR4 Fixed-1. */
1438	{
1439	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1440	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1441	}
1442
1443	/* VMCS Enumeration. */
1444	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1445
1446	/* VPID and EPT Capabilities. */
1447	if (pGuestFeatures->fVmxEpt)
1448	{
1449	/*
1450	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1451	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1452	* when INVVPID instruction is supported just to be more compatible with guest
1453	* hypervisors that may make assumptions by only looking at this MSR even though they
1454	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1455	*
1456	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1457	* See Intel spec. 30.3 "VMX Instructions".
1458	*/
1459	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1460	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1461
1462	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_RWX_X_ONLY);
1463	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1464	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1465	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1466	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1467	uint8_t const f1GPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDPTE_1G);
1468	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1469	uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY);
1470	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1471	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1472	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1473	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1474	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1475	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1476	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_RWX_X_ONLY, fExecOnly)
1477	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1478	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1479	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1480	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1481	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, f1GPage)
1482	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1483	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, fAccessDirty)
1484	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1485	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1486	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1487	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1488	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1489	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1490	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1491	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1492	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1493	}
1494
1495	/* VM Functions. */
1496	if (pGuestFeatures->fVmxVmFunc)
1497	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1498	}
1499
1500
1501	/**
1502	* Checks whether the given guest CPU VMX features are compatible with the provided
1503	* base features.
1504	*
1505	* @returns @c true if compatible, @c false otherwise.
1506	* @param pVM The cross context VM structure.
1507	* @param pBase The base VMX CPU features.
1508	* @param pGst The guest VMX CPU features.
1509	*
1510	* @remarks Only VMX feature bits are examined.
1511	*/
1512	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1513	{
1514	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1515	return false;
1516
1517	/* Check first set of feature bits. */
1518	{
1519	uint64_t const fBase = ((uint64_t)pBase->fVmxInsOutInfo << 0) \| ((uint64_t)pBase->fVmxExtIntExit << 1)
1520	\| ((uint64_t)pBase->fVmxNmiExit << 2) \| ((uint64_t)pBase->fVmxVirtNmi << 3)
1521	\| ((uint64_t)pBase->fVmxPreemptTimer << 4) \| ((uint64_t)pBase->fVmxPostedInt << 5)
1522	\| ((uint64_t)pBase->fVmxIntWindowExit << 6) \| ((uint64_t)pBase->fVmxTscOffsetting << 7)
1523	\| ((uint64_t)pBase->fVmxHltExit << 8) \| ((uint64_t)pBase->fVmxInvlpgExit << 9)
1524	\| ((uint64_t)pBase->fVmxMwaitExit << 10) \| ((uint64_t)pBase->fVmxRdpmcExit << 11)
1525	\| ((uint64_t)pBase->fVmxRdtscExit << 12) \| ((uint64_t)pBase->fVmxCr3LoadExit << 13)
1526	\| ((uint64_t)pBase->fVmxCr3StoreExit << 14) \| ((uint64_t)pBase->fVmxCr8LoadExit << 15)
1527	\| ((uint64_t)pBase->fVmxCr8StoreExit << 16) \| ((uint64_t)pBase->fVmxUseTprShadow << 17)
1528	\| ((uint64_t)pBase->fVmxNmiWindowExit << 18) \| ((uint64_t)pBase->fVmxMovDRxExit << 19)
1529	\| ((uint64_t)pBase->fVmxUncondIoExit << 20) \| ((uint64_t)pBase->fVmxUseIoBitmaps << 21)
1530	\| ((uint64_t)pBase->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pBase->fVmxUseMsrBitmaps << 23)
1531	\| ((uint64_t)pBase->fVmxMonitorExit << 24) \| ((uint64_t)pBase->fVmxPauseExit << 25)
1532	\| ((uint64_t)pBase->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pBase->fVmxVirtApicAccess << 27)
1533	\| ((uint64_t)pBase->fVmxEpt << 28) \| ((uint64_t)pBase->fVmxDescTableExit << 29)
1534	\| ((uint64_t)pBase->fVmxRdtscp << 30) \| ((uint64_t)pBase->fVmxVirtX2ApicMode << 31)
1535	\| ((uint64_t)pBase->fVmxVpid << 32) \| ((uint64_t)pBase->fVmxWbinvdExit << 33)
1536	\| ((uint64_t)pBase->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pBase->fVmxApicRegVirt << 35)
1537	\| ((uint64_t)pBase->fVmxVirtIntDelivery << 36) \| ((uint64_t)pBase->fVmxPauseLoopExit << 37)
1538	\| ((uint64_t)pBase->fVmxRdrandExit << 38) \| ((uint64_t)pBase->fVmxInvpcid << 39)
1539	\| ((uint64_t)pBase->fVmxVmFunc << 40) \| ((uint64_t)pBase->fVmxVmcsShadowing << 41)
1540	\| ((uint64_t)pBase->fVmxRdseedExit << 42) \| ((uint64_t)pBase->fVmxPml << 43)
1541	\| ((uint64_t)pBase->fVmxEptXcptVe << 44) \| ((uint64_t)pBase->fVmxXsavesXrstors << 45)
1542	\| ((uint64_t)pBase->fVmxUseTscScaling << 46) \| ((uint64_t)pBase->fVmxEntryLoadDebugCtls << 47)
1543	\| ((uint64_t)pBase->fVmxIa32eModeGuest << 48) \| ((uint64_t)pBase->fVmxEntryLoadEferMsr << 49)
1544	\| ((uint64_t)pBase->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pBase->fVmxExitSaveDebugCtls << 51)
1545	\| ((uint64_t)pBase->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pBase->fVmxExitAckExtInt << 53)
1546	\| ((uint64_t)pBase->fVmxExitSavePatMsr << 54) \| ((uint64_t)pBase->fVmxExitLoadPatMsr << 55)
1547	\| ((uint64_t)pBase->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pBase->fVmxExitLoadEferMsr << 57)
1548	\| ((uint64_t)pBase->fVmxSavePreemptTimer << 58) \| ((uint64_t)pBase->fVmxExitSaveEferLma << 59)
1549	\| ((uint64_t)pBase->fVmxIntelPt << 60) \| ((uint64_t)pBase->fVmxVmwriteAll << 61)
1550	\| ((uint64_t)pBase->fVmxEntryInjectSoftInt << 62);
1551
1552	uint64_t const fGst = ((uint64_t)pGst->fVmxInsOutInfo << 0) \| ((uint64_t)pGst->fVmxExtIntExit << 1)
1553	\| ((uint64_t)pGst->fVmxNmiExit << 2) \| ((uint64_t)pGst->fVmxVirtNmi << 3)
1554	\| ((uint64_t)pGst->fVmxPreemptTimer << 4) \| ((uint64_t)pGst->fVmxPostedInt << 5)
1555	\| ((uint64_t)pGst->fVmxIntWindowExit << 6) \| ((uint64_t)pGst->fVmxTscOffsetting << 7)
1556	\| ((uint64_t)pGst->fVmxHltExit << 8) \| ((uint64_t)pGst->fVmxInvlpgExit << 9)
1557	\| ((uint64_t)pGst->fVmxMwaitExit << 10) \| ((uint64_t)pGst->fVmxRdpmcExit << 11)
1558	\| ((uint64_t)pGst->fVmxRdtscExit << 12) \| ((uint64_t)pGst->fVmxCr3LoadExit << 13)
1559	\| ((uint64_t)pGst->fVmxCr3StoreExit << 14) \| ((uint64_t)pGst->fVmxCr8LoadExit << 15)
1560	\| ((uint64_t)pGst->fVmxCr8StoreExit << 16) \| ((uint64_t)pGst->fVmxUseTprShadow << 17)
1561	\| ((uint64_t)pGst->fVmxNmiWindowExit << 18) \| ((uint64_t)pGst->fVmxMovDRxExit << 19)
1562	\| ((uint64_t)pGst->fVmxUncondIoExit << 20) \| ((uint64_t)pGst->fVmxUseIoBitmaps << 21)
1563	\| ((uint64_t)pGst->fVmxMonitorTrapFlag << 22) \| ((uint64_t)pGst->fVmxUseMsrBitmaps << 23)
1564	\| ((uint64_t)pGst->fVmxMonitorExit << 24) \| ((uint64_t)pGst->fVmxPauseExit << 25)
1565	\| ((uint64_t)pGst->fVmxSecondaryExecCtls << 26) \| ((uint64_t)pGst->fVmxVirtApicAccess << 27)
1566	\| ((uint64_t)pGst->fVmxEpt << 28) \| ((uint64_t)pGst->fVmxDescTableExit << 29)
1567	\| ((uint64_t)pGst->fVmxRdtscp << 30) \| ((uint64_t)pGst->fVmxVirtX2ApicMode << 31)
1568	\| ((uint64_t)pGst->fVmxVpid << 32) \| ((uint64_t)pGst->fVmxWbinvdExit << 33)
1569	\| ((uint64_t)pGst->fVmxUnrestrictedGuest << 34) \| ((uint64_t)pGst->fVmxApicRegVirt << 35)
1570	\| ((uint64_t)pGst->fVmxVirtIntDelivery << 36) \| ((uint64_t)pGst->fVmxPauseLoopExit << 37)
1571	\| ((uint64_t)pGst->fVmxRdrandExit << 38) \| ((uint64_t)pGst->fVmxInvpcid << 39)
1572	\| ((uint64_t)pGst->fVmxVmFunc << 40) \| ((uint64_t)pGst->fVmxVmcsShadowing << 41)
1573	\| ((uint64_t)pGst->fVmxRdseedExit << 42) \| ((uint64_t)pGst->fVmxPml << 43)
1574	\| ((uint64_t)pGst->fVmxEptXcptVe << 44) \| ((uint64_t)pGst->fVmxXsavesXrstors << 45)
1575	\| ((uint64_t)pGst->fVmxUseTscScaling << 46) \| ((uint64_t)pGst->fVmxEntryLoadDebugCtls << 47)
1576	\| ((uint64_t)pGst->fVmxIa32eModeGuest << 48) \| ((uint64_t)pGst->fVmxEntryLoadEferMsr << 49)
1577	\| ((uint64_t)pGst->fVmxEntryLoadPatMsr << 50) \| ((uint64_t)pGst->fVmxExitSaveDebugCtls << 51)
1578	\| ((uint64_t)pGst->fVmxHostAddrSpaceSize << 52) \| ((uint64_t)pGst->fVmxExitAckExtInt << 53)
1579	\| ((uint64_t)pGst->fVmxExitSavePatMsr << 54) \| ((uint64_t)pGst->fVmxExitLoadPatMsr << 55)
1580	\| ((uint64_t)pGst->fVmxExitSaveEferMsr << 56) \| ((uint64_t)pGst->fVmxExitLoadEferMsr << 57)
1581	\| ((uint64_t)pGst->fVmxSavePreemptTimer << 58) \| ((uint64_t)pGst->fVmxExitSaveEferLma << 59)
1582	\| ((uint64_t)pGst->fVmxIntelPt << 60) \| ((uint64_t)pGst->fVmxVmwriteAll << 61)
1583	\| ((uint64_t)pGst->fVmxEntryInjectSoftInt << 62);
1584
1585	if ((fBase \| fGst) != fBase)
1586	{
1587	uint64_t const fDiff = fBase ^ fGst;
1588	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1589	fBase, fGst, fDiff));
1590	return false;
1591	}
1592	}
1593
1594	/* Check second set of feature bits. */
1595	{
1596	uint64_t const fBase = ((uint64_t)pBase->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pBase->fVmxLoadIwKeyExit << 1);
1597	uint64_t const fGst = ((uint64_t)pGst->fVmxTertiaryExecCtls << 0) \| ((uint64_t)pGst->fVmxLoadIwKeyExit << 1);
1598	if ((fBase \| fGst) != fBase)
1599	{
1600	uint64_t const fDiff = fBase ^ fGst;
1601	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1602	fBase, fGst, fDiff));
1603	return false;
1604	}
1605	}
1606
1607	return true;
1608	}
1609
1610
1611	/**
1612	* Initializes VMX guest features and MSRs.
1613	*
1614	* @param pVM The cross context VM structure.
1615	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1616	* and no hardware-assisted nested-guest execution is
1617	* possible for this VM.
1618	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1619	*/
1620	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1621	{
1622	Assert(pVM);
1623	Assert(pGuestVmxMsrs);
1624
1625	/*
1626	* While it would be nice to check this earlier while initializing fNestedVmxEpt
1627	* but we would not have enumearted host features then, so do it at least now.
1628	*/
1629	if ( !pVM->cpum.s.HostFeatures.fNoExecute
1630	&& pVM->cpum.s.fNestedVmxEpt)
1631	{
1632	LogRel(("CPUM: Warning! EPT not exposed to the guest since NX isn't available on the host.\n"));
1633	pVM->cpum.s.fNestedVmxEpt = false;
1634	pVM->cpum.s.fNestedVmxUnrestrictedGuest = false;
1635	}
1636
1637	/*
1638	* Initialize the set of VMX features we emulate.
1639	*
1640	* Note! Some bits might be reported as 1 always if they fall under the
1641	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1642	*/
1643	CPUMFEATURES EmuFeat;
1644	RT_ZERO(EmuFeat);
1645	EmuFeat.fVmx = 1;
1646	EmuFeat.fVmxInsOutInfo = 1;
1647	EmuFeat.fVmxExtIntExit = 1;
1648	EmuFeat.fVmxNmiExit = 1;
1649	EmuFeat.fVmxVirtNmi = 1;
1650	EmuFeat.fVmxPreemptTimer = pVM->cpum.s.fNestedVmxPreemptTimer;
1651	EmuFeat.fVmxPostedInt = 0;
1652	EmuFeat.fVmxIntWindowExit = 1;
1653	EmuFeat.fVmxTscOffsetting = 1;
1654	EmuFeat.fVmxHltExit = 1;
1655	EmuFeat.fVmxInvlpgExit = 1;
1656	EmuFeat.fVmxMwaitExit = 1;
1657	EmuFeat.fVmxRdpmcExit = 1;
1658	EmuFeat.fVmxRdtscExit = 1;
1659	EmuFeat.fVmxCr3LoadExit = 1;
1660	EmuFeat.fVmxCr3StoreExit = 1;
1661	EmuFeat.fVmxTertiaryExecCtls = 0;
1662	EmuFeat.fVmxCr8LoadExit = 1;
1663	EmuFeat.fVmxCr8StoreExit = 1;
1664	EmuFeat.fVmxUseTprShadow = 1;
1665	EmuFeat.fVmxNmiWindowExit = 0;
1666	EmuFeat.fVmxMovDRxExit = 1;
1667	EmuFeat.fVmxUncondIoExit = 1;
1668	EmuFeat.fVmxUseIoBitmaps = 1;
1669	EmuFeat.fVmxMonitorTrapFlag = 0;
1670	EmuFeat.fVmxUseMsrBitmaps = 1;
1671	EmuFeat.fVmxMonitorExit = 1;
1672	EmuFeat.fVmxPauseExit = 1;
1673	EmuFeat.fVmxSecondaryExecCtls = 1;
1674	EmuFeat.fVmxVirtApicAccess = 1;
1675	EmuFeat.fVmxEpt = pVM->cpum.s.fNestedVmxEpt;
1676	EmuFeat.fVmxDescTableExit = 1;
1677	EmuFeat.fVmxRdtscp = 1;
1678	EmuFeat.fVmxVirtX2ApicMode = 0;
1679	EmuFeat.fVmxVpid = 0; /** @todo Consider enabling this when EPT works. */
1680	EmuFeat.fVmxWbinvdExit = 1;
1681	EmuFeat.fVmxUnrestrictedGuest = pVM->cpum.s.fNestedVmxUnrestrictedGuest;
1682	EmuFeat.fVmxApicRegVirt = 0;
1683	EmuFeat.fVmxVirtIntDelivery = 0;
1684	EmuFeat.fVmxPauseLoopExit = 0;
1685	EmuFeat.fVmxRdrandExit = 0;
1686	EmuFeat.fVmxInvpcid = 1;
1687	EmuFeat.fVmxVmFunc = 0;
1688	EmuFeat.fVmxVmcsShadowing = 0;
1689	EmuFeat.fVmxRdseedExit = 0;
1690	EmuFeat.fVmxPml = 0;
1691	EmuFeat.fVmxEptXcptVe = 0;
1692	EmuFeat.fVmxXsavesXrstors = 0;
1693	EmuFeat.fVmxUseTscScaling = 0;
1694	EmuFeat.fVmxLoadIwKeyExit = 0;
1695	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1696	EmuFeat.fVmxIa32eModeGuest = 1;
1697	EmuFeat.fVmxEntryLoadEferMsr = 1;
1698	EmuFeat.fVmxEntryLoadPatMsr = 0;
1699	EmuFeat.fVmxExitSaveDebugCtls = 1;
1700	EmuFeat.fVmxHostAddrSpaceSize = 1;
1701	EmuFeat.fVmxExitAckExtInt = 1;
1702	EmuFeat.fVmxExitSavePatMsr = 0;
1703	EmuFeat.fVmxExitLoadPatMsr = 0;
1704	EmuFeat.fVmxExitSaveEferMsr = 1;
1705	EmuFeat.fVmxExitLoadEferMsr = 1;
1706	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1707	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1708	EmuFeat.fVmxIntelPt = 0;
1709	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1710	EmuFeat.fVmxEntryInjectSoftInt = 1;
1711
1712	/*
1713	* Merge guest features.
1714	*
1715	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1716	* by the hardware, hence we merge our emulated features with the host features below.
1717	*/
1718	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1719	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1720	Assert(pBaseFeat->fVmx);
1721	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1722	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1723	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1724	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1725	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1726	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1727	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1728	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1729	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1730	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1731	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1732	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1733	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1734	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1735	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1736	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1737	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1738	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1739	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1740	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1741	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1742	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1743	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1744	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1745	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1746	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1747	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1748	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1749	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1750	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1751	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1752	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1753	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1754	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1755	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1756	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1757	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1758	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1759	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1760	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1761	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1762	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1763	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1764	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1765	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1766	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1767	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1768	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1769	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1770	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1771	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1772	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1773	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1774	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1775	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1776	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1777	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1778	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1779	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1780	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1781	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1782	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1783	pGuestFeat->fVmxIntelPt = (pBaseFeat->fVmxIntelPt & EmuFeat.fVmxIntelPt );
1784	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1785	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1786
1787	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1788	if ( pGuestFeat->fVmxPreemptTimer
1789	&& HMIsSubjectToVmxPreemptTimerErratum())
1790	{
1791	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum.\n"));
1792	pGuestFeat->fVmxPreemptTimer = 0;
1793	pGuestFeat->fVmxSavePreemptTimer = 0;
1794	}
1795
1796	/* Sanity checking. */
1797	if (!pGuestFeat->fVmxSecondaryExecCtls)
1798	{
1799	Assert(!pGuestFeat->fVmxVirtApicAccess);
1800	Assert(!pGuestFeat->fVmxEpt);
1801	Assert(!pGuestFeat->fVmxDescTableExit);
1802	Assert(!pGuestFeat->fVmxRdtscp);
1803	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1804	Assert(!pGuestFeat->fVmxVpid);
1805	Assert(!pGuestFeat->fVmxWbinvdExit);
1806	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1807	Assert(!pGuestFeat->fVmxApicRegVirt);
1808	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1809	Assert(!pGuestFeat->fVmxPauseLoopExit);
1810	Assert(!pGuestFeat->fVmxRdrandExit);
1811	Assert(!pGuestFeat->fVmxInvpcid);
1812	Assert(!pGuestFeat->fVmxVmFunc);
1813	Assert(!pGuestFeat->fVmxVmcsShadowing);
1814	Assert(!pGuestFeat->fVmxRdseedExit);
1815	Assert(!pGuestFeat->fVmxPml);
1816	Assert(!pGuestFeat->fVmxEptXcptVe);
1817	Assert(!pGuestFeat->fVmxXsavesXrstors);
1818	Assert(!pGuestFeat->fVmxUseTscScaling);
1819	}
1820	else if (pGuestFeat->fVmxUnrestrictedGuest)
1821	{
1822	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
1823	Assert(pGuestFeat->fVmxExitSaveEferLma);
1824	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
1825	Assert(pGuestFeat->fVmxEpt);
1826	}
1827
1828	if (!pGuestFeat->fVmxTertiaryExecCtls)
1829	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
1830
1831	/*
1832	* Finally initialize the VMX guest MSRs.
1833	*/
1834	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
1835	}
1836
1837
1838	/**
1839	* Gets the host hardware-virtualization MSRs.
1840	*
1841	* @returns VBox status code.
1842	* @param pMsrs Where to store the MSRs.
1843	*/
1844	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
1845	{
1846	Assert(pMsrs);
1847
1848	uint32_t fCaps = 0;
1849	int rc = SUPR3QueryVTCaps(&fCaps);
1850	if (RT_SUCCESS(rc))
1851	{
1852	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
1853	{
1854	SUPHWVIRTMSRS HwvirtMsrs;
1855	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
1856	if (RT_SUCCESS(rc))
1857	{
1858	if (fCaps & SUPVTCAPS_VT_X)
1859	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
1860	else
1861	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
1862	return VINF_SUCCESS;
1863	}
1864
1865	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
1866	return rc;
1867	}
1868
1869	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
1870	return VERR_INTERNAL_ERROR_5;
1871	}
1872	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
1873	return VINF_SUCCESS;
1874	}
1875
1876
1877	/**
1878	* @callback_method_impl{FNTMTIMERINT,
1879	* Callback that fires when the nested VMX-preemption timer expired.}
1880	*/
1881	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
1882	{
1883	RT_NOREF(pVM, hTimer);
1884	PVMCPU pVCpu = (PVMCPUR3)pvUser;
1885	AssertPtr(pVCpu);
1886	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
1887	}
1888
1889
1890	/**
1891	* Initializes the CPUM.
1892	*
1893	* @returns VBox status code.
1894	* @param pVM The cross context VM structure.
1895	*/
1896	VMMR3DECL(int) CPUMR3Init(PVM pVM)
1897	{
1898	LogFlow(("CPUMR3Init\n"));
1899
1900	/*
1901	* Assert alignment, sizes and tables.
1902	*/
1903	AssertCompileMemberAlignment(VM, cpum.s, 32);
1904	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
1905	AssertCompileSizeAlignment(CPUMCTX, 64);
1906	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
1907	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
1908	AssertCompileMemberAlignment(VM, cpum, 64);
1909	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
1910	#ifdef VBOX_STRICT
1911	int rc2 = cpumR3MsrStrictInitChecks();
1912	AssertRCReturn(rc2, rc2);
1913	#endif
1914
1915	/*
1916	* Gather info about the host CPU.
1917	*/
1918	if (!ASMHasCpuId())
1919	{
1920	LogRel(("The CPU doesn't support CPUID!\n"));
1921	return VERR_UNSUPPORTED_CPU;
1922	}
1923
1924	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
1925
1926	CPUMMSRS HostMsrs;
1927	RT_ZERO(HostMsrs);
1928	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
1929	AssertLogRelRCReturn(rc, rc);
1930
1931	PCPUMCPUIDLEAF paLeaves;
1932	uint32_t cLeaves;
1933	rc = CPUMR3CpuIdCollectLeaves(&paLeaves, &cLeaves);
1934	AssertLogRelRCReturn(rc, rc);
1935
1936	rc = cpumR3CpuIdExplodeFeatures(paLeaves, cLeaves, &HostMsrs, &pVM->cpum.s.HostFeatures);
1937	RTMemFree(paLeaves);
1938	AssertLogRelRCReturn(rc, rc);
1939	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
1940
1941	/*
1942	* Check that the CPU supports the minimum features we require.
1943	*/
1944	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
1945	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
1946	if (!pVM->cpum.s.HostFeatures.fMmx)
1947	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
1948	if (!pVM->cpum.s.HostFeatures.fTsc)
1949	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
1950
1951	/*
1952	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
1953	*/
1954	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
1955	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
1956
1957	/*
1958	* Figure out which XSAVE/XRSTOR features are available on the host.
1959	*/
1960	uint64_t fXcr0Host = 0;
1961	uint64_t fXStateHostMask = 0;
1962	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
1963	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
1964	{
1965	fXStateHostMask = fXcr0Host = ASMGetXcr0();
1966	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
1967	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
1968	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
1969	}
1970	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
1971	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
1972	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
1973
1974	/*
1975	* Initialize the host XSAVE/XRSTOR mask.
1976	*/
1977	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
1978	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
1979	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
1980	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
1981	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
1982	, VERR_CPUM_IPE_2);
1983
1984	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1985	{
1986	PVMCPU pVCpu = pVM->apCpusR3[i];
1987
1988	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
1989	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
1990	}
1991
1992	/*
1993	* Register saved state data item.
1994	*/
1995	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
1996	NULL, cpumR3LiveExec, NULL,
1997	NULL, cpumR3SaveExec, NULL,
1998	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
1999	if (RT_FAILURE(rc))
2000	return rc;
2001
2002	/*
2003	* Register info handlers and registers with the debugger facility.
2004	*/
2005	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2006	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2007	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2008	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2009	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2010	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2011	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2012	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2013	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2014	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2015	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2016	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2017	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
2018	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2019	&cpumR3InfoVmxFeatures);
2020
2021	rc = cpumR3DbgInit(pVM);
2022	if (RT_FAILURE(rc))
2023	return rc;
2024
2025	/*
2026	* Check if we need to workaround partial/leaky FPU handling.
2027	*/
2028	cpumR3CheckLeakyFpu(pVM);
2029
2030	/*
2031	* Initialize the Guest CPUID and MSR states.
2032	*/
2033	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2034	if (RT_FAILURE(rc))
2035	return rc;
2036
2037	/*
2038	* Init the VMX/SVM state.
2039	*
2040	* This must be done after initializing CPUID/MSR features as we access the
2041	* the VMX/SVM guest features below.
2042	*
2043	* In the case of nested VT-x, we also need to create the per-VCPU
2044	* VMX preemption timers.
2045	*/
2046	if (pVM->cpum.s.GuestFeatures.fVmx)
2047	cpumR3InitVmxHwVirtState(pVM);
2048	else if (pVM->cpum.s.GuestFeatures.fSvm)
2049	cpumR3InitSvmHwVirtState(pVM);
2050	else
2051	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2052
2053	CPUMR3Reset(pVM);
2054	return VINF_SUCCESS;
2055	}
2056
2057
2058	/**
2059	* Applies relocations to data and code managed by this
2060	* component. This function will be called at init and
2061	* whenever the VMM need to relocate it self inside the GC.
2062	*
2063	* The CPUM will update the addresses used by the switcher.
2064	*
2065	* @param pVM The cross context VM structure.
2066	*/
2067	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2068	{
2069	RT_NOREF(pVM);
2070	}
2071
2072
2073	/**
2074	* Terminates the CPUM.
2075	*
2076	* Termination means cleaning up and freeing all resources,
2077	* the VM it self is at this point powered off or suspended.
2078	*
2079	* @returns VBox status code.
2080	* @param pVM The cross context VM structure.
2081	*/
2082	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2083	{
2084	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2085	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2086	{
2087	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2088	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2089	pVCpu->cpum.s.uMagic = 0;
2090	pvCpu->cpum.s.Guest.dr[5] = 0;
2091	}
2092	#endif
2093
2094	if (pVM->cpum.s.GuestFeatures.fVmx)
2095	{
2096	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2097	{
2098	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2099	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2100	{
2101	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2102	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2103	}
2104	}
2105	}
2106	return VINF_SUCCESS;
2107	}
2108
2109
2110	/**
2111	* Resets a virtual CPU.
2112	*
2113	* Used by CPUMR3Reset and CPU hot plugging.
2114	*
2115	* @param pVM The cross context VM structure.
2116	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2117	* being reset. This may differ from the current EMT.
2118	*/
2119	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2120	{
2121	/** @todo anything different for VCPU > 0? */
2122	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2123
2124	/*
2125	* Initialize everything to ZERO first.
2126	*/
2127	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2128
2129	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2130
2131	pVCpu->cpum.s.fUseFlags = fUseFlags;
2132
2133	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2134	pCtx->eip = 0x0000fff0;
2135	pCtx->edx = 0x00000600; /* P6 processor */
2136	pCtx->eflags.Bits.u1Reserved0 = 1;
2137
2138	pCtx->cs.Sel = 0xf000;
2139	pCtx->cs.ValidSel = 0xf000;
2140	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2141	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2142	pCtx->cs.u32Limit = 0x0000ffff;
2143	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2144	pCtx->cs.Attr.n.u1Present = 1;
2145	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2146
2147	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2148	pCtx->ds.u32Limit = 0x0000ffff;
2149	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2150	pCtx->ds.Attr.n.u1Present = 1;
2151	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2152
2153	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2154	pCtx->es.u32Limit = 0x0000ffff;
2155	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2156	pCtx->es.Attr.n.u1Present = 1;
2157	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2158
2159	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2160	pCtx->fs.u32Limit = 0x0000ffff;
2161	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2162	pCtx->fs.Attr.n.u1Present = 1;
2163	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2164
2165	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2166	pCtx->gs.u32Limit = 0x0000ffff;
2167	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2168	pCtx->gs.Attr.n.u1Present = 1;
2169	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2170
2171	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2172	pCtx->ss.u32Limit = 0x0000ffff;
2173	pCtx->ss.Attr.n.u1Present = 1;
2174	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2175	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2176
2177	pCtx->idtr.cbIdt = 0xffff;
2178	pCtx->gdtr.cbGdt = 0xffff;
2179
2180	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2181	pCtx->ldtr.u32Limit = 0xffff;
2182	pCtx->ldtr.Attr.n.u1Present = 1;
2183	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2184
2185	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2186	pCtx->tr.u32Limit = 0xffff;
2187	pCtx->tr.Attr.n.u1Present = 1;
2188	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2189
2190	pCtx->dr[6] = X86_DR6_INIT_VAL;
2191	pCtx->dr[7] = X86_DR7_INIT_VAL;
2192
2193	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2194	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2195	pFpuCtx->FCW = 0x37f;
2196
2197	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2198	IA-32 Processor States Following Power-up, Reset, or INIT */
2199	pFpuCtx->MXCSR = 0x1F80;
2200	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2201
2202	pCtx->aXcr[0] = XSAVE_C_X87;
2203	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2204	{
2205	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2206	as we don't know what happened before. (Bother optimize later?) */
2207	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2208	}
2209
2210	/*
2211	* MSRs.
2212	*/
2213	/* Init PAT MSR */
2214	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2215
2216	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2217	* The Intel docs don't mention it. */
2218	Assert(!pCtx->msrEFER);
2219
2220	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2221	is supposed to be here, just trying provide useful/sensible values. */
2222	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2223	if (pRange)
2224	{
2225	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2226	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2227	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2228	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2229	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2230	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2231	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2232	}
2233
2234	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2235
2236	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2237	* called from each EMT while we're getting called by CPUMR3Reset()
2238	* iteratively on the same thread. Fix later. */
2239	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2240	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2241	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2242	#endif
2243
2244
2245	/* C-state control. Guesses. */
2246	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2247	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2248	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2249	* functionality. The default value must be different due to incompatible write mask.
2250	*/
2251	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2252	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2253	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2254	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2255
2256	/*
2257	* Hardware virtualization state.
2258	*/
2259	CPUMSetGuestGif(pCtx, true);
2260	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2261	if (pVM->cpum.s.GuestFeatures.fVmx)
2262	cpumR3ResetVmxHwVirtState(pVCpu);
2263	else if (pVM->cpum.s.GuestFeatures.fSvm)
2264	cpumR3ResetSvmHwVirtState(pVCpu);
2265	}
2266
2267
2268	/**
2269	* Resets the CPU.
2270	*
2271	* @returns VINF_SUCCESS.
2272	* @param pVM The cross context VM structure.
2273	*/
2274	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2275	{
2276	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2277	{
2278	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2279	CPUMR3ResetCpu(pVM, pVCpu);
2280
2281	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2282
2283	/* Magic marker for searching in crash dumps. */
2284	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2285	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2286	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2287	#endif
2288	}
2289	}
2290
2291
2292
2293
2294	/**
2295	* Pass 0 live exec callback.
2296	*
2297	* @returns VINF_SSM_DONT_CALL_AGAIN.
2298	* @param pVM The cross context VM structure.
2299	* @param pSSM The saved state handle.
2300	* @param uPass The pass (0).
2301	*/
2302	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2303	{
2304	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2305	cpumR3SaveCpuId(pVM, pSSM);
2306	return VINF_SSM_DONT_CALL_AGAIN;
2307	}
2308
2309
2310	/**
2311	* Execute state save operation.
2312	*
2313	* @returns VBox status code.
2314	* @param pVM The cross context VM structure.
2315	* @param pSSM SSM operation handle.
2316	*/
2317	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2318	{
2319	/*
2320	* Save.
2321	*/
2322	SSMR3PutU32(pSSM, pVM->cCpus);
2323	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2324	CPUMCTX DummyHyperCtx;
2325	RT_ZERO(DummyHyperCtx);
2326	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2327	{
2328	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2329
2330	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2331
2332	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2333	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2334	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2335	if (pGstCtx->fXStateMask != 0)
2336	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2337	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2338	{
2339	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2340	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2341	}
2342	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2343	{
2344	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2345	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2346	}
2347	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2348	{
2349	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2350	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2351	}
2352	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2353	{
2354	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2355	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2356	}
2357	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2358	{
2359	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2360	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2361	}
2362	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2363	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2364	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2365	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2366	if (pVM->cpum.s.GuestFeatures.fSvm)
2367	{
2368	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2369	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2370	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2371	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2372	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2373	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2374	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2375	g_aSvmHwvirtHostState, NULL /* pvUser */);
2376	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2377	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2378	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2379	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fLocalForcedActions);
2380	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2381	}
2382	if (pVM->cpum.s.GuestFeatures.fVmx)
2383	{
2384	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2385	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2386	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2387	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2388	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2389	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2390	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2391	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2392	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2393	0, g_aVmxHwvirtVmcs, NULL);
2394	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2395	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2396	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2397	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2398	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2399	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2400	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2401	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2402	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2403	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2404	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2405	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2406	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2407	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2408	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2409	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2410	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2411	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2412	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2413	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2414	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2415	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2416	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2417	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2418	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2419	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2420	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2421	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2422	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2423	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2424	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2425	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2426	}
2427	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2428	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2429	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2430	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2431	}
2432
2433	cpumR3SaveCpuId(pVM, pSSM);
2434	return VINF_SUCCESS;
2435	}
2436
2437
2438	/**
2439	* @callback_method_impl{FNSSMINTLOADPREP}
2440	*/
2441	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2442	{
2443	NOREF(pSSM);
2444	pVM->cpum.s.fPendingRestore = true;
2445	return VINF_SUCCESS;
2446	}
2447
2448
2449	/**
2450	* @callback_method_impl{FNSSMINTLOADEXEC}
2451	*/
2452	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2453	{
2454	int rc; /* Only for AssertRCReturn use. */
2455
2456	/*
2457	* Validate version.
2458	*/
2459	if ( uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2460	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2461	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2462	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2463	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2464	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2465	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2466	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2467	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2468	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2469	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2470	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2471	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2472	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2473	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2474	{
2475	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2476	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2477	}
2478
2479	if (uPass == SSM_PASS_FINAL)
2480	{
2481	/*
2482	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2483	* really old SSM file versions.)
2484	*/
2485	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2486	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2487	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2488	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2489
2490	/*
2491	* Figure x86 and ctx field definitions to use for older states.
2492	*/
2493	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2494	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2495	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2496	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2497	{
2498	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2499	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2500	}
2501	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2502	{
2503	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2504	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2505	}
2506
2507	/*
2508	* The hyper state used to preceed the CPU count. Starting with
2509	* XSAVE it was moved down till after we've got the count.
2510	*/
2511	CPUMCTX HyperCtxIgnored;
2512	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2513	{
2514	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2515	{
2516	X86FXSTATE Ign;
2517	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2518	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2519	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2520	}
2521	}
2522
2523	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2524	{
2525	uint32_t cCpus;
2526	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2527	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2528	VERR_SSM_UNEXPECTED_DATA);
2529	}
2530	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2531	\|\| pVM->cCpus == 1,
2532	("cCpus=%u\n", pVM->cCpus),
2533	VERR_SSM_UNEXPECTED_DATA);
2534
2535	uint32_t cbMsrs = 0;
2536	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2537	{
2538	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2539	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2540	VERR_SSM_UNEXPECTED_DATA);
2541	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2542	VERR_SSM_UNEXPECTED_DATA);
2543	}
2544
2545	/*
2546	* Do the per-CPU restoring.
2547	*/
2548	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2549	{
2550	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2551	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2552
2553	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2554	{
2555	/*
2556	* The XSAVE saved state layout moved the hyper state down here.
2557	*/
2558	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2559	AssertRCReturn(rc, rc);
2560
2561	/*
2562	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2563	*/
2564	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2565	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2566	AssertRCReturn(rc, rc);
2567
2568	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2569	if (pGstCtx->fXStateMask != 0)
2570	{
2571	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2572	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2573	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2574	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2575	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2576	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2577	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2578	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2579	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2580	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2581	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2582	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2583	}
2584
2585	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2586	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2587	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2588	{
2589	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2590	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2591	VERR_CPUM_INVALID_XCR0);
2592	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2593	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2594	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2595	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2596	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2597	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2598	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2599	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2600	}
2601
2602	/* Check that the XCR1 is zero, as we don't implement it yet. */
2603	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2604
2605	/*
2606	* Restore the individual extended state components we support.
2607	*/
2608	if (pGstCtx->fXStateMask != 0)
2609	{
2610	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2611	0, g_aCpumXSaveHdrFields, NULL);
2612	AssertRCReturn(rc, rc);
2613	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2614	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2615	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2616	VERR_CPUM_INVALID_XSAVE_HDR);
2617	}
2618	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2619	{
2620	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2621	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2622	}
2623	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2624	{
2625	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2626	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2627	}
2628	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2629	{
2630	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2631	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2632	}
2633	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2634	{
2635	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2636	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2637	}
2638	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2639	{
2640	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2641	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2642	}
2643	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2644	{
2645	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2646	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2647	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2648	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2649	}
2650	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2651	{
2652	if (pVM->cpum.s.GuestFeatures.fSvm)
2653	{
2654	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2655	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2656	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2657	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2658	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2659	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2660	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2661	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2662	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2663	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2664	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2665	SSMR3GetU32(pSSM, &pGstCtx->hwvirt.fLocalForcedActions);
2666	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2667	}
2668	}
2669	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2670	{
2671	if (pVM->cpum.s.GuestFeatures.fVmx)
2672	{
2673	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2674	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2675	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2676	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2677	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2678	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2679	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2680	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2681	0, g_aVmxHwvirtVmcs, NULL);
2682	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2683	0, g_aVmxHwvirtVmcs, NULL);
2684	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2685	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2686	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2687	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2688	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2689	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2690	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2691	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2692	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2693	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2694	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2695	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2696	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2697	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2698	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2699	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2700	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2701	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2702	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2703	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2704	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2705	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2706	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2707	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2708	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2709	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2710	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2711	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2712	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2713	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2714	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2715	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2716	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2717	}
2718	}
2719	}
2720	else
2721	{
2722	/*
2723	* Pre XSAVE saved state.
2724	*/
2725	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2726	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2727	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2728	}
2729
2730	/*
2731	* Restore a couple of flags and the MSRs.
2732	*/
2733	uint32_t fIgnoredUsedFlags = 0;
2734	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2735	AssertRCReturn(rc, rc);
2736	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2737
2738	rc = VINF_SUCCESS;
2739	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2740	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2741	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2742	{
2743	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2744	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2745	}
2746	AssertRCReturn(rc, rc);
2747
2748	/* REM and other may have cleared must-be-one fields in DR6 and
2749	DR7, fix these. */
2750	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2751	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2752	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2753	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2754	}
2755
2756	/* Older states does not have the internal selector register flags
2757	and valid selector value. Supply those. */
2758	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2759	{
2760	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2761	{
2762	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2763	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
2764	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2765	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
2766	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
2767	if (fValid)
2768	{
2769	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2770	{
2771	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
2772	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
2773	}
2774
2775	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2776	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2777	}
2778	else
2779	{
2780	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
2781	{
2782	paSelReg[iSelReg].fFlags = 0;
2783	paSelReg[iSelReg].ValidSel = 0;
2784	}
2785
2786	/* This might not be 104% correct, but I think it's close
2787	enough for all practical purposes... (REM always loaded
2788	LDTR registers.) */
2789	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2790	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
2791	}
2792	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
2793	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
2794	}
2795	}
2796
2797	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
2798	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
2799	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2800	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2801	{
2802	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2803	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
2804	}
2805
2806	/*
2807	* A quick sanity check.
2808	*/
2809	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2810	{
2811	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2812	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2813	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2814	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2815	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2816	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2817	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
2818	}
2819	}
2820
2821	pVM->cpum.s.fPendingRestore = false;
2822
2823	/*
2824	* Guest CPUIDs (and VMX MSR features).
2825	*/
2826	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
2827	{
2828	CPUMMSRS GuestMsrs;
2829	RT_ZERO(GuestMsrs);
2830
2831	CPUMFEATURES BaseFeatures;
2832	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
2833	if (fVmxGstFeat)
2834	{
2835	/*
2836	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
2837	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
2838	* here so we can compare them for compatibility after exploding guest features.
2839	*/
2840	BaseFeatures = pVM->cpum.s.GuestFeatures;
2841
2842	/* Use the VMX MSR features from the saved state while exploding guest features. */
2843	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
2844	}
2845
2846	/* Load CPUID and explode guest features. */
2847	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
2848	if (fVmxGstFeat)
2849	{
2850	/*
2851	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
2852	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
2853	* VMX features presented to the guest.
2854	*/
2855	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
2856	if (!fIsCompat)
2857	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
2858	}
2859	return rc;
2860	}
2861	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
2862	}
2863
2864
2865	/**
2866	* @callback_method_impl{FNSSMINTLOADDONE}
2867	*/
2868	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
2869	{
2870	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
2871	return VINF_SUCCESS;
2872
2873	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
2874	if (pVM->cpum.s.fPendingRestore)
2875	{
2876	LogRel(("CPUM: Missing state!\n"));
2877	return VERR_INTERNAL_ERROR_2;
2878	}
2879
2880	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
2881	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2882	{
2883	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2884
2885	/* Notify PGM of the NXE states in case they've changed. */
2886	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
2887
2888	/* During init. this is done in CPUMR3InitCompleted(). */
2889	if (fSupportsLongMode)
2890	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
2891
2892	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
2893	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
2894	}
2895	return VINF_SUCCESS;
2896	}
2897
2898
2899	/**
2900	* Checks if the CPUM state restore is still pending.
2901	*
2902	* @returns true / false.
2903	* @param pVM The cross context VM structure.
2904	*/
2905	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
2906	{
2907	return pVM->cpum.s.fPendingRestore;
2908	}
2909
2910
2911	/**
2912	* Formats the EFLAGS value into mnemonics.
2913	*
2914	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
2915	* @param efl The EFLAGS value.
2916	*/
2917	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
2918	{
2919	/*
2920	* Format the flags.
2921	*/
2922	static const struct
2923	{
2924	const char pszSet; const char pszClear; uint32_t fFlag;
2925	} s_aFlags[] =
2926	{
2927	{ "vip",NULL, X86_EFL_VIP },
2928	{ "vif",NULL, X86_EFL_VIF },
2929	{ "ac", NULL, X86_EFL_AC },
2930	{ "vm", NULL, X86_EFL_VM },
2931	{ "rf", NULL, X86_EFL_RF },
2932	{ "nt", NULL, X86_EFL_NT },
2933	{ "ov", "nv", X86_EFL_OF },
2934	{ "dn", "up", X86_EFL_DF },
2935	{ "ei", "di", X86_EFL_IF },
2936	{ "tf", NULL, X86_EFL_TF },
2937	{ "nt", "pl", X86_EFL_SF },
2938	{ "nz", "zr", X86_EFL_ZF },
2939	{ "ac", "na", X86_EFL_AF },
2940	{ "po", "pe", X86_EFL_PF },
2941	{ "cy", "nc", X86_EFL_CF },
2942	};
2943	char *psz = pszEFlags;
2944	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
2945	{
2946	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
2947	if (pszAdd)
2948	{
2949	strcpy(psz, pszAdd);
2950	psz += strlen(pszAdd);
2951	*psz++ = ' ';
2952	}
2953	}
2954	psz[-1] = '\0';
2955	}
2956
2957
2958	/**
2959	* Formats a full register dump.
2960	*
2961	* @param pVM The cross context VM structure.
2962	* @param pCtx The context to format.
2963	* @param pCtxCore The context core to format.
2964	* @param pHlp Output functions.
2965	* @param enmType The dump type.
2966	* @param pszPrefix Register name prefix.
2967	*/
2968	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType,
2969	const char *pszPrefix)
2970	{
2971	NOREF(pVM);
2972
2973	/*
2974	* Format the EFLAGS.
2975	*/
2976	uint32_t efl = pCtxCore->eflags.u32;
2977	char szEFlags[80];
2978	cpumR3InfoFormatFlags(&szEFlags[0], efl);
2979
2980	/*
2981	* Format the registers.
2982	*/
2983	switch (enmType)
2984	{
2985	case CPUMDUMPTYPE_TERSE:
2986	if (CPUMIsGuestIn64BitCodeEx(pCtx))
2987	pHlp->pfnPrintf(pHlp,
2988	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
2989	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
2990	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
2991	"%sr14=%016RX64 %sr15=%016RX64\n"
2992	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
2993	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
2994	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
2995	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
2996	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
2997	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
2998	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
2999	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3000	else
3001	pHlp->pfnPrintf(pHlp,
3002	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3003	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3004	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3005	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3006	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3007	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3008	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, efl);
3009	break;
3010
3011	case CPUMDUMPTYPE_DEFAULT:
3012	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3013	pHlp->pfnPrintf(pHlp,
3014	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3015	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3016	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3017	"%sr14=%016RX64 %sr15=%016RX64\n"
3018	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3019	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3020	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3021	,
3022	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3023	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3024	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3025	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3026	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3027	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3028	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3029	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3030	else
3031	pHlp->pfnPrintf(pHlp,
3032	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3033	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3034	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3035	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3036	,
3037	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3038	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3039	pszPrefix, pCtxCore->cs.Sel, pszPrefix, pCtxCore->ss.Sel, pszPrefix, pCtxCore->ds.Sel, pszPrefix, pCtxCore->es.Sel,
3040	pszPrefix, pCtxCore->fs.Sel, pszPrefix, pCtxCore->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3041	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3042	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3043	break;
3044
3045	case CPUMDUMPTYPE_VERBOSE:
3046	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3047	pHlp->pfnPrintf(pHlp,
3048	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3049	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3050	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3051	"%sr14=%016RX64 %sr15=%016RX64\n"
3052	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3053	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3054	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3055	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3056	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3057	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3058	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3059	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3060	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3061	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3062	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3063	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3064	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3065	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3066	,
3067	pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
3068	pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
3069	pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
3070	pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3071	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3072	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3073	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3074	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3075	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3076	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3077	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3078	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3079	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3080	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3081	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3082	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3083	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3084	else
3085	pHlp->pfnPrintf(pHlp,
3086	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3087	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3088	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3089	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3090	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3091	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3092	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3093	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3094	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3095	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3096	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3097	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3098	,
3099	pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
3100	pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3101	pszPrefix, pCtxCore->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3102	pszPrefix, pCtxCore->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3103	pszPrefix, pCtxCore->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3104	pszPrefix, pCtxCore->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3105	pszPrefix, pCtxCore->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3106	pszPrefix, pCtxCore->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3107	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3108	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3109	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3110	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3111
3112	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3113	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3114	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3115	{
3116	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3117	pHlp->pfnPrintf(pHlp,
3118	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3119	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3120	,
3121	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3122	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3123	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3124	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3125	);
3126	/*
3127	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3128	* not (FP)R0-7 as Intel SDM suggests.
3129	*/
3130	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3131	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3132	{
3133	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3134	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3135	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3136	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3137	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3138	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3139	iExponent -= 16383; /* subtract bias */
3140	/** @todo This isn't entirenly correct and needs more work! */
3141	pHlp->pfnPrintf(pHlp,
3142	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3143	pszPrefix, iST, pszPrefix, iFPR,
3144	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3145	uTag, chSign, iInteger, u64Fraction, iExponent);
3146	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3147	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3148	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3149	else
3150	pHlp->pfnPrintf(pHlp, "\n");
3151	}
3152
3153	/* XMM/YMM/ZMM registers. */
3154	if (pCtx->fXStateMask & XSAVE_C_YMM)
3155	{
3156	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3157	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3158	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3159	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3160	pszPrefix, i, i < 10 ? " " : "",
3161	pYmmHiCtx->aYmmHi[i].au32[3],
3162	pYmmHiCtx->aYmmHi[i].au32[2],
3163	pYmmHiCtx->aYmmHi[i].au32[1],
3164	pYmmHiCtx->aYmmHi[i].au32[0],
3165	pFpuCtx->aXMM[i].au32[3],
3166	pFpuCtx->aXMM[i].au32[2],
3167	pFpuCtx->aXMM[i].au32[1],
3168	pFpuCtx->aXMM[i].au32[0]);
3169	else
3170	{
3171	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3172	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3173	pHlp->pfnPrintf(pHlp,
3174	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3175	pszPrefix, i, i < 10 ? " " : "",
3176	pZmmHi256->aHi256Regs[i].au32[7],
3177	pZmmHi256->aHi256Regs[i].au32[6],
3178	pZmmHi256->aHi256Regs[i].au32[5],
3179	pZmmHi256->aHi256Regs[i].au32[4],
3180	pZmmHi256->aHi256Regs[i].au32[3],
3181	pZmmHi256->aHi256Regs[i].au32[2],
3182	pZmmHi256->aHi256Regs[i].au32[1],
3183	pZmmHi256->aHi256Regs[i].au32[0],
3184	pYmmHiCtx->aYmmHi[i].au32[3],
3185	pYmmHiCtx->aYmmHi[i].au32[2],
3186	pYmmHiCtx->aYmmHi[i].au32[1],
3187	pYmmHiCtx->aYmmHi[i].au32[0],
3188	pFpuCtx->aXMM[i].au32[3],
3189	pFpuCtx->aXMM[i].au32[2],
3190	pFpuCtx->aXMM[i].au32[1],
3191	pFpuCtx->aXMM[i].au32[0]);
3192
3193	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3194	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3195	pHlp->pfnPrintf(pHlp,
3196	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3197	pszPrefix, i + 16,
3198	pZmm16Hi->aRegs[i].au32[15],
3199	pZmm16Hi->aRegs[i].au32[14],
3200	pZmm16Hi->aRegs[i].au32[13],
3201	pZmm16Hi->aRegs[i].au32[12],
3202	pZmm16Hi->aRegs[i].au32[11],
3203	pZmm16Hi->aRegs[i].au32[10],
3204	pZmm16Hi->aRegs[i].au32[9],
3205	pZmm16Hi->aRegs[i].au32[8],
3206	pZmm16Hi->aRegs[i].au32[7],
3207	pZmm16Hi->aRegs[i].au32[6],
3208	pZmm16Hi->aRegs[i].au32[5],
3209	pZmm16Hi->aRegs[i].au32[4],
3210	pZmm16Hi->aRegs[i].au32[3],
3211	pZmm16Hi->aRegs[i].au32[2],
3212	pZmm16Hi->aRegs[i].au32[1],
3213	pZmm16Hi->aRegs[i].au32[0]);
3214	}
3215	}
3216	else
3217	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3218	pHlp->pfnPrintf(pHlp,
3219	i & 1
3220	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3221	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3222	pszPrefix, i, i < 10 ? " " : "",
3223	pFpuCtx->aXMM[i].au32[3],
3224	pFpuCtx->aXMM[i].au32[2],
3225	pFpuCtx->aXMM[i].au32[1],
3226	pFpuCtx->aXMM[i].au32[0]);
3227
3228	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3229	{
3230	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3231	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3232	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3233	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3234	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3235	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3236	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3237	}
3238
3239	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3240	{
3241	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3242	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3243	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3244	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3245	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3246	}
3247
3248	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3249	{
3250	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3251	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3252	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3253	}
3254
3255	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3256	if (pFpuCtx->au32RsrvdRest[i])
3257	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3258	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3259	}
3260
3261	pHlp->pfnPrintf(pHlp,
3262	"%sEFER =%016RX64\n"
3263	"%sPAT =%016RX64\n"
3264	"%sSTAR =%016RX64\n"
3265	"%sCSTAR =%016RX64\n"
3266	"%sLSTAR =%016RX64\n"
3267	"%sSFMASK =%016RX64\n"
3268	"%sKERNELGSBASE =%016RX64\n",
3269	pszPrefix, pCtx->msrEFER,
3270	pszPrefix, pCtx->msrPAT,
3271	pszPrefix, pCtx->msrSTAR,
3272	pszPrefix, pCtx->msrCSTAR,
3273	pszPrefix, pCtx->msrLSTAR,
3274	pszPrefix, pCtx->msrSFMASK,
3275	pszPrefix, pCtx->msrKERNELGSBASE);
3276
3277	if (CPUMIsGuestInPAEModeEx(pCtx))
3278	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3279	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3280	break;
3281	}
3282	}
3283
3284
3285	/**
3286	* Display all cpu states and any other cpum info.
3287	*
3288	* @param pVM The cross context VM structure.
3289	* @param pHlp The info helper functions.
3290	* @param pszArgs Arguments, ignored.
3291	*/
3292	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3293	{
3294	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3295	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3296	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3297	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3298	cpumR3InfoHost(pVM, pHlp, pszArgs);
3299	}
3300
3301
3302	/**
3303	* Parses the info argument.
3304	*
3305	* The argument starts with 'verbose', 'terse' or 'default' and then
3306	* continues with the comment string.
3307	*
3308	* @param pszArgs The pointer to the argument string.
3309	* @param penmType Where to store the dump type request.
3310	* @param ppszComment Where to store the pointer to the comment string.
3311	*/
3312	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3313	{
3314	if (!pszArgs)
3315	{
3316	*penmType = CPUMDUMPTYPE_DEFAULT;
3317	*ppszComment = "";
3318	}
3319	else
3320	{
3321	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3322	{
3323	pszArgs += 7;
3324	*penmType = CPUMDUMPTYPE_VERBOSE;
3325	}
3326	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3327	{
3328	pszArgs += 5;
3329	*penmType = CPUMDUMPTYPE_TERSE;
3330	}
3331	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3332	{
3333	pszArgs += 7;
3334	*penmType = CPUMDUMPTYPE_DEFAULT;
3335	}
3336	else
3337	*penmType = CPUMDUMPTYPE_DEFAULT;
3338	*ppszComment = RTStrStripL(pszArgs);
3339	}
3340	}
3341
3342
3343	/**
3344	* Display the guest cpu state.
3345	*
3346	* @param pVM The cross context VM structure.
3347	* @param pHlp The info helper functions.
3348	* @param pszArgs Arguments.
3349	*/
3350	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3351	{
3352	CPUMDUMPTYPE enmType;
3353	const char *pszComment;
3354	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3355
3356	PVMCPU pVCpu = VMMGetCpu(pVM);
3357	if (!pVCpu)
3358	pVCpu = pVM->apCpusR3[0];
3359
3360	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3361
3362	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3363	cpumR3InfoOne(pVM, pCtx, CPUMCTX2CORE(pCtx), pHlp, enmType, "");
3364	}
3365
3366
3367	/**
3368	* Displays an SVM VMCB control area.
3369	*
3370	* @param pHlp The info helper functions.
3371	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3372	* @param pszPrefix Caller specified string prefix.
3373	*/
3374	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3375	{
3376	AssertReturnVoid(pHlp);
3377	AssertReturnVoid(pVmcbCtrl);
3378
3379	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3380	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3381	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3382	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3383	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3384	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3385	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3386	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3387	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3388	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3389	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3390	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3391	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3392	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3393	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3394	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3395	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3396	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3397	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3398	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3399	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3400	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3401	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3402	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3403	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3404	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3405	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3406	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3407	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3408	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3409	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3410	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3411	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3412	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3413	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3414	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3415	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3416	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3417	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3418	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3419	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3420	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3421	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3422	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3423	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3424	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3425	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3426	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3427	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3428	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3429	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3430	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3431	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3432	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3433	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3434	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3435	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3436	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3437	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3438	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3439	}
3440
3441
3442	/**
3443	* Helper for dumping the SVM VMCB selector registers.
3444	*
3445	* @param pHlp The info helper functions.
3446	* @param pSel Pointer to the SVM selector register.
3447	* @param pszName Name of the selector.
3448	* @param pszPrefix Caller specified string prefix.
3449	*/
3450	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3451	{
3452	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3453	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3454	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3455	}
3456
3457
3458	/**
3459	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3460	*
3461	* @param pHlp The info helper functions.
3462	* @param pXdtr Pointer to the descriptor table register.
3463	* @param pszName Name of the descriptor table register.
3464	* @param pszPrefix Caller specified string prefix.
3465	*/
3466	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3467	{
3468	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3469	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3470	}
3471
3472
3473	/**
3474	* Displays an SVM VMCB state-save area.
3475	*
3476	* @param pHlp The info helper functions.
3477	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3478	* @param pszPrefix Caller specified string prefix.
3479	*/
3480	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3481	{
3482	AssertReturnVoid(pHlp);
3483	AssertReturnVoid(pVmcbStateSave);
3484
3485	char szEFlags[80];
3486	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3487
3488	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3489	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3490	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3491	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3492	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3493	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3494	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3495	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3496	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3497	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3498	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3499	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3500	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3501	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3502	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3503	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3504	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3505	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3506	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3507	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3508	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3509	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3510	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3511	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3512	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3513	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3514	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3515	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3516	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3517	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3518	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3519	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3520	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3521	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3522	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3523	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3524	}
3525
3526
3527	/**
3528	* Displays a virtual-VMCS.
3529	*
3530	* @param pVCpu The cross context virtual CPU structure.
3531	* @param pHlp The info helper functions.
3532	* @param pVmcs Pointer to a virtual VMCS.
3533	* @param pszPrefix Caller specified string prefix.
3534	*/
3535	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3536	{
3537	AssertReturnVoid(pHlp);
3538	AssertReturnVoid(pVmcs);
3539
3540	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3541	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3542	do { \
3543	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3544	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3545	} while (0)
3546
3547	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3548	do { \
3549	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3550	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3551	} while (0)
3552
3553	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3554	do { \
3555	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3556	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3557	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3558	} while (0)
3559
3560	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3561	do { \
3562	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3563	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3564	} while (0)
3565
3566	/* Header. */
3567	{
3568	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3569	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3570	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3571	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3572	}
3573
3574	/* Control fields. */
3575	{
3576	/* 16-bit. */
3577	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3578	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3579	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3580	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3581
3582	/* 32-bit. */
3583	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3584	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3585	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3586	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3587	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3588	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3589	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3590	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3591	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3592	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3593	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3594	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3595	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3596	{
3597	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3598	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3599	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3600	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3601	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3602	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3603	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3604	}
3605	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3606	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3607	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3608	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3609	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3610
3611	/* 64-bit. */
3612	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3613	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3614	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3615	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3616	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3617	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3618	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3619	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3620	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3621	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3622	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3623	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3624	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3625	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptpPtr.u);
3626	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3627	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3628	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3629	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3630	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3631	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3632	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3633	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3634	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3635	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3636	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3637	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3638	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3639	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3640
3641	/* Natural width. */
3642	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3643	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3644	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3645	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3646	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3647	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3648	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3649	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3650	}
3651
3652	/* Guest state. */
3653	{
3654	char szEFlags[80];
3655	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3656	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3657
3658	/* 16-bit. */
3659	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3660	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3661	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3662	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3663	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3664	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3665	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3666	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3667	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3668	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3669	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3670	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3671
3672	/* 32-bit. */
3673	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3674	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3675	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3676	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3677	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3678
3679	/* 64-bit. */
3680	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3681	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3682	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3683	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3684	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3685	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3686	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3687	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3688	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3689	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3690	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3691	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3692
3693	/* Natural width. */
3694	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3695	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3696	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3697	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3698	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3699	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3700	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3701	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3702	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3703	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3704	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3705	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3706	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3707	}
3708
3709	/* Host state. */
3710	{
3711	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3712
3713	/* 16-bit. */
3714	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3715	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3716	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3717	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3718	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3719	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3720	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3721	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3722	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3723
3724	/* 32-bit. */
3725	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3726
3727	/* 64-bit. */
3728	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3729	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3730	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3731	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3732
3733	/* Natural width. */
3734	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3735	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3736	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3737	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3738	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3739	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3740	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3741	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3742	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3743	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3744
3745	}
3746
3747	/* Read-only fields. */
3748	{
3749	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3750
3751	/* 16-bit (none currently). */
3752
3753	/* 32-bit. */
3754	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3755	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3756	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3757	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
3758	{
3759	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
3760	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
3761	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
3762	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
3763	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
3764	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3765	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3766	}
3767	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
3768	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
3769	{
3770	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
3771	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
3772	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
3773	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
3774	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
3775	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
3776	}
3777	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
3778	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
3779	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
3780
3781	/* 64-bit. */
3782	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
3783
3784	/* Natural width. */
3785	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
3786	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
3787	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
3788	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
3789	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
3790	}
3791
3792	#ifdef DEBUG_ramshankar
3793	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
3794	{
3795	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
3796	Assert(pvPage);
3797	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
3798	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
3799	if (RT_SUCCESS(rc))
3800	{
3801	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
3802	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
3803	pHlp->pfnPrintf(pHlp, "\n");
3804	}
3805	RTMemTmpFree(pvPage);
3806	}
3807	#else
3808	NOREF(pVCpu);
3809	#endif
3810
3811	#undef CPUMVMX_DUMP_HOST_XDTR
3812	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
3813	#undef CPUMVMX_DUMP_GUEST_SEGREG
3814	#undef CPUMVMX_DUMP_GUEST_XDTR
3815	}
3816
3817
3818	/**
3819	* Display the guest's hardware-virtualization cpu state.
3820	*
3821	* @param pVM The cross context VM structure.
3822	* @param pHlp The info helper functions.
3823	* @param pszArgs Arguments, ignored.
3824	*/
3825	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3826	{
3827	RT_NOREF(pszArgs);
3828
3829	PVMCPU pVCpu = VMMGetCpu(pVM);
3830	if (!pVCpu)
3831	pVCpu = pVM->apCpusR3[0];
3832
3833	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3834	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
3835	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
3836
3837	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
3838	pHlp->pfnPrintf(pHlp, "fLocalForcedActions = %#RX32\n", pCtx->hwvirt.fLocalForcedActions);
3839	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
3840
3841	if (fSvm)
3842	{
3843	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
3844	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
3845
3846	char szEFlags[80];
3847	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
3848	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
3849	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
3850	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
3851	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
3852	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
3853	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
3854	pHlp->pfnPrintf(pHlp, " HostState:\n");
3855	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
3856	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
3857	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
3858	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
3859	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
3860	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
3861	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
3862	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
3863	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
3864	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3865	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
3866	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
3867	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3868	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
3869	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
3870	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3871	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
3872	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
3873	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
3874	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
3875	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
3876	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
3877	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
3878	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
3879	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
3880	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
3881	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
3882	}
3883	else if (fVmx)
3884	{
3885	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
3886	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
3887	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
3888	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
3889	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
3890	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
3891	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
3892	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
3893	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
3894	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
3895	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
3896	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
3897	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
3898	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
3899	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
3900	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
3901	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
3902	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
3903	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
3904	}
3905	else
3906	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
3907
3908	#undef CPUMHWVIRTDUMP_NONE
3909	#undef CPUMHWVIRTDUMP_COMMON
3910	#undef CPUMHWVIRTDUMP_SVM
3911	#undef CPUMHWVIRTDUMP_VMX
3912	#undef CPUMHWVIRTDUMP_LAST
3913	#undef CPUMHWVIRTDUMP_ALL
3914	}
3915
3916	/**
3917	* Display the current guest instruction
3918	*
3919	* @param pVM The cross context VM structure.
3920	* @param pHlp The info helper functions.
3921	* @param pszArgs Arguments, ignored.
3922	*/
3923	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3924	{
3925	NOREF(pszArgs);
3926
3927	PVMCPU pVCpu = VMMGetCpu(pVM);
3928	if (!pVCpu)
3929	pVCpu = pVM->apCpusR3[0];
3930
3931	char szInstruction[256];
3932	szInstruction[0] = '\0';
3933	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
3934	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
3935	}
3936
3937
3938	/**
3939	* Display the hypervisor cpu state.
3940	*
3941	* @param pVM The cross context VM structure.
3942	* @param pHlp The info helper functions.
3943	* @param pszArgs Arguments, ignored.
3944	*/
3945	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3946	{
3947	PVMCPU pVCpu = VMMGetCpu(pVM);
3948	if (!pVCpu)
3949	pVCpu = pVM->apCpusR3[0];
3950
3951	CPUMDUMPTYPE enmType;
3952	const char *pszComment;
3953	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3954	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
3955
3956	pHlp->pfnPrintf(pHlp,
3957	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
3958	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
3959	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
3960	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
3961	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
3962	}
3963
3964
3965	/**
3966	* Display the host cpu state.
3967	*
3968	* @param pVM The cross context VM structure.
3969	* @param pHlp The info helper functions.
3970	* @param pszArgs Arguments, ignored.
3971	*/
3972	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3973	{
3974	CPUMDUMPTYPE enmType;
3975	const char *pszComment;
3976	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3977	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
3978
3979	PVMCPU pVCpu = VMMGetCpu(pVM);
3980	if (!pVCpu)
3981	pVCpu = pVM->apCpusR3[0];
3982	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
3983
3984	/*
3985	* Format the EFLAGS.
3986	*/
3987	uint64_t efl = pCtx->rflags;
3988	char szEFlags[80];
3989	cpumR3InfoFormatFlags(&szEFlags[0], efl);
3990
3991	/*
3992	* Format the registers.
3993	*/
3994	pHlp->pfnPrintf(pHlp,
3995	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
3996	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
3997	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
3998	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
3999	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4000	"r14=%016RX64 r15=%016RX64\n"
4001	"iopl=%d %31s\n"
4002	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4003	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4004	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4005	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4006	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4007	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4008	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4009	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4010	,
4011	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4012	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4013	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4014	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4015	pCtx->r11, pCtx->r12, pCtx->r13,
4016	pCtx->r14, pCtx->r15,
4017	X86_EFL_GET_IOPL(efl), szEFlags,
4018	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4019	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4020	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4021	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4022	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4023	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4024	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4025	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4026	}
4027
4028	/**
4029	* Structure used when disassembling and instructions in DBGF.
4030	* This is used so the reader function can get the stuff it needs.
4031	*/
4032	typedef struct CPUMDISASSTATE
4033	{
4034	/** Pointer to the CPU structure. */
4035	PDISCPUSTATE pCpu;
4036	/** Pointer to the VM. */
4037	PVM pVM;
4038	/** Pointer to the VMCPU. */
4039	PVMCPU pVCpu;
4040	/** Pointer to the first byte in the segment. */
4041	RTGCUINTPTR GCPtrSegBase;
4042	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4043	RTGCUINTPTR GCPtrSegEnd;
4044	/** The size of the segment minus 1. */
4045	RTGCUINTPTR cbSegLimit;
4046	/** Pointer to the current page - R3 Ptr. */
4047	void const *pvPageR3;
4048	/** Pointer to the current page - GC Ptr. */
4049	RTGCPTR pvPageGC;
4050	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4051	PGMPAGEMAPLOCK PageMapLock;
4052	/** Whether the PageMapLock is valid or not. */
4053	bool fLocked;
4054	/** 64 bits mode or not. */
4055	bool f64Bits;
4056	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4057
4058
4059	/**
4060	* @callback_method_impl{FNDISREADBYTES}
4061	*/
4062	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4063	{
4064	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4065	for (;;)
4066	{
4067	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4068
4069	/*
4070	* Need to update the page translation?
4071	*/
4072	if ( !pState->pvPageR3
4073	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
4074	{
4075	/* translate the address */
4076	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
4077
4078	/* Release mapping lock previously acquired. */
4079	if (pState->fLocked)
4080	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4081	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4082	if (RT_SUCCESS(rc))
4083	pState->fLocked = true;
4084	else
4085	{
4086	pState->fLocked = false;
4087	pState->pvPageR3 = NULL;
4088	return rc;
4089	}
4090	}
4091
4092	/*
4093	* Check the segment limit.
4094	*/
4095	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4096	return VERR_OUT_OF_SELECTOR_BOUNDS;
4097
4098	/*
4099	* Calc how much we can read.
4100	*/
4101	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
4102	if (!pState->f64Bits)
4103	{
4104	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4105	if (cb > cbSeg && cbSeg)
4106	cb = cbSeg;
4107	}
4108	if (cb > cbMaxRead)
4109	cb = cbMaxRead;
4110
4111	/*
4112	* Read and advance or exit.
4113	*/
4114	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
4115	offInstr += (uint8_t)cb;
4116	if (cb >= cbMinRead)
4117	{
4118	pDis->cbCachedInstr = offInstr;
4119	return VINF_SUCCESS;
4120	}
4121	cbMinRead -= (uint8_t)cb;
4122	cbMaxRead -= (uint8_t)cb;
4123	}
4124	}
4125
4126
4127	/**
4128	* Disassemble an instruction and return the information in the provided structure.
4129	*
4130	* @returns VBox status code.
4131	* @param pVM The cross context VM structure.
4132	* @param pVCpu The cross context virtual CPU structure.
4133	* @param pCtx Pointer to the guest CPU context.
4134	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4135	* @param pCpu Disassembly state.
4136	* @param pszPrefix String prefix for logging (debug only).
4137	*
4138	*/
4139	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4140	const char *pszPrefix)
4141	{
4142	CPUMDISASSTATE State;
4143	int rc;
4144
4145	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4146	State.pCpu = pCpu;
4147	State.pvPageGC = 0;
4148	State.pvPageR3 = NULL;
4149	State.pVM = pVM;
4150	State.pVCpu = pVCpu;
4151	State.fLocked = false;
4152	State.f64Bits = false;
4153
4154	/*
4155	* Get selector information.
4156	*/
4157	DISCPUMODE enmDisCpuMode;
4158	if ( (pCtx->cr0 & X86_CR0_PE)
4159	&& pCtx->eflags.Bits.u1VM == 0)
4160	{
4161	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4162	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4163	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4164	State.GCPtrSegBase = pCtx->cs.u64Base;
4165	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4166	State.cbSegLimit = pCtx->cs.u32Limit;
4167	enmDisCpuMode = (State.f64Bits)
4168	? DISCPUMODE_64BIT
4169	: pCtx->cs.Attr.n.u1DefBig
4170	? DISCPUMODE_32BIT
4171	: DISCPUMODE_16BIT;
4172	}
4173	else
4174	{
4175	/* real or V86 mode */
4176	enmDisCpuMode = DISCPUMODE_16BIT;
4177	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4178	State.GCPtrSegEnd = 0xFFFFFFFF;
4179	State.cbSegLimit = 0xFFFFFFFF;
4180	}
4181
4182	/*
4183	* Disassemble the instruction.
4184	*/
4185	uint32_t cbInstr;
4186	#ifndef LOG_ENABLED
4187	RT_NOREF_PV(pszPrefix);
4188	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4189	if (RT_SUCCESS(rc))
4190	{
4191	#else
4192	char szOutput[160];
4193	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4194	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4195	if (RT_SUCCESS(rc))
4196	{
4197	/* log it */
4198	if (pszPrefix)
4199	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4200	else
4201	Log(("%s", szOutput));
4202	#endif
4203	rc = VINF_SUCCESS;
4204	}
4205	else
4206	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4207
4208	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4209	if (State.fLocked)
4210	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4211
4212	return rc;
4213	}
4214
4215
4216
4217	/**
4218	* API for controlling a few of the CPU features found in CR4.
4219	*
4220	* Currently only X86_CR4_TSD is accepted as input.
4221	*
4222	* @returns VBox status code.
4223	*
4224	* @param pVM The cross context VM structure.
4225	* @param fOr The CR4 OR mask.
4226	* @param fAnd The CR4 AND mask.
4227	*/
4228	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4229	{
4230	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4231	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4232
4233	pVM->cpum.s.CR4.OrMask &= fAnd;
4234	pVM->cpum.s.CR4.OrMask \|= fOr;
4235
4236	return VINF_SUCCESS;
4237	}
4238
4239
4240	/**
4241	* Called when the ring-3 init phase completes.
4242	*
4243	* @returns VBox status code.
4244	* @param pVM The cross context VM structure.
4245	* @param enmWhat Which init phase.
4246	*/
4247	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4248	{
4249	switch (enmWhat)
4250	{
4251	case VMINITCOMPLETED_RING3:
4252	{
4253	/*
4254	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4255	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4256	*/
4257	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4258	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4259	{
4260	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4261
4262	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4263	if (fSupportsLongMode)
4264	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4265	}
4266
4267	/* Register statistic counters for MSRs. */
4268	cpumR3MsrRegStats(pVM);
4269
4270	/* Create VMX-preemption timer for nested guests if required. Must be
4271	done here as CPUM is initialized before TM. */
4272	if (pVM->cpum.s.GuestFeatures.fVmx)
4273	{
4274	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4275	{
4276	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4277	char szName[32];
4278	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4279	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4280	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4281	AssertLogRelRCReturn(rc, rc);
4282	}
4283	}
4284	break;
4285	}
4286
4287	default:
4288	break;
4289	}
4290	return VINF_SUCCESS;
4291	}
4292
4293
4294	/**
4295	* Called when the ring-0 init phases completed.
4296	*
4297	* @param pVM The cross context VM structure.
4298	*/
4299	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4300	{
4301	/*
4302	* Enable log buffering as we're going to log a lot of lines.
4303	*/
4304	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4305
4306	/*
4307	* Log the cpuid.
4308	*/
4309	RTCPUSET OnlineSet;
4310	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4311	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4312	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4313	RTCPUID cCores = RTMpGetCoreCount();
4314	if (cCores)
4315	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4316	LogRel(("*********************** CPUID dump **********************\n"));
4317	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4318	LogRel(("\n"));
4319	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4320	LogRel(("****************** End of CPUID dump ********************\n"));
4321
4322	/*
4323	* Log VT-x extended features.
4324	*
4325	* SVM features are currently all covered under CPUID so there is nothing
4326	* to do here for SVM.
4327	*/
4328	if (pVM->cpum.s.HostFeatures.fVmx)
4329	{
4330	LogRel(("********************* VT-x features *********************\n"));
4331	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4332	LogRel(("\n"));
4333	LogRel(("***************** End of VT-x features ******************\n"));
4334	}
4335
4336	/*
4337	* Restore the log buffering state to what it was previously.
4338	*/
4339	RTLogRelSetBuffering(fOldBuffered);
4340	}
4341

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 91358

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