CPUM.cpp@ 97295

Last change on this file since 97295 was 97286, checked in by vboxsync, 2 years ago
VMM/CPUM,IEM: Moved the CPUMCTX_INHIBIT_XXX flags into reserved EFLAGS space.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 246.8 KB

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1	/* $Id: CPUM.cpp 97286 2022-10-24 22:15:44Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	/** @page pg_cpum CPUM - CPU Monitor / Manager
29	*
30	* The CPU Monitor / Manager keeps track of all the CPU registers. It is
31	* also responsible for lazy FPU handling and some of the context loading
32	* in raw mode.
33	*
34	* There are three CPU contexts, the most important one is the guest one (GC).
35	* When running in raw-mode (RC) there is a special hyper context for the VMM
36	* part that floats around inside the guest address space. When running in
37	* raw-mode, CPUM also maintains a host context for saving and restoring
38	* registers across world switches. This latter is done in cooperation with the
39	* world switcher (@see pg_vmm).
40	*
41	* @see grp_cpum
42	*
43	* @section sec_cpum_fpu FPU / SSE / AVX / ++ state.
44	*
45	* TODO: proper write up, currently just some notes.
46	*
47	* The ring-0 FPU handling per OS:
48	*
49	* - 64-bit Windows uses XMM registers in the kernel as part of the calling
50	* convention (Visual C++ doesn't seem to have a way to disable
51	* generating such code either), so CR0.TS/EM are always zero from what I
52	* can tell. We are also forced to always load/save the guest XMM0-XMM15
53	* registers when entering/leaving guest context. Interrupt handlers
54	* using FPU/SSE will offically have call save and restore functions
55	* exported by the kernel, if the really really have to use the state.
56	*
57	* - 32-bit windows does lazy FPU handling, I think, probably including
58	* lazying saving. The Windows Internals book states that it's a bad
59	* idea to use the FPU in kernel space. However, it looks like it will
60	* restore the FPU state of the current thread in case of a kernel \#NM.
61	* Interrupt handlers should be same as for 64-bit.
62	*
63	* - Darwin allows taking \#NM in kernel space, restoring current thread's
64	* state if I read the code correctly. It saves the FPU state of the
65	* outgoing thread, and uses CR0.TS to lazily load the state of the
66	* incoming one. No idea yet how the FPU is treated by interrupt
67	* handlers, i.e. whether they are allowed to disable the state or
68	* something.
69	*
70	* - Linux also allows \#NM in kernel space (don't know since when), and
71	* uses CR0.TS for lazy loading. Saves outgoing thread's state, lazy
72	* loads the incoming unless configured to agressivly load it. Interrupt
73	* handlers can ask whether they're allowed to use the FPU, and may
74	* freely trash the state if Linux thinks it has saved the thread's state
75	* already. This is a problem.
76	*
77	* - Solaris will, from what I can tell, panic if it gets an \#NM in kernel
78	* context. When switching threads, the kernel will save the state of
79	* the outgoing thread and lazy load the incoming one using CR0.TS.
80	* There are a few routines in seeblk.s which uses the SSE unit in ring-0
81	* to do stuff, HAT are among the users. The routines there will
82	* manually clear CR0.TS and save the XMM registers they use only if
83	* CR0.TS was zero upon entry. They will skip it when not, because as
84	* mentioned above, the FPU state is saved when switching away from a
85	* thread and CR0.TS set to 1, so when CR0.TS is 1 there is nothing to
86	* preserve. This is a problem if we restore CR0.TS to 1 after loading
87	* the guest state.
88	*
89	* - FreeBSD - no idea yet.
90	*
91	* - OS/2 does not allow \#NMs in kernel space IIRC. Does lazy loading,
92	* possibly also lazy saving. Interrupts must preserve the CR0.TS+EM &
93	* FPU states.
94	*
95	* Up to r107425 (2016-05-24) we would only temporarily modify CR0.TS/EM while
96	* saving and restoring the host and guest states. The motivation for this
97	* change is that we want to be able to emulate SSE instruction in ring-0 (IEM).
98	*
99	* Starting with that change, we will leave CR0.TS=EM=0 after saving the host
100	* state and only restore it once we've restore the host FPU state. This has the
101	* accidental side effect of triggering Solaris to preserve XMM registers in
102	* sseblk.s. When CR0 was changed by saving the FPU state, CPUM must now inform
103	* the VT-x (HMVMX) code about it as it caches the CR0 value in the VMCS.
104	*
105	*
106	* @section sec_cpum_logging Logging Level Assignments.
107	*
108	* Following log level assignments:
109	* - Log6 is used for FPU state management.
110	* - Log7 is used for FPU state actualization.
111	*
112	*/
113
114
115	/*********************************************************************************************************************************
116	* Header Files *
117	*********************************************************************************************************************************/
118	#define LOG_GROUP LOG_GROUP_CPUM
119	#define CPUM_WITH_NONCONST_HOST_FEATURES
120	#include <VBox/vmm/cpum.h>
121	#include <VBox/vmm/cpumdis.h>
122	#include <VBox/vmm/cpumctx-v1_6.h>
123	#include <VBox/vmm/pgm.h>
124	#include <VBox/vmm/apic.h>
125	#include <VBox/vmm/mm.h>
126	#include <VBox/vmm/em.h>
127	#include <VBox/vmm/iem.h>
128	#include <VBox/vmm/selm.h>
129	#include <VBox/vmm/dbgf.h>
130	#include <VBox/vmm/hm.h>
131	#include <VBox/vmm/hmvmxinline.h>
132	#include <VBox/vmm/ssm.h>
133	#include "CPUMInternal.h"
134	#include <VBox/vmm/vm.h>
135
136	#include <VBox/param.h>
137	#include <VBox/dis.h>
138	#include <VBox/err.h>
139	#include <VBox/log.h>
140	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
141	# include <iprt/asm-amd64-x86.h>
142	#endif
143	#include <iprt/assert.h>
144	#include <iprt/cpuset.h>
145	#include <iprt/mem.h>
146	#include <iprt/mp.h>
147	#include <iprt/rand.h>
148	#include <iprt/string.h>
149
150
151	/*********************************************************************************************************************************
152	* Defined Constants And Macros *
153	*********************************************************************************************************************************/
154	/**
155	* This was used in the saved state up to the early life of version 14.
156	*
157	* It indicates that we may have some out-of-sync hidden segement registers.
158	* It is only relevant for raw-mode.
159	*/
160	#define CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID RT_BIT(12)
161
162
163	/** For saved state only: Block injection of non-maskable interrupts to the guest.
164	* @note This flag was moved to CPUMCTX::eflags.uBoth in v7.0.4. */
165	#define CPUM_OLD_VMCPU_FF_BLOCK_NMIS RT_BIT_64(25)
166
167
168	/*********************************************************************************************************************************
169	* Structures and Typedefs *
170	*********************************************************************************************************************************/
171
172	/**
173	* What kind of cpu info dump to perform.
174	*/
175	typedef enum CPUMDUMPTYPE
176	{
177	CPUMDUMPTYPE_TERSE,
178	CPUMDUMPTYPE_DEFAULT,
179	CPUMDUMPTYPE_VERBOSE
180	} CPUMDUMPTYPE;
181	/** Pointer to a cpu info dump type. */
182	typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
183
184
185	/*********************************************************************************************************************************
186	* Internal Functions *
187	*********************************************************************************************************************************/
188	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass);
189	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM);
190	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM);
191	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
192	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
193	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
194	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
195	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
196	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
197	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
198	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
199
200
201	/*********************************************************************************************************************************
202	* Global Variables *
203	*********************************************************************************************************************************/
204	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
205	/** Host CPU features. */
206	DECL_HIDDEN_DATA(CPUHOSTFEATURES) g_CpumHostFeatures;
207	#endif
208
209	/** Saved state field descriptors for CPUMCTX. */
210	static const SSMFIELD g_aCpumCtxFields[] =
211	{
212	SSMFIELD_ENTRY( CPUMCTX, rdi),
213	SSMFIELD_ENTRY( CPUMCTX, rsi),
214	SSMFIELD_ENTRY( CPUMCTX, rbp),
215	SSMFIELD_ENTRY( CPUMCTX, rax),
216	SSMFIELD_ENTRY( CPUMCTX, rbx),
217	SSMFIELD_ENTRY( CPUMCTX, rdx),
218	SSMFIELD_ENTRY( CPUMCTX, rcx),
219	SSMFIELD_ENTRY( CPUMCTX, rsp),
220	SSMFIELD_ENTRY( CPUMCTX, rflags),
221	SSMFIELD_ENTRY( CPUMCTX, rip),
222	SSMFIELD_ENTRY( CPUMCTX, r8),
223	SSMFIELD_ENTRY( CPUMCTX, r9),
224	SSMFIELD_ENTRY( CPUMCTX, r10),
225	SSMFIELD_ENTRY( CPUMCTX, r11),
226	SSMFIELD_ENTRY( CPUMCTX, r12),
227	SSMFIELD_ENTRY( CPUMCTX, r13),
228	SSMFIELD_ENTRY( CPUMCTX, r14),
229	SSMFIELD_ENTRY( CPUMCTX, r15),
230	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
231	SSMFIELD_ENTRY( CPUMCTX, es.ValidSel),
232	SSMFIELD_ENTRY( CPUMCTX, es.fFlags),
233	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
234	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
235	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
236	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
237	SSMFIELD_ENTRY( CPUMCTX, cs.ValidSel),
238	SSMFIELD_ENTRY( CPUMCTX, cs.fFlags),
239	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
240	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
241	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
242	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
243	SSMFIELD_ENTRY( CPUMCTX, ss.ValidSel),
244	SSMFIELD_ENTRY( CPUMCTX, ss.fFlags),
245	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
246	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
247	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
248	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
249	SSMFIELD_ENTRY( CPUMCTX, ds.ValidSel),
250	SSMFIELD_ENTRY( CPUMCTX, ds.fFlags),
251	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
252	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
253	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
254	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
255	SSMFIELD_ENTRY( CPUMCTX, fs.ValidSel),
256	SSMFIELD_ENTRY( CPUMCTX, fs.fFlags),
257	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
258	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
259	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
260	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
261	SSMFIELD_ENTRY( CPUMCTX, gs.ValidSel),
262	SSMFIELD_ENTRY( CPUMCTX, gs.fFlags),
263	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
264	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
265	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
266	SSMFIELD_ENTRY( CPUMCTX, cr0),
267	SSMFIELD_ENTRY( CPUMCTX, cr2),
268	SSMFIELD_ENTRY( CPUMCTX, cr3),
269	SSMFIELD_ENTRY( CPUMCTX, cr4),
270	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
271	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
272	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
273	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
274	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
275	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
276	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
277	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
278	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
279	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
280	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
281	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
282	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
283	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
284	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
285	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
286	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
287	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
288	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
289	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
290	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
291	SSMFIELD_ENTRY( CPUMCTX, ldtr.ValidSel),
292	SSMFIELD_ENTRY( CPUMCTX, ldtr.fFlags),
293	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
294	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
295	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
296	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
297	SSMFIELD_ENTRY( CPUMCTX, tr.ValidSel),
298	SSMFIELD_ENTRY( CPUMCTX, tr.fFlags),
299	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
300	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
301	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
302	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[0], CPUM_SAVED_STATE_VERSION_XSAVE),
303	SSMFIELD_ENTRY_VER( CPUMCTX, aXcr[1], CPUM_SAVED_STATE_VERSION_XSAVE),
304	SSMFIELD_ENTRY_VER( CPUMCTX, fXStateMask, CPUM_SAVED_STATE_VERSION_XSAVE),
305	SSMFIELD_ENTRY_TERM()
306	};
307
308	/** Saved state field descriptors for SVM nested hardware-virtualization
309	* Host State. */
310	static const SSMFIELD g_aSvmHwvirtHostState[] =
311	{
312	SSMFIELD_ENTRY( SVMHOSTSTATE, uEferMsr),
313	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr0),
314	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr4),
315	SSMFIELD_ENTRY( SVMHOSTSTATE, uCr3),
316	SSMFIELD_ENTRY( SVMHOSTSTATE, uRip),
317	SSMFIELD_ENTRY( SVMHOSTSTATE, uRsp),
318	SSMFIELD_ENTRY( SVMHOSTSTATE, uRax),
319	SSMFIELD_ENTRY( SVMHOSTSTATE, rflags),
320	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Sel),
321	SSMFIELD_ENTRY( SVMHOSTSTATE, es.ValidSel),
322	SSMFIELD_ENTRY( SVMHOSTSTATE, es.fFlags),
323	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u64Base),
324	SSMFIELD_ENTRY( SVMHOSTSTATE, es.u32Limit),
325	SSMFIELD_ENTRY( SVMHOSTSTATE, es.Attr),
326	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Sel),
327	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.ValidSel),
328	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.fFlags),
329	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u64Base),
330	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.u32Limit),
331	SSMFIELD_ENTRY( SVMHOSTSTATE, cs.Attr),
332	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Sel),
333	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.ValidSel),
334	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.fFlags),
335	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u64Base),
336	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.u32Limit),
337	SSMFIELD_ENTRY( SVMHOSTSTATE, ss.Attr),
338	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Sel),
339	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.ValidSel),
340	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.fFlags),
341	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u64Base),
342	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.u32Limit),
343	SSMFIELD_ENTRY( SVMHOSTSTATE, ds.Attr),
344	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.cbGdt),
345	SSMFIELD_ENTRY( SVMHOSTSTATE, gdtr.pGdt),
346	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.cbIdt),
347	SSMFIELD_ENTRY( SVMHOSTSTATE, idtr.pIdt),
348	SSMFIELD_ENTRY_IGNORE(SVMHOSTSTATE, abPadding),
349	SSMFIELD_ENTRY_TERM()
350	};
351
352	/** Saved state field descriptors for VMX nested hardware-virtualization
353	* VMCS. */
354	static const SSMFIELD g_aVmxHwvirtVmcs[] =
355	{
356	SSMFIELD_ENTRY( VMXVVMCS, u32VmcsRevId),
357	SSMFIELD_ENTRY( VMXVVMCS, enmVmxAbort),
358	SSMFIELD_ENTRY( VMXVVMCS, fVmcsState),
359	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au8Padding0),
360	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved0),
361
362	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, u16Reserved0),
363
364	SSMFIELD_ENTRY( VMXVVMCS, u32RoVmInstrError),
365	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitReason),
366	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntInfo),
367	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitIntErrCode),
368	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringInfo),
369	SSMFIELD_ENTRY( VMXVVMCS, u32RoIdtVectoringErrCode),
370	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrLen),
371	SSMFIELD_ENTRY( VMXVVMCS, u32RoExitInstrInfo),
372	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32RoReserved2),
373
374	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestPhysAddr),
375	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved1),
376
377	SSMFIELD_ENTRY( VMXVVMCS, u64RoExitQual),
378	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRcx),
379	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRsi),
380	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRdi),
381	SSMFIELD_ENTRY( VMXVVMCS, u64RoIoRip),
382	SSMFIELD_ENTRY( VMXVVMCS, u64RoGuestLinearAddr),
383	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved5),
384
385	SSMFIELD_ENTRY( VMXVVMCS, u16Vpid),
386	SSMFIELD_ENTRY( VMXVVMCS, u16PostIntNotifyVector),
387	SSMFIELD_ENTRY( VMXVVMCS, u16EptpIndex),
388	SSMFIELD_ENTRY_VER( VMXVVMCS, u16HlatPrefixSize, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
389	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved0),
390
391	SSMFIELD_ENTRY( VMXVVMCS, u32PinCtls),
392	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls),
393	SSMFIELD_ENTRY( VMXVVMCS, u32XcptBitmap),
394	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMask),
395	SSMFIELD_ENTRY( VMXVVMCS, u32XcptPFMatch),
396	SSMFIELD_ENTRY( VMXVVMCS, u32Cr3TargetCount),
397	SSMFIELD_ENTRY( VMXVVMCS, u32ExitCtls),
398	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrStoreCount),
399	SSMFIELD_ENTRY( VMXVVMCS, u32ExitMsrLoadCount),
400	SSMFIELD_ENTRY( VMXVVMCS, u32EntryCtls),
401	SSMFIELD_ENTRY( VMXVVMCS, u32EntryMsrLoadCount),
402	SSMFIELD_ENTRY( VMXVVMCS, u32EntryIntInfo),
403	SSMFIELD_ENTRY( VMXVVMCS, u32EntryXcptErrCode),
404	SSMFIELD_ENTRY( VMXVVMCS, u32EntryInstrLen),
405	SSMFIELD_ENTRY( VMXVVMCS, u32TprThreshold),
406	SSMFIELD_ENTRY( VMXVVMCS, u32ProcCtls2),
407	SSMFIELD_ENTRY( VMXVVMCS, u32PleGap),
408	SSMFIELD_ENTRY( VMXVVMCS, u32PleWindow),
409	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved1),
410
411	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapA),
412	SSMFIELD_ENTRY( VMXVVMCS, u64AddrIoBitmapB),
413	SSMFIELD_ENTRY( VMXVVMCS, u64AddrMsrBitmap),
414	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrStore),
415	SSMFIELD_ENTRY( VMXVVMCS, u64AddrExitMsrLoad),
416	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEntryMsrLoad),
417	SSMFIELD_ENTRY( VMXVVMCS, u64ExecVmcsPtr),
418	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPml),
419	SSMFIELD_ENTRY( VMXVVMCS, u64TscOffset),
420	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVirtApic),
421	SSMFIELD_ENTRY( VMXVVMCS, u64AddrApicAccess),
422	SSMFIELD_ENTRY( VMXVVMCS, u64AddrPostedIntDesc),
423	SSMFIELD_ENTRY( VMXVVMCS, u64VmFuncCtls),
424	SSMFIELD_ENTRY( VMXVVMCS, u64EptPtr),
425	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap0),
426	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap1),
427	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap2),
428	SSMFIELD_ENTRY( VMXVVMCS, u64EoiExitBitmap3),
429	SSMFIELD_ENTRY( VMXVVMCS, u64AddrEptpList),
430	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmreadBitmap),
431	SSMFIELD_ENTRY( VMXVVMCS, u64AddrVmwriteBitmap),
432	SSMFIELD_ENTRY( VMXVVMCS, u64AddrXcptVeInfo),
433	SSMFIELD_ENTRY( VMXVVMCS, u64XssExitBitmap),
434	SSMFIELD_ENTRY( VMXVVMCS, u64EnclsExitBitmap),
435	SSMFIELD_ENTRY( VMXVVMCS, u64SppTablePtr),
436	SSMFIELD_ENTRY( VMXVVMCS, u64TscMultiplier),
437	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ProcCtls3, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
438	SSMFIELD_ENTRY_VER( VMXVVMCS, u64EnclvExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
439	SSMFIELD_ENTRY_VER( VMXVVMCS, u64PconfigExitBitmap, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
440	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HlatPtr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
441	SSMFIELD_ENTRY_VER( VMXVVMCS, u64ExitCtls2, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3),
442	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved0),
443
444	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0Mask),
445	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4Mask),
446	SSMFIELD_ENTRY( VMXVVMCS, u64Cr0ReadShadow),
447	SSMFIELD_ENTRY( VMXVVMCS, u64Cr4ReadShadow),
448	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target0),
449	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target1),
450	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target2),
451	SSMFIELD_ENTRY( VMXVVMCS, u64Cr3Target3),
452	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved4),
453
454	SSMFIELD_ENTRY( VMXVVMCS, HostEs),
455	SSMFIELD_ENTRY( VMXVVMCS, HostCs),
456	SSMFIELD_ENTRY( VMXVVMCS, HostSs),
457	SSMFIELD_ENTRY( VMXVVMCS, HostDs),
458	SSMFIELD_ENTRY( VMXVVMCS, HostFs),
459	SSMFIELD_ENTRY( VMXVVMCS, HostGs),
460	SSMFIELD_ENTRY( VMXVVMCS, HostTr),
461	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved2),
462
463	SSMFIELD_ENTRY( VMXVVMCS, u32HostSysenterCs),
464	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved4),
465
466	SSMFIELD_ENTRY( VMXVVMCS, u64HostPatMsr),
467	SSMFIELD_ENTRY( VMXVVMCS, u64HostEferMsr),
468	SSMFIELD_ENTRY( VMXVVMCS, u64HostPerfGlobalCtlMsr),
469	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
470	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved3),
471
472	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr0),
473	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr3),
474	SSMFIELD_ENTRY( VMXVVMCS, u64HostCr4),
475	SSMFIELD_ENTRY( VMXVVMCS, u64HostFsBase),
476	SSMFIELD_ENTRY( VMXVVMCS, u64HostGsBase),
477	SSMFIELD_ENTRY( VMXVVMCS, u64HostTrBase),
478	SSMFIELD_ENTRY( VMXVVMCS, u64HostGdtrBase),
479	SSMFIELD_ENTRY( VMXVVMCS, u64HostIdtrBase),
480	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEsp),
481	SSMFIELD_ENTRY( VMXVVMCS, u64HostSysenterEip),
482	SSMFIELD_ENTRY( VMXVVMCS, u64HostRsp),
483	SSMFIELD_ENTRY( VMXVVMCS, u64HostRip),
484	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
485	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
486	SSMFIELD_ENTRY_VER( VMXVVMCS, u64HostIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
487	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved7),
488
489	SSMFIELD_ENTRY( VMXVVMCS, GuestEs),
490	SSMFIELD_ENTRY( VMXVVMCS, GuestCs),
491	SSMFIELD_ENTRY( VMXVVMCS, GuestSs),
492	SSMFIELD_ENTRY( VMXVVMCS, GuestDs),
493	SSMFIELD_ENTRY( VMXVVMCS, GuestFs),
494	SSMFIELD_ENTRY( VMXVVMCS, GuestGs),
495	SSMFIELD_ENTRY( VMXVVMCS, GuestLdtr),
496	SSMFIELD_ENTRY( VMXVVMCS, GuestTr),
497	SSMFIELD_ENTRY( VMXVVMCS, u16GuestIntStatus),
498	SSMFIELD_ENTRY( VMXVVMCS, u16PmlIndex),
499	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au16Reserved1),
500
501	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsLimit),
502	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsLimit),
503	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsLimit),
504	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsLimit),
505	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsLimit),
506	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsLimit),
507	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrLimit),
508	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrLimit),
509	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGdtrLimit),
510	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIdtrLimit),
511	SSMFIELD_ENTRY( VMXVVMCS, u32GuestEsAttr),
512	SSMFIELD_ENTRY( VMXVVMCS, u32GuestCsAttr),
513	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSsAttr),
514	SSMFIELD_ENTRY( VMXVVMCS, u32GuestDsAttr),
515	SSMFIELD_ENTRY( VMXVVMCS, u32GuestFsAttr),
516	SSMFIELD_ENTRY( VMXVVMCS, u32GuestGsAttr),
517	SSMFIELD_ENTRY( VMXVVMCS, u32GuestLdtrAttr),
518	SSMFIELD_ENTRY( VMXVVMCS, u32GuestTrAttr),
519	SSMFIELD_ENTRY( VMXVVMCS, u32GuestIntrState),
520	SSMFIELD_ENTRY( VMXVVMCS, u32GuestActivityState),
521	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSmBase),
522	SSMFIELD_ENTRY( VMXVVMCS, u32GuestSysenterCS),
523	SSMFIELD_ENTRY( VMXVVMCS, u32PreemptTimer),
524	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au32Reserved3),
525
526	SSMFIELD_ENTRY( VMXVVMCS, u64VmcsLinkPtr),
527	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDebugCtlMsr),
528	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPatMsr),
529	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEferMsr),
530	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPerfGlobalCtlMsr),
531	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte0),
532	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte1),
533	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte2),
534	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPdpte3),
535	SSMFIELD_ENTRY( VMXVVMCS, u64GuestBndcfgsMsr),
536	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRtitCtlMsr),
537	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestPkrsMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
538	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved2),
539
540	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr0),
541	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr3),
542	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCr4),
543	SSMFIELD_ENTRY( VMXVVMCS, u64GuestEsBase),
544	SSMFIELD_ENTRY( VMXVVMCS, u64GuestCsBase),
545	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSsBase),
546	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDsBase),
547	SSMFIELD_ENTRY( VMXVVMCS, u64GuestFsBase),
548	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGsBase),
549	SSMFIELD_ENTRY( VMXVVMCS, u64GuestLdtrBase),
550	SSMFIELD_ENTRY( VMXVVMCS, u64GuestTrBase),
551	SSMFIELD_ENTRY( VMXVVMCS, u64GuestGdtrBase),
552	SSMFIELD_ENTRY( VMXVVMCS, u64GuestIdtrBase),
553	SSMFIELD_ENTRY( VMXVVMCS, u64GuestDr7),
554	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRsp),
555	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRip),
556	SSMFIELD_ENTRY( VMXVVMCS, u64GuestRFlags),
557	SSMFIELD_ENTRY( VMXVVMCS, u64GuestPendingDbgXcpts),
558	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEsp),
559	SSMFIELD_ENTRY( VMXVVMCS, u64GuestSysenterEip),
560	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSCetMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
561	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestSsp, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
562	SSMFIELD_ENTRY_VER( VMXVVMCS, u64GuestIntrSspTableAddrMsr, CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2),
563	SSMFIELD_ENTRY_IGNORE(VMXVVMCS, au64Reserved6),
564
565	SSMFIELD_ENTRY_TERM()
566	};
567
568	/** Saved state field descriptors for CPUMCTX. */
569	static const SSMFIELD g_aCpumX87Fields[] =
570	{
571	SSMFIELD_ENTRY( X86FXSTATE, FCW),
572	SSMFIELD_ENTRY( X86FXSTATE, FSW),
573	SSMFIELD_ENTRY( X86FXSTATE, FTW),
574	SSMFIELD_ENTRY( X86FXSTATE, FOP),
575	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
576	SSMFIELD_ENTRY( X86FXSTATE, CS),
577	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
578	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
579	SSMFIELD_ENTRY( X86FXSTATE, DS),
580	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
581	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
582	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
583	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
584	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
585	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
586	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
587	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
588	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
589	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
590	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
591	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
592	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
593	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
594	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
595	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
596	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
597	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
598	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
599	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
600	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
601	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
602	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
603	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
604	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
605	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
606	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
607	SSMFIELD_ENTRY_VER( X86FXSTATE, au32RsrvdForSoftware[0], CPUM_SAVED_STATE_VERSION_XSAVE), /* 32-bit/64-bit hack */
608	SSMFIELD_ENTRY_TERM()
609	};
610
611	/** Saved state field descriptors for X86XSAVEHDR. */
612	static const SSMFIELD g_aCpumXSaveHdrFields[] =
613	{
614	SSMFIELD_ENTRY( X86XSAVEHDR, bmXState),
615	SSMFIELD_ENTRY_TERM()
616	};
617
618	/** Saved state field descriptors for X86XSAVEYMMHI. */
619	static const SSMFIELD g_aCpumYmmHiFields[] =
620	{
621	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[0]),
622	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[1]),
623	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[2]),
624	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[3]),
625	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[4]),
626	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[5]),
627	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[6]),
628	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[7]),
629	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[8]),
630	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[9]),
631	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[10]),
632	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[11]),
633	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[12]),
634	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[13]),
635	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[14]),
636	SSMFIELD_ENTRY( X86XSAVEYMMHI, aYmmHi[15]),
637	SSMFIELD_ENTRY_TERM()
638	};
639
640	/** Saved state field descriptors for X86XSAVEBNDREGS. */
641	static const SSMFIELD g_aCpumBndRegsFields[] =
642	{
643	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[0]),
644	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[1]),
645	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[2]),
646	SSMFIELD_ENTRY( X86XSAVEBNDREGS, aRegs[3]),
647	SSMFIELD_ENTRY_TERM()
648	};
649
650	/** Saved state field descriptors for X86XSAVEBNDCFG. */
651	static const SSMFIELD g_aCpumBndCfgFields[] =
652	{
653	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fConfig),
654	SSMFIELD_ENTRY( X86XSAVEBNDCFG, fStatus),
655	SSMFIELD_ENTRY_TERM()
656	};
657
658	#if 0 /** @todo */
659	/** Saved state field descriptors for X86XSAVEOPMASK. */
660	static const SSMFIELD g_aCpumOpmaskFields[] =
661	{
662	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[0]),
663	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[1]),
664	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[2]),
665	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[3]),
666	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[4]),
667	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[5]),
668	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[6]),
669	SSMFIELD_ENTRY( X86XSAVEOPMASK, aKRegs[7]),
670	SSMFIELD_ENTRY_TERM()
671	};
672	#endif
673
674	/** Saved state field descriptors for X86XSAVEZMMHI256. */
675	static const SSMFIELD g_aCpumZmmHi256Fields[] =
676	{
677	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[0]),
678	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[1]),
679	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[2]),
680	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[3]),
681	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[4]),
682	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[5]),
683	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[6]),
684	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[7]),
685	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[8]),
686	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[9]),
687	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[10]),
688	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[11]),
689	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[12]),
690	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[13]),
691	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[14]),
692	SSMFIELD_ENTRY( X86XSAVEZMMHI256, aHi256Regs[15]),
693	SSMFIELD_ENTRY_TERM()
694	};
695
696	/** Saved state field descriptors for X86XSAVEZMM16HI. */
697	static const SSMFIELD g_aCpumZmm16HiFields[] =
698	{
699	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[0]),
700	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[1]),
701	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[2]),
702	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[3]),
703	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[4]),
704	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[5]),
705	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[6]),
706	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[7]),
707	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[8]),
708	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[9]),
709	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[10]),
710	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[11]),
711	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[12]),
712	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[13]),
713	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[14]),
714	SSMFIELD_ENTRY( X86XSAVEZMM16HI, aRegs[15]),
715	SSMFIELD_ENTRY_TERM()
716	};
717
718
719
720	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
721	* registeres changed. */
722	static const SSMFIELD g_aCpumX87FieldsMem[] =
723	{
724	SSMFIELD_ENTRY( X86FXSTATE, FCW),
725	SSMFIELD_ENTRY( X86FXSTATE, FSW),
726	SSMFIELD_ENTRY( X86FXSTATE, FTW),
727	SSMFIELD_ENTRY( X86FXSTATE, FOP),
728	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
729	SSMFIELD_ENTRY( X86FXSTATE, CS),
730	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
731	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
732	SSMFIELD_ENTRY( X86FXSTATE, DS),
733	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
734	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
735	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
736	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
737	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
738	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
739	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
740	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
741	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
742	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
743	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
744	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
745	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
746	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
747	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
748	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
749	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
750	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
751	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
752	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
753	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
754	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
755	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
756	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
757	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
758	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
759	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
760	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
761	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
762	};
763
764	/** Saved state field descriptors for CPUMCTX in V4.1 before the hidden selector
765	* registeres changed. */
766	static const SSMFIELD g_aCpumCtxFieldsMem[] =
767	{
768	SSMFIELD_ENTRY( CPUMCTX, rdi),
769	SSMFIELD_ENTRY( CPUMCTX, rsi),
770	SSMFIELD_ENTRY( CPUMCTX, rbp),
771	SSMFIELD_ENTRY( CPUMCTX, rax),
772	SSMFIELD_ENTRY( CPUMCTX, rbx),
773	SSMFIELD_ENTRY( CPUMCTX, rdx),
774	SSMFIELD_ENTRY( CPUMCTX, rcx),
775	SSMFIELD_ENTRY( CPUMCTX, rsp),
776	SSMFIELD_ENTRY_OLD( lss_esp, sizeof(uint32_t)),
777	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
778	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
779	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
780	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
781	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
782	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
783	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
784	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
785	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
786	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
787	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
788	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
789	SSMFIELD_ENTRY( CPUMCTX, rflags),
790	SSMFIELD_ENTRY( CPUMCTX, rip),
791	SSMFIELD_ENTRY( CPUMCTX, r8),
792	SSMFIELD_ENTRY( CPUMCTX, r9),
793	SSMFIELD_ENTRY( CPUMCTX, r10),
794	SSMFIELD_ENTRY( CPUMCTX, r11),
795	SSMFIELD_ENTRY( CPUMCTX, r12),
796	SSMFIELD_ENTRY( CPUMCTX, r13),
797	SSMFIELD_ENTRY( CPUMCTX, r14),
798	SSMFIELD_ENTRY( CPUMCTX, r15),
799	SSMFIELD_ENTRY( CPUMCTX, es.u64Base),
800	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
801	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
802	SSMFIELD_ENTRY( CPUMCTX, cs.u64Base),
803	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
804	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
805	SSMFIELD_ENTRY( CPUMCTX, ss.u64Base),
806	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
807	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
808	SSMFIELD_ENTRY( CPUMCTX, ds.u64Base),
809	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
810	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
811	SSMFIELD_ENTRY( CPUMCTX, fs.u64Base),
812	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
813	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
814	SSMFIELD_ENTRY( CPUMCTX, gs.u64Base),
815	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
816	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
817	SSMFIELD_ENTRY( CPUMCTX, cr0),
818	SSMFIELD_ENTRY( CPUMCTX, cr2),
819	SSMFIELD_ENTRY( CPUMCTX, cr3),
820	SSMFIELD_ENTRY( CPUMCTX, cr4),
821	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
822	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
823	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
824	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
825	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
826	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
827	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
828	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
829	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
830	SSMFIELD_ENTRY( CPUMCTX, gdtr.pGdt),
831	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
832	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
833	SSMFIELD_ENTRY( CPUMCTX, idtr.pIdt),
834	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
835	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
836	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
837	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
838	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
839	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
840	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
841	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
842	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
843	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
844	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
845	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
846	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
847	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
848	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
849	SSMFIELD_ENTRY( CPUMCTX, ldtr.u64Base),
850	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
851	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
852	SSMFIELD_ENTRY( CPUMCTX, tr.u64Base),
853	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
854	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
855	SSMFIELD_ENTRY_TERM()
856	};
857
858	/** Saved state field descriptors for CPUMCTX_VER1_6. */
859	static const SSMFIELD g_aCpumX87FieldsV16[] =
860	{
861	SSMFIELD_ENTRY( X86FXSTATE, FCW),
862	SSMFIELD_ENTRY( X86FXSTATE, FSW),
863	SSMFIELD_ENTRY( X86FXSTATE, FTW),
864	SSMFIELD_ENTRY( X86FXSTATE, FOP),
865	SSMFIELD_ENTRY( X86FXSTATE, FPUIP),
866	SSMFIELD_ENTRY( X86FXSTATE, CS),
867	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd1),
868	SSMFIELD_ENTRY( X86FXSTATE, FPUDP),
869	SSMFIELD_ENTRY( X86FXSTATE, DS),
870	SSMFIELD_ENTRY( X86FXSTATE, Rsrvd2),
871	SSMFIELD_ENTRY( X86FXSTATE, MXCSR),
872	SSMFIELD_ENTRY( X86FXSTATE, MXCSR_MASK),
873	SSMFIELD_ENTRY( X86FXSTATE, aRegs[0]),
874	SSMFIELD_ENTRY( X86FXSTATE, aRegs[1]),
875	SSMFIELD_ENTRY( X86FXSTATE, aRegs[2]),
876	SSMFIELD_ENTRY( X86FXSTATE, aRegs[3]),
877	SSMFIELD_ENTRY( X86FXSTATE, aRegs[4]),
878	SSMFIELD_ENTRY( X86FXSTATE, aRegs[5]),
879	SSMFIELD_ENTRY( X86FXSTATE, aRegs[6]),
880	SSMFIELD_ENTRY( X86FXSTATE, aRegs[7]),
881	SSMFIELD_ENTRY( X86FXSTATE, aXMM[0]),
882	SSMFIELD_ENTRY( X86FXSTATE, aXMM[1]),
883	SSMFIELD_ENTRY( X86FXSTATE, aXMM[2]),
884	SSMFIELD_ENTRY( X86FXSTATE, aXMM[3]),
885	SSMFIELD_ENTRY( X86FXSTATE, aXMM[4]),
886	SSMFIELD_ENTRY( X86FXSTATE, aXMM[5]),
887	SSMFIELD_ENTRY( X86FXSTATE, aXMM[6]),
888	SSMFIELD_ENTRY( X86FXSTATE, aXMM[7]),
889	SSMFIELD_ENTRY( X86FXSTATE, aXMM[8]),
890	SSMFIELD_ENTRY( X86FXSTATE, aXMM[9]),
891	SSMFIELD_ENTRY( X86FXSTATE, aXMM[10]),
892	SSMFIELD_ENTRY( X86FXSTATE, aXMM[11]),
893	SSMFIELD_ENTRY( X86FXSTATE, aXMM[12]),
894	SSMFIELD_ENTRY( X86FXSTATE, aXMM[13]),
895	SSMFIELD_ENTRY( X86FXSTATE, aXMM[14]),
896	SSMFIELD_ENTRY( X86FXSTATE, aXMM[15]),
897	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdRest),
898	SSMFIELD_ENTRY_IGNORE( X86FXSTATE, au32RsrvdForSoftware),
899	SSMFIELD_ENTRY_TERM()
900	};
901
902	/** Saved state field descriptors for CPUMCTX_VER1_6. */
903	static const SSMFIELD g_aCpumCtxFieldsV16[] =
904	{
905	SSMFIELD_ENTRY( CPUMCTX, rdi),
906	SSMFIELD_ENTRY( CPUMCTX, rsi),
907	SSMFIELD_ENTRY( CPUMCTX, rbp),
908	SSMFIELD_ENTRY( CPUMCTX, rax),
909	SSMFIELD_ENTRY( CPUMCTX, rbx),
910	SSMFIELD_ENTRY( CPUMCTX, rdx),
911	SSMFIELD_ENTRY( CPUMCTX, rcx),
912	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, rsp),
913	SSMFIELD_ENTRY( CPUMCTX, ss.Sel),
914	SSMFIELD_ENTRY_OLD( ssPadding, sizeof(uint16_t)),
915	SSMFIELD_ENTRY_OLD( CPUMCTX, sizeof(uint64_t) /rsp_notused/),
916	SSMFIELD_ENTRY( CPUMCTX, gs.Sel),
917	SSMFIELD_ENTRY_OLD( gsPadding, sizeof(uint16_t)),
918	SSMFIELD_ENTRY( CPUMCTX, fs.Sel),
919	SSMFIELD_ENTRY_OLD( fsPadding, sizeof(uint16_t)),
920	SSMFIELD_ENTRY( CPUMCTX, es.Sel),
921	SSMFIELD_ENTRY_OLD( esPadding, sizeof(uint16_t)),
922	SSMFIELD_ENTRY( CPUMCTX, ds.Sel),
923	SSMFIELD_ENTRY_OLD( dsPadding, sizeof(uint16_t)),
924	SSMFIELD_ENTRY( CPUMCTX, cs.Sel),
925	SSMFIELD_ENTRY_OLD( csPadding, sizeof(uint16_t)*3),
926	SSMFIELD_ENTRY( CPUMCTX, rflags),
927	SSMFIELD_ENTRY( CPUMCTX, rip),
928	SSMFIELD_ENTRY( CPUMCTX, r8),
929	SSMFIELD_ENTRY( CPUMCTX, r9),
930	SSMFIELD_ENTRY( CPUMCTX, r10),
931	SSMFIELD_ENTRY( CPUMCTX, r11),
932	SSMFIELD_ENTRY( CPUMCTX, r12),
933	SSMFIELD_ENTRY( CPUMCTX, r13),
934	SSMFIELD_ENTRY( CPUMCTX, r14),
935	SSMFIELD_ENTRY( CPUMCTX, r15),
936	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, es.u64Base),
937	SSMFIELD_ENTRY( CPUMCTX, es.u32Limit),
938	SSMFIELD_ENTRY( CPUMCTX, es.Attr),
939	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, cs.u64Base),
940	SSMFIELD_ENTRY( CPUMCTX, cs.u32Limit),
941	SSMFIELD_ENTRY( CPUMCTX, cs.Attr),
942	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ss.u64Base),
943	SSMFIELD_ENTRY( CPUMCTX, ss.u32Limit),
944	SSMFIELD_ENTRY( CPUMCTX, ss.Attr),
945	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ds.u64Base),
946	SSMFIELD_ENTRY( CPUMCTX, ds.u32Limit),
947	SSMFIELD_ENTRY( CPUMCTX, ds.Attr),
948	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, fs.u64Base),
949	SSMFIELD_ENTRY( CPUMCTX, fs.u32Limit),
950	SSMFIELD_ENTRY( CPUMCTX, fs.Attr),
951	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gs.u64Base),
952	SSMFIELD_ENTRY( CPUMCTX, gs.u32Limit),
953	SSMFIELD_ENTRY( CPUMCTX, gs.Attr),
954	SSMFIELD_ENTRY( CPUMCTX, cr0),
955	SSMFIELD_ENTRY( CPUMCTX, cr2),
956	SSMFIELD_ENTRY( CPUMCTX, cr3),
957	SSMFIELD_ENTRY( CPUMCTX, cr4),
958	SSMFIELD_ENTRY_OLD( cr8, sizeof(uint64_t)),
959	SSMFIELD_ENTRY( CPUMCTX, dr[0]),
960	SSMFIELD_ENTRY( CPUMCTX, dr[1]),
961	SSMFIELD_ENTRY( CPUMCTX, dr[2]),
962	SSMFIELD_ENTRY( CPUMCTX, dr[3]),
963	SSMFIELD_ENTRY_OLD( dr[4], sizeof(uint64_t)),
964	SSMFIELD_ENTRY_OLD( dr[5], sizeof(uint64_t)),
965	SSMFIELD_ENTRY( CPUMCTX, dr[6]),
966	SSMFIELD_ENTRY( CPUMCTX, dr[7]),
967	SSMFIELD_ENTRY( CPUMCTX, gdtr.cbGdt),
968	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, gdtr.pGdt),
969	SSMFIELD_ENTRY_OLD( gdtrPadding, sizeof(uint16_t)),
970	SSMFIELD_ENTRY_OLD( gdtrPadding64, sizeof(uint64_t)),
971	SSMFIELD_ENTRY( CPUMCTX, idtr.cbIdt),
972	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, idtr.pIdt),
973	SSMFIELD_ENTRY_OLD( idtrPadding, sizeof(uint16_t)),
974	SSMFIELD_ENTRY_OLD( idtrPadding64, sizeof(uint64_t)),
975	SSMFIELD_ENTRY( CPUMCTX, ldtr.Sel),
976	SSMFIELD_ENTRY_OLD( ldtrPadding, sizeof(uint16_t)),
977	SSMFIELD_ENTRY( CPUMCTX, tr.Sel),
978	SSMFIELD_ENTRY_OLD( trPadding, sizeof(uint16_t)),
979	SSMFIELD_ENTRY( CPUMCTX, SysEnter.cs),
980	SSMFIELD_ENTRY( CPUMCTX, SysEnter.eip),
981	SSMFIELD_ENTRY( CPUMCTX, SysEnter.esp),
982	SSMFIELD_ENTRY( CPUMCTX, msrEFER),
983	SSMFIELD_ENTRY( CPUMCTX, msrSTAR),
984	SSMFIELD_ENTRY( CPUMCTX, msrPAT),
985	SSMFIELD_ENTRY( CPUMCTX, msrLSTAR),
986	SSMFIELD_ENTRY( CPUMCTX, msrCSTAR),
987	SSMFIELD_ENTRY( CPUMCTX, msrSFMASK),
988	SSMFIELD_ENTRY_OLD( msrFSBASE, sizeof(uint64_t)),
989	SSMFIELD_ENTRY_OLD( msrGSBASE, sizeof(uint64_t)),
990	SSMFIELD_ENTRY( CPUMCTX, msrKERNELGSBASE),
991	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, ldtr.u64Base),
992	SSMFIELD_ENTRY( CPUMCTX, ldtr.u32Limit),
993	SSMFIELD_ENTRY( CPUMCTX, ldtr.Attr),
994	SSMFIELD_ENTRY_U32_ZX_U64( CPUMCTX, tr.u64Base),
995	SSMFIELD_ENTRY( CPUMCTX, tr.u32Limit),
996	SSMFIELD_ENTRY( CPUMCTX, tr.Attr),
997	SSMFIELD_ENTRY_OLD( padding, sizeof(uint32_t)*2),
998	SSMFIELD_ENTRY_TERM()
999	};
1000
1001
1002	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
1003	/**
1004	* Checks for partial/leaky FXSAVE/FXRSTOR handling on AMD CPUs.
1005	*
1006	* AMD K7, K8 and newer AMD CPUs do not save/restore the x87 error pointers
1007	* (last instruction pointer, last data pointer, last opcode) except when the ES
1008	* bit (Exception Summary) in x87 FSW (FPU Status Word) is set. Thus if we don't
1009	* clear these registers there is potential, local FPU leakage from a process
1010	* using the FPU to another.
1011	*
1012	* See AMD Instruction Reference for FXSAVE, FXRSTOR.
1013	*
1014	* @param pVM The cross context VM structure.
1015	*/
1016	static void cpumR3CheckLeakyFpu(PVM pVM)
1017	{
1018	uint32_t u32CpuVersion = ASMCpuId_EAX(1);
1019	uint32_t const u32Family = u32CpuVersion >> 8;
1020	if ( u32Family >= 6 /* K7 and higher */
1021	&& (ASMIsAmdCpu() \|\| ASMIsHygonCpu()) )
1022	{
1023	uint32_t cExt = ASMCpuId_EAX(0x80000000);
1024	if (RTX86IsValidExtRange(cExt))
1025	{
1026	uint32_t fExtFeaturesEDX = ASMCpuId_EDX(0x80000001);
1027	if (fExtFeaturesEDX & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
1028	{
1029	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1030	{
1031	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1032	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_FFXSR_LEAKY;
1033	}
1034	Log(("CPUM: Host CPU has leaky fxsave/fxrstor behaviour\n"));
1035	}
1036	}
1037	}
1038	}
1039	#endif
1040
1041
1042	/**
1043	* Initialize the SVM hardware virtualization state.
1044	*
1045	* @param pVM The cross context VM structure.
1046	*/
1047	static void cpumR3InitSvmHwVirtState(PVM pVM)
1048	{
1049	LogRel(("CPUM: AMD-V nested-guest init\n"));
1050	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1051	{
1052	PVMCPU pVCpu = pVM->apCpusR3[i];
1053	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1054
1055	/* Initialize that SVM hardware virtualization is available. */
1056	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_SVM;
1057
1058	AssertCompile(sizeof(pCtx->hwvirt.svm.Vmcb) == SVM_VMCB_PAGES * X86_PAGE_SIZE);
1059	AssertCompile(sizeof(pCtx->hwvirt.svm.abMsrBitmap) == SVM_MSRPM_PAGES * X86_PAGE_SIZE);
1060	AssertCompile(sizeof(pCtx->hwvirt.svm.abIoBitmap) == SVM_IOPM_PAGES * X86_PAGE_SIZE);
1061
1062	/* Initialize non-zero values. */
1063	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1064	}
1065	}
1066
1067
1068	/**
1069	* Resets per-VCPU SVM hardware virtualization state.
1070	*
1071	* @param pVCpu The cross context virtual CPU structure.
1072	*/
1073	DECLINLINE(void) cpumR3ResetSvmHwVirtState(PVMCPU pVCpu)
1074	{
1075	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1076	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_SVM);
1077
1078	RT_ZERO(pCtx->hwvirt.svm.Vmcb);
1079	RT_ZERO(pCtx->hwvirt.svm.HostState);
1080	RT_ZERO(pCtx->hwvirt.svm.abMsrBitmap);
1081	RT_ZERO(pCtx->hwvirt.svm.abIoBitmap);
1082
1083	pCtx->hwvirt.svm.uMsrHSavePa = 0;
1084	pCtx->hwvirt.svm.uPrevPauseTick = 0;
1085	pCtx->hwvirt.svm.GCPhysVmcb = NIL_RTGCPHYS;
1086	pCtx->hwvirt.svm.cPauseFilter = 0;
1087	pCtx->hwvirt.svm.cPauseFilterThreshold = 0;
1088	pCtx->hwvirt.svm.fInterceptEvents = false;
1089	}
1090
1091
1092	/**
1093	* Initializes the VMX hardware virtualization state.
1094	*
1095	* @param pVM The cross context VM structure.
1096	*/
1097	static void cpumR3InitVmxHwVirtState(PVM pVM)
1098	{
1099	LogRel(("CPUM: VT-x nested-guest init\n"));
1100	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1101	{
1102	PVMCPU pVCpu = pVM->apCpusR3[i];
1103	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1104
1105	/* Initialize that VMX hardware virtualization is available. */
1106	pCtx->hwvirt.enmHwvirt = CPUMHWVIRT_VMX;
1107
1108	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_PAGES * X86_PAGE_SIZE);
1109	AssertCompile(sizeof(pCtx->hwvirt.vmx.Vmcs) == VMX_V_VMCS_SIZE);
1110	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_PAGES * X86_PAGE_SIZE);
1111	AssertCompile(sizeof(pCtx->hwvirt.vmx.ShadowVmcs) == VMX_V_SHADOW_VMCS_SIZE);
1112	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1113	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmreadBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1114	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_PAGES * X86_PAGE_SIZE);
1115	AssertCompile(sizeof(pCtx->hwvirt.vmx.abVmwriteBitmap) == VMX_V_VMREAD_VMWRITE_BITMAP_SIZE);
1116	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1117	AssertCompile(sizeof(pCtx->hwvirt.vmx.aEntryMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1118	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1119	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrStoreArea) == VMX_V_AUTOMSR_AREA_SIZE);
1120	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_PAGES * X86_PAGE_SIZE);
1121	AssertCompile(sizeof(pCtx->hwvirt.vmx.aExitMsrLoadArea) == VMX_V_AUTOMSR_AREA_SIZE);
1122	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_PAGES * X86_PAGE_SIZE);
1123	AssertCompile(sizeof(pCtx->hwvirt.vmx.abMsrBitmap) == VMX_V_MSR_BITMAP_SIZE);
1124	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == (VMX_V_IO_BITMAP_A_PAGES + VMX_V_IO_BITMAP_B_PAGES) * X86_PAGE_SIZE);
1125	AssertCompile(sizeof(pCtx->hwvirt.vmx.abIoBitmap) == VMX_V_IO_BITMAP_A_SIZE + VMX_V_IO_BITMAP_B_SIZE);
1126
1127	/* Initialize non-zero values. */
1128	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1129	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1130	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1131	}
1132	}
1133
1134
1135	/**
1136	* Resets per-VCPU VMX hardware virtualization state.
1137	*
1138	* @param pVCpu The cross context virtual CPU structure.
1139	*/
1140	DECLINLINE(void) cpumR3ResetVmxHwVirtState(PVMCPU pVCpu)
1141	{
1142	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
1143	Assert(pCtx->hwvirt.enmHwvirt == CPUMHWVIRT_VMX);
1144
1145	RT_ZERO(pCtx->hwvirt.vmx.Vmcs);
1146	RT_ZERO(pCtx->hwvirt.vmx.ShadowVmcs);
1147	RT_ZERO(pCtx->hwvirt.vmx.abVmreadBitmap);
1148	RT_ZERO(pCtx->hwvirt.vmx.abVmwriteBitmap);
1149	RT_ZERO(pCtx->hwvirt.vmx.aEntryMsrLoadArea);
1150	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrStoreArea);
1151	RT_ZERO(pCtx->hwvirt.vmx.aExitMsrLoadArea);
1152	RT_ZERO(pCtx->hwvirt.vmx.abMsrBitmap);
1153	RT_ZERO(pCtx->hwvirt.vmx.abIoBitmap);
1154
1155	pCtx->hwvirt.vmx.GCPhysVmxon = NIL_RTGCPHYS;
1156	pCtx->hwvirt.vmx.GCPhysShadowVmcs = NIL_RTGCPHYS;
1157	pCtx->hwvirt.vmx.GCPhysVmcs = NIL_RTGCPHYS;
1158	pCtx->hwvirt.vmx.fInVmxRootMode = false;
1159	pCtx->hwvirt.vmx.fInVmxNonRootMode = false;
1160	/* Don't reset diagnostics here. */
1161
1162	pCtx->hwvirt.vmx.fInterceptEvents = false;
1163	pCtx->hwvirt.vmx.fNmiUnblockingIret = false;
1164	pCtx->hwvirt.vmx.uFirstPauseLoopTick = 0;
1165	pCtx->hwvirt.vmx.uPrevPauseTick = 0;
1166	pCtx->hwvirt.vmx.uEntryTick = 0;
1167	pCtx->hwvirt.vmx.offVirtApicWrite = 0;
1168	pCtx->hwvirt.vmx.fVirtNmiBlocking = false;
1169
1170	/* Stop any VMX-preemption timer. */
1171	CPUMStopGuestVmxPremptTimer(pVCpu);
1172
1173	/* Clear all nested-guest FFs. */
1174	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_VMX_ALL_MASK);
1175	}
1176
1177
1178	/**
1179	* Displays the host and guest VMX features.
1180	*
1181	* @param pVM The cross context VM structure.
1182	* @param pHlp The info helper functions.
1183	* @param pszArgs "terse", "default" or "verbose".
1184	*/
1185	DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1186	{
1187	RT_NOREF(pszArgs);
1188	PCCPUMFEATURES pHostFeatures = &pVM->cpum.s.HostFeatures;
1189	PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
1190	if ( pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
1191	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA
1192	\|\| pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_SHANGHAI)
1193	{
1194	#define VMXFEATDUMP(a_szDesc, a_Var) \
1195	pHlp->pfnPrintf(pHlp, " %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
1196
1197	pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
1198	pHlp->pfnPrintf(pHlp, " Mnemonic - Description = guest (host)\n");
1199	VMXFEATDUMP("VMX - Virtual-Machine Extensions ", fVmx);
1200	/* Basic. */
1201	VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info. ", fVmxInsOutInfo);
1202
1203	/* Pin-based controls. */
1204	VMXFEATDUMP("ExtIntExit - External interrupt exiting ", fVmxExtIntExit);
1205	VMXFEATDUMP("NmiExit - NMI exiting ", fVmxNmiExit);
1206	VMXFEATDUMP("VirtNmi - Virtual NMIs ", fVmxVirtNmi);
1207	VMXFEATDUMP("PreemptTimer - VMX preemption timer ", fVmxPreemptTimer);
1208	VMXFEATDUMP("PostedInt - Posted interrupts ", fVmxPostedInt);
1209
1210	/* Processor-based controls. */
1211	VMXFEATDUMP("IntWindowExit - Interrupt-window exiting ", fVmxIntWindowExit);
1212	VMXFEATDUMP("TscOffsetting - TSC offsetting ", fVmxTscOffsetting);
1213	VMXFEATDUMP("HltExit - HLT exiting ", fVmxHltExit);
1214	VMXFEATDUMP("InvlpgExit - INVLPG exiting ", fVmxInvlpgExit);
1215	VMXFEATDUMP("MwaitExit - MWAIT exiting ", fVmxMwaitExit);
1216	VMXFEATDUMP("RdpmcExit - RDPMC exiting ", fVmxRdpmcExit);
1217	VMXFEATDUMP("RdtscExit - RDTSC exiting ", fVmxRdtscExit);
1218	VMXFEATDUMP("Cr3LoadExit - CR3-load exiting ", fVmxCr3LoadExit);
1219	VMXFEATDUMP("Cr3StoreExit - CR3-store exiting ", fVmxCr3StoreExit);
1220	VMXFEATDUMP("TertiaryExecCtls - Activate tertiary controls ", fVmxTertiaryExecCtls);
1221	VMXFEATDUMP("Cr8LoadExit - CR8-load exiting ", fVmxCr8LoadExit);
1222	VMXFEATDUMP("Cr8StoreExit - CR8-store exiting ", fVmxCr8StoreExit);
1223	VMXFEATDUMP("UseTprShadow - Use TPR shadow ", fVmxUseTprShadow);
1224	VMXFEATDUMP("NmiWindowExit - NMI-window exiting ", fVmxNmiWindowExit);
1225	VMXFEATDUMP("MovDRxExit - Mov-DR exiting ", fVmxMovDRxExit);
1226	VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting ", fVmxUncondIoExit);
1227	VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps ", fVmxUseIoBitmaps);
1228	VMXFEATDUMP("MonitorTrapFlag - Monitor Trap Flag ", fVmxMonitorTrapFlag);
1229	VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps ", fVmxUseMsrBitmaps);
1230	VMXFEATDUMP("MonitorExit - MONITOR exiting ", fVmxMonitorExit);
1231	VMXFEATDUMP("PauseExit - PAUSE exiting ", fVmxPauseExit);
1232	VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls ", fVmxSecondaryExecCtls);
1233
1234	/* Secondary processor-based controls. */
1235	VMXFEATDUMP("VirtApic - Virtualize-APIC accesses ", fVmxVirtApicAccess);
1236	VMXFEATDUMP("Ept - Extended Page Tables ", fVmxEpt);
1237	VMXFEATDUMP("DescTableExit - Descriptor-table exiting ", fVmxDescTableExit);
1238	VMXFEATDUMP("Rdtscp - Enable RDTSCP ", fVmxRdtscp);
1239	VMXFEATDUMP("VirtX2ApicMode - Virtualize-x2APIC mode ", fVmxVirtX2ApicMode);
1240	VMXFEATDUMP("Vpid - Enable VPID ", fVmxVpid);
1241	VMXFEATDUMP("WbinvdExit - WBINVD exiting ", fVmxWbinvdExit);
1242	VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest ", fVmxUnrestrictedGuest);
1243	VMXFEATDUMP("ApicRegVirt - APIC-register virtualization ", fVmxApicRegVirt);
1244	VMXFEATDUMP("VirtIntDelivery - Virtual-interrupt delivery ", fVmxVirtIntDelivery);
1245	VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting ", fVmxPauseLoopExit);
1246	VMXFEATDUMP("RdrandExit - RDRAND exiting ", fVmxRdrandExit);
1247	VMXFEATDUMP("Invpcid - Enable INVPCID ", fVmxInvpcid);
1248	VMXFEATDUMP("VmFuncs - Enable VM Functions ", fVmxVmFunc);
1249	VMXFEATDUMP("VmcsShadowing - VMCS shadowing ", fVmxVmcsShadowing);
1250	VMXFEATDUMP("RdseedExiting - RDSEED exiting ", fVmxRdseedExit);
1251	VMXFEATDUMP("PML - Page-Modification Log (PML) ", fVmxPml);
1252	VMXFEATDUMP("EptVe - EPT violations can cause #VE ", fVmxEptXcptVe);
1253	VMXFEATDUMP("ConcealVmxFromPt - Conceal VMX from Processor Trace ", fVmxConcealVmxFromPt);
1254	VMXFEATDUMP("XsavesXRstors - Enable XSAVES/XRSTORS ", fVmxXsavesXrstors);
1255	VMXFEATDUMP("ModeBasedExecuteEpt - Mode-based execute permissions ", fVmxModeBasedExecuteEpt);
1256	VMXFEATDUMP("SppEpt - Sub-page page write permissions for EPT ", fVmxSppEpt);
1257	VMXFEATDUMP("PtEpt - Processor Trace address' translatable by EPT ", fVmxPtEpt);
1258	VMXFEATDUMP("UseTscScaling - Use TSC scaling ", fVmxUseTscScaling);
1259	VMXFEATDUMP("UserWaitPause - Enable TPAUSE, UMONITOR and UMWAIT ", fVmxUserWaitPause);
1260	VMXFEATDUMP("EnclvExit - ENCLV exiting ", fVmxEnclvExit);
1261
1262	/* Tertiary processor-based controls. */
1263	VMXFEATDUMP("LoadIwKeyExit - LOADIWKEY exiting ", fVmxLoadIwKeyExit);
1264
1265	/* VM-entry controls. */
1266	VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry ", fVmxEntryLoadDebugCtls);
1267	VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest ", fVmxIa32eModeGuest);
1268	VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER MSR on VM-entry ", fVmxEntryLoadEferMsr);
1269	VMXFEATDUMP("EntryLoadPatMsr - Load IA32_PAT MSR on VM-entry ", fVmxEntryLoadPatMsr);
1270
1271	/* VM-exit controls. */
1272	VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit ", fVmxExitSaveDebugCtls);
1273	VMXFEATDUMP("HostAddrSpaceSize - Host address-space size ", fVmxHostAddrSpaceSize);
1274	VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit ", fVmxExitAckExtInt);
1275	VMXFEATDUMP("ExitSavePatMsr - Save IA32_PAT MSR on VM-exit ", fVmxExitSavePatMsr);
1276	VMXFEATDUMP("ExitLoadPatMsr - Load IA32_PAT MSR on VM-exit ", fVmxExitLoadPatMsr);
1277	VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER MSR on VM-exit ", fVmxExitSaveEferMsr);
1278	VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER MSR on VM-exit ", fVmxExitLoadEferMsr);
1279	VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer ", fVmxSavePreemptTimer);
1280
1281	/* Miscellaneous data. */
1282	VMXFEATDUMP("ExitSaveEferLma - Save IA32_EFER.LMA on VM-exit ", fVmxExitSaveEferLma);
1283	VMXFEATDUMP("IntelPt - Intel PT (Processor Trace) in VMX operation ", fVmxPt);
1284	VMXFEATDUMP("VmwriteAll - VMWRITE to any supported VMCS field ", fVmxVmwriteAll);
1285	VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
1286	#undef VMXFEATDUMP
1287	}
1288	else
1289	pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
1290	}
1291
1292
1293	/**
1294	* Checks whether nested-guest execution using hardware-assisted VMX (e.g, using HM
1295	* or NEM) is allowed.
1296	*
1297	* @returns @c true if hardware-assisted nested-guest execution is allowed, @c false
1298	* otherwise.
1299	* @param pVM The cross context VM structure.
1300	*/
1301	static bool cpumR3IsHwAssistNstGstExecAllowed(PVM pVM)
1302	{
1303	AssertMsg(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET, ("Calling this function too early!\n"));
1304	#ifndef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
1305	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT
1306	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
1307	return true;
1308	#else
1309	NOREF(pVM);
1310	#endif
1311	return false;
1312	}
1313
1314
1315	/**
1316	* Initializes the VMX guest MSRs from guest CPU features based on the host MSRs.
1317	*
1318	* @param pVM The cross context VM structure.
1319	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1320	* and no hardware-assisted nested-guest execution is
1321	* possible for this VM.
1322	* @param pGuestFeatures The guest features to use (only VMX features are
1323	* accessed).
1324	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1325	*
1326	* @remarks This function ASSUMES the VMX guest-features are already exploded!
1327	*/
1328	static void cpumR3InitVmxGuestMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PCCPUMFEATURES pGuestFeatures, PVMXMSRS pGuestVmxMsrs)
1329	{
1330	bool const fIsNstGstHwExecAllowed = cpumR3IsHwAssistNstGstExecAllowed(pVM);
1331
1332	Assert(!fIsNstGstHwExecAllowed \|\| pHostVmxMsrs);
1333	Assert(pGuestFeatures->fVmx);
1334
1335	/* Basic information. */
1336	uint8_t const fTrueVmxMsrs = 1;
1337	{
1338	uint64_t const u64Basic = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID, VMX_V_VMCS_REVISION_ID )
1339	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_SIZE, VMX_V_VMCS_SIZE )
1340	\| RT_BF_MAKE(VMX_BF_BASIC_PHYSADDR_WIDTH, !pGuestFeatures->fLongMode )
1341	\| RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON, 0 )
1342	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB )
1343	\| RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
1344	\| RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS, fTrueVmxMsrs );
1345	pGuestVmxMsrs->u64Basic = u64Basic;
1346	}
1347
1348	/* Pin-based VM-execution controls. */
1349	{
1350	uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
1351	\| (pGuestFeatures->fVmxNmiExit << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT )
1352	\| (pGuestFeatures->fVmxVirtNmi << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT )
1353	\| (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT)
1354	\| (pGuestFeatures->fVmxPostedInt << VMX_BF_PIN_CTLS_POSTED_INT_SHIFT );
1355	uint32_t const fAllowed0 = VMX_PIN_CTLS_DEFAULT1;
1356	uint32_t const fAllowed1 = fFeatures \| VMX_PIN_CTLS_DEFAULT1;
1357	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n",
1358	fAllowed0, fAllowed1, fFeatures));
1359	pGuestVmxMsrs->PinCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1360
1361	/* True pin-based VM-execution controls. */
1362	if (fTrueVmxMsrs)
1363	{
1364	/* VMX_PIN_CTLS_DEFAULT1 contains MB1 reserved bits and must be reserved MB1 in true pin-based controls as well. */
1365	pGuestVmxMsrs->TruePinCtls.u = pGuestVmxMsrs->PinCtls.u;
1366	}
1367	}
1368
1369	/* Processor-based VM-execution controls. */
1370	{
1371	uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT )
1372	\| (pGuestFeatures->fVmxTscOffsetting << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
1373	\| (pGuestFeatures->fVmxHltExit << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT )
1374	\| (pGuestFeatures->fVmxInvlpgExit << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT )
1375	\| (pGuestFeatures->fVmxMwaitExit << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT )
1376	\| (pGuestFeatures->fVmxRdpmcExit << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT )
1377	\| (pGuestFeatures->fVmxRdtscExit << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT )
1378	\| (pGuestFeatures->fVmxCr3LoadExit << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT )
1379	\| (pGuestFeatures->fVmxCr3StoreExit << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT )
1380	\| (pGuestFeatures->fVmxTertiaryExecCtls << VMX_BF_PROC_CTLS_USE_TERTIARY_CTLS_SHIFT )
1381	\| (pGuestFeatures->fVmxCr8LoadExit << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT )
1382	\| (pGuestFeatures->fVmxCr8StoreExit << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT )
1383	\| (pGuestFeatures->fVmxUseTprShadow << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT )
1384	\| (pGuestFeatures->fVmxNmiWindowExit << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT )
1385	\| (pGuestFeatures->fVmxMovDRxExit << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT )
1386	\| (pGuestFeatures->fVmxUncondIoExit << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT )
1387	\| (pGuestFeatures->fVmxUseIoBitmaps << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT )
1388	\| (pGuestFeatures->fVmxMonitorTrapFlag << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
1389	\| (pGuestFeatures->fVmxUseMsrBitmaps << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT )
1390	\| (pGuestFeatures->fVmxMonitorExit << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT )
1391	\| (pGuestFeatures->fVmxPauseExit << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT )
1392	\| (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
1393	uint32_t const fAllowed0 = VMX_PROC_CTLS_DEFAULT1;
1394	uint32_t const fAllowed1 = fFeatures \| VMX_PROC_CTLS_DEFAULT1;
1395	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1396	fAllowed1, fFeatures));
1397	pGuestVmxMsrs->ProcCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1398
1399	/* True processor-based VM-execution controls. */
1400	if (fTrueVmxMsrs)
1401	{
1402	/* VMX_PROC_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved. */
1403	uint32_t const fTrueAllowed0 = VMX_PROC_CTLS_DEFAULT1 & ~( VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK
1404	\| VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK);
1405	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1406	pGuestVmxMsrs->TrueProcCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1407	}
1408	}
1409
1410	/* Secondary processor-based VM-execution controls. */
1411	if (pGuestFeatures->fVmxSecondaryExecCtls)
1412	{
1413	uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT )
1414	\| (pGuestFeatures->fVmxEpt << VMX_BF_PROC_CTLS2_EPT_SHIFT )
1415	\| (pGuestFeatures->fVmxDescTableExit << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT )
1416	\| (pGuestFeatures->fVmxRdtscp << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT )
1417	\| (pGuestFeatures->fVmxVirtX2ApicMode << VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT )
1418	\| (pGuestFeatures->fVmxVpid << VMX_BF_PROC_CTLS2_VPID_SHIFT )
1419	\| (pGuestFeatures->fVmxWbinvdExit << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT )
1420	\| (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT )
1421	\| (pGuestFeatures->fVmxApicRegVirt << VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT )
1422	\| (pGuestFeatures->fVmxVirtIntDelivery << VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT )
1423	\| (pGuestFeatures->fVmxPauseLoopExit << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT )
1424	\| (pGuestFeatures->fVmxRdrandExit << VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT )
1425	\| (pGuestFeatures->fVmxInvpcid << VMX_BF_PROC_CTLS2_INVPCID_SHIFT )
1426	\| (pGuestFeatures->fVmxVmFunc << VMX_BF_PROC_CTLS2_VMFUNC_SHIFT )
1427	\| (pGuestFeatures->fVmxVmcsShadowing << VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT )
1428	\| (pGuestFeatures->fVmxRdseedExit << VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT )
1429	\| (pGuestFeatures->fVmxPml << VMX_BF_PROC_CTLS2_PML_SHIFT )
1430	\| (pGuestFeatures->fVmxEptXcptVe << VMX_BF_PROC_CTLS2_EPT_VE_SHIFT )
1431	\| (pGuestFeatures->fVmxConcealVmxFromPt << VMX_BF_PROC_CTLS2_CONCEAL_VMX_FROM_PT_SHIFT)
1432	\| (pGuestFeatures->fVmxXsavesXrstors << VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT )
1433	\| (pGuestFeatures->fVmxModeBasedExecuteEpt << VMX_BF_PROC_CTLS2_MODE_BASED_EPT_PERM_SHIFT)
1434	\| (pGuestFeatures->fVmxSppEpt << VMX_BF_PROC_CTLS2_SPP_EPT_SHIFT )
1435	\| (pGuestFeatures->fVmxPtEpt << VMX_BF_PROC_CTLS2_PT_EPT_SHIFT )
1436	\| (pGuestFeatures->fVmxUseTscScaling << VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT )
1437	\| (pGuestFeatures->fVmxUserWaitPause << VMX_BF_PROC_CTLS2_USER_WAIT_PAUSE_SHIFT )
1438	\| (pGuestFeatures->fVmxEnclvExit << VMX_BF_PROC_CTLS2_ENCLV_EXIT_SHIFT );
1439	uint32_t const fAllowed0 = 0;
1440	uint32_t const fAllowed1 = fFeatures;
1441	pGuestVmxMsrs->ProcCtls2.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1442	}
1443
1444	/* Tertiary processor-based VM-execution controls. */
1445	if (pGuestFeatures->fVmxTertiaryExecCtls)
1446	{
1447	pGuestVmxMsrs->u64ProcCtls3 = (pGuestFeatures->fVmxLoadIwKeyExit << VMX_BF_PROC_CTLS3_LOADIWKEY_EXIT_SHIFT);
1448	}
1449
1450	/* VM-exit controls. */
1451	{
1452	uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT )
1453	\| (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
1454	\| (pGuestFeatures->fVmxExitAckExtInt << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT )
1455	\| (pGuestFeatures->fVmxExitSavePatMsr << VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT )
1456	\| (pGuestFeatures->fVmxExitLoadPatMsr << VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT )
1457	\| (pGuestFeatures->fVmxExitSaveEferMsr << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT )
1458	\| (pGuestFeatures->fVmxExitLoadEferMsr << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT )
1459	\| (pGuestFeatures->fVmxSavePreemptTimer << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT )
1460	\| (pGuestFeatures->fVmxExitCtls2 << VMX_BF_EXIT_CTLS_USE_SECONDARY_CTLS_SHIFT );
1461	/* Set the default1 class bits. See Intel spec. A.4 "VM-exit Controls". */
1462	uint32_t const fAllowed0 = VMX_EXIT_CTLS_DEFAULT1;
1463	uint32_t const fAllowed1 = fFeatures \| VMX_EXIT_CTLS_DEFAULT1;
1464	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed1=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1465	fAllowed1, fFeatures));
1466	pGuestVmxMsrs->ExitCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1467
1468	/* True VM-exit controls. */
1469	if (fTrueVmxMsrs)
1470	{
1471	/* VMX_EXIT_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1472	uint32_t const fTrueAllowed0 = VMX_EXIT_CTLS_DEFAULT1 & ~VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK;
1473	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1474	pGuestVmxMsrs->TrueExitCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1475	}
1476	}
1477
1478	/* VM-entry controls. */
1479	{
1480	uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT )
1481	\| (pGuestFeatures->fVmxIa32eModeGuest << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
1482	\| (pGuestFeatures->fVmxEntryLoadEferMsr << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT )
1483	\| (pGuestFeatures->fVmxEntryLoadPatMsr << VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT );
1484	uint32_t const fAllowed0 = VMX_ENTRY_CTLS_DEFAULT1;
1485	uint32_t const fAllowed1 = fFeatures \| VMX_ENTRY_CTLS_DEFAULT1;
1486	AssertMsg((fAllowed0 & fAllowed1) == fAllowed0, ("fAllowed0=%#RX32 fAllowed0=%#RX32 fFeatures=%#RX32\n", fAllowed0,
1487	fAllowed1, fFeatures));
1488	pGuestVmxMsrs->EntryCtls.u = RT_MAKE_U64(fAllowed0, fAllowed1);
1489
1490	/* True VM-entry controls. */
1491	if (fTrueVmxMsrs)
1492	{
1493	/* VMX_ENTRY_CTLS_DEFAULT1 contains MB1 reserved bits but the following are not really reserved */
1494	uint32_t const fTrueAllowed0 = VMX_ENTRY_CTLS_DEFAULT1 & ~( VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK
1495	\| VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK
1496	\| VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK
1497	\| VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK);
1498	uint32_t const fTrueAllowed1 = fFeatures \| fTrueAllowed0;
1499	pGuestVmxMsrs->TrueEntryCtls.u = RT_MAKE_U64(fTrueAllowed0, fTrueAllowed1);
1500	}
1501	}
1502
1503	/* Miscellaneous data. */
1504	{
1505	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Misc : 0;
1506
1507	uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_AUTOMSR_COUNT_MAX);
1508	uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK;
1509	pGuestVmxMsrs->u64Misc = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT )
1510	\| RT_BF_MAKE(VMX_BF_MISC_EXIT_SAVE_EFER_LMA, pGuestFeatures->fVmxExitSaveEferLma )
1511	\| RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState )
1512	\| RT_BF_MAKE(VMX_BF_MISC_INTEL_PT, pGuestFeatures->fVmxPt )
1513	\| RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 )
1514	\| RT_BF_MAKE(VMX_BF_MISC_CR3_TARGET, VMX_V_CR3_TARGET_COUNT )
1515	\| RT_BF_MAKE(VMX_BF_MISC_MAX_MSRS, cMaxMsrs )
1516	\| RT_BF_MAKE(VMX_BF_MISC_VMXOFF_BLOCK_SMI, 0 )
1517	\| RT_BF_MAKE(VMX_BF_MISC_VMWRITE_ALL, pGuestFeatures->fVmxVmwriteAll )
1518	\| RT_BF_MAKE(VMX_BF_MISC_ENTRY_INJECT_SOFT_INT, pGuestFeatures->fVmxEntryInjectSoftInt)
1519	\| RT_BF_MAKE(VMX_BF_MISC_MSEG_ID, VMX_V_MSEG_REV_ID );
1520	}
1521
1522	/* CR0 Fixed-0 (we report this fixed value regardless of whether UX is supported as it does on real hardware). */
1523	pGuestVmxMsrs->u64Cr0Fixed0 = VMX_V_CR0_FIXED0;
1524
1525	/* CR0 Fixed-1. */
1526	{
1527	/*
1528	* All CPUs I've looked at so far report CR0 fixed-1 bits as 0xffffffff.
1529	* This is different from CR4 fixed-1 bits which are reported as per the
1530	* CPU features and/or micro-architecture/generation. Why? Ask Intel.
1531	*/
1532	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1;
1533	pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */
1534	}
1535
1536	/* CR4 Fixed-0. */
1537	pGuestVmxMsrs->u64Cr4Fixed0 = VMX_V_CR4_FIXED0;
1538
1539	/* CR4 Fixed-1. */
1540	{
1541	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM);
1542	pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr \| pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */
1543	}
1544
1545	/* VMCS Enumeration. */
1546	pGuestVmxMsrs->u64VmcsEnum = VMX_V_VMCS_MAX_INDEX << VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT;
1547
1548	/* VPID and EPT Capabilities. */
1549	if (pGuestFeatures->fVmxEpt)
1550	{
1551	/*
1552	* INVVPID instruction always causes a VM-exit unconditionally, so we are free to fake
1553	* and emulate any INVVPID flush type. However, it only makes sense to expose the types
1554	* when INVVPID instruction is supported just to be more compatible with guest
1555	* hypervisors that may make assumptions by only looking at this MSR even though they
1556	* are technically supposed to refer to VMX_PROC_CTLS2_VPID first.
1557	*
1558	* See Intel spec. 25.1.2 "Instructions That Cause VM Exits Unconditionally".
1559	* See Intel spec. 30.3 "VMX Instructions".
1560	*/
1561	uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64EptVpidCaps : UINT64_MAX;
1562	uint8_t const fVpid = pGuestFeatures->fVmxVpid;
1563
1564	uint8_t const fExecOnly = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_EXEC_ONLY);
1565	uint8_t const fPml4 = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1566	uint8_t const fMemTypeUc = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_UC);
1567	uint8_t const fMemTypeWb = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_MEMTYPE_WB);
1568	uint8_t const f2MPage = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_PDE_2M);
1569	uint8_t const fInvept = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT);
1570	/** @todo Nested VMX: Support accessed/dirty bits, see @bugref{10092#c25}. */
1571	/* uint8_t const fAccessDirty = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY); */
1572	uint8_t const fEptSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX);
1573	uint8_t const fEptAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX);
1574	uint8_t const fVpidIndiv = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1575	uint8_t const fVpidSingle = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX);
1576	uint8_t const fVpidAll = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX);
1577	uint8_t const fVpidSingleGlobal = RT_BF_GET(uHostMsr, VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS);
1578	pGuestVmxMsrs->u64EptVpidCaps = RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_EXEC_ONLY, fExecOnly)
1579	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PAGE_WALK_LENGTH_4, fPml4)
1580	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_UC, fMemTypeUc)
1581	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_MEMTYPE_WB, fMemTypeWb)
1582	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDE_2M, f2MPage)
1583	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_PDPTE_1G, 0)
1584	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT, fInvept)
1585	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ACCESS_DIRTY, 0)
1586	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION, 0)
1587	//\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_SUPER_SHW_STACK, 0)
1588	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_SINGLE_CTX, fEptSingle)
1589	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVEPT_ALL_CTX, fEptAll)
1590	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID, fVpid)
1591	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_INDIV_ADDR, fVpid & fVpidIndiv)
1592	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX, fVpid & fVpidSingle)
1593	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_ALL_CTX, fVpid & fVpidAll)
1594	\| RT_BF_MAKE(VMX_BF_EPT_VPID_CAP_INVVPID_SINGLE_CTX_RETAIN_GLOBALS, fVpid & fVpidSingleGlobal);
1595	}
1596
1597	/* VM Functions. */
1598	if (pGuestFeatures->fVmxVmFunc)
1599	pGuestVmxMsrs->u64VmFunc = RT_BF_MAKE(VMX_BF_VMFUNC_EPTP_SWITCHING, 1);
1600	}
1601
1602
1603	/**
1604	* Checks whether the given guest CPU VMX features are compatible with the provided
1605	* base features.
1606	*
1607	* @returns @c true if compatible, @c false otherwise.
1608	* @param pVM The cross context VM structure.
1609	* @param pBase The base VMX CPU features.
1610	* @param pGst The guest VMX CPU features.
1611	*
1612	* @remarks Only VMX feature bits are examined.
1613	*/
1614	static bool cpumR3AreVmxCpuFeaturesCompatible(PVM pVM, PCCPUMFEATURES pBase, PCCPUMFEATURES pGst)
1615	{
1616	if (!cpumR3IsHwAssistNstGstExecAllowed(pVM))
1617	return false;
1618
1619	#define CPUM_VMX_FEAT_SHIFT(a_pFeat, a_FeatName, a_cShift) ((uint64_t)(a_pFeat->a_FeatName) << (a_cShift))
1620	#define CPUM_VMX_MAKE_FEATURES_1(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInsOutInfo , 0) \
1621	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExtIntExit , 1) \
1622	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiExit , 2) \
1623	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtNmi , 3) \
1624	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPreemptTimer , 4) \
1625	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPostedInt , 5) \
1626	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIntWindowExit , 6) \
1627	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTscOffsetting , 7) \
1628	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHltExit , 8) \
1629	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvlpgExit , 9) \
1630	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMwaitExit , 10) \
1631	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdpmcExit , 12) \
1632	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscExit , 13) \
1633	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3LoadExit , 14) \
1634	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr3StoreExit , 15) \
1635	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxTertiaryExecCtls , 16) \
1636	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8LoadExit , 17) \
1637	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxCr8StoreExit , 18) \
1638	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTprShadow , 19) \
1639	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxNmiWindowExit , 20) \
1640	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMovDRxExit , 21) \
1641	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUncondIoExit , 22) \
1642	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseIoBitmaps , 23) \
1643	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorTrapFlag , 24) \
1644	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseMsrBitmaps , 25) \
1645	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxMonitorExit , 26) \
1646	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseExit , 27) \
1647	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSecondaryExecCtls , 28) \
1648	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtApicAccess , 29) \
1649	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEpt , 30) \
1650	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxDescTableExit , 31) \
1651	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdtscp , 32) \
1652	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtX2ApicMode , 33) \
1653	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVpid , 34) \
1654	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxWbinvdExit , 35) \
1655	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUnrestrictedGuest , 36) \
1656	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxApicRegVirt , 37) \
1657	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVirtIntDelivery , 38) \
1658	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPauseLoopExit , 39) \
1659	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdrandExit , 40) \
1660	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxInvpcid , 41) \
1661	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmFunc , 42) \
1662	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmcsShadowing , 43) \
1663	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxRdseedExit , 44) \
1664	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPml , 45) \
1665	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEptXcptVe , 46) \
1666	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxConcealVmxFromPt , 47) \
1667	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxXsavesXrstors , 48) \
1668	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxModeBasedExecuteEpt, 49) \
1669	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSppEpt , 50) \
1670	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPtEpt , 51) \
1671	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUseTscScaling , 52) \
1672	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxUserWaitPause , 53) \
1673	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEnclvExit , 54) \
1674	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxLoadIwKeyExit , 55) \
1675	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadDebugCtls , 56) \
1676	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxIa32eModeGuest , 57) \
1677	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadEferMsr , 58) \
1678	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryLoadPatMsr , 59) \
1679	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveDebugCtls , 60) \
1680	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxHostAddrSpaceSize , 61) \
1681	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitAckExtInt , 62) \
1682	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSavePatMsr , 63))
1683
1684	#define CPUM_VMX_MAKE_FEATURES_2(a_pFeat) ( CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadPatMsr , 0) \
1685	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferMsr , 1) \
1686	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitLoadEferMsr , 2) \
1687	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxSavePreemptTimer , 3) \
1688	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxExitSaveEferLma , 4) \
1689	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxPt , 5) \
1690	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxVmwriteAll , 6) \
1691	\| CPUM_VMX_FEAT_SHIFT(a_pFeat, fVmxEntryInjectSoftInt , 7))
1692
1693	/* Check first set of feature bits. */
1694	{
1695	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_1(pBase);
1696	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_1(pGst);
1697	if ((fBase \| fGst) != fBase)
1698	{
1699	uint64_t const fDiff = fBase ^ fGst;
1700	LogRel(("CPUM: VMX features (1) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1701	fBase, fGst, fDiff));
1702	return false;
1703	}
1704	}
1705
1706	/* Check second set of feature bits. */
1707	{
1708	uint64_t const fBase = CPUM_VMX_MAKE_FEATURES_2(pBase);
1709	uint64_t const fGst = CPUM_VMX_MAKE_FEATURES_2(pGst);
1710	if ((fBase \| fGst) != fBase)
1711	{
1712	uint64_t const fDiff = fBase ^ fGst;
1713	LogRel(("CPUM: VMX features (2) now exposed to the guest are incompatible with those from the saved state. fBase=%#RX64 fGst=%#RX64 fDiff=%#RX64\n",
1714	fBase, fGst, fDiff));
1715	return false;
1716	}
1717	}
1718	#undef CPUM_VMX_FEAT_SHIFT
1719	#undef CPUM_VMX_MAKE_FEATURES_1
1720	#undef CPUM_VMX_MAKE_FEATURES_2
1721
1722	return true;
1723	}
1724
1725
1726	/**
1727	* Initializes VMX guest features and MSRs.
1728	*
1729	* @param pVM The cross context VM structure.
1730	* @param pCpumCfg The CPUM CFGM configuration node.
1731	* @param pHostVmxMsrs The host VMX MSRs. Pass NULL when fully emulating VMX
1732	* and no hardware-assisted nested-guest execution is
1733	* possible for this VM.
1734	* @param pGuestVmxMsrs Where to store the initialized guest VMX MSRs.
1735	*/
1736	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs)
1737	{
1738	Assert(pVM);
1739	Assert(pCpumCfg);
1740	Assert(pGuestVmxMsrs);
1741
1742	/*
1743	* Query VMX features from CFGM.
1744	*/
1745	bool fVmxPreemptTimer;
1746	bool fVmxEpt;
1747	bool fVmxUnrestrictedGuest;
1748	{
1749	/** @cfgm{/CPUM/NestedVmxPreemptTimer, bool, true}
1750	* Whether to expose the VMX-preemption timer feature to the guest (if also
1751	* supported by the host hardware). When disabled will prevent exposing the
1752	* VMX-preemption timer feature to the guest even if the host supports it.
1753	*
1754	* @todo Currently disabled, see @bugref{9180#c108}.
1755	*/
1756	int rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxPreemptTimer", &fVmxPreemptTimer, false);
1757	AssertLogRelRCReturnVoid(rc);
1758
1759	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT
1760	/** @cfgm{/CPUM/NestedVmxEpt, bool, true}
1761	* Whether to expose the EPT feature to the guest. The default is true.
1762	* When disabled will automatically prevent exposing features that rely
1763	* on it. This is dependent upon nested paging being enabled for the VM.
1764	*/
1765	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxEpt", &fVmxEpt, true);
1766	AssertLogRelRCReturnVoid(rc);
1767
1768	/** @cfgm{/CPUM/NestedVmxUnrestrictedGuest, bool, true}
1769	* Whether to expose the Unrestricted Guest feature to the guest. The
1770	* default is the same a /CPUM/Nested/VmxEpt. When disabled will
1771	* automatically prevent exposing features that rely on it.
1772	*/
1773	rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedVmxUnrestrictedGuest", &fVmxUnrestrictedGuest, fVmxEpt);
1774	AssertLogRelRCReturnVoid(rc);
1775	#else
1776	fVmxEpt = fVmxUnrestrictedGuest = false;
1777	#endif
1778	}
1779
1780	if (fVmxEpt)
1781	{
1782	const char *pszWhy = NULL;
1783	if (!VM_IS_HM_ENABLED(pVM) && !VM_IS_EXEC_ENGINE_IEM(pVM))
1784	pszWhy = "execution engine is neither HM nor IEM";
1785	else if (VM_IS_HM_ENABLED(pVM) && !HMIsNestedPagingActive(pVM))
1786	pszWhy = "nested paging is not enabled for the VM or it is not supported by the host";
1787	else if (VM_IS_HM_ENABLED(pVM) && !pVM->cpum.s.HostFeatures.fNoExecute)
1788	pszWhy = "NX is not available on the host";
1789	if (pszWhy)
1790	{
1791	LogRel(("CPUM: Warning! EPT not exposed to the guest because %s\n", pszWhy));
1792	fVmxEpt = false;
1793	}
1794	}
1795	else if (fVmxUnrestrictedGuest)
1796	{
1797	LogRel(("CPUM: Warning! Can't expose \"Unrestricted Guest\" to the guest when EPT is not exposed!\n"));
1798	fVmxUnrestrictedGuest = false;
1799	}
1800
1801	/*
1802	* Initialize the set of VMX features we emulate.
1803	*
1804	* Note! Some bits might be reported as 1 always if they fall under the
1805	* default1 class bits (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
1806	*/
1807	CPUMFEATURES EmuFeat;
1808	RT_ZERO(EmuFeat);
1809	EmuFeat.fVmx = 1;
1810	EmuFeat.fVmxInsOutInfo = 1;
1811	EmuFeat.fVmxExtIntExit = 1;
1812	EmuFeat.fVmxNmiExit = 1;
1813	EmuFeat.fVmxVirtNmi = 1;
1814	EmuFeat.fVmxPreemptTimer = fVmxPreemptTimer;
1815	EmuFeat.fVmxPostedInt = 0;
1816	EmuFeat.fVmxIntWindowExit = 1;
1817	EmuFeat.fVmxTscOffsetting = 1;
1818	EmuFeat.fVmxHltExit = 1;
1819	EmuFeat.fVmxInvlpgExit = 1;
1820	EmuFeat.fVmxMwaitExit = 1;
1821	EmuFeat.fVmxRdpmcExit = 1;
1822	EmuFeat.fVmxRdtscExit = 1;
1823	EmuFeat.fVmxCr3LoadExit = 1;
1824	EmuFeat.fVmxCr3StoreExit = 1;
1825	EmuFeat.fVmxTertiaryExecCtls = 0;
1826	EmuFeat.fVmxCr8LoadExit = 1;
1827	EmuFeat.fVmxCr8StoreExit = 1;
1828	EmuFeat.fVmxUseTprShadow = 1;
1829	EmuFeat.fVmxNmiWindowExit = 0;
1830	EmuFeat.fVmxMovDRxExit = 1;
1831	EmuFeat.fVmxUncondIoExit = 1;
1832	EmuFeat.fVmxUseIoBitmaps = 1;
1833	EmuFeat.fVmxMonitorTrapFlag = 0;
1834	EmuFeat.fVmxUseMsrBitmaps = 1;
1835	EmuFeat.fVmxMonitorExit = 1;
1836	EmuFeat.fVmxPauseExit = 1;
1837	EmuFeat.fVmxSecondaryExecCtls = 1;
1838	EmuFeat.fVmxVirtApicAccess = 1;
1839	EmuFeat.fVmxEpt = fVmxEpt;
1840	EmuFeat.fVmxDescTableExit = 1;
1841	EmuFeat.fVmxRdtscp = 1;
1842	EmuFeat.fVmxVirtX2ApicMode = 0;
1843	EmuFeat.fVmxVpid = 0; /** @todo Consider enabling this when EPT works. */
1844	EmuFeat.fVmxWbinvdExit = 1;
1845	EmuFeat.fVmxUnrestrictedGuest = fVmxUnrestrictedGuest;
1846	EmuFeat.fVmxApicRegVirt = 0;
1847	EmuFeat.fVmxVirtIntDelivery = 0;
1848	EmuFeat.fVmxPauseLoopExit = 0;
1849	EmuFeat.fVmxRdrandExit = 0;
1850	EmuFeat.fVmxInvpcid = 1;
1851	EmuFeat.fVmxVmFunc = 0;
1852	EmuFeat.fVmxVmcsShadowing = 0;
1853	EmuFeat.fVmxRdseedExit = 0;
1854	EmuFeat.fVmxPml = 0;
1855	EmuFeat.fVmxEptXcptVe = 0;
1856	EmuFeat.fVmxConcealVmxFromPt = 0;
1857	EmuFeat.fVmxXsavesXrstors = 0;
1858	EmuFeat.fVmxModeBasedExecuteEpt = 0;
1859	EmuFeat.fVmxSppEpt = 0;
1860	EmuFeat.fVmxPtEpt = 0;
1861	EmuFeat.fVmxUseTscScaling = 0;
1862	EmuFeat.fVmxUserWaitPause = 0;
1863	EmuFeat.fVmxEnclvExit = 0;
1864	EmuFeat.fVmxLoadIwKeyExit = 0;
1865	EmuFeat.fVmxEntryLoadDebugCtls = 1;
1866	EmuFeat.fVmxIa32eModeGuest = 1;
1867	EmuFeat.fVmxEntryLoadEferMsr = 1;
1868	EmuFeat.fVmxEntryLoadPatMsr = 0;
1869	EmuFeat.fVmxExitSaveDebugCtls = 1;
1870	EmuFeat.fVmxHostAddrSpaceSize = 1;
1871	EmuFeat.fVmxExitAckExtInt = 1;
1872	EmuFeat.fVmxExitSavePatMsr = 0;
1873	EmuFeat.fVmxExitLoadPatMsr = 0;
1874	EmuFeat.fVmxExitSaveEferMsr = 1;
1875	EmuFeat.fVmxExitLoadEferMsr = 1;
1876	EmuFeat.fVmxSavePreemptTimer = 0; /* Cannot be enabled if VMX-preemption timer is disabled. */
1877	EmuFeat.fVmxExitCtls2 = 0;
1878	EmuFeat.fVmxExitSaveEferLma = 1; /* Cannot be disabled if unrestricted guest is enabled. */
1879	EmuFeat.fVmxPt = 0;
1880	EmuFeat.fVmxVmwriteAll = 0; /** @todo NSTVMX: enable this when nested VMCS shadowing is enabled. */
1881	EmuFeat.fVmxEntryInjectSoftInt = 1;
1882
1883	/*
1884	* Merge guest features.
1885	*
1886	* When hardware-assisted VMX may be used, any feature we emulate must also be supported
1887	* by the hardware, hence we merge our emulated features with the host features below.
1888	*/
1889	PCCPUMFEATURES pBaseFeat = cpumR3IsHwAssistNstGstExecAllowed(pVM) ? &pVM->cpum.s.HostFeatures : &EmuFeat;
1890	PCPUMFEATURES pGuestFeat = &pVM->cpum.s.GuestFeatures;
1891	Assert(pBaseFeat->fVmx);
1892	pGuestFeat->fVmxInsOutInfo = (pBaseFeat->fVmxInsOutInfo & EmuFeat.fVmxInsOutInfo );
1893	pGuestFeat->fVmxExtIntExit = (pBaseFeat->fVmxExtIntExit & EmuFeat.fVmxExtIntExit );
1894	pGuestFeat->fVmxNmiExit = (pBaseFeat->fVmxNmiExit & EmuFeat.fVmxNmiExit );
1895	pGuestFeat->fVmxVirtNmi = (pBaseFeat->fVmxVirtNmi & EmuFeat.fVmxVirtNmi );
1896	pGuestFeat->fVmxPreemptTimer = (pBaseFeat->fVmxPreemptTimer & EmuFeat.fVmxPreemptTimer );
1897	pGuestFeat->fVmxPostedInt = (pBaseFeat->fVmxPostedInt & EmuFeat.fVmxPostedInt );
1898	pGuestFeat->fVmxIntWindowExit = (pBaseFeat->fVmxIntWindowExit & EmuFeat.fVmxIntWindowExit );
1899	pGuestFeat->fVmxTscOffsetting = (pBaseFeat->fVmxTscOffsetting & EmuFeat.fVmxTscOffsetting );
1900	pGuestFeat->fVmxHltExit = (pBaseFeat->fVmxHltExit & EmuFeat.fVmxHltExit );
1901	pGuestFeat->fVmxInvlpgExit = (pBaseFeat->fVmxInvlpgExit & EmuFeat.fVmxInvlpgExit );
1902	pGuestFeat->fVmxMwaitExit = (pBaseFeat->fVmxMwaitExit & EmuFeat.fVmxMwaitExit );
1903	pGuestFeat->fVmxRdpmcExit = (pBaseFeat->fVmxRdpmcExit & EmuFeat.fVmxRdpmcExit );
1904	pGuestFeat->fVmxRdtscExit = (pBaseFeat->fVmxRdtscExit & EmuFeat.fVmxRdtscExit );
1905	pGuestFeat->fVmxCr3LoadExit = (pBaseFeat->fVmxCr3LoadExit & EmuFeat.fVmxCr3LoadExit );
1906	pGuestFeat->fVmxCr3StoreExit = (pBaseFeat->fVmxCr3StoreExit & EmuFeat.fVmxCr3StoreExit );
1907	pGuestFeat->fVmxTertiaryExecCtls = (pBaseFeat->fVmxTertiaryExecCtls & EmuFeat.fVmxTertiaryExecCtls );
1908	pGuestFeat->fVmxCr8LoadExit = (pBaseFeat->fVmxCr8LoadExit & EmuFeat.fVmxCr8LoadExit );
1909	pGuestFeat->fVmxCr8StoreExit = (pBaseFeat->fVmxCr8StoreExit & EmuFeat.fVmxCr8StoreExit );
1910	pGuestFeat->fVmxUseTprShadow = (pBaseFeat->fVmxUseTprShadow & EmuFeat.fVmxUseTprShadow );
1911	pGuestFeat->fVmxNmiWindowExit = (pBaseFeat->fVmxNmiWindowExit & EmuFeat.fVmxNmiWindowExit );
1912	pGuestFeat->fVmxMovDRxExit = (pBaseFeat->fVmxMovDRxExit & EmuFeat.fVmxMovDRxExit );
1913	pGuestFeat->fVmxUncondIoExit = (pBaseFeat->fVmxUncondIoExit & EmuFeat.fVmxUncondIoExit );
1914	pGuestFeat->fVmxUseIoBitmaps = (pBaseFeat->fVmxUseIoBitmaps & EmuFeat.fVmxUseIoBitmaps );
1915	pGuestFeat->fVmxMonitorTrapFlag = (pBaseFeat->fVmxMonitorTrapFlag & EmuFeat.fVmxMonitorTrapFlag );
1916	pGuestFeat->fVmxUseMsrBitmaps = (pBaseFeat->fVmxUseMsrBitmaps & EmuFeat.fVmxUseMsrBitmaps );
1917	pGuestFeat->fVmxMonitorExit = (pBaseFeat->fVmxMonitorExit & EmuFeat.fVmxMonitorExit );
1918	pGuestFeat->fVmxPauseExit = (pBaseFeat->fVmxPauseExit & EmuFeat.fVmxPauseExit );
1919	pGuestFeat->fVmxSecondaryExecCtls = (pBaseFeat->fVmxSecondaryExecCtls & EmuFeat.fVmxSecondaryExecCtls );
1920	pGuestFeat->fVmxVirtApicAccess = (pBaseFeat->fVmxVirtApicAccess & EmuFeat.fVmxVirtApicAccess );
1921	pGuestFeat->fVmxEpt = (pBaseFeat->fVmxEpt & EmuFeat.fVmxEpt );
1922	pGuestFeat->fVmxDescTableExit = (pBaseFeat->fVmxDescTableExit & EmuFeat.fVmxDescTableExit );
1923	pGuestFeat->fVmxRdtscp = (pBaseFeat->fVmxRdtscp & EmuFeat.fVmxRdtscp );
1924	pGuestFeat->fVmxVirtX2ApicMode = (pBaseFeat->fVmxVirtX2ApicMode & EmuFeat.fVmxVirtX2ApicMode );
1925	pGuestFeat->fVmxVpid = (pBaseFeat->fVmxVpid & EmuFeat.fVmxVpid );
1926	pGuestFeat->fVmxWbinvdExit = (pBaseFeat->fVmxWbinvdExit & EmuFeat.fVmxWbinvdExit );
1927	pGuestFeat->fVmxUnrestrictedGuest = (pBaseFeat->fVmxUnrestrictedGuest & EmuFeat.fVmxUnrestrictedGuest );
1928	pGuestFeat->fVmxApicRegVirt = (pBaseFeat->fVmxApicRegVirt & EmuFeat.fVmxApicRegVirt );
1929	pGuestFeat->fVmxVirtIntDelivery = (pBaseFeat->fVmxVirtIntDelivery & EmuFeat.fVmxVirtIntDelivery );
1930	pGuestFeat->fVmxPauseLoopExit = (pBaseFeat->fVmxPauseLoopExit & EmuFeat.fVmxPauseLoopExit );
1931	pGuestFeat->fVmxRdrandExit = (pBaseFeat->fVmxRdrandExit & EmuFeat.fVmxRdrandExit );
1932	pGuestFeat->fVmxInvpcid = (pBaseFeat->fVmxInvpcid & EmuFeat.fVmxInvpcid );
1933	pGuestFeat->fVmxVmFunc = (pBaseFeat->fVmxVmFunc & EmuFeat.fVmxVmFunc );
1934	pGuestFeat->fVmxVmcsShadowing = (pBaseFeat->fVmxVmcsShadowing & EmuFeat.fVmxVmcsShadowing );
1935	pGuestFeat->fVmxRdseedExit = (pBaseFeat->fVmxRdseedExit & EmuFeat.fVmxRdseedExit );
1936	pGuestFeat->fVmxPml = (pBaseFeat->fVmxPml & EmuFeat.fVmxPml );
1937	pGuestFeat->fVmxEptXcptVe = (pBaseFeat->fVmxEptXcptVe & EmuFeat.fVmxEptXcptVe );
1938	pGuestFeat->fVmxConcealVmxFromPt = (pBaseFeat->fVmxConcealVmxFromPt & EmuFeat.fVmxConcealVmxFromPt );
1939	pGuestFeat->fVmxXsavesXrstors = (pBaseFeat->fVmxXsavesXrstors & EmuFeat.fVmxXsavesXrstors );
1940	pGuestFeat->fVmxModeBasedExecuteEpt = (pBaseFeat->fVmxModeBasedExecuteEpt & EmuFeat.fVmxModeBasedExecuteEpt );
1941	pGuestFeat->fVmxSppEpt = (pBaseFeat->fVmxSppEpt & EmuFeat.fVmxSppEpt );
1942	pGuestFeat->fVmxPtEpt = (pBaseFeat->fVmxPtEpt & EmuFeat.fVmxPtEpt );
1943	pGuestFeat->fVmxUseTscScaling = (pBaseFeat->fVmxUseTscScaling & EmuFeat.fVmxUseTscScaling );
1944	pGuestFeat->fVmxUserWaitPause = (pBaseFeat->fVmxUserWaitPause & EmuFeat.fVmxUserWaitPause );
1945	pGuestFeat->fVmxEnclvExit = (pBaseFeat->fVmxEnclvExit & EmuFeat.fVmxEnclvExit );
1946	pGuestFeat->fVmxLoadIwKeyExit = (pBaseFeat->fVmxLoadIwKeyExit & EmuFeat.fVmxLoadIwKeyExit );
1947	pGuestFeat->fVmxEntryLoadDebugCtls = (pBaseFeat->fVmxEntryLoadDebugCtls & EmuFeat.fVmxEntryLoadDebugCtls );
1948	pGuestFeat->fVmxIa32eModeGuest = (pBaseFeat->fVmxIa32eModeGuest & EmuFeat.fVmxIa32eModeGuest );
1949	pGuestFeat->fVmxEntryLoadEferMsr = (pBaseFeat->fVmxEntryLoadEferMsr & EmuFeat.fVmxEntryLoadEferMsr );
1950	pGuestFeat->fVmxEntryLoadPatMsr = (pBaseFeat->fVmxEntryLoadPatMsr & EmuFeat.fVmxEntryLoadPatMsr );
1951	pGuestFeat->fVmxExitSaveDebugCtls = (pBaseFeat->fVmxExitSaveDebugCtls & EmuFeat.fVmxExitSaveDebugCtls );
1952	pGuestFeat->fVmxHostAddrSpaceSize = (pBaseFeat->fVmxHostAddrSpaceSize & EmuFeat.fVmxHostAddrSpaceSize );
1953	pGuestFeat->fVmxExitAckExtInt = (pBaseFeat->fVmxExitAckExtInt & EmuFeat.fVmxExitAckExtInt );
1954	pGuestFeat->fVmxExitSavePatMsr = (pBaseFeat->fVmxExitSavePatMsr & EmuFeat.fVmxExitSavePatMsr );
1955	pGuestFeat->fVmxExitLoadPatMsr = (pBaseFeat->fVmxExitLoadPatMsr & EmuFeat.fVmxExitLoadPatMsr );
1956	pGuestFeat->fVmxExitSaveEferMsr = (pBaseFeat->fVmxExitSaveEferMsr & EmuFeat.fVmxExitSaveEferMsr );
1957	pGuestFeat->fVmxExitLoadEferMsr = (pBaseFeat->fVmxExitLoadEferMsr & EmuFeat.fVmxExitLoadEferMsr );
1958	pGuestFeat->fVmxSavePreemptTimer = (pBaseFeat->fVmxSavePreemptTimer & EmuFeat.fVmxSavePreemptTimer );
1959	pGuestFeat->fVmxExitCtls2 = (pBaseFeat->fVmxExitCtls2 & EmuFeat.fVmxExitCtls2 );
1960	pGuestFeat->fVmxExitSaveEferLma = (pBaseFeat->fVmxExitSaveEferLma & EmuFeat.fVmxExitSaveEferLma );
1961	pGuestFeat->fVmxPt = (pBaseFeat->fVmxPt & EmuFeat.fVmxPt );
1962	pGuestFeat->fVmxVmwriteAll = (pBaseFeat->fVmxVmwriteAll & EmuFeat.fVmxVmwriteAll );
1963	pGuestFeat->fVmxEntryInjectSoftInt = (pBaseFeat->fVmxEntryInjectSoftInt & EmuFeat.fVmxEntryInjectSoftInt );
1964
1965	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1966	/* Don't expose VMX preemption timer if host is subject to VMX-preemption timer erratum. */
1967	if ( pGuestFeat->fVmxPreemptTimer
1968	&& HMIsSubjectToVmxPreemptTimerErratum())
1969	{
1970	LogRel(("CPUM: Warning! VMX-preemption timer not exposed to guest due to host CPU erratum\n"));
1971	pGuestFeat->fVmxPreemptTimer = 0;
1972	pGuestFeat->fVmxSavePreemptTimer = 0;
1973	}
1974	#endif
1975
1976	/* Sanity checking. */
1977	if (!pGuestFeat->fVmxSecondaryExecCtls)
1978	{
1979	Assert(!pGuestFeat->fVmxVirtApicAccess);
1980	Assert(!pGuestFeat->fVmxEpt);
1981	Assert(!pGuestFeat->fVmxDescTableExit);
1982	Assert(!pGuestFeat->fVmxRdtscp);
1983	Assert(!pGuestFeat->fVmxVirtX2ApicMode);
1984	Assert(!pGuestFeat->fVmxVpid);
1985	Assert(!pGuestFeat->fVmxWbinvdExit);
1986	Assert(!pGuestFeat->fVmxUnrestrictedGuest);
1987	Assert(!pGuestFeat->fVmxApicRegVirt);
1988	Assert(!pGuestFeat->fVmxVirtIntDelivery);
1989	Assert(!pGuestFeat->fVmxPauseLoopExit);
1990	Assert(!pGuestFeat->fVmxRdrandExit);
1991	Assert(!pGuestFeat->fVmxInvpcid);
1992	Assert(!pGuestFeat->fVmxVmFunc);
1993	Assert(!pGuestFeat->fVmxVmcsShadowing);
1994	Assert(!pGuestFeat->fVmxRdseedExit);
1995	Assert(!pGuestFeat->fVmxPml);
1996	Assert(!pGuestFeat->fVmxEptXcptVe);
1997	Assert(!pGuestFeat->fVmxConcealVmxFromPt);
1998	Assert(!pGuestFeat->fVmxXsavesXrstors);
1999	Assert(!pGuestFeat->fVmxModeBasedExecuteEpt);
2000	Assert(!pGuestFeat->fVmxSppEpt);
2001	Assert(!pGuestFeat->fVmxPtEpt);
2002	Assert(!pGuestFeat->fVmxUseTscScaling);
2003	Assert(!pGuestFeat->fVmxUserWaitPause);
2004	Assert(!pGuestFeat->fVmxEnclvExit);
2005	}
2006	else if (pGuestFeat->fVmxUnrestrictedGuest)
2007	{
2008	/* See footnote in Intel spec. 27.2 "Recording VM-Exit Information And Updating VM-entry Control Fields". */
2009	Assert(pGuestFeat->fVmxExitSaveEferLma);
2010	/* Unrestricted guest execution requires EPT. See Intel spec. 25.2.1.1 "VM-Execution Control Fields". */
2011	Assert(pGuestFeat->fVmxEpt);
2012	}
2013
2014	if (!pGuestFeat->fVmxTertiaryExecCtls)
2015	Assert(!pGuestFeat->fVmxLoadIwKeyExit);
2016
2017	/*
2018	* Finally initialize the VMX guest MSRs.
2019	*/
2020	cpumR3InitVmxGuestMsrs(pVM, pHostVmxMsrs, pGuestFeat, pGuestVmxMsrs);
2021	}
2022
2023
2024	/**
2025	* Gets the host hardware-virtualization MSRs.
2026	*
2027	* @returns VBox status code.
2028	* @param pMsrs Where to store the MSRs.
2029	*/
2030	static int cpumR3GetHostHwvirtMsrs(PCPUMMSRS pMsrs)
2031	{
2032	Assert(pMsrs);
2033
2034	uint32_t fCaps = 0;
2035	int rc = SUPR3QueryVTCaps(&fCaps);
2036	if (RT_SUCCESS(rc))
2037	{
2038	if (fCaps & (SUPVTCAPS_VT_X \| SUPVTCAPS_AMD_V))
2039	{
2040	SUPHWVIRTMSRS HwvirtMsrs;
2041	rc = SUPR3GetHwvirtMsrs(&HwvirtMsrs, false /* fForceRequery */);
2042	if (RT_SUCCESS(rc))
2043	{
2044	if (fCaps & SUPVTCAPS_VT_X)
2045	HMGetVmxMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.vmx);
2046	else
2047	HMGetSvmMsrsFromHwvirtMsrs(&HwvirtMsrs, &pMsrs->hwvirt.svm);
2048	return VINF_SUCCESS;
2049	}
2050
2051	LogRel(("CPUM: Querying hardware-virtualization MSRs failed. rc=%Rrc\n", rc));
2052	return rc;
2053	}
2054
2055	LogRel(("CPUM: Querying hardware-virtualization capability succeeded but did not find VT-x or AMD-V\n"));
2056	return VERR_INTERNAL_ERROR_5;
2057	}
2058
2059	LogRel(("CPUM: No hardware-virtualization capability detected\n"));
2060	return VINF_SUCCESS;
2061	}
2062
2063
2064	/**
2065	* @callback_method_impl{FNTMTIMERINT,
2066	* Callback that fires when the nested VMX-preemption timer expired.}
2067	*/
2068	static DECLCALLBACK(void) cpumR3VmxPreemptTimerCallback(PVM pVM, TMTIMERHANDLE hTimer, void *pvUser)
2069	{
2070	RT_NOREF(pVM, hTimer);
2071	PVMCPU pVCpu = (PVMCPUR3)pvUser;
2072	AssertPtr(pVCpu);
2073	VMCPU_FF_SET(pVCpu, VMCPU_FF_VMX_PREEMPT_TIMER);
2074	}
2075
2076
2077	/**
2078	* Initializes the CPUM.
2079	*
2080	* @returns VBox status code.
2081	* @param pVM The cross context VM structure.
2082	*/
2083	VMMR3DECL(int) CPUMR3Init(PVM pVM)
2084	{
2085	LogFlow(("CPUMR3Init\n"));
2086
2087	/*
2088	* Assert alignment, sizes and tables.
2089	*/
2090	AssertCompileMemberAlignment(VM, cpum.s, 32);
2091	AssertCompile(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
2092	AssertCompileSizeAlignment(CPUMCTX, 64);
2093	AssertCompileSizeAlignment(CPUMCTXMSRS, 64);
2094	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
2095	AssertCompileMemberAlignment(VM, cpum, 64);
2096	AssertCompileMemberAlignment(VMCPU, cpum.s, 64);
2097	#ifdef VBOX_STRICT
2098	int rc2 = cpumR3MsrStrictInitChecks();
2099	AssertRCReturn(rc2, rc2);
2100	#endif
2101
2102	/*
2103	* Gather info about the host CPU.
2104	*/
2105	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2106	if (!ASMHasCpuId())
2107	{
2108	LogRel(("The CPU doesn't support CPUID!\n"));
2109	return VERR_UNSUPPORTED_CPU;
2110	}
2111
2112	pVM->cpum.s.fHostMxCsrMask = CPUMR3DeterminHostMxCsrMask();
2113	#endif
2114
2115	CPUMMSRS HostMsrs;
2116	RT_ZERO(HostMsrs);
2117	int rc = cpumR3GetHostHwvirtMsrs(&HostMsrs);
2118	AssertLogRelRCReturn(rc, rc);
2119
2120	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2121	/* Use the host features detected by CPUMR0ModuleInit if available. */
2122	if (pVM->cpum.s.HostFeatures.enmCpuVendor != CPUMCPUVENDOR_INVALID)
2123	g_CpumHostFeatures.s = pVM->cpum.s.HostFeatures;
2124	else
2125	{
2126	PCPUMCPUIDLEAF paLeaves;
2127	uint32_t cLeaves;
2128	rc = CPUMCpuIdCollectLeavesX86(&paLeaves, &cLeaves);
2129	AssertLogRelRCReturn(rc, rc);
2130
2131	rc = cpumCpuIdExplodeFeaturesX86(paLeaves, cLeaves, &HostMsrs, &g_CpumHostFeatures.s);
2132	RTMemFree(paLeaves);
2133	AssertLogRelRCReturn(rc, rc);
2134	}
2135	pVM->cpum.s.HostFeatures = g_CpumHostFeatures.s;
2136	pVM->cpum.s.GuestFeatures.enmCpuVendor = pVM->cpum.s.HostFeatures.enmCpuVendor;
2137	#endif
2138
2139	/*
2140	* Check that the CPU supports the minimum features we require.
2141	*/
2142	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
2143	if (!pVM->cpum.s.HostFeatures.fFxSaveRstor)
2144	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support the FXSAVE/FXRSTOR instruction.");
2145	if (!pVM->cpum.s.HostFeatures.fMmx)
2146	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support MMX.");
2147	if (!pVM->cpum.s.HostFeatures.fTsc)
2148	return VMSetError(pVM, VERR_UNSUPPORTED_CPU, RT_SRC_POS, "Host CPU does not support RDTSC.");
2149	#endif
2150
2151	/*
2152	* Setup the CR4 AND and OR masks used in the raw-mode switcher.
2153	*/
2154	pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT \| X86_CR4_PVI \| X86_CR4_VME;
2155	pVM->cpum.s.CR4.OrMask = X86_CR4_OSFXSR;
2156
2157	/*
2158	* Figure out which XSAVE/XRSTOR features are available on the host.
2159	*/
2160	uint64_t fXcr0Host = 0;
2161	uint64_t fXStateHostMask = 0;
2162	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2163	if ( pVM->cpum.s.HostFeatures.fXSaveRstor
2164	&& pVM->cpum.s.HostFeatures.fOpSysXSaveRstor)
2165	{
2166	fXStateHostMask = fXcr0Host = ASMGetXcr0();
2167	fXStateHostMask &= XSAVE_C_X87 \| XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI;
2168	AssertLogRelMsgStmt((fXStateHostMask & (XSAVE_C_X87 \| XSAVE_C_SSE)) == (XSAVE_C_X87 \| XSAVE_C_SSE),
2169	("%#llx\n", fXStateHostMask), fXStateHostMask = 0);
2170	}
2171	#endif
2172	pVM->cpum.s.fXStateHostMask = fXStateHostMask;
2173	LogRel(("CPUM: fXStateHostMask=%#llx; initial: %#llx; host XCR0=%#llx\n",
2174	pVM->cpum.s.fXStateHostMask, fXStateHostMask, fXcr0Host));
2175
2176	/*
2177	* Initialize the host XSAVE/XRSTOR mask.
2178	*/
2179	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2180	uint32_t cbMaxXState = pVM->cpum.s.HostFeatures.cbMaxExtendedState;
2181	cbMaxXState = RT_ALIGN(cbMaxXState, 128);
2182	AssertLogRelReturn( pVM->cpum.s.HostFeatures.cbMaxExtendedState >= sizeof(X86FXSTATE)
2183	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Host.XState)
2184	&& pVM->cpum.s.HostFeatures.cbMaxExtendedState <= sizeof(pVM->apCpusR3[0]->cpum.s.Guest.XState)
2185	, VERR_CPUM_IPE_2);
2186	#endif
2187
2188	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2189	{
2190	PVMCPU pVCpu = pVM->apCpusR3[i];
2191
2192	pVCpu->cpum.s.Host.fXStateMask = fXStateHostMask;
2193	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2194	}
2195
2196	/*
2197	* Register saved state data item.
2198	*/
2199	rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
2200	NULL, cpumR3LiveExec, NULL,
2201	NULL, cpumR3SaveExec, NULL,
2202	cpumR3LoadPrep, cpumR3LoadExec, cpumR3LoadDone);
2203	if (RT_FAILURE(rc))
2204	return rc;
2205
2206	/*
2207	* Register info handlers and registers with the debugger facility.
2208	*/
2209	DBGFR3InfoRegisterInternalEx(pVM, "cpum", "Displays the all the cpu states.",
2210	&cpumR3InfoAll, DBGFINFO_FLAGS_ALL_EMTS);
2211	DBGFR3InfoRegisterInternalEx(pVM, "cpumguest", "Displays the guest cpu state.",
2212	&cpumR3InfoGuest, DBGFINFO_FLAGS_ALL_EMTS);
2213	DBGFR3InfoRegisterInternalEx(pVM, "cpumguesthwvirt", "Displays the guest hwvirt. cpu state.",
2214	&cpumR3InfoGuestHwvirt, DBGFINFO_FLAGS_ALL_EMTS);
2215	DBGFR3InfoRegisterInternalEx(pVM, "cpumhyper", "Displays the hypervisor cpu state.",
2216	&cpumR3InfoHyper, DBGFINFO_FLAGS_ALL_EMTS);
2217	DBGFR3InfoRegisterInternalEx(pVM, "cpumhost", "Displays the host cpu state.",
2218	&cpumR3InfoHost, DBGFINFO_FLAGS_ALL_EMTS);
2219	DBGFR3InfoRegisterInternalEx(pVM, "cpumguestinstr", "Displays the current guest instruction.",
2220	&cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
2221	DBGFR3InfoRegisterInternal( pVM, "cpuid", "Displays the guest cpuid leaves.",
2222	&cpumR3CpuIdInfo);
2223	DBGFR3InfoRegisterInternal( pVM, "cpumvmxfeat", "Displays the host and guest VMX hwvirt. features.",
2224	&cpumR3InfoVmxFeatures);
2225
2226	rc = cpumR3DbgInit(pVM);
2227	if (RT_FAILURE(rc))
2228	return rc;
2229
2230	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
2231	/*
2232	* Check if we need to workaround partial/leaky FPU handling.
2233	*/
2234	cpumR3CheckLeakyFpu(pVM);
2235	#endif
2236
2237	/*
2238	* Initialize the Guest CPUID and MSR states.
2239	*/
2240	rc = cpumR3InitCpuIdAndMsrs(pVM, &HostMsrs);
2241	if (RT_FAILURE(rc))
2242	return rc;
2243
2244	/*
2245	* Generate the RFLAGS cookie.
2246	*/
2247	pVM->cpum.s.fReservedRFlagsCookie = RTRandU64() & ~(CPUMX86EFLAGS_HW_MASK_64 \| CPUMX86EFLAGS_INT_MASK_64);
2248
2249	/*
2250	* Init the VMX/SVM state.
2251	*
2252	* This must be done after initializing CPUID/MSR features as we access the
2253	* the VMX/SVM guest features below.
2254	*
2255	* In the case of nested VT-x, we also need to create the per-VCPU
2256	* VMX preemption timers.
2257	*/
2258	if (pVM->cpum.s.GuestFeatures.fVmx)
2259	cpumR3InitVmxHwVirtState(pVM);
2260	else if (pVM->cpum.s.GuestFeatures.fSvm)
2261	cpumR3InitSvmHwVirtState(pVM);
2262	else
2263	Assert(pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.enmHwvirt == CPUMHWVIRT_NONE);
2264
2265	/*
2266	* Initialize the general guest CPU state.
2267	*/
2268	CPUMR3Reset(pVM);
2269
2270	return VINF_SUCCESS;
2271	}
2272
2273
2274	/**
2275	* Applies relocations to data and code managed by this
2276	* component. This function will be called at init and
2277	* whenever the VMM need to relocate it self inside the GC.
2278	*
2279	* The CPUM will update the addresses used by the switcher.
2280	*
2281	* @param pVM The cross context VM structure.
2282	*/
2283	VMMR3DECL(void) CPUMR3Relocate(PVM pVM)
2284	{
2285	RT_NOREF(pVM);
2286	}
2287
2288
2289	/**
2290	* Terminates the CPUM.
2291	*
2292	* Termination means cleaning up and freeing all resources,
2293	* the VM it self is at this point powered off or suspended.
2294	*
2295	* @returns VBox status code.
2296	* @param pVM The cross context VM structure.
2297	*/
2298	VMMR3DECL(int) CPUMR3Term(PVM pVM)
2299	{
2300	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2301	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2302	{
2303	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2304	memset(pVCpu->cpum.s.aMagic, 0, sizeof(pVCpu->cpum.s.aMagic));
2305	pVCpu->cpum.s.uMagic = 0;
2306	pvCpu->cpum.s.Guest.dr[5] = 0;
2307	}
2308	#endif
2309
2310	if (pVM->cpum.s.GuestFeatures.fVmx)
2311	{
2312	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2313	{
2314	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2315	if (pVCpu->cpum.s.hNestedVmxPreemptTimer != NIL_TMTIMERHANDLE)
2316	{
2317	int rc = TMR3TimerDestroy(pVM, pVCpu->cpum.s.hNestedVmxPreemptTimer); AssertRC(rc);
2318	pVCpu->cpum.s.hNestedVmxPreemptTimer = NIL_TMTIMERHANDLE;
2319	}
2320	}
2321	}
2322	return VINF_SUCCESS;
2323	}
2324
2325
2326	/**
2327	* Resets a virtual CPU.
2328	*
2329	* Used by CPUMR3Reset and CPU hot plugging.
2330	*
2331	* @param pVM The cross context VM structure.
2332	* @param pVCpu The cross context virtual CPU structure of the CPU that is
2333	* being reset. This may differ from the current EMT.
2334	*/
2335	VMMR3DECL(void) CPUMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2336	{
2337	/** @todo anything different for VCPU > 0? */
2338	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
2339
2340	/*
2341	* Initialize everything to ZERO first.
2342	*/
2343	uint32_t fUseFlags = pVCpu->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
2344
2345	RT_BZERO(pCtx, RT_UOFFSETOF(CPUMCTX, aoffXState));
2346
2347	pVCpu->cpum.s.fUseFlags = fUseFlags;
2348
2349	pCtx->cr0 = X86_CR0_CD \| X86_CR0_NW \| X86_CR0_ET; //0x60000010
2350	pCtx->eip = 0x0000fff0;
2351	pCtx->edx = 0x00000600; /* P6 processor */
2352
2353	Assert((pVM->cpum.s.fReservedRFlagsCookie & (X86_EFL_LIVE_MASK \| X86_EFL_RAZ_LO_MASK \| X86_EFL_RA1_MASK)) == 0);
2354	pCtx->rflags.uBoth = pVM->cpum.s.fReservedRFlagsCookie \| X86_EFL_RA1_MASK;
2355
2356	pCtx->cs.Sel = 0xf000;
2357	pCtx->cs.ValidSel = 0xf000;
2358	pCtx->cs.fFlags = CPUMSELREG_FLAGS_VALID;
2359	pCtx->cs.u64Base = UINT64_C(0xffff0000);
2360	pCtx->cs.u32Limit = 0x0000ffff;
2361	pCtx->cs.Attr.n.u1DescType = 1; /* code/data segment */
2362	pCtx->cs.Attr.n.u1Present = 1;
2363	pCtx->cs.Attr.n.u4Type = X86_SEL_TYPE_ER_ACC;
2364
2365	pCtx->ds.fFlags = CPUMSELREG_FLAGS_VALID;
2366	pCtx->ds.u32Limit = 0x0000ffff;
2367	pCtx->ds.Attr.n.u1DescType = 1; /* code/data segment */
2368	pCtx->ds.Attr.n.u1Present = 1;
2369	pCtx->ds.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2370
2371	pCtx->es.fFlags = CPUMSELREG_FLAGS_VALID;
2372	pCtx->es.u32Limit = 0x0000ffff;
2373	pCtx->es.Attr.n.u1DescType = 1; /* code/data segment */
2374	pCtx->es.Attr.n.u1Present = 1;
2375	pCtx->es.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2376
2377	pCtx->fs.fFlags = CPUMSELREG_FLAGS_VALID;
2378	pCtx->fs.u32Limit = 0x0000ffff;
2379	pCtx->fs.Attr.n.u1DescType = 1; /* code/data segment */
2380	pCtx->fs.Attr.n.u1Present = 1;
2381	pCtx->fs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2382
2383	pCtx->gs.fFlags = CPUMSELREG_FLAGS_VALID;
2384	pCtx->gs.u32Limit = 0x0000ffff;
2385	pCtx->gs.Attr.n.u1DescType = 1; /* code/data segment */
2386	pCtx->gs.Attr.n.u1Present = 1;
2387	pCtx->gs.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2388
2389	pCtx->ss.fFlags = CPUMSELREG_FLAGS_VALID;
2390	pCtx->ss.u32Limit = 0x0000ffff;
2391	pCtx->ss.Attr.n.u1Present = 1;
2392	pCtx->ss.Attr.n.u1DescType = 1; /* code/data segment */
2393	pCtx->ss.Attr.n.u4Type = X86_SEL_TYPE_RW_ACC;
2394
2395	pCtx->idtr.cbIdt = 0xffff;
2396	pCtx->gdtr.cbGdt = 0xffff;
2397
2398	pCtx->ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
2399	pCtx->ldtr.u32Limit = 0xffff;
2400	pCtx->ldtr.Attr.n.u1Present = 1;
2401	pCtx->ldtr.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
2402
2403	pCtx->tr.fFlags = CPUMSELREG_FLAGS_VALID;
2404	pCtx->tr.u32Limit = 0xffff;
2405	pCtx->tr.Attr.n.u1Present = 1;
2406	pCtx->tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY; /* Deduction, not properly documented by Intel. */
2407
2408	pCtx->dr[6] = X86_DR6_INIT_VAL;
2409	pCtx->dr[7] = X86_DR7_INIT_VAL;
2410
2411	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
2412	pFpuCtx->FTW = 0x00; /* All empty (abbridged tag reg edition). */
2413	pFpuCtx->FCW = 0x37f;
2414
2415	/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1.
2416	IA-32 Processor States Following Power-up, Reset, or INIT */
2417	pFpuCtx->MXCSR = 0x1F80;
2418	pFpuCtx->MXCSR_MASK = pVM->cpum.s.GuestInfo.fMxCsrMask; /** @todo check if REM messes this up... */
2419
2420	pCtx->aXcr[0] = XSAVE_C_X87;
2421	if (pVM->cpum.s.HostFeatures.cbMaxExtendedState >= RT_UOFFSETOF(X86XSAVEAREA, Hdr))
2422	{
2423	/* The entire FXSAVE state needs loading when we switch to XSAVE/XRSTOR
2424	as we don't know what happened before. (Bother optimize later?) */
2425	pCtx->XState.Hdr.bmXState = XSAVE_C_X87 \| XSAVE_C_SSE;
2426	}
2427
2428	/*
2429	* MSRs.
2430	*/
2431	/* Init PAT MSR */
2432	pCtx->msrPAT = MSR_IA32_CR_PAT_INIT_VAL;
2433
2434	/* EFER MBZ; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State.
2435	* The Intel docs don't mention it. */
2436	Assert(!pCtx->msrEFER);
2437
2438	/* IA32_MISC_ENABLE - not entirely sure what the init/reset state really
2439	is supposed to be here, just trying provide useful/sensible values. */
2440	PCPUMMSRRANGE pRange = cpumLookupMsrRange(pVM, MSR_IA32_MISC_ENABLE);
2441	if (pRange)
2442	{
2443	pVCpu->cpum.s.GuestMsrs.msr.MiscEnable = MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2444	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL
2445	\| (pVM->cpum.s.GuestFeatures.fMonitorMWait ? MSR_IA32_MISC_ENABLE_MONITOR : 0)
2446	\| MSR_IA32_MISC_ENABLE_FAST_STRINGS;
2447	pRange->fWrIgnMask \|= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL
2448	\| MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
2449	pRange->fWrGpMask &= ~pVCpu->cpum.s.GuestMsrs.msr.MiscEnable;
2450	}
2451
2452	/** @todo Wire IA32_MISC_ENABLE bit 22 to our NT 4 CPUID trick. */
2453
2454	/** @todo r=ramshankar: Currently broken for SMP as TMCpuTickSet() expects to be
2455	* called from each EMT while we're getting called by CPUMR3Reset()
2456	* iteratively on the same thread. Fix later. */
2457	#if 0 /** @todo r=bird: This we will do in TM, not here. */
2458	/* TSC must be 0. Intel spec. Table 9-1. "IA-32 Processor States Following Power-up, Reset, or INIT." */
2459	CPUMSetGuestMsr(pVCpu, MSR_IA32_TSC, 0);
2460	#endif
2461
2462
2463	/* C-state control. Guesses. */
2464	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 1 /C1/ \| RT_BIT_32(25) \| RT_BIT_32(26) \| RT_BIT_32(27) \| RT_BIT_32(28);
2465	/* For Nehalem+ and Atoms, the 0xE2 MSR (MSR_PKG_CST_CONFIG_CONTROL) is documented. For Core 2,
2466	* it's undocumented but exists as MSR_PMG_CST_CONFIG_CONTROL and has similar but not identical
2467	* functionality. The default value must be different due to incompatible write mask.
2468	*/
2469	if (CPUMMICROARCH_IS_INTEL_CORE2(pVM->cpum.s.GuestFeatures.enmMicroarch))
2470	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x202a01; /* From Mac Pro Harpertown, unlocked. */
2471	else if (pVM->cpum.s.GuestFeatures.enmMicroarch == kCpumMicroarch_Intel_Core_Yonah)
2472	pVCpu->cpum.s.GuestMsrs.msr.PkgCStateCfgCtrl = 0x26740c; /* From MacBookPro1,1. */
2473
2474	/*
2475	* Hardware virtualization state.
2476	*/
2477	CPUMSetGuestGif(pCtx, true);
2478	Assert(!pVM->cpum.s.GuestFeatures.fVmx \|\| !pVM->cpum.s.GuestFeatures.fSvm); /* Paranoia. */
2479	if (pVM->cpum.s.GuestFeatures.fVmx)
2480	cpumR3ResetVmxHwVirtState(pVCpu);
2481	else if (pVM->cpum.s.GuestFeatures.fSvm)
2482	cpumR3ResetSvmHwVirtState(pVCpu);
2483	}
2484
2485
2486	/**
2487	* Resets the CPU.
2488	*
2489	* @returns VINF_SUCCESS.
2490	* @param pVM The cross context VM structure.
2491	*/
2492	VMMR3DECL(void) CPUMR3Reset(PVM pVM)
2493	{
2494	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2495	{
2496	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2497	CPUMR3ResetCpu(pVM, pVCpu);
2498
2499	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2500
2501	/* Magic marker for searching in crash dumps. */
2502	strcpy((char *)pVCpu->.cpum.s.aMagic, "CPUMCPU Magic");
2503	pVCpu->cpum.s.uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2504	pVCpu->cpum.s.Guest->dr[5] = UINT64_C(0xDEADBEEFDEADBEEF);
2505	#endif
2506	}
2507	}
2508
2509
2510
2511
2512	/**
2513	* Pass 0 live exec callback.
2514	*
2515	* @returns VINF_SSM_DONT_CALL_AGAIN.
2516	* @param pVM The cross context VM structure.
2517	* @param pSSM The saved state handle.
2518	* @param uPass The pass (0).
2519	*/
2520	static DECLCALLBACK(int) cpumR3LiveExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uPass)
2521	{
2522	AssertReturn(uPass == 0, VERR_SSM_UNEXPECTED_PASS);
2523	cpumR3SaveCpuId(pVM, pSSM);
2524	return VINF_SSM_DONT_CALL_AGAIN;
2525	}
2526
2527
2528	/**
2529	* Execute state save operation.
2530	*
2531	* @returns VBox status code.
2532	* @param pVM The cross context VM structure.
2533	* @param pSSM SSM operation handle.
2534	*/
2535	static DECLCALLBACK(int) cpumR3SaveExec(PVM pVM, PSSMHANDLE pSSM)
2536	{
2537	/*
2538	* Save.
2539	*/
2540	SSMR3PutU32(pSSM, pVM->cCpus);
2541	SSMR3PutU32(pSSM, sizeof(pVM->apCpusR3[0]->cpum.s.GuestMsrs.msr));
2542	CPUMCTX DummyHyperCtx;
2543	RT_ZERO(DummyHyperCtx);
2544	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2545	{
2546	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
2547	PCPUMCTX const pGstCtx = &pVCpu->cpum.s.Guest;
2548
2549	/** @todo ditch this the next time we change the saved state. */
2550	SSMR3PutStructEx(pSSM, &DummyHyperCtx, sizeof(DummyHyperCtx), 0, g_aCpumCtxFields, NULL);
2551
2552	uint64_t const fSavedRFlags = pGstCtx->rflags.uBoth;
2553	pGstCtx->rflags.uBoth &= CPUMX86EFLAGS_HW_MASK_64; /* Temporarily clear the non-hardware bits in RFLAGS while saving. */
2554	SSMR3PutStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2555	pGstCtx->rflags.uBoth = fSavedRFlags;
2556
2557	SSMR3PutStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2558	if (pGstCtx->fXStateMask != 0)
2559	SSMR3PutStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr), 0, g_aCpumXSaveHdrFields, NULL);
2560	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2561	{
2562	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
2563	SSMR3PutStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2564	}
2565	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2566	{
2567	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
2568	SSMR3PutStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2569	}
2570	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2571	{
2572	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
2573	SSMR3PutStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2574	}
2575	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2576	{
2577	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
2578	SSMR3PutStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2579	}
2580	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2581	{
2582	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
2583	SSMR3PutStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2584	}
2585	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[0].u);
2586	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[1].u);
2587	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[2].u);
2588	SSMR3PutU64(pSSM, pGstCtx->aPaePdpes[3].u);
2589	if (pVM->cpum.s.GuestFeatures.fSvm)
2590	{
2591	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uMsrHSavePa);
2592	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.svm.GCPhysVmcb);
2593	SSMR3PutU64(pSSM, pGstCtx->hwvirt.svm.uPrevPauseTick);
2594	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilter);
2595	SSMR3PutU16(pSSM, pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2596	SSMR3PutBool(pSSM, pGstCtx->hwvirt.svm.fInterceptEvents);
2597	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState), 0 /* fFlags */,
2598	g_aSvmHwvirtHostState, NULL /* pvUser */);
2599	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2600	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2601	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2602	/* This is saved in the old VMCPUM_FF format. Change if more flags are added. */
2603	SSMR3PutU32(pSSM, pGstCtx->hwvirt.fSavedInhibit & CPUMCTX_INHIBIT_NMI ? CPUM_OLD_VMCPU_FF_BLOCK_NMIS : 0);
2604	SSMR3PutBool(pSSM, pGstCtx->hwvirt.fGif);
2605	}
2606	if (pVM->cpum.s.GuestFeatures.fVmx)
2607	{
2608	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmxon);
2609	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysVmcs);
2610	SSMR3PutGCPhys(pSSM, pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2611	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxRootMode);
2612	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2613	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fInterceptEvents);
2614	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2615	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs), 0, g_aVmxHwvirtVmcs, NULL);
2616	SSMR3PutStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2617	0, g_aVmxHwvirtVmcs, NULL);
2618	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2619	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2620	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2621	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2622	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2623	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2624	SSMR3PutMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2625	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2626	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uPrevPauseTick);
2627	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.uEntryTick);
2628	SSMR3PutU16(pSSM, pGstCtx->hwvirt.vmx.offVirtApicWrite);
2629	SSMR3PutBool(pSSM, pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2630	SSMR3PutU64(pSSM, MSR_IA32_FEATURE_CONTROL_LOCK \| MSR_IA32_FEATURE_CONTROL_VMXON); /* Deprecated since 2021/09/22. Value kept backwards compatibile with 6.1.26. */
2631	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2632	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2633	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2634	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2635	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2636	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2637	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2638	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2639	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2640	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2641	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2642	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2643	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2644	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2645	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2646	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2647	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2648	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2649	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2650	SSMR3PutU64(pSSM, pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2651	}
2652	SSMR3PutU32(pSSM, pVCpu->cpum.s.fUseFlags);
2653	SSMR3PutU32(pSSM, pVCpu->cpum.s.fChanged);
2654	AssertCompileSizeAlignment(pVCpu->cpum.s.GuestMsrs.msr, sizeof(uint64_t));
2655	SSMR3PutMem(pSSM, &pVCpu->cpum.s.GuestMsrs, sizeof(pVCpu->cpum.s.GuestMsrs.msr));
2656	}
2657
2658	cpumR3SaveCpuId(pVM, pSSM);
2659	return VINF_SUCCESS;
2660	}
2661
2662
2663	/**
2664	* @callback_method_impl{FNSSMINTLOADPREP}
2665	*/
2666	static DECLCALLBACK(int) cpumR3LoadPrep(PVM pVM, PSSMHANDLE pSSM)
2667	{
2668	NOREF(pSSM);
2669	pVM->cpum.s.fPendingRestore = true;
2670	return VINF_SUCCESS;
2671	}
2672
2673
2674	/**
2675	* @callback_method_impl{FNSSMINTLOADEXEC}
2676	*/
2677	static DECLCALLBACK(int) cpumR3LoadExec(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2678	{
2679	int rc; /* Only for AssertRCReturn use. */
2680
2681	/*
2682	* Validate version.
2683	*/
2684	if ( uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3
2685	&& uVersion != CPUM_SAVED_STATE_VERSION_PAE_PDPES
2686	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2
2687	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_VMX
2688	&& uVersion != CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
2689	&& uVersion != CPUM_SAVED_STATE_VERSION_XSAVE
2690	&& uVersion != CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT
2691	&& uVersion != CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT
2692	&& uVersion != CPUM_SAVED_STATE_VERSION_PUT_STRUCT
2693	&& uVersion != CPUM_SAVED_STATE_VERSION_MEM
2694	&& uVersion != CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE
2695	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_2
2696	&& uVersion != CPUM_SAVED_STATE_VERSION_VER3_0
2697	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR
2698	&& uVersion != CPUM_SAVED_STATE_VERSION_VER2_0
2699	&& uVersion != CPUM_SAVED_STATE_VERSION_VER1_6)
2700	{
2701	AssertMsgFailed(("cpumR3LoadExec: Invalid version uVersion=%d!\n", uVersion));
2702	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2703	}
2704
2705	if (uPass == SSM_PASS_FINAL)
2706	{
2707	/*
2708	* Set the size of RTGCPTR for SSMR3GetGCPtr. (Only necessary for
2709	* really old SSM file versions.)
2710	*/
2711	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2712	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR32));
2713	else if (uVersion <= CPUM_SAVED_STATE_VERSION_VER3_0)
2714	SSMR3HandleSetGCPtrSize(pSSM, sizeof(RTGCPTR));
2715
2716	/*
2717	* Figure x86 and ctx field definitions to use for older states.
2718	*/
2719	uint32_t const fLoad = uVersion > CPUM_SAVED_STATE_VERSION_MEM ? 0 : SSMSTRUCT_FLAGS_MEM_BAND_AID_RELAXED;
2720	PCSSMFIELD paCpumCtx1Fields = g_aCpumX87Fields;
2721	PCSSMFIELD paCpumCtx2Fields = g_aCpumCtxFields;
2722	if (uVersion == CPUM_SAVED_STATE_VERSION_VER1_6)
2723	{
2724	paCpumCtx1Fields = g_aCpumX87FieldsV16;
2725	paCpumCtx2Fields = g_aCpumCtxFieldsV16;
2726	}
2727	else if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2728	{
2729	paCpumCtx1Fields = g_aCpumX87FieldsMem;
2730	paCpumCtx2Fields = g_aCpumCtxFieldsMem;
2731	}
2732
2733	/*
2734	* The hyper state used to preceed the CPU count. Starting with
2735	* XSAVE it was moved down till after we've got the count.
2736	*/
2737	CPUMCTX HyperCtxIgnored;
2738	if (uVersion < CPUM_SAVED_STATE_VERSION_XSAVE)
2739	{
2740	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2741	{
2742	X86FXSTATE Ign;
2743	SSMR3GetStructEx(pSSM, &Ign, sizeof(Ign), fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2744	SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored),
2745	fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2746	}
2747	}
2748
2749	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR)
2750	{
2751	uint32_t cCpus;
2752	rc = SSMR3GetU32(pSSM, &cCpus); AssertRCReturn(rc, rc);
2753	AssertLogRelMsgReturn(cCpus == pVM->cCpus, ("Mismatching CPU counts: saved: %u; configured: %u \n", cCpus, pVM->cCpus),
2754	VERR_SSM_UNEXPECTED_DATA);
2755	}
2756	AssertLogRelMsgReturn( uVersion > CPUM_SAVED_STATE_VERSION_VER2_0
2757	\|\| pVM->cCpus == 1,
2758	("cCpus=%u\n", pVM->cCpus),
2759	VERR_SSM_UNEXPECTED_DATA);
2760
2761	uint32_t cbMsrs = 0;
2762	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2763	{
2764	rc = SSMR3GetU32(pSSM, &cbMsrs); AssertRCReturn(rc, rc);
2765	AssertLogRelMsgReturn(RT_ALIGN(cbMsrs, sizeof(uint64_t)) == cbMsrs, ("Size of MSRs is misaligned: %#x\n", cbMsrs),
2766	VERR_SSM_UNEXPECTED_DATA);
2767	AssertLogRelMsgReturn(cbMsrs <= sizeof(CPUMCTXMSRS) && cbMsrs > 0, ("Size of MSRs is out of range: %#x\n", cbMsrs),
2768	VERR_SSM_UNEXPECTED_DATA);
2769	}
2770
2771	/*
2772	* Do the per-CPU restoring.
2773	*/
2774	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2775	{
2776	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2777	PCPUMCTX pGstCtx = &pVCpu->cpum.s.Guest;
2778
2779	if (uVersion >= CPUM_SAVED_STATE_VERSION_XSAVE)
2780	{
2781	/*
2782	* The XSAVE saved state layout moved the hyper state down here.
2783	*/
2784	rc = SSMR3GetStructEx(pSSM, &HyperCtxIgnored, sizeof(HyperCtxIgnored), 0, g_aCpumCtxFields, NULL);
2785	AssertRCReturn(rc, rc);
2786
2787	/*
2788	* Start by restoring the CPUMCTX structure and the X86FXSAVE bits of the extended state.
2789	*/
2790	rc = SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), 0, g_aCpumCtxFields, NULL);
2791	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87), 0, g_aCpumX87Fields, NULL);
2792	AssertRCReturn(rc, rc);
2793
2794	/* Check that the xsave/xrstor mask is valid (invalid results in #GP). */
2795	if (pGstCtx->fXStateMask != 0)
2796	{
2797	AssertLogRelMsgReturn(!(pGstCtx->fXStateMask & ~pVM->cpum.s.fXStateGuestMask),
2798	("fXStateMask=%#RX64 fXStateGuestMask=%#RX64\n",
2799	pGstCtx->fXStateMask, pVM->cpum.s.fXStateGuestMask),
2800	VERR_CPUM_INCOMPATIBLE_XSAVE_COMP_MASK);
2801	AssertLogRelMsgReturn(pGstCtx->fXStateMask & XSAVE_C_X87,
2802	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2803	AssertLogRelMsgReturn((pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2804	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2805	AssertLogRelMsgReturn( (pGstCtx->fXStateMask & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2806	\|\| (pGstCtx->fXStateMask & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2807	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2808	("fXStateMask=%#RX64\n", pGstCtx->fXStateMask), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2809	}
2810
2811	/* Check that the XCR0 mask is valid (invalid results in #GP). */
2812	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87, ("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XCR0);
2813	if (pGstCtx->aXcr[0] != XSAVE_C_X87)
2814	{
2815	AssertLogRelMsgReturn(!(pGstCtx->aXcr[0] & ~(pGstCtx->fXStateMask \| XSAVE_C_X87)),
2816	("xcr0=%#RX64 fXStateMask=%#RX64\n", pGstCtx->aXcr[0], pGstCtx->fXStateMask),
2817	VERR_CPUM_INVALID_XCR0);
2818	AssertLogRelMsgReturn(pGstCtx->aXcr[0] & XSAVE_C_X87,
2819	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2820	AssertLogRelMsgReturn((pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM)) != XSAVE_C_YMM,
2821	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2822	AssertLogRelMsgReturn( (pGstCtx->aXcr[0] & (XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI)) == 0
2823	\|\| (pGstCtx->aXcr[0] & (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI))
2824	== (XSAVE_C_SSE \| XSAVE_C_YMM \| XSAVE_C_OPMASK \| XSAVE_C_ZMM_HI256 \| XSAVE_C_ZMM_16HI),
2825	("xcr0=%#RX64\n", pGstCtx->aXcr[0]), VERR_CPUM_INVALID_XSAVE_COMP_MASK);
2826	}
2827
2828	/* Check that the XCR1 is zero, as we don't implement it yet. */
2829	AssertLogRelMsgReturn(!pGstCtx->aXcr[1], ("xcr1=%#RX64\n", pGstCtx->aXcr[1]), VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2830
2831	/*
2832	* Restore the individual extended state components we support.
2833	*/
2834	if (pGstCtx->fXStateMask != 0)
2835	{
2836	rc = SSMR3GetStructEx(pSSM, &pGstCtx->XState.Hdr, sizeof(pGstCtx->XState.Hdr),
2837	0, g_aCpumXSaveHdrFields, NULL);
2838	AssertRCReturn(rc, rc);
2839	AssertLogRelMsgReturn(!(pGstCtx->XState.Hdr.bmXState & ~pGstCtx->fXStateMask),
2840	("bmXState=%#RX64 fXStateMask=%#RX64\n",
2841	pGstCtx->XState.Hdr.bmXState, pGstCtx->fXStateMask),
2842	VERR_CPUM_INVALID_XSAVE_HDR);
2843	}
2844	if (pGstCtx->fXStateMask & XSAVE_C_YMM)
2845	{
2846	PX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_YMM_BIT, PX86XSAVEYMMHI);
2847	SSMR3GetStructEx(pSSM, pYmmHiCtx, sizeof(*pYmmHiCtx), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumYmmHiFields, NULL);
2848	}
2849	if (pGstCtx->fXStateMask & XSAVE_C_BNDREGS)
2850	{
2851	PX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDREGS_BIT, PX86XSAVEBNDREGS);
2852	SSMR3GetStructEx(pSSM, pBndRegs, sizeof(*pBndRegs), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndRegsFields, NULL);
2853	}
2854	if (pGstCtx->fXStateMask & XSAVE_C_BNDCSR)
2855	{
2856	PX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_BNDCSR_BIT, PX86XSAVEBNDCFG);
2857	SSMR3GetStructEx(pSSM, pBndCfg, sizeof(*pBndCfg), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumBndCfgFields, NULL);
2858	}
2859	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_HI256)
2860	{
2861	PX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_HI256_BIT, PX86XSAVEZMMHI256);
2862	SSMR3GetStructEx(pSSM, pZmmHi256, sizeof(*pZmmHi256), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmmHi256Fields, NULL);
2863	}
2864	if (pGstCtx->fXStateMask & XSAVE_C_ZMM_16HI)
2865	{
2866	PX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pGstCtx, XSAVE_C_ZMM_16HI_BIT, PX86XSAVEZMM16HI);
2867	SSMR3GetStructEx(pSSM, pZmm16Hi, sizeof(*pZmm16Hi), SSMSTRUCT_FLAGS_FULL_STRUCT, g_aCpumZmm16HiFields, NULL);
2868	}
2869	if (uVersion >= CPUM_SAVED_STATE_VERSION_PAE_PDPES)
2870	{
2871	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[0].u);
2872	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[1].u);
2873	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[2].u);
2874	SSMR3GetU64(pSSM, &pGstCtx->aPaePdpes[3].u);
2875	}
2876	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_SVM)
2877	{
2878	if (pVM->cpum.s.GuestFeatures.fSvm)
2879	{
2880	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uMsrHSavePa);
2881	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.svm.GCPhysVmcb);
2882	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.svm.uPrevPauseTick);
2883	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilter);
2884	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.svm.cPauseFilterThreshold);
2885	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.svm.fInterceptEvents);
2886	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.svm.HostState, sizeof(pGstCtx->hwvirt.svm.HostState),
2887	0 /* fFlags /, g_aSvmHwvirtHostState, NULL / pvUser */);
2888	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.Vmcb, sizeof(pGstCtx->hwvirt.svm.Vmcb));
2889	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.svm.abMsrBitmap));
2890	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.svm.abIoBitmap[0], sizeof(pGstCtx->hwvirt.svm.abIoBitmap));
2891
2892	uint32_t fSavedLocalFFs = 0;
2893	rc = SSMR3GetU32(pSSM, &fSavedLocalFFs);
2894	AssertRCReturn(rc, rc);
2895	Assert(fSavedLocalFFs == 0 \|\| fSavedLocalFFs == CPUM_OLD_VMCPU_FF_BLOCK_NMIS);
2896	pGstCtx->hwvirt.fSavedInhibit = fSavedLocalFFs & CPUM_OLD_VMCPU_FF_BLOCK_NMIS ? CPUMCTX_INHIBIT_NMI : 0;
2897
2898	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.fGif);
2899	}
2900	}
2901	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX)
2902	{
2903	if (pVM->cpum.s.GuestFeatures.fVmx)
2904	{
2905	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmxon);
2906	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysVmcs);
2907	SSMR3GetGCPhys(pSSM, &pGstCtx->hwvirt.vmx.GCPhysShadowVmcs);
2908	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxRootMode);
2909	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInVmxNonRootMode);
2910	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fInterceptEvents);
2911	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fNmiUnblockingIret);
2912	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.Vmcs, sizeof(pGstCtx->hwvirt.vmx.Vmcs),
2913	0, g_aVmxHwvirtVmcs, NULL);
2914	SSMR3GetStructEx(pSSM, &pGstCtx->hwvirt.vmx.ShadowVmcs, sizeof(pGstCtx->hwvirt.vmx.ShadowVmcs),
2915	0, g_aVmxHwvirtVmcs, NULL);
2916	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmreadBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmreadBitmap));
2917	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abVmwriteBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abVmwriteBitmap));
2918	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aEntryMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aEntryMsrLoadArea));
2919	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrStoreArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrStoreArea));
2920	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.aExitMsrLoadArea[0], sizeof(pGstCtx->hwvirt.vmx.aExitMsrLoadArea));
2921	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abMsrBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abMsrBitmap));
2922	SSMR3GetMem(pSSM, &pGstCtx->hwvirt.vmx.abIoBitmap[0], sizeof(pGstCtx->hwvirt.vmx.abIoBitmap));
2923	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uFirstPauseLoopTick);
2924	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uPrevPauseTick);
2925	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.uEntryTick);
2926	SSMR3GetU16(pSSM, &pGstCtx->hwvirt.vmx.offVirtApicWrite);
2927	SSMR3GetBool(pSSM, &pGstCtx->hwvirt.vmx.fVirtNmiBlocking);
2928	SSMR3Skip(pSSM, sizeof(uint64_t)); /* Unused - used to be IA32_FEATURE_CONTROL, see @bugref{10106}. */
2929	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Basic);
2930	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.PinCtls.u);
2931	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls.u);
2932	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ProcCtls2.u);
2933	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.ExitCtls.u);
2934	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.EntryCtls.u);
2935	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TruePinCtls.u);
2936	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueProcCtls.u);
2937	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueEntryCtls.u);
2938	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.TrueExitCtls.u);
2939	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Misc);
2940	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed0);
2941	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr0Fixed1);
2942	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed0);
2943	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64Cr4Fixed1);
2944	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmcsEnum);
2945	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64VmFunc);
2946	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64EptVpidCaps);
2947	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2)
2948	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ProcCtls3);
2949	if (uVersion >= CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3)
2950	SSMR3GetU64(pSSM, &pGstCtx->hwvirt.vmx.Msrs.u64ExitCtls2);
2951	}
2952	}
2953	}
2954	else
2955	{
2956	/*
2957	* Pre XSAVE saved state.
2958	*/
2959	SSMR3GetStructEx(pSSM, &pGstCtx->XState.x87, sizeof(pGstCtx->XState.x87),
2960	fLoad \| SSMSTRUCT_FLAGS_NO_TAIL_MARKER, paCpumCtx1Fields, NULL);
2961	SSMR3GetStructEx(pSSM, pGstCtx, sizeof(*pGstCtx), fLoad \| SSMSTRUCT_FLAGS_NO_LEAD_MARKER, paCpumCtx2Fields, NULL);
2962	}
2963
2964	/*
2965	* Restore a couple of flags and the MSRs.
2966	*/
2967	uint32_t fIgnoredUsedFlags = 0;
2968	rc = SSMR3GetU32(pSSM, &fIgnoredUsedFlags); /* we're recalc the two relevant flags after loading state. */
2969	AssertRCReturn(rc, rc);
2970	SSMR3GetU32(pSSM, &pVCpu->cpum.s.fChanged);
2971
2972	rc = VINF_SUCCESS;
2973	if (uVersion > CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE)
2974	rc = SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], cbMsrs);
2975	else if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_0)
2976	{
2977	SSMR3GetMem(pSSM, &pVCpu->cpum.s.GuestMsrs.au64[0], 2 * sizeof(uint64_t)); /* Restore two MSRs. */
2978	rc = SSMR3Skip(pSSM, 62 * sizeof(uint64_t));
2979	}
2980	AssertRCReturn(rc, rc);
2981
2982	/* Deal with the reusing of reserved RFLAGS bits. */
2983	pGstCtx->rflags.uBoth \|= pVM->cpum.s.fReservedRFlagsCookie;
2984
2985	/* REM and other may have cleared must-be-one fields in DR6 and
2986	DR7, fix these. */
2987	pGstCtx->dr[6] &= ~(X86_DR6_RAZ_MASK \| X86_DR6_MBZ_MASK);
2988	pGstCtx->dr[6] \|= X86_DR6_RA1_MASK;
2989	pGstCtx->dr[7] &= ~(X86_DR7_RAZ_MASK \| X86_DR7_MBZ_MASK);
2990	pGstCtx->dr[7] \|= X86_DR7_RA1_MASK;
2991	}
2992
2993	/* Older states does not have the internal selector register flags
2994	and valid selector value. Supply those. */
2995	if (uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
2996	{
2997	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2998	{
2999	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3000	bool const fValid = true /!VM_IS_RAW_MODE_ENABLED(pVM)/
3001	\|\| ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3002	&& !(pVCpu->cpum.s.fChanged & CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID));
3003	PCPUMSELREG paSelReg = CPUMCTX_FIRST_SREG(&pVCpu->cpum.s.Guest);
3004	if (fValid)
3005	{
3006	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3007	{
3008	paSelReg[iSelReg].fFlags = CPUMSELREG_FLAGS_VALID;
3009	paSelReg[iSelReg].ValidSel = paSelReg[iSelReg].Sel;
3010	}
3011
3012	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3013	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3014	}
3015	else
3016	{
3017	for (uint32_t iSelReg = 0; iSelReg < X86_SREG_COUNT; iSelReg++)
3018	{
3019	paSelReg[iSelReg].fFlags = 0;
3020	paSelReg[iSelReg].ValidSel = 0;
3021	}
3022
3023	/* This might not be 104% correct, but I think it's close
3024	enough for all practical purposes... (REM always loaded
3025	LDTR registers.) */
3026	pVCpu->cpum.s.Guest.ldtr.fFlags = CPUMSELREG_FLAGS_VALID;
3027	pVCpu->cpum.s.Guest.ldtr.ValidSel = pVCpu->cpum.s.Guest.ldtr.Sel;
3028	}
3029	pVCpu->cpum.s.Guest.tr.fFlags = CPUMSELREG_FLAGS_VALID;
3030	pVCpu->cpum.s.Guest.tr.ValidSel = pVCpu->cpum.s.Guest.tr.Sel;
3031	}
3032	}
3033
3034	/* Clear CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID. */
3035	if ( uVersion > CPUM_SAVED_STATE_VERSION_VER3_2
3036	&& uVersion <= CPUM_SAVED_STATE_VERSION_MEM)
3037	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3038	{
3039	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3040	pVCpu->cpum.s.fChanged &= CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID;
3041	}
3042
3043	/*
3044	* A quick sanity check.
3045	*/
3046	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3047	{
3048	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3049	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.es.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3050	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.cs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3051	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ss.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3052	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.ds.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3053	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.fs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3054	AssertLogRelReturn(!(pVCpu->cpum.s.Guest.gs.fFlags & ~CPUMSELREG_FLAGS_VALID_MASK), VERR_SSM_UNEXPECTED_DATA);
3055	}
3056	}
3057
3058	pVM->cpum.s.fPendingRestore = false;
3059
3060	/*
3061	* Guest CPUIDs (and VMX MSR features).
3062	*/
3063	if (uVersion >= CPUM_SAVED_STATE_VERSION_VER3_2)
3064	{
3065	CPUMMSRS GuestMsrs;
3066	RT_ZERO(GuestMsrs);
3067
3068	CPUMFEATURES BaseFeatures;
3069	bool const fVmxGstFeat = pVM->cpum.s.GuestFeatures.fVmx;
3070	if (fVmxGstFeat)
3071	{
3072	/*
3073	* At this point the MSRs in the guest CPU-context are loaded with the guest VMX MSRs from the saved state.
3074	* However the VMX sub-features have not been exploded yet. So cache the base (host derived) VMX features
3075	* here so we can compare them for compatibility after exploding guest features.
3076	*/
3077	BaseFeatures = pVM->cpum.s.GuestFeatures;
3078
3079	/* Use the VMX MSR features from the saved state while exploding guest features. */
3080	GuestMsrs.hwvirt.vmx = pVM->apCpusR3[0]->cpum.s.Guest.hwvirt.vmx.Msrs;
3081	}
3082
3083	/* Load CPUID and explode guest features. */
3084	rc = cpumR3LoadCpuId(pVM, pSSM, uVersion, &GuestMsrs);
3085	if (fVmxGstFeat)
3086	{
3087	/*
3088	* Check if the exploded VMX features from the saved state are compatible with the host-derived features
3089	* we cached earlier (above). The is required if we use hardware-assisted nested-guest execution with
3090	* VMX features presented to the guest.
3091	*/
3092	bool const fIsCompat = cpumR3AreVmxCpuFeaturesCompatible(pVM, &BaseFeatures, &pVM->cpum.s.GuestFeatures);
3093	if (!fIsCompat)
3094	return VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO;
3095	}
3096	return rc;
3097	}
3098	return cpumR3LoadCpuIdPre32(pVM, pSSM, uVersion);
3099	}
3100
3101
3102	/**
3103	* @callback_method_impl{FNSSMINTLOADDONE}
3104	*/
3105	static DECLCALLBACK(int) cpumR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
3106	{
3107	if (RT_FAILURE(SSMR3HandleGetStatus(pSSM)))
3108	return VINF_SUCCESS;
3109
3110	/* just check this since we can. / /* @todo Add a SSM unit flag for indicating that it's mandatory during a restore. */
3111	if (pVM->cpum.s.fPendingRestore)
3112	{
3113	LogRel(("CPUM: Missing state!\n"));
3114	return VERR_INTERNAL_ERROR_2;
3115	}
3116
3117	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
3118	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3119	{
3120	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3121
3122	/* Notify PGM of the NXE states in case they've changed. */
3123	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pVCpu->cpum.s.Guest.msrEFER & MSR_K6_EFER_NXE));
3124
3125	/* During init. this is done in CPUMR3InitCompleted(). */
3126	if (fSupportsLongMode)
3127	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
3128
3129	/* Recalc the CPUM_USE_DEBUG_REGS_HYPER value. */
3130	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX);
3131	}
3132	return VINF_SUCCESS;
3133	}
3134
3135
3136	/**
3137	* Checks if the CPUM state restore is still pending.
3138	*
3139	* @returns true / false.
3140	* @param pVM The cross context VM structure.
3141	*/
3142	VMMDECL(bool) CPUMR3IsStateRestorePending(PVM pVM)
3143	{
3144	return pVM->cpum.s.fPendingRestore;
3145	}
3146
3147
3148	/**
3149	* Formats the EFLAGS value into mnemonics.
3150	*
3151	* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
3152	* @param efl The EFLAGS value with both guest hardware and VBox
3153	* internal bits included.
3154	*/
3155	static void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
3156	{
3157	/*
3158	* Format the flags.
3159	*/
3160	static const struct
3161	{
3162	const char pszSet; const char pszClear; uint32_t fFlag;
3163	} s_aFlags[] =
3164	{
3165	{ "vip",NULL, X86_EFL_VIP },
3166	{ "vif",NULL, X86_EFL_VIF },
3167	{ "ac", NULL, X86_EFL_AC },
3168	{ "vm", NULL, X86_EFL_VM },
3169	{ "rf", NULL, X86_EFL_RF },
3170	{ "nt", NULL, X86_EFL_NT },
3171	{ "ov", "nv", X86_EFL_OF },
3172	{ "dn", "up", X86_EFL_DF },
3173	{ "ei", "di", X86_EFL_IF },
3174	{ "tf", NULL, X86_EFL_TF },
3175	{ "nt", "pl", X86_EFL_SF },
3176	{ "nz", "zr", X86_EFL_ZF },
3177	{ "ac", "na", X86_EFL_AF },
3178	{ "po", "pe", X86_EFL_PF },
3179	{ "cy", "nc", X86_EFL_CF },
3180	{ "inh-ss", NULL, CPUMCTX_INHIBIT_SHADOW_SS },
3181	{ "inh-sti", NULL, CPUMCTX_INHIBIT_SHADOW_STI },
3182	{ "inh-nmi", NULL, CPUMCTX_INHIBIT_NMI },
3183	};
3184	char *psz = pszEFlags;
3185	for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
3186	{
3187	const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
3188	if (pszAdd)
3189	{
3190	strcpy(psz, pszAdd);
3191	psz += strlen(pszAdd);
3192	*psz++ = ' ';
3193	}
3194	}
3195	psz[-1] = '\0';
3196	}
3197
3198
3199	/**
3200	* Formats a full register dump.
3201	*
3202	* @param pVM The cross context VM structure.
3203	* @param pCtx The context to format.
3204	* @param pHlp Output functions.
3205	* @param enmType The dump type.
3206	* @param pszPrefix Register name prefix.
3207	*/
3208	static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
3209	{
3210	NOREF(pVM);
3211
3212	/*
3213	* Format the EFLAGS.
3214	*/
3215	char szEFlags[80];
3216	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->eflags.uBoth);
3217
3218	/*
3219	* Format the registers.
3220	*/
3221	uint32_t const efl = pCtx->eflags.u;
3222	switch (enmType)
3223	{
3224	case CPUMDUMPTYPE_TERSE:
3225	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3226	pHlp->pfnPrintf(pHlp,
3227	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3228	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3229	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3230	"%sr14=%016RX64 %sr15=%016RX64\n"
3231	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3232	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3233	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3234	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3235	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3236	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3237	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3238	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3239	else
3240	pHlp->pfnPrintf(pHlp,
3241	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3242	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3243	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
3244	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3245	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3246	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3247	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, efl);
3248	break;
3249
3250	case CPUMDUMPTYPE_DEFAULT:
3251	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3252	pHlp->pfnPrintf(pHlp,
3253	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3254	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3255	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3256	"%sr14=%016RX64 %sr15=%016RX64\n"
3257	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3258	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3259	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
3260	,
3261	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3262	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3263	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3264	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3265	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3266	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3267	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3268	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3269	else
3270	pHlp->pfnPrintf(pHlp,
3271	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3272	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3273	"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
3274	"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
3275	,
3276	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3277	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3278	pszPrefix, pCtx->cs.Sel, pszPrefix, pCtx->ss.Sel, pszPrefix, pCtx->ds.Sel, pszPrefix, pCtx->es.Sel,
3279	pszPrefix, pCtx->fs.Sel, pszPrefix, pCtx->gs.Sel, pszPrefix, pCtx->tr.Sel, pszPrefix, efl,
3280	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3281	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->ldtr.Sel);
3282	break;
3283
3284	case CPUMDUMPTYPE_VERBOSE:
3285	if (CPUMIsGuestIn64BitCodeEx(pCtx))
3286	pHlp->pfnPrintf(pHlp,
3287	"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
3288	"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
3289	"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
3290	"%sr14=%016RX64 %sr15=%016RX64\n"
3291	"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
3292	"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3293	"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3294	"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3295	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3296	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3297	"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
3298	"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
3299	"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
3300	"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
3301	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3302	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3303	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3304	"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
3305	,
3306	pszPrefix, pCtx->rax, pszPrefix, pCtx->rbx, pszPrefix, pCtx->rcx, pszPrefix, pCtx->rdx, pszPrefix, pCtx->rsi, pszPrefix, pCtx->rdi,
3307	pszPrefix, pCtx->r8, pszPrefix, pCtx->r9, pszPrefix, pCtx->r10, pszPrefix, pCtx->r11, pszPrefix, pCtx->r12, pszPrefix, pCtx->r13,
3308	pszPrefix, pCtx->r14, pszPrefix, pCtx->r15,
3309	pszPrefix, pCtx->rip, pszPrefix, pCtx->rsp, pszPrefix, pCtx->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3310	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u,
3311	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u,
3312	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u,
3313	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u,
3314	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u,
3315	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u,
3316	pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3317	pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1], pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3318	pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5], pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3319	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3320	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3321	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3322	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3323	else
3324	pHlp->pfnPrintf(pHlp,
3325	"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
3326	"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
3327	"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
3328	"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
3329	"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
3330	"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
3331	"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
3332	"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
3333	"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
3334	"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3335	"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
3336	"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
3337	,
3338	pszPrefix, pCtx->eax, pszPrefix, pCtx->ebx, pszPrefix, pCtx->ecx, pszPrefix, pCtx->edx, pszPrefix, pCtx->esi, pszPrefix, pCtx->edi,
3339	pszPrefix, pCtx->eip, pszPrefix, pCtx->esp, pszPrefix, pCtx->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
3340	pszPrefix, pCtx->cs.Sel, pCtx->cs.u64Base, pCtx->cs.u32Limit, pCtx->cs.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
3341	pszPrefix, pCtx->ds.Sel, pCtx->ds.u64Base, pCtx->ds.u32Limit, pCtx->ds.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
3342	pszPrefix, pCtx->es.Sel, pCtx->es.u64Base, pCtx->es.u32Limit, pCtx->es.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
3343	pszPrefix, pCtx->fs.Sel, pCtx->fs.u64Base, pCtx->fs.u32Limit, pCtx->fs.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
3344	pszPrefix, pCtx->gs.Sel, pCtx->gs.u64Base, pCtx->gs.u32Limit, pCtx->gs.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
3345	pszPrefix, pCtx->ss.Sel, pCtx->ss.u64Base, pCtx->ss.u32Limit, pCtx->ss.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
3346	pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
3347	pszPrefix, pCtx->ldtr.Sel, pCtx->ldtr.u64Base, pCtx->ldtr.u32Limit, pCtx->ldtr.Attr.u,
3348	pszPrefix, pCtx->tr.Sel, pCtx->tr.u64Base, pCtx->tr.u32Limit, pCtx->tr.Attr.u,
3349	pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
3350
3351	pHlp->pfnPrintf(pHlp, "%sxcr=%016RX64 %sxcr1=%016RX64 %sxss=%016RX64 (fXStateMask=%016RX64)\n",
3352	pszPrefix, pCtx->aXcr[0], pszPrefix, pCtx->aXcr[1],
3353	pszPrefix, UINT64_C(0) /** @todo XSS */, pCtx->fXStateMask);
3354	{
3355	PX86FXSTATE pFpuCtx = &pCtx->XState.x87;
3356	pHlp->pfnPrintf(pHlp,
3357	"%sFCW=%04x %sFSW=%04x %sFTW=%04x %sFOP=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
3358	"%sFPUIP=%08x %sCS=%04x %sRsrvd1=%04x %sFPUDP=%08x %sDS=%04x %sRsvrd2=%04x\n"
3359	,
3360	pszPrefix, pFpuCtx->FCW, pszPrefix, pFpuCtx->FSW, pszPrefix, pFpuCtx->FTW, pszPrefix, pFpuCtx->FOP,
3361	pszPrefix, pFpuCtx->MXCSR, pszPrefix, pFpuCtx->MXCSR_MASK,
3362	pszPrefix, pFpuCtx->FPUIP, pszPrefix, pFpuCtx->CS, pszPrefix, pFpuCtx->Rsrvd1,
3363	pszPrefix, pFpuCtx->FPUDP, pszPrefix, pFpuCtx->DS, pszPrefix, pFpuCtx->Rsrvd2
3364	);
3365	/*
3366	* The FSAVE style memory image contains ST(0)-ST(7) at increasing addresses,
3367	* not (FP)R0-7 as Intel SDM suggests.
3368	*/
3369	unsigned iShift = (pFpuCtx->FSW >> 11) & 7;
3370	for (unsigned iST = 0; iST < RT_ELEMENTS(pFpuCtx->aRegs); iST++)
3371	{
3372	unsigned iFPR = (iST + iShift) % RT_ELEMENTS(pFpuCtx->aRegs);
3373	unsigned uTag = (pFpuCtx->FTW >> (2 * iFPR)) & 3;
3374	char chSign = pFpuCtx->aRegs[iST].au16[4] & 0x8000 ? '-' : '+';
3375	unsigned iInteger = (unsigned)(pFpuCtx->aRegs[iST].au64[0] >> 63);
3376	uint64_t u64Fraction = pFpuCtx->aRegs[iST].au64[0] & UINT64_C(0x7fffffffffffffff);
3377	int iExponent = pFpuCtx->aRegs[iST].au16[4] & 0x7fff;
3378	iExponent -= 16383; /* subtract bias */
3379	/** @todo This isn't entirenly correct and needs more work! */
3380	pHlp->pfnPrintf(pHlp,
3381	"%sST(%u)=%sFPR%u={%04RX16'%08RX32'%08RX32} t%d %c%u.%022llu * 2 ^ %d (*)",
3382	pszPrefix, iST, pszPrefix, iFPR,
3383	pFpuCtx->aRegs[iST].au16[4], pFpuCtx->aRegs[iST].au32[1], pFpuCtx->aRegs[iST].au32[0],
3384	uTag, chSign, iInteger, u64Fraction, iExponent);
3385	if (pFpuCtx->aRegs[iST].au16[5] \|\| pFpuCtx->aRegs[iST].au16[6] \|\| pFpuCtx->aRegs[iST].au16[7])
3386	pHlp->pfnPrintf(pHlp, " res={%04RX16,%04RX16,%04RX16}\n",
3387	pFpuCtx->aRegs[iST].au16[5], pFpuCtx->aRegs[iST].au16[6], pFpuCtx->aRegs[iST].au16[7]);
3388	else
3389	pHlp->pfnPrintf(pHlp, "\n");
3390	}
3391
3392	/* XMM/YMM/ZMM registers. */
3393	if (pCtx->fXStateMask & XSAVE_C_YMM)
3394	{
3395	PCX86XSAVEYMMHI pYmmHiCtx = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_YMM_BIT, PCX86XSAVEYMMHI);
3396	if (!(pCtx->fXStateMask & XSAVE_C_ZMM_HI256))
3397	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3398	pHlp->pfnPrintf(pHlp, "%sYMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3399	pszPrefix, i, i < 10 ? " " : "",
3400	pYmmHiCtx->aYmmHi[i].au32[3],
3401	pYmmHiCtx->aYmmHi[i].au32[2],
3402	pYmmHiCtx->aYmmHi[i].au32[1],
3403	pYmmHiCtx->aYmmHi[i].au32[0],
3404	pFpuCtx->aXMM[i].au32[3],
3405	pFpuCtx->aXMM[i].au32[2],
3406	pFpuCtx->aXMM[i].au32[1],
3407	pFpuCtx->aXMM[i].au32[0]);
3408	else
3409	{
3410	PCX86XSAVEZMMHI256 pZmmHi256 = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_HI256_BIT, PCX86XSAVEZMMHI256);
3411	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3412	pHlp->pfnPrintf(pHlp,
3413	"%sZMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3414	pszPrefix, i, i < 10 ? " " : "",
3415	pZmmHi256->aHi256Regs[i].au32[7],
3416	pZmmHi256->aHi256Regs[i].au32[6],
3417	pZmmHi256->aHi256Regs[i].au32[5],
3418	pZmmHi256->aHi256Regs[i].au32[4],
3419	pZmmHi256->aHi256Regs[i].au32[3],
3420	pZmmHi256->aHi256Regs[i].au32[2],
3421	pZmmHi256->aHi256Regs[i].au32[1],
3422	pZmmHi256->aHi256Regs[i].au32[0],
3423	pYmmHiCtx->aYmmHi[i].au32[3],
3424	pYmmHiCtx->aYmmHi[i].au32[2],
3425	pYmmHiCtx->aYmmHi[i].au32[1],
3426	pYmmHiCtx->aYmmHi[i].au32[0],
3427	pFpuCtx->aXMM[i].au32[3],
3428	pFpuCtx->aXMM[i].au32[2],
3429	pFpuCtx->aXMM[i].au32[1],
3430	pFpuCtx->aXMM[i].au32[0]);
3431
3432	PCX86XSAVEZMM16HI pZmm16Hi = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_ZMM_16HI_BIT, PCX86XSAVEZMM16HI);
3433	for (unsigned i = 0; i < RT_ELEMENTS(pZmm16Hi->aRegs); i++)
3434	pHlp->pfnPrintf(pHlp,
3435	"%sZMM%u=%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32''%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32'%08RX32\n",
3436	pszPrefix, i + 16,
3437	pZmm16Hi->aRegs[i].au32[15],
3438	pZmm16Hi->aRegs[i].au32[14],
3439	pZmm16Hi->aRegs[i].au32[13],
3440	pZmm16Hi->aRegs[i].au32[12],
3441	pZmm16Hi->aRegs[i].au32[11],
3442	pZmm16Hi->aRegs[i].au32[10],
3443	pZmm16Hi->aRegs[i].au32[9],
3444	pZmm16Hi->aRegs[i].au32[8],
3445	pZmm16Hi->aRegs[i].au32[7],
3446	pZmm16Hi->aRegs[i].au32[6],
3447	pZmm16Hi->aRegs[i].au32[5],
3448	pZmm16Hi->aRegs[i].au32[4],
3449	pZmm16Hi->aRegs[i].au32[3],
3450	pZmm16Hi->aRegs[i].au32[2],
3451	pZmm16Hi->aRegs[i].au32[1],
3452	pZmm16Hi->aRegs[i].au32[0]);
3453	}
3454	}
3455	else
3456	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->aXMM); i++)
3457	pHlp->pfnPrintf(pHlp,
3458	i & 1
3459	? "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32\n"
3460	: "%sXMM%u%s=%08RX32'%08RX32'%08RX32'%08RX32 ",
3461	pszPrefix, i, i < 10 ? " " : "",
3462	pFpuCtx->aXMM[i].au32[3],
3463	pFpuCtx->aXMM[i].au32[2],
3464	pFpuCtx->aXMM[i].au32[1],
3465	pFpuCtx->aXMM[i].au32[0]);
3466
3467	if (pCtx->fXStateMask & XSAVE_C_OPMASK)
3468	{
3469	PCX86XSAVEOPMASK pOpMask = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_OPMASK_BIT, PCX86XSAVEOPMASK);
3470	for (unsigned i = 0; i < RT_ELEMENTS(pOpMask->aKRegs); i += 4)
3471	pHlp->pfnPrintf(pHlp, "%sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64 %sK%u=%016RX64\n",
3472	pszPrefix, i + 0, pOpMask->aKRegs[i + 0],
3473	pszPrefix, i + 1, pOpMask->aKRegs[i + 1],
3474	pszPrefix, i + 2, pOpMask->aKRegs[i + 2],
3475	pszPrefix, i + 3, pOpMask->aKRegs[i + 3]);
3476	}
3477
3478	if (pCtx->fXStateMask & XSAVE_C_BNDREGS)
3479	{
3480	PCX86XSAVEBNDREGS pBndRegs = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDREGS_BIT, PCX86XSAVEBNDREGS);
3481	for (unsigned i = 0; i < RT_ELEMENTS(pBndRegs->aRegs); i += 2)
3482	pHlp->pfnPrintf(pHlp, "%sBNDREG%u=%016RX64/%016RX64 %sBNDREG%u=%016RX64/%016RX64\n",
3483	pszPrefix, i, pBndRegs->aRegs[i].uLowerBound, pBndRegs->aRegs[i].uUpperBound,
3484	pszPrefix, i + 1, pBndRegs->aRegs[i + 1].uLowerBound, pBndRegs->aRegs[i + 1].uUpperBound);
3485	}
3486
3487	if (pCtx->fXStateMask & XSAVE_C_BNDCSR)
3488	{
3489	PCX86XSAVEBNDCFG pBndCfg = CPUMCTX_XSAVE_C_PTR(pCtx, XSAVE_C_BNDCSR_BIT, PCX86XSAVEBNDCFG);
3490	pHlp->pfnPrintf(pHlp, "%sBNDCFG.CONFIG=%016RX64 %sBNDCFG.STATUS=%016RX64\n",
3491	pszPrefix, pBndCfg->fConfig, pszPrefix, pBndCfg->fStatus);
3492	}
3493
3494	for (unsigned i = 0; i < RT_ELEMENTS(pFpuCtx->au32RsrvdRest); i++)
3495	if (pFpuCtx->au32RsrvdRest[i])
3496	pHlp->pfnPrintf(pHlp, "%sRsrvdRest[%u]=%RX32 (offset=%#x)\n",
3497	pszPrefix, i, pFpuCtx->au32RsrvdRest[i], RT_UOFFSETOF_DYN(X86FXSTATE, au32RsrvdRest[i]) );
3498	}
3499
3500	pHlp->pfnPrintf(pHlp,
3501	"%sEFER =%016RX64\n"
3502	"%sPAT =%016RX64\n"
3503	"%sSTAR =%016RX64\n"
3504	"%sCSTAR =%016RX64\n"
3505	"%sLSTAR =%016RX64\n"
3506	"%sSFMASK =%016RX64\n"
3507	"%sKERNELGSBASE =%016RX64\n",
3508	pszPrefix, pCtx->msrEFER,
3509	pszPrefix, pCtx->msrPAT,
3510	pszPrefix, pCtx->msrSTAR,
3511	pszPrefix, pCtx->msrCSTAR,
3512	pszPrefix, pCtx->msrLSTAR,
3513	pszPrefix, pCtx->msrSFMASK,
3514	pszPrefix, pCtx->msrKERNELGSBASE);
3515
3516	if (CPUMIsGuestInPAEModeEx(pCtx))
3517	for (unsigned i = 0; i < RT_ELEMENTS(pCtx->aPaePdpes); i++)
3518	pHlp->pfnPrintf(pHlp, "%sPAE PDPTE %u =%016RX64\n", pszPrefix, i, pCtx->aPaePdpes[i]);
3519	break;
3520	}
3521	}
3522
3523
3524	/**
3525	* Display all cpu states and any other cpum info.
3526	*
3527	* @param pVM The cross context VM structure.
3528	* @param pHlp The info helper functions.
3529	* @param pszArgs Arguments, ignored.
3530	*/
3531	static DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3532	{
3533	cpumR3InfoGuest(pVM, pHlp, pszArgs);
3534	cpumR3InfoGuestInstr(pVM, pHlp, pszArgs);
3535	cpumR3InfoGuestHwvirt(pVM, pHlp, pszArgs);
3536	cpumR3InfoHyper(pVM, pHlp, pszArgs);
3537	cpumR3InfoHost(pVM, pHlp, pszArgs);
3538	}
3539
3540
3541	/**
3542	* Parses the info argument.
3543	*
3544	* The argument starts with 'verbose', 'terse' or 'default' and then
3545	* continues with the comment string.
3546	*
3547	* @param pszArgs The pointer to the argument string.
3548	* @param penmType Where to store the dump type request.
3549	* @param ppszComment Where to store the pointer to the comment string.
3550	*/
3551	static void cpumR3InfoParseArg(const char pszArgs, CPUMDUMPTYPE penmType, const char **ppszComment)
3552	{
3553	if (!pszArgs)
3554	{
3555	*penmType = CPUMDUMPTYPE_DEFAULT;
3556	*ppszComment = "";
3557	}
3558	else
3559	{
3560	if (!strncmp(pszArgs, RT_STR_TUPLE("verbose")))
3561	{
3562	pszArgs += 7;
3563	*penmType = CPUMDUMPTYPE_VERBOSE;
3564	}
3565	else if (!strncmp(pszArgs, RT_STR_TUPLE("terse")))
3566	{
3567	pszArgs += 5;
3568	*penmType = CPUMDUMPTYPE_TERSE;
3569	}
3570	else if (!strncmp(pszArgs, RT_STR_TUPLE("default")))
3571	{
3572	pszArgs += 7;
3573	*penmType = CPUMDUMPTYPE_DEFAULT;
3574	}
3575	else
3576	*penmType = CPUMDUMPTYPE_DEFAULT;
3577	*ppszComment = RTStrStripL(pszArgs);
3578	}
3579	}
3580
3581
3582	/**
3583	* Display the guest cpu state.
3584	*
3585	* @param pVM The cross context VM structure.
3586	* @param pHlp The info helper functions.
3587	* @param pszArgs Arguments.
3588	*/
3589	static DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3590	{
3591	CPUMDUMPTYPE enmType;
3592	const char *pszComment;
3593	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
3594
3595	PVMCPU pVCpu = VMMGetCpu(pVM);
3596	if (!pVCpu)
3597	pVCpu = pVM->apCpusR3[0];
3598
3599	pHlp->pfnPrintf(pHlp, "Guest CPUM (VCPU %d) state: %s\n", pVCpu->idCpu, pszComment);
3600
3601	PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
3602	cpumR3InfoOne(pVM, pCtx, pHlp, enmType, "");
3603	}
3604
3605
3606	/**
3607	* Displays an SVM VMCB control area.
3608	*
3609	* @param pHlp The info helper functions.
3610	* @param pVmcbCtrl Pointer to a SVM VMCB controls area.
3611	* @param pszPrefix Caller specified string prefix.
3612	*/
3613	static void cpumR3InfoSvmVmcbCtrl(PCDBGFINFOHLP pHlp, PCSVMVMCBCTRL pVmcbCtrl, const char *pszPrefix)
3614	{
3615	AssertReturnVoid(pHlp);
3616	AssertReturnVoid(pVmcbCtrl);
3617
3618	pHlp->pfnPrintf(pHlp, "%sCRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdCRx);
3619	pHlp->pfnPrintf(pHlp, "%sCRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrCRx);
3620	pHlp->pfnPrintf(pHlp, "%sDRX-read intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptRdDRx);
3621	pHlp->pfnPrintf(pHlp, "%sDRX-write intercepts = %#RX16\n", pszPrefix, pVmcbCtrl->u16InterceptWrDRx);
3622	pHlp->pfnPrintf(pHlp, "%sException intercepts = %#RX32\n", pszPrefix, pVmcbCtrl->u32InterceptXcpt);
3623	pHlp->pfnPrintf(pHlp, "%sControl intercepts = %#RX64\n", pszPrefix, pVmcbCtrl->u64InterceptCtrl);
3624	pHlp->pfnPrintf(pHlp, "%sPause-filter threshold = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterThreshold);
3625	pHlp->pfnPrintf(pHlp, "%sPause-filter count = %#RX16\n", pszPrefix, pVmcbCtrl->u16PauseFilterCount);
3626	pHlp->pfnPrintf(pHlp, "%sIOPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64IOPMPhysAddr);
3627	pHlp->pfnPrintf(pHlp, "%sMSRPM bitmap physaddr = %#RX64\n", pszPrefix, pVmcbCtrl->u64MSRPMPhysAddr);
3628	pHlp->pfnPrintf(pHlp, "%sTSC offset = %#RX64\n", pszPrefix, pVmcbCtrl->u64TSCOffset);
3629	pHlp->pfnPrintf(pHlp, "%sTLB Control\n", pszPrefix);
3630	pHlp->pfnPrintf(pHlp, " %sASID = %#RX32\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u32ASID);
3631	pHlp->pfnPrintf(pHlp, " %sTLB-flush type = %u\n", pszPrefix, pVmcbCtrl->TLBCtrl.n.u8TLBFlush);
3632	pHlp->pfnPrintf(pHlp, "%sInterrupt Control\n", pszPrefix);
3633	pHlp->pfnPrintf(pHlp, " %sVTPR = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VTPR, pVmcbCtrl->IntCtrl.n.u8VTPR);
3634	pHlp->pfnPrintf(pHlp, " %sVIRQ (Pending) = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIrqPending);
3635	pHlp->pfnPrintf(pHlp, " %sVINTR vector = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u8VIntrVector);
3636	pHlp->pfnPrintf(pHlp, " %sVGIF = %u\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGif);
3637	pHlp->pfnPrintf(pHlp, " %sVINTR priority = %#RX8\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u4VIntrPrio);
3638	pHlp->pfnPrintf(pHlp, " %sIgnore TPR = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1IgnoreTPR);
3639	pHlp->pfnPrintf(pHlp, " %sVINTR masking = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VIntrMasking);
3640	pHlp->pfnPrintf(pHlp, " %sVGIF enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1VGifEnable);
3641	pHlp->pfnPrintf(pHlp, " %sAVIC enable = %RTbool\n", pszPrefix, pVmcbCtrl->IntCtrl.n.u1AvicEnable);
3642	pHlp->pfnPrintf(pHlp, "%sInterrupt Shadow\n", pszPrefix);
3643	pHlp->pfnPrintf(pHlp, " %sInterrupt shadow = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1IntShadow);
3644	pHlp->pfnPrintf(pHlp, " %sGuest-interrupt Mask = %RTbool\n", pszPrefix, pVmcbCtrl->IntShadow.n.u1GuestIntMask);
3645	pHlp->pfnPrintf(pHlp, "%sExit Code = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitCode);
3646	pHlp->pfnPrintf(pHlp, "%sEXITINFO1 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo1);
3647	pHlp->pfnPrintf(pHlp, "%sEXITINFO2 = %#RX64\n", pszPrefix, pVmcbCtrl->u64ExitInfo2);
3648	pHlp->pfnPrintf(pHlp, "%sExit Interrupt Info\n", pszPrefix);
3649	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1Valid);
3650	pHlp->pfnPrintf(pHlp, " %sVector = %#RX8 (%u)\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u8Vector, pVmcbCtrl->ExitIntInfo.n.u8Vector);
3651	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u3Type);
3652	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u1ErrorCodeValid);
3653	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->ExitIntInfo.n.u32ErrorCode);
3654	pHlp->pfnPrintf(pHlp, "%sNested paging and SEV\n", pszPrefix);
3655	pHlp->pfnPrintf(pHlp, " %sNested paging = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1NestedPaging);
3656	pHlp->pfnPrintf(pHlp, " %sSEV (Secure Encrypted VM) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1Sev);
3657	pHlp->pfnPrintf(pHlp, " %sSEV-ES (Encrypted State) = %RTbool\n", pszPrefix, pVmcbCtrl->NestedPagingCtrl.n.u1SevEs);
3658	pHlp->pfnPrintf(pHlp, "%sEvent Inject\n", pszPrefix);
3659	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1Valid);
3660	pHlp->pfnPrintf(pHlp, " %sVector = %#RX32 (%u)\n", pszPrefix, pVmcbCtrl->EventInject.n.u8Vector, pVmcbCtrl->EventInject.n.u8Vector);
3661	pHlp->pfnPrintf(pHlp, " %sType = %u\n", pszPrefix, pVmcbCtrl->EventInject.n.u3Type);
3662	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, pVmcbCtrl->EventInject.n.u1ErrorCodeValid);
3663	pHlp->pfnPrintf(pHlp, " %sError-code = %#RX32\n", pszPrefix, pVmcbCtrl->EventInject.n.u32ErrorCode);
3664	pHlp->pfnPrintf(pHlp, "%sNested-paging CR3 = %#RX64\n", pszPrefix, pVmcbCtrl->u64NestedPagingCR3);
3665	pHlp->pfnPrintf(pHlp, "%sLBR Virtualization\n", pszPrefix);
3666	pHlp->pfnPrintf(pHlp, " %sLBR virt = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1LbrVirt);
3667	pHlp->pfnPrintf(pHlp, " %sVirt. VMSAVE/VMLOAD = %RTbool\n", pszPrefix, pVmcbCtrl->LbrVirt.n.u1VirtVmsaveVmload);
3668	pHlp->pfnPrintf(pHlp, "%sVMCB Clean Bits = %#RX32\n", pszPrefix, pVmcbCtrl->u32VmcbCleanBits);
3669	pHlp->pfnPrintf(pHlp, "%sNext-RIP = %#RX64\n", pszPrefix, pVmcbCtrl->u64NextRIP);
3670	pHlp->pfnPrintf(pHlp, "%sInstruction bytes fetched = %u\n", pszPrefix, pVmcbCtrl->cbInstrFetched);
3671	pHlp->pfnPrintf(pHlp, "%sInstruction bytes = %.*Rhxs\n", pszPrefix, sizeof(pVmcbCtrl->abInstr), pVmcbCtrl->abInstr);
3672	pHlp->pfnPrintf(pHlp, "%sAVIC\n", pszPrefix);
3673	pHlp->pfnPrintf(pHlp, " %sBar addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBar.n.u40Addr);
3674	pHlp->pfnPrintf(pHlp, " %sBacking page addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicBackingPagePtr.n.u40Addr);
3675	pHlp->pfnPrintf(pHlp, " %sLogical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicLogicalTablePtr.n.u40Addr);
3676	pHlp->pfnPrintf(pHlp, " %sPhysical table addr = %#RX64\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u40Addr);
3677	pHlp->pfnPrintf(pHlp, " %sLast guest core Id = %u\n", pszPrefix, pVmcbCtrl->AvicPhysicalTablePtr.n.u8LastGuestCoreId);
3678	}
3679
3680
3681	/**
3682	* Helper for dumping the SVM VMCB selector registers.
3683	*
3684	* @param pHlp The info helper functions.
3685	* @param pSel Pointer to the SVM selector register.
3686	* @param pszName Name of the selector.
3687	* @param pszPrefix Caller specified string prefix.
3688	*/
3689	DECLINLINE(void) cpumR3InfoSvmVmcbSelReg(PCDBGFINFOHLP pHlp, PCSVMSELREG pSel, const char pszName, const char pszPrefix)
3690	{
3691	/* The string width of 4 used below is to handle 'LDTR'. Change later if longer register names are used. */
3692	pHlp->pfnPrintf(pHlp, "%s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", pszPrefix,
3693	pszName, pSel->u16Sel, pSel->u64Base, pSel->u32Limit, pSel->u16Attr);
3694	}
3695
3696
3697	/**
3698	* Helper for dumping the SVM VMCB GDTR/IDTR registers.
3699	*
3700	* @param pHlp The info helper functions.
3701	* @param pXdtr Pointer to the descriptor table register.
3702	* @param pszName Name of the descriptor table register.
3703	* @param pszPrefix Caller specified string prefix.
3704	*/
3705	DECLINLINE(void) cpumR3InfoSvmVmcbXdtr(PCDBGFINFOHLP pHlp, PCSVMXDTR pXdtr, const char pszName, const char pszPrefix)
3706	{
3707	/* The string width of 4 used below is to cover 'GDTR', 'IDTR'. Change later if longer register names are used. */
3708	pHlp->pfnPrintf(pHlp, "%s%-4s = %016RX64:%04x\n", pszPrefix, pszName, pXdtr->u64Base, pXdtr->u32Limit);
3709	}
3710
3711
3712	/**
3713	* Displays an SVM VMCB state-save area.
3714	*
3715	* @param pHlp The info helper functions.
3716	* @param pVmcbStateSave Pointer to a SVM VMCB controls area.
3717	* @param pszPrefix Caller specified string prefix.
3718	*/
3719	static void cpumR3InfoSvmVmcbStateSave(PCDBGFINFOHLP pHlp, PCSVMVMCBSTATESAVE pVmcbStateSave, const char *pszPrefix)
3720	{
3721	AssertReturnVoid(pHlp);
3722	AssertReturnVoid(pVmcbStateSave);
3723
3724	char szEFlags[80];
3725	cpumR3InfoFormatFlags(&szEFlags[0], pVmcbStateSave->u64RFlags);
3726
3727	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->CS, "CS", pszPrefix);
3728	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->SS, "SS", pszPrefix);
3729	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->ES, "ES", pszPrefix);
3730	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->DS, "DS", pszPrefix);
3731	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->FS, "FS", pszPrefix);
3732	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->GS, "GS", pszPrefix);
3733	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->LDTR, "LDTR", pszPrefix);
3734	cpumR3InfoSvmVmcbSelReg(pHlp, &pVmcbStateSave->TR, "TR", pszPrefix);
3735	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->GDTR, "GDTR", pszPrefix);
3736	cpumR3InfoSvmVmcbXdtr(pHlp, &pVmcbStateSave->IDTR, "IDTR", pszPrefix);
3737	pHlp->pfnPrintf(pHlp, "%sCPL = %u\n", pszPrefix, pVmcbStateSave->u8CPL);
3738	pHlp->pfnPrintf(pHlp, "%sEFER = %#RX64\n", pszPrefix, pVmcbStateSave->u64EFER);
3739	pHlp->pfnPrintf(pHlp, "%sCR4 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR4);
3740	pHlp->pfnPrintf(pHlp, "%sCR3 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR3);
3741	pHlp->pfnPrintf(pHlp, "%sCR0 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR0);
3742	pHlp->pfnPrintf(pHlp, "%sDR7 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR7);
3743	pHlp->pfnPrintf(pHlp, "%sDR6 = %#RX64\n", pszPrefix, pVmcbStateSave->u64DR6);
3744	pHlp->pfnPrintf(pHlp, "%sRFLAGS = %#RX64 %31s\n", pszPrefix, pVmcbStateSave->u64RFlags, szEFlags);
3745	pHlp->pfnPrintf(pHlp, "%sRIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RIP);
3746	pHlp->pfnPrintf(pHlp, "%sRSP = %#RX64\n", pszPrefix, pVmcbStateSave->u64RSP);
3747	pHlp->pfnPrintf(pHlp, "%sRAX = %#RX64\n", pszPrefix, pVmcbStateSave->u64RAX);
3748	pHlp->pfnPrintf(pHlp, "%sSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64STAR);
3749	pHlp->pfnPrintf(pHlp, "%sLSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64LSTAR);
3750	pHlp->pfnPrintf(pHlp, "%sCSTAR = %#RX64\n", pszPrefix, pVmcbStateSave->u64CSTAR);
3751	pHlp->pfnPrintf(pHlp, "%sSFMASK = %#RX64\n", pszPrefix, pVmcbStateSave->u64SFMASK);
3752	pHlp->pfnPrintf(pHlp, "%sKERNELGSBASE = %#RX64\n", pszPrefix, pVmcbStateSave->u64KernelGSBase);
3753	pHlp->pfnPrintf(pHlp, "%sSysEnter CS = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterCS);
3754	pHlp->pfnPrintf(pHlp, "%sSysEnter EIP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterEIP);
3755	pHlp->pfnPrintf(pHlp, "%sSysEnter ESP = %#RX64\n", pszPrefix, pVmcbStateSave->u64SysEnterESP);
3756	pHlp->pfnPrintf(pHlp, "%sCR2 = %#RX64\n", pszPrefix, pVmcbStateSave->u64CR2);
3757	pHlp->pfnPrintf(pHlp, "%sPAT = %#RX64\n", pszPrefix, pVmcbStateSave->u64PAT);
3758	pHlp->pfnPrintf(pHlp, "%sDBGCTL = %#RX64\n", pszPrefix, pVmcbStateSave->u64DBGCTL);
3759	pHlp->pfnPrintf(pHlp, "%sBR_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_FROM);
3760	pHlp->pfnPrintf(pHlp, "%sBR_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64BR_TO);
3761	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_FROM = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPFROM);
3762	pHlp->pfnPrintf(pHlp, "%sLASTXCPT_TO = %#RX64\n", pszPrefix, pVmcbStateSave->u64LASTEXCPTO);
3763	}
3764
3765
3766	/**
3767	* Displays a virtual-VMCS.
3768	*
3769	* @param pVCpu The cross context virtual CPU structure.
3770	* @param pHlp The info helper functions.
3771	* @param pVmcs Pointer to a virtual VMCS.
3772	* @param pszPrefix Caller specified string prefix.
3773	*/
3774	static void cpumR3InfoVmxVmcs(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, PCVMXVVMCS pVmcs, const char *pszPrefix)
3775	{
3776	AssertReturnVoid(pHlp);
3777	AssertReturnVoid(pVmcs);
3778
3779	/* The string width of -4 used in the macros below to cover 'LDTR', 'GDTR', 'IDTR. */
3780	#define CPUMVMX_DUMP_HOST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3781	do { \
3782	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64}\n", \
3783	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Host##a_Seg##Base.u); \
3784	} while (0)
3785
3786	#define CPUMVMX_DUMP_HOST_FS_GS_TR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3787	do { \
3788	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64}\n", \
3789	(a_pszPrefix), (a_SegName), (a_pVmcs)->Host##a_Seg, (a_pVmcs)->u64Host##a_Seg##Base.u); \
3790	} while (0)
3791
3792	#define CPUMVMX_DUMP_GUEST_SEGREG(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3793	do { \
3794	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {%04x base=%016RX64 limit=%08x flags=%04x}\n", \
3795	(a_pszPrefix), (a_SegName), (a_pVmcs)->Guest##a_Seg, (a_pVmcs)->u64Guest##a_Seg##Base.u, \
3796	(a_pVmcs)->u32Guest##a_Seg##Limit, (a_pVmcs)->u32Guest##a_Seg##Attr); \
3797	} while (0)
3798
3799	#define CPUMVMX_DUMP_GUEST_XDTR(a_pHlp, a_pVmcs, a_Seg, a_SegName, a_pszPrefix) \
3800	do { \
3801	(a_pHlp)->pfnPrintf((a_pHlp), " %s%-4s = {base=%016RX64 limit=%08x}\n", \
3802	(a_pszPrefix), (a_SegName), (a_pVmcs)->u64Guest##a_Seg##Base.u, (a_pVmcs)->u32Guest##a_Seg##Limit); \
3803	} while (0)
3804
3805	/* Header. */
3806	{
3807	pHlp->pfnPrintf(pHlp, "%sHeader:\n", pszPrefix);
3808	pHlp->pfnPrintf(pHlp, " %sVMCS revision id = %#RX32\n", pszPrefix, pVmcs->u32VmcsRevId);
3809	pHlp->pfnPrintf(pHlp, " %sVMX-abort id = %#RX32 (%s)\n", pszPrefix, pVmcs->enmVmxAbort, VMXGetAbortDesc(pVmcs->enmVmxAbort));
3810	pHlp->pfnPrintf(pHlp, " %sVMCS state = %#x (%s)\n", pszPrefix, pVmcs->fVmcsState, VMXGetVmcsStateDesc(pVmcs->fVmcsState));
3811	}
3812
3813	/* Control fields. */
3814	{
3815	/* 16-bit. */
3816	pHlp->pfnPrintf(pHlp, "%sControl:\n", pszPrefix);
3817	pHlp->pfnPrintf(pHlp, " %sVPID = %#RX16\n", pszPrefix, pVmcs->u16Vpid);
3818	pHlp->pfnPrintf(pHlp, " %sPosted intr notify vector = %#RX16\n", pszPrefix, pVmcs->u16PostIntNotifyVector);
3819	pHlp->pfnPrintf(pHlp, " %sEPTP index = %#RX16\n", pszPrefix, pVmcs->u16EptpIndex);
3820	pHlp->pfnPrintf(pHlp, " %sHLAT prefix size = %#RX16\n", pszPrefix, pVmcs->u16HlatPrefixSize);
3821
3822	/* 32-bit. */
3823	pHlp->pfnPrintf(pHlp, " %sPin ctls = %#RX32\n", pszPrefix, pVmcs->u32PinCtls);
3824	pHlp->pfnPrintf(pHlp, " %sProcessor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls);
3825	pHlp->pfnPrintf(pHlp, " %sSecondary processor ctls = %#RX32\n", pszPrefix, pVmcs->u32ProcCtls2);
3826	pHlp->pfnPrintf(pHlp, " %sVM-exit ctls = %#RX32\n", pszPrefix, pVmcs->u32ExitCtls);
3827	pHlp->pfnPrintf(pHlp, " %sVM-entry ctls = %#RX32\n", pszPrefix, pVmcs->u32EntryCtls);
3828	pHlp->pfnPrintf(pHlp, " %sException bitmap = %#RX32\n", pszPrefix, pVmcs->u32XcptBitmap);
3829	pHlp->pfnPrintf(pHlp, " %sPage-fault mask = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMask);
3830	pHlp->pfnPrintf(pHlp, " %sPage-fault match = %#RX32\n", pszPrefix, pVmcs->u32XcptPFMatch);
3831	pHlp->pfnPrintf(pHlp, " %sCR3-target count = %RU32\n", pszPrefix, pVmcs->u32Cr3TargetCount);
3832	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrStoreCount);
3833	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load count = %RU32\n", pszPrefix, pVmcs->u32ExitMsrLoadCount);
3834	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load count = %RU32\n", pszPrefix, pVmcs->u32EntryMsrLoadCount);
3835	pHlp->pfnPrintf(pHlp, " %sVM-entry interruption info = %#RX32\n", pszPrefix, pVmcs->u32EntryIntInfo);
3836	{
3837	uint32_t const fInfo = pVmcs->u32EntryIntInfo;
3838	uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(fInfo);
3839	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_VALID(fInfo));
3840	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetEntryIntInfoTypeDesc(uType));
3841	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_ENTRY_INT_INFO_VECTOR(fInfo));
3842	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
3843	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
3844	}
3845	pHlp->pfnPrintf(pHlp, " %sVM-entry xcpt error-code = %#RX32\n", pszPrefix, pVmcs->u32EntryXcptErrCode);
3846	pHlp->pfnPrintf(pHlp, " %sVM-entry instr length = %u byte(s)\n", pszPrefix, pVmcs->u32EntryInstrLen);
3847	pHlp->pfnPrintf(pHlp, " %sTPR threshold = %#RX32\n", pszPrefix, pVmcs->u32TprThreshold);
3848	pHlp->pfnPrintf(pHlp, " %sPLE gap = %#RX32\n", pszPrefix, pVmcs->u32PleGap);
3849	pHlp->pfnPrintf(pHlp, " %sPLE window = %#RX32\n", pszPrefix, pVmcs->u32PleWindow);
3850
3851	/* 64-bit. */
3852	pHlp->pfnPrintf(pHlp, " %sIO-bitmap A addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapA.u);
3853	pHlp->pfnPrintf(pHlp, " %sIO-bitmap B addr = %#RX64\n", pszPrefix, pVmcs->u64AddrIoBitmapB.u);
3854	pHlp->pfnPrintf(pHlp, " %sMSR-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrMsrBitmap.u);
3855	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR store addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrStore.u);
3856	pHlp->pfnPrintf(pHlp, " %sVM-exit MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrExitMsrLoad.u);
3857	pHlp->pfnPrintf(pHlp, " %sVM-entry MSR load addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEntryMsrLoad.u);
3858	pHlp->pfnPrintf(pHlp, " %sExecutive VMCS ptr = %#RX64\n", pszPrefix, pVmcs->u64ExecVmcsPtr.u);
3859	pHlp->pfnPrintf(pHlp, " %sPML addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPml.u);
3860	pHlp->pfnPrintf(pHlp, " %sTSC offset = %#RX64\n", pszPrefix, pVmcs->u64TscOffset.u);
3861	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVirtApic.u);
3862	pHlp->pfnPrintf(pHlp, " %sAPIC-access addr = %#RX64\n", pszPrefix, pVmcs->u64AddrApicAccess.u);
3863	pHlp->pfnPrintf(pHlp, " %sPosted-intr desc addr = %#RX64\n", pszPrefix, pVmcs->u64AddrPostedIntDesc.u);
3864	pHlp->pfnPrintf(pHlp, " %sVM-functions control = %#RX64\n", pszPrefix, pVmcs->u64VmFuncCtls.u);
3865	pHlp->pfnPrintf(pHlp, " %sEPTP ptr = %#RX64\n", pszPrefix, pVmcs->u64EptPtr.u);
3866	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 0 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap0.u);
3867	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 1 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap1.u);
3868	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 2 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap2.u);
3869	pHlp->pfnPrintf(pHlp, " %sEOI-exit bitmap 3 = %#RX64\n", pszPrefix, pVmcs->u64EoiExitBitmap3.u);
3870	pHlp->pfnPrintf(pHlp, " %sEPTP-list addr = %#RX64\n", pszPrefix, pVmcs->u64AddrEptpList.u);
3871	pHlp->pfnPrintf(pHlp, " %sVMREAD-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmreadBitmap.u);
3872	pHlp->pfnPrintf(pHlp, " %sVMWRITE-bitmap addr = %#RX64\n", pszPrefix, pVmcs->u64AddrVmwriteBitmap.u);
3873	pHlp->pfnPrintf(pHlp, " %sVirt-Xcpt info addr = %#RX64\n", pszPrefix, pVmcs->u64AddrXcptVeInfo.u);
3874	pHlp->pfnPrintf(pHlp, " %sXSS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64XssExitBitmap.u);
3875	pHlp->pfnPrintf(pHlp, " %sENCLS-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclsExitBitmap.u);
3876	pHlp->pfnPrintf(pHlp, " %sSPP-table ptr = %#RX64\n", pszPrefix, pVmcs->u64SppTablePtr.u);
3877	pHlp->pfnPrintf(pHlp, " %sTSC multiplier = %#RX64\n", pszPrefix, pVmcs->u64TscMultiplier.u);
3878	pHlp->pfnPrintf(pHlp, " %sTertiary processor ctls = %#RX64\n", pszPrefix, pVmcs->u64ProcCtls3.u);
3879	pHlp->pfnPrintf(pHlp, " %sENCLV-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64EnclvExitBitmap.u);
3880	pHlp->pfnPrintf(pHlp, " %sPCONFIG-exiting bitmap = %#RX64\n", pszPrefix, pVmcs->u64PconfigExitBitmap.u);
3881	pHlp->pfnPrintf(pHlp, " %sHLAT ptr = %#RX64\n", pszPrefix, pVmcs->u64HlatPtr.u);
3882	pHlp->pfnPrintf(pHlp, " %sSecondary VM-exit controls = %#RX64\n", pszPrefix, pVmcs->u64ExitCtls2.u);
3883
3884	/* Natural width. */
3885	pHlp->pfnPrintf(pHlp, " %sCR0 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr0Mask.u);
3886	pHlp->pfnPrintf(pHlp, " %sCR4 guest/host mask = %#RX64\n", pszPrefix, pVmcs->u64Cr4Mask.u);
3887	pHlp->pfnPrintf(pHlp, " %sCR0 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr0ReadShadow.u);
3888	pHlp->pfnPrintf(pHlp, " %sCR4 read shadow = %#RX64\n", pszPrefix, pVmcs->u64Cr4ReadShadow.u);
3889	pHlp->pfnPrintf(pHlp, " %sCR3-target 0 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target0.u);
3890	pHlp->pfnPrintf(pHlp, " %sCR3-target 1 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target1.u);
3891	pHlp->pfnPrintf(pHlp, " %sCR3-target 2 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target2.u);
3892	pHlp->pfnPrintf(pHlp, " %sCR3-target 3 = %#RX64\n", pszPrefix, pVmcs->u64Cr3Target3.u);
3893	}
3894
3895	/* Guest state. */
3896	{
3897	char szEFlags[80];
3898	cpumR3InfoFormatFlags(&szEFlags[0], pVmcs->u64GuestRFlags.u);
3899	pHlp->pfnPrintf(pHlp, "%sGuest state:\n", pszPrefix);
3900
3901	/* 16-bit. */
3902	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Cs, "CS", pszPrefix);
3903	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ss, "SS", pszPrefix);
3904	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Es, "ES", pszPrefix);
3905	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ds, "DS", pszPrefix);
3906	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Fs, "FS", pszPrefix);
3907	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Gs, "GS", pszPrefix);
3908	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Ldtr, "LDTR", pszPrefix);
3909	CPUMVMX_DUMP_GUEST_SEGREG(pHlp, pVmcs, Tr, "TR", pszPrefix);
3910	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3911	CPUMVMX_DUMP_GUEST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3912	pHlp->pfnPrintf(pHlp, " %sInterrupt status = %#RX16\n", pszPrefix, pVmcs->u16GuestIntStatus);
3913	pHlp->pfnPrintf(pHlp, " %sPML index = %#RX16\n", pszPrefix, pVmcs->u16PmlIndex);
3914
3915	/* 32-bit. */
3916	pHlp->pfnPrintf(pHlp, " %sInterruptibility state = %#RX32\n", pszPrefix, pVmcs->u32GuestIntrState);
3917	pHlp->pfnPrintf(pHlp, " %sActivity state = %#RX32\n", pszPrefix, pVmcs->u32GuestActivityState);
3918	pHlp->pfnPrintf(pHlp, " %sSMBASE = %#RX32\n", pszPrefix, pVmcs->u32GuestSmBase);
3919	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32GuestSysenterCS);
3920	pHlp->pfnPrintf(pHlp, " %sVMX-preemption timer value = %#RX32\n", pszPrefix, pVmcs->u32PreemptTimer);
3921
3922	/* 64-bit. */
3923	pHlp->pfnPrintf(pHlp, " %sVMCS link ptr = %#RX64\n", pszPrefix, pVmcs->u64VmcsLinkPtr.u);
3924	pHlp->pfnPrintf(pHlp, " %sDBGCTL = %#RX64\n", pszPrefix, pVmcs->u64GuestDebugCtlMsr.u);
3925	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64GuestPatMsr.u);
3926	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64GuestEferMsr.u);
3927	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64GuestPerfGlobalCtlMsr.u);
3928	pHlp->pfnPrintf(pHlp, " %sPDPTE 0 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte0.u);
3929	pHlp->pfnPrintf(pHlp, " %sPDPTE 1 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte1.u);
3930	pHlp->pfnPrintf(pHlp, " %sPDPTE 2 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte2.u);
3931	pHlp->pfnPrintf(pHlp, " %sPDPTE 3 = %#RX64\n", pszPrefix, pVmcs->u64GuestPdpte3.u);
3932	pHlp->pfnPrintf(pHlp, " %sBNDCFGS = %#RX64\n", pszPrefix, pVmcs->u64GuestBndcfgsMsr.u);
3933	pHlp->pfnPrintf(pHlp, " %sRTIT_CTL = %#RX64\n", pszPrefix, pVmcs->u64GuestRtitCtlMsr.u);
3934	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64GuestPkrsMsr.u);
3935
3936	/* Natural width. */
3937	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr0.u);
3938	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr3.u);
3939	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64GuestCr4.u);
3940	pHlp->pfnPrintf(pHlp, " %sDR7 = %#RX64\n", pszPrefix, pVmcs->u64GuestDr7.u);
3941	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64GuestRsp.u);
3942	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64GuestRip.u);
3943	pHlp->pfnPrintf(pHlp, " %sRFLAGS = %#RX64 %31s\n",pszPrefix, pVmcs->u64GuestRFlags.u, szEFlags);
3944	pHlp->pfnPrintf(pHlp, " %sPending debug xcpts = %#RX64\n", pszPrefix, pVmcs->u64GuestPendingDbgXcpts.u);
3945	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEsp.u);
3946	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64GuestSysenterEip.u);
3947	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64GuestSCetMsr.u);
3948	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64GuestSsp.u);
3949	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64GuestIntrSspTableAddrMsr.u);
3950	}
3951
3952	/* Host state. */
3953	{
3954	pHlp->pfnPrintf(pHlp, "%sHost state:\n", pszPrefix);
3955
3956	/* 16-bit. */
3957	pHlp->pfnPrintf(pHlp, " %sCS = %#RX16\n", pszPrefix, pVmcs->HostCs);
3958	pHlp->pfnPrintf(pHlp, " %sSS = %#RX16\n", pszPrefix, pVmcs->HostSs);
3959	pHlp->pfnPrintf(pHlp, " %sDS = %#RX16\n", pszPrefix, pVmcs->HostDs);
3960	pHlp->pfnPrintf(pHlp, " %sES = %#RX16\n", pszPrefix, pVmcs->HostEs);
3961	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Fs, "FS", pszPrefix);
3962	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Gs, "GS", pszPrefix);
3963	CPUMVMX_DUMP_HOST_FS_GS_TR(pHlp, pVmcs, Tr, "TR", pszPrefix);
3964	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Gdtr, "GDTR", pszPrefix);
3965	CPUMVMX_DUMP_HOST_XDTR(pHlp, pVmcs, Idtr, "IDTR", pszPrefix);
3966
3967	/* 32-bit. */
3968	pHlp->pfnPrintf(pHlp, " %sSysEnter CS = %#RX32\n", pszPrefix, pVmcs->u32HostSysenterCs);
3969
3970	/* 64-bit. */
3971	pHlp->pfnPrintf(pHlp, " %sEFER = %#RX64\n", pszPrefix, pVmcs->u64HostEferMsr.u);
3972	pHlp->pfnPrintf(pHlp, " %sPAT = %#RX64\n", pszPrefix, pVmcs->u64HostPatMsr.u);
3973	pHlp->pfnPrintf(pHlp, " %sPERFGLOBALCTRL = %#RX64\n", pszPrefix, pVmcs->u64HostPerfGlobalCtlMsr.u);
3974	pHlp->pfnPrintf(pHlp, " %sPKRS = %#RX64\n", pszPrefix, pVmcs->u64HostPkrsMsr.u);
3975
3976	/* Natural width. */
3977	pHlp->pfnPrintf(pHlp, " %sCR0 = %#RX64\n", pszPrefix, pVmcs->u64HostCr0.u);
3978	pHlp->pfnPrintf(pHlp, " %sCR3 = %#RX64\n", pszPrefix, pVmcs->u64HostCr3.u);
3979	pHlp->pfnPrintf(pHlp, " %sCR4 = %#RX64\n", pszPrefix, pVmcs->u64HostCr4.u);
3980	pHlp->pfnPrintf(pHlp, " %sSysEnter ESP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEsp.u);
3981	pHlp->pfnPrintf(pHlp, " %sSysEnter EIP = %#RX64\n", pszPrefix, pVmcs->u64HostSysenterEip.u);
3982	pHlp->pfnPrintf(pHlp, " %sRSP = %#RX64\n", pszPrefix, pVmcs->u64HostRsp.u);
3983	pHlp->pfnPrintf(pHlp, " %sRIP = %#RX64\n", pszPrefix, pVmcs->u64HostRip.u);
3984	pHlp->pfnPrintf(pHlp, " %sS_CET = %#RX64\n", pszPrefix, pVmcs->u64HostSCetMsr.u);
3985	pHlp->pfnPrintf(pHlp, " %sSSP = %#RX64\n", pszPrefix, pVmcs->u64HostSsp.u);
3986	pHlp->pfnPrintf(pHlp, " %sINTERRUPT_SSP_TABLE_ADDR = %#RX64\n", pszPrefix, pVmcs->u64HostIntrSspTableAddrMsr.u);
3987	}
3988
3989	/* Read-only fields. */
3990	{
3991	pHlp->pfnPrintf(pHlp, "%sRead-only data fields:\n", pszPrefix);
3992
3993	/* 16-bit (none currently). */
3994
3995	/* 32-bit. */
3996	pHlp->pfnPrintf(pHlp, " %sExit reason = %u (%s)\n", pszPrefix, pVmcs->u32RoExitReason, HMGetVmxExitName(pVmcs->u32RoExitReason));
3997	pHlp->pfnPrintf(pHlp, " %sExit qualification = %#RX64\n", pszPrefix, pVmcs->u64RoExitQual.u);
3998	pHlp->pfnPrintf(pHlp, " %sVM-instruction error = %#RX32\n", pszPrefix, pVmcs->u32RoVmInstrError);
3999	pHlp->pfnPrintf(pHlp, " %sVM-exit intr info = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntInfo);
4000	{
4001	uint32_t const fInfo = pVmcs->u32RoExitIntInfo;
4002	uint8_t const uType = VMX_EXIT_INT_INFO_TYPE(fInfo);
4003	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_VALID(fInfo));
4004	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetExitIntInfoTypeDesc(uType));
4005	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_EXIT_INT_INFO_VECTOR(fInfo));
4006	pHlp->pfnPrintf(pHlp, " %sNMI-unblocking-IRET = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(fInfo));
4007	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(fInfo));
4008	}
4009	pHlp->pfnPrintf(pHlp, " %sVM-exit intr error-code = %#RX32\n", pszPrefix, pVmcs->u32RoExitIntErrCode);
4010	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring info = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringInfo);
4011	{
4012	uint32_t const fInfo = pVmcs->u32RoIdtVectoringInfo;
4013	uint8_t const uType = VMX_IDT_VECTORING_INFO_TYPE(fInfo);
4014	pHlp->pfnPrintf(pHlp, " %sValid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_VALID(fInfo));
4015	pHlp->pfnPrintf(pHlp, " %sType = %#x (%s)\n", pszPrefix, uType, VMXGetIdtVectoringInfoTypeDesc(uType));
4016	pHlp->pfnPrintf(pHlp, " %sVector = %#x\n", pszPrefix, VMX_IDT_VECTORING_INFO_VECTOR(fInfo));
4017	pHlp->pfnPrintf(pHlp, " %sError-code valid = %RTbool\n", pszPrefix, VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(fInfo));
4018	}
4019	pHlp->pfnPrintf(pHlp, " %sIDT-vectoring error-code = %#RX32\n", pszPrefix, pVmcs->u32RoIdtVectoringErrCode);
4020	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction length = %u byte(s)\n", pszPrefix, pVmcs->u32RoExitInstrLen);
4021	pHlp->pfnPrintf(pHlp, " %sVM-exit instruction info = %#RX64\n", pszPrefix, pVmcs->u32RoExitInstrInfo);
4022
4023	/* 64-bit. */
4024	pHlp->pfnPrintf(pHlp, " %sGuest-physical addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestPhysAddr.u);
4025
4026	/* Natural width. */
4027	pHlp->pfnPrintf(pHlp, " %sI/O RCX = %#RX64\n", pszPrefix, pVmcs->u64RoIoRcx.u);
4028	pHlp->pfnPrintf(pHlp, " %sI/O RSI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRsi.u);
4029	pHlp->pfnPrintf(pHlp, " %sI/O RDI = %#RX64\n", pszPrefix, pVmcs->u64RoIoRdi.u);
4030	pHlp->pfnPrintf(pHlp, " %sI/O RIP = %#RX64\n", pszPrefix, pVmcs->u64RoIoRip.u);
4031	pHlp->pfnPrintf(pHlp, " %sGuest-linear addr = %#RX64\n", pszPrefix, pVmcs->u64RoGuestLinearAddr.u);
4032	}
4033
4034	#ifdef DEBUG_ramshankar
4035	if (pVmcs->u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
4036	{
4037	void *pvPage = RTMemTmpAllocZ(VMX_V_VIRT_APIC_SIZE);
4038	Assert(pvPage);
4039	RTGCPHYS const GCPhysVirtApic = pVmcs->u64AddrVirtApic.u;
4040	int rc = PGMPhysSimpleReadGCPhys(pVCpu->CTX_SUFF(pVM), pvPage, GCPhysVirtApic, VMX_V_VIRT_APIC_SIZE);
4041	if (RT_SUCCESS(rc))
4042	{
4043	pHlp->pfnPrintf(pHlp, " %sVirtual-APIC page\n", pszPrefix);
4044	pHlp->pfnPrintf(pHlp, "%.*Rhxs\n", VMX_V_VIRT_APIC_SIZE, pvPage);
4045	pHlp->pfnPrintf(pHlp, "\n");
4046	}
4047	RTMemTmpFree(pvPage);
4048	}
4049	#else
4050	NOREF(pVCpu);
4051	#endif
4052
4053	#undef CPUMVMX_DUMP_HOST_XDTR
4054	#undef CPUMVMX_DUMP_HOST_FS_GS_TR
4055	#undef CPUMVMX_DUMP_GUEST_SEGREG
4056	#undef CPUMVMX_DUMP_GUEST_XDTR
4057	}
4058
4059
4060	/**
4061	* Display the guest's hardware-virtualization cpu state.
4062	*
4063	* @param pVM The cross context VM structure.
4064	* @param pHlp The info helper functions.
4065	* @param pszArgs Arguments, ignored.
4066	*/
4067	static DECLCALLBACK(void) cpumR3InfoGuestHwvirt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4068	{
4069	RT_NOREF(pszArgs);
4070
4071	PVMCPU pVCpu = VMMGetCpu(pVM);
4072	if (!pVCpu)
4073	pVCpu = pVM->apCpusR3[0];
4074
4075	PCCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
4076	bool const fSvm = pVM->cpum.s.GuestFeatures.fSvm;
4077	bool const fVmx = pVM->cpum.s.GuestFeatures.fVmx;
4078
4079	pHlp->pfnPrintf(pHlp, "VCPU[%u] hardware virtualization state:\n", pVCpu->idCpu);
4080	pHlp->pfnPrintf(pHlp, "fSavedInhibit = %#RX32\n", pCtx->hwvirt.fSavedInhibit);
4081	pHlp->pfnPrintf(pHlp, "In nested-guest hwvirt mode = %RTbool\n", CPUMIsGuestInNestedHwvirtMode(pCtx));
4082
4083	if (fSvm)
4084	{
4085	pHlp->pfnPrintf(pHlp, "SVM hwvirt state:\n");
4086	pHlp->pfnPrintf(pHlp, " fGif = %RTbool\n", pCtx->hwvirt.fGif);
4087
4088	char szEFlags[80];
4089	cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
4090	pHlp->pfnPrintf(pHlp, " uMsrHSavePa = %#RX64\n", pCtx->hwvirt.svm.uMsrHSavePa);
4091	pHlp->pfnPrintf(pHlp, " GCPhysVmcb = %#RGp\n", pCtx->hwvirt.svm.GCPhysVmcb);
4092	pHlp->pfnPrintf(pHlp, " VmcbCtrl:\n");
4093	cpumR3InfoSvmVmcbCtrl(pHlp, &pCtx->hwvirt.svm.Vmcb.ctrl, " " /* pszPrefix */);
4094	pHlp->pfnPrintf(pHlp, " VmcbStateSave:\n");
4095	cpumR3InfoSvmVmcbStateSave(pHlp, &pCtx->hwvirt.svm.Vmcb.guest, " " /* pszPrefix */);
4096	pHlp->pfnPrintf(pHlp, " HostState:\n");
4097	pHlp->pfnPrintf(pHlp, " uEferMsr = %#RX64\n", pCtx->hwvirt.svm.HostState.uEferMsr);
4098	pHlp->pfnPrintf(pHlp, " uCr0 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr0);
4099	pHlp->pfnPrintf(pHlp, " uCr4 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr4);
4100	pHlp->pfnPrintf(pHlp, " uCr3 = %#RX64\n", pCtx->hwvirt.svm.HostState.uCr3);
4101	pHlp->pfnPrintf(pHlp, " uRip = %#RX64\n", pCtx->hwvirt.svm.HostState.uRip);
4102	pHlp->pfnPrintf(pHlp, " uRsp = %#RX64\n", pCtx->hwvirt.svm.HostState.uRsp);
4103	pHlp->pfnPrintf(pHlp, " uRax = %#RX64\n", pCtx->hwvirt.svm.HostState.uRax);
4104	pHlp->pfnPrintf(pHlp, " rflags = %#RX64 %31s\n", pCtx->hwvirt.svm.HostState.rflags.u64, szEFlags);
4105	PCCPUMSELREG pSelEs = &pCtx->hwvirt.svm.HostState.es;
4106	pHlp->pfnPrintf(pHlp, " es = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4107	pSelEs->Sel, pSelEs->u64Base, pSelEs->u32Limit, pSelEs->Attr.u);
4108	PCCPUMSELREG pSelCs = &pCtx->hwvirt.svm.HostState.cs;
4109	pHlp->pfnPrintf(pHlp, " cs = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4110	pSelCs->Sel, pSelCs->u64Base, pSelCs->u32Limit, pSelCs->Attr.u);
4111	PCCPUMSELREG pSelSs = &pCtx->hwvirt.svm.HostState.ss;
4112	pHlp->pfnPrintf(pHlp, " ss = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4113	pSelSs->Sel, pSelSs->u64Base, pSelSs->u32Limit, pSelSs->Attr.u);
4114	PCCPUMSELREG pSelDs = &pCtx->hwvirt.svm.HostState.ds;
4115	pHlp->pfnPrintf(pHlp, " ds = {%04x base=%016RX64 limit=%08x flags=%08x}\n",
4116	pSelDs->Sel, pSelDs->u64Base, pSelDs->u32Limit, pSelDs->Attr.u);
4117	pHlp->pfnPrintf(pHlp, " gdtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.gdtr.pGdt,
4118	pCtx->hwvirt.svm.HostState.gdtr.cbGdt);
4119	pHlp->pfnPrintf(pHlp, " idtr = %016RX64:%04x\n", pCtx->hwvirt.svm.HostState.idtr.pIdt,
4120	pCtx->hwvirt.svm.HostState.idtr.cbIdt);
4121	pHlp->pfnPrintf(pHlp, " cPauseFilter = %RU16\n", pCtx->hwvirt.svm.cPauseFilter);
4122	pHlp->pfnPrintf(pHlp, " cPauseFilterThreshold = %RU32\n", pCtx->hwvirt.svm.cPauseFilterThreshold);
4123	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %u\n", pCtx->hwvirt.svm.fInterceptEvents);
4124	}
4125	else if (fVmx)
4126	{
4127	pHlp->pfnPrintf(pHlp, "VMX hwvirt state:\n");
4128	pHlp->pfnPrintf(pHlp, " GCPhysVmxon = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmxon);
4129	pHlp->pfnPrintf(pHlp, " GCPhysVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysVmcs);
4130	pHlp->pfnPrintf(pHlp, " GCPhysShadowVmcs = %#RGp\n", pCtx->hwvirt.vmx.GCPhysShadowVmcs);
4131	pHlp->pfnPrintf(pHlp, " enmDiag = %u (%s)\n", pCtx->hwvirt.vmx.enmDiag, HMGetVmxDiagDesc(pCtx->hwvirt.vmx.enmDiag));
4132	pHlp->pfnPrintf(pHlp, " uDiagAux = %#RX64\n", pCtx->hwvirt.vmx.uDiagAux);
4133	pHlp->pfnPrintf(pHlp, " enmAbort = %u (%s)\n", pCtx->hwvirt.vmx.enmAbort, VMXGetAbortDesc(pCtx->hwvirt.vmx.enmAbort));
4134	pHlp->pfnPrintf(pHlp, " uAbortAux = %u (%#x)\n", pCtx->hwvirt.vmx.uAbortAux, pCtx->hwvirt.vmx.uAbortAux);
4135	pHlp->pfnPrintf(pHlp, " fInVmxRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxRootMode);
4136	pHlp->pfnPrintf(pHlp, " fInVmxNonRootMode = %RTbool\n", pCtx->hwvirt.vmx.fInVmxNonRootMode);
4137	pHlp->pfnPrintf(pHlp, " fInterceptEvents = %RTbool\n", pCtx->hwvirt.vmx.fInterceptEvents);
4138	pHlp->pfnPrintf(pHlp, " fNmiUnblockingIret = %RTbool\n", pCtx->hwvirt.vmx.fNmiUnblockingIret);
4139	pHlp->pfnPrintf(pHlp, " uFirstPauseLoopTick = %RX64\n", pCtx->hwvirt.vmx.uFirstPauseLoopTick);
4140	pHlp->pfnPrintf(pHlp, " uPrevPauseTick = %RX64\n", pCtx->hwvirt.vmx.uPrevPauseTick);
4141	pHlp->pfnPrintf(pHlp, " uEntryTick = %RX64\n", pCtx->hwvirt.vmx.uEntryTick);
4142	pHlp->pfnPrintf(pHlp, " offVirtApicWrite = %#RX16\n", pCtx->hwvirt.vmx.offVirtApicWrite);
4143	pHlp->pfnPrintf(pHlp, " fVirtNmiBlocking = %RTbool\n", pCtx->hwvirt.vmx.fVirtNmiBlocking);
4144	pHlp->pfnPrintf(pHlp, " VMCS cache:\n");
4145	cpumR3InfoVmxVmcs(pVCpu, pHlp, &pCtx->hwvirt.vmx.Vmcs, " " /* pszPrefix */);
4146	}
4147	else
4148	pHlp->pfnPrintf(pHlp, "Hwvirt state disabled.\n");
4149
4150	#undef CPUMHWVIRTDUMP_NONE
4151	#undef CPUMHWVIRTDUMP_COMMON
4152	#undef CPUMHWVIRTDUMP_SVM
4153	#undef CPUMHWVIRTDUMP_VMX
4154	#undef CPUMHWVIRTDUMP_LAST
4155	#undef CPUMHWVIRTDUMP_ALL
4156	}
4157
4158	/**
4159	* Display the current guest instruction
4160	*
4161	* @param pVM The cross context VM structure.
4162	* @param pHlp The info helper functions.
4163	* @param pszArgs Arguments, ignored.
4164	*/
4165	static DECLCALLBACK(void) cpumR3InfoGuestInstr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4166	{
4167	NOREF(pszArgs);
4168
4169	PVMCPU pVCpu = VMMGetCpu(pVM);
4170	if (!pVCpu)
4171	pVCpu = pVM->apCpusR3[0];
4172
4173	char szInstruction[256];
4174	szInstruction[0] = '\0';
4175	DBGFR3DisasInstrCurrent(pVCpu, szInstruction, sizeof(szInstruction));
4176	pHlp->pfnPrintf(pHlp, "\nCPUM%u: %s\n\n", pVCpu->idCpu, szInstruction);
4177	}
4178
4179
4180	/**
4181	* Display the hypervisor cpu state.
4182	*
4183	* @param pVM The cross context VM structure.
4184	* @param pHlp The info helper functions.
4185	* @param pszArgs Arguments, ignored.
4186	*/
4187	static DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4188	{
4189	PVMCPU pVCpu = VMMGetCpu(pVM);
4190	if (!pVCpu)
4191	pVCpu = pVM->apCpusR3[0];
4192
4193	CPUMDUMPTYPE enmType;
4194	const char *pszComment;
4195	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4196	pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
4197
4198	pHlp->pfnPrintf(pHlp,
4199	".dr0=%016RX64 .dr1=%016RX64 .dr2=%016RX64 .dr3=%016RX64\n"
4200	".dr4=%016RX64 .dr5=%016RX64 .dr6=%016RX64 .dr7=%016RX64\n",
4201	pVCpu->cpum.s.Hyper.dr[0], pVCpu->cpum.s.Hyper.dr[1], pVCpu->cpum.s.Hyper.dr[2], pVCpu->cpum.s.Hyper.dr[3],
4202	pVCpu->cpum.s.Hyper.dr[4], pVCpu->cpum.s.Hyper.dr[5], pVCpu->cpum.s.Hyper.dr[6], pVCpu->cpum.s.Hyper.dr[7]);
4203	pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
4204	}
4205
4206
4207	/**
4208	* Display the host cpu state.
4209	*
4210	* @param pVM The cross context VM structure.
4211	* @param pHlp The info helper functions.
4212	* @param pszArgs Arguments, ignored.
4213	*/
4214	static DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
4215	{
4216	CPUMDUMPTYPE enmType;
4217	const char *pszComment;
4218	cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
4219	pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
4220
4221	PVMCPU pVCpu = VMMGetCpu(pVM);
4222	if (!pVCpu)
4223	pVCpu = pVM->apCpusR3[0];
4224	PCPUMHOSTCTX pCtx = &pVCpu->cpum.s.Host;
4225
4226	/*
4227	* Format the EFLAGS.
4228	*/
4229	uint64_t efl = pCtx->rflags;
4230	char szEFlags[80];
4231	cpumR3InfoFormatFlags(&szEFlags[0], efl);
4232
4233	/*
4234	* Format the registers.
4235	*/
4236	pHlp->pfnPrintf(pHlp,
4237	"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
4238	"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
4239	"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
4240	" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
4241	"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
4242	"r14=%016RX64 r15=%016RX64\n"
4243	"iopl=%d %31s\n"
4244	"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
4245	"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
4246	"cr4=%016RX64 ldtr=%04x tr=%04x\n"
4247	"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
4248	"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
4249	"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
4250	"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
4251	"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
4252	,
4253	/pCtx->rax,/ pCtx->rbx, /*pCtx->rcx,
4254	pCtx->rdx,*/ pCtx->rsi, pCtx->rdi,
4255	/pCtx->rip,/ pCtx->rsp, pCtx->rbp,
4256	/pCtx->r8, pCtx->r9,/ pCtx->r10,
4257	pCtx->r11, pCtx->r12, pCtx->r13,
4258	pCtx->r14, pCtx->r15,
4259	X86_EFL_GET_IOPL(efl), szEFlags,
4260	pCtx->cs, pCtx->ds, pCtx->es, pCtx->fs, pCtx->gs, efl,
4261	pCtx->cr0, /pCtx->cr2,/ pCtx->cr3,
4262	pCtx->cr4, pCtx->ldtr, pCtx->tr,
4263	pCtx->dr0, pCtx->dr1, pCtx->dr2,
4264	pCtx->dr3, pCtx->dr6, pCtx->dr7,
4265	pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
4266	pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
4267	pCtx->FSbase, pCtx->GSbase, pCtx->efer);
4268	}
4269
4270	/**
4271	* Structure used when disassembling and instructions in DBGF.
4272	* This is used so the reader function can get the stuff it needs.
4273	*/
4274	typedef struct CPUMDISASSTATE
4275	{
4276	/** Pointer to the CPU structure. */
4277	PDISCPUSTATE pCpu;
4278	/** Pointer to the VM. */
4279	PVM pVM;
4280	/** Pointer to the VMCPU. */
4281	PVMCPU pVCpu;
4282	/** Pointer to the first byte in the segment. */
4283	RTGCUINTPTR GCPtrSegBase;
4284	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
4285	RTGCUINTPTR GCPtrSegEnd;
4286	/** The size of the segment minus 1. */
4287	RTGCUINTPTR cbSegLimit;
4288	/** Pointer to the current page - R3 Ptr. */
4289	void const *pvPageR3;
4290	/** Pointer to the current page - GC Ptr. */
4291	RTGCPTR pvPageGC;
4292	/** The lock information that PGMPhysReleasePageMappingLock needs. */
4293	PGMPAGEMAPLOCK PageMapLock;
4294	/** Whether the PageMapLock is valid or not. */
4295	bool fLocked;
4296	/** 64 bits mode or not. */
4297	bool f64Bits;
4298	} CPUMDISASSTATE, *PCPUMDISASSTATE;
4299
4300
4301	/**
4302	* @callback_method_impl{FNDISREADBYTES}
4303	*/
4304	static DECLCALLBACK(int) cpumR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
4305	{
4306	PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pDis->pvUser;
4307	for (;;)
4308	{
4309	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
4310
4311	/*
4312	* Need to update the page translation?
4313	*/
4314	if ( !pState->pvPageR3
4315	\|\| (GCPtr >> GUEST_PAGE_SHIFT) != (pState->pvPageGC >> GUEST_PAGE_SHIFT))
4316	{
4317	/* translate the address */
4318	pState->pvPageGC = GCPtr & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
4319
4320	/* Release mapping lock previously acquired. */
4321	if (pState->fLocked)
4322	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
4323	int rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
4324	if (RT_SUCCESS(rc))
4325	pState->fLocked = true;
4326	else
4327	{
4328	pState->fLocked = false;
4329	pState->pvPageR3 = NULL;
4330	return rc;
4331	}
4332	}
4333
4334	/*
4335	* Check the segment limit.
4336	*/
4337	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
4338	return VERR_OUT_OF_SELECTOR_BOUNDS;
4339
4340	/*
4341	* Calc how much we can read.
4342	*/
4343	uint32_t cb = GUEST_PAGE_SIZE - (GCPtr & GUEST_PAGE_OFFSET_MASK);
4344	if (!pState->f64Bits)
4345	{
4346	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
4347	if (cb > cbSeg && cbSeg)
4348	cb = cbSeg;
4349	}
4350	if (cb > cbMaxRead)
4351	cb = cbMaxRead;
4352
4353	/*
4354	* Read and advance or exit.
4355	*/
4356	memcpy(&pDis->abInstr[offInstr], (uint8_t *)pState->pvPageR3 + (GCPtr & GUEST_PAGE_OFFSET_MASK), cb);
4357	offInstr += (uint8_t)cb;
4358	if (cb >= cbMinRead)
4359	{
4360	pDis->cbCachedInstr = offInstr;
4361	return VINF_SUCCESS;
4362	}
4363	cbMinRead -= (uint8_t)cb;
4364	cbMaxRead -= (uint8_t)cb;
4365	}
4366	}
4367
4368
4369	/**
4370	* Disassemble an instruction and return the information in the provided structure.
4371	*
4372	* @returns VBox status code.
4373	* @param pVM The cross context VM structure.
4374	* @param pVCpu The cross context virtual CPU structure.
4375	* @param pCtx Pointer to the guest CPU context.
4376	* @param GCPtrPC Program counter (relative to CS) to disassemble from.
4377	* @param pCpu Disassembly state.
4378	* @param pszPrefix String prefix for logging (debug only).
4379	*
4380	*/
4381	VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu,
4382	const char *pszPrefix)
4383	{
4384	CPUMDISASSTATE State;
4385	int rc;
4386
4387	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
4388	State.pCpu = pCpu;
4389	State.pvPageGC = 0;
4390	State.pvPageR3 = NULL;
4391	State.pVM = pVM;
4392	State.pVCpu = pVCpu;
4393	State.fLocked = false;
4394	State.f64Bits = false;
4395
4396	/*
4397	* Get selector information.
4398	*/
4399	DISCPUMODE enmDisCpuMode;
4400	if ( (pCtx->cr0 & X86_CR0_PE)
4401	&& pCtx->eflags.Bits.u1VM == 0)
4402	{
4403	if (!CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs))
4404	return VERR_CPUM_HIDDEN_CS_LOAD_ERROR;
4405	State.f64Bits = enmMode >= PGMMODE_AMD64 && pCtx->cs.Attr.n.u1Long;
4406	State.GCPtrSegBase = pCtx->cs.u64Base;
4407	State.GCPtrSegEnd = pCtx->cs.u32Limit + 1 + (RTGCUINTPTR)pCtx->cs.u64Base;
4408	State.cbSegLimit = pCtx->cs.u32Limit;
4409	enmDisCpuMode = (State.f64Bits)
4410	? DISCPUMODE_64BIT
4411	: pCtx->cs.Attr.n.u1DefBig
4412	? DISCPUMODE_32BIT
4413	: DISCPUMODE_16BIT;
4414	}
4415	else
4416	{
4417	/* real or V86 mode */
4418	enmDisCpuMode = DISCPUMODE_16BIT;
4419	State.GCPtrSegBase = pCtx->cs.Sel * 16;
4420	State.GCPtrSegEnd = 0xFFFFFFFF;
4421	State.cbSegLimit = 0xFFFFFFFF;
4422	}
4423
4424	/*
4425	* Disassemble the instruction.
4426	*/
4427	uint32_t cbInstr;
4428	#ifndef LOG_ENABLED
4429	RT_NOREF_PV(pszPrefix);
4430	rc = DISInstrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State, pCpu, &cbInstr);
4431	if (RT_SUCCESS(rc))
4432	{
4433	#else
4434	char szOutput[160];
4435	rc = DISInstrToStrWithReader(GCPtrPC, enmDisCpuMode, cpumR3DisasInstrRead, &State,
4436	pCpu, &cbInstr, szOutput, sizeof(szOutput));
4437	if (RT_SUCCESS(rc))
4438	{
4439	/* log it */
4440	if (pszPrefix)
4441	Log(("%s-CPU%d: %s", pszPrefix, pVCpu->idCpu, szOutput));
4442	else
4443	Log(("%s", szOutput));
4444	#endif
4445	rc = VINF_SUCCESS;
4446	}
4447	else
4448	Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%RGv rc=%Rrc\n", pCtx->cs.Sel, GCPtrPC, rc));
4449
4450	/* Release mapping lock acquired in cpumR3DisasInstrRead. */
4451	if (State.fLocked)
4452	PGMPhysReleasePageMappingLock(pVM, &State.PageMapLock);
4453
4454	return rc;
4455	}
4456
4457
4458
4459	/**
4460	* API for controlling a few of the CPU features found in CR4.
4461	*
4462	* Currently only X86_CR4_TSD is accepted as input.
4463	*
4464	* @returns VBox status code.
4465	*
4466	* @param pVM The cross context VM structure.
4467	* @param fOr The CR4 OR mask.
4468	* @param fAnd The CR4 AND mask.
4469	*/
4470	VMMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd)
4471	{
4472	AssertMsgReturn(!(fOr & ~(X86_CR4_TSD)), ("%#x\n", fOr), VERR_INVALID_PARAMETER);
4473	AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
4474
4475	pVM->cpum.s.CR4.OrMask &= fAnd;
4476	pVM->cpum.s.CR4.OrMask \|= fOr;
4477
4478	return VINF_SUCCESS;
4479	}
4480
4481
4482	/**
4483	* Called when the ring-3 init phase completes.
4484	*
4485	* @returns VBox status code.
4486	* @param pVM The cross context VM structure.
4487	* @param enmWhat Which init phase.
4488	*/
4489	VMMR3DECL(int) CPUMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
4490	{
4491	switch (enmWhat)
4492	{
4493	case VMINITCOMPLETED_RING3:
4494	{
4495	/*
4496	* Figure out if the guest uses 32-bit or 64-bit FPU state at runtime for 64-bit capable VMs.
4497	* Only applicable/used on 64-bit hosts, refer CPUMR0A.asm. See @bugref{7138}.
4498	*/
4499	bool const fSupportsLongMode = VMR3IsLongModeAllowed(pVM);
4500	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4501	{
4502	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4503
4504	/* While loading a saved-state we fix it up in, cpumR3LoadDone(). */
4505	if (fSupportsLongMode)
4506	pVCpu->cpum.s.fUseFlags \|= CPUM_USE_SUPPORTS_LONGMODE;
4507	}
4508
4509	/* Register statistic counters for MSRs. */
4510	cpumR3MsrRegStats(pVM);
4511
4512	/* There shouldn't be any more calls to CPUMR3SetGuestCpuIdFeature and
4513	CPUMR3ClearGuestCpuIdFeature now, so do some final CPUID polishing (NX). */
4514	cpumR3CpuIdRing3InitDone(pVM);
4515
4516	/* Create VMX-preemption timer for nested guests if required. Must be
4517	done here as CPUM is initialized before TM. */
4518	if (pVM->cpum.s.GuestFeatures.fVmx)
4519	{
4520	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
4521	{
4522	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
4523	char szName[32];
4524	RTStrPrintf(szName, sizeof(szName), "Nested VMX-preemption %u", idCpu);
4525	int rc = TMR3TimerCreate(pVM, TMCLOCK_VIRTUAL_SYNC, cpumR3VmxPreemptTimerCallback, pVCpu,
4526	TMTIMER_FLAGS_RING0, szName, &pVCpu->cpum.s.hNestedVmxPreemptTimer);
4527	AssertLogRelRCReturn(rc, rc);
4528	}
4529	}
4530	break;
4531	}
4532
4533	default:
4534	break;
4535	}
4536	return VINF_SUCCESS;
4537	}
4538
4539
4540	/**
4541	* Called when the ring-0 init phases completed.
4542	*
4543	* @param pVM The cross context VM structure.
4544	*/
4545	VMMR3DECL(void) CPUMR3LogCpuIdAndMsrFeatures(PVM pVM)
4546	{
4547	/*
4548	* Enable log buffering as we're going to log a lot of lines.
4549	*/
4550	bool const fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
4551
4552	/*
4553	* Log the cpuid.
4554	*/
4555	RTCPUSET OnlineSet;
4556	LogRel(("CPUM: Logical host processors: %u present, %u max, %u online, online mask: %016RX64\n",
4557	(unsigned)RTMpGetPresentCount(), (unsigned)RTMpGetCount(), (unsigned)RTMpGetOnlineCount(),
4558	RTCpuSetToU64(RTMpGetOnlineSet(&OnlineSet)) ));
4559	RTCPUID cCores = RTMpGetCoreCount();
4560	if (cCores)
4561	LogRel(("CPUM: Physical host cores: %u\n", (unsigned)cCores));
4562	LogRel(("*********************** CPUID dump **********************\n"));
4563	DBGFR3Info(pVM->pUVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
4564	LogRel(("\n"));
4565	DBGFR3_INFO_LOG_SAFE(pVM, "cpuid", "verbose"); /* macro */
4566	LogRel(("****************** End of CPUID dump ********************\n"));
4567
4568	/*
4569	* Log VT-x extended features.
4570	*
4571	* SVM features are currently all covered under CPUID so there is nothing
4572	* to do here for SVM.
4573	*/
4574	if (pVM->cpum.s.HostFeatures.fVmx)
4575	{
4576	LogRel(("********************* VT-x features *********************\n"));
4577	DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
4578	LogRel(("\n"));
4579	LogRel(("***************** End of VT-x features ******************\n"));
4580	}
4581
4582	/*
4583	* Restore the log buffering state to what it was previously.
4584	*/
4585	RTLogRelSetBuffering(fOldBuffered);
4586	}
4587
4588
4589	/**
4590	* Marks the guest debug state as active.
4591	*
4592	* @returns nothing.
4593	* @param pVCpu The cross context virtual CPU structure.
4594	*
4595	* @note This is used solely by NEM (hence the name) to set the correct flags here
4596	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4597	* The specific NEM backends have to make sure to load the correct values.
4598	*/
4599	VMMR3_INT_DECL(void) CPUMR3NemActivateGuestDebugState(PVMCPUCC pVCpu)
4600	{
4601	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_HYPER);
4602	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_GUEST);
4603	}
4604
4605
4606	/**
4607	* Marks the hyper debug state as active.
4608	*
4609	* @returns nothing.
4610	* @param pVCpu The cross context virtual CPU structure.
4611	*
4612	* @note This is used solely by NEM (hence the name) to set the correct flags here
4613	* without loading the host's DRx registers, which is not possible from ring-3 anyway.
4614	* The specific NEM backends have to make sure to load the correct values.
4615	*/
4616	VMMR3_INT_DECL(void) CPUMR3NemActivateHyperDebugState(PVMCPUCC pVCpu)
4617	{
4618	/*
4619	* Make sure the hypervisor values are up to date.
4620	*/
4621	CPUMRecalcHyperDRx(pVCpu, UINT8_MAX /* no loading, please */);
4622
4623	ASMAtomicAndU32(&pVCpu->cpum.s.fUseFlags, ~CPUM_USED_DEBUG_REGS_GUEST);
4624	ASMAtomicOrU32(&pVCpu->cpum.s.fUseFlags, CPUM_USED_DEBUG_REGS_HYPER);
4625	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUM.cpp@ 97295

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