| 1 | /* $Id: CPUMDbg.cpp 35410 2011-01-05 17:21:11Z vboxsync $ */
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| 2 | /** @file
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| 3 | * CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2010 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 |
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| 19 | /*******************************************************************************
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| 20 | * Header Files *
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| 21 | *******************************************************************************/
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| 22 | #define LOG_GROUP LOG_GROUP_DBGF
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| 23 | #include <VBox/vmm/dbgf.h>
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| 24 | #include "DBGFInternal.h"
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| 25 | #include <VBox/vmm/vm.h>
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| 26 | #include <VBox/param.h>
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| 27 | #include <VBox/err.h>
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| 28 | #include <VBox/log.h>
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| 29 |
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| 30 |
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| 31 | static DECLCALLBACK(int) dbgfR3RegSet_seg(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 32 | {
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| 33 | return VERR_NOT_IMPLEMENTED;
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| 34 | }
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| 35 |
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| 36 | static DECLCALLBACK(int) dbgfR3RegGet_crX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue)
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| 37 | {
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| 38 | return VERR_NOT_IMPLEMENTED;
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| 39 | }
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| 40 |
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| 41 | static DECLCALLBACK(int) dbgfR3RegSet_crX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 42 | {
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| 43 | return VERR_NOT_IMPLEMENTED;
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| 44 | }
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| 45 |
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| 46 | static DECLCALLBACK(int) dbgfR3RegGet_drX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue)
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| 47 | {
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| 48 | return VERR_NOT_IMPLEMENTED;
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| 49 | }
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| 50 |
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| 51 | static DECLCALLBACK(int) dbgfR3RegSet_drX(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 52 | {
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| 53 | return VERR_NOT_IMPLEMENTED;
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| 54 | }
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| 55 |
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| 56 | static DECLCALLBACK(int) dbgfR3RegGet_msr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue)
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| 57 | {
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| 58 | return VERR_NOT_IMPLEMENTED;
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| 59 | }
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| 60 |
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| 61 | static DECLCALLBACK(int) dbgfR3RegSet_msr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 62 | {
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| 63 | return VERR_NOT_IMPLEMENTED;
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| 64 | }
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| 65 |
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| 66 | static DECLCALLBACK(int) dbgfR3RegGet_gdtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue)
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| 67 | {
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| 68 | return VERR_NOT_IMPLEMENTED;
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| 69 | }
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| 70 |
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| 71 | static DECLCALLBACK(int) dbgfR3RegSet_gdtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 72 | {
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| 73 | return VERR_NOT_IMPLEMENTED;
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| 74 | }
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| 75 |
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| 76 | static DECLCALLBACK(int) dbgfR3RegGet_idtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue)
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| 77 | {
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| 78 | return VERR_NOT_IMPLEMENTED;
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| 79 | }
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| 80 |
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| 81 | static DECLCALLBACK(int) dbgfR3RegSet_idtr(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 82 | {
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| 83 | return VERR_NOT_IMPLEMENTED;
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| 84 | }
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| 85 |
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| 86 | static DECLCALLBACK(int) dbgfR3RegGet_ftw(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue)
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| 87 | {
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| 88 | return VERR_NOT_IMPLEMENTED;
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| 89 | }
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| 90 |
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| 91 | static DECLCALLBACK(int) dbgfR3RegSet_ftw(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 92 | {
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| 93 | return VERR_NOT_IMPLEMENTED;
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| 94 | }
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| 95 |
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| 96 | static DECLCALLBACK(int) dbgfR3RegGet_stN(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCCPUMCTX pCtx, PRTUINT128U puValue)
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| 97 | {
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| 98 | return VERR_NOT_IMPLEMENTED;
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| 99 | }
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| 100 |
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| 101 | static DECLCALLBACK(int) dbgfR3RegSet_stN(PVMCPU pVCpu, struct DBGFREGDESC const *pDesc, PCPUMCTX pCtx, RTUINT128U uValue, RTUINT128U fMask)
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| 102 | {
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| 103 | return VERR_NOT_IMPLEMENTED;
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| 104 | }
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| 105 |
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| 106 |
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| 107 |
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| 108 | /*
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| 109 | * Set up aliases.
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| 110 | */
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| 111 | #define DBGFREGALIAS_STD(Name, psz32, psz16, psz8) \
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| 112 | static DBGFREGALIAS const g_aDbgfRegAliases_##Name[] = \
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| 113 | { \
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| 114 | { psz32, DBGFREGVALTYPE_U32 }, \
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| 115 | { psz16, DBGFREGVALTYPE_U16 }, \
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| 116 | { psz8, DBGFREGVALTYPE_U8 }, \
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| 117 | { NULL, DBGFREGVALTYPE_INVALID } \
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| 118 | }
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| 119 | DBGFREGALIAS_STD(rax, "eax", "ax", "al");
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| 120 | DBGFREGALIAS_STD(rcx, "ecx", "cx", "cl");
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| 121 | DBGFREGALIAS_STD(rdx, "edx", "dx", "dl");
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| 122 | DBGFREGALIAS_STD(rbx, "ebx", "bx", "bl");
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| 123 | DBGFREGALIAS_STD(rsp, "esp", "sp", NULL);
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| 124 | DBGFREGALIAS_STD(rbp, "ebp", "bp", NULL);
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| 125 | DBGFREGALIAS_STD(rsi, "esi", "si", "sil");
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| 126 | DBGFREGALIAS_STD(rdi, "edi", "di", "dil");
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| 127 | DBGFREGALIAS_STD(r8, "r8d", "r8w", "r8b");
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| 128 | DBGFREGALIAS_STD(r9, "r9d", "r9w", "r9b");
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| 129 | DBGFREGALIAS_STD(r10, "r10d", "r10w", "r10b");
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| 130 | DBGFREGALIAS_STD(r11, "r11d", "r11w", "r11b");
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| 131 | DBGFREGALIAS_STD(r12, "r12d", "r12w", "r12b");
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| 132 | DBGFREGALIAS_STD(r13, "r13d", "r13w", "r13b");
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| 133 | DBGFREGALIAS_STD(r14, "r14d", "r14w", "r14b");
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| 134 | DBGFREGALIAS_STD(r15, "r15d", "r15w", "r15b");
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| 135 | DBGFREGALIAS_STD(rip, "eip", "ip", NULL);
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| 136 | DBGFREGALIAS_STD(rflags, "eflags", "flags", NULL);
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| 137 | #undef DBGFREGALIAS_STD
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| 138 |
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| 139 | static DBGFREGALIAS const g_aDbgfRegAliases_fpuip[] =
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| 140 | {
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| 141 | { "fpuip", DBGFREGVALTYPE_U16 },
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| 142 | { NULL, DBGFREGVALTYPE_INVALID }
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| 143 | };
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| 144 |
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| 145 | static DBGFREGALIAS const g_aDbgfRegAliases_fpudp[] =
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| 146 | {
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| 147 | { "fpudp", DBGFREGVALTYPE_U16 },
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| 148 | { NULL, DBGFREGVALTYPE_INVALID }
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| 149 | };
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| 150 |
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| 151 | static DBGFREGALIAS const g_aDbgfRegAliases_cr0[] =
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| 152 | {
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| 153 | { "msw", DBGFREGVALTYPE_U16 },
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| 154 | { NULL, DBGFREGVALTYPE_INVALID }
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| 155 | };
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| 156 |
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| 157 | /*
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| 158 | * Sub fields.
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| 159 | */
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| 160 | /** Sub-fields for the (hidden) segment attribute register. */
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| 161 | static DBGFREGSUBFIELD const g_aDbgfRegFields_seg[] =
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| 162 | {
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| 163 | { "type", 0, 4, 0 },
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| 164 | { "s", 4, 1, 0 },
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| 165 | { "dpl", 5, 2, 0 },
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| 166 | { "p", 7, 1, 0 },
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| 167 | { "avl", 12, 1, 0 },
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| 168 | { "l", 13, 1, 0 },
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| 169 | { "d", 14, 1, 0 },
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| 170 | { "g", 15, 1, 0 },
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| 171 | { NULL, 0, 0, 0 }
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| 172 | };
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| 173 |
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| 174 | /** Sub-fields for the flags register. */
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| 175 | static DBGFREGSUBFIELD const g_aDbgfRegFields_rflags[] =
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| 176 | {
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| 177 | { "cf", 0, 1, 0 },
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| 178 | { "pf", 2, 1, 0 },
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| 179 | { "af", 4, 1, 0 },
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| 180 | { "zf", 6, 1, 0 },
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| 181 | { "sf", 7, 1, 0 },
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| 182 | { "tf", 8, 1, 0 },
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| 183 | { "if", 9, 1, 0 },
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| 184 | { "df", 10, 1, 0 },
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| 185 | { "of", 11, 1, 0 },
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| 186 | { "iopl", 12, 2, 0 },
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| 187 | { "nt", 14, 1, 0 },
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| 188 | { "rf", 16, 1, 0 },
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| 189 | { "vm", 17, 1, 0 },
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| 190 | { "ac", 18, 1, 0 },
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| 191 | { "vif", 19, 1, 0 },
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| 192 | { "vip", 20, 1, 0 },
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| 193 | { "id", 21, 1, 0 },
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| 194 | { NULL, 0, 0, 0 }
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| 195 | };
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| 196 |
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| 197 | /** Sub-fields for the FPU control word register. */
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| 198 | static DBGFREGSUBFIELD const g_aDbgfRegFields_fcw[] =
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| 199 | {
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| 200 | { "im", 1, 1, 0 },
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| 201 | { "dm", 2, 1, 0 },
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| 202 | { "zm", 3, 1, 0 },
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| 203 | { "om", 4, 1, 0 },
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| 204 | { "um", 5, 1, 0 },
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| 205 | { "pm", 6, 1, 0 },
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| 206 | { "pc", 8, 2, 0 },
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| 207 | { "rc", 10, 2, 0 },
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| 208 | { "x", 12, 1, 0 },
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| 209 | { NULL, 0, 0, 0 }
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| 210 | };
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| 211 |
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| 212 | /** Sub-fields for the FPU status word register. */
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| 213 | static DBGFREGSUBFIELD const g_aDbgfRegFields_fsw[] =
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| 214 | {
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| 215 | { "ie", 0, 1, 0 },
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| 216 | { "de", 1, 1, 0 },
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| 217 | { "ze", 2, 1, 0 },
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| 218 | { "oe", 3, 1, 0 },
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| 219 | { "ue", 4, 1, 0 },
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| 220 | { "pe", 5, 1, 0 },
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| 221 | { "se", 6, 1, 0 },
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| 222 | { "es", 7, 1, 0 },
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| 223 | { "c0", 8, 1, 0 },
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| 224 | { "c1", 9, 1, 0 },
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| 225 | { "c2", 10, 1, 0 },
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| 226 | { "top", 11, 3, 0 },
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| 227 | { "c3", 14, 1, 0 },
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| 228 | { "b", 15, 1, 0 },
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| 229 | { NULL, 0, 0, 0 }
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| 230 | };
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| 231 |
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| 232 | /** Sub-fields for the FPU tag word register. */
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| 233 | static DBGFREGSUBFIELD const g_aDbgfRegFields_ftw[] =
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| 234 | {
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| 235 | { "tag0", 0, 2, 0 },
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| 236 | { "tag1", 2, 2, 0 },
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| 237 | { "tag2", 4, 2, 0 },
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| 238 | { "tag3", 6, 2, 0 },
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| 239 | { "tag4", 8, 2, 0 },
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| 240 | { "tag5", 10, 2, 0 },
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| 241 | { "tag6", 12, 2, 0 },
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| 242 | { "tag7", 14, 2, 0 },
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| 243 | { NULL, 0, 0, 0 }
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| 244 | };
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| 245 |
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| 246 | /** Sub-fields for the Multimedia Extensions Control and Status Register. */
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| 247 | static DBGFREGSUBFIELD const g_aDbgfRegFields_mxcsr[] =
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| 248 | {
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| 249 | { "ie", 0, 1, 0 },
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| 250 | { "de", 1, 1, 0 },
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| 251 | { "ze", 2, 1, 0 },
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| 252 | { "oe", 3, 1, 0 },
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| 253 | { "ue", 4, 1, 0 },
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| 254 | { "pe", 5, 1, 0 },
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| 255 | { "daz", 6, 1, 0 },
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| 256 | { "im", 7, 1, 0 },
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| 257 | { "dm", 8, 1, 0 },
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| 258 | { "zm", 9, 1, 0 },
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| 259 | { "om", 10, 1, 0 },
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| 260 | { "um", 11, 1, 0 },
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| 261 | { "pm", 12, 1, 0 },
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| 262 | { "rc", 13, 2, 0 },
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| 263 | { "fz", 14, 1, 0 },
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| 264 | { NULL, 0, 0, 0 }
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| 265 | };
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| 266 |
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| 267 | /** Sub-fields for the FPU tag word register. */
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| 268 | static DBGFREGSUBFIELD const g_aDbgfRegFields_stN[] =
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| 269 | {
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| 270 | { "man", 0, 64, 0 },
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| 271 | { "exp", 64, 15, 0 },
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| 272 | { "sig", 79, 1, 0 },
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| 273 | { NULL, 0, 0, 0 }
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| 274 | };
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| 275 |
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| 276 | /** Sub-fields for the MMX registers. */
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| 277 | static DBGFREGSUBFIELD const g_aDbgfRegFields_mmN[] =
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| 278 | {
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| 279 | { "dw0", 0, 32, 0 },
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| 280 | { "dw1", 32, 32, 0 },
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| 281 | { "w0", 0, 16, 0 },
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| 282 | { "w1", 16, 16, 0 },
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| 283 | { "w2", 32, 16, 0 },
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| 284 | { "w3", 48, 16, 0 },
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| 285 | { "b0", 0, 8, 0 },
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| 286 | { "b1", 8, 8, 0 },
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| 287 | { "b2", 16, 8, 0 },
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| 288 | { "b3", 24, 8, 0 },
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| 289 | { "b4", 32, 8, 0 },
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| 290 | { "b5", 40, 8, 0 },
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| 291 | { "b6", 48, 8, 0 },
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| 292 | { "b7", 56, 8, 0 },
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| 293 | { NULL, 0, 0, 0 }
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| 294 | };
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| 295 |
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| 296 | /** Sub-fields for the XMM registers. */
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| 297 | static DBGFREGSUBFIELD const g_aDbgfRegFields_xmmN[] =
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| 298 | {
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| 299 | { "r0", 0, 32, 0 },
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| 300 | { "r0.man", 0+ 0, 23, 0 },
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| 301 | { "r0.exp", 0+23, 8, 0 },
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| 302 | { "r0.sig", 0+31, 1, 0 },
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| 303 | { "r1", 32, 32, 0 },
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| 304 | { "r1.man", 32+ 0, 23, 0 },
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| 305 | { "r1.exp", 32+23, 8, 0 },
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| 306 | { "r1.sig", 32+31, 1, 0 },
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| 307 | { "r2", 64, 32, 0 },
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| 308 | { "r2.man", 64+ 0, 23, 0 },
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| 309 | { "r2.exp", 64+23, 8, 0 },
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| 310 | { "r2.sig", 64+31, 1, 0 },
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| 311 | { "r3", 96, 32, 0 },
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| 312 | { "r3.man", 96+ 0, 23, 0 },
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| 313 | { "r3.exp", 96+23, 8, 0 },
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| 314 | { "r3.sig", 96+31, 1, 0 },
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| 315 | { NULL, 0, 0, 0 }
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| 316 | };
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| 317 |
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| 318 | /** Sub-fields for the CR0 register. */
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| 319 | static DBGFREGSUBFIELD const g_aDbgfRegFields_cr0[] =
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| 320 | {
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| 321 | /** @todo */
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| 322 | { NULL, 0, 0, 0 }
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| 323 | };
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| 324 |
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| 325 | /** Sub-fields for the CR3 register. */
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| 326 | static DBGFREGSUBFIELD const g_aDbgfRegFields_cr3[] =
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| 327 | {
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| 328 | /** @todo */
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| 329 | { NULL, 0, 0, 0 }
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| 330 | };
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| 331 |
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| 332 | /** Sub-fields for the CR4 register. */
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| 333 | static DBGFREGSUBFIELD const g_aDbgfRegFields_cr4[] =
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| 334 | {
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| 335 | /** @todo */
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| 336 | { NULL, 0, 0, 0 }
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| 337 | };
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| 338 |
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| 339 | /** Sub-fields for the DR6 register. */
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| 340 | static DBGFREGSUBFIELD const g_aDbgfRegFields_dr6[] =
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| 341 | {
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| 342 | /** @todo */
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| 343 | { NULL, 0, 0, 0 }
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| 344 | };
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| 345 |
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| 346 | /** Sub-fields for the DR7 register. */
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| 347 | static DBGFREGSUBFIELD const g_aDbgfRegFields_dr7[] =
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| 348 | {
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| 349 | /** @todo */
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| 350 | { NULL, 0, 0, 0 }
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| 351 | };
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| 352 |
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| 353 | /** Sub-fields for the CR_PAT MSR. */
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| 354 | static DBGFREGSUBFIELD const g_aDbgfRegFields_apic_base[] =
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| 355 | {
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| 356 | { "bsp", 8, 1, 0 },
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| 357 | { "ge", 9, 1, 0 },
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| 358 | { "base", 12, 20, 12 },
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| 359 | { NULL, 0, 0, 0 }
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| 360 | };
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| 361 |
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| 362 | /** Sub-fields for the CR_PAT MSR. */
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| 363 | static DBGFREGSUBFIELD const g_aDbgfRegFields_cr_pat[] =
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| 364 | {
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| 365 | /** @todo */
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| 366 | { NULL, 0, 0, 0 }
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| 367 | };
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| 368 |
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| 369 | /** Sub-fields for the PERF_STATUS MSR. */
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| 370 | static DBGFREGSUBFIELD const g_aDbgfRegFields_perf_status[] =
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| 371 | {
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| 372 | /** @todo */
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| 373 | { NULL, 0, 0, 0 }
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| 374 | };
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| 375 |
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| 376 | /** Sub-fields for the EFER MSR. */
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| 377 | static DBGFREGSUBFIELD const g_aDbgfRegFields_efer[] =
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| 378 | {
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| 379 | /** @todo */
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| 380 | { NULL, 0, 0, 0 }
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| 381 | };
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| 382 |
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| 383 | /** Sub-fields for the STAR MSR. */
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| 384 | static DBGFREGSUBFIELD const g_aDbgfRegFields_star[] =
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| 385 | {
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| 386 | /** @todo */
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| 387 | { NULL, 0, 0, 0 }
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| 388 | };
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| 389 |
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| 390 | /** Sub-fields for the CSTAR MSR. */
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| 391 | static DBGFREGSUBFIELD const g_aDbgfRegFields_cstar[] =
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| 392 | {
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| 393 | /** @todo */
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| 394 | { NULL, 0, 0, 0 }
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| 395 | };
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| 396 |
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| 397 | /** Sub-fields for the LSTAR MSR. */
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| 398 | static DBGFREGSUBFIELD const g_aDbgfRegFields_lstar[] =
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| 399 | {
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| 400 | /** @todo */
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| 401 | { NULL, 0, 0, 0 }
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| 402 | };
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| 403 |
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| 404 | /** Sub-fields for the SF_MASK MSR. */
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| 405 | static DBGFREGSUBFIELD const g_aDbgfRegFields_sf_mask[] =
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| 406 | {
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| 407 | /** @todo */
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| 408 | { NULL, 0, 0, 0 }
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| 409 | };
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| 410 |
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| 411 |
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| 412 |
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| 413 | /**
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| 414 | * The register descriptors.
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| 415 | */
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| 416 | static DBGFREGDESC const g_aDbgfRegDescs[] =
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| 417 | {
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| 418 | #define DBGFREGDESC_REG(UName, LName) \
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| 419 | { #LName, DBGFREG_##UName, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, LName), NULL, NULL, g_aDbgfRegAliases_##LName, NULL }
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| 420 | DBGFREGDESC_REG(RAX, rax),
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| 421 | DBGFREGDESC_REG(RCX, rcx),
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| 422 | DBGFREGDESC_REG(RDX, rdx),
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| 423 | DBGFREGDESC_REG(RSP, rsp),
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| 424 | DBGFREGDESC_REG(RBP, rbp),
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| 425 | DBGFREGDESC_REG(RSI, rsi),
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| 426 | DBGFREGDESC_REG(RDI, rdi),
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| 427 | DBGFREGDESC_REG(R8, r8),
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| 428 | DBGFREGDESC_REG(R9, r9),
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| 429 | DBGFREGDESC_REG(R10, r10),
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| 430 | DBGFREGDESC_REG(R11, r11),
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| 431 | DBGFREGDESC_REG(R12, r12),
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| 432 | DBGFREGDESC_REG(R13, r13),
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| 433 | DBGFREGDESC_REG(R14, r14),
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| 434 | DBGFREGDESC_REG(R15, r15),
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| 435 | #define DBGFREGDESC_SEG(UName, LName) \
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| 436 | { #LName, DBGFREG_##UName, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, LName), NULL, dbgfR3RegSet_seg, NULL, NULL }, \
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|---|
| 437 | { #LName "_attr", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, LName##Hid.Attr.u), NULL, NULL, NULL, g_aDbgfRegFields_seg }, \
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| 438 | { #LName "_base", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, LName##Hid.u64Base), NULL, NULL, NULL, NULL }, \
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| 439 | { #LName "_lim", DBGFREG_##UName##_ATTR, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, LName##Hid.u32Limit), NULL, NULL, NULL, NULL }
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| 440 | DBGFREGDESC_SEG(CS, cs),
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| 441 | DBGFREGDESC_SEG(DS, ds),
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| 442 | DBGFREGDESC_SEG(ES, es),
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| 443 | DBGFREGDESC_SEG(FS, fs),
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| 444 | DBGFREGDESC_SEG(GS, gs),
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| 445 | DBGFREGDESC_SEG(SS, ss),
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| 446 | DBGFREGDESC_REG(RIP, rip),
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| 447 | { "rflags", DBGFREG_RFLAGS, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, rflags), NULL, NULL, g_aDbgfRegAliases_rflags, g_aDbgfRegFields_rflags },
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|---|
| 448 | { "fcw", DBGFREG_FCW, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FCW), NULL, NULL, NULL, g_aDbgfRegFields_fcw },
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| 449 | { "fsw", DBGFREG_FSW, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FSW), NULL, NULL, NULL, g_aDbgfRegFields_fsw },
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|---|
| 450 | { "ftw", DBGFREG_FTW, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FTW), dbgfR3RegGet_ftw, dbgfR3RegSet_ftw, NULL, g_aDbgfRegFields_ftw },
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|---|
| 451 | { "fop", DBGFREG_FOP, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.FOP), NULL, NULL, NULL, NULL },
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|---|
| 452 | { "fpuip", DBGFREG_FPUIP, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.FPUIP), NULL, NULL, g_aDbgfRegAliases_fpuip, NULL },
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|---|
| 453 | { "fpucs", DBGFREG_FPUCS, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.CS), NULL, NULL, NULL, NULL },
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|---|
| 454 | { "fpudp", DBGFREG_FPUDP, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.FPUDP), NULL, NULL, g_aDbgfRegAliases_fpudp, NULL },
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|---|
| 455 | { "fpuds", DBGFREG_FPUDS, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, fpu.DS), NULL, NULL, NULL, NULL },
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|---|
| 456 | { "mxcsr", DBGFREG_MXCSR, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.MXCSR), NULL, NULL, NULL, g_aDbgfRegFields_mxcsr },
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|---|
| 457 | { "mxcsr_mask", DBGFREG_MXCSR_MASK, DBGFREGVALTYPE_U32, RT_OFFSETOF(CPUMCTX, fpu.MXCSR_MASK), NULL, NULL, NULL, g_aDbgfRegFields_mxcsr },
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|---|
| 458 | #define DBGFREGDESC_ST(n) \
|
|---|
| 459 | { "st" #n, DBGFREG_ST##n, DBGFREGVALTYPE_80, ~(size_t)0, dbgfR3RegGet_stN, dbgfR3RegSet_stN, NULL, g_aDbgfRegFields_stN }
|
|---|
| 460 | DBGFREGDESC_ST(0),
|
|---|
| 461 | DBGFREGDESC_ST(1),
|
|---|
| 462 | DBGFREGDESC_ST(2),
|
|---|
| 463 | DBGFREGDESC_ST(3),
|
|---|
| 464 | DBGFREGDESC_ST(4),
|
|---|
| 465 | DBGFREGDESC_ST(5),
|
|---|
| 466 | DBGFREGDESC_ST(6),
|
|---|
| 467 | DBGFREGDESC_ST(7),
|
|---|
| 468 | #define DBGFREGDESC_MM(n) \
|
|---|
| 469 | { "mm" #n, DBGFREG_MM##n, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, fpu.aRegs[n].mmx), NULL, NULL, NULL, g_aDbgfRegFields_mmN }
|
|---|
| 470 | DBGFREGDESC_MM(0),
|
|---|
| 471 | DBGFREGDESC_MM(1),
|
|---|
| 472 | DBGFREGDESC_MM(2),
|
|---|
| 473 | DBGFREGDESC_MM(3),
|
|---|
| 474 | DBGFREGDESC_MM(4),
|
|---|
| 475 | DBGFREGDESC_MM(5),
|
|---|
| 476 | DBGFREGDESC_MM(6),
|
|---|
| 477 | DBGFREGDESC_MM(7),
|
|---|
| 478 | #define DBGFREGDESC_XMM(n) \
|
|---|
| 479 | { "xmm" #n, DBGFREG_XMM##n, DBGFREGVALTYPE_U128, RT_OFFSETOF(CPUMCTX, fpu.aXMM[n].xmm), NULL, NULL, NULL, g_aDbgfRegFields_xmmN }
|
|---|
| 480 | DBGFREGDESC_XMM(0),
|
|---|
| 481 | DBGFREGDESC_XMM(1),
|
|---|
| 482 | DBGFREGDESC_XMM(2),
|
|---|
| 483 | DBGFREGDESC_XMM(3),
|
|---|
| 484 | DBGFREGDESC_XMM(4),
|
|---|
| 485 | DBGFREGDESC_XMM(5),
|
|---|
| 486 | DBGFREGDESC_XMM(6),
|
|---|
| 487 | DBGFREGDESC_XMM(7),
|
|---|
| 488 | DBGFREGDESC_XMM(8),
|
|---|
| 489 | DBGFREGDESC_XMM(9),
|
|---|
| 490 | DBGFREGDESC_XMM(10),
|
|---|
| 491 | DBGFREGDESC_XMM(11),
|
|---|
| 492 | DBGFREGDESC_XMM(12),
|
|---|
| 493 | DBGFREGDESC_XMM(13),
|
|---|
| 494 | DBGFREGDESC_XMM(14),
|
|---|
| 495 | DBGFREGDESC_XMM(15),
|
|---|
| 496 | { "gdtr_base", DBGFREG_GDTR_BASE, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, gdtr.pGdt), NULL, NULL, NULL, NULL },
|
|---|
| 497 | { "gdtr_limit", DBGFREG_GDTR_LIMIT, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, gdtr.cbGdt), NULL, NULL, NULL, NULL },
|
|---|
| 498 | { "idtr_base", DBGFREG_IDTR_BASE, DBGFREGVALTYPE_U64, RT_OFFSETOF(CPUMCTX, idtr.pIdt), NULL, NULL, NULL, NULL },
|
|---|
| 499 | { "idtr_limit", DBGFREG_IDTR_LIMIT, DBGFREGVALTYPE_U16, RT_OFFSETOF(CPUMCTX, idtr.cbIdt), NULL, NULL, NULL, NULL },
|
|---|
| 500 | DBGFREGDESC_SEG(LDTR, ldtr),
|
|---|
| 501 | DBGFREGDESC_SEG(TR, tr),
|
|---|
| 502 | { "cr0", DBGFREG_CR0, DBGFREGVALTYPE_U32, 0, dbgfR3RegGet_crX, dbgfR3RegSet_crX, g_aDbgfRegAliases_cr0, g_aDbgfRegFields_cr0 },
|
|---|
| 503 | { "cr2", DBGFREG_CR2, DBGFREGVALTYPE_U64, 2, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, NULL },
|
|---|
| 504 | { "cr3", DBGFREG_CR3, DBGFREGVALTYPE_U64, 3, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, g_aDbgfRegFields_cr3 },
|
|---|
| 505 | { "cr4", DBGFREG_CR4, DBGFREGVALTYPE_U32, 4, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, g_aDbgfRegFields_cr4 },
|
|---|
| 506 | { "cr8", DBGFREG_CR8, DBGFREGVALTYPE_U32, 8, dbgfR3RegGet_crX, dbgfR3RegSet_crX, NULL, NULL },
|
|---|
| 507 | { "dr0", DBGFREG_DR0, DBGFREGVALTYPE_U64, 0, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL },
|
|---|
| 508 | { "dr1", DBGFREG_DR1, DBGFREGVALTYPE_U64, 1, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL },
|
|---|
| 509 | { "dr2", DBGFREG_DR2, DBGFREGVALTYPE_U64, 2, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL },
|
|---|
| 510 | { "dr3", DBGFREG_DR3, DBGFREGVALTYPE_U64, 3, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, NULL },
|
|---|
| 511 | { "dr6", DBGFREG_DR6, DBGFREGVALTYPE_U32, 6, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, g_aDbgfRegFields_dr6 },
|
|---|
| 512 | { "dr7", DBGFREG_DR7, DBGFREGVALTYPE_U32, 7, dbgfR3RegGet_drX, dbgfR3RegSet_drX, NULL, g_aDbgfRegFields_dr7 },
|
|---|
| 513 | { "apic_base", DBGFREG_MSR_IA32_APICBASE, DBGFREGVALTYPE_U32, MSR_IA32_APICBASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_apic_base },
|
|---|
| 514 | { "pat", DBGFREG_MSR_IA32_CR_PAT, DBGFREGVALTYPE_U64, MSR_IA32_CR_PAT, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_cr_pat },
|
|---|
| 515 | { "perf_status", DBGFREG_MSR_IA32_PERF_STATUS, DBGFREGVALTYPE_U64, MSR_IA32_PERF_STATUS, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_perf_status },
|
|---|
| 516 | { "sysenter_cs", DBGFREG_MSR_IA32_SYSENTER_CS, DBGFREGVALTYPE_U16, MSR_IA32_SYSENTER_CS, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 517 | { "sysenter_eip", DBGFREG_MSR_IA32_SYSENTER_EIP, DBGFREGVALTYPE_U32, MSR_IA32_SYSENTER_EIP, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 518 | { "sysenter_esp", DBGFREG_MSR_IA32_SYSENTER_ESP, DBGFREGVALTYPE_U32, MSR_IA32_SYSENTER_ESP, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 519 | { "tsc", DBGFREG_MSR_IA32_TSC, DBGFREGVALTYPE_U32, MSR_IA32_TSC, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 520 | { "efer", DBGFREG_MSR_K6_EFER, DBGFREGVALTYPE_U32, MSR_K6_EFER, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_efer },
|
|---|
| 521 | { "star", DBGFREG_MSR_K6_STAR, DBGFREGVALTYPE_U64, MSR_K6_STAR, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_star },
|
|---|
| 522 | { "cstar", DBGFREG_MSR_K8_CSTAR, DBGFREGVALTYPE_U64, MSR_K8_CSTAR, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_cstar },
|
|---|
| 523 | { "msr_fs_base", DBGFREG_MSR_K8_FS_BASE, DBGFREGVALTYPE_U64, MSR_K8_FS_BASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 524 | { "msr_gs_base", DBGFREG_MSR_K8_GS_BASE, DBGFREGVALTYPE_U64, MSR_K8_GS_BASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 525 | { "krnl_gs_base", DBGFREG_MSR_K8_KERNEL_GS_BASE, DBGFREGVALTYPE_U64, MSR_K8_KERNEL_GS_BASE, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 526 | { "lstar", DBGFREG_MSR_K8_LSTAR, DBGFREGVALTYPE_U64, MSR_K8_LSTAR, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, g_aDbgfRegFields_lstar },
|
|---|
| 527 | { "tsc_aux", DBGFREG_MSR_K8_TSC_AUX, DBGFREGVALTYPE_U64, MSR_K8_TSC_AUX, dbgfR3RegGet_msr, dbgfR3RegSet_msr, NULL, NULL },
|
|---|
| 528 | { "ah", DBGFREG_AH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rax) + 1, NULL, NULL, NULL, NULL },
|
|---|
| 529 | { "ch", DBGFREG_CH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rcx) + 1, NULL, NULL, NULL, NULL },
|
|---|
| 530 | { "dh", DBGFREG_DH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rdx) + 1, NULL, NULL, NULL, NULL },
|
|---|
| 531 | { "bh", DBGFREG_BH, DBGFREGVALTYPE_U8, RT_OFFSETOF(CPUMCTX, rbx) + 1, NULL, NULL, NULL, NULL },
|
|---|
| 532 | { "gdtr", DBGFREG_GDTR, DBGFREGVALTYPE_DTR, ~(size_t)0, dbgfR3RegGet_gdtr, dbgfR3RegSet_gdtr, NULL, NULL },
|
|---|
| 533 | { "idtr", DBGFREG_IDTR, DBGFREGVALTYPE_DTR, ~(size_t)0, dbgfR3RegGet_idtr, dbgfR3RegSet_idtr, NULL, NULL },
|
|---|
| 534 | #undef DBGFREGDESC_REG
|
|---|
| 535 | #undef DBGFREGDESC_SEG
|
|---|
| 536 | #undef DBGFREGDESC_ST
|
|---|
| 537 | #undef DBGFREGDESC_MM
|
|---|
| 538 | #undef DBGFREGDESC_XMM
|
|---|
| 539 | };
|
|---|
| 540 |
|
|---|
