CPUMDbg.cpp@ 35490

Last change on this file since 35490 was 35490, checked in by vboxsync, 14 years ago
CPUM,Debugger: Registers, still some details left.
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1	/* $Id: CPUMDbg.cpp 35490 2011-01-11 15:17:10Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/uint128.h>
33
34
35	/**
36	* @interface_method_impl{DBGFREGDESC, pfnGet}
37	*/
38	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
39	{
40	PVMCPU pVCpu = (PVMCPU)pvUser;
41	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
42
43	VMCPU_ASSERT_EMT(pVCpu);
44
45	switch (pDesc->enmType)
46	{
47	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
48	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
52	default:
53	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
54	}
55	}
56
57
58	/**
59	* @interface_method_impl{DBGFREGDESC, pfnGet}
60	*/
61	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
62	{
63	PVMCPU pVCpu = (PVMCPU)pvUser;
64	void pv = (uint8_t )&pVCpu->cpum.s.Guest + pDesc->offRegister;
65
66	VMCPU_ASSERT_EMT(pVCpu);
67
68	switch (pDesc->enmType)
69	{
70	case DBGFREGVALTYPE_U8:
71	(uint8_t )pv &= ~pfMask->u8;
72	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
73	return VINF_SUCCESS;
74
75	case DBGFREGVALTYPE_U16:
76	(uint16_t )pv &= ~pfMask->u16;
77	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
78	return VINF_SUCCESS;
79
80	case DBGFREGVALTYPE_U32:
81	(uint32_t )pv &= ~pfMask->u32;
82	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
83	return VINF_SUCCESS;
84
85	case DBGFREGVALTYPE_U64:
86	(uint64_t )pv &= ~pfMask->u64;
87	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
88	return VINF_SUCCESS;
89
90	case DBGFREGVALTYPE_U128:
91	{
92	RTUINT128U Val;
93	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
94	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
95	return VINF_SUCCESS;
96	}
97
98	default:
99	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
100	}
101	}
102
103
104	/**
105	* @interface_method_impl{DBGFREGDESC, pfnGet}
106	*/
107	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
108	{
109	/** @todo perform a selector load, updating hidden selectors and stuff. */
110	return VERR_NOT_IMPLEMENTED;
111	}
112
113
114	/**
115	* @interface_method_impl{DBGFREGDESC, pfnGet}
116	*/
117	static DECLCALLBACK(int) cpumR3RegGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
118	{
119	PVMCPU pVCpu = (PVMCPU)pvUser;
120	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
121
122	VMCPU_ASSERT_EMT(pVCpu);
123
124	uint64_t u64Value;
125	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
126	AssertRCReturn(rc, rc);
127	switch (pDesc->enmType)
128	{
129	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
130	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
131	default:
132	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
133	}
134	return VINF_SUCCESS;
135	}
136
137
138	/**
139	* @interface_method_impl{DBGFREGDESC, pfnGet}
140	*/
141	static DECLCALLBACK(int) cpumR3RegSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
142	{
143	int rc;
144	PVMCPU pVCpu = (PVMCPU)pvUser;
145	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
146
147	VMCPU_ASSERT_EMT(pVCpu);
148
149	/*
150	* Calculate the new value.
151	*/
152	uint64_t u64Value;
153	uint64_t fMask;
154	uint64_t fMaskMax;
155	switch (pDesc->enmType)
156	{
157	case DBGFREGVALTYPE_U64:
158	u64Value = pValue->u64;
159	fMask = pfMask->u64;
160	fMaskMax = UINT64_MAX;
161	break;
162	case DBGFREGVALTYPE_U32:
163	u64Value = pValue->u32;
164	fMask = pfMask->u32;
165	fMaskMax = UINT32_MAX;
166	break;
167	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
168	}
169	if (fMask != fMaskMax)
170	{
171	uint64_t u64FullValue;
172	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
173	if (RT_FAILURE(rc))
174	return rc;
175	u64Value = (u64FullValue & ~fMask)
176	\| (u64Value & fMask);
177	}
178
179	/*
180	* Perform the assignment.
181	*/
182	switch (pDesc->offRegister)
183	{
184	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
185	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
186	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
187	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
188	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
189	default:
190	AssertFailedReturn(VERR_INTERNAL_ERROR_2);
191	}
192	return rc;
193	}
194
195
196	/**
197	* @interface_method_impl{DBGFREGDESC, pfnGet}
198	*/
199	static DECLCALLBACK(int) cpumR3RegGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
200	{
201	PVMCPU pVCpu = (PVMCPU)pvUser;
202	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
203
204	VMCPU_ASSERT_EMT(pVCpu);
205
206	uint64_t u64Value;
207	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
208	AssertRCReturn(rc, rc);
209	switch (pDesc->enmType)
210	{
211	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
212	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
213	default:
214	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
215	}
216	return VINF_SUCCESS;
217	}
218
219
220	/**
221	* @interface_method_impl{DBGFREGDESC, pfnGet}
222	*/
223	static DECLCALLBACK(int) cpumR3RegSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
224	{
225	int rc;
226	PVMCPU pVCpu = (PVMCPU)pvUser;
227	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
228
229	VMCPU_ASSERT_EMT(pVCpu);
230
231	/*
232	* Calculate the new value.
233	*/
234	uint64_t u64Value;
235	uint64_t fMask;
236	uint64_t fMaskMax;
237	switch (pDesc->enmType)
238	{
239	case DBGFREGVALTYPE_U64:
240	u64Value = pValue->u64;
241	fMask = pfMask->u64;
242	fMaskMax = UINT64_MAX;
243	break;
244	case DBGFREGVALTYPE_U32:
245	u64Value = pValue->u32;
246	fMask = pfMask->u32;
247	fMaskMax = UINT32_MAX;
248	break;
249	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
250	}
251	if (fMask != fMaskMax)
252	{
253	uint64_t u64FullValue;
254	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
255	if (RT_FAILURE(rc))
256	return rc;
257	u64Value = (u64FullValue & ~fMask)
258	\| (u64Value & fMask);
259	}
260
261	/*
262	* Perform the assignment.
263	*/
264	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
265	}
266
267
268	/**
269	* @interface_method_impl{DBGFREGDESC, pfnGet}
270	*/
271	static DECLCALLBACK(int) cpumR3RegGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
272	{
273	PVMCPU pVCpu = (PVMCPU)pvUser;
274	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
275
276	VMCPU_ASSERT_EMT(pVCpu);
277	uint64_t u64Value;
278	int rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
279	if (RT_SUCCESS(rc))
280	{
281	switch (pDesc->enmType)
282	{
283	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
284	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
285	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
286	default:
287	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
288	}
289	}
290	/** @todo what to do about errors? */
291	return rc;
292	}
293
294
295	/**
296	* @interface_method_impl{DBGFREGDESC, pfnGet}
297	*/
298	static DECLCALLBACK(int) cpumR3RegSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
299	{
300	int rc;
301	PVMCPU pVCpu = (PVMCPU)pvUser;
302	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
303
304	VMCPU_ASSERT_EMT(pVCpu);
305
306	/*
307	* Calculate the new value.
308	*/
309	uint64_t u64Value;
310	uint64_t fMask;
311	uint64_t fMaskMax;
312	switch (pDesc->enmType)
313	{
314	case DBGFREGVALTYPE_U64:
315	u64Value = pValue->u64;
316	fMask = pfMask->u64;
317	fMaskMax = UINT64_MAX;
318	break;
319	case DBGFREGVALTYPE_U32:
320	u64Value = pValue->u32;
321	fMask = pfMask->u32;
322	fMaskMax = UINT32_MAX;
323	break;
324	case DBGFREGVALTYPE_U16:
325	u64Value = pValue->u16;
326	fMask = pfMask->u16;
327	fMaskMax = UINT16_MAX;
328	break;
329	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
330	}
331	if (fMask != fMaskMax)
332	{
333	uint64_t u64FullValue;
334	rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
335	if (RT_FAILURE(rc))
336	return rc;
337	u64Value = (u64FullValue & ~fMask)
338	\| (u64Value & fMask);
339	}
340
341	/*
342	* Perform the assignment.
343	*/
344	return CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
345	}
346
347
348	/**
349	* @interface_method_impl{DBGFREGDESC, pfnGet}
350	*/
351	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
352	{
353	PVMCPU pVCpu = (PVMCPU)pvUser;
354	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
355
356	VMCPU_ASSERT_EMT(pVCpu);
357	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
358
359	pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.gdtr.cbGdt;
360	pValue->dtr.u64Base = pVCpu->cpum.s.Guest.gdtr.pGdt;
361	return VINF_SUCCESS;
362	}
363
364
365	/**
366	* @interface_method_impl{DBGFREGDESC, pfnGet}
367	*/
368	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
369	{
370	return VERR_NOT_IMPLEMENTED;
371	}
372
373
374	/**
375	* @interface_method_impl{DBGFREGDESC, pfnGet}
376	*/
377	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
378	{
379	PVMCPU pVCpu = (PVMCPU)pvUser;
380	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
381
382	VMCPU_ASSERT_EMT(pVCpu);
383	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
384
385	pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.idtr.cbIdt;
386	pValue->dtr.u64Base = pVCpu->cpum.s.Guest.idtr.pIdt;
387	return VINF_SUCCESS;
388	}
389
390
391	/**
392	* @interface_method_impl{DBGFREGDESC, pfnGet}
393	*/
394	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
395	{
396	return VERR_NOT_IMPLEMENTED;
397	}
398
399	/**
400	* @interface_method_impl{DBGFREGDESC, pfnGet}
401	*/
402	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
403	{
404	return VERR_NOT_IMPLEMENTED;
405	}
406
407	/**
408	* @interface_method_impl{DBGFREGDESC, pfnGet}
409	*/
410	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
411	{
412	return VERR_NOT_IMPLEMENTED;
413	}
414
415	/**
416	* @interface_method_impl{DBGFREGDESC, pfnGet}
417	*/
418	static DECLCALLBACK(int) cpumR3RegGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
419	{
420	return VERR_NOT_IMPLEMENTED;
421	}
422
423	/**
424	* @interface_method_impl{DBGFREGDESC, pfnGet}
425	*/
426	static DECLCALLBACK(int) cpumR3RegSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
427	{
428	return VERR_NOT_IMPLEMENTED;
429	}
430
431
432	/*
433	* Set up aliases.
434	*/
435	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
436	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
437	{ \
438	{ psz32, DBGFREGVALTYPE_U32 }, \
439	{ psz16, DBGFREGVALTYPE_U16 }, \
440	{ psz8, DBGFREGVALTYPE_U8 }, \
441	{ NULL, DBGFREGVALTYPE_INVALID } \
442	}
443	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
444	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
445	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
446	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
447	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
448	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
449	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
450	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
451	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
452	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
453	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
454	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
455	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
456	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
457	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
458	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
459	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
460	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
461	#undef CPUMREGALIAS_STD
462
463	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
464	{
465	{ "fpuip16", DBGFREGVALTYPE_U16 },
466	{ NULL, DBGFREGVALTYPE_INVALID }
467	};
468
469	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
470	{
471	{ "fpudp16", DBGFREGVALTYPE_U16 },
472	{ NULL, DBGFREGVALTYPE_INVALID }
473	};
474
475	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
476	{
477	{ "msw", DBGFREGVALTYPE_U16 },
478	{ NULL, DBGFREGVALTYPE_INVALID }
479	};
480
481	/*
482	* Sub fields.
483	*/
484	/** Sub-fields for the (hidden) segment attribute register. */
485	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
486	{
487	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
488	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
489	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
490	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
491	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
492	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
493	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
494	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
495	DBGFREGSUBFIELD_TERMINATOR()
496	};
497
498	/** Sub-fields for the flags register. */
499	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
500	{
501	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
502	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
503	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
504	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
505	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
506	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
507	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
508	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
509	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
510	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
511	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
512	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
513	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
514	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
515	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
516	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
517	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
518	DBGFREGSUBFIELD_TERMINATOR()
519	};
520
521	/** Sub-fields for the FPU control word register. */
522	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
523	{
524	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
525	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
526	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
527	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
528	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
529	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
530	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
531	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
532	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
533	DBGFREGSUBFIELD_TERMINATOR()
534	};
535
536	/** Sub-fields for the FPU status word register. */
537	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
538	{
539	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
540	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
541	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
542	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
543	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
544	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
545	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
546	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
547	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
548	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
549	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
550	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
551	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
552	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
553	DBGFREGSUBFIELD_TERMINATOR()
554	};
555
556	/** Sub-fields for the FPU tag word register. */
557	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
558	{
559	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
560	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
561	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
562	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
563	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
564	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
565	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
566	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
567	DBGFREGSUBFIELD_TERMINATOR()
568	};
569
570	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
571	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
572	{
573	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
574	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
575	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
576	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
577	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
578	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
579	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
580	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
581	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
582	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
583	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
584	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
585	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
586	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
587	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
588	DBGFREGSUBFIELD_TERMINATOR()
589	};
590
591	/** Sub-fields for the FPU tag word register. */
592	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
593	{
594	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
595	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
596	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
597	DBGFREGSUBFIELD_TERMINATOR()
598	};
599
600	/** Sub-fields for the MMX registers. */
601	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
602	{
603	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
604	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
605	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
606	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
607	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
608	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
609	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
610	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
611	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
612	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
613	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
614	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
615	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
616	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
617	DBGFREGSUBFIELD_TERMINATOR()
618	};
619
620	/** Sub-fields for the XMM registers. */
621	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
622	{
623	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
624	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
625	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
626	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
627	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
628	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
629	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
630	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
631	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
632	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
633	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
634	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
635	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
636	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
637	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
638	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
639	DBGFREGSUBFIELD_TERMINATOR()
640	};
641
642	/** Sub-fields for the CR0 register. */
643	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
644	{
645	/** @todo */
646	DBGFREGSUBFIELD_TERMINATOR()
647	};
648
649	/** Sub-fields for the CR3 register. */
650	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
651	{
652	/** @todo */
653	DBGFREGSUBFIELD_TERMINATOR()
654	};
655
656	/** Sub-fields for the CR4 register. */
657	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
658	{
659	/** @todo */
660	DBGFREGSUBFIELD_TERMINATOR()
661	};
662
663	/** Sub-fields for the DR6 register. */
664	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
665	{
666	/** @todo */
667	DBGFREGSUBFIELD_TERMINATOR()
668	};
669
670	/** Sub-fields for the DR7 register. */
671	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
672	{
673	/** @todo */
674	DBGFREGSUBFIELD_TERMINATOR()
675	};
676
677	/** Sub-fields for the CR_PAT MSR. */
678	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
679	{
680	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
681	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
682	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
683	DBGFREGSUBFIELD_TERMINATOR()
684	};
685
686	/** Sub-fields for the CR_PAT MSR. */
687	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
688	{
689	/** @todo */
690	DBGFREGSUBFIELD_TERMINATOR()
691	};
692
693	/** Sub-fields for the PERF_STATUS MSR. */
694	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
695	{
696	/** @todo */
697	DBGFREGSUBFIELD_TERMINATOR()
698	};
699
700	/** Sub-fields for the EFER MSR. */
701	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
702	{
703	/** @todo */
704	DBGFREGSUBFIELD_TERMINATOR()
705	};
706
707	/** Sub-fields for the STAR MSR. */
708	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
709	{
710	/** @todo */
711	DBGFREGSUBFIELD_TERMINATOR()
712	};
713
714	/** Sub-fields for the CSTAR MSR. */
715	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
716	{
717	/** @todo */
718	DBGFREGSUBFIELD_TERMINATOR()
719	};
720
721	/** Sub-fields for the LSTAR MSR. */
722	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
723	{
724	/** @todo */
725	DBGFREGSUBFIELD_TERMINATOR()
726	};
727
728	/** Sub-fields for the SF_MASK MSR. */
729	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
730	{
731	/** @todo */
732	DBGFREGSUBFIELD_TERMINATOR()
733	};
734
735
736
737	/**
738	* The register descriptors.
739	*/
740	static DBGFREGDESC const g_aCpumRegDescs[] =
741	{
742	#define CPUMREGDESC_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
743	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
744	#define CPUMREGDESC_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
745	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
746	#define CPUMREGDESC_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
747	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
748
749	#define CPUMREGDESC_REG(UName, LName) \
750	CPUMREGDESC_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
751	CPUMREGDESC_REG(RAX, rax),
752	CPUMREGDESC_REG(RCX, rcx),
753	CPUMREGDESC_REG(RDX, rdx),
754	CPUMREGDESC_REG(RBX, rbx),
755	CPUMREGDESC_REG(RSP, rsp),
756	CPUMREGDESC_REG(RBP, rbp),
757	CPUMREGDESC_REG(RSI, rsi),
758	CPUMREGDESC_REG(RDI, rdi),
759	CPUMREGDESC_REG(R8, r8),
760	CPUMREGDESC_REG(R9, r9),
761	CPUMREGDESC_REG(R10, r10),
762	CPUMREGDESC_REG(R11, r11),
763	CPUMREGDESC_REG(R12, r12),
764	CPUMREGDESC_REG(R13, r13),
765	CPUMREGDESC_REG(R14, r14),
766	CPUMREGDESC_REG(R15, r15),
767	#define CPUMREGDESC_SEG(UName, LName) \
768	CPUMREGDESC_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
769	CPUMREGDESC_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
770	CPUMREGDESC_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
771	CPUMREGDESC_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
772	CPUMREGDESC_SEG(CS, cs),
773	CPUMREGDESC_SEG(DS, ds),
774	CPUMREGDESC_SEG(ES, es),
775	CPUMREGDESC_SEG(FS, fs),
776	CPUMREGDESC_SEG(GS, gs),
777	CPUMREGDESC_SEG(SS, ss),
778	CPUMREGDESC_REG(RIP, rip),
779	CPUMREGDESC_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
780	CPUMREGDESC_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
781	CPUMREGDESC_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
782	CPUMREGDESC_RW_AS("ftw", FTW, U16, fpu.FTW, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
783	CPUMREGDESC_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
784	CPUMREGDESC_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
785	CPUMREGDESC_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
786	CPUMREGDESC_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
787	CPUMREGDESC_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
788	CPUMREGDESC_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
789	CPUMREGDESC_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
790	#define CPUMREGDESC_ST(n) \
791	CPUMREGDESC_RW_AS("st" #n, ST##n, LRD, fpu.aRegs[n], cpumR3RegGet_stN, cpumR3RegSet_stN, NULL, g_aCpumRegFields_stN )
792	CPUMREGDESC_ST(0),
793	CPUMREGDESC_ST(1),
794	CPUMREGDESC_ST(2),
795	CPUMREGDESC_ST(3),
796	CPUMREGDESC_ST(4),
797	CPUMREGDESC_ST(5),
798	CPUMREGDESC_ST(6),
799	CPUMREGDESC_ST(7),
800	#define CPUMREGDESC_MM(n) \
801	CPUMREGDESC_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN )
802	CPUMREGDESC_MM(0),
803	CPUMREGDESC_MM(1),
804	CPUMREGDESC_MM(2),
805	CPUMREGDESC_MM(3),
806	CPUMREGDESC_MM(4),
807	CPUMREGDESC_MM(5),
808	CPUMREGDESC_MM(6),
809	CPUMREGDESC_MM(7),
810	#define CPUMREGDESC_XMM(n) \
811	CPUMREGDESC_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN )
812	CPUMREGDESC_XMM(0),
813	CPUMREGDESC_XMM(1),
814	CPUMREGDESC_XMM(2),
815	CPUMREGDESC_XMM(3),
816	CPUMREGDESC_XMM(4),
817	CPUMREGDESC_XMM(5),
818	CPUMREGDESC_XMM(6),
819	CPUMREGDESC_XMM(7),
820	CPUMREGDESC_XMM(8),
821	CPUMREGDESC_XMM(9),
822	CPUMREGDESC_XMM(10),
823	CPUMREGDESC_XMM(11),
824	CPUMREGDESC_XMM(12),
825	CPUMREGDESC_XMM(13),
826	CPUMREGDESC_XMM(14),
827	CPUMREGDESC_XMM(15),
828	CPUMREGDESC_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
829	CPUMREGDESC_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
830	CPUMREGDESC_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
831	CPUMREGDESC_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
832	CPUMREGDESC_SEG(LDTR, ldtr),
833	CPUMREGDESC_SEG(TR, tr),
834	CPUMREGDESC_EX_AS("cr0", CR0, U32, 0, cpumR3RegGet_crX, cpumR3RegSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
835	CPUMREGDESC_EX_AS("cr2", CR2, U64, 2, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ),
836	CPUMREGDESC_EX_AS("cr3", CR3, U64, 3, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr3 ),
837	CPUMREGDESC_EX_AS("cr4", CR4, U32, 4, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr4 ),
838	CPUMREGDESC_EX_AS("cr8", CR8, U32, 8, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ),
839	CPUMREGDESC_EX_AS("dr0", DR0, U64, 0, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
840	CPUMREGDESC_EX_AS("dr1", DR1, U64, 1, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
841	CPUMREGDESC_EX_AS("dr2", DR2, U64, 2, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
842	CPUMREGDESC_EX_AS("dr3", DR3, U64, 3, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
843	CPUMREGDESC_EX_AS("dr6", DR6, U32, 6, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr6 ),
844	CPUMREGDESC_EX_AS("dr7", DR7, U32, 7, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr7 ),
845	#define CPUMREGDESC_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
846	CPUMREGDESC_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, a_paSubFields )
847	CPUMREGDESC_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
848	CPUMREGDESC_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
849	CPUMREGDESC_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
850	CPUMREGDESC_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
851	CPUMREGDESC_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
852	CPUMREGDESC_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
853	CPUMREGDESC_MSR("tsc", IA32_TSC, U32, NULL ),
854	CPUMREGDESC_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
855	CPUMREGDESC_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
856	CPUMREGDESC_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
857	CPUMREGDESC_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
858	CPUMREGDESC_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
859	CPUMREGDESC_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
860	CPUMREGDESC_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
861	CPUMREGDESC_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
862	CPUMREGDESC_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
863	CPUMREGDESC_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCTX, rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
864	CPUMREGDESC_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCTX, rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
865	CPUMREGDESC_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCTX, rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
866	CPUMREGDESC_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCTX, rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
867	CPUMREGDESC_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
868	CPUMREGDESC_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
869	DBGFREGDESC_TERMINATOR()
870	#undef CPUMREGDESC_REG
871	#undef CPUMREGDESC_SEG
872	#undef CPUMREGDESC_ST
873	#undef CPUMREGDESC_MM
874	#undef CPUMREGDESC_XMM
875	#undef CPUMREGDESC_MSR
876	};
877
878
879	/**
880	* Initializes the debugger related sides of the CPUM component.
881	*
882	* Called by CPUMR3Init.
883	*
884	* @returns VBox status code.
885	* @param pVM The VM handle.
886	*/
887	int cpumR3DbgInit(PVM pVM)
888	{
889	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
890	{
891	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegDescs);
892	AssertLogRelRCReturn(rc, rc);
893	}
894
895	return VINF_SUCCESS;
896	}
897

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 35490

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