CPUMDbg.cpp@ 35572

Last change on this file since 35572 was 35513, checked in by vboxsync, 14 years ago
DBGFReg: long double -> RTFLOAT80U2. Get floating point registers and stuff.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 37.1 KB

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1	/* $Id: CPUMDbg.cpp 35513 2011-01-12 17:50:43Z vboxsync $ */
2	/** @file
3	* CPUM - CPU Monitor / Manager, Debugger & Debugging APIs.
4	*/
5
6	/*
7	* Copyright (C) 2010-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include "CPUMInternal.h"
27	#include <VBox/vmm/vm.h>
28	#include <VBox/param.h>
29	#include <VBox/err.h>
30	#include <VBox/log.h>
31	#include <iprt/thread.h>
32	#include <iprt/uint128.h>
33
34
35	/**
36	* @interface_method_impl{DBGFREGDESC, pfnGet}
37	*/
38	static DECLCALLBACK(int) cpumR3RegGet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
39	{
40	PVMCPU pVCpu = (PVMCPU)pvUser;
41	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
42
43	VMCPU_ASSERT_EMT(pVCpu);
44
45	switch (pDesc->enmType)
46	{
47	case DBGFREGVALTYPE_U8: pValue->u8 = (uint8_t const )pv; return VINF_SUCCESS;
48	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t const )pv; return VINF_SUCCESS;
49	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t const )pv; return VINF_SUCCESS;
50	case DBGFREGVALTYPE_U64: pValue->u64 = (uint64_t const )pv; return VINF_SUCCESS;
51	case DBGFREGVALTYPE_U128: pValue->u128 = *(PCRTUINT128U )pv; return VINF_SUCCESS;
52	default:
53	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
54	}
55	}
56
57
58	/**
59	* @interface_method_impl{DBGFREGDESC, pfnGet}
60	*/
61	static DECLCALLBACK(int) cpumR3RegSet_Generic(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
62	{
63	PVMCPU pVCpu = (PVMCPU)pvUser;
64	void pv = (uint8_t )&pVCpu->cpum.s.Guest + pDesc->offRegister;
65
66	VMCPU_ASSERT_EMT(pVCpu);
67
68	switch (pDesc->enmType)
69	{
70	case DBGFREGVALTYPE_U8:
71	(uint8_t )pv &= ~pfMask->u8;
72	(uint8_t )pv \|= pValue->u8 & pfMask->u8;
73	return VINF_SUCCESS;
74
75	case DBGFREGVALTYPE_U16:
76	(uint16_t )pv &= ~pfMask->u16;
77	(uint16_t )pv \|= pValue->u16 & pfMask->u16;
78	return VINF_SUCCESS;
79
80	case DBGFREGVALTYPE_U32:
81	(uint32_t )pv &= ~pfMask->u32;
82	(uint32_t )pv \|= pValue->u32 & pfMask->u32;
83	return VINF_SUCCESS;
84
85	case DBGFREGVALTYPE_U64:
86	(uint64_t )pv &= ~pfMask->u64;
87	(uint64_t )pv \|= pValue->u64 & pfMask->u64;
88	return VINF_SUCCESS;
89
90	case DBGFREGVALTYPE_U128:
91	{
92	RTUINT128U Val;
93	RTUInt128AssignAnd((PRTUINT128U)pv, RTUInt128AssignBitwiseNot(RTUInt128Assign(&Val, &pfMask->u128)));
94	RTUInt128AssignOr((PRTUINT128U)pv, RTUInt128AssignAnd(RTUInt128Assign(&Val, &pValue->u128), &pfMask->u128));
95	return VINF_SUCCESS;
96	}
97
98	default:
99	AssertMsgFailedReturn(("%d %s\n", pDesc->enmType, pDesc->pszName), VERR_INTERNAL_ERROR_3);
100	}
101	}
102
103
104	/**
105	* @interface_method_impl{DBGFREGDESC, pfnGet}
106	*/
107	static DECLCALLBACK(int) cpumR3RegSet_seg(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
108	{
109	/** @todo perform a selector load, updating hidden selectors and stuff. */
110	return VERR_NOT_IMPLEMENTED;
111	}
112
113
114	/**
115	* @interface_method_impl{DBGFREGDESC, pfnGet}
116	*/
117	static DECLCALLBACK(int) cpumR3RegGet_crX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
118	{
119	PVMCPU pVCpu = (PVMCPU)pvUser;
120	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
121
122	VMCPU_ASSERT_EMT(pVCpu);
123
124	uint64_t u64Value;
125	int rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64Value);
126	AssertRCReturn(rc, rc);
127	switch (pDesc->enmType)
128	{
129	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
130	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
131	default:
132	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
133	}
134	return VINF_SUCCESS;
135	}
136
137
138	/**
139	* @interface_method_impl{DBGFREGDESC, pfnGet}
140	*/
141	static DECLCALLBACK(int) cpumR3RegSet_crX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
142	{
143	int rc;
144	PVMCPU pVCpu = (PVMCPU)pvUser;
145	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
146
147	VMCPU_ASSERT_EMT(pVCpu);
148
149	/*
150	* Calculate the new value.
151	*/
152	uint64_t u64Value;
153	uint64_t fMask;
154	uint64_t fMaskMax;
155	switch (pDesc->enmType)
156	{
157	case DBGFREGVALTYPE_U64:
158	u64Value = pValue->u64;
159	fMask = pfMask->u64;
160	fMaskMax = UINT64_MAX;
161	break;
162	case DBGFREGVALTYPE_U32:
163	u64Value = pValue->u32;
164	fMask = pfMask->u32;
165	fMaskMax = UINT32_MAX;
166	break;
167	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
168	}
169	if (fMask != fMaskMax)
170	{
171	uint64_t u64FullValue;
172	rc = CPUMGetGuestCRx(pVCpu, pDesc->offRegister, &u64FullValue);
173	if (RT_FAILURE(rc))
174	return rc;
175	u64Value = (u64FullValue & ~fMask)
176	\| (u64Value & fMask);
177	}
178
179	/*
180	* Perform the assignment.
181	*/
182	switch (pDesc->offRegister)
183	{
184	case 0: rc = CPUMSetGuestCR0(pVCpu, u64Value); break;
185	case 2: rc = CPUMSetGuestCR2(pVCpu, u64Value); break;
186	case 3: rc = CPUMSetGuestCR3(pVCpu, u64Value); break;
187	case 4: rc = CPUMSetGuestCR4(pVCpu, u64Value); break;
188	case 8: rc = PDMApicSetTPR(pVCpu, (uint8_t)(u64Value << 4)); break;
189	default:
190	AssertFailedReturn(VERR_INTERNAL_ERROR_2);
191	}
192	return rc;
193	}
194
195
196	/**
197	* @interface_method_impl{DBGFREGDESC, pfnGet}
198	*/
199	static DECLCALLBACK(int) cpumR3RegGet_drX(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
200	{
201	PVMCPU pVCpu = (PVMCPU)pvUser;
202	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
203
204	VMCPU_ASSERT_EMT(pVCpu);
205
206	uint64_t u64Value;
207	int rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64Value);
208	AssertRCReturn(rc, rc);
209	switch (pDesc->enmType)
210	{
211	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
212	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
213	default:
214	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
215	}
216	return VINF_SUCCESS;
217	}
218
219
220	/**
221	* @interface_method_impl{DBGFREGDESC, pfnGet}
222	*/
223	static DECLCALLBACK(int) cpumR3RegSet_drX(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
224	{
225	int rc;
226	PVMCPU pVCpu = (PVMCPU)pvUser;
227	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
228
229	VMCPU_ASSERT_EMT(pVCpu);
230
231	/*
232	* Calculate the new value.
233	*/
234	uint64_t u64Value;
235	uint64_t fMask;
236	uint64_t fMaskMax;
237	switch (pDesc->enmType)
238	{
239	case DBGFREGVALTYPE_U64:
240	u64Value = pValue->u64;
241	fMask = pfMask->u64;
242	fMaskMax = UINT64_MAX;
243	break;
244	case DBGFREGVALTYPE_U32:
245	u64Value = pValue->u32;
246	fMask = pfMask->u32;
247	fMaskMax = UINT32_MAX;
248	break;
249	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
250	}
251	if (fMask != fMaskMax)
252	{
253	uint64_t u64FullValue;
254	rc = CPUMGetGuestDRx(pVCpu, pDesc->offRegister, &u64FullValue);
255	if (RT_FAILURE(rc))
256	return rc;
257	u64Value = (u64FullValue & ~fMask)
258	\| (u64Value & fMask);
259	}
260
261	/*
262	* Perform the assignment.
263	*/
264	return CPUMSetGuestDRx(pVCpu, pDesc->offRegister, u64Value);
265	}
266
267
268	/**
269	* @interface_method_impl{DBGFREGDESC, pfnGet}
270	*/
271	static DECLCALLBACK(int) cpumR3RegGet_msr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
272	{
273	PVMCPU pVCpu = (PVMCPU)pvUser;
274	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
275
276	VMCPU_ASSERT_EMT(pVCpu);
277	uint64_t u64Value;
278	int rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64Value);
279	if (RT_SUCCESS(rc))
280	{
281	switch (pDesc->enmType)
282	{
283	case DBGFREGVALTYPE_U64: pValue->u64 = u64Value; break;
284	case DBGFREGVALTYPE_U32: pValue->u32 = (uint32_t)u64Value; break;
285	case DBGFREGVALTYPE_U16: pValue->u16 = (uint16_t)u64Value; break;
286	default:
287	AssertFailedReturn(VERR_INTERNAL_ERROR_4);
288	}
289	}
290	/** @todo what to do about errors? */
291	return rc;
292	}
293
294
295	/**
296	* @interface_method_impl{DBGFREGDESC, pfnGet}
297	*/
298	static DECLCALLBACK(int) cpumR3RegSet_msr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
299	{
300	int rc;
301	PVMCPU pVCpu = (PVMCPU)pvUser;
302	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
303
304	VMCPU_ASSERT_EMT(pVCpu);
305
306	/*
307	* Calculate the new value.
308	*/
309	uint64_t u64Value;
310	uint64_t fMask;
311	uint64_t fMaskMax;
312	switch (pDesc->enmType)
313	{
314	case DBGFREGVALTYPE_U64:
315	u64Value = pValue->u64;
316	fMask = pfMask->u64;
317	fMaskMax = UINT64_MAX;
318	break;
319	case DBGFREGVALTYPE_U32:
320	u64Value = pValue->u32;
321	fMask = pfMask->u32;
322	fMaskMax = UINT32_MAX;
323	break;
324	case DBGFREGVALTYPE_U16:
325	u64Value = pValue->u16;
326	fMask = pfMask->u16;
327	fMaskMax = UINT16_MAX;
328	break;
329	default: AssertFailedReturn(VERR_INTERNAL_ERROR_4);
330	}
331	if (fMask != fMaskMax)
332	{
333	uint64_t u64FullValue;
334	rc = CPUMQueryGuestMsr(pVCpu, pDesc->offRegister, &u64FullValue);
335	if (RT_FAILURE(rc))
336	return rc;
337	u64Value = (u64FullValue & ~fMask)
338	\| (u64Value & fMask);
339	}
340
341	/*
342	* Perform the assignment.
343	*/
344	return CPUMSetGuestMsr(pVCpu, pDesc->offRegister, u64Value);
345	}
346
347
348	/**
349	* @interface_method_impl{DBGFREGDESC, pfnGet}
350	*/
351	static DECLCALLBACK(int) cpumR3RegGet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
352	{
353	PVMCPU pVCpu = (PVMCPU)pvUser;
354	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
355
356	VMCPU_ASSERT_EMT(pVCpu);
357	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
358
359	pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.gdtr.cbGdt;
360	pValue->dtr.u64Base = pVCpu->cpum.s.Guest.gdtr.pGdt;
361	return VINF_SUCCESS;
362	}
363
364
365	/**
366	* @interface_method_impl{DBGFREGDESC, pfnGet}
367	*/
368	static DECLCALLBACK(int) cpumR3RegSet_gdtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
369	{
370	return VERR_NOT_IMPLEMENTED;
371	}
372
373
374	/**
375	* @interface_method_impl{DBGFREGDESC, pfnGet}
376	*/
377	static DECLCALLBACK(int) cpumR3RegGet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
378	{
379	PVMCPU pVCpu = (PVMCPU)pvUser;
380	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
381
382	VMCPU_ASSERT_EMT(pVCpu);
383	Assert(pDesc->enmType == DBGFREGVALTYPE_DTR);
384
385	pValue->dtr.u32Limit = pVCpu->cpum.s.Guest.idtr.cbIdt;
386	pValue->dtr.u64Base = pVCpu->cpum.s.Guest.idtr.pIdt;
387	return VINF_SUCCESS;
388	}
389
390
391	/**
392	* @interface_method_impl{DBGFREGDESC, pfnGet}
393	*/
394	static DECLCALLBACK(int) cpumR3RegSet_idtr(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
395	{
396	return VERR_NOT_IMPLEMENTED;
397	}
398
399
400	/**
401	* Is the FPU state in FXSAVE format or not.
402	*
403	* @returns true if it is, false if it's in FNSAVE.
404	* @param pVCpu The virtual CPU handle.
405	*/
406	DECLINLINE(bool) cpumR3RegIsFxSaveFormat(PVMCPU pVCpu)
407	{
408	#ifdef RT_ARCH_AMD64
409	return true;
410	#else
411	return pVCpu->pVMR3->cpum.s.CPUFeatures.edx.u1FXSR;
412	#endif
413	}
414
415
416	/**
417	* Determins the tag register value for a CPU register when the FPU state
418	* format is FXSAVE.
419	*
420	* @returns The tag register value.
421	* @param pVCpu The virtual CPU handle.
422	* @param iReg The register number (0..7).
423	*/
424	DECLINLINE(uint16_t) cpumR3RegCalcFpuTagFromFxSave(PVMCPU pVCpu, unsigned iReg)
425	{
426	/*
427	* See table 11-1 in the AMD docs.
428	*/
429	if (!(pVCpu->cpum.s.Guest.fpu.FTW & RT_BIT_32(iReg)))
430	return 3; /* b11 - empty */
431
432	uint16_t const uExp = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au16[4];
433	if (uExp == 0)
434	{
435	if (pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] == 0) /* J & M == 0 */
436	return 1; /* b01 - zero */
437	return 2; /* b10 - special */
438	}
439
440	if (uExp == UINT16_C(0xffff))
441	return 2; /* b10 - special */
442
443	if (!(pVCpu->cpum.s.Guest.fpu.aRegs[iReg].au64[0] >> 63)) /* J == 0 */
444	return 2; /* b10 - special */
445
446	return 0; /* b00 - valid (normal) */
447	}
448
449
450	/**
451	* @interface_method_impl{DBGFREGDESC, pfnGet}
452	*/
453	static DECLCALLBACK(int) cpumR3RegGet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
454	{
455	PVMCPU pVCpu = (PVMCPU)pvUser;
456	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
457
458	VMCPU_ASSERT_EMT(pVCpu);
459	Assert(pDesc->enmType == DBGFREGVALTYPE_U16);
460
461	if (cpumR3RegIsFxSaveFormat(pVCpu))
462	pValue->u16 = cpumR3RegCalcFpuTagFromFxSave(pVCpu, 0)
463	\| (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 1) << 2)
464	\| (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 2) << 4)
465	\| (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 3) << 6)
466	\| (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 4) << 8)
467	\| (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 5) << 10)
468	\| (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 6) << 12)
469	\| (cpumR3RegCalcFpuTagFromFxSave(pVCpu, 7) << 14);
470	else
471	{
472	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
473	pValue->u16 = pOldFpu->FTW;
474	}
475	return VINF_SUCCESS;
476	}
477
478
479	/**
480	* @interface_method_impl{DBGFREGDESC, pfnGet}
481	*/
482	static DECLCALLBACK(int) cpumR3RegSet_ftw(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
483	{
484	return VERR_DBGF_READ_ONLY_REGISTER;
485	}
486
487
488	/**
489	* @interface_method_impl{DBGFREGDESC, pfnGet}
490	*/
491	static DECLCALLBACK(int) cpumR3RegGet_stN(void *pvUser, PCDBGFREGDESC pDesc, PDBGFREGVAL pValue)
492	{
493	PVMCPU pVCpu = (PVMCPU)pvUser;
494	void const pv = (uint8_t const )&pVCpu->cpum.s.Guest + pDesc->offRegister;
495
496	VMCPU_ASSERT_EMT(pVCpu);
497	Assert(pDesc->enmType == DBGFREGVALTYPE_R80);
498
499	if (cpumR3RegIsFxSaveFormat(pVCpu))
500	{
501	unsigned iReg = (pVCpu->cpum.s.Guest.fpu.FSW >> 11) & 7;
502	iReg += pDesc->offRegister;
503	iReg &= 7;
504	pValue->r80 = pVCpu->cpum.s.Guest.fpu.aRegs[iReg].r80;
505	}
506	else
507	{
508	PCX86FPUSTATE pOldFpu = (PCX86FPUSTATE)&pVCpu->cpum.s.Guest.fpu;
509
510	unsigned iReg = (pOldFpu->FSW >> 11) & 7;
511	iReg += pDesc->offRegister;
512	iReg &= 7;
513
514	pValue->r80 = pOldFpu->regs[iReg].r80;
515	}
516
517	return VINF_SUCCESS;
518	}
519
520	/**
521	* @interface_method_impl{DBGFREGDESC, pfnGet}
522	*/
523	static DECLCALLBACK(int) cpumR3RegSet_stN(void *pvUser, PCDBGFREGDESC pDesc, PCDBGFREGVAL pValue, PCDBGFREGVAL pfMask)
524	{
525	return VERR_NOT_IMPLEMENTED;
526	}
527
528
529	/*
530	* Set up aliases.
531	*/
532	#define CPUMREGALIAS_STD(Name, psz32, psz16, psz8) \
533	static DBGFREGALIAS const g_aCpumRegAliases_##Name[] = \
534	{ \
535	{ psz32, DBGFREGVALTYPE_U32 }, \
536	{ psz16, DBGFREGVALTYPE_U16 }, \
537	{ psz8, DBGFREGVALTYPE_U8 }, \
538	{ NULL, DBGFREGVALTYPE_INVALID } \
539	}
540	CPUMREGALIAS_STD(rax, "eax", "ax", "al");
541	CPUMREGALIAS_STD(rcx, "ecx", "cx", "cl");
542	CPUMREGALIAS_STD(rdx, "edx", "dx", "dl");
543	CPUMREGALIAS_STD(rbx, "ebx", "bx", "bl");
544	CPUMREGALIAS_STD(rsp, "esp", "sp", NULL);
545	CPUMREGALIAS_STD(rbp, "ebp", "bp", NULL);
546	CPUMREGALIAS_STD(rsi, "esi", "si", "sil");
547	CPUMREGALIAS_STD(rdi, "edi", "di", "dil");
548	CPUMREGALIAS_STD(r8, "r8d", "r8w", "r8b");
549	CPUMREGALIAS_STD(r9, "r9d", "r9w", "r9b");
550	CPUMREGALIAS_STD(r10, "r10d", "r10w", "r10b");
551	CPUMREGALIAS_STD(r11, "r11d", "r11w", "r11b");
552	CPUMREGALIAS_STD(r12, "r12d", "r12w", "r12b");
553	CPUMREGALIAS_STD(r13, "r13d", "r13w", "r13b");
554	CPUMREGALIAS_STD(r14, "r14d", "r14w", "r14b");
555	CPUMREGALIAS_STD(r15, "r15d", "r15w", "r15b");
556	CPUMREGALIAS_STD(rip, "eip", "ip", NULL);
557	CPUMREGALIAS_STD(rflags, "eflags", "flags", NULL);
558	#undef CPUMREGALIAS_STD
559
560	static DBGFREGALIAS const g_aCpumRegAliases_fpuip[] =
561	{
562	{ "fpuip16", DBGFREGVALTYPE_U16 },
563	{ NULL, DBGFREGVALTYPE_INVALID }
564	};
565
566	static DBGFREGALIAS const g_aCpumRegAliases_fpudp[] =
567	{
568	{ "fpudp16", DBGFREGVALTYPE_U16 },
569	{ NULL, DBGFREGVALTYPE_INVALID }
570	};
571
572	static DBGFREGALIAS const g_aCpumRegAliases_cr0[] =
573	{
574	{ "msw", DBGFREGVALTYPE_U16 },
575	{ NULL, DBGFREGVALTYPE_INVALID }
576	};
577
578	/*
579	* Sub fields.
580	*/
581	/** Sub-fields for the (hidden) segment attribute register. */
582	static DBGFREGSUBFIELD const g_aCpumRegFields_seg[] =
583	{
584	DBGFREGSUBFIELD_RW("type", 0, 4, 0),
585	DBGFREGSUBFIELD_RW("s", 4, 1, 0),
586	DBGFREGSUBFIELD_RW("dpl", 5, 2, 0),
587	DBGFREGSUBFIELD_RW("p", 7, 1, 0),
588	DBGFREGSUBFIELD_RW("avl", 12, 1, 0),
589	DBGFREGSUBFIELD_RW("l", 13, 1, 0),
590	DBGFREGSUBFIELD_RW("d", 14, 1, 0),
591	DBGFREGSUBFIELD_RW("g", 15, 1, 0),
592	DBGFREGSUBFIELD_TERMINATOR()
593	};
594
595	/** Sub-fields for the flags register. */
596	static DBGFREGSUBFIELD const g_aCpumRegFields_rflags[] =
597	{
598	DBGFREGSUBFIELD_RW("cf", 0, 1, 0),
599	DBGFREGSUBFIELD_RW("pf", 2, 1, 0),
600	DBGFREGSUBFIELD_RW("af", 4, 1, 0),
601	DBGFREGSUBFIELD_RW("zf", 6, 1, 0),
602	DBGFREGSUBFIELD_RW("sf", 7, 1, 0),
603	DBGFREGSUBFIELD_RW("tf", 8, 1, 0),
604	DBGFREGSUBFIELD_RW("if", 9, 1, 0),
605	DBGFREGSUBFIELD_RW("df", 10, 1, 0),
606	DBGFREGSUBFIELD_RW("of", 11, 1, 0),
607	DBGFREGSUBFIELD_RW("iopl", 12, 2, 0),
608	DBGFREGSUBFIELD_RW("nt", 14, 1, 0),
609	DBGFREGSUBFIELD_RW("rf", 16, 1, 0),
610	DBGFREGSUBFIELD_RW("vm", 17, 1, 0),
611	DBGFREGSUBFIELD_RW("ac", 18, 1, 0),
612	DBGFREGSUBFIELD_RW("vif", 19, 1, 0),
613	DBGFREGSUBFIELD_RW("vip", 20, 1, 0),
614	DBGFREGSUBFIELD_RW("id", 21, 1, 0),
615	DBGFREGSUBFIELD_TERMINATOR()
616	};
617
618	/** Sub-fields for the FPU control word register. */
619	static DBGFREGSUBFIELD const g_aCpumRegFields_fcw[] =
620	{
621	DBGFREGSUBFIELD_RW("im", 1, 1, 0),
622	DBGFREGSUBFIELD_RW("dm", 2, 1, 0),
623	DBGFREGSUBFIELD_RW("zm", 3, 1, 0),
624	DBGFREGSUBFIELD_RW("om", 4, 1, 0),
625	DBGFREGSUBFIELD_RW("um", 5, 1, 0),
626	DBGFREGSUBFIELD_RW("pm", 6, 1, 0),
627	DBGFREGSUBFIELD_RW("pc", 8, 2, 0),
628	DBGFREGSUBFIELD_RW("rc", 10, 2, 0),
629	DBGFREGSUBFIELD_RW("x", 12, 1, 0),
630	DBGFREGSUBFIELD_TERMINATOR()
631	};
632
633	/** Sub-fields for the FPU status word register. */
634	static DBGFREGSUBFIELD const g_aCpumRegFields_fsw[] =
635	{
636	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
637	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
638	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
639	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
640	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
641	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
642	DBGFREGSUBFIELD_RW("se", 6, 1, 0),
643	DBGFREGSUBFIELD_RW("es", 7, 1, 0),
644	DBGFREGSUBFIELD_RW("c0", 8, 1, 0),
645	DBGFREGSUBFIELD_RW("c1", 9, 1, 0),
646	DBGFREGSUBFIELD_RW("c2", 10, 1, 0),
647	DBGFREGSUBFIELD_RW("top", 11, 3, 0),
648	DBGFREGSUBFIELD_RW("c3", 14, 1, 0),
649	DBGFREGSUBFIELD_RW("b", 15, 1, 0),
650	DBGFREGSUBFIELD_TERMINATOR()
651	};
652
653	/** Sub-fields for the FPU tag word register. */
654	static DBGFREGSUBFIELD const g_aCpumRegFields_ftw[] =
655	{
656	DBGFREGSUBFIELD_RW("tag0", 0, 2, 0),
657	DBGFREGSUBFIELD_RW("tag1", 2, 2, 0),
658	DBGFREGSUBFIELD_RW("tag2", 4, 2, 0),
659	DBGFREGSUBFIELD_RW("tag3", 6, 2, 0),
660	DBGFREGSUBFIELD_RW("tag4", 8, 2, 0),
661	DBGFREGSUBFIELD_RW("tag5", 10, 2, 0),
662	DBGFREGSUBFIELD_RW("tag6", 12, 2, 0),
663	DBGFREGSUBFIELD_RW("tag7", 14, 2, 0),
664	DBGFREGSUBFIELD_TERMINATOR()
665	};
666
667	/** Sub-fields for the Multimedia Extensions Control and Status Register. */
668	static DBGFREGSUBFIELD const g_aCpumRegFields_mxcsr[] =
669	{
670	DBGFREGSUBFIELD_RW("ie", 0, 1, 0),
671	DBGFREGSUBFIELD_RW("de", 1, 1, 0),
672	DBGFREGSUBFIELD_RW("ze", 2, 1, 0),
673	DBGFREGSUBFIELD_RW("oe", 3, 1, 0),
674	DBGFREGSUBFIELD_RW("ue", 4, 1, 0),
675	DBGFREGSUBFIELD_RW("pe", 5, 1, 0),
676	DBGFREGSUBFIELD_RW("daz", 6, 1, 0),
677	DBGFREGSUBFIELD_RW("im", 7, 1, 0),
678	DBGFREGSUBFIELD_RW("dm", 8, 1, 0),
679	DBGFREGSUBFIELD_RW("zm", 9, 1, 0),
680	DBGFREGSUBFIELD_RW("om", 10, 1, 0),
681	DBGFREGSUBFIELD_RW("um", 11, 1, 0),
682	DBGFREGSUBFIELD_RW("pm", 12, 1, 0),
683	DBGFREGSUBFIELD_RW("rc", 13, 2, 0),
684	DBGFREGSUBFIELD_RW("fz", 14, 1, 0),
685	DBGFREGSUBFIELD_TERMINATOR()
686	};
687
688	/** Sub-fields for the FPU tag word register. */
689	static DBGFREGSUBFIELD const g_aCpumRegFields_stN[] =
690	{
691	DBGFREGSUBFIELD_RW("man", 0, 64, 0),
692	DBGFREGSUBFIELD_RW("exp", 64, 15, 0),
693	DBGFREGSUBFIELD_RW("sig", 79, 1, 0),
694	DBGFREGSUBFIELD_TERMINATOR()
695	};
696
697	/** Sub-fields for the MMX registers. */
698	static DBGFREGSUBFIELD const g_aCpumRegFields_mmN[] =
699	{
700	DBGFREGSUBFIELD_RW("dw0", 0, 32, 0),
701	DBGFREGSUBFIELD_RW("dw1", 32, 32, 0),
702	DBGFREGSUBFIELD_RW("w0", 0, 16, 0),
703	DBGFREGSUBFIELD_RW("w1", 16, 16, 0),
704	DBGFREGSUBFIELD_RW("w2", 32, 16, 0),
705	DBGFREGSUBFIELD_RW("w3", 48, 16, 0),
706	DBGFREGSUBFIELD_RW("b0", 0, 8, 0),
707	DBGFREGSUBFIELD_RW("b1", 8, 8, 0),
708	DBGFREGSUBFIELD_RW("b2", 16, 8, 0),
709	DBGFREGSUBFIELD_RW("b3", 24, 8, 0),
710	DBGFREGSUBFIELD_RW("b4", 32, 8, 0),
711	DBGFREGSUBFIELD_RW("b5", 40, 8, 0),
712	DBGFREGSUBFIELD_RW("b6", 48, 8, 0),
713	DBGFREGSUBFIELD_RW("b7", 56, 8, 0),
714	DBGFREGSUBFIELD_TERMINATOR()
715	};
716
717	/** Sub-fields for the XMM registers. */
718	static DBGFREGSUBFIELD const g_aCpumRegFields_xmmN[] =
719	{
720	DBGFREGSUBFIELD_RW("r0", 0, 32, 0),
721	DBGFREGSUBFIELD_RW("r0.man", 0+ 0, 23, 0),
722	DBGFREGSUBFIELD_RW("r0.exp", 0+23, 8, 0),
723	DBGFREGSUBFIELD_RW("r0.sig", 0+31, 1, 0),
724	DBGFREGSUBFIELD_RW("r1", 32, 32, 0),
725	DBGFREGSUBFIELD_RW("r1.man", 32+ 0, 23, 0),
726	DBGFREGSUBFIELD_RW("r1.exp", 32+23, 8, 0),
727	DBGFREGSUBFIELD_RW("r1.sig", 32+31, 1, 0),
728	DBGFREGSUBFIELD_RW("r2", 64, 32, 0),
729	DBGFREGSUBFIELD_RW("r2.man", 64+ 0, 23, 0),
730	DBGFREGSUBFIELD_RW("r2.exp", 64+23, 8, 0),
731	DBGFREGSUBFIELD_RW("r2.sig", 64+31, 1, 0),
732	DBGFREGSUBFIELD_RW("r3", 96, 32, 0),
733	DBGFREGSUBFIELD_RW("r3.man", 96+ 0, 23, 0),
734	DBGFREGSUBFIELD_RW("r3.exp", 96+23, 8, 0),
735	DBGFREGSUBFIELD_RW("r3.sig", 96+31, 1, 0),
736	DBGFREGSUBFIELD_TERMINATOR()
737	};
738
739	/** Sub-fields for the CR0 register. */
740	static DBGFREGSUBFIELD const g_aCpumRegFields_cr0[] =
741	{
742	/** @todo */
743	DBGFREGSUBFIELD_TERMINATOR()
744	};
745
746	/** Sub-fields for the CR3 register. */
747	static DBGFREGSUBFIELD const g_aCpumRegFields_cr3[] =
748	{
749	/** @todo */
750	DBGFREGSUBFIELD_TERMINATOR()
751	};
752
753	/** Sub-fields for the CR4 register. */
754	static DBGFREGSUBFIELD const g_aCpumRegFields_cr4[] =
755	{
756	/** @todo */
757	DBGFREGSUBFIELD_TERMINATOR()
758	};
759
760	/** Sub-fields for the DR6 register. */
761	static DBGFREGSUBFIELD const g_aCpumRegFields_dr6[] =
762	{
763	/** @todo */
764	DBGFREGSUBFIELD_TERMINATOR()
765	};
766
767	/** Sub-fields for the DR7 register. */
768	static DBGFREGSUBFIELD const g_aCpumRegFields_dr7[] =
769	{
770	/** @todo */
771	DBGFREGSUBFIELD_TERMINATOR()
772	};
773
774	/** Sub-fields for the CR_PAT MSR. */
775	static DBGFREGSUBFIELD const g_aCpumRegFields_apic_base[] =
776	{
777	DBGFREGSUBFIELD_RW("bsp", 8, 1, 0),
778	DBGFREGSUBFIELD_RW("ge", 9, 1, 0),
779	DBGFREGSUBFIELD_RW("base", 12, 20, 12),
780	DBGFREGSUBFIELD_TERMINATOR()
781	};
782
783	/** Sub-fields for the CR_PAT MSR. */
784	static DBGFREGSUBFIELD const g_aCpumRegFields_cr_pat[] =
785	{
786	/** @todo */
787	DBGFREGSUBFIELD_TERMINATOR()
788	};
789
790	/** Sub-fields for the PERF_STATUS MSR. */
791	static DBGFREGSUBFIELD const g_aCpumRegFields_perf_status[] =
792	{
793	/** @todo */
794	DBGFREGSUBFIELD_TERMINATOR()
795	};
796
797	/** Sub-fields for the EFER MSR. */
798	static DBGFREGSUBFIELD const g_aCpumRegFields_efer[] =
799	{
800	/** @todo */
801	DBGFREGSUBFIELD_TERMINATOR()
802	};
803
804	/** Sub-fields for the STAR MSR. */
805	static DBGFREGSUBFIELD const g_aCpumRegFields_star[] =
806	{
807	/** @todo */
808	DBGFREGSUBFIELD_TERMINATOR()
809	};
810
811	/** Sub-fields for the CSTAR MSR. */
812	static DBGFREGSUBFIELD const g_aCpumRegFields_cstar[] =
813	{
814	/** @todo */
815	DBGFREGSUBFIELD_TERMINATOR()
816	};
817
818	/** Sub-fields for the LSTAR MSR. */
819	static DBGFREGSUBFIELD const g_aCpumRegFields_lstar[] =
820	{
821	/** @todo */
822	DBGFREGSUBFIELD_TERMINATOR()
823	};
824
825	/** Sub-fields for the SF_MASK MSR. */
826	static DBGFREGSUBFIELD const g_aCpumRegFields_sf_mask[] =
827	{
828	/** @todo */
829	DBGFREGSUBFIELD_TERMINATOR()
830	};
831
832
833
834	/**
835	* The register descriptors.
836	*/
837	static DBGFREGDESC const g_aCpumRegDescs[] =
838	{
839	#define CPUMREGDESC_RW_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
840	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
841	#define CPUMREGDESC_RO_AS(a_szName, a_RegSuff, a_TypeSuff, a_CpumCtxMemb, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
842	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, DBGFREG_FLAGS_READ_ONLY, RT_OFFSETOF(CPUMCTX, a_CpumCtxMemb), a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
843	#define CPUMREGDESC_EX_AS(a_szName, a_RegSuff, a_TypeSuff, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields) \
844	{ a_szName, DBGFREG_##a_RegSuff, DBGFREGVALTYPE_##a_TypeSuff, 0 /fFlags/, a_offRegister, a_pfnGet, a_pfnSet, a_paAliases, a_paSubFields }
845
846	#define CPUMREGDESC_REG(UName, LName) \
847	CPUMREGDESC_RW_AS(#LName, UName, U64, LName, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_##LName, NULL)
848	CPUMREGDESC_REG(RAX, rax),
849	CPUMREGDESC_REG(RCX, rcx),
850	CPUMREGDESC_REG(RDX, rdx),
851	CPUMREGDESC_REG(RBX, rbx),
852	CPUMREGDESC_REG(RSP, rsp),
853	CPUMREGDESC_REG(RBP, rbp),
854	CPUMREGDESC_REG(RSI, rsi),
855	CPUMREGDESC_REG(RDI, rdi),
856	CPUMREGDESC_REG(R8, r8),
857	CPUMREGDESC_REG(R9, r9),
858	CPUMREGDESC_REG(R10, r10),
859	CPUMREGDESC_REG(R11, r11),
860	CPUMREGDESC_REG(R12, r12),
861	CPUMREGDESC_REG(R13, r13),
862	CPUMREGDESC_REG(R14, r14),
863	CPUMREGDESC_REG(R15, r15),
864	#define CPUMREGDESC_SEG(UName, LName) \
865	CPUMREGDESC_RW_AS(#LName, UName, U16, LName, cpumR3RegGet_Generic, cpumR3RegSet_seg, NULL, NULL ), \
866	CPUMREGDESC_RW_AS(#LName "_attr", UName##_ATTR, U32, LName##Hid.Attr.u, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_seg), \
867	CPUMREGDESC_RW_AS(#LName "_base", UName##_BASE, U64, LName##Hid.u64Base, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ), \
868	CPUMREGDESC_RW_AS(#LName "_lim", UName##_LIMIT, U32, LName##Hid.u32Limit, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL )
869	CPUMREGDESC_SEG(CS, cs),
870	CPUMREGDESC_SEG(DS, ds),
871	CPUMREGDESC_SEG(ES, es),
872	CPUMREGDESC_SEG(FS, fs),
873	CPUMREGDESC_SEG(GS, gs),
874	CPUMREGDESC_SEG(SS, ss),
875	CPUMREGDESC_REG(RIP, rip),
876	CPUMREGDESC_RW_AS("rflags", RFLAGS, U64, rflags, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_rflags, g_aCpumRegFields_rflags ),
877	CPUMREGDESC_RW_AS("fcw", FCW, U16, fpu.FCW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fcw ),
878	CPUMREGDESC_RW_AS("fsw", FSW, U16, fpu.FSW, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_fsw ),
879	CPUMREGDESC_RO_AS("ftw", FTW, U16, fpu.FTW, cpumR3RegGet_ftw, cpumR3RegSet_ftw, NULL, g_aCpumRegFields_ftw ),
880	CPUMREGDESC_RW_AS("fop", FOP, U16, fpu.FOP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
881	CPUMREGDESC_RW_AS("fpuip", FPUIP, U32, fpu.FPUIP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpuip, NULL ),
882	CPUMREGDESC_RW_AS("fpucs", FPUCS, U16, fpu.CS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
883	CPUMREGDESC_RW_AS("fpudp", FPUDP, U32, fpu.FPUDP, cpumR3RegGet_Generic, cpumR3RegSet_Generic, g_aCpumRegAliases_fpudp, NULL ),
884	CPUMREGDESC_RW_AS("fpuds", FPUDS, U16, fpu.DS, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
885	CPUMREGDESC_RW_AS("mxcsr", MXCSR, U32, fpu.MXCSR, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
886	CPUMREGDESC_RW_AS("mxcsr_mask", MXCSR_MASK, U32, fpu.MXCSR_MASK, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mxcsr ),
887	#define CPUMREGDESC_ST(n) \
888	CPUMREGDESC_RW_AS("st" #n, ST##n, R80, fpu.aRegs[n], cpumR3RegGet_stN, cpumR3RegSet_stN, NULL, g_aCpumRegFields_stN )
889	CPUMREGDESC_ST(0),
890	CPUMREGDESC_ST(1),
891	CPUMREGDESC_ST(2),
892	CPUMREGDESC_ST(3),
893	CPUMREGDESC_ST(4),
894	CPUMREGDESC_ST(5),
895	CPUMREGDESC_ST(6),
896	CPUMREGDESC_ST(7),
897	#define CPUMREGDESC_MM(n) \
898	CPUMREGDESC_RW_AS("mm" #n, MM##n, U64, fpu.aRegs[n].mmx, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_mmN )
899	CPUMREGDESC_MM(0),
900	CPUMREGDESC_MM(1),
901	CPUMREGDESC_MM(2),
902	CPUMREGDESC_MM(3),
903	CPUMREGDESC_MM(4),
904	CPUMREGDESC_MM(5),
905	CPUMREGDESC_MM(6),
906	CPUMREGDESC_MM(7),
907	#define CPUMREGDESC_XMM(n) \
908	CPUMREGDESC_RW_AS("xmm" #n, XMM##n, U128, fpu.aXMM[n].xmm, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, g_aCpumRegFields_xmmN )
909	CPUMREGDESC_XMM(0),
910	CPUMREGDESC_XMM(1),
911	CPUMREGDESC_XMM(2),
912	CPUMREGDESC_XMM(3),
913	CPUMREGDESC_XMM(4),
914	CPUMREGDESC_XMM(5),
915	CPUMREGDESC_XMM(6),
916	CPUMREGDESC_XMM(7),
917	CPUMREGDESC_XMM(8),
918	CPUMREGDESC_XMM(9),
919	CPUMREGDESC_XMM(10),
920	CPUMREGDESC_XMM(11),
921	CPUMREGDESC_XMM(12),
922	CPUMREGDESC_XMM(13),
923	CPUMREGDESC_XMM(14),
924	CPUMREGDESC_XMM(15),
925	CPUMREGDESC_RW_AS("gdtr_base", GDTR_BASE, U64, gdtr.pGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
926	CPUMREGDESC_RW_AS("gdtr_limit", GDTR_LIMIT, U16, gdtr.cbGdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
927	CPUMREGDESC_RW_AS("idtr_base", IDTR_BASE, U64, idtr.pIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
928	CPUMREGDESC_RW_AS("idtr_limit", IDTR_LIMIT, U16, idtr.cbIdt, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
929	CPUMREGDESC_SEG(LDTR, ldtr),
930	CPUMREGDESC_SEG(TR, tr),
931	CPUMREGDESC_EX_AS("cr0", CR0, U32, 0, cpumR3RegGet_crX, cpumR3RegSet_crX, g_aCpumRegAliases_cr0, g_aCpumRegFields_cr0 ),
932	CPUMREGDESC_EX_AS("cr2", CR2, U64, 2, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ),
933	CPUMREGDESC_EX_AS("cr3", CR3, U64, 3, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr3 ),
934	CPUMREGDESC_EX_AS("cr4", CR4, U32, 4, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, g_aCpumRegFields_cr4 ),
935	CPUMREGDESC_EX_AS("cr8", CR8, U32, 8, cpumR3RegGet_crX, cpumR3RegSet_crX, NULL, NULL ),
936	CPUMREGDESC_EX_AS("dr0", DR0, U64, 0, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
937	CPUMREGDESC_EX_AS("dr1", DR1, U64, 1, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
938	CPUMREGDESC_EX_AS("dr2", DR2, U64, 2, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
939	CPUMREGDESC_EX_AS("dr3", DR3, U64, 3, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, NULL ),
940	CPUMREGDESC_EX_AS("dr6", DR6, U32, 6, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr6 ),
941	CPUMREGDESC_EX_AS("dr7", DR7, U32, 7, cpumR3RegGet_drX, cpumR3RegSet_drX, NULL, g_aCpumRegFields_dr7 ),
942	#define CPUMREGDESC_MSR(a_szName, UName, a_TypeSuff, a_paSubFields) \
943	CPUMREGDESC_EX_AS(a_szName, MSR_##UName, a_TypeSuff, MSR_##UName, cpumR3RegGet_msr, cpumR3RegSet_msr, NULL, a_paSubFields )
944	CPUMREGDESC_MSR("apic_base", IA32_APICBASE, U32, g_aCpumRegFields_apic_base ),
945	CPUMREGDESC_MSR("pat", IA32_CR_PAT, U64, g_aCpumRegFields_cr_pat ),
946	CPUMREGDESC_MSR("perf_status", IA32_PERF_STATUS, U64, g_aCpumRegFields_perf_status),
947	CPUMREGDESC_MSR("sysenter_cs", IA32_SYSENTER_CS, U16, NULL ),
948	CPUMREGDESC_MSR("sysenter_eip", IA32_SYSENTER_EIP, U32, NULL ),
949	CPUMREGDESC_MSR("sysenter_esp", IA32_SYSENTER_ESP, U32, NULL ),
950	CPUMREGDESC_MSR("tsc", IA32_TSC, U32, NULL ),
951	CPUMREGDESC_MSR("efer", K6_EFER, U32, g_aCpumRegFields_efer ),
952	CPUMREGDESC_MSR("star", K6_STAR, U64, g_aCpumRegFields_star ),
953	CPUMREGDESC_MSR("cstar", K8_CSTAR, U64, g_aCpumRegFields_cstar ),
954	CPUMREGDESC_MSR("msr_fs_base", K8_FS_BASE, U64, NULL ),
955	CPUMREGDESC_MSR("msr_gs_base", K8_GS_BASE, U64, NULL ),
956	CPUMREGDESC_MSR("krnl_gs_base", K8_KERNEL_GS_BASE, U64, NULL ),
957	CPUMREGDESC_MSR("lstar", K8_LSTAR, U64, g_aCpumRegFields_lstar ),
958	CPUMREGDESC_MSR("sf_mask", K8_SF_MASK, U64, NULL ),
959	CPUMREGDESC_MSR("tsc_aux", K8_TSC_AUX, U64, NULL ),
960	CPUMREGDESC_EX_AS("ah", AH, U8, RT_OFFSETOF(CPUMCTX, rax) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
961	CPUMREGDESC_EX_AS("ch", CH, U8, RT_OFFSETOF(CPUMCTX, rcx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
962	CPUMREGDESC_EX_AS("dh", DH, U8, RT_OFFSETOF(CPUMCTX, rdx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
963	CPUMREGDESC_EX_AS("bh", BH, U8, RT_OFFSETOF(CPUMCTX, rbx) + 1, cpumR3RegGet_Generic, cpumR3RegSet_Generic, NULL, NULL ),
964	CPUMREGDESC_RW_AS("gdtr", GDTR, DTR, gdtr, cpumR3RegGet_gdtr, cpumR3RegSet_gdtr, NULL, NULL ),
965	CPUMREGDESC_RW_AS("idtr", IDTR, DTR, idtr, cpumR3RegGet_idtr, cpumR3RegSet_idtr, NULL, NULL ),
966	DBGFREGDESC_TERMINATOR()
967	#undef CPUMREGDESC_REG
968	#undef CPUMREGDESC_SEG
969	#undef CPUMREGDESC_ST
970	#undef CPUMREGDESC_MM
971	#undef CPUMREGDESC_XMM
972	#undef CPUMREGDESC_MSR
973	};
974
975
976	/**
977	* Initializes the debugger related sides of the CPUM component.
978	*
979	* Called by CPUMR3Init.
980	*
981	* @returns VBox status code.
982	* @param pVM The VM handle.
983	*/
984	int cpumR3DbgInit(PVM pVM)
985	{
986	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
987	{
988	int rc = DBGFR3RegRegisterCpu(pVM, &pVM->aCpus[iCpu], g_aCpumRegDescs);
989	AssertLogRelRCReturn(rc, rc);
990	}
991
992	return VINF_SUCCESS;
993	}
994

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMDbg.cpp@ 35572

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